src/mesa/drivers/dri/i965/brw_ff_gs_emit.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #include "main/macros.h"
  34 #include "main/enums.h"
  35
  36 #include "program/program.h"
  37 #include "intel_batchbuffer.h"
  38
  39 #include "brw_defines.h"
  40 #include "brw_context.h"
  41 #include "brw_eu.h"
  42 #include "brw_ff_gs.h"
  43
  44 /**
  45  * Allocate registers for GS.
  46  *
  47  * If sol_program is true, then:
  48  *
  49  * - The thread will be spawned with the "SVBI Payload Enable" bit set, so GRF
  50  *   1 needs to be set aside to hold the streamed vertex buffer indices.
  51  *
  52  * - The thread will need to use the destination_indices register.
  53  */
  54 static void brw_ff_gs_alloc_regs(struct brw_ff_gs_compile *c,
  55                                  GLuint nr_verts,
  56                                  bool sol_program)
  57 {
  58    GLuint i = 0,j;
  59
  60    /* Register usage is static, precompute here:
  61     */
  62    c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
  63
  64    /* Streamed vertex buffer indices */
  65    if (sol_program)
  66       c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  67
  68    /* Payload vertices plus space for more generated vertices:
  69     */
  70    for (j = 0; j < nr_verts; j++) {
  71       c->reg.vertex[j] = brw_vec4_grf(i, 0);
  72       i += c->nr_regs;
  73    }
  74
  75    c->reg.header = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  76    c->reg.temp = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  77
  78    if (sol_program) {
  79       c->reg.destination_indices =
  80          retype(brw_vec4_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  81    }
  82
  83    c->prog_data.urb_read_length = c->nr_regs;
  84    c->prog_data.total_grf = i;
  85 }
  86
  87
  88 /**
  89  * Set up the initial value of c->reg.header register based on c->reg.R0.
  90  *
  91  * The following information is passed to the GS thread in R0, and needs to be
  92  * included in the first URB_WRITE or FF_SYNC message sent by the GS:
  93  *
  94  * - DWORD 0 [31:0] handle info (Gen4 only)
  95  * - DWORD 5 [7:0] FFTID
  96  * - DWORD 6 [31:0] Debug info
  97  * - DWORD 7 [31:0] Debug info
  98  *
  99  * This function sets up the above data by copying by copying the contents of
 100  * R0 to the header register.
 101  */
 102 static void brw_ff_gs_initialize_header(struct brw_ff_gs_compile *c)
 103 {
 104    struct brw_codegen *p = &c->func;
 105    brw_MOV(p, c->reg.header, c->reg.R0);
 106 }
 107
 108 /**
 109  * Overwrite DWORD 2 of c->reg.header with the given immediate unsigned value.
 110  *
 111  * In URB_WRITE messages, DWORD 2 contains the fields PrimType, PrimStart,
 112  * PrimEnd, Increment CL_INVOCATIONS, and SONumPrimsWritten, many of which we
 113  * need to be able to update on a per-vertex basis.
 114  */
 115 static void brw_ff_gs_overwrite_header_dw2(struct brw_ff_gs_compile *c,
 116                                            unsigned dw2)
 117 {
 118    struct brw_codegen *p = &c->func;
 119    brw_MOV(p, get_element_ud(c->reg.header, 2), brw_imm_ud(dw2));
 120 }
 121
 122 /**
 123  * Overwrite DWORD 2 of c->reg.header with the primitive type from c->reg.R0.
 124  *
 125  * When the thread is spawned, GRF 0 contains the primitive type in bits 4:0
 126  * of DWORD 2.  URB_WRITE messages need the primitive type in bits 6:2 of
 127  * DWORD 2.  So this function extracts the primitive type field, bitshifts it
 128  * appropriately, and stores it in c->reg.header.
 129  */
 130 static void brw_ff_gs_overwrite_header_dw2_from_r0(struct brw_ff_gs_compile *c)
 131 {
 132    struct brw_codegen *p = &c->func;
 133    brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2),
 134            brw_imm_ud(0x1f));
 135    brw_SHL(p, get_element_ud(c->reg.header, 2),
 136            get_element_ud(c->reg.header, 2), brw_imm_ud(2));
 137 }
 138
 139 /**
 140  * Apply an additive offset to DWORD 2 of c->reg.header.
 141  *
 142  * This is used to set/unset the "PrimStart" and "PrimEnd" flags appropriately
 143  * for each vertex.
 144  */
 145 static void brw_ff_gs_offset_header_dw2(struct brw_ff_gs_compile *c,
 146                                         int offset)
 147 {
 148    struct brw_codegen *p = &c->func;
 149    brw_ADD(p, get_element_d(c->reg.header, 2), get_element_d(c->reg.header, 2),
 150            brw_imm_d(offset));
 151 }
 152
 153
 154 /**
 155  * Emit a vertex using the URB_WRITE message.  Use the contents of
 156  * c->reg.header for the message header, and the registers starting at \c vert
 157  * for the vertex data.
 158  *
 159  * If \c last is true, then this is the last vertex, so no further URB space
 160  * should be allocated, and this message should end the thread.
 161  *
 162  * If \c last is false, then a new URB entry will be allocated, and its handle
 163  * will be stored in DWORD 0 of c->reg.header for use in the next URB_WRITE
 164  * message.
 165  */
 166 static void brw_ff_gs_emit_vue(struct brw_ff_gs_compile *c,
 167                                struct brw_reg vert,
 168                                bool last)
 169 {
 170    struct brw_codegen *p = &c->func;
 171    int write_offset = 0;
 172    bool complete = false;
 173
 174    do {
 175       /* We can't write more than 14 registers at a time to the URB */
 176       int write_len = MIN2(c->nr_regs - write_offset, 14);
 177       if (write_len == c->nr_regs - write_offset)
 178          complete = true;
 179
 180       /* Copy the vertex from vertn into m1..mN+1:
 181        */
 182       brw_copy8(p, brw_message_reg(1), offset(vert, write_offset), write_len);
 183
 184       /* Send the vertex data to the URB.  If this is the last write for this
 185        * vertex, then we mark it as complete, and either end the thread or
 186        * allocate another vertex URB entry (depending whether this is the last
 187        * vertex).
 188        */
 189       enum brw_urb_write_flags flags;
 190       if (!complete)
 191          flags = BRW_URB_WRITE_NO_FLAGS;
 192       else if (last)
 193          flags = BRW_URB_WRITE_EOT_COMPLETE;
 194       else
 195          flags = BRW_URB_WRITE_ALLOCATE_COMPLETE;
 196       brw_urb_WRITE(p,
 197                     (flags & BRW_URB_WRITE_ALLOCATE) ? c->reg.temp
 198                     : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 199                     0,
 200                     c->reg.header,
 201                     flags,
 202                     write_len + 1, /* msg length */
 203                     (flags & BRW_URB_WRITE_ALLOCATE) ? 1
 204                     : 0, /* response length */
 205                     write_offset,  /* urb offset */
 206                     BRW_URB_SWIZZLE_NONE);
 207       write_offset += write_len;
 208    } while (!complete);
 209
 210    if (!last) {
 211       brw_MOV(p, get_element_ud(c->reg.header, 0),
 212               get_element_ud(c->reg.temp, 0));
 213    }
 214 }
 215
 216 /**
 217  * Send an FF_SYNC message to ensure that all previously spawned GS threads
 218  * have finished sending primitives down the pipeline, and to allocate a URB
 219  * entry for the first output vertex.  Only needed on Ironlake+.
 220  *
 221  * This function modifies c->reg.header: in DWORD 1, it stores num_prim (which
 222  * is needed by the FF_SYNC message), and in DWORD 0, it stores the handle to
 223  * the allocated URB entry (which will be needed by the URB_WRITE meesage that
 224  * follows).
 225  */
 226 static void brw_ff_gs_ff_sync(struct brw_ff_gs_compile *c, int num_prim)
 227 {
 228    struct brw_codegen *p = &c->func;
 229
 230    brw_MOV(p, get_element_ud(c->reg.header, 1), brw_imm_ud(num_prim));
 231    brw_ff_sync(p,
 232                c->reg.temp,
 233                0,
 234                c->reg.header,
 235                1, /* allocate */
 236                1, /* response length */
 237                0 /* eot */);
 238    brw_MOV(p, get_element_ud(c->reg.header, 0),
 239            get_element_ud(c->reg.temp, 0));
 240 }
 241
 242
 243 void
 244 brw_ff_gs_quads(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key)
 245 {
 246    brw_ff_gs_alloc_regs(c, 4, false);
 247    brw_ff_gs_initialize_header(c);
 248    /* Use polygons for correct edgeflag behaviour. Note that vertex 3
 249     * is the PV for quads, but vertex 0 for polygons:
 250     */
 251    if (c->func.devinfo->gen == 5)
 252       brw_ff_gs_ff_sync(c, 1);
 253    brw_ff_gs_overwrite_header_dw2(
 254       c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 255           | URB_WRITE_PRIM_START));
 256    if (key->pv_first) {
 257       brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
 258       brw_ff_gs_overwrite_header_dw2(
 259          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 260       brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
 261       brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
 262       brw_ff_gs_overwrite_header_dw2(
 263          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 264              | URB_WRITE_PRIM_END));
 265       brw_ff_gs_emit_vue(c, c->reg.vertex[3], 1);
 266    }
 267    else {
 268       brw_ff_gs_emit_vue(c, c->reg.vertex[3], 0);
 269       brw_ff_gs_overwrite_header_dw2(
 270          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 271       brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
 272       brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
 273       brw_ff_gs_overwrite_header_dw2(
 274          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 275              | URB_WRITE_PRIM_END));
 276       brw_ff_gs_emit_vue(c, c->reg.vertex[2], 1);
 277    }
 278 }
 279
 280 void
 281 brw_ff_gs_quad_strip(struct brw_ff_gs_compile *c,
 282                      struct brw_ff_gs_prog_key *key)
 283 {
 284    brw_ff_gs_alloc_regs(c, 4, false);
 285    brw_ff_gs_initialize_header(c);
 286
 287    if (c->func.devinfo->gen == 5)
 288       brw_ff_gs_ff_sync(c, 1);
 289    brw_ff_gs_overwrite_header_dw2(
 290       c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 291           | URB_WRITE_PRIM_START));
 292    if (key->pv_first) {
 293       brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
 294       brw_ff_gs_overwrite_header_dw2(
 295          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 296       brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
 297       brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
 298       brw_ff_gs_overwrite_header_dw2(
 299          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 300              | URB_WRITE_PRIM_END));
 301       brw_ff_gs_emit_vue(c, c->reg.vertex[3], 1);
 302    }
 303    else {
 304       brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
 305       brw_ff_gs_overwrite_header_dw2(
 306          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 307       brw_ff_gs_emit_vue(c, c->reg.vertex[3], 0);
 308       brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
 309       brw_ff_gs_overwrite_header_dw2(
 310          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 311              | URB_WRITE_PRIM_END));
 312       brw_ff_gs_emit_vue(c, c->reg.vertex[1], 1);
 313    }
 314 }
 315
 316 void brw_ff_gs_lines(struct brw_ff_gs_compile *c)
 317 {
 318    brw_ff_gs_alloc_regs(c, 2, false);
 319    brw_ff_gs_initialize_header(c);
 320
 321    if (c->func.devinfo->gen == 5)
 322       brw_ff_gs_ff_sync(c, 1);
 323    brw_ff_gs_overwrite_header_dw2(
 324       c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
 325           | URB_WRITE_PRIM_START));
 326    brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
 327    brw_ff_gs_overwrite_header_dw2(
 328       c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
 329           | URB_WRITE_PRIM_END));
 330    brw_ff_gs_emit_vue(c, c->reg.vertex[1], 1);
 331 }
 332
 333 /**
 334  * Generate the geometry shader program used on Gen6 to perform stream output
 335  * (transform feedback).
 336  */
 337 void
 338 gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key,
 339                  unsigned num_verts, bool check_edge_flags)
 340 {
 341    struct brw_codegen *p = &c->func;
 342    brw_inst *inst;
 343    c->prog_data.svbi_postincrement_value = num_verts;
 344
 345    brw_ff_gs_alloc_regs(c, num_verts, true);
 346    brw_ff_gs_initialize_header(c);
 347
 348    if (key->num_transform_feedback_bindings > 0) {
 349       unsigned vertex, binding;
 350       struct brw_reg destination_indices_uw =
 351          vec8(retype(c->reg.destination_indices, BRW_REGISTER_TYPE_UW));
 352
 353       /* Note: since we use the binding table to keep track of buffer offsets
 354        * and stride, the GS doesn't need to keep track of a separate pointer
 355        * into each buffer; it uses a single pointer which increments by 1 for
 356        * each vertex.  So we use SVBI0 for this pointer, regardless of whether
 357        * transform feedback is in interleaved or separate attribs mode.
 358        *
 359        * Make sure that the buffers have enough room for all the vertices.
 360        */
 361       brw_ADD(p, get_element_ud(c->reg.temp, 0),
 362                  get_element_ud(c->reg.SVBI, 0), brw_imm_ud(num_verts));
 363       brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE,
 364                  get_element_ud(c->reg.temp, 0),
 365                  get_element_ud(c->reg.SVBI, 4));
 366       brw_IF(p, BRW_EXECUTE_1);
 367
 368       /* Compute the destination indices to write to.  Usually we use SVBI[0]
 369        * + (0, 1, 2).  However, for odd-numbered triangles in tristrips, the
 370        * vertices come down the pipeline in reversed winding order, so we need
 371        * to flip the order when writing to the transform feedback buffer.  To
 372        * ensure that flatshading accuracy is preserved, we need to write them
 373        * in order SVBI[0] + (0, 2, 1) if we're using the first provoking
 374        * vertex convention, and in order SVBI[0] + (1, 0, 2) if we're using
 375        * the last provoking vertex convention.
 376        *
 377        * Note: since brw_imm_v can only be used in instructions in
 378        * packed-word execution mode, and SVBI is a double-word, we need to
 379        * first move the appropriate immediate constant ((0, 1, 2), (0, 2, 1),
 380        * or (1, 0, 2)) to the destination_indices register, and then add SVBI
 381        * using a separate instruction.  Also, since the immediate constant is
 382        * expressed as packed words, and we need to load double-words into
 383        * destination_indices, we need to intersperse zeros to fill the upper
 384        * halves of each double-word.
 385        */
 386       brw_MOV(p, destination_indices_uw,
 387               brw_imm_v(0x00020100)); /* (0, 1, 2) */
 388       if (num_verts == 3) {
 389          /* Get primitive type into temp register. */
 390          brw_AND(p, get_element_ud(c->reg.temp, 0),
 391                  get_element_ud(c->reg.R0, 2), brw_imm_ud(0x1f));
 392
 393          /* Test if primitive type is TRISTRIP_REVERSE.  We need to do this as
 394           * an 8-wide comparison so that the conditional MOV that follows
 395           * moves all 8 words correctly.
 396           */
 397          brw_CMP(p, vec8(brw_null_reg()), BRW_CONDITIONAL_EQ,
 398                  get_element_ud(c->reg.temp, 0),
 399                  brw_imm_ud(_3DPRIM_TRISTRIP_REVERSE));
 400
 401          /* If so, then overwrite destination_indices_uw with the appropriate
 402           * reordering.
 403           */
 404          inst = brw_MOV(p, destination_indices_uw,
 405                         brw_imm_v(key->pv_first ? 0x00010200    /* (0, 2, 1) */
 406                                                 : 0x00020001)); /* (1, 0, 2) */
 407          brw_inst_set_pred_control(p->devinfo, inst, BRW_PREDICATE_NORMAL);
 408       }
 409       brw_ADD(p, c->reg.destination_indices,
 410               c->reg.destination_indices, get_element_ud(c->reg.SVBI, 0));
 411
 412       /* For each vertex, generate code to output each varying using the
 413        * appropriate binding table entry.
 414        */
 415       for (vertex = 0; vertex < num_verts; ++vertex) {
 416          /* Set up the correct destination index for this vertex */
 417          brw_MOV(p, get_element_ud(c->reg.header, 5),
 418                  get_element_ud(c->reg.destination_indices, vertex));
 419
 420          for (binding = 0; binding < key->num_transform_feedback_bindings;
 421               ++binding) {
 422             unsigned char varying =
 423                key->transform_feedback_bindings[binding];
 424             unsigned char slot = c->vue_map.varying_to_slot[varying];
 425             /* From the Sandybridge PRM, Volume 2, Part 1, Section 4.5.1:
 426              *
 427              *   "Prior to End of Thread with a URB_WRITE, the kernel must
 428              *   ensure that all writes are complete by sending the final
 429              *   write as a committed write."
 430              */
 431             bool final_write =
 432                binding == key->num_transform_feedback_bindings - 1 &&
 433                vertex == num_verts - 1;
 434             struct brw_reg vertex_slot = c->reg.vertex[vertex];
 435             vertex_slot.nr += slot / 2;
 436             vertex_slot.subnr = (slot % 2) * 16;
 437             /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w. */
 438             vertex_slot.swizzle = varying == VARYING_SLOT_PSIZ
 439                ? BRW_SWIZZLE_WWWW : key->transform_feedback_swizzles[binding];
 440             brw_set_default_access_mode(p, BRW_ALIGN_16);
 441             brw_MOV(p, stride(c->reg.header, 4, 4, 1),
 442                     retype(vertex_slot, BRW_REGISTER_TYPE_UD));
 443             brw_set_default_access_mode(p, BRW_ALIGN_1);
 444             brw_svb_write(p,
 445                           final_write ? c->reg.temp : brw_null_reg(), /* dest */
 446                           1, /* msg_reg_nr */
 447                           c->reg.header, /* src0 */
 448                           SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
 449                           final_write); /* send_commit_msg */
 450          }
 451       }
 452       brw_ENDIF(p);
 453
 454       /* Now, reinitialize the header register from R0 to restore the parts of
 455        * the register that we overwrote while streaming out transform feedback
 456        * data.
 457        */
 458       brw_ff_gs_initialize_header(c);
 459
 460       /* Finally, wait for the write commit to occur so that we can proceed to
 461        * other things safely.
 462        *
 463        * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
 464        *
 465        *   The write commit does not modify the destination register, but
 466        *   merely clears the dependency associated with the destination
 467        *   register. Thus, a simple “mov” instruction using the register as a
 468        *   source is sufficient to wait for the write commit to occur.
 469        */
 470       brw_MOV(p, c->reg.temp, c->reg.temp);
 471    }
 472
 473    brw_ff_gs_ff_sync(c, 1);
 474
 475    brw_ff_gs_overwrite_header_dw2_from_r0(c);
 476    switch (num_verts) {
 477    case 1:
 478       brw_ff_gs_offset_header_dw2(c,
 479                                   URB_WRITE_PRIM_START | URB_WRITE_PRIM_END);
 480       brw_ff_gs_emit_vue(c, c->reg.vertex[0], true);
 481       break;
 482    case 2:
 483       brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
 484       brw_ff_gs_emit_vue(c, c->reg.vertex[0], false);
 485       brw_ff_gs_offset_header_dw2(c,
 486                                   URB_WRITE_PRIM_END - URB_WRITE_PRIM_START);
 487       brw_ff_gs_emit_vue(c, c->reg.vertex[1], true);
 488       break;
 489    case 3:
 490       if (check_edge_flags) {
 491          /* Only emit vertices 0 and 1 if this is the first triangle of the
 492           * polygon.  Otherwise they are redundant.
 493           */
 494          brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 495                  get_element_ud(c->reg.R0, 2),
 496                  brw_imm_ud(BRW_GS_EDGE_INDICATOR_0));
 497          brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
 498          brw_IF(p, BRW_EXECUTE_1);
 499       }
 500       brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
 501       brw_ff_gs_emit_vue(c, c->reg.vertex[0], false);
 502       brw_ff_gs_offset_header_dw2(c, -URB_WRITE_PRIM_START);
 503       brw_ff_gs_emit_vue(c, c->reg.vertex[1], false);
 504       if (check_edge_flags) {
 505          brw_ENDIF(p);
 506          /* Only emit vertex 2 in PRIM_END mode if this is the last triangle
 507           * of the polygon.  Otherwise leave the primitive incomplete because
 508           * there are more polygon vertices coming.
 509           */
 510          brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 511                  get_element_ud(c->reg.R0, 2),
 512                  brw_imm_ud(BRW_GS_EDGE_INDICATOR_1));
 513          brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
 514          brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
 515       }
 516       brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_END);
 517       brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
 518       brw_ff_gs_emit_vue(c, c->reg.vertex[2], true);
 519       break;
 520    }
 521 }