2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "main/glheader.h"
34 #include "main/macros.h"
35 #include "main/enums.h"
37 #include "program/program.h"
38 #include "intel_batchbuffer.h"
40 #include "brw_defines.h"
41 #include "brw_context.h"
43 #include "brw_ff_gs.h"
46 * Allocate registers for GS.
48 * If sol_program is true, then:
50 * - The thread will be spawned with the "SVBI Payload Enable" bit set, so GRF
51 * 1 needs to be set aside to hold the streamed vertex buffer indices.
53 * - The thread will need to use the destination_indices register.
55 static void brw_ff_gs_alloc_regs(struct brw_ff_gs_compile
*c
,
61 /* Register usage is static, precompute here:
63 c
->reg
.R0
= retype(brw_vec8_grf(i
, 0), BRW_REGISTER_TYPE_UD
); i
++;
65 /* Streamed vertex buffer indices */
67 c
->reg
.SVBI
= retype(brw_vec8_grf(i
++, 0), BRW_REGISTER_TYPE_UD
);
69 /* Payload vertices plus space for more generated vertices:
71 for (j
= 0; j
< nr_verts
; j
++) {
72 c
->reg
.vertex
[j
] = brw_vec4_grf(i
, 0);
76 c
->reg
.header
= retype(brw_vec8_grf(i
++, 0), BRW_REGISTER_TYPE_UD
);
77 c
->reg
.temp
= retype(brw_vec8_grf(i
++, 0), BRW_REGISTER_TYPE_UD
);
80 c
->reg
.destination_indices
=
81 retype(brw_vec4_grf(i
++, 0), BRW_REGISTER_TYPE_UD
);
84 c
->prog_data
.urb_read_length
= c
->nr_regs
;
85 c
->prog_data
.total_grf
= i
;
90 * Set up the initial value of c->reg.header register based on c->reg.R0.
92 * The following information is passed to the GS thread in R0, and needs to be
93 * included in the first URB_WRITE or FF_SYNC message sent by the GS:
95 * - DWORD 0 [31:0] handle info (Gen4 only)
96 * - DWORD 5 [7:0] FFTID
97 * - DWORD 6 [31:0] Debug info
98 * - DWORD 7 [31:0] Debug info
100 * This function sets up the above data by copying by copying the contents of
101 * R0 to the header register.
103 static void brw_ff_gs_initialize_header(struct brw_ff_gs_compile
*c
)
105 struct brw_compile
*p
= &c
->func
;
106 brw_MOV(p
, c
->reg
.header
, c
->reg
.R0
);
110 * Overwrite DWORD 2 of c->reg.header with the given immediate unsigned value.
112 * In URB_WRITE messages, DWORD 2 contains the fields PrimType, PrimStart,
113 * PrimEnd, Increment CL_INVOCATIONS, and SONumPrimsWritten, many of which we
114 * need to be able to update on a per-vertex basis.
116 static void brw_ff_gs_overwrite_header_dw2(struct brw_ff_gs_compile
*c
,
119 struct brw_compile
*p
= &c
->func
;
120 brw_MOV(p
, get_element_ud(c
->reg
.header
, 2), brw_imm_ud(dw2
));
124 * Overwrite DWORD 2 of c->reg.header with the primitive type from c->reg.R0.
126 * When the thread is spawned, GRF 0 contains the primitive type in bits 4:0
127 * of DWORD 2. URB_WRITE messages need the primitive type in bits 6:2 of
128 * DWORD 2. So this function extracts the primitive type field, bitshifts it
129 * appropriately, and stores it in c->reg.header.
131 static void brw_ff_gs_overwrite_header_dw2_from_r0(struct brw_ff_gs_compile
*c
)
133 struct brw_compile
*p
= &c
->func
;
134 brw_AND(p
, get_element_ud(c
->reg
.header
, 2), get_element_ud(c
->reg
.R0
, 2),
136 brw_SHL(p
, get_element_ud(c
->reg
.header
, 2),
137 get_element_ud(c
->reg
.header
, 2), brw_imm_ud(2));
141 * Apply an additive offset to DWORD 2 of c->reg.header.
143 * This is used to set/unset the "PrimStart" and "PrimEnd" flags appropriately
146 static void brw_ff_gs_offset_header_dw2(struct brw_ff_gs_compile
*c
,
149 struct brw_compile
*p
= &c
->func
;
150 brw_ADD(p
, get_element_d(c
->reg
.header
, 2), get_element_d(c
->reg
.header
, 2),
156 * Emit a vertex using the URB_WRITE message. Use the contents of
157 * c->reg.header for the message header, and the registers starting at \c vert
158 * for the vertex data.
160 * If \c last is true, then this is the last vertex, so no further URB space
161 * should be allocated, and this message should end the thread.
163 * If \c last is false, then a new URB entry will be allocated, and its handle
164 * will be stored in DWORD 0 of c->reg.header for use in the next URB_WRITE
167 static void brw_ff_gs_emit_vue(struct brw_ff_gs_compile
*c
,
171 struct brw_compile
*p
= &c
->func
;
172 int write_offset
= 0;
173 bool complete
= false;
176 /* We can't write more than 14 registers at a time to the URB */
177 int write_len
= MIN2(c
->nr_regs
- write_offset
, 14);
178 if (write_len
== c
->nr_regs
- write_offset
)
181 /* Copy the vertex from vertn into m1..mN+1:
183 brw_copy8(p
, brw_message_reg(1), offset(vert
, write_offset
), write_len
);
185 /* Send the vertex data to the URB. If this is the last write for this
186 * vertex, then we mark it as complete, and either end the thread or
187 * allocate another vertex URB entry (depending whether this is the last
190 enum brw_urb_write_flags flags
;
192 flags
= BRW_URB_WRITE_NO_FLAGS
;
194 flags
= BRW_URB_WRITE_EOT_COMPLETE
;
196 flags
= BRW_URB_WRITE_ALLOCATE_COMPLETE
;
198 (flags
& BRW_URB_WRITE_ALLOCATE
) ? c
->reg
.temp
199 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
203 write_len
+ 1, /* msg length */
204 (flags
& BRW_URB_WRITE_ALLOCATE
) ? 1
205 : 0, /* response length */
206 write_offset
, /* urb offset */
207 BRW_URB_SWIZZLE_NONE
);
208 write_offset
+= write_len
;
212 brw_MOV(p
, get_element_ud(c
->reg
.header
, 0),
213 get_element_ud(c
->reg
.temp
, 0));
218 * Send an FF_SYNC message to ensure that all previously spawned GS threads
219 * have finished sending primitives down the pipeline, and to allocate a URB
220 * entry for the first output vertex. Only needed on Ironlake+.
222 * This function modifies c->reg.header: in DWORD 1, it stores num_prim (which
223 * is needed by the FF_SYNC message), and in DWORD 0, it stores the handle to
224 * the allocated URB entry (which will be needed by the URB_WRITE meesage that
227 static void brw_ff_gs_ff_sync(struct brw_ff_gs_compile
*c
, int num_prim
)
229 struct brw_compile
*p
= &c
->func
;
231 brw_MOV(p
, get_element_ud(c
->reg
.header
, 1), brw_imm_ud(num_prim
));
237 1, /* response length */
239 brw_MOV(p
, get_element_ud(c
->reg
.header
, 0),
240 get_element_ud(c
->reg
.temp
, 0));
245 brw_ff_gs_quads(struct brw_ff_gs_compile
*c
, struct brw_ff_gs_prog_key
*key
)
247 brw_ff_gs_alloc_regs(c
, 4, false);
248 brw_ff_gs_initialize_header(c
);
249 /* Use polygons for correct edgeflag behaviour. Note that vertex 3
250 * is the PV for quads, but vertex 0 for polygons:
252 if (c
->func
.devinfo
->gen
== 5)
253 brw_ff_gs_ff_sync(c
, 1);
254 brw_ff_gs_overwrite_header_dw2(
255 c
, ((_3DPRIM_POLYGON
<< URB_WRITE_PRIM_TYPE_SHIFT
)
256 | URB_WRITE_PRIM_START
));
258 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[0], 0);
259 brw_ff_gs_overwrite_header_dw2(
260 c
, _3DPRIM_POLYGON
<< URB_WRITE_PRIM_TYPE_SHIFT
);
261 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[1], 0);
262 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[2], 0);
263 brw_ff_gs_overwrite_header_dw2(
264 c
, ((_3DPRIM_POLYGON
<< URB_WRITE_PRIM_TYPE_SHIFT
)
265 | URB_WRITE_PRIM_END
));
266 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[3], 1);
269 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[3], 0);
270 brw_ff_gs_overwrite_header_dw2(
271 c
, _3DPRIM_POLYGON
<< URB_WRITE_PRIM_TYPE_SHIFT
);
272 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[0], 0);
273 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[1], 0);
274 brw_ff_gs_overwrite_header_dw2(
275 c
, ((_3DPRIM_POLYGON
<< URB_WRITE_PRIM_TYPE_SHIFT
)
276 | URB_WRITE_PRIM_END
));
277 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[2], 1);
282 brw_ff_gs_quad_strip(struct brw_ff_gs_compile
*c
,
283 struct brw_ff_gs_prog_key
*key
)
285 brw_ff_gs_alloc_regs(c
, 4, false);
286 brw_ff_gs_initialize_header(c
);
288 if (c
->func
.devinfo
->gen
== 5)
289 brw_ff_gs_ff_sync(c
, 1);
290 brw_ff_gs_overwrite_header_dw2(
291 c
, ((_3DPRIM_POLYGON
<< URB_WRITE_PRIM_TYPE_SHIFT
)
292 | URB_WRITE_PRIM_START
));
294 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[0], 0);
295 brw_ff_gs_overwrite_header_dw2(
296 c
, _3DPRIM_POLYGON
<< URB_WRITE_PRIM_TYPE_SHIFT
);
297 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[1], 0);
298 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[2], 0);
299 brw_ff_gs_overwrite_header_dw2(
300 c
, ((_3DPRIM_POLYGON
<< URB_WRITE_PRIM_TYPE_SHIFT
)
301 | URB_WRITE_PRIM_END
));
302 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[3], 1);
305 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[2], 0);
306 brw_ff_gs_overwrite_header_dw2(
307 c
, _3DPRIM_POLYGON
<< URB_WRITE_PRIM_TYPE_SHIFT
);
308 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[3], 0);
309 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[0], 0);
310 brw_ff_gs_overwrite_header_dw2(
311 c
, ((_3DPRIM_POLYGON
<< URB_WRITE_PRIM_TYPE_SHIFT
)
312 | URB_WRITE_PRIM_END
));
313 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[1], 1);
317 void brw_ff_gs_lines(struct brw_ff_gs_compile
*c
)
319 brw_ff_gs_alloc_regs(c
, 2, false);
320 brw_ff_gs_initialize_header(c
);
322 if (c
->func
.devinfo
->gen
== 5)
323 brw_ff_gs_ff_sync(c
, 1);
324 brw_ff_gs_overwrite_header_dw2(
325 c
, ((_3DPRIM_LINESTRIP
<< URB_WRITE_PRIM_TYPE_SHIFT
)
326 | URB_WRITE_PRIM_START
));
327 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[0], 0);
328 brw_ff_gs_overwrite_header_dw2(
329 c
, ((_3DPRIM_LINESTRIP
<< URB_WRITE_PRIM_TYPE_SHIFT
)
330 | URB_WRITE_PRIM_END
));
331 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[1], 1);
335 * Generate the geometry shader program used on Gen6 to perform stream output
336 * (transform feedback).
339 gen6_sol_program(struct brw_ff_gs_compile
*c
, struct brw_ff_gs_prog_key
*key
,
340 unsigned num_verts
, bool check_edge_flags
)
342 struct brw_compile
*p
= &c
->func
;
344 c
->prog_data
.svbi_postincrement_value
= num_verts
;
346 brw_ff_gs_alloc_regs(c
, num_verts
, true);
347 brw_ff_gs_initialize_header(c
);
349 if (key
->num_transform_feedback_bindings
> 0) {
350 unsigned vertex
, binding
;
351 struct brw_reg destination_indices_uw
=
352 vec8(retype(c
->reg
.destination_indices
, BRW_REGISTER_TYPE_UW
));
354 /* Note: since we use the binding table to keep track of buffer offsets
355 * and stride, the GS doesn't need to keep track of a separate pointer
356 * into each buffer; it uses a single pointer which increments by 1 for
357 * each vertex. So we use SVBI0 for this pointer, regardless of whether
358 * transform feedback is in interleaved or separate attribs mode.
360 * Make sure that the buffers have enough room for all the vertices.
362 brw_ADD(p
, get_element_ud(c
->reg
.temp
, 0),
363 get_element_ud(c
->reg
.SVBI
, 0), brw_imm_ud(num_verts
));
364 brw_CMP(p
, vec1(brw_null_reg()), BRW_CONDITIONAL_LE
,
365 get_element_ud(c
->reg
.temp
, 0),
366 get_element_ud(c
->reg
.SVBI
, 4));
367 brw_IF(p
, BRW_EXECUTE_1
);
369 /* Compute the destination indices to write to. Usually we use SVBI[0]
370 * + (0, 1, 2). However, for odd-numbered triangles in tristrips, the
371 * vertices come down the pipeline in reversed winding order, so we need
372 * to flip the order when writing to the transform feedback buffer. To
373 * ensure that flatshading accuracy is preserved, we need to write them
374 * in order SVBI[0] + (0, 2, 1) if we're using the first provoking
375 * vertex convention, and in order SVBI[0] + (1, 0, 2) if we're using
376 * the last provoking vertex convention.
378 * Note: since brw_imm_v can only be used in instructions in
379 * packed-word execution mode, and SVBI is a double-word, we need to
380 * first move the appropriate immediate constant ((0, 1, 2), (0, 2, 1),
381 * or (1, 0, 2)) to the destination_indices register, and then add SVBI
382 * using a separate instruction. Also, since the immediate constant is
383 * expressed as packed words, and we need to load double-words into
384 * destination_indices, we need to intersperse zeros to fill the upper
385 * halves of each double-word.
387 brw_MOV(p
, destination_indices_uw
,
388 brw_imm_v(0x00020100)); /* (0, 1, 2) */
389 if (num_verts
== 3) {
390 /* Get primitive type into temp register. */
391 brw_AND(p
, get_element_ud(c
->reg
.temp
, 0),
392 get_element_ud(c
->reg
.R0
, 2), brw_imm_ud(0x1f));
394 /* Test if primitive type is TRISTRIP_REVERSE. We need to do this as
395 * an 8-wide comparison so that the conditional MOV that follows
396 * moves all 8 words correctly.
398 brw_CMP(p
, vec8(brw_null_reg()), BRW_CONDITIONAL_EQ
,
399 get_element_ud(c
->reg
.temp
, 0),
400 brw_imm_ud(_3DPRIM_TRISTRIP_REVERSE
));
402 /* If so, then overwrite destination_indices_uw with the appropriate
405 inst
= brw_MOV(p
, destination_indices_uw
,
406 brw_imm_v(key
->pv_first
? 0x00010200 /* (0, 2, 1) */
407 : 0x00020001)); /* (1, 0, 2) */
408 brw_inst_set_pred_control(p
->devinfo
, inst
, BRW_PREDICATE_NORMAL
);
410 brw_ADD(p
, c
->reg
.destination_indices
,
411 c
->reg
.destination_indices
, get_element_ud(c
->reg
.SVBI
, 0));
413 /* For each vertex, generate code to output each varying using the
414 * appropriate binding table entry.
416 for (vertex
= 0; vertex
< num_verts
; ++vertex
) {
417 /* Set up the correct destination index for this vertex */
418 brw_MOV(p
, get_element_ud(c
->reg
.header
, 5),
419 get_element_ud(c
->reg
.destination_indices
, vertex
));
421 for (binding
= 0; binding
< key
->num_transform_feedback_bindings
;
423 unsigned char varying
=
424 key
->transform_feedback_bindings
[binding
];
425 unsigned char slot
= c
->vue_map
.varying_to_slot
[varying
];
426 /* From the Sandybridge PRM, Volume 2, Part 1, Section 4.5.1:
428 * "Prior to End of Thread with a URB_WRITE, the kernel must
429 * ensure that all writes are complete by sending the final
430 * write as a committed write."
433 binding
== key
->num_transform_feedback_bindings
- 1 &&
434 vertex
== num_verts
- 1;
435 struct brw_reg vertex_slot
= c
->reg
.vertex
[vertex
];
436 vertex_slot
.nr
+= slot
/ 2;
437 vertex_slot
.subnr
= (slot
% 2) * 16;
438 /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w. */
439 vertex_slot
.dw1
.bits
.swizzle
= varying
== VARYING_SLOT_PSIZ
440 ? BRW_SWIZZLE_WWWW
: key
->transform_feedback_swizzles
[binding
];
441 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
442 brw_MOV(p
, stride(c
->reg
.header
, 4, 4, 1),
443 retype(vertex_slot
, BRW_REGISTER_TYPE_UD
));
444 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
446 final_write
? c
->reg
.temp
: brw_null_reg(), /* dest */
448 c
->reg
.header
, /* src0 */
449 SURF_INDEX_GEN6_SOL_BINDING(binding
), /* binding_table_index */
450 final_write
); /* send_commit_msg */
455 /* Now, reinitialize the header register from R0 to restore the parts of
456 * the register that we overwrote while streaming out transform feedback
459 brw_ff_gs_initialize_header(c
);
461 /* Finally, wait for the write commit to occur so that we can proceed to
462 * other things safely.
464 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
466 * The write commit does not modify the destination register, but
467 * merely clears the dependency associated with the destination
468 * register. Thus, a simple “mov” instruction using the register as a
469 * source is sufficient to wait for the write commit to occur.
471 brw_MOV(p
, c
->reg
.temp
, c
->reg
.temp
);
474 brw_ff_gs_ff_sync(c
, 1);
476 brw_ff_gs_overwrite_header_dw2_from_r0(c
);
479 brw_ff_gs_offset_header_dw2(c
,
480 URB_WRITE_PRIM_START
| URB_WRITE_PRIM_END
);
481 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[0], true);
484 brw_ff_gs_offset_header_dw2(c
, URB_WRITE_PRIM_START
);
485 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[0], false);
486 brw_ff_gs_offset_header_dw2(c
,
487 URB_WRITE_PRIM_END
- URB_WRITE_PRIM_START
);
488 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[1], true);
491 if (check_edge_flags
) {
492 /* Only emit vertices 0 and 1 if this is the first triangle of the
493 * polygon. Otherwise they are redundant.
495 brw_AND(p
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
496 get_element_ud(c
->reg
.R0
, 2),
497 brw_imm_ud(BRW_GS_EDGE_INDICATOR_0
));
498 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
499 brw_IF(p
, BRW_EXECUTE_1
);
501 brw_ff_gs_offset_header_dw2(c
, URB_WRITE_PRIM_START
);
502 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[0], false);
503 brw_ff_gs_offset_header_dw2(c
, -URB_WRITE_PRIM_START
);
504 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[1], false);
505 if (check_edge_flags
) {
507 /* Only emit vertex 2 in PRIM_END mode if this is the last triangle
508 * of the polygon. Otherwise leave the primitive incomplete because
509 * there are more polygon vertices coming.
511 brw_AND(p
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
512 get_element_ud(c
->reg
.R0
, 2),
513 brw_imm_ud(BRW_GS_EDGE_INDICATOR_1
));
514 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
515 brw_set_default_predicate_control(p
, BRW_PREDICATE_NORMAL
);
517 brw_ff_gs_offset_header_dw2(c
, URB_WRITE_PRIM_END
);
518 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
519 brw_ff_gs_emit_vue(c
, c
->reg
.vertex
[2], true);