2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "compiler/glsl_types.h"
46 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
47 const fs_reg
*src
, unsigned sources
)
49 memset(this, 0, sizeof(*this));
51 this->src
= new fs_reg
[MAX2(sources
, 3)];
52 for (unsigned i
= 0; i
< sources
; i
++)
53 this->src
[i
] = src
[i
];
55 this->opcode
= opcode
;
57 this->sources
= sources
;
58 this->exec_size
= exec_size
;
60 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
62 assert(this->exec_size
!= 0);
64 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
66 /* This will be the case for almost all instructions. */
73 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
77 this->regs_written
= 0;
81 unreachable("Invalid destination register file");
84 this->writes_accumulator
= false;
89 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
92 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
94 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
99 init(opcode
, exec_size
, dst
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
105 const fs_reg src
[1] = { src0
};
106 init(opcode
, exec_size
, dst
, src
, 1);
109 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg
&src0
, const fs_reg
&src1
)
112 const fs_reg src
[2] = { src0
, src1
};
113 init(opcode
, exec_size
, dst
, src
, 2);
116 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
117 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
119 const fs_reg src
[3] = { src0
, src1
, src2
};
120 init(opcode
, exec_size
, dst
, src
, 3);
123 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
124 const fs_reg src
[], unsigned sources
)
126 init(opcode
, exec_width
, dst
, src
, sources
);
129 fs_inst::fs_inst(const fs_inst
&that
)
131 memcpy(this, &that
, sizeof(that
));
133 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
135 for (unsigned i
= 0; i
< that
.sources
; i
++)
136 this->src
[i
] = that
.src
[i
];
145 fs_inst::resize_sources(uint8_t num_sources
)
147 if (this->sources
!= num_sources
) {
148 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
150 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
151 src
[i
] = this->src
[i
];
155 this->sources
= num_sources
;
160 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
162 const fs_reg
&surf_index
,
163 const fs_reg
&varying_offset
,
164 uint32_t const_offset
)
166 /* We have our constant surface use a pitch of 4 bytes, so our index can
167 * be any component of a vector, and then we load 4 contiguous
168 * components starting from that.
170 * We break down the const_offset to a portion added to the variable
171 * offset and a portion done using reg_offset, which means that if you
172 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
173 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
174 * CSE can later notice that those loads are all the same and eliminate
175 * the redundant ones.
177 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
178 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
181 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
182 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
183 * u, v, r) as parameters, or we can just use the SIMD16 message
184 * consisting of (header, u). We choose the second, at the cost of a
185 * longer return length.
191 if (devinfo
->gen
>= 7)
192 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
194 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
196 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
197 fs_reg vec4_result
= fs_reg(VGRF
, alloc
.allocate(regs_written
), dst
.type
);
198 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
199 inst
->regs_written
= regs_written
;
201 if (devinfo
->gen
< 7) {
202 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
203 inst
->header_size
= 1;
204 if (devinfo
->gen
== 4)
207 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
210 bld
.MOV(dst
, offset(vec4_result
, bld
, ((const_offset
& 0xf) / 4) * scale
));
214 * A helper for MOV generation for fixing up broken hardware SEND dependency
218 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
220 /* The caller always wants uncompressed to emit the minimal extra
221 * dependencies, and to avoid having to deal with aligning its regs to 2.
223 const fs_builder ubld
= bld
.annotate("send dependency resolve")
226 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
230 fs_inst::equals(fs_inst
*inst
) const
232 return (opcode
== inst
->opcode
&&
233 dst
.equals(inst
->dst
) &&
234 src
[0].equals(inst
->src
[0]) &&
235 src
[1].equals(inst
->src
[1]) &&
236 src
[2].equals(inst
->src
[2]) &&
237 saturate
== inst
->saturate
&&
238 predicate
== inst
->predicate
&&
239 conditional_mod
== inst
->conditional_mod
&&
240 mlen
== inst
->mlen
&&
241 base_mrf
== inst
->base_mrf
&&
242 target
== inst
->target
&&
244 header_size
== inst
->header_size
&&
245 shadow_compare
== inst
->shadow_compare
&&
246 exec_size
== inst
->exec_size
&&
247 offset
== inst
->offset
);
251 fs_inst::overwrites_reg(const fs_reg
®
) const
253 return reg
.in_range(dst
, regs_written
);
257 fs_inst::is_send_from_grf() const
260 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
261 case SHADER_OPCODE_SHADER_TIME_ADD
:
262 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
263 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
264 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
265 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
266 case SHADER_OPCODE_UNTYPED_ATOMIC
:
267 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
268 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
269 case SHADER_OPCODE_TYPED_ATOMIC
:
270 case SHADER_OPCODE_TYPED_SURFACE_READ
:
271 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
272 case SHADER_OPCODE_URB_WRITE_SIMD8
:
273 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
274 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
275 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
276 case SHADER_OPCODE_URB_READ_SIMD8
:
277 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
279 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
280 return src
[1].file
== VGRF
;
281 case FS_OPCODE_FB_WRITE
:
282 return src
[0].file
== VGRF
;
285 return src
[0].file
== VGRF
;
292 * Returns true if this instruction's sources and destinations cannot
293 * safely be the same register.
295 * In most cases, a register can be written over safely by the same
296 * instruction that is its last use. For a single instruction, the
297 * sources are dereferenced before writing of the destination starts
300 * However, there are a few cases where this can be problematic:
302 * - Virtual opcodes that translate to multiple instructions in the
303 * code generator: if src == dst and one instruction writes the
304 * destination before a later instruction reads the source, then
305 * src will have been clobbered.
307 * - SIMD16 compressed instructions with certain regioning (see below).
309 * The register allocator uses this information to set up conflicts between
310 * GRF sources and the destination.
313 fs_inst::has_source_and_destination_hazard() const
316 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
317 /* Multiple partial writes to the destination */
320 /* The SIMD16 compressed instruction
322 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
324 * is actually decoded in hardware as:
326 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
327 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
329 * Which is safe. However, if we have uniform accesses
330 * happening, we get into trouble:
332 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
333 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
335 * Now our destination for the first instruction overwrote the
336 * second instruction's src0, and we get garbage for those 8
337 * pixels. There's a similar issue for the pre-gen6
338 * pixel_x/pixel_y, which are registers of 16-bit values and thus
339 * would get stomped by the first decode as well.
341 if (exec_size
== 16) {
342 for (int i
= 0; i
< sources
; i
++) {
343 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
344 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
345 src
[i
].type
== BRW_REGISTER_TYPE_W
||
346 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
347 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
357 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
359 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
362 fs_reg reg
= this->src
[0];
363 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
366 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
369 for (int i
= 0; i
< this->sources
; i
++) {
370 reg
.type
= this->src
[i
].type
;
371 if (!this->src
[i
].equals(reg
))
374 if (i
< this->header_size
) {
377 reg
.reg_offset
+= this->exec_size
/ 8;
385 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
387 if (devinfo
->gen
== 6 && is_math())
390 if (is_send_from_grf())
393 if (!backend_instruction::can_do_source_mods())
400 fs_inst::can_change_types() const
402 return dst
.type
== src
[0].type
&&
403 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
404 (opcode
== BRW_OPCODE_MOV
||
405 (opcode
== BRW_OPCODE_SEL
&&
406 dst
.type
== src
[1].type
&&
407 predicate
!= BRW_PREDICATE_NONE
&&
408 !src
[1].abs
&& !src
[1].negate
));
412 fs_inst::has_side_effects() const
414 return this->eot
|| backend_instruction::has_side_effects();
420 memset(this, 0, sizeof(*this));
424 /** Generic unset register constructor. */
428 this->file
= BAD_FILE
;
431 fs_reg::fs_reg(struct ::brw_reg reg
) :
434 this->reg_offset
= 0;
435 this->subreg_offset
= 0;
436 this->reladdr
= NULL
;
438 if (this->file
== IMM
&&
439 (this->type
!= BRW_REGISTER_TYPE_V
&&
440 this->type
!= BRW_REGISTER_TYPE_UV
&&
441 this->type
!= BRW_REGISTER_TYPE_VF
)) {
447 fs_reg::equals(const fs_reg
&r
) const
449 return (this->backend_reg::equals(r
) &&
450 subreg_offset
== r
.subreg_offset
&&
451 !reladdr
&& !r
.reladdr
&&
456 fs_reg::set_smear(unsigned subreg
)
458 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
459 subreg_offset
= subreg
* type_sz(type
);
465 fs_reg::is_contiguous() const
471 fs_reg::component_size(unsigned width
) const
473 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
476 return MAX2(width
* stride
, 1) * type_sz(type
);
480 type_size_scalar(const struct glsl_type
*type
)
482 unsigned int size
, i
;
484 switch (type
->base_type
) {
487 case GLSL_TYPE_FLOAT
:
489 return type
->components();
490 case GLSL_TYPE_ARRAY
:
491 return type_size_scalar(type
->fields
.array
) * type
->length
;
492 case GLSL_TYPE_STRUCT
:
494 for (i
= 0; i
< type
->length
; i
++) {
495 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
498 case GLSL_TYPE_SAMPLER
:
499 /* Samplers take up no register space, since they're baked in at
503 case GLSL_TYPE_ATOMIC_UINT
:
505 case GLSL_TYPE_SUBROUTINE
:
507 case GLSL_TYPE_IMAGE
:
508 return BRW_IMAGE_PARAM_SIZE
;
510 case GLSL_TYPE_ERROR
:
511 case GLSL_TYPE_INTERFACE
:
512 case GLSL_TYPE_DOUBLE
:
513 case GLSL_TYPE_FUNCTION
:
514 unreachable("not reached");
521 * Returns the number of scalar components needed to store type, assuming
522 * that vectors are padded out to vec4.
524 * This has the packing rules of type_size_vec4(), but counts components
525 * similar to type_size_scalar().
528 type_size_vec4_times_4(const struct glsl_type
*type
)
530 return 4 * type_size_vec4(type
);
534 * Create a MOV to read the timestamp register.
536 * The caller is responsible for emitting the MOV. The return value is
537 * the destination of the MOV, with extra parameters set.
540 fs_visitor::get_timestamp(const fs_builder
&bld
)
542 assert(devinfo
->gen
>= 7);
544 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
547 BRW_REGISTER_TYPE_UD
));
549 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
551 /* We want to read the 3 fields we care about even if it's not enabled in
554 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
560 fs_visitor::emit_shader_time_begin()
562 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
564 /* We want only the low 32 bits of the timestamp. Since it's running
565 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
566 * which is plenty of time for our purposes. It is identical across the
567 * EUs, but since it's tracking GPU core speed it will increment at a
568 * varying rate as render P-states change.
570 shader_start_time
.set_smear(0);
574 fs_visitor::emit_shader_time_end()
576 /* Insert our code just before the final SEND with EOT. */
577 exec_node
*end
= this->instructions
.get_tail();
578 assert(end
&& ((fs_inst
*) end
)->eot
);
579 const fs_builder ibld
= bld
.annotate("shader time end")
580 .exec_all().at(NULL
, end
);
582 fs_reg shader_end_time
= get_timestamp(ibld
);
584 /* We only use the low 32 bits of the timestamp - see
585 * emit_shader_time_begin()).
587 * We could also check if render P-states have changed (or anything
588 * else that might disrupt timing) by setting smear to 2 and checking if
589 * that field is != 0.
591 shader_end_time
.set_smear(0);
593 /* Check that there weren't any timestamp reset events (assuming these
594 * were the only two timestamp reads that happened).
596 fs_reg reset
= shader_end_time
;
598 set_condmod(BRW_CONDITIONAL_Z
,
599 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
600 ibld
.IF(BRW_PREDICATE_NORMAL
);
602 fs_reg start
= shader_start_time
;
604 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
607 const fs_builder cbld
= ibld
.group(1, 0);
608 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
610 /* If there were no instructions between the two timestamp gets, the diff
611 * is 2 cycles. Remove that overhead, so I can forget about that when
612 * trying to determine the time taken for single instructions.
614 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
615 SHADER_TIME_ADD(cbld
, 0, diff
);
616 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
617 ibld
.emit(BRW_OPCODE_ELSE
);
618 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
619 ibld
.emit(BRW_OPCODE_ENDIF
);
623 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
624 int shader_time_subindex
,
627 int index
= shader_time_index
* 3 + shader_time_subindex
;
628 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
631 if (dispatch_width
== 8)
632 payload
= vgrf(glsl_type::uvec2_type
);
634 payload
= vgrf(glsl_type::uint_type
);
636 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
640 fs_visitor::vfail(const char *format
, va_list va
)
649 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
650 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
652 this->fail_msg
= msg
;
655 fprintf(stderr
, "%s", msg
);
660 fs_visitor::fail(const char *format
, ...)
664 va_start(va
, format
);
670 * Mark this program as impossible to compile in SIMD16 mode.
672 * During the SIMD8 compile (which happens first), we can detect and flag
673 * things that are unsupported in SIMD16 mode, so the compiler can skip
674 * the SIMD16 compile altogether.
676 * During a SIMD16 compile (if one happens anyway), this just calls fail().
679 fs_visitor::no16(const char *msg
)
681 if (dispatch_width
== 16) {
684 simd16_unsupported
= true;
686 compiler
->shader_perf_log(log_data
,
687 "SIMD16 shader failed to compile: %s", msg
);
692 * Returns true if the instruction has a flag that means it won't
693 * update an entire destination register.
695 * For example, dead code elimination and live variable analysis want to know
696 * when a write to a variable screens off any preceding values that were in
700 fs_inst::is_partial_write() const
702 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
703 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
704 !this->dst
.is_contiguous());
708 fs_inst::components_read(unsigned i
) const
711 case FS_OPCODE_LINTERP
:
717 case FS_OPCODE_PIXEL_X
:
718 case FS_OPCODE_PIXEL_Y
:
722 case FS_OPCODE_FB_WRITE_LOGICAL
:
723 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
724 /* First/second FB write color. */
726 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
730 case SHADER_OPCODE_TEX_LOGICAL
:
731 case SHADER_OPCODE_TXD_LOGICAL
:
732 case SHADER_OPCODE_TXF_LOGICAL
:
733 case SHADER_OPCODE_TXL_LOGICAL
:
734 case SHADER_OPCODE_TXS_LOGICAL
:
735 case FS_OPCODE_TXB_LOGICAL
:
736 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
737 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
738 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
739 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
740 case SHADER_OPCODE_LOD_LOGICAL
:
741 case SHADER_OPCODE_TG4_LOGICAL
:
742 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
743 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
744 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
745 /* Texture coordinates. */
746 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
747 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
748 /* Texture derivatives. */
749 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
750 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
751 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
752 /* Texture offset. */
753 else if (i
== TEX_LOGICAL_SRC_OFFSET_VALUE
)
756 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
761 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
762 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
763 assert(src
[3].file
== IMM
);
764 /* Surface coordinates. */
767 /* Surface operation source (ignored for reads). */
773 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
774 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
775 assert(src
[3].file
== IMM
&&
777 /* Surface coordinates. */
780 /* Surface operation source. */
786 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
787 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
788 assert(src
[3].file
== IMM
&&
790 const unsigned op
= src
[4].ud
;
791 /* Surface coordinates. */
794 /* Surface operation source. */
795 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
797 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
798 op
== BRW_AOP_PREDEC
))
810 fs_inst::regs_read(int arg
) const
813 case FS_OPCODE_FB_WRITE
:
814 case SHADER_OPCODE_URB_WRITE_SIMD8
:
815 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
816 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
817 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
818 case SHADER_OPCODE_URB_READ_SIMD8
:
819 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
820 case SHADER_OPCODE_UNTYPED_ATOMIC
:
821 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
822 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
823 case SHADER_OPCODE_TYPED_ATOMIC
:
824 case SHADER_OPCODE_TYPED_SURFACE_READ
:
825 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
826 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
831 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
832 /* The payload is actually stored in src1 */
837 case FS_OPCODE_LINTERP
:
842 case SHADER_OPCODE_LOAD_PAYLOAD
:
843 if (arg
< this->header_size
)
847 case CS_OPCODE_CS_TERMINATE
:
848 case SHADER_OPCODE_BARRIER
:
851 case SHADER_OPCODE_MOV_INDIRECT
:
853 assert(src
[2].file
== IMM
);
854 unsigned region_length
= src
[2].ud
;
856 if (src
[0].file
== UNIFORM
) {
857 assert(region_length
% 4 == 0);
858 return region_length
/ 4;
859 } else if (src
[0].file
== FIXED_GRF
) {
860 /* If the start of the region is not register aligned, then
861 * there's some portion of the register that's technically
862 * unread at the beginning.
864 * However, the register allocator works in terms of whole
865 * registers, and does not use subnr. It assumes that the
866 * read starts at the beginning of the register, and extends
867 * regs_read() whole registers beyond that.
869 * To compensate, we extend the region length to include this
870 * unread portion at the beginning.
873 region_length
+= src
[0].subnr
;
875 return DIV_ROUND_UP(region_length
, REG_SIZE
);
877 assert(!"Invalid register file");
883 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
888 switch (src
[arg
].file
) {
898 return DIV_ROUND_UP(components_read(arg
) *
899 src
[arg
].component_size(exec_size
),
902 unreachable("MRF registers are not allowed as sources");
908 fs_inst::reads_flag() const
914 fs_inst::writes_flag() const
916 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
917 opcode
!= BRW_OPCODE_IF
&&
918 opcode
!= BRW_OPCODE_WHILE
)) ||
919 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
923 * Returns how many MRFs an FS opcode will write over.
925 * Note that this is not the 0 or 1 implied writes in an actual gen
926 * instruction -- the FS opcodes often generate MOVs in addition.
929 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
934 if (inst
->base_mrf
== -1)
937 switch (inst
->opcode
) {
938 case SHADER_OPCODE_RCP
:
939 case SHADER_OPCODE_RSQ
:
940 case SHADER_OPCODE_SQRT
:
941 case SHADER_OPCODE_EXP2
:
942 case SHADER_OPCODE_LOG2
:
943 case SHADER_OPCODE_SIN
:
944 case SHADER_OPCODE_COS
:
945 return 1 * dispatch_width
/ 8;
946 case SHADER_OPCODE_POW
:
947 case SHADER_OPCODE_INT_QUOTIENT
:
948 case SHADER_OPCODE_INT_REMAINDER
:
949 return 2 * dispatch_width
/ 8;
950 case SHADER_OPCODE_TEX
:
952 case SHADER_OPCODE_TXD
:
953 case SHADER_OPCODE_TXF
:
954 case SHADER_OPCODE_TXF_CMS
:
955 case SHADER_OPCODE_TXF_CMS_W
:
956 case SHADER_OPCODE_TXF_MCS
:
957 case SHADER_OPCODE_TG4
:
958 case SHADER_OPCODE_TG4_OFFSET
:
959 case SHADER_OPCODE_TXL
:
960 case SHADER_OPCODE_TXS
:
961 case SHADER_OPCODE_LOD
:
962 case SHADER_OPCODE_SAMPLEINFO
:
964 case FS_OPCODE_FB_WRITE
:
966 case FS_OPCODE_GET_BUFFER_SIZE
:
967 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
968 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
970 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
972 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
974 case SHADER_OPCODE_UNTYPED_ATOMIC
:
975 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
976 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
977 case SHADER_OPCODE_TYPED_ATOMIC
:
978 case SHADER_OPCODE_TYPED_SURFACE_READ
:
979 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
980 case SHADER_OPCODE_URB_WRITE_SIMD8
:
981 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
982 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
983 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
984 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
985 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
986 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
987 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
990 unreachable("not reached");
995 fs_visitor::vgrf(const glsl_type
*const type
)
997 int reg_width
= dispatch_width
/ 8;
998 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
999 brw_type_for_base_type(type
));
1002 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1007 this->type
= BRW_REGISTER_TYPE_F
;
1008 this->stride
= (file
== UNIFORM
? 0 : 1);
1011 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1017 this->stride
= (file
== UNIFORM
? 0 : 1);
1020 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1021 * This brings in those uniform definitions
1024 fs_visitor::import_uniforms(fs_visitor
*v
)
1026 this->push_constant_loc
= v
->push_constant_loc
;
1027 this->pull_constant_loc
= v
->pull_constant_loc
;
1028 this->uniforms
= v
->uniforms
;
1029 this->param_size
= v
->param_size
;
1033 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
1034 bool origin_upper_left
)
1036 assert(stage
== MESA_SHADER_FRAGMENT
);
1037 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1038 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1040 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
1042 /* gl_FragCoord.x */
1043 if (pixel_center_integer
) {
1044 bld
.MOV(wpos
, this->pixel_x
);
1046 bld
.ADD(wpos
, this->pixel_x
, brw_imm_f(0.5f
));
1048 wpos
= offset(wpos
, bld
, 1);
1050 /* gl_FragCoord.y */
1051 if (!flip
&& pixel_center_integer
) {
1052 bld
.MOV(wpos
, this->pixel_y
);
1054 fs_reg pixel_y
= this->pixel_y
;
1055 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
1058 pixel_y
.negate
= true;
1059 offset
+= key
->drawable_height
- 1.0f
;
1062 bld
.ADD(wpos
, pixel_y
, brw_imm_f(offset
));
1064 wpos
= offset(wpos
, bld
, 1);
1066 /* gl_FragCoord.z */
1067 if (devinfo
->gen
>= 6) {
1068 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1070 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1071 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1072 interp_reg(VARYING_SLOT_POS
, 2));
1074 wpos
= offset(wpos
, bld
, 1);
1076 /* gl_FragCoord.w: Already set up in emit_interpolation */
1077 bld
.MOV(wpos
, this->wpos_w
);
1083 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1084 glsl_interp_qualifier interpolation_mode
,
1085 bool is_centroid
, bool is_sample
)
1087 brw_wm_barycentric_interp_mode barycoord_mode
;
1088 if (devinfo
->gen
>= 6) {
1090 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1091 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1093 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1094 } else if (is_sample
) {
1095 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1096 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1098 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1100 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1101 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1103 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1106 /* On Ironlake and below, there is only one interpolation mode.
1107 * Centroid interpolation doesn't mean anything on this hardware --
1108 * there is no multisampling.
1110 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1112 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1113 this->delta_xy
[barycoord_mode
], interp
);
1117 fs_visitor::emit_general_interpolation(fs_reg
*attr
, const char *name
,
1118 const glsl_type
*type
,
1119 glsl_interp_qualifier interpolation_mode
,
1120 int *location
, bool mod_centroid
,
1123 assert(stage
== MESA_SHADER_FRAGMENT
);
1124 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1125 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1127 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1129 *location
== VARYING_SLOT_COL0
|| *location
== VARYING_SLOT_COL1
;
1130 if (key
->flat_shade
&& is_gl_Color
) {
1131 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1133 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1137 if (type
->is_array() || type
->is_matrix()) {
1138 const glsl_type
*elem_type
= glsl_get_array_element(type
);
1139 const unsigned length
= glsl_get_length(type
);
1141 for (unsigned i
= 0; i
< length
; i
++) {
1142 emit_general_interpolation(attr
, name
, elem_type
, interpolation_mode
,
1143 location
, mod_centroid
, mod_sample
);
1145 } else if (type
->is_record()) {
1146 for (unsigned i
= 0; i
< type
->length
; i
++) {
1147 const glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
1148 emit_general_interpolation(attr
, name
, field_type
, interpolation_mode
,
1149 location
, mod_centroid
, mod_sample
);
1152 assert(type
->is_scalar() || type
->is_vector());
1154 if (prog_data
->urb_setup
[*location
] == -1) {
1155 /* If there's no incoming setup data for this slot, don't
1156 * emit interpolation for it.
1158 *attr
= offset(*attr
, bld
, type
->vector_elements
);
1163 attr
->type
= brw_type_for_base_type(type
->get_scalar_type());
1165 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1166 /* Constant interpolation (flat shading) case. The SF has
1167 * handed us defined values in only the constant offset
1168 * field of the setup reg.
1170 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1171 struct brw_reg interp
= interp_reg(*location
, i
);
1172 interp
= suboffset(interp
, 3);
1173 interp
.type
= attr
->type
;
1174 bld
.emit(FS_OPCODE_CINTERP
, *attr
, fs_reg(interp
));
1175 *attr
= offset(*attr
, bld
, 1);
1178 /* Smooth/noperspective interpolation case. */
1179 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1180 struct brw_reg interp
= interp_reg(*location
, i
);
1181 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1182 /* Get the pixel/sample mask into f0 so that we know
1183 * which pixels are lit. Then, for each channel that is
1184 * unlit, replace the centroid data with non-centroid
1187 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1190 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1192 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1193 inst
->predicate_inverse
= true;
1194 if (devinfo
->has_pln
)
1195 inst
->no_dd_clear
= true;
1197 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1198 mod_centroid
&& !key
->persample_shading
,
1199 mod_sample
|| key
->persample_shading
);
1200 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1201 inst
->predicate_inverse
= false;
1202 if (devinfo
->has_pln
)
1203 inst
->no_dd_check
= true;
1206 emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1207 mod_centroid
&& !key
->persample_shading
,
1208 mod_sample
|| key
->persample_shading
);
1210 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1211 bld
.MUL(*attr
, *attr
, this->pixel_w
);
1213 *attr
= offset(*attr
, bld
, 1);
1221 fs_visitor::emit_frontfacing_interpolation()
1223 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1225 if (devinfo
->gen
>= 6) {
1226 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1227 * a boolean result from this (~0/true or 0/false).
1229 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1230 * this task in only one instruction:
1231 * - a negation source modifier will flip the bit; and
1232 * - a W -> D type conversion will sign extend the bit into the high
1233 * word of the destination.
1235 * An ASR 15 fills the low word of the destination.
1237 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1240 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1242 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1243 * a boolean result from this (1/true or 0/false).
1245 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1246 * the negation source modifier to flip it. Unfortunately the SHR
1247 * instruction only operates on UD (or D with an abs source modifier)
1248 * sources without negation.
1250 * Instead, use ASR (which will give ~0/true or 0/false).
1252 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1255 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1262 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1264 assert(stage
== MESA_SHADER_FRAGMENT
);
1265 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1266 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1268 if (key
->compute_pos_offset
) {
1269 /* Convert int_sample_pos to floating point */
1270 bld
.MOV(dst
, int_sample_pos
);
1271 /* Scale to the range [0, 1] */
1272 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1275 /* From ARB_sample_shading specification:
1276 * "When rendering to a non-multisample buffer, or if multisample
1277 * rasterization is disabled, gl_SamplePosition will always be
1280 bld
.MOV(dst
, brw_imm_f(0.5f
));
1285 fs_visitor::emit_samplepos_setup()
1287 assert(devinfo
->gen
>= 6);
1289 const fs_builder abld
= bld
.annotate("compute sample position");
1290 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1292 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1293 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1295 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1296 * mode will be enabled.
1298 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1299 * R31.1:0 Position Offset X/Y for Slot[3:0]
1300 * R31.3:2 Position Offset X/Y for Slot[7:4]
1303 * The X, Y sample positions come in as bytes in thread payload. So, read
1304 * the positions using vstride=16, width=8, hstride=2.
1306 struct brw_reg sample_pos_reg
=
1307 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1308 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1310 if (dispatch_width
== 8) {
1311 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1313 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1314 abld
.half(1).MOV(half(int_sample_x
, 1),
1315 fs_reg(suboffset(sample_pos_reg
, 16)));
1317 /* Compute gl_SamplePosition.x */
1318 compute_sample_position(pos
, int_sample_x
);
1319 pos
= offset(pos
, abld
, 1);
1320 if (dispatch_width
== 8) {
1321 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1323 abld
.half(0).MOV(half(int_sample_y
, 0),
1324 fs_reg(suboffset(sample_pos_reg
, 1)));
1325 abld
.half(1).MOV(half(int_sample_y
, 1),
1326 fs_reg(suboffset(sample_pos_reg
, 17)));
1328 /* Compute gl_SamplePosition.y */
1329 compute_sample_position(pos
, int_sample_y
);
1334 fs_visitor::emit_sampleid_setup()
1336 assert(stage
== MESA_SHADER_FRAGMENT
);
1337 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1338 assert(devinfo
->gen
>= 6);
1340 const fs_builder abld
= bld
.annotate("compute sample id");
1341 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1343 if (key
->compute_sample_id
) {
1344 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1346 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1348 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1349 * 8x multisampling, subspan 0 will represent sample N (where N
1350 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1351 * 7. We can find the value of N by looking at R0.0 bits 7:6
1352 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1353 * (since samples are always delivered in pairs). That is, we
1354 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1355 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1356 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1357 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1358 * populating a temporary variable with the sequence (0, 1, 2, 3),
1359 * and then reading from it using vstride=1, width=4, hstride=0.
1360 * These computations hold good for 4x multisampling as well.
1362 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1363 * the first four slots are sample 0 of subspan 0; the next four
1364 * are sample 1 of subspan 0; the third group is sample 0 of
1365 * subspan 1, and finally sample 1 of subspan 1.
1368 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1369 * accomodate 16x MSAA.
1371 unsigned sspi_mask
= devinfo
->gen
>= 9 ? 0x1c0 : 0xc0;
1373 abld
.exec_all().group(1, 0)
1374 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1375 brw_imm_ud(sspi_mask
));
1376 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1378 /* This works for both SIMD8 and SIMD16 */
1379 abld
.exec_all().group(4, 0)
1380 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1382 /* This special instruction takes care of setting vstride=1,
1383 * width=4, hstride=0 of t2 during an ADD instruction.
1385 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1387 /* As per GL_ARB_sample_shading specification:
1388 * "When rendering to a non-multisample buffer, or if multisample
1389 * rasterization is disabled, gl_SampleID will always be zero."
1391 abld
.MOV(*reg
, brw_imm_d(0));
1398 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1400 if (!src
.abs
&& !src
.negate
)
1403 fs_reg temp
= bld
.vgrf(src
.type
);
1410 fs_visitor::emit_discard_jump()
1412 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1414 /* For performance, after a discard, jump to the end of the
1415 * shader if all relevant channels have been discarded.
1417 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1418 discard_jump
->flag_subreg
= 1;
1420 discard_jump
->predicate
= (dispatch_width
== 8)
1421 ? BRW_PREDICATE_ALIGN1_ANY8H
1422 : BRW_PREDICATE_ALIGN1_ANY16H
;
1423 discard_jump
->predicate_inverse
= true;
1427 fs_visitor::emit_gs_thread_end()
1429 assert(stage
== MESA_SHADER_GEOMETRY
);
1431 struct brw_gs_prog_data
*gs_prog_data
=
1432 (struct brw_gs_prog_data
*) prog_data
;
1434 if (gs_compile
->control_data_header_size_bits
> 0) {
1435 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1438 const fs_builder abld
= bld
.annotate("thread end");
1441 if (gs_prog_data
->static_vertex_count
!= -1) {
1442 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1443 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1444 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1445 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1446 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1449 /* Delete now dead instructions. */
1450 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1456 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1460 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1461 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1462 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1465 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1466 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1467 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1468 sources
[1] = this->final_gs_vertex_count
;
1469 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1470 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1478 fs_visitor::assign_curb_setup()
1480 if (dispatch_width
== 8) {
1481 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1483 if (stage
== MESA_SHADER_FRAGMENT
) {
1484 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1485 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1486 } else if (stage
== MESA_SHADER_COMPUTE
) {
1487 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1488 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1490 unreachable("Unsupported shader type!");
1494 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1496 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1497 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1498 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1499 if (inst
->src
[i
].file
== UNIFORM
) {
1500 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1502 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1503 constant_nr
= push_constant_loc
[uniform_nr
];
1505 /* Section 5.11 of the OpenGL 4.1 spec says:
1506 * "Out-of-bounds reads return undefined values, which include
1507 * values from other variables of the active program or zero."
1508 * Just return the first push constant.
1513 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1516 brw_reg
.abs
= inst
->src
[i
].abs
;
1517 brw_reg
.negate
= inst
->src
[i
].negate
;
1519 assert(inst
->src
[i
].stride
== 0);
1520 inst
->src
[i
] = byte_offset(
1521 retype(brw_reg
, inst
->src
[i
].type
),
1522 inst
->src
[i
].subreg_offset
);
1527 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1528 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1532 fs_visitor::calculate_urb_setup()
1534 assert(stage
== MESA_SHADER_FRAGMENT
);
1535 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1536 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1538 memset(prog_data
->urb_setup
, -1,
1539 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1542 /* Figure out where each of the incoming setup attributes lands. */
1543 if (devinfo
->gen
>= 6) {
1544 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1545 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1546 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1547 * first 16 varying inputs, so we can put them wherever we want.
1548 * Just put them in order.
1550 * This is useful because it means that (a) inputs not used by the
1551 * fragment shader won't take up valuable register space, and (b) we
1552 * won't have to recompile the fragment shader if it gets paired with
1553 * a different vertex (or geometry) shader.
1555 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1556 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1557 BITFIELD64_BIT(i
)) {
1558 prog_data
->urb_setup
[i
] = urb_next
++;
1562 bool include_vue_header
=
1563 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1565 /* We have enough input varyings that the SF/SBE pipeline stage can't
1566 * arbitrarily rearrange them to suit our whim; we have to put them
1567 * in an order that matches the output of the previous pipeline stage
1568 * (geometry or vertex shader).
1570 struct brw_vue_map prev_stage_vue_map
;
1571 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1572 key
->input_slots_valid
,
1573 nir
->info
.separate_shader
);
1575 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1577 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1578 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1580 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1581 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1582 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1583 BITFIELD64_BIT(varying
))) {
1584 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1587 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1590 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1591 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1592 /* Point size is packed into the header, not as a general attribute */
1593 if (i
== VARYING_SLOT_PSIZ
)
1596 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1597 /* The back color slot is skipped when the front color is
1598 * also written to. In addition, some slots can be
1599 * written in the vertex shader and not read in the
1600 * fragment shader. So the register number must always be
1601 * incremented, mapped or not.
1603 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1604 prog_data
->urb_setup
[i
] = urb_next
;
1610 * It's a FS only attribute, and we did interpolation for this attribute
1611 * in SF thread. So, count it here, too.
1613 * See compile_sf_prog() for more info.
1615 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1616 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1619 prog_data
->num_varying_inputs
= urb_next
;
1623 fs_visitor::assign_urb_setup()
1625 assert(stage
== MESA_SHADER_FRAGMENT
);
1626 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1628 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1630 /* Offset all the urb_setup[] index by the actual position of the
1631 * setup regs, now that the location of the constants has been chosen.
1633 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1634 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1635 assert(inst
->src
[1].file
== FIXED_GRF
);
1636 inst
->src
[1].nr
+= urb_start
;
1639 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1640 assert(inst
->src
[0].file
== FIXED_GRF
);
1641 inst
->src
[0].nr
+= urb_start
;
1645 /* Each attribute is 4 setup channels, each of which is half a reg. */
1646 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1650 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1652 for (int i
= 0; i
< inst
->sources
; i
++) {
1653 if (inst
->src
[i
].file
== ATTR
) {
1654 int grf
= payload
.num_regs
+
1655 prog_data
->curb_read_length
+
1657 inst
->src
[i
].reg_offset
;
1659 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : inst
->exec_size
;
1660 struct brw_reg reg
=
1661 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1662 inst
->src
[i
].subreg_offset
),
1663 inst
->exec_size
* inst
->src
[i
].stride
,
1664 width
, inst
->src
[i
].stride
);
1665 reg
.abs
= inst
->src
[i
].abs
;
1666 reg
.negate
= inst
->src
[i
].negate
;
1674 fs_visitor::assign_vs_urb_setup()
1676 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1678 assert(stage
== MESA_SHADER_VERTEX
);
1680 /* Each attribute is 4 regs. */
1681 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1683 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1685 /* Rewrite all ATTR file references to the hw grf that they land in. */
1686 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1687 convert_attr_sources_to_hw_regs(inst
);
1692 fs_visitor::assign_tes_urb_setup()
1694 assert(stage
== MESA_SHADER_TESS_EVAL
);
1696 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1698 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1700 /* Rewrite all ATTR file references to HW_REGs. */
1701 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1702 convert_attr_sources_to_hw_regs(inst
);
1707 fs_visitor::assign_gs_urb_setup()
1709 assert(stage
== MESA_SHADER_GEOMETRY
);
1711 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1713 first_non_payload_grf
+=
1714 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1716 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1717 /* Rewrite all ATTR file references to GRFs. */
1718 convert_attr_sources_to_hw_regs(inst
);
1724 * Split large virtual GRFs into separate components if we can.
1726 * This is mostly duplicated with what brw_fs_vector_splitting does,
1727 * but that's really conservative because it's afraid of doing
1728 * splitting that doesn't result in real progress after the rest of
1729 * the optimization phases, which would cause infinite looping in
1730 * optimization. We can do it once here, safely. This also has the
1731 * opportunity to split interpolated values, or maybe even uniforms,
1732 * which we don't have at the IR level.
1734 * We want to split, because virtual GRFs are what we register
1735 * allocate and spill (due to contiguousness requirements for some
1736 * instructions), and they're what we naturally generate in the
1737 * codegen process, but most virtual GRFs don't actually need to be
1738 * contiguous sets of GRFs. If we split, we'll end up with reduced
1739 * live intervals and better dead code elimination and coalescing.
1742 fs_visitor::split_virtual_grfs()
1744 int num_vars
= this->alloc
.count
;
1746 /* Count the total number of registers */
1748 int vgrf_to_reg
[num_vars
];
1749 for (int i
= 0; i
< num_vars
; i
++) {
1750 vgrf_to_reg
[i
] = reg_count
;
1751 reg_count
+= alloc
.sizes
[i
];
1754 /* An array of "split points". For each register slot, this indicates
1755 * if this slot can be separated from the previous slot. Every time an
1756 * instruction uses multiple elements of a register (as a source or
1757 * destination), we mark the used slots as inseparable. Then we go
1758 * through and split the registers into the smallest pieces we can.
1760 bool split_points
[reg_count
];
1761 memset(split_points
, 0, sizeof(split_points
));
1763 /* Mark all used registers as fully splittable */
1764 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1765 if (inst
->dst
.file
== VGRF
) {
1766 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1767 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1768 split_points
[reg
+ j
] = true;
1771 for (int i
= 0; i
< inst
->sources
; i
++) {
1772 if (inst
->src
[i
].file
== VGRF
) {
1773 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1774 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1775 split_points
[reg
+ j
] = true;
1780 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1781 if (inst
->dst
.file
== VGRF
) {
1782 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1783 for (int j
= 1; j
< inst
->regs_written
; j
++)
1784 split_points
[reg
+ j
] = false;
1786 for (int i
= 0; i
< inst
->sources
; i
++) {
1787 if (inst
->src
[i
].file
== VGRF
) {
1788 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1789 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1790 split_points
[reg
+ j
] = false;
1795 int new_virtual_grf
[reg_count
];
1796 int new_reg_offset
[reg_count
];
1799 for (int i
= 0; i
< num_vars
; i
++) {
1800 /* The first one should always be 0 as a quick sanity check. */
1801 assert(split_points
[reg
] == false);
1804 new_reg_offset
[reg
] = 0;
1809 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1810 /* If this is a split point, reset the offset to 0 and allocate a
1811 * new virtual GRF for the previous offset many registers
1813 if (split_points
[reg
]) {
1814 assert(offset
<= MAX_VGRF_SIZE
);
1815 int grf
= alloc
.allocate(offset
);
1816 for (int k
= reg
- offset
; k
< reg
; k
++)
1817 new_virtual_grf
[k
] = grf
;
1820 new_reg_offset
[reg
] = offset
;
1825 /* The last one gets the original register number */
1826 assert(offset
<= MAX_VGRF_SIZE
);
1827 alloc
.sizes
[i
] = offset
;
1828 for (int k
= reg
- offset
; k
< reg
; k
++)
1829 new_virtual_grf
[k
] = i
;
1831 assert(reg
== reg_count
);
1833 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1834 if (inst
->dst
.file
== VGRF
) {
1835 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1836 inst
->dst
.nr
= new_virtual_grf
[reg
];
1837 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1838 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1840 for (int i
= 0; i
< inst
->sources
; i
++) {
1841 if (inst
->src
[i
].file
== VGRF
) {
1842 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1843 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1844 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1845 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1849 invalidate_live_intervals();
1853 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1855 * During code generation, we create tons of temporary variables, many of
1856 * which get immediately killed and are never used again. Yet, in later
1857 * optimization and analysis passes, such as compute_live_intervals, we need
1858 * to loop over all the virtual GRFs. Compacting them can save a lot of
1862 fs_visitor::compact_virtual_grfs()
1864 bool progress
= false;
1865 int remap_table
[this->alloc
.count
];
1866 memset(remap_table
, -1, sizeof(remap_table
));
1868 /* Mark which virtual GRFs are used. */
1869 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1870 if (inst
->dst
.file
== VGRF
)
1871 remap_table
[inst
->dst
.nr
] = 0;
1873 for (int i
= 0; i
< inst
->sources
; i
++) {
1874 if (inst
->src
[i
].file
== VGRF
)
1875 remap_table
[inst
->src
[i
].nr
] = 0;
1879 /* Compact the GRF arrays. */
1881 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1882 if (remap_table
[i
] == -1) {
1883 /* We just found an unused register. This means that we are
1884 * actually going to compact something.
1888 remap_table
[i
] = new_index
;
1889 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1890 invalidate_live_intervals();
1895 this->alloc
.count
= new_index
;
1897 /* Patch all the instructions to use the newly renumbered registers */
1898 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1899 if (inst
->dst
.file
== VGRF
)
1900 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1902 for (int i
= 0; i
< inst
->sources
; i
++) {
1903 if (inst
->src
[i
].file
== VGRF
)
1904 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1908 /* Patch all the references to delta_xy, since they're used in register
1909 * allocation. If they're unused, switch them to BAD_FILE so we don't
1910 * think some random VGRF is delta_xy.
1912 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1913 if (delta_xy
[i
].file
== VGRF
) {
1914 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1915 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1917 delta_xy
[i
].file
= BAD_FILE
;
1926 * Assign UNIFORM file registers to either push constants or pull constants.
1928 * We allow a fragment shader to have more than the specified minimum
1929 * maximum number of fragment shader uniform components (64). If
1930 * there are too many of these, they'd fill up all of register space.
1931 * So, this will push some of them out to the pull constant buffer and
1932 * update the program to load them. We also use pull constants for all
1933 * indirect constant loads because we don't support indirect accesses in
1937 fs_visitor::assign_constant_locations()
1939 /* Only the first compile gets to decide on locations. */
1940 if (dispatch_width
!= min_dispatch_width
)
1943 unsigned int num_pull_constants
= 0;
1945 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1946 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1948 bool is_live
[uniforms
];
1949 memset(is_live
, 0, sizeof(is_live
));
1951 /* First, we walk through the instructions and do two things:
1953 * 1) Figure out which uniforms are live.
1955 * 2) Find all indirect access of uniform arrays and flag them as needing
1956 * to go into the pull constant buffer.
1958 * Note that we don't move constant-indexed accesses to arrays. No
1959 * testing has been done of the performance impact of this choice.
1961 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1962 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1963 if (inst
->src
[i
].file
!= UNIFORM
)
1966 if (inst
->src
[i
].reladdr
) {
1967 int uniform
= inst
->src
[i
].nr
;
1969 /* If this array isn't already present in the pull constant buffer,
1972 if (pull_constant_loc
[uniform
] == -1) {
1973 assert(param_size
[uniform
]);
1974 for (int j
= 0; j
< param_size
[uniform
]; j
++)
1975 pull_constant_loc
[uniform
+ j
] = num_pull_constants
++;
1978 /* Mark the the one accessed uniform as live */
1979 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1980 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1981 is_live
[constant_nr
] = true;
1986 /* Only allow 16 registers (128 uniform components) as push constants.
1988 * Just demote the end of the list. We could probably do better
1989 * here, demoting things that are rarely used in the program first.
1991 * If changing this value, note the limitation about total_regs in
1994 unsigned int max_push_components
= 16 * 8;
1995 unsigned int num_push_constants
= 0;
1997 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1999 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2000 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
2001 /* This UNIFORM register is either dead, or has already been demoted
2002 * to a pull const. Mark it as no longer living in the param[] array.
2004 push_constant_loc
[i
] = -1;
2008 if (num_push_constants
< max_push_components
) {
2009 /* Retain as a push constant. Record the location in the params[]
2012 push_constant_loc
[i
] = num_push_constants
++;
2014 /* Demote to a pull constant. */
2015 push_constant_loc
[i
] = -1;
2016 pull_constant_loc
[i
] = num_pull_constants
++;
2020 stage_prog_data
->nr_params
= num_push_constants
;
2021 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2023 /* Up until now, the param[] array has been indexed by reg + reg_offset
2024 * of UNIFORM registers. Move pull constants into pull_param[] and
2025 * condense param[] to only contain the uniforms we chose to push.
2027 * NOTE: Because we are condensing the params[] array, we know that
2028 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2029 * having to make a copy.
2031 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2032 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
2034 if (pull_constant_loc
[i
] != -1) {
2035 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2036 } else if (push_constant_loc
[i
] != -1) {
2037 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2043 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2044 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2047 fs_visitor::demote_pull_constants()
2049 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2050 for (int i
= 0; i
< inst
->sources
; i
++) {
2051 if (inst
->src
[i
].file
!= UNIFORM
)
2055 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2056 if (location
>= uniforms
) /* Out of bounds access */
2059 pull_index
= pull_constant_loc
[location
];
2061 if (pull_index
== -1)
2064 /* Set up the annotation tracking for new generated instructions. */
2065 const fs_builder
ibld(this, block
, inst
);
2066 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2067 fs_reg dst
= vgrf(glsl_type::float_type
);
2069 assert(inst
->src
[i
].stride
== 0);
2071 /* Generate a pull load into dst. */
2072 if (inst
->src
[i
].reladdr
) {
2073 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
2075 *inst
->src
[i
].reladdr
,
2077 inst
->src
[i
].reladdr
= NULL
;
2078 inst
->src
[i
].stride
= 1;
2080 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2081 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2082 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2083 dst
, brw_imm_ud(index
), offset
);
2084 inst
->src
[i
].set_smear(pull_index
& 3);
2086 brw_mark_surface_used(prog_data
, index
);
2088 /* Rewrite the instruction to use the temporary VGRF. */
2089 inst
->src
[i
].file
= VGRF
;
2090 inst
->src
[i
].nr
= dst
.nr
;
2091 inst
->src
[i
].reg_offset
= 0;
2094 invalidate_live_intervals();
2098 fs_visitor::opt_algebraic()
2100 bool progress
= false;
2102 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2103 switch (inst
->opcode
) {
2104 case BRW_OPCODE_MOV
:
2105 if (inst
->src
[0].file
!= IMM
)
2108 if (inst
->saturate
) {
2109 if (inst
->dst
.type
!= inst
->src
[0].type
)
2110 assert(!"unimplemented: saturate mixed types");
2112 if (brw_saturate_immediate(inst
->dst
.type
,
2113 &inst
->src
[0].as_brw_reg())) {
2114 inst
->saturate
= false;
2120 case BRW_OPCODE_MUL
:
2121 if (inst
->src
[1].file
!= IMM
)
2125 if (inst
->src
[1].is_one()) {
2126 inst
->opcode
= BRW_OPCODE_MOV
;
2127 inst
->src
[1] = reg_undef
;
2133 if (inst
->src
[1].is_negative_one()) {
2134 inst
->opcode
= BRW_OPCODE_MOV
;
2135 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2136 inst
->src
[1] = reg_undef
;
2142 if (inst
->src
[1].is_zero()) {
2143 inst
->opcode
= BRW_OPCODE_MOV
;
2144 inst
->src
[0] = inst
->src
[1];
2145 inst
->src
[1] = reg_undef
;
2150 if (inst
->src
[0].file
== IMM
) {
2151 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2152 inst
->opcode
= BRW_OPCODE_MOV
;
2153 inst
->src
[0].f
*= inst
->src
[1].f
;
2154 inst
->src
[1] = reg_undef
;
2159 case BRW_OPCODE_ADD
:
2160 if (inst
->src
[1].file
!= IMM
)
2164 if (inst
->src
[1].is_zero()) {
2165 inst
->opcode
= BRW_OPCODE_MOV
;
2166 inst
->src
[1] = reg_undef
;
2171 if (inst
->src
[0].file
== IMM
) {
2172 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2173 inst
->opcode
= BRW_OPCODE_MOV
;
2174 inst
->src
[0].f
+= inst
->src
[1].f
;
2175 inst
->src
[1] = reg_undef
;
2181 if (inst
->src
[0].equals(inst
->src
[1])) {
2182 inst
->opcode
= BRW_OPCODE_MOV
;
2183 inst
->src
[1] = reg_undef
;
2188 case BRW_OPCODE_LRP
:
2189 if (inst
->src
[1].equals(inst
->src
[2])) {
2190 inst
->opcode
= BRW_OPCODE_MOV
;
2191 inst
->src
[0] = inst
->src
[1];
2192 inst
->src
[1] = reg_undef
;
2193 inst
->src
[2] = reg_undef
;
2198 case BRW_OPCODE_CMP
:
2199 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2201 inst
->src
[0].negate
&&
2202 inst
->src
[1].is_zero()) {
2203 inst
->src
[0].abs
= false;
2204 inst
->src
[0].negate
= false;
2205 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2210 case BRW_OPCODE_SEL
:
2211 if (inst
->src
[0].equals(inst
->src
[1])) {
2212 inst
->opcode
= BRW_OPCODE_MOV
;
2213 inst
->src
[1] = reg_undef
;
2214 inst
->predicate
= BRW_PREDICATE_NONE
;
2215 inst
->predicate_inverse
= false;
2217 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2218 switch (inst
->conditional_mod
) {
2219 case BRW_CONDITIONAL_LE
:
2220 case BRW_CONDITIONAL_L
:
2221 switch (inst
->src
[1].type
) {
2222 case BRW_REGISTER_TYPE_F
:
2223 if (inst
->src
[1].f
>= 1.0f
) {
2224 inst
->opcode
= BRW_OPCODE_MOV
;
2225 inst
->src
[1] = reg_undef
;
2226 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2234 case BRW_CONDITIONAL_GE
:
2235 case BRW_CONDITIONAL_G
:
2236 switch (inst
->src
[1].type
) {
2237 case BRW_REGISTER_TYPE_F
:
2238 if (inst
->src
[1].f
<= 0.0f
) {
2239 inst
->opcode
= BRW_OPCODE_MOV
;
2240 inst
->src
[1] = reg_undef
;
2241 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2253 case BRW_OPCODE_MAD
:
2254 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2255 inst
->opcode
= BRW_OPCODE_MOV
;
2256 inst
->src
[1] = reg_undef
;
2257 inst
->src
[2] = reg_undef
;
2259 } else if (inst
->src
[0].is_zero()) {
2260 inst
->opcode
= BRW_OPCODE_MUL
;
2261 inst
->src
[0] = inst
->src
[2];
2262 inst
->src
[2] = reg_undef
;
2264 } else if (inst
->src
[1].is_one()) {
2265 inst
->opcode
= BRW_OPCODE_ADD
;
2266 inst
->src
[1] = inst
->src
[2];
2267 inst
->src
[2] = reg_undef
;
2269 } else if (inst
->src
[2].is_one()) {
2270 inst
->opcode
= BRW_OPCODE_ADD
;
2271 inst
->src
[2] = reg_undef
;
2273 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2274 inst
->opcode
= BRW_OPCODE_ADD
;
2275 inst
->src
[1].f
*= inst
->src
[2].f
;
2276 inst
->src
[2] = reg_undef
;
2280 case SHADER_OPCODE_BROADCAST
:
2281 if (is_uniform(inst
->src
[0])) {
2282 inst
->opcode
= BRW_OPCODE_MOV
;
2284 inst
->force_writemask_all
= true;
2286 } else if (inst
->src
[1].file
== IMM
) {
2287 inst
->opcode
= BRW_OPCODE_MOV
;
2288 inst
->src
[0] = component(inst
->src
[0],
2291 inst
->force_writemask_all
= true;
2300 /* Swap if src[0] is immediate. */
2301 if (progress
&& inst
->is_commutative()) {
2302 if (inst
->src
[0].file
== IMM
) {
2303 fs_reg tmp
= inst
->src
[1];
2304 inst
->src
[1] = inst
->src
[0];
2313 * Optimize sample messages that have constant zero values for the trailing
2314 * texture coordinates. We can just reduce the message length for these
2315 * instructions instead of reserving a register for it. Trailing parameters
2316 * that aren't sent default to zero anyway. This will cause the dead code
2317 * eliminator to remove the MOV instruction that would otherwise be emitted to
2318 * set up the zero value.
2321 fs_visitor::opt_zero_samples()
2323 /* Gen4 infers the texturing opcode based on the message length so we can't
2326 if (devinfo
->gen
< 5)
2329 bool progress
= false;
2331 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2332 if (!inst
->is_tex())
2335 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2337 if (load_payload
->is_head_sentinel() ||
2338 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2341 /* We don't want to remove the message header or the first parameter.
2342 * Removing the first parameter is not allowed, see the Haswell PRM
2343 * volume 7, page 149:
2345 * "Parameter 0 is required except for the sampleinfo message, which
2346 * has no parameter 0"
2348 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2349 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2350 (inst
->exec_size
/ 8) +
2351 inst
->header_size
- 1].is_zero()) {
2352 inst
->mlen
-= inst
->exec_size
/ 8;
2358 invalidate_live_intervals();
2364 * Optimize sample messages which are followed by the final RT write.
2366 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2367 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2368 * final texturing results copied to the framebuffer write payload and modify
2369 * them to write to the framebuffer directly.
2372 fs_visitor::opt_sampler_eot()
2374 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2376 if (stage
!= MESA_SHADER_FRAGMENT
)
2379 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2382 /* FINISHME: It should be possible to implement this optimization when there
2383 * are multiple drawbuffers.
2385 if (key
->nr_color_regions
!= 1)
2388 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2389 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2390 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2391 assert(fb_write
->eot
);
2392 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2394 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2396 /* There wasn't one; nothing to do. */
2397 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2400 /* 3D Sampler » Messages » Message Format
2402 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2403 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2405 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2406 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2407 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2408 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2409 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2412 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2413 * It's very likely to be the previous instruction.
2415 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2416 if (load_payload
->is_head_sentinel() ||
2417 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2420 assert(!tex_inst
->eot
); /* We can't get here twice */
2421 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2423 const fs_builder
ibld(this, block
, tex_inst
);
2425 tex_inst
->offset
|= fb_write
->target
<< 24;
2426 tex_inst
->eot
= true;
2427 tex_inst
->dst
= ibld
.null_reg_ud();
2428 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2430 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2431 * to create a new LOAD_PAYLOAD command with the same sources and a space
2432 * saved for the header. Using a new destination register not only makes sure
2433 * we have enough space, but it will make sure the dead code eliminator kills
2434 * the instruction that this will replace.
2436 if (tex_inst
->header_size
!= 0) {
2437 invalidate_live_intervals();
2441 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2442 load_payload
->sources
+ 1);
2443 fs_reg
*new_sources
=
2444 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2446 new_sources
[0] = fs_reg();
2447 for (int i
= 0; i
< load_payload
->sources
; i
++)
2448 new_sources
[i
+1] = load_payload
->src
[i
];
2450 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2451 * requires a lot of information about the sources to appropriately figure
2452 * out the number of registers needed to be used. Given this stage in our
2453 * optimization, we may not have the appropriate GRFs required by
2454 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2455 * manually emit the instruction.
2457 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2458 load_payload
->exec_size
,
2461 load_payload
->sources
+ 1);
2463 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2464 new_load_payload
->header_size
= 1;
2466 tex_inst
->header_size
= 1;
2467 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2468 tex_inst
->src
[0] = send_header
;
2470 invalidate_live_intervals();
2475 fs_visitor::opt_register_renaming()
2477 bool progress
= false;
2480 int remap
[alloc
.count
];
2481 memset(remap
, -1, sizeof(int) * alloc
.count
);
2483 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2484 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2486 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2487 inst
->opcode
== BRW_OPCODE_WHILE
) {
2491 /* Rewrite instruction sources. */
2492 for (int i
= 0; i
< inst
->sources
; i
++) {
2493 if (inst
->src
[i
].file
== VGRF
&&
2494 remap
[inst
->src
[i
].nr
] != -1 &&
2495 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2496 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2501 const int dst
= inst
->dst
.nr
;
2504 inst
->dst
.file
== VGRF
&&
2505 alloc
.sizes
[inst
->dst
.nr
] == inst
->exec_size
/ 8 &&
2506 !inst
->is_partial_write()) {
2507 if (remap
[dst
] == -1) {
2510 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2511 inst
->dst
.nr
= remap
[dst
];
2514 } else if (inst
->dst
.file
== VGRF
&&
2516 remap
[dst
] != dst
) {
2517 inst
->dst
.nr
= remap
[dst
];
2523 invalidate_live_intervals();
2525 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2526 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2527 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2536 * Remove redundant or useless discard jumps.
2538 * For example, we can eliminate jumps in the following sequence:
2540 * discard-jump (redundant with the next jump)
2541 * discard-jump (useless; jumps to the next instruction)
2545 fs_visitor::opt_redundant_discard_jumps()
2547 bool progress
= false;
2549 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2551 fs_inst
*placeholder_halt
= NULL
;
2552 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2553 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2554 placeholder_halt
= inst
;
2559 if (!placeholder_halt
)
2562 /* Delete any HALTs immediately before the placeholder halt. */
2563 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2564 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2565 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2566 prev
->remove(last_bblock
);
2571 invalidate_live_intervals();
2577 fs_visitor::compute_to_mrf()
2579 bool progress
= false;
2582 /* No MRFs on Gen >= 7. */
2583 if (devinfo
->gen
>= 7)
2586 calculate_live_intervals();
2588 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2592 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2593 inst
->is_partial_write() ||
2594 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2595 inst
->dst
.type
!= inst
->src
[0].type
||
2596 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2597 !inst
->src
[0].is_contiguous() ||
2598 inst
->src
[0].subreg_offset
)
2601 /* Work out which hardware MRF registers are written by this
2604 int mrf_low
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2606 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2607 mrf_high
= mrf_low
+ 4;
2608 } else if (inst
->exec_size
== 16) {
2609 mrf_high
= mrf_low
+ 1;
2614 /* Can't compute-to-MRF this GRF if someone else was going to
2617 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2620 /* Found a move of a GRF to a MRF. Let's see if we can go
2621 * rewrite the thing that made this GRF to write into the MRF.
2623 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2624 if (scan_inst
->dst
.file
== VGRF
&&
2625 scan_inst
->dst
.nr
== inst
->src
[0].nr
) {
2626 /* Found the last thing to write our reg we want to turn
2627 * into a compute-to-MRF.
2630 /* If this one instruction didn't populate all the
2631 * channels, bail. We might be able to rewrite everything
2632 * that writes that reg, but it would require smarter
2633 * tracking to delay the rewriting until complete success.
2635 if (scan_inst
->is_partial_write())
2638 /* Things returning more than one register would need us to
2639 * understand coalescing out more than one MOV at a time.
2641 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2644 /* SEND instructions can't have MRF as a destination. */
2645 if (scan_inst
->mlen
)
2648 if (devinfo
->gen
== 6) {
2649 /* gen6 math instructions must have the destination be
2650 * GRF, so no compute-to-MRF for them.
2652 if (scan_inst
->is_math()) {
2657 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2658 /* Found the creator of our MRF's source value. */
2659 scan_inst
->dst
.file
= MRF
;
2660 scan_inst
->dst
.nr
= inst
->dst
.nr
;
2661 scan_inst
->saturate
|= inst
->saturate
;
2662 inst
->remove(block
);
2668 /* We don't handle control flow here. Most computation of
2669 * values that end up in MRFs are shortly before the MRF
2672 if (block
->start() == scan_inst
)
2675 /* You can't read from an MRF, so if someone else reads our
2676 * MRF's source GRF that we wanted to rewrite, that stops us.
2678 bool interfered
= false;
2679 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2680 if (scan_inst
->src
[i
].file
== VGRF
&&
2681 scan_inst
->src
[i
].nr
== inst
->src
[0].nr
&&
2682 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2689 if (scan_inst
->dst
.file
== MRF
) {
2690 /* If somebody else writes our MRF here, we can't
2691 * compute-to-MRF before that.
2693 int scan_mrf_low
= scan_inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2696 if (scan_inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2697 scan_mrf_high
= scan_mrf_low
+ 4;
2698 } else if (scan_inst
->exec_size
== 16) {
2699 scan_mrf_high
= scan_mrf_low
+ 1;
2701 scan_mrf_high
= scan_mrf_low
;
2704 if (mrf_low
== scan_mrf_low
||
2705 mrf_low
== scan_mrf_high
||
2706 mrf_high
== scan_mrf_low
||
2707 mrf_high
== scan_mrf_high
) {
2712 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2713 /* Found a SEND instruction, which means that there are
2714 * live values in MRFs from base_mrf to base_mrf +
2715 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2718 if (mrf_low
>= scan_inst
->base_mrf
&&
2719 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2722 if (mrf_high
>= scan_inst
->base_mrf
&&
2723 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2731 invalidate_live_intervals();
2737 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2738 * flow. We could probably do better here with some form of divergence
2742 fs_visitor::eliminate_find_live_channel()
2744 bool progress
= false;
2747 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2748 switch (inst
->opcode
) {
2754 case BRW_OPCODE_ENDIF
:
2755 case BRW_OPCODE_WHILE
:
2759 case FS_OPCODE_DISCARD_JUMP
:
2760 /* This can potentially make control flow non-uniform until the end
2765 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2767 inst
->opcode
= BRW_OPCODE_MOV
;
2768 inst
->src
[0] = brw_imm_ud(0u);
2770 inst
->force_writemask_all
= true;
2784 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2785 * instructions to FS_OPCODE_REP_FB_WRITE.
2788 fs_visitor::emit_repclear_shader()
2790 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2792 int color_mrf
= base_mrf
+ 2;
2796 mov
= bld
.exec_all().group(4, 0)
2797 .MOV(brw_message_reg(color_mrf
),
2798 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2800 struct brw_reg reg
=
2801 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2802 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
2803 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2805 mov
= bld
.exec_all().group(4, 0)
2806 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2810 if (key
->nr_color_regions
== 1) {
2811 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2812 write
->saturate
= key
->clamp_fragment_color
;
2813 write
->base_mrf
= color_mrf
;
2815 write
->header_size
= 0;
2818 assume(key
->nr_color_regions
> 0);
2819 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2820 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2821 write
->saturate
= key
->clamp_fragment_color
;
2822 write
->base_mrf
= base_mrf
;
2824 write
->header_size
= 2;
2832 assign_constant_locations();
2833 assign_curb_setup();
2835 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2837 assert(mov
->src
[0].file
== FIXED_GRF
);
2838 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2843 * Walks through basic blocks, looking for repeated MRF writes and
2844 * removing the later ones.
2847 fs_visitor::remove_duplicate_mrf_writes()
2849 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2850 bool progress
= false;
2852 /* Need to update the MRF tracking for compressed instructions. */
2853 if (dispatch_width
== 16)
2856 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2858 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2859 if (inst
->is_control_flow()) {
2860 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2863 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2864 inst
->dst
.file
== MRF
) {
2865 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2866 if (prev_inst
&& inst
->equals(prev_inst
)) {
2867 inst
->remove(block
);
2873 /* Clear out the last-write records for MRFs that were overwritten. */
2874 if (inst
->dst
.file
== MRF
) {
2875 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2878 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2879 /* Found a SEND instruction, which will include two or fewer
2880 * implied MRF writes. We could do better here.
2882 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2883 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2887 /* Clear out any MRF move records whose sources got overwritten. */
2888 if (inst
->dst
.file
== VGRF
) {
2889 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2890 if (last_mrf_move
[i
] &&
2891 last_mrf_move
[i
]->src
[0].nr
== inst
->dst
.nr
) {
2892 last_mrf_move
[i
] = NULL
;
2897 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2898 inst
->dst
.file
== MRF
&&
2899 inst
->src
[0].file
== VGRF
&&
2900 !inst
->is_partial_write()) {
2901 last_mrf_move
[inst
->dst
.nr
] = inst
;
2906 invalidate_live_intervals();
2912 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2914 /* Clear the flag for registers that actually got read (as expected). */
2915 for (int i
= 0; i
< inst
->sources
; i
++) {
2917 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
2918 grf
= inst
->src
[i
].nr
;
2923 if (grf
>= first_grf
&&
2924 grf
< first_grf
+ grf_len
) {
2925 deps
[grf
- first_grf
] = false;
2926 if (inst
->exec_size
== 16)
2927 deps
[grf
- first_grf
+ 1] = false;
2933 * Implements this workaround for the original 965:
2935 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2936 * check for post destination dependencies on this instruction, software
2937 * must ensure that there is no destination hazard for the case of ‘write
2938 * followed by a posted write’ shown in the following example.
2941 * 2. send r3.xy <rest of send instruction>
2944 * Due to no post-destination dependency check on the ‘send’, the above
2945 * code sequence could have two instructions (1 and 2) in flight at the
2946 * same time that both consider ‘r3’ as the target of their final writes.
2949 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2952 int write_len
= inst
->regs_written
;
2953 int first_write_grf
= inst
->dst
.nr
;
2954 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2955 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2957 memset(needs_dep
, false, sizeof(needs_dep
));
2958 memset(needs_dep
, true, write_len
);
2960 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2962 /* Walk backwards looking for writes to registers we're writing which
2963 * aren't read since being written. If we hit the start of the program,
2964 * we assume that there are no outstanding dependencies on entry to the
2967 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2968 /* If we hit control flow, assume that there *are* outstanding
2969 * dependencies, and force their cleanup before our instruction.
2971 if (block
->start() == scan_inst
) {
2972 for (int i
= 0; i
< write_len
; i
++) {
2974 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
2975 first_write_grf
+ i
);
2980 /* We insert our reads as late as possible on the assumption that any
2981 * instruction but a MOV that might have left us an outstanding
2982 * dependency has more latency than a MOV.
2984 if (scan_inst
->dst
.file
== VGRF
) {
2985 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2986 int reg
= scan_inst
->dst
.nr
+ i
;
2988 if (reg
>= first_write_grf
&&
2989 reg
< first_write_grf
+ write_len
&&
2990 needs_dep
[reg
- first_write_grf
]) {
2991 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
2992 needs_dep
[reg
- first_write_grf
] = false;
2993 if (scan_inst
->exec_size
== 16)
2994 needs_dep
[reg
- first_write_grf
+ 1] = false;
2999 /* Clear the flag for registers that actually got read (as expected). */
3000 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3002 /* Continue the loop only if we haven't resolved all the dependencies */
3004 for (i
= 0; i
< write_len
; i
++) {
3014 * Implements this workaround for the original 965:
3016 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3017 * used as a destination register until after it has been sourced by an
3018 * instruction with a different destination register.
3021 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3023 int write_len
= inst
->regs_written
;
3024 int first_write_grf
= inst
->dst
.nr
;
3025 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3026 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3028 memset(needs_dep
, false, sizeof(needs_dep
));
3029 memset(needs_dep
, true, write_len
);
3030 /* Walk forwards looking for writes to registers we're writing which aren't
3031 * read before being written.
3033 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3034 /* If we hit control flow, force resolve all remaining dependencies. */
3035 if (block
->end() == scan_inst
) {
3036 for (int i
= 0; i
< write_len
; i
++) {
3038 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3039 first_write_grf
+ i
);
3044 /* Clear the flag for registers that actually got read (as expected). */
3045 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3047 /* We insert our reads as late as possible since they're reading the
3048 * result of a SEND, which has massive latency.
3050 if (scan_inst
->dst
.file
== VGRF
&&
3051 scan_inst
->dst
.nr
>= first_write_grf
&&
3052 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3053 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3054 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3056 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3059 /* Continue the loop only if we haven't resolved all the dependencies */
3061 for (i
= 0; i
< write_len
; i
++) {
3071 fs_visitor::insert_gen4_send_dependency_workarounds()
3073 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3076 bool progress
= false;
3078 /* Note that we're done with register allocation, so GRF fs_regs always
3079 * have a .reg_offset of 0.
3082 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3083 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3084 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3085 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3091 invalidate_live_intervals();
3095 * Turns the generic expression-style uniform pull constant load instruction
3096 * into a hardware-specific series of instructions for loading a pull
3099 * The expression style allows the CSE pass before this to optimize out
3100 * repeated loads from the same offset, and gives the pre-register-allocation
3101 * scheduling full flexibility, while the conversion to native instructions
3102 * allows the post-register-allocation scheduler the best information
3105 * Note that execution masking for setting up pull constant loads is special:
3106 * the channels that need to be written are unrelated to the current execution
3107 * mask, since a later instruction will use one of the result channels as a
3108 * source operand for all 8 or 16 of its channels.
3111 fs_visitor::lower_uniform_pull_constant_loads()
3113 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3114 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3117 if (devinfo
->gen
>= 7) {
3118 /* The offset arg is a vec4-aligned immediate byte offset. */
3119 fs_reg const_offset_reg
= inst
->src
[1];
3120 assert(const_offset_reg
.file
== IMM
&&
3121 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3122 assert(const_offset_reg
.ud
% 16 == 0);
3124 fs_reg payload
, offset
;
3125 if (devinfo
->gen
>= 9) {
3126 /* We have to use a message header on Skylake to get SIMD4x2
3127 * mode. Reserve space for the register.
3129 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3130 offset
.reg_offset
++;
3133 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3137 /* This is actually going to be a MOV, but since only the first dword
3138 * is accessed, we have a special opcode to do just that one. Note
3139 * that this needs to be an operation that will be considered a def
3140 * by live variable analysis, or register allocation will explode.
3142 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3143 8, offset
, const_offset_reg
);
3144 setup
->force_writemask_all
= true;
3146 setup
->ir
= inst
->ir
;
3147 setup
->annotation
= inst
->annotation
;
3148 inst
->insert_before(block
, setup
);
3150 /* Similarly, this will only populate the first 4 channels of the
3151 * result register (since we only use smear values from 0-3), but we
3152 * don't tell the optimizer.
3154 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3155 inst
->src
[1] = payload
;
3156 inst
->base_mrf
= -1;
3158 invalidate_live_intervals();
3160 /* Before register allocation, we didn't tell the scheduler about the
3161 * MRF we use. We know it's safe to use this MRF because nothing
3162 * else does except for register spill/unspill, which generates and
3163 * uses its MRF within a single IR instruction.
3165 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3172 fs_visitor::lower_load_payload()
3174 bool progress
= false;
3176 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3177 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3180 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3181 assert(inst
->saturate
== false);
3182 fs_reg dst
= inst
->dst
;
3184 /* Get rid of COMPR4. We'll add it back in if we need it */
3185 if (dst
.file
== MRF
)
3186 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3188 const fs_builder
ibld(this, block
, inst
);
3189 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3191 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3192 if (inst
->src
[i
].file
!= BAD_FILE
) {
3193 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3194 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3195 hbld
.MOV(mov_dst
, mov_src
);
3197 dst
= offset(dst
, hbld
, 1);
3200 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3201 inst
->exec_size
> 8) {
3202 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3203 * a straightforward copy. Instead, the result of the
3204 * LOAD_PAYLOAD is treated as interleaved and the first four
3205 * non-header sources are unpacked as:
3216 * This is used for gen <= 5 fb writes.
3218 assert(inst
->exec_size
== 16);
3219 assert(inst
->header_size
+ 4 <= inst
->sources
);
3220 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3221 if (inst
->src
[i
].file
!= BAD_FILE
) {
3222 if (devinfo
->has_compr4
) {
3223 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3224 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3225 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3227 /* Platform doesn't have COMPR4. We have to fake it */
3228 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3229 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3231 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3238 /* The loop above only ever incremented us through the first set
3239 * of 4 registers. However, thanks to the magic of COMPR4, we
3240 * actually wrote to the first 8 registers, so we need to take
3241 * that into account now.
3245 /* The COMPR4 code took care of the first 4 sources. We'll let
3246 * the regular path handle any remaining sources. Yes, we are
3247 * modifying the instruction but we're about to delete it so
3248 * this really doesn't hurt anything.
3250 inst
->header_size
+= 4;
3253 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3254 if (inst
->src
[i
].file
!= BAD_FILE
)
3255 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3256 dst
= offset(dst
, ibld
, 1);
3259 inst
->remove(block
);
3264 invalidate_live_intervals();
3270 fs_visitor::lower_integer_multiplication()
3272 bool progress
= false;
3274 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3275 const fs_builder
ibld(this, block
, inst
);
3277 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3278 if (inst
->dst
.is_accumulator() ||
3279 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3280 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3283 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3284 * operation directly, but CHV/BXT cannot.
3286 if (devinfo
->gen
>= 8 &&
3287 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3290 if (inst
->src
[1].file
== IMM
&&
3291 inst
->src
[1].ud
< (1 << 16)) {
3292 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3293 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3296 * If multiplying by an immediate value that fits in 16-bits, do a
3297 * single MUL instruction with that value in the proper location.
3299 if (devinfo
->gen
< 7) {
3300 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3302 ibld
.MOV(imm
, inst
->src
[1]);
3303 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3305 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3308 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3309 * do 32-bit integer multiplication in one instruction, but instead
3310 * must do a sequence (which actually calculates a 64-bit result):
3312 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3313 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3314 * mov(8) g2<1>D acc0<8,8,1>D
3316 * But on Gen > 6, the ability to use second accumulator register
3317 * (acc1) for non-float data types was removed, preventing a simple
3318 * implementation in SIMD16. A 16-channel result can be calculated by
3319 * executing the three instructions twice in SIMD8, once with quarter
3320 * control of 1Q for the first eight channels and again with 2Q for
3321 * the second eight channels.
3323 * Which accumulator register is implicitly accessed (by AccWrEnable
3324 * for instance) is determined by the quarter control. Unfortunately
3325 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3326 * implicit accumulator access by an instruction with 2Q will access
3327 * acc1 regardless of whether the data type is usable in acc1.
3329 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3330 * integer data types.
3332 * Since we only want the low 32-bits of the result, we can do two
3333 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3334 * adjust the high result and add them (like the mach is doing):
3336 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3337 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3338 * shl(8) g9<1>D g8<8,8,1>D 16D
3339 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3341 * We avoid the shl instruction by realizing that we only want to add
3342 * the low 16-bits of the "high" result to the high 16-bits of the
3343 * "low" result and using proper regioning on the add:
3345 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3346 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3347 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3349 * Since it does not use the (single) accumulator register, we can
3350 * schedule multi-component multiplications much better.
3353 fs_reg orig_dst
= inst
->dst
;
3354 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3355 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3358 fs_reg low
= inst
->dst
;
3359 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3362 if (devinfo
->gen
>= 7) {
3363 fs_reg src1_0_w
= inst
->src
[1];
3364 fs_reg src1_1_w
= inst
->src
[1];
3366 if (inst
->src
[1].file
== IMM
) {
3367 src1_0_w
.ud
&= 0xffff;
3370 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3371 if (src1_0_w
.stride
!= 0) {
3372 assert(src1_0_w
.stride
== 1);
3373 src1_0_w
.stride
= 2;
3376 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3377 if (src1_1_w
.stride
!= 0) {
3378 assert(src1_1_w
.stride
== 1);
3379 src1_1_w
.stride
= 2;
3381 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3383 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3384 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3386 fs_reg src0_0_w
= inst
->src
[0];
3387 fs_reg src0_1_w
= inst
->src
[0];
3389 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3390 if (src0_0_w
.stride
!= 0) {
3391 assert(src0_0_w
.stride
== 1);
3392 src0_0_w
.stride
= 2;
3395 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3396 if (src0_1_w
.stride
!= 0) {
3397 assert(src0_1_w
.stride
== 1);
3398 src0_1_w
.stride
= 2;
3400 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3402 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3403 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3406 fs_reg dst
= inst
->dst
;
3407 dst
.type
= BRW_REGISTER_TYPE_UW
;
3408 dst
.subreg_offset
= 2;
3411 high
.type
= BRW_REGISTER_TYPE_UW
;
3414 low
.type
= BRW_REGISTER_TYPE_UW
;
3415 low
.subreg_offset
= 2;
3418 ibld
.ADD(dst
, low
, high
);
3420 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3421 set_condmod(inst
->conditional_mod
,
3422 ibld
.MOV(orig_dst
, inst
->dst
));
3426 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3427 /* Should have been lowered to 8-wide. */
3428 assert(inst
->exec_size
<= 8);
3429 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3431 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3432 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3434 if (devinfo
->gen
>= 8) {
3435 /* Until Gen8, integer multiplies read 32-bits from one source,
3436 * and 16-bits from the other, and relying on the MACH instruction
3437 * to generate the high bits of the result.
3439 * On Gen8, the multiply instruction does a full 32x32-bit
3440 * multiply, but in order to do a 64-bit multiply we can simulate
3441 * the previous behavior and then use a MACH instruction.
3443 * FINISHME: Don't use source modifiers on src1.
3445 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3446 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3447 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3448 mul
->src
[1].stride
*= 2;
3450 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3451 inst
->force_sechalf
) {
3452 /* Among other things the quarter control bits influence which
3453 * accumulator register is used by the hardware for instructions
3454 * that access the accumulator implicitly (e.g. MACH). A
3455 * second-half instruction would normally map to acc1, which
3456 * doesn't exist on Gen7 and up (the hardware does emulate it for
3457 * floating-point instructions *only* by taking advantage of the
3458 * extra precision of acc0 not normally used for floating point
3461 * HSW and up are careful enough not to try to access an
3462 * accumulator register that doesn't exist, but on earlier Gen7
3463 * hardware we need to make sure that the quarter control bits are
3464 * zero to avoid non-deterministic behaviour and emit an extra MOV
3465 * to get the result masked correctly according to the current
3468 mach
->force_sechalf
= false;
3469 mach
->force_writemask_all
= true;
3470 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3471 ibld
.MOV(inst
->dst
, mach
->dst
);
3477 inst
->remove(block
);
3482 invalidate_live_intervals();
3488 fs_visitor::lower_minmax()
3490 assert(devinfo
->gen
< 6);
3492 bool progress
= false;
3494 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3495 const fs_builder
ibld(this, block
, inst
);
3497 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3498 inst
->predicate
== BRW_PREDICATE_NONE
) {
3499 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3500 * the original SEL.L/GE instruction
3502 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3503 inst
->conditional_mod
);
3504 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3505 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3512 invalidate_live_intervals();
3518 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3519 fs_reg
*dst
, fs_reg color
, unsigned components
)
3521 if (key
->clamp_fragment_color
) {
3522 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3523 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3525 for (unsigned i
= 0; i
< components
; i
++)
3527 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3532 for (unsigned i
= 0; i
< components
; i
++)
3533 dst
[i
] = offset(color
, bld
, i
);
3537 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3538 const brw_wm_prog_data
*prog_data
,
3539 const brw_wm_prog_key
*key
,
3540 const fs_visitor::thread_payload
&payload
)
3542 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3543 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3544 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3545 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3546 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3547 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3548 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3549 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3550 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3551 const unsigned components
=
3552 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3554 /* We can potentially have a message length of up to 15, so we have to set
3555 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3558 int header_size
= 2, payload_header_size
;
3559 unsigned length
= 0;
3561 /* From the Sandy Bridge PRM, volume 4, page 198:
3563 * "Dispatched Pixel Enables. One bit per pixel indicating
3564 * which pixels were originally enabled when the thread was
3565 * dispatched. This field is only required for the end-of-
3566 * thread message and on all dual-source messages."
3568 if (devinfo
->gen
>= 6 &&
3569 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3570 color1
.file
== BAD_FILE
&&
3571 key
->nr_color_regions
== 1) {
3575 if (header_size
!= 0) {
3576 assert(header_size
== 2);
3577 /* Allocate 2 registers for a header */
3581 if (payload
.aa_dest_stencil_reg
) {
3582 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3583 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3584 .MOV(sources
[length
],
3585 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3589 if (prog_data
->uses_omask
) {
3590 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3591 BRW_REGISTER_TYPE_UD
);
3593 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3594 * relevant. Since it's unsigned single words one vgrf is always
3595 * 16-wide, but only the lower or higher 8 channels will be used by the
3596 * hardware when doing a SIMD8 write depending on whether we have
3597 * selected the subspans for the first or second half respectively.
3599 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3600 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3601 sample_mask
.stride
*= 2;
3603 bld
.exec_all().annotate("FB write oMask")
3604 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3605 inst
->force_sechalf
),
3610 payload_header_size
= length
;
3612 if (src0_alpha
.file
!= BAD_FILE
) {
3613 /* FIXME: This is being passed at the wrong location in the payload and
3614 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3615 * It's supposed to be immediately before oMask but there seems to be no
3616 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3617 * requires header sources to form a contiguous segment at the beginning
3618 * of the message and src0_alpha has per-channel semantics.
3620 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3624 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3627 if (color1
.file
!= BAD_FILE
) {
3628 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3632 if (src_depth
.file
!= BAD_FILE
) {
3633 sources
[length
] = src_depth
;
3637 if (dst_depth
.file
!= BAD_FILE
) {
3638 sources
[length
] = dst_depth
;
3642 if (src_stencil
.file
!= BAD_FILE
) {
3643 assert(devinfo
->gen
>= 9);
3644 assert(bld
.dispatch_width() != 16);
3646 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3647 * available on gen9+. As such it's impossible to have both enabled at the
3648 * same time and therefore length cannot overrun the array.
3650 assert(length
< 15);
3652 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3653 bld
.exec_all().annotate("FB write OS")
3654 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3655 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3660 if (devinfo
->gen
>= 7) {
3661 /* Send from the GRF */
3662 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3663 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3664 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3665 load
->dst
= payload
;
3667 inst
->src
[0] = payload
;
3668 inst
->resize_sources(1);
3669 inst
->base_mrf
= -1;
3671 /* Send from the MRF */
3672 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3673 sources
, length
, payload_header_size
);
3675 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3676 * will do this for us if we just give it a COMPR4 destination.
3678 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3679 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3681 inst
->resize_sources(0);
3685 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3686 inst
->mlen
= load
->regs_written
;
3687 inst
->header_size
= header_size
;
3691 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3692 const fs_reg
&coordinate
,
3693 const fs_reg
&shadow_c
,
3694 const fs_reg
&lod
, const fs_reg
&lod2
,
3695 const fs_reg
&surface
,
3696 const fs_reg
&sampler
,
3697 unsigned coord_components
,
3698 unsigned grad_components
)
3700 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3701 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3702 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3703 fs_reg msg_end
= msg_begin
;
3706 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3708 for (unsigned i
= 0; i
< coord_components
; i
++)
3709 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3710 offset(coordinate
, bld
, i
));
3712 msg_end
= offset(msg_end
, bld
, coord_components
);
3714 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3715 * require all three components to be present and zero if they are unused.
3717 if (coord_components
> 0 &&
3718 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3719 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3720 for (unsigned i
= coord_components
; i
< 3; i
++)
3721 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3723 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3726 if (op
== SHADER_OPCODE_TXD
) {
3727 /* TXD unsupported in SIMD16 mode. */
3728 assert(bld
.dispatch_width() == 8);
3730 /* the slots for u and v are always present, but r is optional */
3731 if (coord_components
< 2)
3732 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3735 * dPdx = dudx, dvdx, drdx
3736 * dPdy = dudy, dvdy, drdy
3738 * 1-arg: Does not exist.
3740 * 2-arg: dudx dvdx dudy dvdy
3741 * dPdx.x dPdx.y dPdy.x dPdy.y
3744 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3745 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3746 * m5 m6 m7 m8 m9 m10
3748 for (unsigned i
= 0; i
< grad_components
; i
++)
3749 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3751 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3753 for (unsigned i
= 0; i
< grad_components
; i
++)
3754 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3756 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3760 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3761 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3763 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3764 bld
.dispatch_width() == 16);
3766 const brw_reg_type type
=
3767 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3768 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3769 bld
.MOV(retype(msg_end
, type
), lod
);
3770 msg_end
= offset(msg_end
, bld
, 1);
3773 if (shadow_c
.file
!= BAD_FILE
) {
3774 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3775 /* There's no plain shadow compare message, so we use shadow
3776 * compare with a bias of 0.0.
3778 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3779 msg_end
= offset(msg_end
, bld
, 1);
3782 bld
.MOV(msg_end
, shadow_c
);
3783 msg_end
= offset(msg_end
, bld
, 1);
3787 inst
->src
[0] = reg_undef
;
3788 inst
->src
[1] = surface
;
3789 inst
->src
[2] = sampler
;
3790 inst
->resize_sources(3);
3791 inst
->base_mrf
= msg_begin
.nr
;
3792 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3793 inst
->header_size
= 1;
3797 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3799 const fs_reg
&shadow_c
,
3800 fs_reg lod
, fs_reg lod2
,
3801 const fs_reg
&sample_index
,
3802 const fs_reg
&surface
,
3803 const fs_reg
&sampler
,
3804 const fs_reg
&offset_value
,
3805 unsigned coord_components
,
3806 unsigned grad_components
)
3808 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3809 fs_reg msg_coords
= message
;
3810 unsigned header_size
= 0;
3812 if (offset_value
.file
!= BAD_FILE
) {
3813 /* The offsets set up by the visitor are in the m1 header, so we can't
3820 for (unsigned i
= 0; i
< coord_components
; i
++) {
3821 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3822 coordinate
= offset(coordinate
, bld
, 1);
3824 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3825 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3827 if (shadow_c
.file
!= BAD_FILE
) {
3828 fs_reg msg_shadow
= msg_lod
;
3829 bld
.MOV(msg_shadow
, shadow_c
);
3830 msg_lod
= offset(msg_shadow
, bld
, 1);
3835 case SHADER_OPCODE_TXL
:
3837 bld
.MOV(msg_lod
, lod
);
3838 msg_end
= offset(msg_lod
, bld
, 1);
3840 case SHADER_OPCODE_TXD
:
3843 * dPdx = dudx, dvdx, drdx
3844 * dPdy = dudy, dvdy, drdy
3846 * Load up these values:
3847 * - dudx dudy dvdx dvdy drdx drdy
3848 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3851 for (unsigned i
= 0; i
< grad_components
; i
++) {
3852 bld
.MOV(msg_end
, lod
);
3853 lod
= offset(lod
, bld
, 1);
3854 msg_end
= offset(msg_end
, bld
, 1);
3856 bld
.MOV(msg_end
, lod2
);
3857 lod2
= offset(lod2
, bld
, 1);
3858 msg_end
= offset(msg_end
, bld
, 1);
3861 case SHADER_OPCODE_TXS
:
3862 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3863 bld
.MOV(msg_lod
, lod
);
3864 msg_end
= offset(msg_lod
, bld
, 1);
3866 case SHADER_OPCODE_TXF
:
3867 msg_lod
= offset(msg_coords
, bld
, 3);
3868 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3869 msg_end
= offset(msg_lod
, bld
, 1);
3871 case SHADER_OPCODE_TXF_CMS
:
3872 msg_lod
= offset(msg_coords
, bld
, 3);
3874 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3876 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3877 msg_end
= offset(msg_lod
, bld
, 2);
3884 inst
->src
[0] = reg_undef
;
3885 inst
->src
[1] = surface
;
3886 inst
->src
[2] = sampler
;
3887 inst
->resize_sources(3);
3888 inst
->base_mrf
= message
.nr
;
3889 inst
->mlen
= msg_end
.nr
- message
.nr
;
3890 inst
->header_size
= header_size
;
3892 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3893 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3897 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3899 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3902 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
3906 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3908 const fs_reg
&shadow_c
,
3909 fs_reg lod
, fs_reg lod2
,
3910 const fs_reg
&sample_index
,
3912 const fs_reg
&surface
,
3913 const fs_reg
&sampler
,
3914 fs_reg offset_value
,
3915 unsigned coord_components
,
3916 unsigned grad_components
)
3918 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3919 int reg_width
= bld
.dispatch_width() / 8;
3920 unsigned header_size
= 0, length
= 0;
3921 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3922 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3923 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3925 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3926 offset_value
.file
!= BAD_FILE
||
3927 is_high_sampler(devinfo
, sampler
)) {
3928 /* For general texture offsets (no txf workaround), we need a header to
3929 * put them in. Note that we're only reserving space for it in the
3930 * message payload as it will be initialized implicitly by the
3933 * TG4 needs to place its channel select in the header, for interaction
3934 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3935 * larger sampler numbers we need to offset the Sampler State Pointer in
3939 sources
[0] = fs_reg();
3943 if (shadow_c
.file
!= BAD_FILE
) {
3944 bld
.MOV(sources
[length
], shadow_c
);
3948 bool coordinate_done
= false;
3950 /* The sampler can only meaningfully compute LOD for fragment shader
3951 * messages. For all other stages, we change the opcode to TXL and
3952 * hardcode the LOD to 0.
3954 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3955 op
== SHADER_OPCODE_TEX
) {
3956 op
= SHADER_OPCODE_TXL
;
3957 lod
= brw_imm_f(0.0f
);
3960 /* Set up the LOD info */
3963 case SHADER_OPCODE_TXL
:
3964 bld
.MOV(sources
[length
], lod
);
3967 case SHADER_OPCODE_TXD
:
3968 /* TXD should have been lowered in SIMD16 mode. */
3969 assert(bld
.dispatch_width() == 8);
3971 /* Load dPdx and the coordinate together:
3972 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3974 for (unsigned i
= 0; i
< coord_components
; i
++) {
3975 bld
.MOV(sources
[length
], coordinate
);
3976 coordinate
= offset(coordinate
, bld
, 1);
3979 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3980 * only derivatives for (u, v, r).
3982 if (i
< grad_components
) {
3983 bld
.MOV(sources
[length
], lod
);
3984 lod
= offset(lod
, bld
, 1);
3987 bld
.MOV(sources
[length
], lod2
);
3988 lod2
= offset(lod2
, bld
, 1);
3993 coordinate_done
= true;
3995 case SHADER_OPCODE_TXS
:
3996 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3999 case SHADER_OPCODE_TXF
:
4000 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4001 * On Gen9 they are u, v, lod, r
4003 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4004 coordinate
= offset(coordinate
, bld
, 1);
4007 if (devinfo
->gen
>= 9) {
4008 if (coord_components
>= 2) {
4009 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4010 coordinate
= offset(coordinate
, bld
, 1);
4015 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4018 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
4019 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4020 coordinate
= offset(coordinate
, bld
, 1);
4024 coordinate_done
= true;
4026 case SHADER_OPCODE_TXF_CMS
:
4027 case SHADER_OPCODE_TXF_CMS_W
:
4028 case SHADER_OPCODE_TXF_UMS
:
4029 case SHADER_OPCODE_TXF_MCS
:
4030 if (op
== SHADER_OPCODE_TXF_UMS
||
4031 op
== SHADER_OPCODE_TXF_CMS
||
4032 op
== SHADER_OPCODE_TXF_CMS_W
) {
4033 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4037 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4038 /* Data from the multisample control surface. */
4039 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4042 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4045 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4046 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4049 offset(mcs
, bld
, 1));
4054 /* There is no offsetting for this message; just copy in the integer
4055 * texture coordinates.
4057 for (unsigned i
= 0; i
< coord_components
; i
++) {
4058 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4059 coordinate
= offset(coordinate
, bld
, 1);
4063 coordinate_done
= true;
4065 case SHADER_OPCODE_TG4_OFFSET
:
4066 /* gather4_po_c should have been lowered in SIMD16 mode. */
4067 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
4069 /* More crazy intermixing */
4070 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
4071 bld
.MOV(sources
[length
], coordinate
);
4072 coordinate
= offset(coordinate
, bld
, 1);
4076 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
4077 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
4078 offset_value
= offset(offset_value
, bld
, 1);
4082 if (coord_components
== 3) { /* r if present */
4083 bld
.MOV(sources
[length
], coordinate
);
4084 coordinate
= offset(coordinate
, bld
, 1);
4088 coordinate_done
= true;
4094 /* Set up the coordinate (except for cases where it was done above) */
4095 if (!coordinate_done
) {
4096 for (unsigned i
= 0; i
< coord_components
; i
++) {
4097 bld
.MOV(sources
[length
], coordinate
);
4098 coordinate
= offset(coordinate
, bld
, 1);
4105 mlen
= length
* reg_width
- header_size
;
4107 mlen
= length
* reg_width
;
4109 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4110 BRW_REGISTER_TYPE_F
);
4111 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4113 /* Generate the SEND. */
4115 inst
->src
[0] = src_payload
;
4116 inst
->src
[1] = surface
;
4117 inst
->src
[2] = sampler
;
4118 inst
->resize_sources(3);
4119 inst
->base_mrf
= -1;
4121 inst
->header_size
= header_size
;
4123 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4124 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4128 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4130 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4131 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4132 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4133 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4134 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4135 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4136 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4137 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4138 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4139 const fs_reg
&offset_value
= inst
->src
[TEX_LOGICAL_SRC_OFFSET_VALUE
];
4140 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4141 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4142 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4143 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4145 if (devinfo
->gen
>= 7) {
4146 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4147 shadow_c
, lod
, lod2
, sample_index
,
4148 mcs
, surface
, sampler
, offset_value
,
4149 coord_components
, grad_components
);
4150 } else if (devinfo
->gen
>= 5) {
4151 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4152 shadow_c
, lod
, lod2
, sample_index
,
4153 surface
, sampler
, offset_value
,
4154 coord_components
, grad_components
);
4156 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4157 shadow_c
, lod
, lod2
,
4159 coord_components
, grad_components
);
4164 * Initialize the header present in some typed and untyped surface
4168 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4170 fs_builder ubld
= bld
.exec_all().group(8, 0);
4171 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4172 ubld
.MOV(dst
, brw_imm_d(0));
4173 ubld
.MOV(component(dst
, 7), sample_mask
);
4178 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4179 const fs_reg
&sample_mask
)
4181 /* Get the logical send arguments. */
4182 const fs_reg
&addr
= inst
->src
[0];
4183 const fs_reg
&src
= inst
->src
[1];
4184 const fs_reg
&surface
= inst
->src
[2];
4185 const UNUSED fs_reg
&dims
= inst
->src
[3];
4186 const fs_reg
&arg
= inst
->src
[4];
4188 /* Calculate the total number of components of the payload. */
4189 const unsigned addr_sz
= inst
->components_read(0);
4190 const unsigned src_sz
= inst
->components_read(1);
4191 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4192 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4194 /* Allocate space for the payload. */
4195 fs_reg
*const components
= new fs_reg
[sz
];
4196 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4199 /* Construct the payload. */
4201 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4203 for (unsigned i
= 0; i
< addr_sz
; i
++)
4204 components
[n
++] = offset(addr
, bld
, i
);
4206 for (unsigned i
= 0; i
< src_sz
; i
++)
4207 components
[n
++] = offset(src
, bld
, i
);
4209 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4211 /* Update the original instruction. */
4213 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4214 inst
->header_size
= header_sz
;
4216 inst
->src
[0] = payload
;
4217 inst
->src
[1] = surface
;
4219 inst
->resize_sources(3);
4221 delete[] components
;
4225 fs_visitor::lower_logical_sends()
4227 bool progress
= false;
4229 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4230 const fs_builder
ibld(this, block
, inst
);
4232 switch (inst
->opcode
) {
4233 case FS_OPCODE_FB_WRITE_LOGICAL
:
4234 assert(stage
== MESA_SHADER_FRAGMENT
);
4235 lower_fb_write_logical_send(ibld
, inst
,
4236 (const brw_wm_prog_data
*)prog_data
,
4237 (const brw_wm_prog_key
*)key
,
4241 case SHADER_OPCODE_TEX_LOGICAL
:
4242 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4245 case SHADER_OPCODE_TXD_LOGICAL
:
4246 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4249 case SHADER_OPCODE_TXF_LOGICAL
:
4250 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4253 case SHADER_OPCODE_TXL_LOGICAL
:
4254 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4257 case SHADER_OPCODE_TXS_LOGICAL
:
4258 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4261 case FS_OPCODE_TXB_LOGICAL
:
4262 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4265 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4266 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4269 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4270 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4273 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4274 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4277 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4278 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4281 case SHADER_OPCODE_LOD_LOGICAL
:
4282 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4285 case SHADER_OPCODE_TG4_LOGICAL
:
4286 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4289 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4290 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4293 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4294 lower_surface_logical_send(ibld
, inst
,
4295 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4299 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4300 lower_surface_logical_send(ibld
, inst
,
4301 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4302 ibld
.sample_mask_reg());
4305 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4306 lower_surface_logical_send(ibld
, inst
,
4307 SHADER_OPCODE_UNTYPED_ATOMIC
,
4308 ibld
.sample_mask_reg());
4311 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4312 lower_surface_logical_send(ibld
, inst
,
4313 SHADER_OPCODE_TYPED_SURFACE_READ
,
4317 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4318 lower_surface_logical_send(ibld
, inst
,
4319 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4320 ibld
.sample_mask_reg());
4323 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4324 lower_surface_logical_send(ibld
, inst
,
4325 SHADER_OPCODE_TYPED_ATOMIC
,
4326 ibld
.sample_mask_reg());
4337 invalidate_live_intervals();
4343 * Get the closest native SIMD width supported by the hardware for instruction
4344 * \p inst. The instruction will be left untouched by
4345 * fs_visitor::lower_simd_width() if the returned value is equal to the
4346 * original execution size.
4349 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4350 const fs_inst
*inst
)
4352 switch (inst
->opcode
) {
4353 case BRW_OPCODE_MOV
:
4354 case BRW_OPCODE_SEL
:
4355 case BRW_OPCODE_NOT
:
4356 case BRW_OPCODE_AND
:
4358 case BRW_OPCODE_XOR
:
4359 case BRW_OPCODE_SHR
:
4360 case BRW_OPCODE_SHL
:
4361 case BRW_OPCODE_ASR
:
4362 case BRW_OPCODE_CMP
:
4363 case BRW_OPCODE_CMPN
:
4364 case BRW_OPCODE_CSEL
:
4365 case BRW_OPCODE_F32TO16
:
4366 case BRW_OPCODE_F16TO32
:
4367 case BRW_OPCODE_BFREV
:
4368 case BRW_OPCODE_BFE
:
4369 case BRW_OPCODE_BFI1
:
4370 case BRW_OPCODE_BFI2
:
4371 case BRW_OPCODE_ADD
:
4372 case BRW_OPCODE_MUL
:
4373 case BRW_OPCODE_AVG
:
4374 case BRW_OPCODE_FRC
:
4375 case BRW_OPCODE_RNDU
:
4376 case BRW_OPCODE_RNDD
:
4377 case BRW_OPCODE_RNDE
:
4378 case BRW_OPCODE_RNDZ
:
4379 case BRW_OPCODE_LZD
:
4380 case BRW_OPCODE_FBH
:
4381 case BRW_OPCODE_FBL
:
4382 case BRW_OPCODE_CBIT
:
4383 case BRW_OPCODE_SAD2
:
4384 case BRW_OPCODE_MAD
:
4385 case BRW_OPCODE_LRP
:
4386 case SHADER_OPCODE_RCP
:
4387 case SHADER_OPCODE_RSQ
:
4388 case SHADER_OPCODE_SQRT
:
4389 case SHADER_OPCODE_EXP2
:
4390 case SHADER_OPCODE_LOG2
:
4391 case SHADER_OPCODE_POW
:
4392 case SHADER_OPCODE_INT_QUOTIENT
:
4393 case SHADER_OPCODE_INT_REMAINDER
:
4394 case SHADER_OPCODE_SIN
:
4395 case SHADER_OPCODE_COS
: {
4396 /* According to the PRMs:
4397 * "A. In Direct Addressing mode, a source cannot span more than 2
4398 * adjacent GRF registers.
4399 * B. A destination cannot span more than 2 adjacent GRF registers."
4401 * Look for the source or destination with the largest register region
4402 * which is the one that is going to limit the overal execution size of
4403 * the instruction due to this rule.
4405 unsigned reg_count
= inst
->regs_written
;
4407 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4408 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4410 /* Calculate the maximum execution size of the instruction based on the
4411 * factor by which it goes over the hardware limit of 2 GRFs.
4413 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4415 case SHADER_OPCODE_MULH
:
4416 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4417 * is 8-wide on Gen7+.
4419 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4421 case FS_OPCODE_FB_WRITE_LOGICAL
:
4422 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4425 assert(devinfo
->gen
!= 6 ||
4426 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4427 inst
->exec_size
== 8);
4428 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4429 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4430 8 : inst
->exec_size
);
4432 case SHADER_OPCODE_TXD_LOGICAL
:
4433 /* TXD is unsupported in SIMD16 mode. */
4436 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4437 /* gather4_po_c is unsupported in SIMD16 mode. */
4438 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4439 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4441 case SHADER_OPCODE_TXL_LOGICAL
:
4442 case FS_OPCODE_TXB_LOGICAL
: {
4443 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4444 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4445 * mode because the message exceeds the maximum length of 11.
4447 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4448 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4450 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4453 return inst
->exec_size
;
4455 case SHADER_OPCODE_TXF_LOGICAL
:
4456 case SHADER_OPCODE_TXS_LOGICAL
:
4457 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4458 * messages. Use SIMD16 instead.
4460 if (devinfo
->gen
== 4)
4463 return inst
->exec_size
;
4465 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4466 /* This opcode can take up to 6 arguments which means that in some
4467 * circumstances it can end up with a message that is too long in SIMD16
4470 const unsigned coord_components
=
4471 inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4472 /* First three arguments are the sample index and the two arguments for
4475 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4478 return inst
->exec_size
;
4481 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4482 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4483 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4486 case SHADER_OPCODE_MOV_INDIRECT
:
4487 /* Prior to Broadwell, we only have 8 address subregisters */
4488 return devinfo
->gen
< 8 ? 8 : MIN2(inst
->exec_size
, 16);
4491 return inst
->exec_size
;
4496 * The \p rows array of registers represents a \p num_rows by \p num_columns
4497 * matrix in row-major order, write it in column-major order into the register
4498 * passed as destination. \p stride gives the separation between matrix
4499 * elements in the input in fs_builder::dispatch_width() units.
4502 emit_transpose(const fs_builder
&bld
,
4503 const fs_reg
&dst
, const fs_reg
*rows
,
4504 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4506 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4508 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4509 for (unsigned j
= 0; j
< num_rows
; ++j
)
4510 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4513 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4515 delete[] components
;
4519 fs_visitor::lower_simd_width()
4521 bool progress
= false;
4523 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4524 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4526 if (lower_width
!= inst
->exec_size
) {
4527 /* Builder matching the original instruction. We may also need to
4528 * emit an instruction of width larger than the original, set the
4529 * execution size of the builder to the highest of both for now so
4530 * we're sure that both cases can be handled.
4532 const fs_builder ibld
= bld
.at(block
, inst
)
4533 .exec_all(inst
->force_writemask_all
)
4534 .group(MAX2(inst
->exec_size
, lower_width
),
4535 inst
->force_sechalf
);
4537 /* Split the copies in chunks of the execution width of either the
4538 * original or the lowered instruction, whichever is lower.
4540 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4541 const unsigned n
= inst
->exec_size
/ copy_width
;
4542 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4543 inst
->dst
.component_size(inst
->exec_size
);
4546 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4547 !inst
->writes_accumulator
&& !inst
->mlen
);
4549 for (unsigned i
= 0; i
< n
; i
++) {
4550 /* Emit a copy of the original instruction with the lowered width.
4551 * If the EOT flag was set throw it away except for the last
4552 * instruction to avoid killing the thread prematurely.
4554 fs_inst split_inst
= *inst
;
4555 split_inst
.exec_size
= lower_width
;
4556 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4558 /* Select the correct channel enables for the i-th group, then
4559 * transform the sources and destination and emit the lowered
4562 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4564 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4565 if (inst
->src
[j
].file
!= BAD_FILE
&&
4566 !is_uniform(inst
->src
[j
])) {
4567 /* Get the i-th copy_width-wide chunk of the source. */
4568 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4569 const unsigned src_size
= inst
->components_read(j
);
4571 /* Use a trivial transposition to copy one every n
4572 * copy_width-wide components of the register into a
4573 * temporary passed as source to the lowered instruction.
4575 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4576 emit_transpose(lbld
.group(copy_width
, 0),
4577 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4581 if (inst
->regs_written
) {
4582 /* Allocate enough space to hold the result of the lowered
4583 * instruction and fix up the number of registers written.
4585 split_inst
.dst
= dsts
[i
] =
4586 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4587 split_inst
.regs_written
=
4588 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4592 lbld
.emit(split_inst
);
4595 if (inst
->regs_written
) {
4596 /* Distance between useful channels in the temporaries, skipping
4597 * garbage if the lowered instruction is wider than the original.
4599 const unsigned m
= lower_width
/ copy_width
;
4601 /* Interleave the components of the result from the lowered
4602 * instructions. We need to set exec_all() when copying more than
4603 * one half per component, because LOAD_PAYLOAD (in terms of which
4604 * emit_transpose is implemented) can only use the same channel
4605 * enable signals for all of its non-header sources.
4607 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4608 .group(copy_width
, 0),
4609 inst
->dst
, dsts
, n
, dst_size
, m
);
4612 inst
->remove(block
);
4618 invalidate_live_intervals();
4624 fs_visitor::dump_instructions()
4626 dump_instructions(NULL
);
4630 fs_visitor::dump_instructions(const char *name
)
4632 FILE *file
= stderr
;
4633 if (name
&& geteuid() != 0) {
4634 file
= fopen(name
, "w");
4640 calculate_register_pressure();
4641 int ip
= 0, max_pressure
= 0;
4642 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4643 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4644 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4645 dump_instruction(inst
, file
);
4648 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4651 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4652 fprintf(file
, "%4d: ", ip
++);
4653 dump_instruction(inst
, file
);
4657 if (file
!= stderr
) {
4663 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4665 dump_instruction(be_inst
, stderr
);
4669 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4671 fs_inst
*inst
= (fs_inst
*)be_inst
;
4673 if (inst
->predicate
) {
4674 fprintf(file
, "(%cf0.%d) ",
4675 inst
->predicate_inverse
? '-' : '+',
4679 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4681 fprintf(file
, ".sat");
4682 if (inst
->conditional_mod
) {
4683 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4684 if (!inst
->predicate
&&
4685 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4686 inst
->opcode
!= BRW_OPCODE_IF
&&
4687 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4688 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4691 fprintf(file
, "(%d) ", inst
->exec_size
);
4694 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4697 switch (inst
->dst
.file
) {
4699 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
4700 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
4701 inst
->dst
.subreg_offset
)
4702 fprintf(file
, "+%d.%d",
4703 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4706 fprintf(file
, "g%d", inst
->dst
.nr
);
4709 fprintf(file
, "m%d", inst
->dst
.nr
);
4712 fprintf(file
, "(null)");
4715 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4718 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4721 switch (inst
->dst
.nr
) {
4723 fprintf(file
, "null");
4725 case BRW_ARF_ADDRESS
:
4726 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
4728 case BRW_ARF_ACCUMULATOR
:
4729 fprintf(file
, "acc%d", inst
->dst
.subnr
);
4732 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4735 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4738 if (inst
->dst
.subnr
)
4739 fprintf(file
, "+%d", inst
->dst
.subnr
);
4742 unreachable("not reached");
4744 if (inst
->dst
.stride
!= 1)
4745 fprintf(file
, "<%u>", inst
->dst
.stride
);
4746 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4748 for (int i
= 0; i
< inst
->sources
; i
++) {
4749 if (inst
->src
[i
].negate
)
4751 if (inst
->src
[i
].abs
)
4753 switch (inst
->src
[i
].file
) {
4755 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
4756 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
4757 inst
->src
[i
].subreg_offset
)
4758 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4759 inst
->src
[i
].subreg_offset
);
4762 fprintf(file
, "g%d", inst
->src
[i
].nr
);
4765 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
4768 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
4771 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
4772 if (inst
->src
[i
].reladdr
) {
4773 fprintf(file
, "+reladdr");
4774 } else if (inst
->src
[i
].subreg_offset
) {
4775 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4776 inst
->src
[i
].subreg_offset
);
4780 fprintf(file
, "(null)");
4783 switch (inst
->src
[i
].type
) {
4784 case BRW_REGISTER_TYPE_F
:
4785 fprintf(file
, "%-gf", inst
->src
[i
].f
);
4787 case BRW_REGISTER_TYPE_W
:
4788 case BRW_REGISTER_TYPE_D
:
4789 fprintf(file
, "%dd", inst
->src
[i
].d
);
4791 case BRW_REGISTER_TYPE_UW
:
4792 case BRW_REGISTER_TYPE_UD
:
4793 fprintf(file
, "%uu", inst
->src
[i
].ud
);
4795 case BRW_REGISTER_TYPE_VF
:
4796 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4797 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
4798 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
4799 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
4800 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
4803 fprintf(file
, "???");
4808 switch (inst
->src
[i
].nr
) {
4810 fprintf(file
, "null");
4812 case BRW_ARF_ADDRESS
:
4813 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
4815 case BRW_ARF_ACCUMULATOR
:
4816 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
4819 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4822 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4825 if (inst
->src
[i
].subnr
)
4826 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
4829 if (inst
->src
[i
].abs
)
4832 if (inst
->src
[i
].file
!= IMM
) {
4834 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
4835 unsigned hstride
= inst
->src
[i
].hstride
;
4836 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
4838 stride
= inst
->src
[i
].stride
;
4841 fprintf(file
, "<%u>", stride
);
4843 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4846 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4847 fprintf(file
, ", ");
4852 if (inst
->force_writemask_all
)
4853 fprintf(file
, "NoMask ");
4855 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4856 if (inst
->force_sechalf
)
4857 fprintf(file
, "2ndhalf ");
4859 fprintf(file
, "1sthalf ");
4862 fprintf(file
, "\n");
4866 * Possibly returns an instruction that set up @param reg.
4868 * Sometimes we want to take the result of some expression/variable
4869 * dereference tree and rewrite the instruction generating the result
4870 * of the tree. When processing the tree, we know that the
4871 * instructions generated are all writing temporaries that are dead
4872 * outside of this tree. So, if we have some instructions that write
4873 * a temporary, we're free to point that temp write somewhere else.
4875 * Note that this doesn't guarantee that the instruction generated
4876 * only reg -- it might be the size=4 destination of a texture instruction.
4879 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4884 end
->is_partial_write() ||
4886 !reg
.equals(end
->dst
)) {
4894 fs_visitor::setup_fs_payload_gen6()
4896 assert(stage
== MESA_SHADER_FRAGMENT
);
4897 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4898 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4900 unsigned barycentric_interp_modes
=
4901 (stage
== MESA_SHADER_FRAGMENT
) ?
4902 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4904 assert(devinfo
->gen
>= 6);
4906 /* R0-1: masks, pixel X/Y coordinates. */
4907 payload
.num_regs
= 2;
4908 /* R2: only for 32-pixel dispatch.*/
4910 /* R3-26: barycentric interpolation coordinates. These appear in the
4911 * same order that they appear in the brw_wm_barycentric_interp_mode
4912 * enum. Each set of coordinates occupies 2 registers if dispatch width
4913 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4914 * appear if they were enabled using the "Barycentric Interpolation
4915 * Mode" bits in WM_STATE.
4917 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4918 if (barycentric_interp_modes
& (1 << i
)) {
4919 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4920 payload
.num_regs
+= 2;
4921 if (dispatch_width
== 16) {
4922 payload
.num_regs
+= 2;
4927 /* R27: interpolated depth if uses source depth */
4928 prog_data
->uses_src_depth
=
4929 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4930 if (prog_data
->uses_src_depth
) {
4931 payload
.source_depth_reg
= payload
.num_regs
;
4933 if (dispatch_width
== 16) {
4934 /* R28: interpolated depth if not SIMD8. */
4939 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4940 prog_data
->uses_src_w
=
4941 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4942 if (prog_data
->uses_src_w
) {
4943 payload
.source_w_reg
= payload
.num_regs
;
4945 if (dispatch_width
== 16) {
4946 /* R30: interpolated W if not SIMD8. */
4951 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4952 /* R31: MSAA position offsets. */
4953 if (prog_data
->uses_pos_offset
) {
4954 payload
.sample_pos_reg
= payload
.num_regs
;
4958 /* R32: MSAA input coverage mask */
4959 prog_data
->uses_sample_mask
=
4960 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
4961 if (prog_data
->uses_sample_mask
) {
4962 assert(devinfo
->gen
>= 7);
4963 payload
.sample_mask_in_reg
= payload
.num_regs
;
4965 if (dispatch_width
== 16) {
4966 /* R33: input coverage mask if not SIMD8. */
4971 /* R34-: bary for 32-pixel. */
4972 /* R58-59: interp W for 32-pixel. */
4974 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4975 source_depth_to_render_target
= true;
4980 fs_visitor::setup_vs_payload()
4982 /* R0: thread header, R1: urb handles */
4983 payload
.num_regs
= 2;
4987 * We are building the local ID push constant data using the simplest possible
4988 * method. We simply push the local IDs directly as they should appear in the
4989 * registers for the uvec3 gl_LocalInvocationID variable.
4991 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4992 * registers worth of push constant space.
4994 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
4995 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
4998 * FINISHME: There are a few easy optimizations to consider.
5000 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
5001 * no need for using push constant space for that dimension.
5003 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
5004 * easily use 16-bit words rather than 32-bit dwords in the push constant
5007 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
5008 * conveying the data, and thereby reduce push constant usage.
5012 fs_visitor::setup_gs_payload()
5014 assert(stage
== MESA_SHADER_GEOMETRY
);
5016 struct brw_gs_prog_data
*gs_prog_data
=
5017 (struct brw_gs_prog_data
*) prog_data
;
5018 struct brw_vue_prog_data
*vue_prog_data
=
5019 (struct brw_vue_prog_data
*) prog_data
;
5021 /* R0: thread header, R1: output URB handles */
5022 payload
.num_regs
= 2;
5024 if (gs_prog_data
->include_primitive_id
) {
5025 /* R2: Primitive ID 0..7 */
5029 /* Use a maximum of 32 registers for push-model inputs. */
5030 const unsigned max_push_components
= 32;
5032 /* If pushing our inputs would take too many registers, reduce the URB read
5033 * length (which is in HWords, or 8 registers), and resort to pulling.
5035 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5036 * have to multiply by VerticesIn to obtain the total storage requirement.
5038 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5039 max_push_components
) {
5040 gs_prog_data
->base
.include_vue_handles
= true;
5042 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5043 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5045 vue_prog_data
->urb_read_length
=
5046 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5051 fs_visitor::setup_cs_payload()
5053 assert(devinfo
->gen
>= 7);
5054 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
5056 payload
.num_regs
= 1;
5058 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
5059 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
5060 payload
.local_invocation_id_reg
= payload
.num_regs
;
5061 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
5066 fs_visitor::calculate_register_pressure()
5068 invalidate_live_intervals();
5069 calculate_live_intervals();
5071 unsigned num_instructions
= 0;
5072 foreach_block(block
, cfg
)
5073 num_instructions
+= block
->instructions
.length();
5075 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5077 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5078 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5079 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5084 fs_visitor::optimize()
5086 /* Start by validating the shader we currently have. */
5089 /* bld is the common builder object pointing at the end of the program we
5090 * used to translate it into i965 IR. For the optimization and lowering
5091 * passes coming next, any code added after the end of the program without
5092 * having explicitly called fs_builder::at() clearly points at a mistake.
5093 * Ideally optimization passes wouldn't be part of the visitor so they
5094 * wouldn't have access to bld at all, but they do, so just in case some
5095 * pass forgets to ask for a location explicitly set it to NULL here to
5096 * make it trip. The dispatch width is initialized to a bogus value to
5097 * make sure that optimizations set the execution controls explicitly to
5098 * match the code they are manipulating instead of relying on the defaults.
5100 bld
= fs_builder(this, 64);
5102 assign_constant_locations();
5103 demote_pull_constants();
5107 split_virtual_grfs();
5110 #define OPT(pass, args...) ({ \
5112 bool this_progress = pass(args); \
5114 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5115 char filename[64]; \
5116 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5117 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5119 backend_shader::dump_instructions(filename); \
5124 progress = progress || this_progress; \
5128 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5130 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5131 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5133 backend_shader::dump_instructions(filename
);
5136 bool progress
= false;
5140 OPT(lower_simd_width
);
5141 OPT(lower_logical_sends
);
5148 OPT(remove_duplicate_mrf_writes
);
5152 OPT(opt_copy_propagate
);
5153 OPT(opt_predicated_break
, this);
5154 OPT(opt_cmod_propagation
);
5155 OPT(dead_code_eliminate
);
5156 OPT(opt_peephole_sel
);
5157 OPT(dead_control_flow_eliminate
, this);
5158 OPT(opt_register_renaming
);
5159 OPT(opt_redundant_discard_jumps
);
5160 OPT(opt_saturate_propagation
);
5161 OPT(opt_zero_samples
);
5162 OPT(register_coalesce
);
5163 OPT(compute_to_mrf
);
5164 OPT(eliminate_find_live_channel
);
5166 OPT(compact_virtual_grfs
);
5171 OPT(opt_sampler_eot
);
5173 if (OPT(lower_load_payload
)) {
5174 split_virtual_grfs();
5175 OPT(register_coalesce
);
5176 OPT(compute_to_mrf
);
5177 OPT(dead_code_eliminate
);
5180 OPT(opt_combine_constants
);
5181 OPT(lower_integer_multiplication
);
5183 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5184 OPT(opt_cmod_propagation
);
5186 OPT(opt_copy_propagate
);
5187 OPT(dead_code_eliminate
);
5190 lower_uniform_pull_constant_loads();
5196 * Three source instruction must have a GRF/MRF destination register.
5197 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5200 fs_visitor::fixup_3src_null_dest()
5202 bool progress
= false;
5204 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5205 if (inst
->is_3src() && inst
->dst
.is_null()) {
5206 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5213 invalidate_live_intervals();
5217 fs_visitor::allocate_registers()
5219 bool allocated_without_spills
;
5221 static const enum instruction_scheduler_mode pre_modes
[] = {
5223 SCHEDULE_PRE_NON_LIFO
,
5227 /* Try each scheduling heuristic to see if it can successfully register
5228 * allocate without spilling. They should be ordered by decreasing
5229 * performance but increasing likelihood of allocating.
5231 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5232 schedule_instructions(pre_modes
[i
]);
5235 assign_regs_trivial();
5236 allocated_without_spills
= true;
5238 allocated_without_spills
= assign_regs(false);
5240 if (allocated_without_spills
)
5244 if (!allocated_without_spills
) {
5245 /* We assume that any spilling is worse than just dropping back to
5246 * SIMD8. There's probably actually some intermediate point where
5247 * SIMD16 with a couple of spills is still better.
5249 if (dispatch_width
== 16 && min_dispatch_width
<= 8) {
5250 fail("Failure to register allocate. Reduce number of "
5251 "live scalar values to avoid this.");
5253 compiler
->shader_perf_log(log_data
,
5254 "%s shader triggered register spilling. "
5255 "Try reducing the number of live scalar "
5256 "values to improve performance.\n",
5260 /* Since we're out of heuristics, just go spill registers until we
5261 * get an allocation.
5263 while (!assign_regs(true)) {
5269 /* This must come after all optimization and register allocation, since
5270 * it inserts dead code that happens to have side effects, and it does
5271 * so based on the actual physical registers in use.
5273 insert_gen4_send_dependency_workarounds();
5278 schedule_instructions(SCHEDULE_POST
);
5280 if (last_scratch
> 0)
5281 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5285 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5287 assert(stage
== MESA_SHADER_VERTEX
);
5291 if (shader_time_index
>= 0)
5292 emit_shader_time_begin();
5299 compute_clip_distance(clip_planes
);
5303 if (shader_time_index
>= 0)
5304 emit_shader_time_end();
5310 assign_curb_setup();
5311 assign_vs_urb_setup();
5313 fixup_3src_null_dest();
5314 allocate_registers();
5320 fs_visitor::run_tes()
5322 assert(stage
== MESA_SHADER_TESS_EVAL
);
5324 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
5325 payload
.num_regs
= 5;
5327 if (shader_time_index
>= 0)
5328 emit_shader_time_begin();
5337 if (shader_time_index
>= 0)
5338 emit_shader_time_end();
5344 assign_curb_setup();
5345 assign_tes_urb_setup();
5347 fixup_3src_null_dest();
5348 allocate_registers();
5354 fs_visitor::run_gs()
5356 assert(stage
== MESA_SHADER_GEOMETRY
);
5360 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
5362 if (gs_compile
->control_data_header_size_bits
> 0) {
5363 /* Create a VGRF to store accumulated control data bits. */
5364 this->control_data_bits
= vgrf(glsl_type::uint_type
);
5366 /* If we're outputting more than 32 control data bits, then EmitVertex()
5367 * will set control_data_bits to 0 after emitting the first vertex.
5368 * Otherwise, we need to initialize it to 0 here.
5370 if (gs_compile
->control_data_header_size_bits
<= 32) {
5371 const fs_builder abld
= bld
.annotate("initialize control data bits");
5372 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
5376 if (shader_time_index
>= 0)
5377 emit_shader_time_begin();
5381 emit_gs_thread_end();
5383 if (shader_time_index
>= 0)
5384 emit_shader_time_end();
5393 assign_curb_setup();
5394 assign_gs_urb_setup();
5396 fixup_3src_null_dest();
5397 allocate_registers();
5403 fs_visitor::run_fs(bool do_rep_send
)
5405 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5406 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5408 assert(stage
== MESA_SHADER_FRAGMENT
);
5410 if (devinfo
->gen
>= 6)
5411 setup_fs_payload_gen6();
5413 setup_fs_payload_gen4();
5417 } else if (do_rep_send
) {
5418 assert(dispatch_width
== 16);
5419 emit_repclear_shader();
5421 if (shader_time_index
>= 0)
5422 emit_shader_time_begin();
5424 calculate_urb_setup();
5425 if (nir
->info
.inputs_read
> 0) {
5426 if (devinfo
->gen
< 6)
5427 emit_interpolation_setup_gen4();
5429 emit_interpolation_setup_gen6();
5432 /* We handle discards by keeping track of the still-live pixels in f0.1.
5433 * Initialize it with the dispatched pixels.
5435 if (wm_prog_data
->uses_kill
) {
5436 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5437 discard_init
->flag_subreg
= 1;
5440 /* Generate FS IR for main(). (the visitor only descends into
5441 * functions called "main").
5448 if (wm_prog_data
->uses_kill
)
5449 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5451 if (wm_key
->alpha_test_func
)
5456 if (shader_time_index
>= 0)
5457 emit_shader_time_end();
5463 assign_curb_setup();
5466 fixup_3src_null_dest();
5467 allocate_registers();
5473 if (dispatch_width
== 8)
5474 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5476 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5482 fs_visitor::run_cs()
5484 assert(stage
== MESA_SHADER_COMPUTE
);
5488 if (shader_time_index
>= 0)
5489 emit_shader_time_begin();
5491 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
5492 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
5493 const fs_builder abld
= bld
.exec_all().group(1, 0);
5494 abld
.MOV(retype(suboffset(brw_sr0_reg(), 1), BRW_REGISTER_TYPE_UW
),
5495 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
5503 emit_cs_terminate();
5505 if (shader_time_index
>= 0)
5506 emit_shader_time_end();
5512 assign_curb_setup();
5514 fixup_3src_null_dest();
5515 allocate_registers();
5524 * Return a bitfield where bit n is set if barycentric interpolation mode n
5525 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5528 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5529 bool shade_model_flat
,
5530 bool persample_shading
,
5531 const nir_shader
*shader
)
5533 unsigned barycentric_interp_modes
= 0;
5535 nir_foreach_variable(var
, &shader
->inputs
) {
5536 enum glsl_interp_qualifier interp_qualifier
=
5537 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5538 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5539 bool is_sample
= var
->data
.sample
|| persample_shading
;
5540 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5541 (var
->data
.location
== VARYING_SLOT_COL1
);
5543 /* Ignore WPOS and FACE, because they don't require interpolation. */
5544 if (var
->data
.location
== VARYING_SLOT_POS
||
5545 var
->data
.location
== VARYING_SLOT_FACE
)
5548 /* Determine the set (or sets) of barycentric coordinates needed to
5549 * interpolate this variable. Note that when
5550 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5551 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5552 * for lit pixels, so we need both sets of barycentric coordinates.
5554 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5556 barycentric_interp_modes
|=
5557 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5558 } else if (is_sample
) {
5559 barycentric_interp_modes
|=
5560 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5562 if ((!is_centroid
&& !is_sample
) ||
5563 devinfo
->needs_unlit_centroid_workaround
) {
5564 barycentric_interp_modes
|=
5565 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5567 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5568 (!(shade_model_flat
&& is_gl_Color
) &&
5569 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5571 barycentric_interp_modes
|=
5572 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5573 } else if (is_sample
) {
5574 barycentric_interp_modes
|=
5575 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5577 if ((!is_centroid
&& !is_sample
) ||
5578 devinfo
->needs_unlit_centroid_workaround
) {
5579 barycentric_interp_modes
|=
5580 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5585 return barycentric_interp_modes
;
5589 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
5590 bool shade_model_flat
, const nir_shader
*shader
)
5592 prog_data
->flat_inputs
= 0;
5594 nir_foreach_variable(var
, &shader
->inputs
) {
5595 enum glsl_interp_qualifier interp_qualifier
=
5596 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5597 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5598 (var
->data
.location
== VARYING_SLOT_COL1
);
5600 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
5602 if (input_index
< 0)
5606 if (interp_qualifier
== INTERP_QUALIFIER_FLAT
||
5607 (shade_model_flat
&& is_gl_Color
&&
5608 interp_qualifier
== INTERP_QUALIFIER_NONE
))
5609 prog_data
->flat_inputs
|= (1 << input_index
);
5614 computed_depth_mode(const nir_shader
*shader
)
5616 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5617 switch (shader
->info
.fs
.depth_layout
) {
5618 case FRAG_DEPTH_LAYOUT_NONE
:
5619 case FRAG_DEPTH_LAYOUT_ANY
:
5620 return BRW_PSCDEPTH_ON
;
5621 case FRAG_DEPTH_LAYOUT_GREATER
:
5622 return BRW_PSCDEPTH_ON_GE
;
5623 case FRAG_DEPTH_LAYOUT_LESS
:
5624 return BRW_PSCDEPTH_ON_LE
;
5625 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5626 return BRW_PSCDEPTH_OFF
;
5629 return BRW_PSCDEPTH_OFF
;
5633 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5635 const struct brw_wm_prog_key
*key
,
5636 struct brw_wm_prog_data
*prog_data
,
5637 const nir_shader
*src_shader
,
5638 struct gl_program
*prog
,
5639 int shader_time_index8
, int shader_time_index16
,
5641 unsigned *final_assembly_size
,
5644 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5645 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5647 brw_nir_lower_fs_inputs(shader
);
5648 brw_nir_lower_fs_outputs(shader
);
5649 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5651 /* key->alpha_test_func means simulating alpha testing via discards,
5652 * so the shader definitely kills pixels.
5654 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5655 prog_data
->uses_omask
=
5656 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5657 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5658 prog_data
->computed_stencil
=
5659 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5661 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5663 prog_data
->barycentric_interp_modes
=
5664 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5666 key
->persample_shading
,
5669 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5670 &prog_data
->base
, prog
, shader
, 8,
5671 shader_time_index8
);
5672 if (!v
.run_fs(false /* do_rep_send */)) {
5674 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5679 cfg_t
*simd16_cfg
= NULL
;
5680 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5681 &prog_data
->base
, prog
, shader
, 16,
5682 shader_time_index16
);
5683 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5684 if (!v
.simd16_unsupported
) {
5685 /* Try a SIMD16 compile */
5686 v2
.import_uniforms(&v
);
5687 if (!v2
.run_fs(use_rep_send
)) {
5688 compiler
->shader_perf_log(log_data
,
5689 "SIMD16 shader failed to compile: %s",
5692 simd16_cfg
= v2
.cfg
;
5697 /* We have to compute the flat inputs after the visitor is finished running
5698 * because it relies on prog_data->urb_setup which is computed in
5699 * fs_visitor::calculate_urb_setup().
5701 brw_compute_flat_inputs(prog_data
, key
->flat_shade
, shader
);
5704 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5705 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5707 prog_data
->no_8
= true;
5710 prog_data
->no_8
= false;
5713 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5714 v
.promoted_constants
, v
.runtime_check_aads_emit
,
5715 MESA_SHADER_FRAGMENT
);
5717 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5718 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5719 shader
->info
.label
? shader
->info
.label
:
5721 shader
->info
.name
));
5725 g
.generate_code(simd8_cfg
, 8);
5727 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5729 return g
.get_assembly(final_assembly_size
);
5733 fs_visitor::emit_cs_local_invocation_id_setup()
5735 assert(stage
== MESA_SHADER_COMPUTE
);
5737 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5739 struct brw_reg src
=
5740 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5741 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5743 src
.nr
+= dispatch_width
/ 8;
5744 bld
.MOV(offset(*reg
, bld
, 1), src
);
5745 src
.nr
+= dispatch_width
/ 8;
5746 bld
.MOV(offset(*reg
, bld
, 2), src
);
5752 fs_visitor::emit_cs_work_group_id_setup()
5754 assert(stage
== MESA_SHADER_COMPUTE
);
5756 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5758 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5759 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5760 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5762 bld
.MOV(*reg
, r0_1
);
5763 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5764 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5770 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5772 const struct brw_cs_prog_key
*key
,
5773 struct brw_cs_prog_data
*prog_data
,
5774 const nir_shader
*src_shader
,
5775 int shader_time_index
,
5776 unsigned *final_assembly_size
,
5779 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5780 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5782 brw_nir_lower_cs_shared(shader
);
5783 prog_data
->base
.total_shared
+= shader
->num_shared
;
5784 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5786 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5787 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5788 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5789 unsigned local_workgroup_size
=
5790 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5791 shader
->info
.cs
.local_size
[2];
5793 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5794 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
5797 const char *fail_msg
= NULL
;
5799 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5801 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5802 NULL
, /* Never used in core profile */
5803 shader
, 8, shader_time_index
);
5804 if (simd_required
<= 8) {
5806 fail_msg
= v8
.fail_msg
;
5809 prog_data
->simd_size
= 8;
5813 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5814 NULL
, /* Never used in core profile */
5815 shader
, 16, shader_time_index
);
5816 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5817 !fail_msg
&& !v8
.simd16_unsupported
&&
5818 local_workgroup_size
<= 16 * max_cs_threads
) {
5819 /* Try a SIMD16 compile */
5820 if (simd_required
<= 8)
5821 v16
.import_uniforms(&v8
);
5822 if (!v16
.run_cs()) {
5823 compiler
->shader_perf_log(log_data
,
5824 "SIMD16 shader failed to compile: %s",
5828 "Couldn't generate SIMD16 program and not "
5829 "enough threads for SIMD8";
5833 prog_data
->simd_size
= 16;
5837 if (unlikely(cfg
== NULL
)) {
5840 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5845 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5846 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
5847 MESA_SHADER_COMPUTE
);
5848 if (INTEL_DEBUG
& DEBUG_CS
) {
5849 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5850 shader
->info
.label
? shader
->info
.label
:
5853 g
.enable_debug(name
);
5856 g
.generate_code(cfg
, prog_data
->simd_size
);
5858 return g
.get_assembly(final_assembly_size
);
5862 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
5863 void *buffer
, uint32_t threads
, uint32_t stride
)
5865 if (prog_data
->local_invocation_id_regs
== 0)
5868 /* 'stride' should be an integer number of registers, that is, a multiple
5871 assert(stride
% 32 == 0);
5873 unsigned x
= 0, y
= 0, z
= 0;
5874 for (unsigned t
= 0; t
< threads
; t
++) {
5875 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
5877 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
5878 param
[0 * prog_data
->simd_size
+ i
] = x
;
5879 param
[1 * prog_data
->simd_size
+ i
] = y
;
5880 param
[2 * prog_data
->simd_size
+ i
] = z
;
5883 if (x
== prog_data
->local_size
[0]) {
5886 if (y
== prog_data
->local_size
[1]) {
5889 if (z
== prog_data
->local_size
[2])