2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "../glsl/glsl_types.h"
48 #include "../glsl/ir_optimization.h"
49 #include "../glsl/ir_print_visitor.h"
51 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
54 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
56 struct brw_shader
*shader
;
58 shader
= talloc_zero(NULL
, struct brw_shader
);
60 shader
->base
.Type
= type
;
61 shader
->base
.Name
= name
;
62 _mesa_init_shader(ctx
, &shader
->base
);
68 struct gl_shader_program
*
69 brw_new_shader_program(struct gl_context
*ctx
, GLuint name
)
71 struct brw_shader_program
*prog
;
72 prog
= talloc_zero(NULL
, struct brw_shader_program
);
74 prog
->base
.Name
= name
;
75 _mesa_init_shader_program(ctx
, &prog
->base
);
81 brw_compile_shader(struct gl_context
*ctx
, struct gl_shader
*shader
)
83 if (!_mesa_ir_compile_shader(ctx
, shader
))
90 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
92 struct brw_shader
*shader
=
93 (struct brw_shader
*)prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
95 void *mem_ctx
= talloc_new(NULL
);
99 talloc_free(shader
->ir
);
100 shader
->ir
= new(shader
) exec_list
;
101 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
103 do_mat_op_to_vec(shader
->ir
);
104 do_mod_to_fract(shader
->ir
);
105 do_div_to_mul_rcp(shader
->ir
);
106 do_sub_to_add_neg(shader
->ir
);
107 do_explog_to_explog2(shader
->ir
);
108 do_lower_texture_projection(shader
->ir
);
109 brw_do_cubemap_normalize(shader
->ir
);
114 brw_do_channel_expressions(shader
->ir
);
115 brw_do_vector_splitting(shader
->ir
);
117 progress
= do_lower_jumps(shader
->ir
, true, true,
118 true, /* main return */
119 false, /* continue */
123 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
125 progress
= lower_noise(shader
->ir
) || progress
;
127 lower_variable_index_to_cond_assign(shader
->ir
,
129 GL_TRUE
, /* output */
131 GL_TRUE
/* uniform */
135 validate_ir_tree(shader
->ir
);
137 reparent_ir(shader
->ir
, shader
->ir
);
138 talloc_free(mem_ctx
);
141 if (!_mesa_ir_link_shader(ctx
, prog
))
148 type_size(const struct glsl_type
*type
)
150 unsigned int size
, i
;
152 switch (type
->base_type
) {
155 case GLSL_TYPE_FLOAT
:
157 return type
->components();
158 case GLSL_TYPE_ARRAY
:
159 return type_size(type
->fields
.array
) * type
->length
;
160 case GLSL_TYPE_STRUCT
:
162 for (i
= 0; i
< type
->length
; i
++) {
163 size
+= type_size(type
->fields
.structure
[i
].type
);
166 case GLSL_TYPE_SAMPLER
:
167 /* Samplers take up no register space, since they're baked in at
172 assert(!"not reached");
178 fs_visitor::virtual_grf_alloc(int size
)
180 if (virtual_grf_array_size
<= virtual_grf_next
) {
181 if (virtual_grf_array_size
== 0)
182 virtual_grf_array_size
= 16;
184 virtual_grf_array_size
*= 2;
185 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
186 int, virtual_grf_array_size
);
188 /* This slot is always unused. */
189 virtual_grf_sizes
[0] = 0;
191 virtual_grf_sizes
[virtual_grf_next
] = size
;
192 return virtual_grf_next
++;
195 /** Fixed HW reg constructor. */
196 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
200 this->hw_reg
= hw_reg
;
201 this->type
= BRW_REGISTER_TYPE_F
;
204 /** Fixed HW reg constructor. */
205 fs_reg::fs_reg(enum register_file file
, int hw_reg
, uint32_t type
)
209 this->hw_reg
= hw_reg
;
214 brw_type_for_base_type(const struct glsl_type
*type
)
216 switch (type
->base_type
) {
217 case GLSL_TYPE_FLOAT
:
218 return BRW_REGISTER_TYPE_F
;
221 return BRW_REGISTER_TYPE_D
;
223 return BRW_REGISTER_TYPE_UD
;
224 case GLSL_TYPE_ARRAY
:
225 case GLSL_TYPE_STRUCT
:
226 case GLSL_TYPE_SAMPLER
:
227 /* These should be overridden with the type of the member when
228 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
229 * way to trip up if we don't.
231 return BRW_REGISTER_TYPE_UD
;
233 assert(!"not reached");
234 return BRW_REGISTER_TYPE_F
;
238 /** Automatic reg constructor. */
239 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
244 this->reg
= v
->virtual_grf_alloc(type_size(type
));
245 this->reg_offset
= 0;
246 this->type
= brw_type_for_base_type(type
);
250 fs_visitor::variable_storage(ir_variable
*var
)
252 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
255 /* Our support for uniforms is piggy-backed on the struct
256 * gl_fragment_program, because that's where the values actually
257 * get stored, rather than in some global gl_shader_program uniform
261 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
263 unsigned int offset
= 0;
266 if (type
->is_matrix()) {
267 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
268 type
->vector_elements
,
271 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
272 offset
+= setup_uniform_values(loc
+ offset
, column
);
278 switch (type
->base_type
) {
279 case GLSL_TYPE_FLOAT
:
283 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
284 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
285 unsigned int param
= c
->prog_data
.nr_params
++;
287 assert(param
< ARRAY_SIZE(c
->prog_data
.param
));
289 switch (type
->base_type
) {
290 case GLSL_TYPE_FLOAT
:
291 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
294 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2U
;
297 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2I
;
300 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2B
;
303 assert(!"not reached");
304 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
308 c
->prog_data
.param
[param
] = &vec_values
[i
];
312 case GLSL_TYPE_STRUCT
:
313 for (unsigned int i
= 0; i
< type
->length
; i
++) {
314 offset
+= setup_uniform_values(loc
+ offset
,
315 type
->fields
.structure
[i
].type
);
319 case GLSL_TYPE_ARRAY
:
320 for (unsigned int i
= 0; i
< type
->length
; i
++) {
321 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
325 case GLSL_TYPE_SAMPLER
:
326 /* The sampler takes up a slot, but we don't use any values from it. */
330 assert(!"not reached");
336 /* Our support for builtin uniforms is even scarier than non-builtin.
337 * It sits on top of the PROG_STATE_VAR parameters that are
338 * automatically updated from GL context state.
341 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
343 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
345 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
346 statevar
= &_mesa_builtin_uniform_desc
[i
];
347 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
351 if (!statevar
->name
) {
353 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
358 if (ir
->type
->is_array()) {
359 array_count
= ir
->type
->length
;
364 for (int a
= 0; a
< array_count
; a
++) {
365 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
366 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
367 int tokens
[STATE_LENGTH
];
369 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
370 if (ir
->type
->is_array()) {
374 /* This state reference has already been setup by ir_to_mesa,
375 * but we'll get the same index back here.
377 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
378 (gl_state_index
*)tokens
);
379 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
381 /* Add each of the unique swizzles of the element as a
382 * parameter. This'll end up matching the expected layout of
383 * the array/matrix/structure we're trying to fill in.
386 for (unsigned int i
= 0; i
< 4; i
++) {
387 int swiz
= GET_SWZ(element
->swizzle
, i
);
388 if (swiz
== last_swiz
)
392 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
394 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
401 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
403 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
405 fs_reg neg_y
= this->pixel_y
;
407 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
410 if (ir
->pixel_center_integer
) {
411 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
413 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
418 if (!flip
&& ir
->pixel_center_integer
) {
419 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
421 fs_reg pixel_y
= this->pixel_y
;
422 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
425 pixel_y
.negate
= true;
426 offset
+= c
->key
.drawable_height
- 1.0;
429 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
434 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
435 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
438 /* gl_FragCoord.w: Already set up in emit_interpolation */
439 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
445 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
447 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
448 /* Interpolation is always in floating point regs. */
449 reg
->type
= BRW_REGISTER_TYPE_F
;
452 unsigned int array_elements
;
453 const glsl_type
*type
;
455 if (ir
->type
->is_array()) {
456 array_elements
= ir
->type
->length
;
457 if (array_elements
== 0) {
460 type
= ir
->type
->fields
.array
;
466 int location
= ir
->location
;
467 for (unsigned int i
= 0; i
< array_elements
; i
++) {
468 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
469 if (urb_setup
[location
] == -1) {
470 /* If there's no incoming setup data for this slot, don't
471 * emit interpolation for it.
473 attr
.reg_offset
+= type
->vector_elements
;
478 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
479 struct brw_reg interp
= interp_reg(location
, c
);
480 emit(fs_inst(FS_OPCODE_LINTERP
,
488 if (intel
->gen
< 6) {
489 attr
.reg_offset
-= type
->vector_elements
;
490 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
491 emit(fs_inst(BRW_OPCODE_MUL
,
506 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
508 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
510 /* The frontfacing comes in as a bit in the thread payload. */
511 if (intel
->gen
>= 6) {
512 emit(fs_inst(BRW_OPCODE_ASR
,
514 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
516 emit(fs_inst(BRW_OPCODE_NOT
,
519 emit(fs_inst(BRW_OPCODE_AND
,
524 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
525 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
528 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
532 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
533 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
540 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src
)
552 assert(!"not reached: bad math opcode");
556 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
557 * might be able to do better by doing execsize = 1 math and then
558 * expanding that result out, but we would need to be careful with
561 if (intel
->gen
>= 6 && src
.file
== UNIFORM
) {
562 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
563 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src
));
567 fs_inst
*inst
= emit(fs_inst(opcode
, dst
, src
));
569 if (intel
->gen
< 6) {
578 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
583 assert(opcode
== FS_OPCODE_POW
);
585 if (intel
->gen
>= 6) {
586 /* Can't do hstride == 0 args to gen6 math, so expand it out. */
587 if (src0
.file
== UNIFORM
) {
588 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
589 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src0
));
593 if (src1
.file
== UNIFORM
) {
594 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
595 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src1
));
599 inst
= emit(fs_inst(opcode
, dst
, src0
, src1
));
601 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1), src1
));
602 inst
= emit(fs_inst(opcode
, dst
, src0
, reg_null_f
));
604 inst
->base_mrf
= base_mrf
;
611 fs_visitor::visit(ir_variable
*ir
)
615 if (variable_storage(ir
))
618 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
619 this->frag_color
= ir
;
620 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
621 this->frag_data
= ir
;
622 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
623 this->frag_depth
= ir
;
626 if (ir
->mode
== ir_var_in
) {
627 if (!strcmp(ir
->name
, "gl_FragCoord")) {
628 reg
= emit_fragcoord_interpolation(ir
);
629 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
630 reg
= emit_frontfacing_interpolation(ir
);
632 reg
= emit_general_interpolation(ir
);
635 hash_table_insert(this->variable_ht
, reg
, ir
);
639 if (ir
->mode
== ir_var_uniform
) {
640 int param_index
= c
->prog_data
.nr_params
;
642 if (!strncmp(ir
->name
, "gl_", 3)) {
643 setup_builtin_uniform_values(ir
);
645 setup_uniform_values(ir
->location
, ir
->type
);
648 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
649 reg
->type
= brw_type_for_base_type(ir
->type
);
653 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
655 hash_table_insert(this->variable_ht
, reg
, ir
);
659 fs_visitor::visit(ir_dereference_variable
*ir
)
661 fs_reg
*reg
= variable_storage(ir
->var
);
666 fs_visitor::visit(ir_dereference_record
*ir
)
668 const glsl_type
*struct_type
= ir
->record
->type
;
670 ir
->record
->accept(this);
672 unsigned int offset
= 0;
673 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
674 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
676 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
678 this->result
.reg_offset
+= offset
;
679 this->result
.type
= brw_type_for_base_type(ir
->type
);
683 fs_visitor::visit(ir_dereference_array
*ir
)
688 ir
->array
->accept(this);
689 index
= ir
->array_index
->as_constant();
691 element_size
= type_size(ir
->type
);
692 this->result
.type
= brw_type_for_base_type(ir
->type
);
695 assert(this->result
.file
== UNIFORM
||
696 (this->result
.file
== GRF
&&
697 this->result
.reg
!= 0));
698 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
700 assert(!"FINISHME: non-constant array element");
705 fs_visitor::visit(ir_expression
*ir
)
707 unsigned int operand
;
711 assert(ir
->get_num_operands() <= 2);
712 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
713 ir
->operands
[operand
]->accept(this);
714 if (this->result
.file
== BAD_FILE
) {
716 printf("Failed to get tree for expression operand:\n");
717 ir
->operands
[operand
]->accept(&v
);
720 op
[operand
] = this->result
;
722 /* Matrix expression operands should have been broken down to vector
723 * operations already.
725 assert(!ir
->operands
[operand
]->type
->is_matrix());
726 /* And then those vector operands should have been broken down to scalar.
728 assert(!ir
->operands
[operand
]->type
->is_vector());
731 /* Storage for our result. If our result goes into an assignment, it will
732 * just get copy-propagated out, so no worries.
734 this->result
= fs_reg(this, ir
->type
);
736 switch (ir
->operation
) {
737 case ir_unop_logic_not
:
738 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
739 * ones complement of the whole register, not just bit 0.
741 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1)));
744 op
[0].negate
= !op
[0].negate
;
745 this->result
= op
[0];
749 this->result
= op
[0];
752 temp
= fs_reg(this, ir
->type
);
754 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
756 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
757 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
758 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
759 inst
->predicated
= true;
761 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
762 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
763 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
764 inst
->predicated
= true;
768 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
772 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
775 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
779 assert(!"not reached: should be handled by ir_explog_to_explog2");
782 case ir_unop_sin_reduced
:
783 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
786 case ir_unop_cos_reduced
:
787 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
791 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
794 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
798 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
801 assert(!"not reached: should be handled by ir_sub_to_add_neg");
805 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
808 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
811 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
815 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
816 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
817 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
819 case ir_binop_greater
:
820 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
821 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
822 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
824 case ir_binop_lequal
:
825 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
826 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
827 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
829 case ir_binop_gequal
:
830 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
831 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
832 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
835 case ir_binop_all_equal
: /* same as nequal for scalars */
836 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
837 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
838 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
840 case ir_binop_nequal
:
841 case ir_binop_any_nequal
: /* same as nequal for scalars */
842 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
843 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
844 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
847 case ir_binop_logic_xor
:
848 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
851 case ir_binop_logic_or
:
852 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
855 case ir_binop_logic_and
:
856 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
861 assert(!"not reached: should be handled by brw_fs_channel_expressions");
865 assert(!"not reached: should be handled by lower_noise");
869 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
873 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
880 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
884 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
885 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
886 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
,
887 this->result
, fs_reg(1)));
891 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
894 op
[0].negate
= !op
[0].negate
;
895 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
896 this->result
.negate
= true;
899 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
902 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
904 case ir_unop_round_even
:
905 emit(fs_inst(BRW_OPCODE_RNDE
, this->result
, op
[0]));
909 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
910 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
912 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
913 inst
->predicated
= true;
916 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
917 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
919 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
920 inst
->predicated
= true;
924 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
927 case ir_unop_bit_not
:
928 inst
= emit(fs_inst(BRW_OPCODE_NOT
, this->result
, op
[0]));
930 case ir_binop_bit_and
:
931 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
933 case ir_binop_bit_xor
:
934 inst
= emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
936 case ir_binop_bit_or
:
937 inst
= emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
941 case ir_binop_lshift
:
942 case ir_binop_rshift
:
943 assert(!"GLSL 1.30 features unsupported");
949 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
950 const glsl_type
*type
, bool predicated
)
952 switch (type
->base_type
) {
953 case GLSL_TYPE_FLOAT
:
957 for (unsigned int i
= 0; i
< type
->components(); i
++) {
958 l
.type
= brw_type_for_base_type(type
);
959 r
.type
= brw_type_for_base_type(type
);
961 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
962 inst
->predicated
= predicated
;
968 case GLSL_TYPE_ARRAY
:
969 for (unsigned int i
= 0; i
< type
->length
; i
++) {
970 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
974 case GLSL_TYPE_STRUCT
:
975 for (unsigned int i
= 0; i
< type
->length
; i
++) {
976 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
981 case GLSL_TYPE_SAMPLER
:
985 assert(!"not reached");
991 fs_visitor::visit(ir_assignment
*ir
)
996 /* FINISHME: arrays on the lhs */
997 ir
->lhs
->accept(this);
1000 ir
->rhs
->accept(this);
1003 assert(l
.file
!= BAD_FILE
);
1004 assert(r
.file
!= BAD_FILE
);
1006 if (ir
->condition
) {
1007 emit_bool_to_cond_code(ir
->condition
);
1010 if (ir
->lhs
->type
->is_scalar() ||
1011 ir
->lhs
->type
->is_vector()) {
1012 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1013 if (ir
->write_mask
& (1 << i
)) {
1014 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1016 inst
->predicated
= true;
1022 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1027 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1031 bool simd16
= false;
1037 if (ir
->shadow_comparitor
) {
1038 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1039 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1041 coordinate
.reg_offset
++;
1043 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1046 if (ir
->op
== ir_tex
) {
1047 /* There's no plain shadow compare message, so we use shadow
1048 * compare with a bias of 0.0.
1050 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1053 } else if (ir
->op
== ir_txb
) {
1054 ir
->lod_info
.bias
->accept(this);
1055 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1059 assert(ir
->op
== ir_txl
);
1060 ir
->lod_info
.lod
->accept(this);
1061 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1066 ir
->shadow_comparitor
->accept(this);
1067 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1069 } else if (ir
->op
== ir_tex
) {
1070 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1071 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1073 coordinate
.reg_offset
++;
1075 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1078 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1079 * instructions. We'll need to do SIMD16 here.
1081 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1083 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1084 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2),
1086 coordinate
.reg_offset
++;
1089 /* lod/bias appears after u/v/r. */
1092 if (ir
->op
== ir_txb
) {
1093 ir
->lod_info
.bias
->accept(this);
1094 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1098 ir
->lod_info
.lod
->accept(this);
1099 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1104 /* The unused upper half. */
1107 /* Now, since we're doing simd16, the return is 2 interleaved
1108 * vec4s where the odd-indexed ones are junk. We'll need to move
1109 * this weirdness around to the expected layout.
1113 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1115 dst
.type
= BRW_REGISTER_TYPE_F
;
1118 fs_inst
*inst
= NULL
;
1121 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1124 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1127 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1131 assert(!"GLSL 1.30 features unsupported");
1134 inst
->base_mrf
= base_mrf
;
1138 for (int i
= 0; i
< 4; i
++) {
1139 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1140 orig_dst
.reg_offset
++;
1141 dst
.reg_offset
+= 2;
1149 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1151 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1152 * optional parameters like shadow comparitor or LOD bias. If
1153 * optional parameters aren't present, those base slots are
1154 * optional and don't need to be included in the message.
1156 * We don't fill in the unnecessary slots regardless, which may
1157 * look surprising in the disassembly.
1159 int mlen
= 1; /* g0 header always present. */
1162 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1163 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1165 coordinate
.reg_offset
++;
1167 mlen
+= ir
->coordinate
->type
->vector_elements
;
1169 if (ir
->shadow_comparitor
) {
1170 mlen
= MAX2(mlen
, 5);
1172 ir
->shadow_comparitor
->accept(this);
1173 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1177 fs_inst
*inst
= NULL
;
1180 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1183 ir
->lod_info
.bias
->accept(this);
1184 mlen
= MAX2(mlen
, 5);
1185 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1188 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1191 ir
->lod_info
.lod
->accept(this);
1192 mlen
= MAX2(mlen
, 5);
1193 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1196 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1200 assert(!"GLSL 1.30 features unsupported");
1203 inst
->base_mrf
= base_mrf
;
1210 fs_visitor::visit(ir_texture
*ir
)
1213 fs_inst
*inst
= NULL
;
1215 ir
->coordinate
->accept(this);
1216 fs_reg coordinate
= this->result
;
1218 /* Should be lowered by do_lower_texture_projection */
1219 assert(!ir
->projector
);
1221 sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
1222 ctx
->Shader
.CurrentFragmentProgram
,
1223 &brw
->fragment_program
->Base
);
1224 sampler
= c
->fp
->program
.Base
.SamplerUnits
[sampler
];
1226 /* The 965 requires the EU to do the normalization of GL rectangle
1227 * texture coordinates. We use the program parameter state
1228 * tracking to get the scaling factor.
1230 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1231 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1232 int tokens
[STATE_LENGTH
] = {
1234 STATE_TEXRECT_SCALE
,
1240 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
1242 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
+ 1] =
1245 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1246 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1247 GLuint index
= _mesa_add_state_reference(params
,
1248 (gl_state_index
*)tokens
);
1249 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
1251 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[0];
1252 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[1];
1254 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1255 fs_reg src
= coordinate
;
1258 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_x
));
1261 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_y
));
1264 /* Writemasking doesn't eliminate channels on SIMD8 texture
1265 * samples, so don't worry about them.
1267 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1269 if (intel
->gen
< 5) {
1270 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1272 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1275 inst
->sampler
= sampler
;
1279 if (ir
->shadow_comparitor
)
1280 inst
->shadow_compare
= true;
1282 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1283 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1285 for (int i
= 0; i
< 4; i
++) {
1286 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1287 fs_reg l
= swizzle_dst
;
1290 if (swiz
== SWIZZLE_ZERO
) {
1291 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1292 } else if (swiz
== SWIZZLE_ONE
) {
1293 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1296 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1297 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1300 this->result
= swizzle_dst
;
1305 fs_visitor::visit(ir_swizzle
*ir
)
1307 ir
->val
->accept(this);
1308 fs_reg val
= this->result
;
1310 if (ir
->type
->vector_elements
== 1) {
1311 this->result
.reg_offset
+= ir
->mask
.x
;
1315 fs_reg result
= fs_reg(this, ir
->type
);
1316 this->result
= result
;
1318 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1319 fs_reg channel
= val
;
1337 channel
.reg_offset
+= swiz
;
1338 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1339 result
.reg_offset
++;
1344 fs_visitor::visit(ir_discard
*ir
)
1346 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1348 assert(ir
->condition
== NULL
); /* FINISHME */
1350 emit(fs_inst(FS_OPCODE_DISCARD_NOT
, temp
, reg_null_d
));
1351 emit(fs_inst(FS_OPCODE_DISCARD_AND
, reg_null_d
, temp
));
1352 kill_emitted
= true;
1356 fs_visitor::visit(ir_constant
*ir
)
1358 fs_reg
reg(this, ir
->type
);
1361 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1362 switch (ir
->type
->base_type
) {
1363 case GLSL_TYPE_FLOAT
:
1364 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1366 case GLSL_TYPE_UINT
:
1367 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1370 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1372 case GLSL_TYPE_BOOL
:
1373 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1376 assert(!"Non-float/uint/int/bool constant");
1383 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1385 ir_expression
*expr
= ir
->as_expression();
1391 assert(expr
->get_num_operands() <= 2);
1392 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1393 assert(expr
->operands
[i
]->type
->is_scalar());
1395 expr
->operands
[i
]->accept(this);
1396 op
[i
] = this->result
;
1399 switch (expr
->operation
) {
1400 case ir_unop_logic_not
:
1401 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1)));
1402 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1405 case ir_binop_logic_xor
:
1406 inst
= emit(fs_inst(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]));
1407 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1410 case ir_binop_logic_or
:
1411 inst
= emit(fs_inst(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]));
1412 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1415 case ir_binop_logic_and
:
1416 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]));
1417 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1421 if (intel
->gen
>= 6) {
1422 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1423 op
[0], fs_reg(0.0f
)));
1425 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1427 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1431 if (intel
->gen
>= 6) {
1432 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0)));
1434 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1436 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1439 case ir_binop_greater
:
1440 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1441 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1443 case ir_binop_gequal
:
1444 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1445 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1448 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1449 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1451 case ir_binop_lequal
:
1452 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1453 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1455 case ir_binop_equal
:
1456 case ir_binop_all_equal
:
1457 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1458 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1460 case ir_binop_nequal
:
1461 case ir_binop_any_nequal
:
1462 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1463 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1466 assert(!"not reached");
1475 if (intel
->gen
>= 6) {
1476 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
,
1477 this->result
, fs_reg(1)));
1478 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1480 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, this->result
));
1481 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1486 * Emit a gen6 IF statement with the comparison folded into the IF
1490 fs_visitor::emit_if_gen6(ir_if
*ir
)
1492 ir_expression
*expr
= ir
->condition
->as_expression();
1499 assert(expr
->get_num_operands() <= 2);
1500 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1501 assert(expr
->operands
[i
]->type
->is_scalar());
1503 expr
->operands
[i
]->accept(this);
1504 op
[i
] = this->result
;
1507 switch (expr
->operation
) {
1508 case ir_unop_logic_not
:
1509 inst
= emit(fs_inst(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(1)));
1510 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1513 case ir_binop_logic_xor
:
1514 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1515 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1518 case ir_binop_logic_or
:
1519 temp
= fs_reg(this, glsl_type::bool_type
);
1520 emit(fs_inst(BRW_OPCODE_OR
, temp
, op
[0], op
[1]));
1521 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1522 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1525 case ir_binop_logic_and
:
1526 temp
= fs_reg(this, glsl_type::bool_type
);
1527 emit(fs_inst(BRW_OPCODE_AND
, temp
, op
[0], op
[1]));
1528 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1529 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1533 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0)));
1534 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1538 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1539 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1542 case ir_binop_greater
:
1543 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1544 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1546 case ir_binop_gequal
:
1547 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1548 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1551 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1552 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1554 case ir_binop_lequal
:
1555 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1556 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1558 case ir_binop_equal
:
1559 case ir_binop_all_equal
:
1560 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1561 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1563 case ir_binop_nequal
:
1564 case ir_binop_any_nequal
:
1565 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1566 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1569 assert(!"not reached");
1570 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1571 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1578 ir
->condition
->accept(this);
1580 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0)));
1581 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1585 fs_visitor::visit(ir_if
*ir
)
1589 /* Don't point the annotation at the if statement, because then it plus
1590 * the then and else blocks get printed.
1592 this->base_ir
= ir
->condition
;
1594 if (intel
->gen
>= 6) {
1597 emit_bool_to_cond_code(ir
->condition
);
1599 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1600 inst
->predicated
= true;
1603 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1604 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1610 if (!ir
->else_instructions
.is_empty()) {
1611 emit(fs_inst(BRW_OPCODE_ELSE
));
1613 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1614 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1621 emit(fs_inst(BRW_OPCODE_ENDIF
));
1625 fs_visitor::visit(ir_loop
*ir
)
1627 fs_reg counter
= reg_undef
;
1630 this->base_ir
= ir
->counter
;
1631 ir
->counter
->accept(this);
1632 counter
= *(variable_storage(ir
->counter
));
1635 this->base_ir
= ir
->from
;
1636 ir
->from
->accept(this);
1638 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1642 emit(fs_inst(BRW_OPCODE_DO
));
1645 this->base_ir
= ir
->to
;
1646 ir
->to
->accept(this);
1648 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1649 counter
, this->result
));
1651 case ir_binop_equal
:
1652 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1654 case ir_binop_nequal
:
1655 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1657 case ir_binop_gequal
:
1658 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1660 case ir_binop_lequal
:
1661 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1663 case ir_binop_greater
:
1664 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1667 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1670 assert(!"not reached: unknown loop condition");
1675 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1676 inst
->predicated
= true;
1679 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1680 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1686 if (ir
->increment
) {
1687 this->base_ir
= ir
->increment
;
1688 ir
->increment
->accept(this);
1689 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1692 emit(fs_inst(BRW_OPCODE_WHILE
));
1696 fs_visitor::visit(ir_loop_jump
*ir
)
1699 case ir_loop_jump::jump_break
:
1700 emit(fs_inst(BRW_OPCODE_BREAK
));
1702 case ir_loop_jump::jump_continue
:
1703 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1709 fs_visitor::visit(ir_call
*ir
)
1711 assert(!"FINISHME");
1715 fs_visitor::visit(ir_return
*ir
)
1717 assert(!"FINISHME");
1721 fs_visitor::visit(ir_function
*ir
)
1723 /* Ignore function bodies other than main() -- we shouldn't see calls to
1724 * them since they should all be inlined before we get to ir_to_mesa.
1726 if (strcmp(ir
->name
, "main") == 0) {
1727 const ir_function_signature
*sig
;
1730 sig
= ir
->matching_signature(&empty
);
1734 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1735 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1744 fs_visitor::visit(ir_function_signature
*ir
)
1746 assert(!"not reached");
1751 fs_visitor::emit(fs_inst inst
)
1753 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1756 list_inst
->annotation
= this->current_annotation
;
1757 list_inst
->ir
= this->base_ir
;
1759 this->instructions
.push_tail(list_inst
);
1764 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1766 fs_visitor::emit_dummy_fs()
1768 /* Everyone's favorite color. */
1769 emit(fs_inst(BRW_OPCODE_MOV
,
1772 emit(fs_inst(BRW_OPCODE_MOV
,
1775 emit(fs_inst(BRW_OPCODE_MOV
,
1778 emit(fs_inst(BRW_OPCODE_MOV
,
1783 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1786 write
->base_mrf
= 0;
1789 /* The register location here is relative to the start of the URB
1790 * data. It will get adjusted to be a real location before
1791 * generate_code() time.
1794 fs_visitor::interp_reg(int location
, int channel
)
1796 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1797 int stride
= (channel
& 1) * 4;
1799 assert(urb_setup
[location
] != -1);
1801 return brw_vec1_grf(regnr
, stride
);
1804 /** Emits the interpolation for the varying inputs. */
1806 fs_visitor::emit_interpolation_setup_gen4()
1808 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1810 this->current_annotation
= "compute pixel centers";
1811 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1812 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1813 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1814 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1815 emit(fs_inst(BRW_OPCODE_ADD
,
1817 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1818 fs_reg(brw_imm_v(0x10101010))));
1819 emit(fs_inst(BRW_OPCODE_ADD
,
1821 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1822 fs_reg(brw_imm_v(0x11001100))));
1824 this->current_annotation
= "compute pixel deltas from v0";
1826 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1827 this->delta_y
= this->delta_x
;
1828 this->delta_y
.reg_offset
++;
1830 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1831 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1833 emit(fs_inst(BRW_OPCODE_ADD
,
1836 fs_reg(negate(brw_vec1_grf(1, 0)))));
1837 emit(fs_inst(BRW_OPCODE_ADD
,
1840 fs_reg(negate(brw_vec1_grf(1, 1)))));
1842 this->current_annotation
= "compute pos.w and 1/pos.w";
1843 /* Compute wpos.w. It's always in our setup, since it's needed to
1844 * interpolate the other attributes.
1846 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1847 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1848 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1849 /* Compute the pixel 1/W value from wpos.w. */
1850 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1851 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1852 this->current_annotation
= NULL
;
1855 /** Emits the interpolation for the varying inputs. */
1857 fs_visitor::emit_interpolation_setup_gen6()
1859 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1861 /* If the pixel centers end up used, the setup is the same as for gen4. */
1862 this->current_annotation
= "compute pixel centers";
1863 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1864 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1865 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1866 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1867 emit(fs_inst(BRW_OPCODE_ADD
,
1869 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1870 fs_reg(brw_imm_v(0x10101010))));
1871 emit(fs_inst(BRW_OPCODE_ADD
,
1873 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1874 fs_reg(brw_imm_v(0x11001100))));
1876 /* As of gen6, we can no longer mix float and int sources. We have
1877 * to turn the integer pixel centers into floats for their actual
1880 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1881 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1882 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
));
1883 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
));
1885 this->current_annotation
= "compute 1/pos.w";
1886 this->wpos_w
= fs_reg(brw_vec8_grf(c
->key
.source_w_reg
, 0));
1887 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1888 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1890 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1891 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1893 this->current_annotation
= NULL
;
1897 fs_visitor::emit_fb_writes()
1899 this->current_annotation
= "FB write header";
1900 GLboolean header_present
= GL_TRUE
;
1903 if (intel
->gen
>= 6 &&
1904 !this->kill_emitted
&&
1905 c
->key
.nr_color_regions
== 1) {
1906 header_present
= false;
1909 if (header_present
) {
1914 if (c
->key
.aa_dest_stencil_reg
) {
1915 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1916 fs_reg(brw_vec8_grf(c
->key
.aa_dest_stencil_reg
, 0))));
1919 /* Reserve space for color. It'll be filled in per MRT below. */
1923 if (c
->key
.source_depth_to_render_target
) {
1924 if (c
->key
.computes_depth
) {
1925 /* Hand over gl_FragDepth. */
1926 assert(this->frag_depth
);
1927 fs_reg depth
= *(variable_storage(this->frag_depth
));
1929 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
1931 /* Pass through the payload depth. */
1932 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1933 fs_reg(brw_vec8_grf(c
->key
.source_depth_reg
, 0))));
1937 if (c
->key
.dest_depth_reg
) {
1938 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1939 fs_reg(brw_vec8_grf(c
->key
.dest_depth_reg
, 0))));
1942 fs_reg color
= reg_undef
;
1943 if (this->frag_color
)
1944 color
= *(variable_storage(this->frag_color
));
1945 else if (this->frag_data
)
1946 color
= *(variable_storage(this->frag_data
));
1948 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1949 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1950 "FB write target %d",
1952 if (this->frag_color
|| this->frag_data
) {
1953 for (int i
= 0; i
< 4; i
++) {
1954 emit(fs_inst(BRW_OPCODE_MOV
,
1955 fs_reg(MRF
, color_mrf
+ i
),
1961 if (this->frag_color
)
1962 color
.reg_offset
-= 4;
1964 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1965 reg_undef
, reg_undef
));
1966 inst
->target
= target
;
1969 if (target
== c
->key
.nr_color_regions
- 1)
1971 inst
->header_present
= header_present
;
1974 if (c
->key
.nr_color_regions
== 0) {
1975 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1976 reg_undef
, reg_undef
));
1980 inst
->header_present
= header_present
;
1983 this->current_annotation
= NULL
;
1987 fs_visitor::generate_fb_write(fs_inst
*inst
)
1989 GLboolean eot
= inst
->eot
;
1990 struct brw_reg implied_header
;
1992 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1995 brw_push_insn_state(p
);
1996 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1997 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1999 if (inst
->header_present
) {
2000 if (intel
->gen
>= 6) {
2002 brw_message_reg(inst
->base_mrf
),
2003 brw_vec8_grf(0, 0));
2005 if (inst
->target
> 0) {
2006 /* Set the render target index for choosing BLEND_STATE. */
2007 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 2),
2008 BRW_REGISTER_TYPE_UD
),
2009 brw_imm_ud(inst
->target
));
2012 /* Clear viewport index, render target array index. */
2013 brw_AND(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 0),
2014 BRW_REGISTER_TYPE_UD
),
2015 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2016 brw_imm_ud(0xf7ff));
2018 implied_header
= brw_null_reg();
2020 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2024 brw_message_reg(inst
->base_mrf
+ 1),
2025 brw_vec8_grf(1, 0));
2027 implied_header
= brw_null_reg();
2030 brw_pop_insn_state(p
);
2033 8, /* dispatch_width */
2034 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
2044 fs_visitor::generate_linterp(fs_inst
*inst
,
2045 struct brw_reg dst
, struct brw_reg
*src
)
2047 struct brw_reg delta_x
= src
[0];
2048 struct brw_reg delta_y
= src
[1];
2049 struct brw_reg interp
= src
[2];
2052 delta_y
.nr
== delta_x
.nr
+ 1 &&
2053 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2054 brw_PLN(p
, dst
, interp
, delta_x
);
2056 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2057 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2062 fs_visitor::generate_math(fs_inst
*inst
,
2063 struct brw_reg dst
, struct brw_reg
*src
)
2067 switch (inst
->opcode
) {
2069 op
= BRW_MATH_FUNCTION_INV
;
2072 op
= BRW_MATH_FUNCTION_RSQ
;
2074 case FS_OPCODE_SQRT
:
2075 op
= BRW_MATH_FUNCTION_SQRT
;
2077 case FS_OPCODE_EXP2
:
2078 op
= BRW_MATH_FUNCTION_EXP
;
2080 case FS_OPCODE_LOG2
:
2081 op
= BRW_MATH_FUNCTION_LOG
;
2084 op
= BRW_MATH_FUNCTION_POW
;
2087 op
= BRW_MATH_FUNCTION_SIN
;
2090 op
= BRW_MATH_FUNCTION_COS
;
2093 assert(!"not reached: unknown math function");
2098 if (intel
->gen
>= 6) {
2099 assert(inst
->mlen
== 0);
2101 if (inst
->opcode
== FS_OPCODE_POW
) {
2102 brw_math2(p
, dst
, op
, src
[0], src
[1]);
2106 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2107 BRW_MATH_SATURATE_NONE
,
2109 BRW_MATH_DATA_VECTOR
,
2110 BRW_MATH_PRECISION_FULL
);
2113 assert(inst
->mlen
>= 1);
2117 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2118 BRW_MATH_SATURATE_NONE
,
2119 inst
->base_mrf
, src
[0],
2120 BRW_MATH_DATA_VECTOR
,
2121 BRW_MATH_PRECISION_FULL
);
2126 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
)
2130 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2132 if (intel
->gen
>= 5) {
2133 switch (inst
->opcode
) {
2135 if (inst
->shadow_compare
) {
2136 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2138 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2142 if (inst
->shadow_compare
) {
2143 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2145 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2150 switch (inst
->opcode
) {
2152 /* Note that G45 and older determines shadow compare and dispatch width
2153 * from message length for most messages.
2155 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2156 if (inst
->shadow_compare
) {
2157 assert(inst
->mlen
== 6);
2159 assert(inst
->mlen
<= 4);
2163 if (inst
->shadow_compare
) {
2164 assert(inst
->mlen
== 6);
2165 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2167 assert(inst
->mlen
== 9);
2168 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2169 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2174 assert(msg_type
!= -1);
2176 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2182 retype(dst
, BRW_REGISTER_TYPE_UW
),
2184 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2185 SURF_INDEX_TEXTURE(inst
->sampler
),
2197 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2200 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2202 * and we're trying to produce:
2205 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2206 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2207 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2208 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2209 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2210 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2211 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2212 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2214 * and add another set of two more subspans if in 16-pixel dispatch mode.
2216 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2217 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2218 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2219 * between each other. We could probably do it like ddx and swizzle the right
2220 * order later, but bail for now and just produce
2221 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2224 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2226 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2227 BRW_REGISTER_TYPE_F
,
2228 BRW_VERTICAL_STRIDE_2
,
2230 BRW_HORIZONTAL_STRIDE_0
,
2231 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2232 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2233 BRW_REGISTER_TYPE_F
,
2234 BRW_VERTICAL_STRIDE_2
,
2236 BRW_HORIZONTAL_STRIDE_0
,
2237 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2238 brw_ADD(p
, dst
, src0
, negate(src1
));
2242 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2244 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2245 BRW_REGISTER_TYPE_F
,
2246 BRW_VERTICAL_STRIDE_4
,
2248 BRW_HORIZONTAL_STRIDE_0
,
2249 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2250 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2251 BRW_REGISTER_TYPE_F
,
2252 BRW_VERTICAL_STRIDE_4
,
2254 BRW_HORIZONTAL_STRIDE_0
,
2255 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2256 brw_ADD(p
, dst
, src0
, negate(src1
));
2260 fs_visitor::generate_discard_not(fs_inst
*inst
, struct brw_reg mask
)
2262 if (intel
->gen
>= 6) {
2263 /* Gen6 no longer has the mask reg for us to just read the
2264 * active channels from. However, cmp updates just the channels
2265 * of the flag reg that are enabled, so we can get at the
2266 * channel enables that way. In this step, make a reg of ones
2269 brw_MOV(p
, mask
, brw_imm_ud(1));
2271 brw_push_insn_state(p
);
2272 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2273 brw_NOT(p
, mask
, brw_mask_reg(1)); /* IMASK */
2274 brw_pop_insn_state(p
);
2279 fs_visitor::generate_discard_and(fs_inst
*inst
, struct brw_reg mask
)
2281 if (intel
->gen
>= 6) {
2282 struct brw_reg f0
= brw_flag_reg();
2283 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
2285 brw_push_insn_state(p
);
2286 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2287 brw_MOV(p
, f0
, brw_imm_uw(0xffff)); /* inactive channels undiscarded */
2288 brw_pop_insn_state(p
);
2290 brw_CMP(p
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
2291 BRW_CONDITIONAL_Z
, mask
, brw_imm_ud(0)); /* active channels fail test */
2292 /* Undo CMP's whacking of predication*/
2293 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2295 brw_push_insn_state(p
);
2296 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2297 brw_AND(p
, g1
, f0
, g1
);
2298 brw_pop_insn_state(p
);
2300 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2302 mask
= brw_uw1_reg(mask
.file
, mask
.nr
, 0);
2304 brw_push_insn_state(p
);
2305 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2306 brw_AND(p
, g0
, mask
, g0
);
2307 brw_pop_insn_state(p
);
2312 fs_visitor::generate_spill(fs_inst
*inst
, struct brw_reg src
)
2314 assert(inst
->mlen
!= 0);
2317 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
2318 retype(src
, BRW_REGISTER_TYPE_UD
));
2319 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
), 1,
2324 fs_visitor::generate_unspill(fs_inst
*inst
, struct brw_reg dst
)
2326 assert(inst
->mlen
!= 0);
2328 /* Clear any post destination dependencies that would be ignored by
2329 * the block read. See the B-Spec for pre-gen5 send instruction.
2331 * This could use a better solution, since texture sampling and
2332 * math reads could potentially run into it as well -- anywhere
2333 * that we have a SEND with a destination that is a register that
2334 * was written but not read within the last N instructions (what's
2335 * N? unsure). This is rare because of dead code elimination, but
2338 if (intel
->gen
== 4 && !intel
->is_g4x
)
2339 brw_MOV(p
, brw_null_reg(), dst
);
2341 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
), 1,
2344 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2345 /* gen4 errata: destination from a send can't be used as a
2346 * destination until it's been read. Just read it so we don't
2349 brw_MOV(p
, brw_null_reg(), dst
);
2355 fs_visitor::generate_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
)
2357 assert(inst
->mlen
!= 0);
2359 /* Clear any post destination dependencies that would be ignored by
2360 * the block read. See the B-Spec for pre-gen5 send instruction.
2362 * This could use a better solution, since texture sampling and
2363 * math reads could potentially run into it as well -- anywhere
2364 * that we have a SEND with a destination that is a register that
2365 * was written but not read within the last N instructions (what's
2366 * N? unsure). This is rare because of dead code elimination, but
2369 if (intel
->gen
== 4 && !intel
->is_g4x
)
2370 brw_MOV(p
, brw_null_reg(), dst
);
2372 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
2373 inst
->offset
, SURF_INDEX_FRAG_CONST_BUFFER
);
2375 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2376 /* gen4 errata: destination from a send can't be used as a
2377 * destination until it's been read. Just read it so we don't
2380 brw_MOV(p
, brw_null_reg(), dst
);
2385 fs_visitor::assign_curb_setup()
2387 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
2388 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2390 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2391 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2392 fs_inst
*inst
= (fs_inst
*)iter
.get();
2394 for (unsigned int i
= 0; i
< 3; i
++) {
2395 if (inst
->src
[i
].file
== UNIFORM
) {
2396 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2397 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2401 inst
->src
[i
].file
= FIXED_HW_REG
;
2402 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
2409 fs_visitor::calculate_urb_setup()
2411 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2416 /* Figure out where each of the incoming setup attributes lands. */
2417 if (intel
->gen
>= 6) {
2418 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2419 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2420 urb_setup
[i
] = urb_next
++;
2424 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2425 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2426 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2429 if (i
>= VERT_RESULT_VAR0
)
2430 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2431 else if (i
<= VERT_RESULT_TEX7
)
2437 urb_setup
[fp_index
] = urb_next
++;
2442 /* Each attribute is 4 setup channels, each of which is half a reg. */
2443 c
->prog_data
.urb_read_length
= urb_next
* 2;
2447 fs_visitor::assign_urb_setup()
2449 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2451 /* Offset all the urb_setup[] index by the actual position of the
2452 * setup regs, now that the location of the constants has been chosen.
2454 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2455 fs_inst
*inst
= (fs_inst
*)iter
.get();
2457 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2460 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2462 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2465 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2469 * Split large virtual GRFs into separate components if we can.
2471 * This is mostly duplicated with what brw_fs_vector_splitting does,
2472 * but that's really conservative because it's afraid of doing
2473 * splitting that doesn't result in real progress after the rest of
2474 * the optimization phases, which would cause infinite looping in
2475 * optimization. We can do it once here, safely. This also has the
2476 * opportunity to split interpolated values, or maybe even uniforms,
2477 * which we don't have at the IR level.
2479 * We want to split, because virtual GRFs are what we register
2480 * allocate and spill (due to contiguousness requirements for some
2481 * instructions), and they're what we naturally generate in the
2482 * codegen process, but most virtual GRFs don't actually need to be
2483 * contiguous sets of GRFs. If we split, we'll end up with reduced
2484 * live intervals and better dead code elimination and coalescing.
2487 fs_visitor::split_virtual_grfs()
2489 int num_vars
= this->virtual_grf_next
;
2490 bool split_grf
[num_vars
];
2491 int new_virtual_grf
[num_vars
];
2493 /* Try to split anything > 0 sized. */
2494 for (int i
= 0; i
< num_vars
; i
++) {
2495 if (this->virtual_grf_sizes
[i
] != 1)
2496 split_grf
[i
] = true;
2498 split_grf
[i
] = false;
2502 /* PLN opcodes rely on the delta_xy being contiguous. */
2503 split_grf
[this->delta_x
.reg
] = false;
2506 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2507 fs_inst
*inst
= (fs_inst
*)iter
.get();
2509 /* Texturing produces 4 contiguous registers, so no splitting. */
2510 if ((inst
->opcode
== FS_OPCODE_TEX
||
2511 inst
->opcode
== FS_OPCODE_TXB
||
2512 inst
->opcode
== FS_OPCODE_TXL
) &&
2513 inst
->dst
.file
== GRF
) {
2514 split_grf
[inst
->dst
.reg
] = false;
2518 /* Allocate new space for split regs. Note that the virtual
2519 * numbers will be contiguous.
2521 for (int i
= 0; i
< num_vars
; i
++) {
2523 new_virtual_grf
[i
] = virtual_grf_alloc(1);
2524 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
2525 int reg
= virtual_grf_alloc(1);
2526 assert(reg
== new_virtual_grf
[i
] + j
- 1);
2529 this->virtual_grf_sizes
[i
] = 1;
2533 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2534 fs_inst
*inst
= (fs_inst
*)iter
.get();
2536 if (inst
->dst
.file
== GRF
&&
2537 split_grf
[inst
->dst
.reg
] &&
2538 inst
->dst
.reg_offset
!= 0) {
2539 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
2540 inst
->dst
.reg_offset
- 1);
2541 inst
->dst
.reg_offset
= 0;
2543 for (int i
= 0; i
< 3; i
++) {
2544 if (inst
->src
[i
].file
== GRF
&&
2545 split_grf
[inst
->src
[i
].reg
] &&
2546 inst
->src
[i
].reg_offset
!= 0) {
2547 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
2548 inst
->src
[i
].reg_offset
- 1);
2549 inst
->src
[i
].reg_offset
= 0;
2556 * Choose accesses from the UNIFORM file to demote to using the pull
2559 * We allow a fragment shader to have more than the specified minimum
2560 * maximum number of fragment shader uniform components (64). If
2561 * there are too many of these, they'd fill up all of register space.
2562 * So, this will push some of them out to the pull constant buffer and
2563 * update the program to load them.
2566 fs_visitor::setup_pull_constants()
2568 /* Only allow 16 registers (128 uniform components) as push constants. */
2569 unsigned int max_uniform_components
= 16 * 8;
2570 if (c
->prog_data
.nr_params
<= max_uniform_components
)
2573 /* Just demote the end of the list. We could probably do better
2574 * here, demoting things that are rarely used in the program first.
2576 int pull_uniform_base
= max_uniform_components
;
2577 int pull_uniform_count
= c
->prog_data
.nr_params
- pull_uniform_base
;
2579 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2580 fs_inst
*inst
= (fs_inst
*)iter
.get();
2582 for (int i
= 0; i
< 3; i
++) {
2583 if (inst
->src
[i
].file
!= UNIFORM
)
2586 int uniform_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2587 if (uniform_nr
< pull_uniform_base
)
2590 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
2591 fs_inst
*pull
= new(mem_ctx
) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
2593 pull
->offset
= ((uniform_nr
- pull_uniform_base
) * 4) & ~15;
2594 pull
->ir
= inst
->ir
;
2595 pull
->annotation
= inst
->annotation
;
2596 pull
->base_mrf
= 14;
2599 inst
->insert_before(pull
);
2601 inst
->src
[i
].file
= GRF
;
2602 inst
->src
[i
].reg
= dst
.reg
;
2603 inst
->src
[i
].reg_offset
= 0;
2604 inst
->src
[i
].smear
= (uniform_nr
- pull_uniform_base
) & 3;
2608 for (int i
= 0; i
< pull_uniform_count
; i
++) {
2609 c
->prog_data
.pull_param
[i
] = c
->prog_data
.param
[pull_uniform_base
+ i
];
2610 c
->prog_data
.pull_param_convert
[i
] =
2611 c
->prog_data
.param_convert
[pull_uniform_base
+ i
];
2613 c
->prog_data
.nr_params
-= pull_uniform_count
;
2614 c
->prog_data
.nr_pull_params
= pull_uniform_count
;
2618 fs_visitor::calculate_live_intervals()
2620 int num_vars
= this->virtual_grf_next
;
2621 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2622 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2625 int bb_header_ip
= 0;
2627 for (int i
= 0; i
< num_vars
; i
++) {
2633 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2634 fs_inst
*inst
= (fs_inst
*)iter
.get();
2636 if (inst
->opcode
== BRW_OPCODE_DO
) {
2637 if (loop_depth
++ == 0)
2639 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2642 if (loop_depth
== 0) {
2643 /* Patches up the use of vars marked for being live across
2646 for (int i
= 0; i
< num_vars
; i
++) {
2647 if (use
[i
] == loop_start
) {
2653 for (unsigned int i
= 0; i
< 3; i
++) {
2654 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2655 int reg
= inst
->src
[i
].reg
;
2657 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2658 def
[reg
] >= bb_header_ip
)) {
2661 def
[reg
] = MIN2(loop_start
, def
[reg
]);
2662 use
[reg
] = loop_start
;
2664 /* Nobody else is going to go smash our start to
2665 * later in the loop now, because def[reg] now
2666 * points before the bb header.
2671 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2672 int reg
= inst
->dst
.reg
;
2674 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2675 !inst
->predicated
)) {
2676 def
[reg
] = MIN2(def
[reg
], ip
);
2678 def
[reg
] = MIN2(def
[reg
], loop_start
);
2685 /* Set the basic block header IP. This is used for determining
2686 * if a complete def of single-register virtual GRF in a loop
2687 * dominates a use in the same basic block. It's a quick way to
2688 * reduce the live interval range of most register used in a
2691 if (inst
->opcode
== BRW_OPCODE_IF
||
2692 inst
->opcode
== BRW_OPCODE_ELSE
||
2693 inst
->opcode
== BRW_OPCODE_ENDIF
||
2694 inst
->opcode
== BRW_OPCODE_DO
||
2695 inst
->opcode
== BRW_OPCODE_WHILE
||
2696 inst
->opcode
== BRW_OPCODE_BREAK
||
2697 inst
->opcode
== BRW_OPCODE_CONTINUE
) {
2702 talloc_free(this->virtual_grf_def
);
2703 talloc_free(this->virtual_grf_use
);
2704 this->virtual_grf_def
= def
;
2705 this->virtual_grf_use
= use
;
2709 * Attempts to move immediate constants into the immediate
2710 * constant slot of following instructions.
2712 * Immediate constants are a bit tricky -- they have to be in the last
2713 * operand slot, you can't do abs/negate on them,
2717 fs_visitor::propagate_constants()
2719 bool progress
= false;
2721 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2722 fs_inst
*inst
= (fs_inst
*)iter
.get();
2724 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2726 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2727 inst
->dst
.type
!= inst
->src
[0].type
)
2730 /* Don't bother with cases where we should have had the
2731 * operation on the constant folded in GLSL already.
2736 /* Found a move of a constant to a GRF. Find anything else using the GRF
2737 * before it's written, and replace it with the constant if we can.
2739 exec_list_iterator scan_iter
= iter
;
2741 for (; scan_iter
.has_next(); scan_iter
.next()) {
2742 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2744 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2745 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2746 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2747 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2751 for (int i
= 2; i
>= 0; i
--) {
2752 if (scan_inst
->src
[i
].file
!= GRF
||
2753 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2754 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2757 /* Don't bother with cases where we should have had the
2758 * operation on the constant folded in GLSL already.
2760 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2763 switch (scan_inst
->opcode
) {
2764 case BRW_OPCODE_MOV
:
2765 scan_inst
->src
[i
] = inst
->src
[0];
2769 case BRW_OPCODE_MUL
:
2770 case BRW_OPCODE_ADD
:
2772 scan_inst
->src
[i
] = inst
->src
[0];
2774 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2775 /* Fit this constant in by commuting the operands */
2776 scan_inst
->src
[0] = scan_inst
->src
[1];
2777 scan_inst
->src
[1] = inst
->src
[0];
2780 case BRW_OPCODE_CMP
:
2782 scan_inst
->src
[i
] = inst
->src
[0];
2788 if (scan_inst
->dst
.file
== GRF
&&
2789 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2790 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2791 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2800 * Must be called after calculate_live_intervales() to remove unused
2801 * writes to registers -- register allocation will fail otherwise
2802 * because something deffed but not used won't be considered to
2803 * interfere with other regs.
2806 fs_visitor::dead_code_eliminate()
2808 bool progress
= false;
2811 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2812 fs_inst
*inst
= (fs_inst
*)iter
.get();
2814 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
2826 fs_visitor::register_coalesce()
2828 bool progress
= false;
2830 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2831 fs_inst
*inst
= (fs_inst
*)iter
.get();
2833 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2836 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
2837 inst
->dst
.type
!= inst
->src
[0].type
)
2840 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
2841 * them: check for no writes to either one until the exit of the
2844 bool interfered
= false;
2845 exec_list_iterator scan_iter
= iter
;
2847 for (; scan_iter
.has_next(); scan_iter
.next()) {
2848 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2850 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2851 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2852 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2858 if (scan_inst
->dst
.file
== GRF
) {
2859 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2860 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2861 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2865 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
2866 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
2867 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2877 /* Update live interval so we don't have to recalculate. */
2878 this->virtual_grf_use
[inst
->src
[0].reg
] = MAX2(virtual_grf_use
[inst
->src
[0].reg
],
2879 virtual_grf_use
[inst
->dst
.reg
]);
2881 /* Rewrite the later usage to point at the source of the move to
2884 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
2886 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2888 for (int i
= 0; i
< 3; i
++) {
2889 if (scan_inst
->src
[i
].file
== GRF
&&
2890 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
2891 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
2892 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
2893 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
2894 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
2895 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
2896 scan_inst
->src
[i
].smear
= inst
->src
[0].smear
;
2910 fs_visitor::compute_to_mrf()
2912 bool progress
= false;
2915 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2916 fs_inst
*inst
= (fs_inst
*)iter
.get();
2921 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2923 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2924 inst
->dst
.type
!= inst
->src
[0].type
||
2925 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
2928 /* Can't compute-to-MRF this GRF if someone else was going to
2931 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
2934 /* Found a move of a GRF to a MRF. Let's see if we can go
2935 * rewrite the thing that made this GRF to write into the MRF.
2939 for (scan_inst
= (fs_inst
*)inst
->prev
;
2940 scan_inst
->prev
!= NULL
;
2941 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2942 /* We don't handle flow control here. Most computation of
2943 * values that end up in MRFs are shortly before the MRF
2946 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2947 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2948 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2952 /* You can't read from an MRF, so if someone else reads our
2953 * MRF's source GRF that we wanted to rewrite, that stops us.
2955 bool interfered
= false;
2956 for (int i
= 0; i
< 3; i
++) {
2957 if (scan_inst
->src
[i
].file
== GRF
&&
2958 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2959 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2966 if (scan_inst
->dst
.file
== MRF
&&
2967 scan_inst
->dst
.hw_reg
== inst
->dst
.hw_reg
) {
2968 /* Somebody else wrote our MRF here, so we can't can't
2969 * compute-to-MRF before that.
2974 if (scan_inst
->mlen
> 0) {
2975 /* Found a SEND instruction, which will do some amount of
2976 * implied write that may overwrite our MRF that we were
2977 * hoping to compute-to-MRF somewhere above it. Nothing
2978 * we have implied-writes more than 2 MRFs from base_mrf,
2981 int implied_write_len
= MIN2(scan_inst
->mlen
, 2);
2982 if (inst
->dst
.hw_reg
>= scan_inst
->base_mrf
&&
2983 inst
->dst
.hw_reg
< scan_inst
->base_mrf
+ implied_write_len
) {
2988 if (scan_inst
->dst
.file
== GRF
&&
2989 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2990 /* Found the last thing to write our reg we want to turn
2991 * into a compute-to-MRF.
2994 if (scan_inst
->opcode
== FS_OPCODE_TEX
) {
2995 /* texturing writes several continuous regs, so we can't
2996 * compute-to-mrf that.
3001 /* If it's predicated, it (probably) didn't populate all
3004 if (scan_inst
->predicated
)
3007 /* SEND instructions can't have MRF as a destination. */
3008 if (scan_inst
->mlen
)
3011 if (intel
->gen
>= 6) {
3012 /* gen6 math instructions must have the destination be
3013 * GRF, so no compute-to-MRF for them.
3015 if (scan_inst
->opcode
== FS_OPCODE_RCP
||
3016 scan_inst
->opcode
== FS_OPCODE_RSQ
||
3017 scan_inst
->opcode
== FS_OPCODE_SQRT
||
3018 scan_inst
->opcode
== FS_OPCODE_EXP2
||
3019 scan_inst
->opcode
== FS_OPCODE_LOG2
||
3020 scan_inst
->opcode
== FS_OPCODE_SIN
||
3021 scan_inst
->opcode
== FS_OPCODE_COS
||
3022 scan_inst
->opcode
== FS_OPCODE_POW
) {
3027 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
3028 /* Found the creator of our MRF's source value. */
3035 scan_inst
->dst
.file
= MRF
;
3036 scan_inst
->dst
.hw_reg
= inst
->dst
.hw_reg
;
3037 scan_inst
->saturate
|= inst
->saturate
;
3047 fs_visitor::virtual_grf_interferes(int a
, int b
)
3049 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
3050 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
3052 /* For dead code, just check if the def interferes with the other range. */
3053 if (this->virtual_grf_use
[a
] == -1) {
3054 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
3055 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
3057 if (this->virtual_grf_use
[b
] == -1) {
3058 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
3059 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
3065 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
3067 struct brw_reg brw_reg
;
3069 switch (reg
->file
) {
3073 if (reg
->smear
== -1) {
3074 brw_reg
= brw_vec8_reg(reg
->file
,
3077 brw_reg
= brw_vec1_reg(reg
->file
,
3078 reg
->hw_reg
, reg
->smear
);
3080 brw_reg
= retype(brw_reg
, reg
->type
);
3083 switch (reg
->type
) {
3084 case BRW_REGISTER_TYPE_F
:
3085 brw_reg
= brw_imm_f(reg
->imm
.f
);
3087 case BRW_REGISTER_TYPE_D
:
3088 brw_reg
= brw_imm_d(reg
->imm
.i
);
3090 case BRW_REGISTER_TYPE_UD
:
3091 brw_reg
= brw_imm_ud(reg
->imm
.u
);
3094 assert(!"not reached");
3099 brw_reg
= reg
->fixed_hw_reg
;
3102 /* Probably unused. */
3103 brw_reg
= brw_null_reg();
3106 assert(!"not reached");
3107 brw_reg
= brw_null_reg();
3111 brw_reg
= brw_abs(brw_reg
);
3113 brw_reg
= negate(brw_reg
);
3119 fs_visitor::generate_code()
3121 int last_native_inst
= 0;
3122 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
3123 int if_stack_depth
= 0, loop_stack_depth
= 0;
3124 int if_depth_in_loop
[16];
3125 const char *last_annotation_string
= NULL
;
3126 ir_instruction
*last_annotation_ir
= NULL
;
3128 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3129 printf("Native code for fragment shader %d:\n",
3130 ctx
->Shader
.CurrentFragmentProgram
->Name
);
3133 if_depth_in_loop
[loop_stack_depth
] = 0;
3135 memset(&if_stack
, 0, sizeof(if_stack
));
3136 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3137 fs_inst
*inst
= (fs_inst
*)iter
.get();
3138 struct brw_reg src
[3], dst
;
3140 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3141 if (last_annotation_ir
!= inst
->ir
) {
3142 last_annotation_ir
= inst
->ir
;
3143 if (last_annotation_ir
) {
3145 last_annotation_ir
->print();
3149 if (last_annotation_string
!= inst
->annotation
) {
3150 last_annotation_string
= inst
->annotation
;
3151 if (last_annotation_string
)
3152 printf(" %s\n", last_annotation_string
);
3156 for (unsigned int i
= 0; i
< 3; i
++) {
3157 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
3159 dst
= brw_reg_from_fs_reg(&inst
->dst
);
3161 brw_set_conditionalmod(p
, inst
->conditional_mod
);
3162 brw_set_predicate_control(p
, inst
->predicated
);
3164 switch (inst
->opcode
) {
3165 case BRW_OPCODE_MOV
:
3166 brw_MOV(p
, dst
, src
[0]);
3168 case BRW_OPCODE_ADD
:
3169 brw_ADD(p
, dst
, src
[0], src
[1]);
3171 case BRW_OPCODE_MUL
:
3172 brw_MUL(p
, dst
, src
[0], src
[1]);
3175 case BRW_OPCODE_FRC
:
3176 brw_FRC(p
, dst
, src
[0]);
3178 case BRW_OPCODE_RNDD
:
3179 brw_RNDD(p
, dst
, src
[0]);
3181 case BRW_OPCODE_RNDE
:
3182 brw_RNDE(p
, dst
, src
[0]);
3184 case BRW_OPCODE_RNDZ
:
3185 brw_RNDZ(p
, dst
, src
[0]);
3188 case BRW_OPCODE_AND
:
3189 brw_AND(p
, dst
, src
[0], src
[1]);
3192 brw_OR(p
, dst
, src
[0], src
[1]);
3194 case BRW_OPCODE_XOR
:
3195 brw_XOR(p
, dst
, src
[0], src
[1]);
3197 case BRW_OPCODE_NOT
:
3198 brw_NOT(p
, dst
, src
[0]);
3200 case BRW_OPCODE_ASR
:
3201 brw_ASR(p
, dst
, src
[0], src
[1]);
3203 case BRW_OPCODE_SHR
:
3204 brw_SHR(p
, dst
, src
[0], src
[1]);
3206 case BRW_OPCODE_SHL
:
3207 brw_SHL(p
, dst
, src
[0], src
[1]);
3210 case BRW_OPCODE_CMP
:
3211 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
3213 case BRW_OPCODE_SEL
:
3214 brw_SEL(p
, dst
, src
[0], src
[1]);
3218 assert(if_stack_depth
< 16);
3219 if (inst
->src
[0].file
!= BAD_FILE
) {
3220 assert(intel
->gen
>= 6);
3221 if_stack
[if_stack_depth
] = brw_IF_gen6(p
, inst
->conditional_mod
, src
[0], src
[1]);
3223 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
3225 if_depth_in_loop
[loop_stack_depth
]++;
3229 case BRW_OPCODE_ELSE
:
3230 if_stack
[if_stack_depth
- 1] =
3231 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
3233 case BRW_OPCODE_ENDIF
:
3235 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
3236 if_depth_in_loop
[loop_stack_depth
]--;
3240 /* FINISHME: We need to write the loop instruction support still. */
3241 if (intel
->gen
>= 6)
3244 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
3245 if_depth_in_loop
[loop_stack_depth
] = 0;
3248 case BRW_OPCODE_BREAK
:
3249 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
3250 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3252 case BRW_OPCODE_CONTINUE
:
3253 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
3254 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3257 case BRW_OPCODE_WHILE
: {
3258 struct brw_instruction
*inst0
, *inst1
;
3261 if (intel
->gen
>= 5)
3264 assert(loop_stack_depth
> 0);
3266 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
3267 /* patch all the BREAK/CONT instructions from last BGNLOOP */
3268 while (inst0
> loop_stack
[loop_stack_depth
]) {
3270 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
3271 inst0
->bits3
.if_else
.jump_count
== 0) {
3272 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
3274 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
3275 inst0
->bits3
.if_else
.jump_count
== 0) {
3276 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
3284 case FS_OPCODE_SQRT
:
3285 case FS_OPCODE_EXP2
:
3286 case FS_OPCODE_LOG2
:
3290 generate_math(inst
, dst
, src
);
3292 case FS_OPCODE_LINTERP
:
3293 generate_linterp(inst
, dst
, src
);
3298 generate_tex(inst
, dst
);
3300 case FS_OPCODE_DISCARD_NOT
:
3301 generate_discard_not(inst
, dst
);
3303 case FS_OPCODE_DISCARD_AND
:
3304 generate_discard_and(inst
, src
[0]);
3307 generate_ddx(inst
, dst
, src
[0]);
3310 generate_ddy(inst
, dst
, src
[0]);
3313 case FS_OPCODE_SPILL
:
3314 generate_spill(inst
, src
[0]);
3317 case FS_OPCODE_UNSPILL
:
3318 generate_unspill(inst
, dst
);
3321 case FS_OPCODE_PULL_CONSTANT_LOAD
:
3322 generate_pull_constant_load(inst
, dst
);
3325 case FS_OPCODE_FB_WRITE
:
3326 generate_fb_write(inst
);
3329 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
3330 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
3331 brw_opcodes
[inst
->opcode
].name
);
3333 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
3338 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3339 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
3341 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3342 ((uint32_t *)&p
->store
[i
])[3],
3343 ((uint32_t *)&p
->store
[i
])[2],
3344 ((uint32_t *)&p
->store
[i
])[1],
3345 ((uint32_t *)&p
->store
[i
])[0]);
3347 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3352 last_native_inst
= p
->nr_insn
;
3357 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
3359 struct intel_context
*intel
= &brw
->intel
;
3360 struct gl_context
*ctx
= &intel
->ctx
;
3361 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentFragmentProgram
;
3366 struct brw_shader
*shader
=
3367 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3371 /* We always use 8-wide mode, at least for now. For one, flow
3372 * control only works in 8-wide. Also, when we're fragment shader
3373 * bound, we're almost always under register pressure as well, so
3374 * 8-wide would save us from the performance cliff of spilling
3377 c
->dispatch_width
= 8;
3379 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3380 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3381 _mesa_print_ir(shader
->ir
, NULL
);
3385 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3387 fs_visitor
v(c
, shader
);
3392 v
.calculate_urb_setup();
3394 v
.emit_interpolation_setup_gen4();
3396 v
.emit_interpolation_setup_gen6();
3398 /* Generate FS IR for main(). (the visitor only descends into
3399 * functions called "main").
3401 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3402 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3409 v
.split_virtual_grfs();
3410 v
.setup_pull_constants();
3412 v
.assign_curb_setup();
3413 v
.assign_urb_setup();
3418 v
.calculate_live_intervals();
3419 progress
= v
.propagate_constants() || progress
;
3420 progress
= v
.register_coalesce() || progress
;
3421 progress
= v
.compute_to_mrf() || progress
;
3422 progress
= v
.dead_code_eliminate() || progress
;
3426 /* Debug of register spilling: Go spill everything. */
3427 int virtual_grf_count
= v
.virtual_grf_next
;
3428 for (int i
= 1; i
< virtual_grf_count
; i
++) {
3431 v
.calculate_live_intervals();
3435 v
.assign_regs_trivial();
3437 while (!v
.assign_regs()) {
3441 v
.calculate_live_intervals();
3449 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3454 c
->prog_data
.total_grf
= v
.grf_used
;