2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "compiler/glsl_types.h"
42 #include "compiler/nir/nir_builder.h"
43 #include "program/prog_parameter.h"
47 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
51 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
52 const fs_reg
*src
, unsigned sources
)
54 memset(this, 0, sizeof(*this));
56 this->src
= new fs_reg
[MAX2(sources
, 3)];
57 for (unsigned i
= 0; i
< sources
; i
++)
58 this->src
[i
] = src
[i
];
60 this->opcode
= opcode
;
62 this->sources
= sources
;
63 this->exec_size
= exec_size
;
66 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
68 assert(this->exec_size
!= 0);
70 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
72 /* This will be the case for almost all instructions. */
79 this->size_written
= dst
.component_size(exec_size
);
82 this->size_written
= 0;
86 unreachable("Invalid destination register file");
89 this->writes_accumulator
= false;
94 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
99 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
104 init(opcode
, exec_size
, dst
, NULL
, 0);
107 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg src
[1] = { src0
};
111 init(opcode
, exec_size
, dst
, src
, 1);
114 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
115 const fs_reg
&src0
, const fs_reg
&src1
)
117 const fs_reg src
[2] = { src0
, src1
};
118 init(opcode
, exec_size
, dst
, src
, 2);
121 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
122 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
124 const fs_reg src
[3] = { src0
, src1
, src2
};
125 init(opcode
, exec_size
, dst
, src
, 3);
128 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
129 const fs_reg src
[], unsigned sources
)
131 init(opcode
, exec_width
, dst
, src
, sources
);
134 fs_inst::fs_inst(const fs_inst
&that
)
136 memcpy(this, &that
, sizeof(that
));
138 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
140 for (unsigned i
= 0; i
< that
.sources
; i
++)
141 this->src
[i
] = that
.src
[i
];
150 fs_inst::resize_sources(uint8_t num_sources
)
152 if (this->sources
!= num_sources
) {
153 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
155 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
156 src
[i
] = this->src
[i
];
160 this->sources
= num_sources
;
165 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
167 const fs_reg
&surf_index
,
168 const fs_reg
&varying_offset
,
169 uint32_t const_offset
)
171 /* We have our constant surface use a pitch of 4 bytes, so our index can
172 * be any component of a vector, and then we load 4 contiguous
173 * components starting from that.
175 * We break down the const_offset to a portion added to the variable offset
176 * and a portion done using fs_reg::offset, which means that if you have
177 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
178 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
179 * later notice that those loads are all the same and eliminate the
182 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
183 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
185 /* The pull load message will load a vec4 (16 bytes). If we are loading
186 * a double this means we are only loading 2 elements worth of data.
187 * We also want to use a 32-bit data type for the dst of the load operation
188 * so other parts of the driver don't get confused about the size of the
191 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
192 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
193 vec4_result
, surf_index
, vec4_offset
);
194 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
196 if (type_sz(dst
.type
) == 8) {
197 shuffle_32bit_load_result_to_64bit_data(
198 bld
, retype(vec4_result
, dst
.type
), vec4_result
, 2);
201 vec4_result
.type
= dst
.type
;
202 bld
.MOV(dst
, offset(vec4_result
, bld
,
203 (const_offset
& 0xf) / type_sz(vec4_result
.type
)));
207 * A helper for MOV generation for fixing up broken hardware SEND dependency
211 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
213 /* The caller always wants uncompressed to emit the minimal extra
214 * dependencies, and to avoid having to deal with aligning its regs to 2.
216 const fs_builder ubld
= bld
.annotate("send dependency resolve")
219 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
223 fs_inst::equals(fs_inst
*inst
) const
225 return (opcode
== inst
->opcode
&&
226 dst
.equals(inst
->dst
) &&
227 src
[0].equals(inst
->src
[0]) &&
228 src
[1].equals(inst
->src
[1]) &&
229 src
[2].equals(inst
->src
[2]) &&
230 saturate
== inst
->saturate
&&
231 predicate
== inst
->predicate
&&
232 conditional_mod
== inst
->conditional_mod
&&
233 mlen
== inst
->mlen
&&
234 base_mrf
== inst
->base_mrf
&&
235 target
== inst
->target
&&
237 header_size
== inst
->header_size
&&
238 shadow_compare
== inst
->shadow_compare
&&
239 exec_size
== inst
->exec_size
&&
240 offset
== inst
->offset
);
244 fs_inst::is_send_from_grf() const
247 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
248 case SHADER_OPCODE_SHADER_TIME_ADD
:
249 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
250 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
251 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
252 case SHADER_OPCODE_UNTYPED_ATOMIC
:
253 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
254 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
255 case SHADER_OPCODE_TYPED_ATOMIC
:
256 case SHADER_OPCODE_TYPED_SURFACE_READ
:
257 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
258 case SHADER_OPCODE_URB_WRITE_SIMD8
:
259 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
260 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
261 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
262 case SHADER_OPCODE_URB_READ_SIMD8
:
263 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
265 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
266 return src
[1].file
== VGRF
;
267 case FS_OPCODE_FB_WRITE
:
268 case FS_OPCODE_FB_READ
:
269 return src
[0].file
== VGRF
;
272 return src
[0].file
== VGRF
;
279 * Returns true if this instruction's sources and destinations cannot
280 * safely be the same register.
282 * In most cases, a register can be written over safely by the same
283 * instruction that is its last use. For a single instruction, the
284 * sources are dereferenced before writing of the destination starts
287 * However, there are a few cases where this can be problematic:
289 * - Virtual opcodes that translate to multiple instructions in the
290 * code generator: if src == dst and one instruction writes the
291 * destination before a later instruction reads the source, then
292 * src will have been clobbered.
294 * - SIMD16 compressed instructions with certain regioning (see below).
296 * The register allocator uses this information to set up conflicts between
297 * GRF sources and the destination.
300 fs_inst::has_source_and_destination_hazard() const
303 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
304 /* Multiple partial writes to the destination */
307 /* The SIMD16 compressed instruction
309 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
311 * is actually decoded in hardware as:
313 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
314 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
316 * Which is safe. However, if we have uniform accesses
317 * happening, we get into trouble:
319 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
320 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
322 * Now our destination for the first instruction overwrote the
323 * second instruction's src0, and we get garbage for those 8
324 * pixels. There's a similar issue for the pre-gen6
325 * pixel_x/pixel_y, which are registers of 16-bit values and thus
326 * would get stomped by the first decode as well.
328 if (exec_size
== 16) {
329 for (int i
= 0; i
< sources
; i
++) {
330 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
331 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
332 src
[i
].type
== BRW_REGISTER_TYPE_W
||
333 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
334 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
344 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
346 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
349 fs_reg reg
= this->src
[0];
350 if (reg
.file
!= VGRF
|| reg
.offset
!= 0 || reg
.stride
!= 1)
353 if (grf_alloc
.sizes
[reg
.nr
] * REG_SIZE
!= this->size_written
)
356 for (int i
= 0; i
< this->sources
; i
++) {
357 reg
.type
= this->src
[i
].type
;
358 if (!this->src
[i
].equals(reg
))
361 if (i
< this->header_size
) {
362 reg
.offset
+= REG_SIZE
;
364 reg
= horiz_offset(reg
, this->exec_size
);
372 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
)
374 if (devinfo
->gen
== 6 && is_math())
377 if (is_send_from_grf())
380 if (!backend_instruction::can_do_source_mods())
387 fs_inst::can_change_types() const
389 return dst
.type
== src
[0].type
&&
390 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
391 (opcode
== BRW_OPCODE_MOV
||
392 (opcode
== BRW_OPCODE_SEL
&&
393 dst
.type
== src
[1].type
&&
394 predicate
!= BRW_PREDICATE_NONE
&&
395 !src
[1].abs
&& !src
[1].negate
));
399 fs_inst::has_side_effects() const
401 return this->eot
|| backend_instruction::has_side_effects();
407 memset(this, 0, sizeof(*this));
411 /** Generic unset register constructor. */
415 this->file
= BAD_FILE
;
418 fs_reg::fs_reg(struct ::brw_reg reg
) :
423 if (this->file
== IMM
&&
424 (this->type
!= BRW_REGISTER_TYPE_V
&&
425 this->type
!= BRW_REGISTER_TYPE_UV
&&
426 this->type
!= BRW_REGISTER_TYPE_VF
)) {
432 fs_reg::equals(const fs_reg
&r
) const
434 return (this->backend_reg::equals(r
) &&
439 fs_reg::is_contiguous() const
445 fs_reg::component_size(unsigned width
) const
447 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
450 return MAX2(width
* stride
, 1) * type_sz(type
);
454 type_size_scalar(const struct glsl_type
*type
)
456 unsigned int size
, i
;
458 switch (type
->base_type
) {
461 case GLSL_TYPE_FLOAT
:
463 return type
->components();
464 case GLSL_TYPE_DOUBLE
:
465 return type
->components() * 2;
466 case GLSL_TYPE_ARRAY
:
467 return type_size_scalar(type
->fields
.array
) * type
->length
;
468 case GLSL_TYPE_STRUCT
:
470 for (i
= 0; i
< type
->length
; i
++) {
471 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
474 case GLSL_TYPE_SAMPLER
:
475 /* Samplers take up no register space, since they're baked in at
479 case GLSL_TYPE_ATOMIC_UINT
:
481 case GLSL_TYPE_SUBROUTINE
:
483 case GLSL_TYPE_IMAGE
:
484 return BRW_IMAGE_PARAM_SIZE
;
486 case GLSL_TYPE_ERROR
:
487 case GLSL_TYPE_INTERFACE
:
488 case GLSL_TYPE_FUNCTION
:
489 unreachable("not reached");
496 * Returns the number of scalar components needed to store type, assuming
497 * that vectors are padded out to vec4.
499 * This has the packing rules of type_size_vec4(), but counts components
500 * similar to type_size_scalar().
503 type_size_vec4_times_4(const struct glsl_type
*type
)
505 return 4 * type_size_vec4(type
);
508 /* Attribute arrays are loaded as one vec4 per element (or matrix column),
509 * except for double-precision types, which are loaded as one dvec4.
512 type_size_vs_input(const struct glsl_type
*type
)
514 if (type
->is_double()) {
515 return type_size_dvec4(type
);
517 return type_size_vec4(type
);
522 * Create a MOV to read the timestamp register.
524 * The caller is responsible for emitting the MOV. The return value is
525 * the destination of the MOV, with extra parameters set.
528 fs_visitor::get_timestamp(const fs_builder
&bld
)
530 assert(devinfo
->gen
>= 7);
532 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
535 BRW_REGISTER_TYPE_UD
));
537 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
539 /* We want to read the 3 fields we care about even if it's not enabled in
542 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
548 fs_visitor::emit_shader_time_begin()
550 /* We want only the low 32 bits of the timestamp. Since it's running
551 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
552 * which is plenty of time for our purposes. It is identical across the
553 * EUs, but since it's tracking GPU core speed it will increment at a
554 * varying rate as render P-states change.
556 shader_start_time
= component(
557 get_timestamp(bld
.annotate("shader time start")), 0);
561 fs_visitor::emit_shader_time_end()
563 /* Insert our code just before the final SEND with EOT. */
564 exec_node
*end
= this->instructions
.get_tail();
565 assert(end
&& ((fs_inst
*) end
)->eot
);
566 const fs_builder ibld
= bld
.annotate("shader time end")
567 .exec_all().at(NULL
, end
);
568 const fs_reg timestamp
= get_timestamp(ibld
);
570 /* We only use the low 32 bits of the timestamp - see
571 * emit_shader_time_begin()).
573 * We could also check if render P-states have changed (or anything
574 * else that might disrupt timing) by setting smear to 2 and checking if
575 * that field is != 0.
577 const fs_reg shader_end_time
= component(timestamp
, 0);
579 /* Check that there weren't any timestamp reset events (assuming these
580 * were the only two timestamp reads that happened).
582 const fs_reg reset
= component(timestamp
, 2);
583 set_condmod(BRW_CONDITIONAL_Z
,
584 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
585 ibld
.IF(BRW_PREDICATE_NORMAL
);
587 fs_reg start
= shader_start_time
;
589 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
590 BRW_REGISTER_TYPE_UD
),
592 const fs_builder cbld
= ibld
.group(1, 0);
593 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
595 /* If there were no instructions between the two timestamp gets, the diff
596 * is 2 cycles. Remove that overhead, so I can forget about that when
597 * trying to determine the time taken for single instructions.
599 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
600 SHADER_TIME_ADD(cbld
, 0, diff
);
601 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
602 ibld
.emit(BRW_OPCODE_ELSE
);
603 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
604 ibld
.emit(BRW_OPCODE_ENDIF
);
608 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
609 int shader_time_subindex
,
612 int index
= shader_time_index
* 3 + shader_time_subindex
;
613 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
616 if (dispatch_width
== 8)
617 payload
= vgrf(glsl_type::uvec2_type
);
619 payload
= vgrf(glsl_type::uint_type
);
621 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
625 fs_visitor::vfail(const char *format
, va_list va
)
634 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
635 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
637 this->fail_msg
= msg
;
640 fprintf(stderr
, "%s", msg
);
645 fs_visitor::fail(const char *format
, ...)
649 va_start(va
, format
);
655 * Mark this program as impossible to compile with dispatch width greater
658 * During the SIMD8 compile (which happens first), we can detect and flag
659 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
660 * SIMD16+ compile altogether.
662 * During a compile of dispatch width greater than n (if one happens anyway),
663 * this just calls fail().
666 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
668 if (dispatch_width
> n
) {
671 max_dispatch_width
= n
;
672 compiler
->shader_perf_log(log_data
,
673 "Shader dispatch width limited to SIMD%d: %s",
679 * Returns true if the instruction has a flag that means it won't
680 * update an entire destination register.
682 * For example, dead code elimination and live variable analysis want to know
683 * when a write to a variable screens off any preceding values that were in
687 fs_inst::is_partial_write() const
689 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
690 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
691 !this->dst
.is_contiguous() ||
692 this->dst
.offset
% REG_SIZE
!= 0);
696 fs_inst::components_read(unsigned i
) const
698 /* Return zero if the source is not present. */
699 if (src
[i
].file
== BAD_FILE
)
703 case FS_OPCODE_LINTERP
:
709 case FS_OPCODE_PIXEL_X
:
710 case FS_OPCODE_PIXEL_Y
:
714 case FS_OPCODE_FB_WRITE_LOGICAL
:
715 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
716 /* First/second FB write color. */
718 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
722 case SHADER_OPCODE_TEX_LOGICAL
:
723 case SHADER_OPCODE_TXD_LOGICAL
:
724 case SHADER_OPCODE_TXF_LOGICAL
:
725 case SHADER_OPCODE_TXL_LOGICAL
:
726 case SHADER_OPCODE_TXS_LOGICAL
:
727 case FS_OPCODE_TXB_LOGICAL
:
728 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
729 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
730 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
731 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
732 case SHADER_OPCODE_LOD_LOGICAL
:
733 case SHADER_OPCODE_TG4_LOGICAL
:
734 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
735 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
736 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
737 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
738 /* Texture coordinates. */
739 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
740 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
741 /* Texture derivatives. */
742 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
743 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
744 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
745 /* Texture offset. */
746 else if (i
== TEX_LOGICAL_SRC_OFFSET_VALUE
)
749 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
754 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
755 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
756 assert(src
[3].file
== IMM
);
757 /* Surface coordinates. */
760 /* Surface operation source (ignored for reads). */
766 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
767 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
768 assert(src
[3].file
== IMM
&&
770 /* Surface coordinates. */
773 /* Surface operation source. */
779 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
780 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
781 assert(src
[3].file
== IMM
&&
783 const unsigned op
= src
[4].ud
;
784 /* Surface coordinates. */
787 /* Surface operation source. */
788 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
790 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
791 op
== BRW_AOP_PREDEC
))
803 fs_inst::size_read(int arg
) const
806 case FS_OPCODE_FB_WRITE
:
807 case FS_OPCODE_FB_READ
:
808 case SHADER_OPCODE_URB_WRITE_SIMD8
:
809 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
810 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
811 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
812 case SHADER_OPCODE_URB_READ_SIMD8
:
813 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
814 case SHADER_OPCODE_UNTYPED_ATOMIC
:
815 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
816 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
817 case SHADER_OPCODE_TYPED_ATOMIC
:
818 case SHADER_OPCODE_TYPED_SURFACE_READ
:
819 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
820 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
822 return mlen
* REG_SIZE
;
825 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
826 /* The payload is actually stored in src1 */
828 return mlen
* REG_SIZE
;
831 case FS_OPCODE_LINTERP
:
836 case SHADER_OPCODE_LOAD_PAYLOAD
:
837 if (arg
< this->header_size
)
841 case CS_OPCODE_CS_TERMINATE
:
842 case SHADER_OPCODE_BARRIER
:
845 case SHADER_OPCODE_MOV_INDIRECT
:
847 assert(src
[2].file
== IMM
);
853 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
854 return mlen
* REG_SIZE
;
858 switch (src
[arg
].file
) {
861 return components_read(arg
) * type_sz(src
[arg
].type
);
867 return components_read(arg
) * src
[arg
].component_size(exec_size
);
869 unreachable("MRF registers are not allowed as sources");
875 /* Return the subset of flag registers that an instruction could
876 * potentially read or write based on the execution controls and flag
877 * subregister number of the instruction.
880 flag_mask(const fs_inst
*inst
)
882 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
883 const unsigned end
= start
+ inst
->exec_size
;
884 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
889 fs_inst::flags_read(const gen_device_info
*devinfo
) const
891 /* XXX - This doesn't consider explicit uses of the flag register as source
894 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
895 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
896 /* The vertical predication modes combine corresponding bits from
897 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
899 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
900 return flag_mask(this) << shift
| flag_mask(this);
901 } else if (predicate
) {
902 return flag_mask(this);
909 fs_inst::flags_written() const
911 /* XXX - This doesn't consider explicit uses of the flag register as
912 * destination region.
914 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
915 opcode
!= BRW_OPCODE_IF
&&
916 opcode
!= BRW_OPCODE_WHILE
)) ||
917 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
918 return flag_mask(this);
925 * Returns how many MRFs an FS opcode will write over.
927 * Note that this is not the 0 or 1 implied writes in an actual gen
928 * instruction -- the FS opcodes often generate MOVs in addition.
931 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
936 if (inst
->base_mrf
== -1)
939 switch (inst
->opcode
) {
940 case SHADER_OPCODE_RCP
:
941 case SHADER_OPCODE_RSQ
:
942 case SHADER_OPCODE_SQRT
:
943 case SHADER_OPCODE_EXP2
:
944 case SHADER_OPCODE_LOG2
:
945 case SHADER_OPCODE_SIN
:
946 case SHADER_OPCODE_COS
:
947 return 1 * dispatch_width
/ 8;
948 case SHADER_OPCODE_POW
:
949 case SHADER_OPCODE_INT_QUOTIENT
:
950 case SHADER_OPCODE_INT_REMAINDER
:
951 return 2 * dispatch_width
/ 8;
952 case SHADER_OPCODE_TEX
:
954 case SHADER_OPCODE_TXD
:
955 case SHADER_OPCODE_TXF
:
956 case SHADER_OPCODE_TXF_CMS
:
957 case SHADER_OPCODE_TXF_MCS
:
958 case SHADER_OPCODE_TG4
:
959 case SHADER_OPCODE_TG4_OFFSET
:
960 case SHADER_OPCODE_TXL
:
961 case SHADER_OPCODE_TXS
:
962 case SHADER_OPCODE_LOD
:
963 case SHADER_OPCODE_SAMPLEINFO
:
965 case FS_OPCODE_FB_WRITE
:
967 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
968 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
970 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
972 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
975 unreachable("not reached");
980 fs_visitor::vgrf(const glsl_type
*const type
)
982 int reg_width
= dispatch_width
/ 8;
983 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
984 brw_type_for_base_type(type
));
987 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
992 this->type
= BRW_REGISTER_TYPE_F
;
993 this->stride
= (file
== UNIFORM
? 0 : 1);
996 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1002 this->stride
= (file
== UNIFORM
? 0 : 1);
1005 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1006 * This brings in those uniform definitions
1009 fs_visitor::import_uniforms(fs_visitor
*v
)
1011 this->push_constant_loc
= v
->push_constant_loc
;
1012 this->pull_constant_loc
= v
->pull_constant_loc
;
1013 this->uniforms
= v
->uniforms
;
1017 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1019 assert(stage
== MESA_SHADER_FRAGMENT
);
1021 /* gl_FragCoord.x */
1022 bld
.MOV(wpos
, this->pixel_x
);
1023 wpos
= offset(wpos
, bld
, 1);
1025 /* gl_FragCoord.y */
1026 bld
.MOV(wpos
, this->pixel_y
);
1027 wpos
= offset(wpos
, bld
, 1);
1029 /* gl_FragCoord.z */
1030 if (devinfo
->gen
>= 6) {
1031 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1033 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1034 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1035 interp_reg(VARYING_SLOT_POS
, 2));
1037 wpos
= offset(wpos
, bld
, 1);
1039 /* gl_FragCoord.w: Already set up in emit_interpolation */
1040 bld
.MOV(wpos
, this->wpos_w
);
1043 enum brw_barycentric_mode
1044 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1046 /* Barycentric modes don't make sense for flat inputs. */
1047 assert(mode
!= INTERP_MODE_FLAT
);
1051 case nir_intrinsic_load_barycentric_pixel
:
1052 case nir_intrinsic_load_barycentric_at_offset
:
1053 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1055 case nir_intrinsic_load_barycentric_centroid
:
1056 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1058 case nir_intrinsic_load_barycentric_sample
:
1059 case nir_intrinsic_load_barycentric_at_sample
:
1060 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1063 unreachable("invalid intrinsic");
1066 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1069 return (enum brw_barycentric_mode
) bary
;
1073 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1075 static enum brw_barycentric_mode
1076 centroid_to_pixel(enum brw_barycentric_mode bary
)
1078 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1079 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1080 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1084 fs_visitor::emit_frontfacing_interpolation()
1086 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1088 if (devinfo
->gen
>= 6) {
1089 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1090 * a boolean result from this (~0/true or 0/false).
1092 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1093 * this task in only one instruction:
1094 * - a negation source modifier will flip the bit; and
1095 * - a W -> D type conversion will sign extend the bit into the high
1096 * word of the destination.
1098 * An ASR 15 fills the low word of the destination.
1100 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1103 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1105 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1106 * a boolean result from this (1/true or 0/false).
1108 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1109 * the negation source modifier to flip it. Unfortunately the SHR
1110 * instruction only operates on UD (or D with an abs source modifier)
1111 * sources without negation.
1113 * Instead, use ASR (which will give ~0/true or 0/false).
1115 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1118 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1125 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1127 assert(stage
== MESA_SHADER_FRAGMENT
);
1128 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1129 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1131 if (wm_prog_data
->persample_dispatch
) {
1132 /* Convert int_sample_pos to floating point */
1133 bld
.MOV(dst
, int_sample_pos
);
1134 /* Scale to the range [0, 1] */
1135 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1138 /* From ARB_sample_shading specification:
1139 * "When rendering to a non-multisample buffer, or if multisample
1140 * rasterization is disabled, gl_SamplePosition will always be
1143 bld
.MOV(dst
, brw_imm_f(0.5f
));
1148 fs_visitor::emit_samplepos_setup()
1150 assert(devinfo
->gen
>= 6);
1152 const fs_builder abld
= bld
.annotate("compute sample position");
1153 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1155 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1156 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1158 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1159 * mode will be enabled.
1161 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1162 * R31.1:0 Position Offset X/Y for Slot[3:0]
1163 * R31.3:2 Position Offset X/Y for Slot[7:4]
1166 * The X, Y sample positions come in as bytes in thread payload. So, read
1167 * the positions using vstride=16, width=8, hstride=2.
1169 struct brw_reg sample_pos_reg
=
1170 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1171 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1173 if (dispatch_width
== 8) {
1174 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1176 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1177 abld
.half(1).MOV(half(int_sample_x
, 1),
1178 fs_reg(suboffset(sample_pos_reg
, 16)));
1180 /* Compute gl_SamplePosition.x */
1181 compute_sample_position(pos
, int_sample_x
);
1182 pos
= offset(pos
, abld
, 1);
1183 if (dispatch_width
== 8) {
1184 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1186 abld
.half(0).MOV(half(int_sample_y
, 0),
1187 fs_reg(suboffset(sample_pos_reg
, 1)));
1188 abld
.half(1).MOV(half(int_sample_y
, 1),
1189 fs_reg(suboffset(sample_pos_reg
, 17)));
1191 /* Compute gl_SamplePosition.y */
1192 compute_sample_position(pos
, int_sample_y
);
1197 fs_visitor::emit_sampleid_setup()
1199 assert(stage
== MESA_SHADER_FRAGMENT
);
1200 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1201 assert(devinfo
->gen
>= 6);
1203 const fs_builder abld
= bld
.annotate("compute sample id");
1204 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1206 if (!key
->multisample_fbo
) {
1207 /* As per GL_ARB_sample_shading specification:
1208 * "When rendering to a non-multisample buffer, or if multisample
1209 * rasterization is disabled, gl_SampleID will always be zero."
1211 abld
.MOV(*reg
, brw_imm_d(0));
1212 } else if (devinfo
->gen
>= 8) {
1213 /* Sample ID comes in as 4-bit numbers in g1.0:
1215 * 15:12 Slot 3 SampleID (only used in SIMD16)
1216 * 11:8 Slot 2 SampleID (only used in SIMD16)
1217 * 7:4 Slot 1 SampleID
1218 * 3:0 Slot 0 SampleID
1220 * Each slot corresponds to four channels, so we want to replicate each
1221 * half-byte value to 4 channels in a row:
1223 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1224 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1226 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1227 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1229 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1230 * channels to read the first byte (7:0), and the second group of 8
1231 * channels to read the second byte (15:8). Then, we shift right by
1232 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1233 * values into place. Finally, we AND with 0xf to keep the low nibble.
1235 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1236 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1238 * TODO: These payload bits exist on Gen7 too, but they appear to always
1239 * be zero, so this code fails to work. We should find out why.
1241 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1243 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1244 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1245 brw_imm_v(0x44440000));
1246 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1248 const fs_reg t1
= component(fs_reg(VGRF
, alloc
.allocate(1),
1249 BRW_REGISTER_TYPE_D
), 0);
1250 const fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1252 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1253 * 8x multisampling, subspan 0 will represent sample N (where N
1254 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1255 * 7. We can find the value of N by looking at R0.0 bits 7:6
1256 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1257 * (since samples are always delivered in pairs). That is, we
1258 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1259 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1260 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1261 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1262 * populating a temporary variable with the sequence (0, 1, 2, 3),
1263 * and then reading from it using vstride=1, width=4, hstride=0.
1264 * These computations hold good for 4x multisampling as well.
1266 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1267 * the first four slots are sample 0 of subspan 0; the next four
1268 * are sample 1 of subspan 0; the third group is sample 0 of
1269 * subspan 1, and finally sample 1 of subspan 1.
1272 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1273 * accomodate 16x MSAA.
1275 abld
.exec_all().group(1, 0)
1276 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1278 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1280 /* This works for both SIMD8 and SIMD16 */
1281 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1283 /* This special instruction takes care of setting vstride=1,
1284 * width=4, hstride=0 of t2 during an ADD instruction.
1286 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1293 fs_visitor::emit_samplemaskin_setup()
1295 assert(stage
== MESA_SHADER_FRAGMENT
);
1296 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1297 assert(devinfo
->gen
>= 6);
1299 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1301 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1302 BRW_REGISTER_TYPE_D
));
1304 if (wm_prog_data
->persample_dispatch
) {
1305 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1306 * and a mask representing which sample is being processed by the
1307 * current shader invocation.
1309 * From the OES_sample_variables specification:
1310 * "When per-sample shading is active due to the use of a fragment input
1311 * qualified by "sample" or due to the use of the gl_SampleID or
1312 * gl_SamplePosition variables, only the bit for the current sample is
1313 * set in gl_SampleMaskIn."
1315 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1317 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1318 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1320 fs_reg one
= vgrf(glsl_type::int_type
);
1321 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1322 abld
.MOV(one
, brw_imm_d(1));
1323 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1324 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1326 /* In per-pixel mode, the coverage mask is sufficient. */
1327 *reg
= coverage_mask
;
1333 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1335 if (!src
.abs
&& !src
.negate
)
1338 fs_reg temp
= bld
.vgrf(src
.type
);
1345 fs_visitor::emit_discard_jump()
1347 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1349 /* For performance, after a discard, jump to the end of the
1350 * shader if all relevant channels have been discarded.
1352 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1353 discard_jump
->flag_subreg
= 1;
1355 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1356 discard_jump
->predicate_inverse
= true;
1360 fs_visitor::emit_gs_thread_end()
1362 assert(stage
== MESA_SHADER_GEOMETRY
);
1364 struct brw_gs_prog_data
*gs_prog_data
=
1365 (struct brw_gs_prog_data
*) prog_data
;
1367 if (gs_compile
->control_data_header_size_bits
> 0) {
1368 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1371 const fs_builder abld
= bld
.annotate("thread end");
1374 if (gs_prog_data
->static_vertex_count
!= -1) {
1375 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1376 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1377 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1378 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1379 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1382 /* Delete now dead instructions. */
1383 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1389 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1393 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1394 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1395 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1398 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1399 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1400 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1401 sources
[1] = this->final_gs_vertex_count
;
1402 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1403 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1411 fs_visitor::assign_curb_setup()
1413 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1415 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1416 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1417 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1418 if (inst
->src
[i
].file
== UNIFORM
) {
1419 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1421 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1422 constant_nr
= push_constant_loc
[uniform_nr
];
1424 /* Section 5.11 of the OpenGL 4.1 spec says:
1425 * "Out-of-bounds reads return undefined values, which include
1426 * values from other variables of the active program or zero."
1427 * Just return the first push constant.
1432 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1435 brw_reg
.abs
= inst
->src
[i
].abs
;
1436 brw_reg
.negate
= inst
->src
[i
].negate
;
1438 assert(inst
->src
[i
].stride
== 0);
1439 inst
->src
[i
] = byte_offset(
1440 retype(brw_reg
, inst
->src
[i
].type
),
1441 inst
->src
[i
].offset
% 4);
1446 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1447 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1451 fs_visitor::calculate_urb_setup()
1453 assert(stage
== MESA_SHADER_FRAGMENT
);
1454 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1455 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1457 memset(prog_data
->urb_setup
, -1,
1458 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1461 /* Figure out where each of the incoming setup attributes lands. */
1462 if (devinfo
->gen
>= 6) {
1463 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1464 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1465 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1466 * first 16 varying inputs, so we can put them wherever we want.
1467 * Just put them in order.
1469 * This is useful because it means that (a) inputs not used by the
1470 * fragment shader won't take up valuable register space, and (b) we
1471 * won't have to recompile the fragment shader if it gets paired with
1472 * a different vertex (or geometry) shader.
1474 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1475 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1476 BITFIELD64_BIT(i
)) {
1477 prog_data
->urb_setup
[i
] = urb_next
++;
1481 bool include_vue_header
=
1482 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1484 /* We have enough input varyings that the SF/SBE pipeline stage can't
1485 * arbitrarily rearrange them to suit our whim; we have to put them
1486 * in an order that matches the output of the previous pipeline stage
1487 * (geometry or vertex shader).
1489 struct brw_vue_map prev_stage_vue_map
;
1490 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1491 key
->input_slots_valid
,
1492 nir
->info
.separate_shader
);
1494 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1496 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1497 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1499 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1500 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1501 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1502 BITFIELD64_BIT(varying
))) {
1503 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1506 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1509 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1510 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1511 /* Point size is packed into the header, not as a general attribute */
1512 if (i
== VARYING_SLOT_PSIZ
)
1515 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1516 /* The back color slot is skipped when the front color is
1517 * also written to. In addition, some slots can be
1518 * written in the vertex shader and not read in the
1519 * fragment shader. So the register number must always be
1520 * incremented, mapped or not.
1522 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1523 prog_data
->urb_setup
[i
] = urb_next
;
1529 * It's a FS only attribute, and we did interpolation for this attribute
1530 * in SF thread. So, count it here, too.
1532 * See compile_sf_prog() for more info.
1534 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1535 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1538 prog_data
->num_varying_inputs
= urb_next
;
1542 fs_visitor::assign_urb_setup()
1544 assert(stage
== MESA_SHADER_FRAGMENT
);
1545 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1547 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1549 /* Offset all the urb_setup[] index by the actual position of the
1550 * setup regs, now that the location of the constants has been chosen.
1552 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1553 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1554 assert(inst
->src
[1].file
== FIXED_GRF
);
1555 inst
->src
[1].nr
+= urb_start
;
1558 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1559 assert(inst
->src
[0].file
== FIXED_GRF
);
1560 inst
->src
[0].nr
+= urb_start
;
1564 /* Each attribute is 4 setup channels, each of which is half a reg. */
1565 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1569 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1571 for (int i
= 0; i
< inst
->sources
; i
++) {
1572 if (inst
->src
[i
].file
== ATTR
) {
1573 int grf
= payload
.num_regs
+
1574 prog_data
->curb_read_length
+
1576 inst
->src
[i
].offset
/ REG_SIZE
;
1578 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1580 * VertStride must be used to cross GRF register boundaries. This
1581 * rule implies that elements within a 'Width' cannot cross GRF
1584 * So, for registers that are large enough, we have to split the exec
1585 * size in two and trust the compression state to sort it out.
1587 unsigned total_size
= inst
->exec_size
*
1588 inst
->src
[i
].stride
*
1589 type_sz(inst
->src
[i
].type
);
1591 assert(total_size
<= 2 * REG_SIZE
);
1592 const unsigned exec_size
=
1593 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1595 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1596 struct brw_reg reg
=
1597 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1598 inst
->src
[i
].offset
% REG_SIZE
),
1599 exec_size
* inst
->src
[i
].stride
,
1600 width
, inst
->src
[i
].stride
);
1601 reg
.abs
= inst
->src
[i
].abs
;
1602 reg
.negate
= inst
->src
[i
].negate
;
1610 fs_visitor::assign_vs_urb_setup()
1612 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1614 assert(stage
== MESA_SHADER_VERTEX
);
1616 /* Each attribute is 4 regs. */
1617 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1619 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1621 /* Rewrite all ATTR file references to the hw grf that they land in. */
1622 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1623 convert_attr_sources_to_hw_regs(inst
);
1628 fs_visitor::assign_tcs_single_patch_urb_setup()
1630 assert(stage
== MESA_SHADER_TESS_CTRL
);
1632 /* Rewrite all ATTR file references to HW_REGs. */
1633 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1634 convert_attr_sources_to_hw_regs(inst
);
1639 fs_visitor::assign_tes_urb_setup()
1641 assert(stage
== MESA_SHADER_TESS_EVAL
);
1643 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1645 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1647 /* Rewrite all ATTR file references to HW_REGs. */
1648 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1649 convert_attr_sources_to_hw_regs(inst
);
1654 fs_visitor::assign_gs_urb_setup()
1656 assert(stage
== MESA_SHADER_GEOMETRY
);
1658 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1660 first_non_payload_grf
+=
1661 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1663 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1664 /* Rewrite all ATTR file references to GRFs. */
1665 convert_attr_sources_to_hw_regs(inst
);
1671 * Split large virtual GRFs into separate components if we can.
1673 * This is mostly duplicated with what brw_fs_vector_splitting does,
1674 * but that's really conservative because it's afraid of doing
1675 * splitting that doesn't result in real progress after the rest of
1676 * the optimization phases, which would cause infinite looping in
1677 * optimization. We can do it once here, safely. This also has the
1678 * opportunity to split interpolated values, or maybe even uniforms,
1679 * which we don't have at the IR level.
1681 * We want to split, because virtual GRFs are what we register
1682 * allocate and spill (due to contiguousness requirements for some
1683 * instructions), and they're what we naturally generate in the
1684 * codegen process, but most virtual GRFs don't actually need to be
1685 * contiguous sets of GRFs. If we split, we'll end up with reduced
1686 * live intervals and better dead code elimination and coalescing.
1689 fs_visitor::split_virtual_grfs()
1691 int num_vars
= this->alloc
.count
;
1693 /* Count the total number of registers */
1695 int vgrf_to_reg
[num_vars
];
1696 for (int i
= 0; i
< num_vars
; i
++) {
1697 vgrf_to_reg
[i
] = reg_count
;
1698 reg_count
+= alloc
.sizes
[i
];
1701 /* An array of "split points". For each register slot, this indicates
1702 * if this slot can be separated from the previous slot. Every time an
1703 * instruction uses multiple elements of a register (as a source or
1704 * destination), we mark the used slots as inseparable. Then we go
1705 * through and split the registers into the smallest pieces we can.
1707 bool split_points
[reg_count
];
1708 memset(split_points
, 0, sizeof(split_points
));
1710 /* Mark all used registers as fully splittable */
1711 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1712 if (inst
->dst
.file
== VGRF
) {
1713 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1714 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1715 split_points
[reg
+ j
] = true;
1718 for (int i
= 0; i
< inst
->sources
; i
++) {
1719 if (inst
->src
[i
].file
== VGRF
) {
1720 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1721 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1722 split_points
[reg
+ j
] = true;
1727 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1728 if (inst
->dst
.file
== VGRF
) {
1729 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1730 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1731 split_points
[reg
+ j
] = false;
1733 for (int i
= 0; i
< inst
->sources
; i
++) {
1734 if (inst
->src
[i
].file
== VGRF
) {
1735 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1736 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1737 split_points
[reg
+ j
] = false;
1742 int new_virtual_grf
[reg_count
];
1743 int new_reg_offset
[reg_count
];
1746 for (int i
= 0; i
< num_vars
; i
++) {
1747 /* The first one should always be 0 as a quick sanity check. */
1748 assert(split_points
[reg
] == false);
1751 new_reg_offset
[reg
] = 0;
1756 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1757 /* If this is a split point, reset the offset to 0 and allocate a
1758 * new virtual GRF for the previous offset many registers
1760 if (split_points
[reg
]) {
1761 assert(offset
<= MAX_VGRF_SIZE
);
1762 int grf
= alloc
.allocate(offset
);
1763 for (int k
= reg
- offset
; k
< reg
; k
++)
1764 new_virtual_grf
[k
] = grf
;
1767 new_reg_offset
[reg
] = offset
;
1772 /* The last one gets the original register number */
1773 assert(offset
<= MAX_VGRF_SIZE
);
1774 alloc
.sizes
[i
] = offset
;
1775 for (int k
= reg
- offset
; k
< reg
; k
++)
1776 new_virtual_grf
[k
] = i
;
1778 assert(reg
== reg_count
);
1780 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1781 if (inst
->dst
.file
== VGRF
) {
1782 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1783 inst
->dst
.nr
= new_virtual_grf
[reg
];
1784 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
1785 inst
->dst
.offset
% REG_SIZE
;
1786 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1788 for (int i
= 0; i
< inst
->sources
; i
++) {
1789 if (inst
->src
[i
].file
== VGRF
) {
1790 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1791 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1792 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
1793 inst
->src
[i
].offset
% REG_SIZE
;
1794 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1798 invalidate_live_intervals();
1802 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1804 * During code generation, we create tons of temporary variables, many of
1805 * which get immediately killed and are never used again. Yet, in later
1806 * optimization and analysis passes, such as compute_live_intervals, we need
1807 * to loop over all the virtual GRFs. Compacting them can save a lot of
1811 fs_visitor::compact_virtual_grfs()
1813 bool progress
= false;
1814 int remap_table
[this->alloc
.count
];
1815 memset(remap_table
, -1, sizeof(remap_table
));
1817 /* Mark which virtual GRFs are used. */
1818 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1819 if (inst
->dst
.file
== VGRF
)
1820 remap_table
[inst
->dst
.nr
] = 0;
1822 for (int i
= 0; i
< inst
->sources
; i
++) {
1823 if (inst
->src
[i
].file
== VGRF
)
1824 remap_table
[inst
->src
[i
].nr
] = 0;
1828 /* Compact the GRF arrays. */
1830 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1831 if (remap_table
[i
] == -1) {
1832 /* We just found an unused register. This means that we are
1833 * actually going to compact something.
1837 remap_table
[i
] = new_index
;
1838 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1839 invalidate_live_intervals();
1844 this->alloc
.count
= new_index
;
1846 /* Patch all the instructions to use the newly renumbered registers */
1847 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1848 if (inst
->dst
.file
== VGRF
)
1849 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1851 for (int i
= 0; i
< inst
->sources
; i
++) {
1852 if (inst
->src
[i
].file
== VGRF
)
1853 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1857 /* Patch all the references to delta_xy, since they're used in register
1858 * allocation. If they're unused, switch them to BAD_FILE so we don't
1859 * think some random VGRF is delta_xy.
1861 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1862 if (delta_xy
[i
].file
== VGRF
) {
1863 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1864 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1866 delta_xy
[i
].file
= BAD_FILE
;
1875 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
, bool contiguous
,
1876 int *push_constant_loc
, int *pull_constant_loc
,
1877 unsigned *num_push_constants
,
1878 unsigned *num_pull_constants
,
1879 const unsigned max_push_components
,
1880 const unsigned max_chunk_size
,
1881 struct brw_stage_prog_data
*stage_prog_data
)
1883 /* This is the first live uniform in the chunk */
1884 if (*chunk_start
< 0)
1885 *chunk_start
= uniform
;
1887 /* If this element does not need to be contiguous with the next, we
1888 * split at this point and everything between chunk_start and u forms a
1892 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
1894 /* Decide whether we should push or pull this parameter. In the
1895 * Vulkan driver, push constants are explicitly exposed via the API
1896 * so we push everything. In GL, we only push small arrays.
1898 if (stage_prog_data
->pull_param
== NULL
||
1899 (*num_push_constants
+ chunk_size
<= max_push_components
&&
1900 chunk_size
<= max_chunk_size
)) {
1901 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
1902 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1903 push_constant_loc
[j
] = (*num_push_constants
)++;
1905 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1906 pull_constant_loc
[j
] = (*num_pull_constants
)++;
1914 * Assign UNIFORM file registers to either push constants or pull constants.
1916 * We allow a fragment shader to have more than the specified minimum
1917 * maximum number of fragment shader uniform components (64). If
1918 * there are too many of these, they'd fill up all of register space.
1919 * So, this will push some of them out to the pull constant buffer and
1920 * update the program to load them.
1923 fs_visitor::assign_constant_locations()
1925 /* Only the first compile gets to decide on locations. */
1926 if (dispatch_width
!= min_dispatch_width
)
1929 bool is_live
[uniforms
];
1930 memset(is_live
, 0, sizeof(is_live
));
1931 bool is_live_64bit
[uniforms
];
1932 memset(is_live_64bit
, 0, sizeof(is_live_64bit
));
1934 /* For each uniform slot, a value of true indicates that the given slot and
1935 * the next slot must remain contiguous. This is used to keep us from
1936 * splitting arrays apart.
1938 bool contiguous
[uniforms
];
1939 memset(contiguous
, 0, sizeof(contiguous
));
1941 int thread_local_id_index
=
1942 (stage
== MESA_SHADER_COMPUTE
) ?
1943 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
: -1;
1945 /* First, we walk through the instructions and do two things:
1947 * 1) Figure out which uniforms are live.
1949 * 2) Mark any indirectly used ranges of registers as contiguous.
1951 * Note that we don't move constant-indexed accesses to arrays. No
1952 * testing has been done of the performance impact of this choice.
1954 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1955 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1956 if (inst
->src
[i
].file
!= UNIFORM
)
1959 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1961 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
1962 assert(inst
->src
[2].ud
% 4 == 0);
1963 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
1964 assert(last
< uniforms
);
1966 for (unsigned j
= constant_nr
; j
< last
; j
++) {
1968 contiguous
[j
] = true;
1969 if (type_sz(inst
->src
[i
].type
) == 8) {
1970 is_live_64bit
[j
] = true;
1973 is_live
[last
] = true;
1975 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
1976 int regs_read
= inst
->components_read(i
) *
1977 type_sz(inst
->src
[i
].type
) / 4;
1978 for (int j
= 0; j
< regs_read
; j
++) {
1979 is_live
[constant_nr
+ j
] = true;
1980 if (type_sz(inst
->src
[i
].type
) == 8) {
1981 is_live_64bit
[constant_nr
+ j
] = true;
1989 if (thread_local_id_index
>= 0 && !is_live
[thread_local_id_index
])
1990 thread_local_id_index
= -1;
1992 /* Only allow 16 registers (128 uniform components) as push constants.
1994 * Just demote the end of the list. We could probably do better
1995 * here, demoting things that are rarely used in the program first.
1997 * If changing this value, note the limitation about total_regs in
2000 unsigned int max_push_components
= 16 * 8;
2001 if (thread_local_id_index
>= 0)
2002 max_push_components
--; /* Save a slot for the thread ID */
2004 /* We push small arrays, but no bigger than 16 floats. This is big enough
2005 * for a vec4 but hopefully not large enough to push out other stuff. We
2006 * should probably use a better heuristic at some point.
2008 const unsigned int max_chunk_size
= 16;
2010 unsigned int num_push_constants
= 0;
2011 unsigned int num_pull_constants
= 0;
2013 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2014 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2016 /* Default to -1 meaning no location */
2017 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2018 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2020 int chunk_start
= -1;
2022 /* First push 64-bit uniforms to ensure they are properly aligned */
2023 for (unsigned u
= 0; u
< uniforms
; u
++) {
2024 if (!is_live
[u
] || !is_live_64bit
[u
])
2027 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2028 push_constant_loc
, pull_constant_loc
,
2029 &num_push_constants
, &num_pull_constants
,
2030 max_push_components
, max_chunk_size
,
2035 /* Then push the rest of uniforms */
2036 for (unsigned u
= 0; u
< uniforms
; u
++) {
2037 if (!is_live
[u
] || is_live_64bit
[u
])
2040 /* Skip thread_local_id_index to put it in the last push register. */
2041 if (thread_local_id_index
== (int)u
)
2044 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2045 push_constant_loc
, pull_constant_loc
,
2046 &num_push_constants
, &num_pull_constants
,
2047 max_push_components
, max_chunk_size
,
2051 /* Add the CS local thread ID uniform at the end of the push constants */
2052 if (thread_local_id_index
>= 0)
2053 push_constant_loc
[thread_local_id_index
] = num_push_constants
++;
2055 /* As the uniforms are going to be reordered, take the data from a temporary
2056 * copy of the original param[].
2058 gl_constant_value
**param
= ralloc_array(NULL
, gl_constant_value
*,
2059 stage_prog_data
->nr_params
);
2060 memcpy(param
, stage_prog_data
->param
,
2061 sizeof(gl_constant_value
*) * stage_prog_data
->nr_params
);
2062 stage_prog_data
->nr_params
= num_push_constants
;
2063 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2065 /* Up until now, the param[] array has been indexed by reg + offset
2066 * of UNIFORM registers. Move pull constants into pull_param[] and
2067 * condense param[] to only contain the uniforms we chose to push.
2069 * NOTE: Because we are condensing the params[] array, we know that
2070 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2071 * having to make a copy.
2073 int new_thread_local_id_index
= -1;
2074 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2075 const gl_constant_value
*value
= param
[i
];
2077 if (pull_constant_loc
[i
] != -1) {
2078 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2079 } else if (push_constant_loc
[i
] != -1) {
2080 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2081 if (thread_local_id_index
== (int)i
)
2082 new_thread_local_id_index
= push_constant_loc
[i
];
2087 if (stage
== MESA_SHADER_COMPUTE
)
2088 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
=
2089 new_thread_local_id_index
;
2093 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2094 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2097 fs_visitor::lower_constant_loads()
2099 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2101 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2102 /* Set up the annotation tracking for new generated instructions. */
2103 const fs_builder
ibld(this, block
, inst
);
2105 for (int i
= 0; i
< inst
->sources
; i
++) {
2106 if (inst
->src
[i
].file
!= UNIFORM
)
2109 /* We'll handle this case later */
2110 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2113 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
2114 if (location
>= uniforms
)
2115 continue; /* Out of bounds access */
2117 int pull_index
= pull_constant_loc
[location
];
2119 if (pull_index
== -1)
2122 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2125 if (type_sz(inst
->src
[i
].type
) <= 4)
2126 dst
= vgrf(glsl_type::float_type
);
2128 dst
= vgrf(glsl_type::double_type
);
2130 assert(inst
->src
[i
].stride
== 0);
2132 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2133 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2134 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2135 dst
, brw_imm_ud(index
), offset
);
2137 /* Rewrite the instruction to use the temporary VGRF. */
2138 inst
->src
[i
].file
= VGRF
;
2139 inst
->src
[i
].nr
= dst
.nr
;
2140 inst
->src
[i
].offset
= (pull_index
& 3) * 4 + inst
->src
[i
].offset
% 4;
2142 brw_mark_surface_used(prog_data
, index
);
2145 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2146 inst
->src
[0].file
== UNIFORM
) {
2148 unsigned location
= inst
->src
[0].nr
+ inst
->src
[0].offset
/ 4;
2149 if (location
>= uniforms
)
2150 continue; /* Out of bounds access */
2152 int pull_index
= pull_constant_loc
[location
];
2154 if (pull_index
== -1)
2157 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2161 inst
->remove(block
);
2163 brw_mark_surface_used(prog_data
, index
);
2166 invalidate_live_intervals();
2170 fs_visitor::opt_algebraic()
2172 bool progress
= false;
2174 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2175 switch (inst
->opcode
) {
2176 case BRW_OPCODE_MOV
:
2177 if (inst
->src
[0].file
!= IMM
)
2180 if (inst
->saturate
) {
2181 if (inst
->dst
.type
!= inst
->src
[0].type
)
2182 assert(!"unimplemented: saturate mixed types");
2184 if (brw_saturate_immediate(inst
->dst
.type
,
2185 &inst
->src
[0].as_brw_reg())) {
2186 inst
->saturate
= false;
2192 case BRW_OPCODE_MUL
:
2193 if (inst
->src
[1].file
!= IMM
)
2197 if (inst
->src
[1].is_one()) {
2198 inst
->opcode
= BRW_OPCODE_MOV
;
2199 inst
->src
[1] = reg_undef
;
2205 if (inst
->src
[1].is_negative_one()) {
2206 inst
->opcode
= BRW_OPCODE_MOV
;
2207 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2208 inst
->src
[1] = reg_undef
;
2214 if (inst
->src
[1].is_zero()) {
2215 inst
->opcode
= BRW_OPCODE_MOV
;
2216 inst
->src
[0] = inst
->src
[1];
2217 inst
->src
[1] = reg_undef
;
2222 if (inst
->src
[0].file
== IMM
) {
2223 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2224 inst
->opcode
= BRW_OPCODE_MOV
;
2225 inst
->src
[0].f
*= inst
->src
[1].f
;
2226 inst
->src
[1] = reg_undef
;
2231 case BRW_OPCODE_ADD
:
2232 if (inst
->src
[1].file
!= IMM
)
2236 if (inst
->src
[1].is_zero()) {
2237 inst
->opcode
= BRW_OPCODE_MOV
;
2238 inst
->src
[1] = reg_undef
;
2243 if (inst
->src
[0].file
== IMM
) {
2244 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2245 inst
->opcode
= BRW_OPCODE_MOV
;
2246 inst
->src
[0].f
+= inst
->src
[1].f
;
2247 inst
->src
[1] = reg_undef
;
2253 if (inst
->src
[0].equals(inst
->src
[1])) {
2254 inst
->opcode
= BRW_OPCODE_MOV
;
2255 inst
->src
[1] = reg_undef
;
2260 case BRW_OPCODE_LRP
:
2261 if (inst
->src
[1].equals(inst
->src
[2])) {
2262 inst
->opcode
= BRW_OPCODE_MOV
;
2263 inst
->src
[0] = inst
->src
[1];
2264 inst
->src
[1] = reg_undef
;
2265 inst
->src
[2] = reg_undef
;
2270 case BRW_OPCODE_CMP
:
2271 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2273 inst
->src
[0].negate
&&
2274 inst
->src
[1].is_zero()) {
2275 inst
->src
[0].abs
= false;
2276 inst
->src
[0].negate
= false;
2277 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2282 case BRW_OPCODE_SEL
:
2283 if (inst
->src
[0].equals(inst
->src
[1])) {
2284 inst
->opcode
= BRW_OPCODE_MOV
;
2285 inst
->src
[1] = reg_undef
;
2286 inst
->predicate
= BRW_PREDICATE_NONE
;
2287 inst
->predicate_inverse
= false;
2289 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2290 switch (inst
->conditional_mod
) {
2291 case BRW_CONDITIONAL_LE
:
2292 case BRW_CONDITIONAL_L
:
2293 switch (inst
->src
[1].type
) {
2294 case BRW_REGISTER_TYPE_F
:
2295 if (inst
->src
[1].f
>= 1.0f
) {
2296 inst
->opcode
= BRW_OPCODE_MOV
;
2297 inst
->src
[1] = reg_undef
;
2298 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2306 case BRW_CONDITIONAL_GE
:
2307 case BRW_CONDITIONAL_G
:
2308 switch (inst
->src
[1].type
) {
2309 case BRW_REGISTER_TYPE_F
:
2310 if (inst
->src
[1].f
<= 0.0f
) {
2311 inst
->opcode
= BRW_OPCODE_MOV
;
2312 inst
->src
[1] = reg_undef
;
2313 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2325 case BRW_OPCODE_MAD
:
2326 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2327 inst
->opcode
= BRW_OPCODE_MOV
;
2328 inst
->src
[1] = reg_undef
;
2329 inst
->src
[2] = reg_undef
;
2331 } else if (inst
->src
[0].is_zero()) {
2332 inst
->opcode
= BRW_OPCODE_MUL
;
2333 inst
->src
[0] = inst
->src
[2];
2334 inst
->src
[2] = reg_undef
;
2336 } else if (inst
->src
[1].is_one()) {
2337 inst
->opcode
= BRW_OPCODE_ADD
;
2338 inst
->src
[1] = inst
->src
[2];
2339 inst
->src
[2] = reg_undef
;
2341 } else if (inst
->src
[2].is_one()) {
2342 inst
->opcode
= BRW_OPCODE_ADD
;
2343 inst
->src
[2] = reg_undef
;
2345 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2346 inst
->opcode
= BRW_OPCODE_ADD
;
2347 inst
->src
[1].f
*= inst
->src
[2].f
;
2348 inst
->src
[2] = reg_undef
;
2352 case SHADER_OPCODE_BROADCAST
:
2353 if (is_uniform(inst
->src
[0])) {
2354 inst
->opcode
= BRW_OPCODE_MOV
;
2356 inst
->force_writemask_all
= true;
2358 } else if (inst
->src
[1].file
== IMM
) {
2359 inst
->opcode
= BRW_OPCODE_MOV
;
2360 inst
->src
[0] = component(inst
->src
[0],
2363 inst
->force_writemask_all
= true;
2372 /* Swap if src[0] is immediate. */
2373 if (progress
&& inst
->is_commutative()) {
2374 if (inst
->src
[0].file
== IMM
) {
2375 fs_reg tmp
= inst
->src
[1];
2376 inst
->src
[1] = inst
->src
[0];
2385 * Optimize sample messages that have constant zero values for the trailing
2386 * texture coordinates. We can just reduce the message length for these
2387 * instructions instead of reserving a register for it. Trailing parameters
2388 * that aren't sent default to zero anyway. This will cause the dead code
2389 * eliminator to remove the MOV instruction that would otherwise be emitted to
2390 * set up the zero value.
2393 fs_visitor::opt_zero_samples()
2395 /* Gen4 infers the texturing opcode based on the message length so we can't
2398 if (devinfo
->gen
< 5)
2401 bool progress
= false;
2403 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2404 if (!inst
->is_tex())
2407 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2409 if (load_payload
->is_head_sentinel() ||
2410 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2413 /* We don't want to remove the message header or the first parameter.
2414 * Removing the first parameter is not allowed, see the Haswell PRM
2415 * volume 7, page 149:
2417 * "Parameter 0 is required except for the sampleinfo message, which
2418 * has no parameter 0"
2420 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2421 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2422 (inst
->exec_size
/ 8) +
2423 inst
->header_size
- 1].is_zero()) {
2424 inst
->mlen
-= inst
->exec_size
/ 8;
2430 invalidate_live_intervals();
2436 * Optimize sample messages which are followed by the final RT write.
2438 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2439 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2440 * final texturing results copied to the framebuffer write payload and modify
2441 * them to write to the framebuffer directly.
2444 fs_visitor::opt_sampler_eot()
2446 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2448 if (stage
!= MESA_SHADER_FRAGMENT
)
2451 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2454 /* FINISHME: It should be possible to implement this optimization when there
2455 * are multiple drawbuffers.
2457 if (key
->nr_color_regions
!= 1)
2460 /* Requires emitting a bunch of saturating MOV instructions during logical
2461 * send lowering to clamp the color payload, which the sampler unit isn't
2462 * going to do for us.
2464 if (key
->clamp_fragment_color
)
2467 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2468 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2469 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2470 assert(fb_write
->eot
);
2471 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2473 /* There wasn't one; nothing to do. */
2474 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2477 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2479 /* 3D Sampler » Messages » Message Format
2481 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2482 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2484 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2485 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2486 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2487 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2488 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2489 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2490 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2491 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2494 /* XXX - This shouldn't be necessary. */
2495 if (tex_inst
->prev
->is_head_sentinel())
2498 /* Check that the FB write sources are fully initialized by the single
2499 * texturing instruction.
2501 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2502 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2503 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2504 fb_write
->size_read(i
) != tex_inst
->size_written
)
2506 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2507 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2512 assert(!tex_inst
->eot
); /* We can't get here twice */
2513 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2515 const fs_builder
ibld(this, block
, tex_inst
);
2517 tex_inst
->offset
|= fb_write
->target
<< 24;
2518 tex_inst
->eot
= true;
2519 tex_inst
->dst
= ibld
.null_reg_ud();
2520 tex_inst
->size_written
= 0;
2521 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2523 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2524 * flag and submit a header together with the sampler message as required
2527 invalidate_live_intervals();
2532 fs_visitor::opt_register_renaming()
2534 bool progress
= false;
2537 int remap
[alloc
.count
];
2538 memset(remap
, -1, sizeof(int) * alloc
.count
);
2540 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2541 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2543 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2544 inst
->opcode
== BRW_OPCODE_WHILE
) {
2548 /* Rewrite instruction sources. */
2549 for (int i
= 0; i
< inst
->sources
; i
++) {
2550 if (inst
->src
[i
].file
== VGRF
&&
2551 remap
[inst
->src
[i
].nr
] != -1 &&
2552 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2553 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2558 const int dst
= inst
->dst
.nr
;
2561 inst
->dst
.file
== VGRF
&&
2562 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
2563 !inst
->is_partial_write()) {
2564 if (remap
[dst
] == -1) {
2567 remap
[dst
] = alloc
.allocate(regs_written(inst
));
2568 inst
->dst
.nr
= remap
[dst
];
2571 } else if (inst
->dst
.file
== VGRF
&&
2573 remap
[dst
] != dst
) {
2574 inst
->dst
.nr
= remap
[dst
];
2580 invalidate_live_intervals();
2582 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2583 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2584 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2593 * Remove redundant or useless discard jumps.
2595 * For example, we can eliminate jumps in the following sequence:
2597 * discard-jump (redundant with the next jump)
2598 * discard-jump (useless; jumps to the next instruction)
2602 fs_visitor::opt_redundant_discard_jumps()
2604 bool progress
= false;
2606 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2608 fs_inst
*placeholder_halt
= NULL
;
2609 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2610 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2611 placeholder_halt
= inst
;
2616 if (!placeholder_halt
)
2619 /* Delete any HALTs immediately before the placeholder halt. */
2620 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2621 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2622 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2623 prev
->remove(last_bblock
);
2628 invalidate_live_intervals();
2634 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2635 * from \p r.offset which overlaps the region starting at \p s.offset and
2636 * spanning \p ds bytes.
2638 static inline unsigned
2639 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
2641 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
2642 const int shift
= rel_offset
/ REG_SIZE
;
2643 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
2644 assert(reg_space(r
) == reg_space(s
) &&
2645 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
2646 return ((1 << n
) - 1) << shift
;
2650 fs_visitor::compute_to_mrf()
2652 bool progress
= false;
2655 /* No MRFs on Gen >= 7. */
2656 if (devinfo
->gen
>= 7)
2659 calculate_live_intervals();
2661 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2665 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2666 inst
->is_partial_write() ||
2667 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2668 inst
->dst
.type
!= inst
->src
[0].type
||
2669 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2670 !inst
->src
[0].is_contiguous() ||
2671 inst
->src
[0].offset
% REG_SIZE
!= 0)
2674 /* Can't compute-to-MRF this GRF if someone else was going to
2677 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2680 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2681 * things that computed the value of all GRFs of the source region. The
2682 * regs_left bitset keeps track of the registers we haven't yet found a
2683 * generating instruction for.
2685 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
2687 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2688 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2689 inst
->src
[0], inst
->size_read(0))) {
2690 /* Found the last thing to write our reg we want to turn
2691 * into a compute-to-MRF.
2694 /* If this one instruction didn't populate all the
2695 * channels, bail. We might be able to rewrite everything
2696 * that writes that reg, but it would require smarter
2699 if (scan_inst
->is_partial_write())
2702 /* Handling things not fully contained in the source of the copy
2703 * would need us to understand coalescing out more than one MOV at
2706 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
2707 inst
->src
[0], inst
->size_read(0)))
2710 /* SEND instructions can't have MRF as a destination. */
2711 if (scan_inst
->mlen
)
2714 if (devinfo
->gen
== 6) {
2715 /* gen6 math instructions must have the destination be
2716 * GRF, so no compute-to-MRF for them.
2718 if (scan_inst
->is_math()) {
2723 /* Clear the bits for any registers this instruction overwrites. */
2724 regs_left
&= ~mask_relative_to(
2725 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2730 /* We don't handle control flow here. Most computation of
2731 * values that end up in MRFs are shortly before the MRF
2734 if (block
->start() == scan_inst
)
2737 /* You can't read from an MRF, so if someone else reads our
2738 * MRF's source GRF that we wanted to rewrite, that stops us.
2740 bool interfered
= false;
2741 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2742 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
2743 inst
->src
[0], inst
->size_read(0))) {
2750 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2751 inst
->dst
, inst
->size_written
)) {
2752 /* If somebody else writes our MRF here, we can't
2753 * compute-to-MRF before that.
2758 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2759 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2760 inst
->dst
, inst
->size_written
)) {
2761 /* Found a SEND instruction, which means that there are
2762 * live values in MRFs from base_mrf to base_mrf +
2763 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2773 /* Found all generating instructions of our MRF's source value, so it
2774 * should be safe to rewrite them to point to the MRF directly.
2776 regs_left
= (1 << regs_read(inst
, 0)) - 1;
2778 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2779 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2780 inst
->src
[0], inst
->size_read(0))) {
2781 /* Clear the bits for any registers this instruction overwrites. */
2782 regs_left
&= ~mask_relative_to(
2783 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2785 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
2786 reg_offset(inst
->src
[0]);
2788 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2789 /* Apply the same address transformation done by the hardware
2790 * for COMPR4 MRF writes.
2792 assert(rel_offset
< 2 * REG_SIZE
);
2793 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
2795 /* Clear the COMPR4 bit if the generating instruction is not
2798 if (scan_inst
->size_written
< 2 * REG_SIZE
)
2799 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2802 /* Calculate the MRF number the result of this instruction is
2803 * ultimately written to.
2805 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
2808 scan_inst
->dst
.file
= MRF
;
2809 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
2810 scan_inst
->saturate
|= inst
->saturate
;
2817 inst
->remove(block
);
2822 invalidate_live_intervals();
2828 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2829 * flow. We could probably do better here with some form of divergence
2833 fs_visitor::eliminate_find_live_channel()
2835 bool progress
= false;
2838 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
2839 /* The optimization below assumes that channel zero is live on thread
2840 * dispatch, which may not be the case if the fixed function dispatches
2846 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2847 switch (inst
->opcode
) {
2853 case BRW_OPCODE_ENDIF
:
2854 case BRW_OPCODE_WHILE
:
2858 case FS_OPCODE_DISCARD_JUMP
:
2859 /* This can potentially make control flow non-uniform until the end
2864 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2866 inst
->opcode
= BRW_OPCODE_MOV
;
2867 inst
->src
[0] = brw_imm_ud(0u);
2869 inst
->force_writemask_all
= true;
2883 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2884 * instructions to FS_OPCODE_REP_FB_WRITE.
2887 fs_visitor::emit_repclear_shader()
2889 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2891 int color_mrf
= base_mrf
+ 2;
2895 mov
= bld
.exec_all().group(4, 0)
2896 .MOV(brw_message_reg(color_mrf
),
2897 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2899 struct brw_reg reg
=
2900 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2901 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
2902 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2904 mov
= bld
.exec_all().group(4, 0)
2905 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2909 if (key
->nr_color_regions
== 1) {
2910 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2911 write
->saturate
= key
->clamp_fragment_color
;
2912 write
->base_mrf
= color_mrf
;
2914 write
->header_size
= 0;
2917 assume(key
->nr_color_regions
> 0);
2918 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2919 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2920 write
->saturate
= key
->clamp_fragment_color
;
2921 write
->base_mrf
= base_mrf
;
2923 write
->header_size
= 2;
2931 assign_constant_locations();
2932 assign_curb_setup();
2934 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2936 assert(mov
->src
[0].file
== FIXED_GRF
);
2937 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2942 * Walks through basic blocks, looking for repeated MRF writes and
2943 * removing the later ones.
2946 fs_visitor::remove_duplicate_mrf_writes()
2948 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2949 bool progress
= false;
2951 /* Need to update the MRF tracking for compressed instructions. */
2952 if (dispatch_width
>= 16)
2955 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2957 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2958 if (inst
->is_control_flow()) {
2959 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2962 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2963 inst
->dst
.file
== MRF
) {
2964 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2965 if (prev_inst
&& inst
->equals(prev_inst
)) {
2966 inst
->remove(block
);
2972 /* Clear out the last-write records for MRFs that were overwritten. */
2973 if (inst
->dst
.file
== MRF
) {
2974 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2977 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2978 /* Found a SEND instruction, which will include two or fewer
2979 * implied MRF writes. We could do better here.
2981 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2982 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2986 /* Clear out any MRF move records whose sources got overwritten. */
2987 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2988 if (last_mrf_move
[i
] &&
2989 regions_overlap(inst
->dst
, inst
->size_written
,
2990 last_mrf_move
[i
]->src
[0],
2991 last_mrf_move
[i
]->size_read(0))) {
2992 last_mrf_move
[i
] = NULL
;
2996 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2997 inst
->dst
.file
== MRF
&&
2998 inst
->src
[0].file
!= ARF
&&
2999 !inst
->is_partial_write()) {
3000 last_mrf_move
[inst
->dst
.nr
] = inst
;
3005 invalidate_live_intervals();
3011 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3013 /* Clear the flag for registers that actually got read (as expected). */
3014 for (int i
= 0; i
< inst
->sources
; i
++) {
3016 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3017 grf
= inst
->src
[i
].nr
;
3022 if (grf
>= first_grf
&&
3023 grf
< first_grf
+ grf_len
) {
3024 deps
[grf
- first_grf
] = false;
3025 if (inst
->exec_size
== 16)
3026 deps
[grf
- first_grf
+ 1] = false;
3032 * Implements this workaround for the original 965:
3034 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3035 * check for post destination dependencies on this instruction, software
3036 * must ensure that there is no destination hazard for the case of ‘write
3037 * followed by a posted write’ shown in the following example.
3040 * 2. send r3.xy <rest of send instruction>
3043 * Due to no post-destination dependency check on the ‘send’, the above
3044 * code sequence could have two instructions (1 and 2) in flight at the
3045 * same time that both consider ‘r3’ as the target of their final writes.
3048 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3051 int write_len
= regs_written(inst
);
3052 int first_write_grf
= inst
->dst
.nr
;
3053 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3054 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3056 memset(needs_dep
, false, sizeof(needs_dep
));
3057 memset(needs_dep
, true, write_len
);
3059 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3061 /* Walk backwards looking for writes to registers we're writing which
3062 * aren't read since being written. If we hit the start of the program,
3063 * we assume that there are no outstanding dependencies on entry to the
3066 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3067 /* If we hit control flow, assume that there *are* outstanding
3068 * dependencies, and force their cleanup before our instruction.
3070 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3071 for (int i
= 0; i
< write_len
; i
++) {
3073 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3074 first_write_grf
+ i
);
3079 /* We insert our reads as late as possible on the assumption that any
3080 * instruction but a MOV that might have left us an outstanding
3081 * dependency has more latency than a MOV.
3083 if (scan_inst
->dst
.file
== VGRF
) {
3084 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3085 int reg
= scan_inst
->dst
.nr
+ i
;
3087 if (reg
>= first_write_grf
&&
3088 reg
< first_write_grf
+ write_len
&&
3089 needs_dep
[reg
- first_write_grf
]) {
3090 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3091 needs_dep
[reg
- first_write_grf
] = false;
3092 if (scan_inst
->exec_size
== 16)
3093 needs_dep
[reg
- first_write_grf
+ 1] = false;
3098 /* Clear the flag for registers that actually got read (as expected). */
3099 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3101 /* Continue the loop only if we haven't resolved all the dependencies */
3103 for (i
= 0; i
< write_len
; i
++) {
3113 * Implements this workaround for the original 965:
3115 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3116 * used as a destination register until after it has been sourced by an
3117 * instruction with a different destination register.
3120 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3122 int write_len
= regs_written(inst
);
3123 int first_write_grf
= inst
->dst
.nr
;
3124 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3125 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3127 memset(needs_dep
, false, sizeof(needs_dep
));
3128 memset(needs_dep
, true, write_len
);
3129 /* Walk forwards looking for writes to registers we're writing which aren't
3130 * read before being written.
3132 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3133 /* If we hit control flow, force resolve all remaining dependencies. */
3134 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3135 for (int i
= 0; i
< write_len
; i
++) {
3137 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3138 first_write_grf
+ i
);
3143 /* Clear the flag for registers that actually got read (as expected). */
3144 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3146 /* We insert our reads as late as possible since they're reading the
3147 * result of a SEND, which has massive latency.
3149 if (scan_inst
->dst
.file
== VGRF
&&
3150 scan_inst
->dst
.nr
>= first_write_grf
&&
3151 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3152 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3153 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3155 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3158 /* Continue the loop only if we haven't resolved all the dependencies */
3160 for (i
= 0; i
< write_len
; i
++) {
3170 fs_visitor::insert_gen4_send_dependency_workarounds()
3172 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3175 bool progress
= false;
3177 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3178 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3179 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3180 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3186 invalidate_live_intervals();
3190 * Turns the generic expression-style uniform pull constant load instruction
3191 * into a hardware-specific series of instructions for loading a pull
3194 * The expression style allows the CSE pass before this to optimize out
3195 * repeated loads from the same offset, and gives the pre-register-allocation
3196 * scheduling full flexibility, while the conversion to native instructions
3197 * allows the post-register-allocation scheduler the best information
3200 * Note that execution masking for setting up pull constant loads is special:
3201 * the channels that need to be written are unrelated to the current execution
3202 * mask, since a later instruction will use one of the result channels as a
3203 * source operand for all 8 or 16 of its channels.
3206 fs_visitor::lower_uniform_pull_constant_loads()
3208 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3209 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3212 if (devinfo
->gen
>= 7) {
3213 /* The offset arg is a vec4-aligned immediate byte offset. */
3214 fs_reg const_offset_reg
= inst
->src
[1];
3215 assert(const_offset_reg
.file
== IMM
&&
3216 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3217 assert(const_offset_reg
.ud
% 16 == 0);
3219 fs_reg payload
, offset
;
3220 if (devinfo
->gen
>= 9) {
3221 /* We have to use a message header on Skylake to get SIMD4x2
3222 * mode. Reserve space for the register.
3224 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3225 offset
.offset
+= REG_SIZE
;
3228 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3232 /* This is actually going to be a MOV, but since only the first dword
3233 * is accessed, we have a special opcode to do just that one. Note
3234 * that this needs to be an operation that will be considered a def
3235 * by live variable analysis, or register allocation will explode.
3237 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3238 8, offset
, const_offset_reg
);
3239 setup
->force_writemask_all
= true;
3241 setup
->ir
= inst
->ir
;
3242 setup
->annotation
= inst
->annotation
;
3243 inst
->insert_before(block
, setup
);
3245 /* Similarly, this will only populate the first 4 channels of the
3246 * result register (since we only use smear values from 0-3), but we
3247 * don't tell the optimizer.
3249 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3250 inst
->src
[1] = payload
;
3252 invalidate_live_intervals();
3254 /* Before register allocation, we didn't tell the scheduler about the
3255 * MRF we use. We know it's safe to use this MRF because nothing
3256 * else does except for register spill/unspill, which generates and
3257 * uses its MRF within a single IR instruction.
3259 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3266 fs_visitor::lower_load_payload()
3268 bool progress
= false;
3270 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3271 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3274 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3275 assert(inst
->saturate
== false);
3276 fs_reg dst
= inst
->dst
;
3278 /* Get rid of COMPR4. We'll add it back in if we need it */
3279 if (dst
.file
== MRF
)
3280 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3282 const fs_builder
ibld(this, block
, inst
);
3283 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3285 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3286 if (inst
->src
[i
].file
!= BAD_FILE
) {
3287 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3288 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3289 hbld
.MOV(mov_dst
, mov_src
);
3291 dst
= offset(dst
, hbld
, 1);
3294 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3295 inst
->exec_size
> 8) {
3296 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3297 * a straightforward copy. Instead, the result of the
3298 * LOAD_PAYLOAD is treated as interleaved and the first four
3299 * non-header sources are unpacked as:
3310 * This is used for gen <= 5 fb writes.
3312 assert(inst
->exec_size
== 16);
3313 assert(inst
->header_size
+ 4 <= inst
->sources
);
3314 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3315 if (inst
->src
[i
].file
!= BAD_FILE
) {
3316 if (devinfo
->has_compr4
) {
3317 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3318 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3319 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3321 /* Platform doesn't have COMPR4. We have to fake it */
3322 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3323 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3325 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3332 /* The loop above only ever incremented us through the first set
3333 * of 4 registers. However, thanks to the magic of COMPR4, we
3334 * actually wrote to the first 8 registers, so we need to take
3335 * that into account now.
3339 /* The COMPR4 code took care of the first 4 sources. We'll let
3340 * the regular path handle any remaining sources. Yes, we are
3341 * modifying the instruction but we're about to delete it so
3342 * this really doesn't hurt anything.
3344 inst
->header_size
+= 4;
3347 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3348 if (inst
->src
[i
].file
!= BAD_FILE
)
3349 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3350 dst
= offset(dst
, ibld
, 1);
3353 inst
->remove(block
);
3358 invalidate_live_intervals();
3364 fs_visitor::lower_integer_multiplication()
3366 bool progress
= false;
3368 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3369 const fs_builder
ibld(this, block
, inst
);
3371 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3372 if (inst
->dst
.is_accumulator() ||
3373 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3374 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3377 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3378 * operation directly, but CHV/BXT cannot.
3380 if (devinfo
->gen
>= 8 &&
3381 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3384 if (inst
->src
[1].file
== IMM
&&
3385 inst
->src
[1].ud
< (1 << 16)) {
3386 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3387 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3390 * If multiplying by an immediate value that fits in 16-bits, do a
3391 * single MUL instruction with that value in the proper location.
3393 if (devinfo
->gen
< 7) {
3394 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3396 ibld
.MOV(imm
, inst
->src
[1]);
3397 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3399 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3400 ibld
.MUL(inst
->dst
, inst
->src
[0],
3401 ud
? brw_imm_uw(inst
->src
[1].ud
)
3402 : brw_imm_w(inst
->src
[1].d
));
3405 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3406 * do 32-bit integer multiplication in one instruction, but instead
3407 * must do a sequence (which actually calculates a 64-bit result):
3409 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3410 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3411 * mov(8) g2<1>D acc0<8,8,1>D
3413 * But on Gen > 6, the ability to use second accumulator register
3414 * (acc1) for non-float data types was removed, preventing a simple
3415 * implementation in SIMD16. A 16-channel result can be calculated by
3416 * executing the three instructions twice in SIMD8, once with quarter
3417 * control of 1Q for the first eight channels and again with 2Q for
3418 * the second eight channels.
3420 * Which accumulator register is implicitly accessed (by AccWrEnable
3421 * for instance) is determined by the quarter control. Unfortunately
3422 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3423 * implicit accumulator access by an instruction with 2Q will access
3424 * acc1 regardless of whether the data type is usable in acc1.
3426 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3427 * integer data types.
3429 * Since we only want the low 32-bits of the result, we can do two
3430 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3431 * adjust the high result and add them (like the mach is doing):
3433 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3434 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3435 * shl(8) g9<1>D g8<8,8,1>D 16D
3436 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3438 * We avoid the shl instruction by realizing that we only want to add
3439 * the low 16-bits of the "high" result to the high 16-bits of the
3440 * "low" result and using proper regioning on the add:
3442 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3443 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3444 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3446 * Since it does not use the (single) accumulator register, we can
3447 * schedule multi-component multiplications much better.
3450 fs_reg orig_dst
= inst
->dst
;
3451 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3452 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3455 fs_reg low
= inst
->dst
;
3456 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3459 if (devinfo
->gen
>= 7) {
3460 if (inst
->src
[1].file
== IMM
) {
3461 ibld
.MUL(low
, inst
->src
[0],
3462 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3463 ibld
.MUL(high
, inst
->src
[0],
3464 brw_imm_uw(inst
->src
[1].ud
>> 16));
3466 ibld
.MUL(low
, inst
->src
[0],
3467 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3468 ibld
.MUL(high
, inst
->src
[0],
3469 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3472 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
3474 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
3478 ibld
.ADD(subscript(inst
->dst
, BRW_REGISTER_TYPE_UW
, 1),
3479 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3480 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
3482 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3483 set_condmod(inst
->conditional_mod
,
3484 ibld
.MOV(orig_dst
, inst
->dst
));
3488 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3489 /* Should have been lowered to 8-wide. */
3490 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3491 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3493 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3494 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3496 if (devinfo
->gen
>= 8) {
3497 /* Until Gen8, integer multiplies read 32-bits from one source,
3498 * and 16-bits from the other, and relying on the MACH instruction
3499 * to generate the high bits of the result.
3501 * On Gen8, the multiply instruction does a full 32x32-bit
3502 * multiply, but in order to do a 64-bit multiply we can simulate
3503 * the previous behavior and then use a MACH instruction.
3505 * FINISHME: Don't use source modifiers on src1.
3507 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3508 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3509 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3510 mul
->src
[1].stride
*= 2;
3512 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3514 /* Among other things the quarter control bits influence which
3515 * accumulator register is used by the hardware for instructions
3516 * that access the accumulator implicitly (e.g. MACH). A
3517 * second-half instruction would normally map to acc1, which
3518 * doesn't exist on Gen7 and up (the hardware does emulate it for
3519 * floating-point instructions *only* by taking advantage of the
3520 * extra precision of acc0 not normally used for floating point
3523 * HSW and up are careful enough not to try to access an
3524 * accumulator register that doesn't exist, but on earlier Gen7
3525 * hardware we need to make sure that the quarter control bits are
3526 * zero to avoid non-deterministic behaviour and emit an extra MOV
3527 * to get the result masked correctly according to the current
3531 mach
->force_writemask_all
= true;
3532 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3533 ibld
.MOV(inst
->dst
, mach
->dst
);
3539 inst
->remove(block
);
3544 invalidate_live_intervals();
3550 fs_visitor::lower_minmax()
3552 assert(devinfo
->gen
< 6);
3554 bool progress
= false;
3556 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3557 const fs_builder
ibld(this, block
, inst
);
3559 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3560 inst
->predicate
== BRW_PREDICATE_NONE
) {
3561 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3562 * the original SEL.L/GE instruction
3564 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3565 inst
->conditional_mod
);
3566 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3567 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3574 invalidate_live_intervals();
3580 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3581 fs_reg
*dst
, fs_reg color
, unsigned components
)
3583 if (key
->clamp_fragment_color
) {
3584 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3585 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3587 for (unsigned i
= 0; i
< components
; i
++)
3589 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3594 for (unsigned i
= 0; i
< components
; i
++)
3595 dst
[i
] = offset(color
, bld
, i
);
3599 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3600 const brw_wm_prog_data
*prog_data
,
3601 const brw_wm_prog_key
*key
,
3602 const fs_visitor::thread_payload
&payload
)
3604 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3605 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3606 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3607 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3608 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3609 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3610 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3611 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3612 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3613 const unsigned components
=
3614 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3616 /* We can potentially have a message length of up to 15, so we have to set
3617 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3620 int header_size
= 2, payload_header_size
;
3621 unsigned length
= 0;
3623 /* From the Sandy Bridge PRM, volume 4, page 198:
3625 * "Dispatched Pixel Enables. One bit per pixel indicating
3626 * which pixels were originally enabled when the thread was
3627 * dispatched. This field is only required for the end-of-
3628 * thread message and on all dual-source messages."
3630 if (devinfo
->gen
>= 6 &&
3631 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3632 color1
.file
== BAD_FILE
&&
3633 key
->nr_color_regions
== 1) {
3637 if (header_size
!= 0) {
3638 assert(header_size
== 2);
3639 /* Allocate 2 registers for a header */
3643 if (payload
.aa_dest_stencil_reg
) {
3644 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3645 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3646 .MOV(sources
[length
],
3647 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3651 if (sample_mask
.file
!= BAD_FILE
) {
3652 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3653 BRW_REGISTER_TYPE_UD
);
3655 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3656 * relevant. Since it's unsigned single words one vgrf is always
3657 * 16-wide, but only the lower or higher 8 channels will be used by the
3658 * hardware when doing a SIMD8 write depending on whether we have
3659 * selected the subspans for the first or second half respectively.
3661 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3662 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3663 sample_mask
.stride
*= 2;
3665 bld
.exec_all().annotate("FB write oMask")
3666 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3672 payload_header_size
= length
;
3674 if (src0_alpha
.file
!= BAD_FILE
) {
3675 /* FIXME: This is being passed at the wrong location in the payload and
3676 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3677 * It's supposed to be immediately before oMask but there seems to be no
3678 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3679 * requires header sources to form a contiguous segment at the beginning
3680 * of the message and src0_alpha has per-channel semantics.
3682 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3686 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3689 if (color1
.file
!= BAD_FILE
) {
3690 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3694 if (src_depth
.file
!= BAD_FILE
) {
3695 sources
[length
] = src_depth
;
3699 if (dst_depth
.file
!= BAD_FILE
) {
3700 sources
[length
] = dst_depth
;
3704 if (src_stencil
.file
!= BAD_FILE
) {
3705 assert(devinfo
->gen
>= 9);
3706 assert(bld
.dispatch_width() != 16);
3708 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3709 * available on gen9+. As such it's impossible to have both enabled at the
3710 * same time and therefore length cannot overrun the array.
3712 assert(length
< 15);
3714 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3715 bld
.exec_all().annotate("FB write OS")
3716 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3717 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3722 if (devinfo
->gen
>= 7) {
3723 /* Send from the GRF */
3724 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3725 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3726 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
3727 load
->dst
= payload
;
3729 inst
->src
[0] = payload
;
3730 inst
->resize_sources(1);
3732 /* Send from the MRF */
3733 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3734 sources
, length
, payload_header_size
);
3736 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3737 * will do this for us if we just give it a COMPR4 destination.
3739 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3740 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3742 inst
->resize_sources(0);
3746 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3747 inst
->mlen
= regs_written(load
);
3748 inst
->header_size
= header_size
;
3752 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
3754 const fs_builder
&ubld
= bld
.exec_all();
3755 const unsigned length
= 2;
3756 const fs_reg header
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
, length
);
3759 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3761 inst
->resize_sources(1);
3762 inst
->src
[0] = header
;
3763 inst
->opcode
= FS_OPCODE_FB_READ
;
3764 inst
->mlen
= length
;
3765 inst
->header_size
= length
;
3769 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3770 const fs_reg
&coordinate
,
3771 const fs_reg
&shadow_c
,
3772 const fs_reg
&lod
, const fs_reg
&lod2
,
3773 const fs_reg
&surface
,
3774 const fs_reg
&sampler
,
3775 unsigned coord_components
,
3776 unsigned grad_components
)
3778 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3779 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3780 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3781 fs_reg msg_end
= msg_begin
;
3784 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3786 for (unsigned i
= 0; i
< coord_components
; i
++)
3787 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3788 offset(coordinate
, bld
, i
));
3790 msg_end
= offset(msg_end
, bld
, coord_components
);
3792 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3793 * require all three components to be present and zero if they are unused.
3795 if (coord_components
> 0 &&
3796 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3797 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3798 for (unsigned i
= coord_components
; i
< 3; i
++)
3799 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3801 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3804 if (op
== SHADER_OPCODE_TXD
) {
3805 /* TXD unsupported in SIMD16 mode. */
3806 assert(bld
.dispatch_width() == 8);
3808 /* the slots for u and v are always present, but r is optional */
3809 if (coord_components
< 2)
3810 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3813 * dPdx = dudx, dvdx, drdx
3814 * dPdy = dudy, dvdy, drdy
3816 * 1-arg: Does not exist.
3818 * 2-arg: dudx dvdx dudy dvdy
3819 * dPdx.x dPdx.y dPdy.x dPdy.y
3822 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3823 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3824 * m5 m6 m7 m8 m9 m10
3826 for (unsigned i
= 0; i
< grad_components
; i
++)
3827 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3829 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3831 for (unsigned i
= 0; i
< grad_components
; i
++)
3832 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3834 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3838 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3839 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3841 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3842 bld
.dispatch_width() == 16);
3844 const brw_reg_type type
=
3845 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3846 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3847 bld
.MOV(retype(msg_end
, type
), lod
);
3848 msg_end
= offset(msg_end
, bld
, 1);
3851 if (shadow_c
.file
!= BAD_FILE
) {
3852 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3853 /* There's no plain shadow compare message, so we use shadow
3854 * compare with a bias of 0.0.
3856 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3857 msg_end
= offset(msg_end
, bld
, 1);
3860 bld
.MOV(msg_end
, shadow_c
);
3861 msg_end
= offset(msg_end
, bld
, 1);
3865 inst
->src
[0] = reg_undef
;
3866 inst
->src
[1] = surface
;
3867 inst
->src
[2] = sampler
;
3868 inst
->resize_sources(3);
3869 inst
->base_mrf
= msg_begin
.nr
;
3870 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3871 inst
->header_size
= 1;
3875 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3876 const fs_reg
&coordinate
,
3877 const fs_reg
&shadow_c
,
3878 const fs_reg
&lod
, const fs_reg
&lod2
,
3879 const fs_reg
&sample_index
,
3880 const fs_reg
&surface
,
3881 const fs_reg
&sampler
,
3882 const fs_reg
&offset_value
,
3883 unsigned coord_components
,
3884 unsigned grad_components
)
3886 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3887 fs_reg msg_coords
= message
;
3888 unsigned header_size
= 0;
3890 if (offset_value
.file
!= BAD_FILE
) {
3891 /* The offsets set up by the visitor are in the m1 header, so we can't
3898 for (unsigned i
= 0; i
< coord_components
; i
++)
3899 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
3900 offset(coordinate
, bld
, i
));
3902 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3903 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3905 if (shadow_c
.file
!= BAD_FILE
) {
3906 fs_reg msg_shadow
= msg_lod
;
3907 bld
.MOV(msg_shadow
, shadow_c
);
3908 msg_lod
= offset(msg_shadow
, bld
, 1);
3913 case SHADER_OPCODE_TXL
:
3915 bld
.MOV(msg_lod
, lod
);
3916 msg_end
= offset(msg_lod
, bld
, 1);
3918 case SHADER_OPCODE_TXD
:
3921 * dPdx = dudx, dvdx, drdx
3922 * dPdy = dudy, dvdy, drdy
3924 * Load up these values:
3925 * - dudx dudy dvdx dvdy drdx drdy
3926 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3929 for (unsigned i
= 0; i
< grad_components
; i
++) {
3930 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
3931 msg_end
= offset(msg_end
, bld
, 1);
3933 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
3934 msg_end
= offset(msg_end
, bld
, 1);
3937 case SHADER_OPCODE_TXS
:
3938 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3939 bld
.MOV(msg_lod
, lod
);
3940 msg_end
= offset(msg_lod
, bld
, 1);
3942 case SHADER_OPCODE_TXF
:
3943 msg_lod
= offset(msg_coords
, bld
, 3);
3944 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3945 msg_end
= offset(msg_lod
, bld
, 1);
3947 case SHADER_OPCODE_TXF_CMS
:
3948 msg_lod
= offset(msg_coords
, bld
, 3);
3950 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3952 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3953 msg_end
= offset(msg_lod
, bld
, 2);
3960 inst
->src
[0] = reg_undef
;
3961 inst
->src
[1] = surface
;
3962 inst
->src
[2] = sampler
;
3963 inst
->resize_sources(3);
3964 inst
->base_mrf
= message
.nr
;
3965 inst
->mlen
= msg_end
.nr
- message
.nr
;
3966 inst
->header_size
= header_size
;
3968 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3969 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3973 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
3975 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3978 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
3982 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3983 const fs_reg
&coordinate
,
3984 const fs_reg
&shadow_c
,
3985 fs_reg lod
, const fs_reg
&lod2
,
3986 const fs_reg
&sample_index
,
3988 const fs_reg
&surface
,
3989 const fs_reg
&sampler
,
3990 const fs_reg
&offset_value
,
3991 unsigned coord_components
,
3992 unsigned grad_components
)
3994 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3995 unsigned reg_width
= bld
.dispatch_width() / 8;
3996 unsigned header_size
= 0, length
= 0;
3997 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3998 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3999 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4001 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4002 offset_value
.file
!= BAD_FILE
|| inst
->eot
||
4003 op
== SHADER_OPCODE_SAMPLEINFO
||
4004 is_high_sampler(devinfo
, sampler
)) {
4005 /* For general texture offsets (no txf workaround), we need a header to
4006 * put them in. Note that we're only reserving space for it in the
4007 * message payload as it will be initialized implicitly by the
4010 * TG4 needs to place its channel select in the header, for interaction
4011 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4012 * larger sampler numbers we need to offset the Sampler State Pointer in
4016 sources
[0] = fs_reg();
4019 /* If we're requesting fewer than four channels worth of response,
4020 * and we have an explicit header, we need to set up the sampler
4021 * writemask. It's reversed from normal: 1 means "don't write".
4023 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4024 assert(regs_written(inst
) % reg_width
== 0);
4025 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4026 inst
->offset
|= mask
<< 12;
4030 if (shadow_c
.file
!= BAD_FILE
) {
4031 bld
.MOV(sources
[length
], shadow_c
);
4035 bool coordinate_done
= false;
4037 /* Set up the LOD info */
4040 case SHADER_OPCODE_TXL
:
4041 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4042 op
= SHADER_OPCODE_TXL_LZ
;
4045 bld
.MOV(sources
[length
], lod
);
4048 case SHADER_OPCODE_TXD
:
4049 /* TXD should have been lowered in SIMD16 mode. */
4050 assert(bld
.dispatch_width() == 8);
4052 /* Load dPdx and the coordinate together:
4053 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4055 for (unsigned i
= 0; i
< coord_components
; i
++) {
4056 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4058 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4059 * only derivatives for (u, v, r).
4061 if (i
< grad_components
) {
4062 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4063 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4067 coordinate_done
= true;
4069 case SHADER_OPCODE_TXS
:
4070 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4073 case SHADER_OPCODE_TXF
:
4074 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4075 * On Gen9 they are u, v, lod, r
4077 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4079 if (devinfo
->gen
>= 9) {
4080 if (coord_components
>= 2) {
4081 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4082 offset(coordinate
, bld
, 1));
4084 sources
[length
] = brw_imm_d(0);
4089 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4090 op
= SHADER_OPCODE_TXF_LZ
;
4092 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4096 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4097 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4098 offset(coordinate
, bld
, i
));
4100 coordinate_done
= true;
4103 case SHADER_OPCODE_TXF_CMS
:
4104 case SHADER_OPCODE_TXF_CMS_W
:
4105 case SHADER_OPCODE_TXF_UMS
:
4106 case SHADER_OPCODE_TXF_MCS
:
4107 if (op
== SHADER_OPCODE_TXF_UMS
||
4108 op
== SHADER_OPCODE_TXF_CMS
||
4109 op
== SHADER_OPCODE_TXF_CMS_W
) {
4110 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4114 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4115 /* Data from the multisample control surface. */
4116 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4119 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4122 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4123 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4126 offset(mcs
, bld
, 1));
4131 /* There is no offsetting for this message; just copy in the integer
4132 * texture coordinates.
4134 for (unsigned i
= 0; i
< coord_components
; i
++)
4135 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4136 offset(coordinate
, bld
, i
));
4138 coordinate_done
= true;
4140 case SHADER_OPCODE_TG4_OFFSET
:
4141 /* More crazy intermixing */
4142 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4143 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4145 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4146 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4147 offset(offset_value
, bld
, i
));
4149 if (coord_components
== 3) /* r if present */
4150 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4152 coordinate_done
= true;
4158 /* Set up the coordinate (except for cases where it was done above) */
4159 if (!coordinate_done
) {
4160 for (unsigned i
= 0; i
< coord_components
; i
++)
4161 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4166 mlen
= length
* reg_width
- header_size
;
4168 mlen
= length
* reg_width
;
4170 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4171 BRW_REGISTER_TYPE_F
);
4172 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4174 /* Generate the SEND. */
4176 inst
->src
[0] = src_payload
;
4177 inst
->src
[1] = surface
;
4178 inst
->src
[2] = sampler
;
4179 inst
->resize_sources(3);
4181 inst
->header_size
= header_size
;
4183 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4184 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4188 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4190 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4191 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4192 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4193 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4194 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4195 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4196 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4197 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4198 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4199 const fs_reg
&offset_value
= inst
->src
[TEX_LOGICAL_SRC_OFFSET_VALUE
];
4200 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4201 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4202 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4203 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4205 if (devinfo
->gen
>= 7) {
4206 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4207 shadow_c
, lod
, lod2
, sample_index
,
4208 mcs
, surface
, sampler
, offset_value
,
4209 coord_components
, grad_components
);
4210 } else if (devinfo
->gen
>= 5) {
4211 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4212 shadow_c
, lod
, lod2
, sample_index
,
4213 surface
, sampler
, offset_value
,
4214 coord_components
, grad_components
);
4216 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4217 shadow_c
, lod
, lod2
,
4219 coord_components
, grad_components
);
4224 * Initialize the header present in some typed and untyped surface
4228 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4230 fs_builder ubld
= bld
.exec_all().group(8, 0);
4231 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4232 ubld
.MOV(dst
, brw_imm_d(0));
4233 ubld
.MOV(component(dst
, 7), sample_mask
);
4238 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4239 const fs_reg
&sample_mask
)
4241 /* Get the logical send arguments. */
4242 const fs_reg
&addr
= inst
->src
[0];
4243 const fs_reg
&src
= inst
->src
[1];
4244 const fs_reg
&surface
= inst
->src
[2];
4245 const UNUSED fs_reg
&dims
= inst
->src
[3];
4246 const fs_reg
&arg
= inst
->src
[4];
4248 /* Calculate the total number of components of the payload. */
4249 const unsigned addr_sz
= inst
->components_read(0);
4250 const unsigned src_sz
= inst
->components_read(1);
4251 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4252 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4254 /* Allocate space for the payload. */
4255 fs_reg
*const components
= new fs_reg
[sz
];
4256 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4259 /* Construct the payload. */
4261 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4263 for (unsigned i
= 0; i
< addr_sz
; i
++)
4264 components
[n
++] = offset(addr
, bld
, i
);
4266 for (unsigned i
= 0; i
< src_sz
; i
++)
4267 components
[n
++] = offset(src
, bld
, i
);
4269 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4271 /* Update the original instruction. */
4273 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4274 inst
->header_size
= header_sz
;
4276 inst
->src
[0] = payload
;
4277 inst
->src
[1] = surface
;
4279 inst
->resize_sources(3);
4281 delete[] components
;
4285 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4287 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4289 if (devinfo
->gen
>= 7) {
4290 /* We are switching the instruction from an ALU-like instruction to a
4291 * send-from-grf instruction. Since sends can't handle strides or
4292 * source modifiers, we have to make a copy of the offset source.
4294 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4295 bld
.MOV(tmp
, inst
->src
[1]);
4298 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4301 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4302 BRW_REGISTER_TYPE_UD
);
4304 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4306 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4307 inst
->resize_sources(1);
4308 inst
->base_mrf
= payload
.nr
;
4309 inst
->header_size
= 1;
4310 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4315 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4317 assert(bld
.shader
->devinfo
->gen
< 6);
4320 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4322 if (inst
->sources
> 1) {
4323 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4324 * "Message Payload":
4326 * "Operand0[7]. For the INT DIV functions, this operand is the
4329 * "Operand1[7]. For the INT DIV functions, this operand is the
4332 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4333 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4334 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4336 inst
->resize_sources(1);
4337 inst
->src
[0] = src0
;
4339 assert(inst
->exec_size
== 8);
4340 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4345 fs_visitor::lower_logical_sends()
4347 bool progress
= false;
4349 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4350 const fs_builder
ibld(this, block
, inst
);
4352 switch (inst
->opcode
) {
4353 case FS_OPCODE_FB_WRITE_LOGICAL
:
4354 assert(stage
== MESA_SHADER_FRAGMENT
);
4355 lower_fb_write_logical_send(ibld
, inst
,
4356 (const brw_wm_prog_data
*)prog_data
,
4357 (const brw_wm_prog_key
*)key
,
4361 case FS_OPCODE_FB_READ_LOGICAL
:
4362 lower_fb_read_logical_send(ibld
, inst
);
4365 case SHADER_OPCODE_TEX_LOGICAL
:
4366 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4369 case SHADER_OPCODE_TXD_LOGICAL
:
4370 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4373 case SHADER_OPCODE_TXF_LOGICAL
:
4374 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4377 case SHADER_OPCODE_TXL_LOGICAL
:
4378 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4381 case SHADER_OPCODE_TXS_LOGICAL
:
4382 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4385 case FS_OPCODE_TXB_LOGICAL
:
4386 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4389 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4390 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4393 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4394 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4397 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4398 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4401 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4402 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4405 case SHADER_OPCODE_LOD_LOGICAL
:
4406 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4409 case SHADER_OPCODE_TG4_LOGICAL
:
4410 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4413 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4414 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4417 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4418 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4421 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4422 lower_surface_logical_send(ibld
, inst
,
4423 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4427 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4428 lower_surface_logical_send(ibld
, inst
,
4429 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4430 ibld
.sample_mask_reg());
4433 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4434 lower_surface_logical_send(ibld
, inst
,
4435 SHADER_OPCODE_UNTYPED_ATOMIC
,
4436 ibld
.sample_mask_reg());
4439 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4440 lower_surface_logical_send(ibld
, inst
,
4441 SHADER_OPCODE_TYPED_SURFACE_READ
,
4445 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4446 lower_surface_logical_send(ibld
, inst
,
4447 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4448 ibld
.sample_mask_reg());
4451 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4452 lower_surface_logical_send(ibld
, inst
,
4453 SHADER_OPCODE_TYPED_ATOMIC
,
4454 ibld
.sample_mask_reg());
4457 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4458 lower_varying_pull_constant_logical_send(ibld
, inst
);
4461 case SHADER_OPCODE_RCP
:
4462 case SHADER_OPCODE_RSQ
:
4463 case SHADER_OPCODE_SQRT
:
4464 case SHADER_OPCODE_EXP2
:
4465 case SHADER_OPCODE_LOG2
:
4466 case SHADER_OPCODE_SIN
:
4467 case SHADER_OPCODE_COS
:
4468 case SHADER_OPCODE_POW
:
4469 case SHADER_OPCODE_INT_QUOTIENT
:
4470 case SHADER_OPCODE_INT_REMAINDER
:
4471 /* The math opcodes are overloaded for the send-like and
4472 * expression-like instructions which seems kind of icky. Gen6+ has
4473 * a native (but rather quirky) MATH instruction so we don't need to
4474 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4475 * logical instructions (which we can easily recognize because they
4476 * have mlen = 0) into send-like virtual instructions.
4478 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4479 lower_math_logical_send(ibld
, inst
);
4494 invalidate_live_intervals();
4500 * Get the closest allowed SIMD width for instruction \p inst accounting for
4501 * some common regioning and execution control restrictions that apply to FPU
4502 * instructions. These restrictions don't necessarily have any relevance to
4503 * instructions not executed by the FPU pipeline like extended math, control
4504 * flow or send message instructions.
4506 * For virtual opcodes it's really up to the instruction -- In some cases
4507 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4508 * instructions) it may simplify virtual instruction lowering if we can
4509 * enforce FPU-like regioning restrictions already on the virtual instruction,
4510 * in other cases (e.g. virtual send-like instructions) this may be
4511 * excessively restrictive.
4514 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
4515 const fs_inst
*inst
)
4517 /* Maximum execution size representable in the instruction controls. */
4518 unsigned max_width
= MIN2(32, inst
->exec_size
);
4520 /* According to the PRMs:
4521 * "A. In Direct Addressing mode, a source cannot span more than 2
4522 * adjacent GRF registers.
4523 * B. A destination cannot span more than 2 adjacent GRF registers."
4525 * Look for the source or destination with the largest register region
4526 * which is the one that is going to limit the overall execution size of
4527 * the instruction due to this rule.
4529 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4531 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4532 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
4534 /* Calculate the maximum execution size of the instruction based on the
4535 * factor by which it goes over the hardware limit of 2 GRFs.
4538 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4540 /* According to the IVB PRMs:
4541 * "When destination spans two registers, the source MUST span two
4542 * registers. The exception to the above rule:
4544 * - When source is scalar, the source registers are not incremented.
4545 * - When source is packed integer Word and destination is packed
4546 * integer DWord, the source register is not incremented but the
4547 * source sub register is incremented."
4549 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4550 * restrictions. The code below intentionally doesn't check whether the
4551 * destination type is integer because empirically the hardware doesn't
4552 * seem to care what the actual type is as long as it's dword-aligned.
4554 if (devinfo
->gen
< 8) {
4555 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4556 if (inst
->size_written
> REG_SIZE
&&
4557 inst
->size_read(i
) != 0 && inst
->size_read(i
) <= REG_SIZE
&&
4558 !is_uniform(inst
->src
[i
]) &&
4559 !(type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4560 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1)) {
4561 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4562 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4567 /* From the IVB PRMs:
4568 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4569 * are applied for both halves of the SIMD32 instruction. If different
4570 * execution mask channels are required, split the instruction into two
4571 * SIMD16 instructions."
4573 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4574 * 32-wide control flow support in hardware and will behave similarly.
4576 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4577 max_width
= MIN2(max_width
, 16);
4579 /* From the IVB PRMs (applies to HSW too):
4580 * "Instructions with condition modifiers must not use SIMD32."
4582 * From the BDW PRMs (applies to later hardware too):
4583 * "Ternary instruction with condition modifiers must not use SIMD32."
4585 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4586 max_width
= MIN2(max_width
, 16);
4588 /* From the IVB PRMs (applies to other devices that don't have the
4589 * gen_device_info::supports_simd16_3src flag set):
4590 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4591 * SIMD8 is not allowed for DF operations."
4593 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4594 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4596 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
4597 * the 8-bit quarter of the execution mask signals specified in the
4598 * instruction control fields) for the second compressed half of any
4599 * single-precision instruction (for double-precision instructions
4600 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
4601 * the EU will apply the wrong execution controls for the second
4602 * sequential GRF write if the number of channels per GRF is not exactly
4603 * eight in single-precision mode (or four in double-float mode).
4605 * In this situation we calculate the maximum size of the split
4606 * instructions so they only ever write to a single register.
4608 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
4609 !inst
->force_writemask_all
) {
4610 const unsigned channels_per_grf
= inst
->exec_size
/
4611 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4612 unsigned exec_type_size
= 0;
4613 for (int i
= 0; i
< inst
->sources
; i
++) {
4614 if (inst
->src
[i
].file
!= BAD_FILE
)
4615 exec_type_size
= MAX2(exec_type_size
, type_sz(inst
->src
[i
].type
));
4617 assert(exec_type_size
);
4619 /* The hardware shifts exactly 8 channels per compressed half of the
4620 * instruction in single-precision mode and exactly 4 in double-precision.
4622 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
4623 max_width
= MIN2(max_width
, channels_per_grf
);
4626 /* Only power-of-two execution sizes are representable in the instruction
4629 return 1 << _mesa_logbase2(max_width
);
4633 * Get the maximum allowed SIMD width for instruction \p inst accounting for
4634 * various payload size restrictions that apply to sampler message
4637 * This is only intended to provide a maximum theoretical bound for the
4638 * execution size of the message based on the number of argument components
4639 * alone, which in most cases will determine whether the SIMD8 or SIMD16
4640 * variant of the message can be used, though some messages may have
4641 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
4642 * the message length to determine the exact SIMD width and argument count,
4643 * which makes a number of sampler message combinations impossible to
4647 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
4648 const fs_inst
*inst
)
4650 /* Calculate the number of coordinate components that have to be present
4651 * assuming that additional arguments follow the texel coordinates in the
4652 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
4653 * need to pad to four or three components depending on the message,
4654 * pre-ILK we need to pad to at most three components.
4656 const unsigned req_coord_components
=
4657 (devinfo
->gen
>= 7 ||
4658 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
4659 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
4660 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
4663 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
4664 * variant of the TXL or TXF message.
4666 const bool implicit_lod
= devinfo
->gen
>= 9 &&
4667 (inst
->opcode
== SHADER_OPCODE_TXL
||
4668 inst
->opcode
== SHADER_OPCODE_TXF
) &&
4669 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
4671 /* Calculate the total number of argument components that need to be passed
4672 * to the sampler unit.
4674 const unsigned num_payload_components
=
4675 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
4676 req_coord_components
) +
4677 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
4678 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
4679 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
4680 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
4681 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
4682 inst
->components_read(TEX_LOGICAL_SRC_OFFSET_VALUE
) : 0) +
4683 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
4685 /* SIMD16 messages with more than five arguments exceed the maximum message
4686 * size supported by the sampler, regardless of whether a header is
4689 return MIN2(inst
->exec_size
,
4690 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
4694 * Get the closest native SIMD width supported by the hardware for instruction
4695 * \p inst. The instruction will be left untouched by
4696 * fs_visitor::lower_simd_width() if the returned value is equal to the
4697 * original execution size.
4700 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
4701 const fs_inst
*inst
)
4703 switch (inst
->opcode
) {
4704 case BRW_OPCODE_MOV
:
4705 case BRW_OPCODE_SEL
:
4706 case BRW_OPCODE_NOT
:
4707 case BRW_OPCODE_AND
:
4709 case BRW_OPCODE_XOR
:
4710 case BRW_OPCODE_SHR
:
4711 case BRW_OPCODE_SHL
:
4712 case BRW_OPCODE_ASR
:
4713 case BRW_OPCODE_CMPN
:
4714 case BRW_OPCODE_CSEL
:
4715 case BRW_OPCODE_F32TO16
:
4716 case BRW_OPCODE_F16TO32
:
4717 case BRW_OPCODE_BFREV
:
4718 case BRW_OPCODE_BFE
:
4719 case BRW_OPCODE_ADD
:
4720 case BRW_OPCODE_MUL
:
4721 case BRW_OPCODE_AVG
:
4722 case BRW_OPCODE_FRC
:
4723 case BRW_OPCODE_RNDU
:
4724 case BRW_OPCODE_RNDD
:
4725 case BRW_OPCODE_RNDE
:
4726 case BRW_OPCODE_RNDZ
:
4727 case BRW_OPCODE_LZD
:
4728 case BRW_OPCODE_FBH
:
4729 case BRW_OPCODE_FBL
:
4730 case BRW_OPCODE_CBIT
:
4731 case BRW_OPCODE_SAD2
:
4732 case BRW_OPCODE_MAD
:
4733 case BRW_OPCODE_LRP
:
4734 case FS_OPCODE_PACK
:
4735 return get_fpu_lowered_simd_width(devinfo
, inst
);
4737 case BRW_OPCODE_CMP
: {
4738 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4739 * when the destination is a GRF the dependency-clear bit on the flag
4740 * register is cleared early.
4742 * Suggested workarounds are to disable coissuing CMP instructions
4743 * or to split CMP(16) instructions into two CMP(8) instructions.
4745 * We choose to split into CMP(8) instructions since disabling
4746 * coissuing would affect CMP instructions not otherwise affected by
4749 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4750 !inst
->dst
.is_null() ? 8 : ~0);
4751 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4753 case BRW_OPCODE_BFI1
:
4754 case BRW_OPCODE_BFI2
:
4755 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4757 * "Force BFI instructions to be executed always in SIMD8."
4759 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4760 get_fpu_lowered_simd_width(devinfo
, inst
));
4763 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4764 return inst
->exec_size
;
4766 case SHADER_OPCODE_RCP
:
4767 case SHADER_OPCODE_RSQ
:
4768 case SHADER_OPCODE_SQRT
:
4769 case SHADER_OPCODE_EXP2
:
4770 case SHADER_OPCODE_LOG2
:
4771 case SHADER_OPCODE_SIN
:
4772 case SHADER_OPCODE_COS
:
4773 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4776 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4777 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4778 MIN2(8, inst
->exec_size
));
4780 case SHADER_OPCODE_POW
:
4781 /* SIMD16 is only allowed on Gen7+. */
4782 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4783 MIN2(8, inst
->exec_size
));
4785 case SHADER_OPCODE_INT_QUOTIENT
:
4786 case SHADER_OPCODE_INT_REMAINDER
:
4787 /* Integer division is limited to SIMD8 on all generations. */
4788 return MIN2(8, inst
->exec_size
);
4790 case FS_OPCODE_LINTERP
:
4791 case FS_OPCODE_GET_BUFFER_SIZE
:
4792 case FS_OPCODE_DDX_COARSE
:
4793 case FS_OPCODE_DDX_FINE
:
4794 case FS_OPCODE_DDY_COARSE
:
4795 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4796 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4797 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4798 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4799 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4800 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4801 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4802 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4803 return MIN2(16, inst
->exec_size
);
4805 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4806 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4807 * message used to implement varying pull constant loads, so expand it
4808 * to SIMD16. An alternative with longer message payload length but
4809 * shorter return payload would be to use the SIMD8 sampler message that
4810 * takes (header, u, v, r) as parameters instead of (header, u).
4812 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4814 case FS_OPCODE_DDY_FINE
:
4815 /* The implementation of this virtual opcode may require emitting
4816 * compressed Align16 instructions, which are severely limited on some
4819 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4820 * Region Restrictions):
4822 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4823 * and SIMD8 is not allowed for DF operations."
4825 * In this context, "DW operations" means "operations acting on 32-bit
4826 * values", so it includes operations on floats.
4828 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4829 * (Instruction Compression -> Rules and Restrictions):
4831 * "A compressed instruction must be in Align1 access mode. Align16
4832 * mode instructions cannot be compressed."
4834 * Similar text exists in the g45 PRM.
4836 * Empirically, compressed align16 instructions using odd register
4837 * numbers don't appear to work on Sandybridge either.
4839 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4840 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4841 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
4843 case SHADER_OPCODE_MULH
:
4844 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4845 * is 8-wide on Gen7+.
4847 return (devinfo
->gen
>= 7 ? 8 :
4848 get_fpu_lowered_simd_width(devinfo
, inst
));
4850 case FS_OPCODE_FB_WRITE_LOGICAL
:
4851 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4854 assert(devinfo
->gen
!= 6 ||
4855 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4856 inst
->exec_size
== 8);
4857 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4858 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4859 8 : MIN2(16, inst
->exec_size
));
4861 case FS_OPCODE_FB_READ_LOGICAL
:
4862 return MIN2(16, inst
->exec_size
);
4864 case SHADER_OPCODE_TEX_LOGICAL
:
4865 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4866 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4867 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4868 case SHADER_OPCODE_LOD_LOGICAL
:
4869 case SHADER_OPCODE_TG4_LOGICAL
:
4870 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4871 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4872 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4873 return get_sampler_lowered_simd_width(devinfo
, inst
);
4875 case SHADER_OPCODE_TXD_LOGICAL
:
4876 /* TXD is unsupported in SIMD16 mode. */
4879 case SHADER_OPCODE_TXL_LOGICAL
:
4880 case FS_OPCODE_TXB_LOGICAL
:
4881 /* Only one execution size is representable pre-ILK depending on whether
4882 * the shadow reference argument is present.
4884 if (devinfo
->gen
== 4)
4885 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
4887 return get_sampler_lowered_simd_width(devinfo
, inst
);
4889 case SHADER_OPCODE_TXF_LOGICAL
:
4890 case SHADER_OPCODE_TXS_LOGICAL
:
4891 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4892 * messages. Use SIMD16 instead.
4894 if (devinfo
->gen
== 4)
4897 return get_sampler_lowered_simd_width(devinfo
, inst
);
4899 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4900 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4901 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4904 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4905 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4906 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4907 return MIN2(16, inst
->exec_size
);
4909 case SHADER_OPCODE_URB_READ_SIMD8
:
4910 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
4911 case SHADER_OPCODE_URB_WRITE_SIMD8
:
4912 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
4913 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
4914 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
4915 return MIN2(8, inst
->exec_size
);
4917 case SHADER_OPCODE_MOV_INDIRECT
:
4918 /* Prior to Broadwell, we only have 8 address subregisters */
4919 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
4920 2 * REG_SIZE
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
4923 case SHADER_OPCODE_LOAD_PAYLOAD
: {
4924 const unsigned reg_count
=
4925 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
4927 if (reg_count
> 2) {
4928 /* Only LOAD_PAYLOAD instructions with per-channel destination region
4929 * can be easily lowered (which excludes headers and heterogeneous
4932 assert(!inst
->header_size
);
4933 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4934 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
4935 inst
->src
[i
].file
== BAD_FILE
);
4937 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4939 return inst
->exec_size
;
4943 return inst
->exec_size
;
4948 * Return true if splitting out the group of channels of instruction \p inst
4949 * given by lbld.group() requires allocating a temporary for the i-th source
4950 * of the lowered instruction.
4953 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
4955 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
4956 (inst
->components_read(i
) == 1 &&
4957 lbld
.dispatch_width() <= inst
->exec_size
));
4961 * Extract the data that would be consumed by the channel group given by
4962 * lbld.group() from the i-th source region of instruction \p inst and return
4963 * it as result in packed form. If any copy instructions are required they
4964 * will be emitted before the given \p inst in \p block.
4967 emit_unzip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
,
4970 /* Specified channel group from the source region. */
4971 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
4973 if (needs_src_copy(lbld
, inst
, i
)) {
4974 /* Builder of the right width to perform the copy avoiding uninitialized
4975 * data if the lowered execution size is greater than the original
4976 * execution size of the instruction.
4978 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
4979 inst
->exec_size
), 0);
4980 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
4982 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
4983 cbld
.at(block
, inst
)
4984 .MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
4988 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
4989 /* The source is invariant for all dispatch_width-wide groups of the
4992 return inst
->src
[i
];
4995 /* We can just point the lowered instruction at the right channel group
4996 * from the original region.
5003 * Return true if splitting out the group of channels of instruction \p inst
5004 * given by lbld.group() requires allocating a temporary for the destination
5005 * of the lowered instruction and copying the data back to the original
5006 * destination region.
5009 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5011 /* If the instruction writes more than one component we'll have to shuffle
5012 * the results of multiple lowered instructions in order to make sure that
5013 * they end up arranged correctly in the original destination region.
5015 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
5018 /* If the lowered execution size is larger than the original the result of
5019 * the instruction won't fit in the original destination, so we'll have to
5020 * allocate a temporary in any case.
5022 if (lbld
.dispatch_width() > inst
->exec_size
)
5025 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5026 /* If we already made a copy of the source for other reasons there won't
5027 * be any overlap with the destination.
5029 if (needs_src_copy(lbld
, inst
, i
))
5032 /* In order to keep the logic simple we emit a copy whenever the
5033 * destination region doesn't exactly match an overlapping source, which
5034 * may point at the source and destination not being aligned group by
5035 * group which could cause one of the lowered instructions to overwrite
5036 * the data read from the same source by other lowered instructions.
5038 if (regions_overlap(inst
->dst
, inst
->size_written
,
5039 inst
->src
[i
], inst
->size_read(i
)) &&
5040 !inst
->dst
.equals(inst
->src
[i
]))
5048 * Insert data from a packed temporary into the channel group given by
5049 * lbld.group() of the destination region of instruction \p inst and return
5050 * the temporary as result. If any copy instructions are required they will
5051 * be emitted around the given \p inst in \p block.
5054 emit_zip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
)
5056 /* Builder of the right width to perform the copy avoiding uninitialized
5057 * data if the lowered execution size is greater than the original
5058 * execution size of the instruction.
5060 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5061 inst
->exec_size
), 0);
5063 /* Specified channel group from the destination region. */
5064 const fs_reg dst
= horiz_offset(inst
->dst
, lbld
.group());
5065 const unsigned dst_size
= inst
->size_written
/
5066 inst
->dst
.component_size(inst
->exec_size
);
5068 if (needs_dst_copy(lbld
, inst
)) {
5069 const fs_reg tmp
= lbld
.vgrf(inst
->dst
.type
, dst_size
);
5071 if (inst
->predicate
) {
5072 /* Handle predication by copying the original contents of
5073 * the destination into the temporary before emitting the
5074 * lowered instruction.
5076 for (unsigned k
= 0; k
< dst_size
; ++k
)
5077 cbld
.at(block
, inst
)
5078 .MOV(offset(tmp
, lbld
, k
), offset(dst
, inst
->exec_size
, k
));
5081 for (unsigned k
= 0; k
< dst_size
; ++k
)
5082 cbld
.at(block
, inst
->next
)
5083 .MOV(offset(dst
, inst
->exec_size
, k
), offset(tmp
, lbld
, k
));
5088 /* No need to allocate a temporary for the lowered instruction, just
5089 * take the right group of channels from the original region.
5096 fs_visitor::lower_simd_width()
5098 bool progress
= false;
5100 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5101 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5103 if (lower_width
!= inst
->exec_size
) {
5104 /* Builder matching the original instruction. We may also need to
5105 * emit an instruction of width larger than the original, set the
5106 * execution size of the builder to the highest of both for now so
5107 * we're sure that both cases can be handled.
5109 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5110 const fs_builder ibld
= bld
.at(block
, inst
)
5111 .exec_all(inst
->force_writemask_all
)
5112 .group(max_width
, inst
->group
/ max_width
);
5114 /* Split the copies in chunks of the execution width of either the
5115 * original or the lowered instruction, whichever is lower.
5117 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5118 const unsigned dst_size
= inst
->size_written
/
5119 inst
->dst
.component_size(inst
->exec_size
);
5121 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5123 for (unsigned i
= 0; i
< n
; i
++) {
5124 /* Emit a copy of the original instruction with the lowered width.
5125 * If the EOT flag was set throw it away except for the last
5126 * instruction to avoid killing the thread prematurely.
5128 fs_inst split_inst
= *inst
;
5129 split_inst
.exec_size
= lower_width
;
5130 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
5132 /* Select the correct channel enables for the i-th group, then
5133 * transform the sources and destination and emit the lowered
5136 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5138 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5139 split_inst
.src
[j
] = emit_unzip(lbld
, block
, inst
, j
);
5141 split_inst
.dst
= emit_zip(lbld
, block
, inst
);
5142 split_inst
.size_written
=
5143 split_inst
.dst
.component_size(lower_width
) * dst_size
;
5145 lbld
.emit(split_inst
);
5148 inst
->remove(block
);
5154 invalidate_live_intervals();
5160 fs_visitor::dump_instructions()
5162 dump_instructions(NULL
);
5166 fs_visitor::dump_instructions(const char *name
)
5168 FILE *file
= stderr
;
5169 if (name
&& geteuid() != 0) {
5170 file
= fopen(name
, "w");
5176 calculate_register_pressure();
5177 int ip
= 0, max_pressure
= 0;
5178 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5179 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5180 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5181 dump_instruction(inst
, file
);
5184 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5187 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5188 fprintf(file
, "%4d: ", ip
++);
5189 dump_instruction(inst
, file
);
5193 if (file
!= stderr
) {
5199 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5201 dump_instruction(be_inst
, stderr
);
5205 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5207 fs_inst
*inst
= (fs_inst
*)be_inst
;
5209 if (inst
->predicate
) {
5210 fprintf(file
, "(%cf0.%d) ",
5211 inst
->predicate_inverse
? '-' : '+',
5215 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5217 fprintf(file
, ".sat");
5218 if (inst
->conditional_mod
) {
5219 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5220 if (!inst
->predicate
&&
5221 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5222 inst
->opcode
!= BRW_OPCODE_IF
&&
5223 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5224 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5227 fprintf(file
, "(%d) ", inst
->exec_size
);
5230 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5234 fprintf(file
, "(EOT) ");
5237 switch (inst
->dst
.file
) {
5239 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5242 fprintf(file
, "g%d", inst
->dst
.nr
);
5245 fprintf(file
, "m%d", inst
->dst
.nr
);
5248 fprintf(file
, "(null)");
5251 fprintf(file
, "***u%d***", inst
->dst
.nr
);
5254 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
5257 switch (inst
->dst
.nr
) {
5259 fprintf(file
, "null");
5261 case BRW_ARF_ADDRESS
:
5262 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5264 case BRW_ARF_ACCUMULATOR
:
5265 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5268 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5271 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5276 unreachable("not reached");
5279 if (inst
->dst
.offset
||
5280 (inst
->dst
.file
== VGRF
&&
5281 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
5282 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
5283 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
5284 inst
->dst
.offset
% reg_size
);
5287 if (inst
->dst
.stride
!= 1)
5288 fprintf(file
, "<%u>", inst
->dst
.stride
);
5289 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
5291 for (int i
= 0; i
< inst
->sources
; i
++) {
5292 if (inst
->src
[i
].negate
)
5294 if (inst
->src
[i
].abs
)
5296 switch (inst
->src
[i
].file
) {
5298 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5301 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5304 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5307 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
5310 fprintf(file
, "u%d", inst
->src
[i
].nr
);
5313 fprintf(file
, "(null)");
5316 switch (inst
->src
[i
].type
) {
5317 case BRW_REGISTER_TYPE_F
:
5318 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5320 case BRW_REGISTER_TYPE_DF
:
5321 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5323 case BRW_REGISTER_TYPE_W
:
5324 case BRW_REGISTER_TYPE_D
:
5325 fprintf(file
, "%dd", inst
->src
[i
].d
);
5327 case BRW_REGISTER_TYPE_UW
:
5328 case BRW_REGISTER_TYPE_UD
:
5329 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5331 case BRW_REGISTER_TYPE_VF
:
5332 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5333 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5334 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5335 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5336 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5339 fprintf(file
, "???");
5344 switch (inst
->src
[i
].nr
) {
5346 fprintf(file
, "null");
5348 case BRW_ARF_ADDRESS
:
5349 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5351 case BRW_ARF_ACCUMULATOR
:
5352 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5355 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5358 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5364 if (inst
->src
[i
].offset
||
5365 (inst
->src
[i
].file
== VGRF
&&
5366 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
5367 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
5368 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
5369 inst
->src
[i
].offset
% reg_size
);
5372 if (inst
->src
[i
].abs
)
5375 if (inst
->src
[i
].file
!= IMM
) {
5377 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5378 unsigned hstride
= inst
->src
[i
].hstride
;
5379 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5381 stride
= inst
->src
[i
].stride
;
5384 fprintf(file
, "<%u>", stride
);
5386 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
5389 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5390 fprintf(file
, ", ");
5395 if (inst
->force_writemask_all
)
5396 fprintf(file
, "NoMask ");
5398 if (inst
->exec_size
!= dispatch_width
)
5399 fprintf(file
, "group%d ", inst
->group
);
5401 fprintf(file
, "\n");
5405 * Possibly returns an instruction that set up @param reg.
5407 * Sometimes we want to take the result of some expression/variable
5408 * dereference tree and rewrite the instruction generating the result
5409 * of the tree. When processing the tree, we know that the
5410 * instructions generated are all writing temporaries that are dead
5411 * outside of this tree. So, if we have some instructions that write
5412 * a temporary, we're free to point that temp write somewhere else.
5414 * Note that this doesn't guarantee that the instruction generated
5415 * only reg -- it might be the size=4 destination of a texture instruction.
5418 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5423 end
->is_partial_write() ||
5424 !reg
.equals(end
->dst
)) {
5432 fs_visitor::setup_fs_payload_gen6()
5434 assert(stage
== MESA_SHADER_FRAGMENT
);
5435 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5437 unsigned barycentric_interp_modes
=
5438 (stage
== MESA_SHADER_FRAGMENT
) ?
5439 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
5441 assert(devinfo
->gen
>= 6);
5443 /* R0-1: masks, pixel X/Y coordinates. */
5444 payload
.num_regs
= 2;
5445 /* R2: only for 32-pixel dispatch.*/
5447 /* R3-26: barycentric interpolation coordinates. These appear in the
5448 * same order that they appear in the brw_barycentric_mode
5449 * enum. Each set of coordinates occupies 2 registers if dispatch width
5450 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5451 * appear if they were enabled using the "Barycentric Interpolation
5452 * Mode" bits in WM_STATE.
5454 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5455 if (barycentric_interp_modes
& (1 << i
)) {
5456 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5457 payload
.num_regs
+= 2;
5458 if (dispatch_width
== 16) {
5459 payload
.num_regs
+= 2;
5464 /* R27: interpolated depth if uses source depth */
5465 prog_data
->uses_src_depth
=
5466 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5467 if (prog_data
->uses_src_depth
) {
5468 payload
.source_depth_reg
= payload
.num_regs
;
5470 if (dispatch_width
== 16) {
5471 /* R28: interpolated depth if not SIMD8. */
5476 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5477 prog_data
->uses_src_w
=
5478 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5479 if (prog_data
->uses_src_w
) {
5480 payload
.source_w_reg
= payload
.num_regs
;
5482 if (dispatch_width
== 16) {
5483 /* R30: interpolated W if not SIMD8. */
5488 /* R31: MSAA position offsets. */
5489 if (prog_data
->persample_dispatch
&&
5490 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5491 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5493 * "MSDISPMODE_PERSAMPLE is required in order to select
5496 * So we can only really get sample positions if we are doing real
5497 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5498 * persample dispatch, we hard-code it to 0.5.
5500 prog_data
->uses_pos_offset
= true;
5501 payload
.sample_pos_reg
= payload
.num_regs
;
5505 /* R32: MSAA input coverage mask */
5506 prog_data
->uses_sample_mask
=
5507 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5508 if (prog_data
->uses_sample_mask
) {
5509 assert(devinfo
->gen
>= 7);
5510 payload
.sample_mask_in_reg
= payload
.num_regs
;
5512 if (dispatch_width
== 16) {
5513 /* R33: input coverage mask if not SIMD8. */
5518 /* R34-: bary for 32-pixel. */
5519 /* R58-59: interp W for 32-pixel. */
5521 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5522 source_depth_to_render_target
= true;
5527 fs_visitor::setup_vs_payload()
5529 /* R0: thread header, R1: urb handles */
5530 payload
.num_regs
= 2;
5534 fs_visitor::setup_gs_payload()
5536 assert(stage
== MESA_SHADER_GEOMETRY
);
5538 struct brw_gs_prog_data
*gs_prog_data
=
5539 (struct brw_gs_prog_data
*) prog_data
;
5540 struct brw_vue_prog_data
*vue_prog_data
=
5541 (struct brw_vue_prog_data
*) prog_data
;
5543 /* R0: thread header, R1: output URB handles */
5544 payload
.num_regs
= 2;
5546 if (gs_prog_data
->include_primitive_id
) {
5547 /* R2: Primitive ID 0..7 */
5551 /* Use a maximum of 24 registers for push-model inputs. */
5552 const unsigned max_push_components
= 24;
5554 /* If pushing our inputs would take too many registers, reduce the URB read
5555 * length (which is in HWords, or 8 registers), and resort to pulling.
5557 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5558 * have to multiply by VerticesIn to obtain the total storage requirement.
5560 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5561 max_push_components
|| gs_prog_data
->invocations
> 1) {
5562 gs_prog_data
->base
.include_vue_handles
= true;
5564 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5565 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5567 vue_prog_data
->urb_read_length
=
5568 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5573 fs_visitor::setup_cs_payload()
5575 assert(devinfo
->gen
>= 7);
5576 payload
.num_regs
= 1;
5580 fs_visitor::calculate_register_pressure()
5582 invalidate_live_intervals();
5583 calculate_live_intervals();
5585 unsigned num_instructions
= 0;
5586 foreach_block(block
, cfg
)
5587 num_instructions
+= block
->instructions
.length();
5589 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5591 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5592 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5593 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5598 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5600 * The needs_unlit_centroid_workaround ends up producing one of these per
5601 * channel of centroid input, so it's good to clean them up.
5603 * An assumption here is that nothing ever modifies the dispatched pixels
5604 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5605 * dictates that anyway.
5608 fs_visitor::opt_drop_redundant_mov_to_flags()
5610 bool flag_mov_found
[2] = {false};
5611 bool progress
= false;
5613 /* Instructions removed by this pass can only be added if this were true */
5614 if (!devinfo
->needs_unlit_centroid_workaround
)
5617 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5618 if (inst
->is_control_flow()) {
5619 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5620 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5621 if (!flag_mov_found
[inst
->flag_subreg
]) {
5622 flag_mov_found
[inst
->flag_subreg
] = true;
5624 inst
->remove(block
);
5627 } else if (inst
->flags_written()) {
5628 flag_mov_found
[inst
->flag_subreg
] = false;
5636 fs_visitor::optimize()
5638 /* Start by validating the shader we currently have. */
5641 /* bld is the common builder object pointing at the end of the program we
5642 * used to translate it into i965 IR. For the optimization and lowering
5643 * passes coming next, any code added after the end of the program without
5644 * having explicitly called fs_builder::at() clearly points at a mistake.
5645 * Ideally optimization passes wouldn't be part of the visitor so they
5646 * wouldn't have access to bld at all, but they do, so just in case some
5647 * pass forgets to ask for a location explicitly set it to NULL here to
5648 * make it trip. The dispatch width is initialized to a bogus value to
5649 * make sure that optimizations set the execution controls explicitly to
5650 * match the code they are manipulating instead of relying on the defaults.
5652 bld
= fs_builder(this, 64);
5654 assign_constant_locations();
5655 lower_constant_loads();
5659 split_virtual_grfs();
5662 #define OPT(pass, args...) ({ \
5664 bool this_progress = pass(args); \
5666 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5667 char filename[64]; \
5668 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5669 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5671 backend_shader::dump_instructions(filename); \
5676 progress = progress || this_progress; \
5680 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5682 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5683 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5685 backend_shader::dump_instructions(filename
);
5688 bool progress
= false;
5692 OPT(opt_drop_redundant_mov_to_flags
);
5699 OPT(remove_duplicate_mrf_writes
);
5703 OPT(opt_copy_propagate
);
5704 OPT(opt_predicated_break
, this);
5705 OPT(opt_cmod_propagation
);
5706 OPT(dead_code_eliminate
);
5707 OPT(opt_peephole_sel
);
5708 OPT(dead_control_flow_eliminate
, this);
5709 OPT(opt_register_renaming
);
5710 OPT(opt_saturate_propagation
);
5711 OPT(register_coalesce
);
5712 OPT(compute_to_mrf
);
5713 OPT(eliminate_find_live_channel
);
5715 OPT(compact_virtual_grfs
);
5721 if (OPT(lower_pack
)) {
5722 OPT(register_coalesce
);
5723 OPT(dead_code_eliminate
);
5726 if (OPT(lower_d2x
)) {
5727 OPT(opt_copy_propagate
);
5728 OPT(dead_code_eliminate
);
5731 OPT(lower_simd_width
);
5733 /* After SIMD lowering just in case we had to unroll the EOT send. */
5734 OPT(opt_sampler_eot
);
5736 OPT(lower_logical_sends
);
5739 OPT(opt_copy_propagate
);
5740 /* Only run after logical send lowering because it's easier to implement
5741 * in terms of physical sends.
5743 if (OPT(opt_zero_samples
))
5744 OPT(opt_copy_propagate
);
5745 /* Run after logical send lowering to give it a chance to CSE the
5746 * LOAD_PAYLOAD instructions created to construct the payloads of
5747 * e.g. texturing messages in cases where it wasn't possible to CSE the
5748 * whole logical instruction.
5751 OPT(register_coalesce
);
5752 OPT(compute_to_mrf
);
5753 OPT(dead_code_eliminate
);
5754 OPT(remove_duplicate_mrf_writes
);
5755 OPT(opt_peephole_sel
);
5758 OPT(opt_redundant_discard_jumps
);
5760 if (OPT(lower_load_payload
)) {
5761 split_virtual_grfs();
5762 OPT(register_coalesce
);
5763 OPT(compute_to_mrf
);
5764 OPT(dead_code_eliminate
);
5767 OPT(opt_combine_constants
);
5768 OPT(lower_integer_multiplication
);
5770 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5771 OPT(opt_cmod_propagation
);
5773 OPT(opt_copy_propagate
);
5774 OPT(dead_code_eliminate
);
5777 lower_uniform_pull_constant_loads();
5783 * Three source instruction must have a GRF/MRF destination register.
5784 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5787 fs_visitor::fixup_3src_null_dest()
5789 bool progress
= false;
5791 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5792 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5793 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5800 invalidate_live_intervals();
5804 fs_visitor::allocate_registers(bool allow_spilling
)
5806 bool allocated_without_spills
;
5808 static const enum instruction_scheduler_mode pre_modes
[] = {
5810 SCHEDULE_PRE_NON_LIFO
,
5814 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
5816 /* Try each scheduling heuristic to see if it can successfully register
5817 * allocate without spilling. They should be ordered by decreasing
5818 * performance but increasing likelihood of allocating.
5820 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5821 schedule_instructions(pre_modes
[i
]);
5824 assign_regs_trivial();
5825 allocated_without_spills
= true;
5827 allocated_without_spills
= assign_regs(false, spill_all
);
5829 if (allocated_without_spills
)
5833 if (!allocated_without_spills
) {
5834 if (!allow_spilling
)
5835 fail("Failure to register allocate and spilling is not allowed.");
5837 /* We assume that any spilling is worse than just dropping back to
5838 * SIMD8. There's probably actually some intermediate point where
5839 * SIMD16 with a couple of spills is still better.
5841 if (dispatch_width
> min_dispatch_width
) {
5842 fail("Failure to register allocate. Reduce number of "
5843 "live scalar values to avoid this.");
5845 compiler
->shader_perf_log(log_data
,
5846 "%s shader triggered register spilling. "
5847 "Try reducing the number of live scalar "
5848 "values to improve performance.\n",
5852 /* Since we're out of heuristics, just go spill registers until we
5853 * get an allocation.
5855 while (!assign_regs(true, spill_all
)) {
5861 /* This must come after all optimization and register allocation, since
5862 * it inserts dead code that happens to have side effects, and it does
5863 * so based on the actual physical registers in use.
5865 insert_gen4_send_dependency_workarounds();
5870 schedule_instructions(SCHEDULE_POST
);
5872 if (last_scratch
> 0) {
5873 unsigned max_scratch_size
= 2 * 1024 * 1024;
5875 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5877 if (stage
== MESA_SHADER_COMPUTE
) {
5878 if (devinfo
->is_haswell
) {
5879 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5880 * field documentation, Haswell supports a minimum of 2kB of
5881 * scratch space for compute shaders, unlike every other stage
5884 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
5885 } else if (devinfo
->gen
<= 7) {
5886 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5887 * field documentation, platforms prior to Haswell measure scratch
5888 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
5890 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
5891 max_scratch_size
= 12 * 1024;
5895 /* We currently only support up to 2MB of scratch space. If we
5896 * need to support more eventually, the documentation suggests
5897 * that we could allocate a larger buffer, and partition it out
5898 * ourselves. We'd just have to undo the hardware's address
5899 * calculation by subtracting (FFTID * Per Thread Scratch Space)
5900 * and then add FFTID * (Larger Per Thread Scratch Space).
5902 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
5903 * Thread Group Tracking > Local Memory/Scratch Space.
5905 assert(prog_data
->total_scratch
< max_scratch_size
);
5910 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5912 assert(stage
== MESA_SHADER_VERTEX
);
5916 if (shader_time_index
>= 0)
5917 emit_shader_time_begin();
5924 compute_clip_distance(clip_planes
);
5928 if (shader_time_index
>= 0)
5929 emit_shader_time_end();
5935 assign_curb_setup();
5936 assign_vs_urb_setup();
5938 fixup_3src_null_dest();
5939 allocate_registers(true);
5945 fs_visitor::run_tcs_single_patch()
5947 assert(stage
== MESA_SHADER_TESS_CTRL
);
5949 struct brw_tcs_prog_data
*tcs_prog_data
=
5950 (struct brw_tcs_prog_data
*) prog_data
;
5952 /* r1-r4 contain the ICP handles. */
5953 payload
.num_regs
= 5;
5955 if (shader_time_index
>= 0)
5956 emit_shader_time_begin();
5958 /* Initialize gl_InvocationID */
5959 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
5960 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5961 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
5962 bld
.MOV(channels_ud
, channels_uw
);
5964 if (tcs_prog_data
->instances
== 1) {
5965 invocation_id
= channels_ud
;
5967 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5969 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
5970 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5971 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5972 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
5973 brw_imm_ud(INTEL_MASK(23, 17)));
5974 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
5976 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
5979 /* Fix the disptach mask */
5980 if (nir
->info
.tcs
.vertices_out
% 8) {
5981 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
5982 brw_imm_ud(nir
->info
.tcs
.vertices_out
), BRW_CONDITIONAL_L
);
5983 bld
.IF(BRW_PREDICATE_NORMAL
);
5988 if (nir
->info
.tcs
.vertices_out
% 8) {
5989 bld
.emit(BRW_OPCODE_ENDIF
);
5992 /* Emit EOT write; set TR DS Cache bit */
5994 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
5995 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
5996 fs_reg(brw_imm_ud(0)),
5998 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
5999 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6001 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6002 bld
.null_reg_ud(), payload
);
6006 if (shader_time_index
>= 0)
6007 emit_shader_time_end();
6016 assign_curb_setup();
6017 assign_tcs_single_patch_urb_setup();
6019 fixup_3src_null_dest();
6020 allocate_registers(true);
6026 fs_visitor::run_tes()
6028 assert(stage
== MESA_SHADER_TESS_EVAL
);
6030 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6031 payload
.num_regs
= 5;
6033 if (shader_time_index
>= 0)
6034 emit_shader_time_begin();
6043 if (shader_time_index
>= 0)
6044 emit_shader_time_end();
6050 assign_curb_setup();
6051 assign_tes_urb_setup();
6053 fixup_3src_null_dest();
6054 allocate_registers(true);
6060 fs_visitor::run_gs()
6062 assert(stage
== MESA_SHADER_GEOMETRY
);
6066 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6068 if (gs_compile
->control_data_header_size_bits
> 0) {
6069 /* Create a VGRF to store accumulated control data bits. */
6070 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6072 /* If we're outputting more than 32 control data bits, then EmitVertex()
6073 * will set control_data_bits to 0 after emitting the first vertex.
6074 * Otherwise, we need to initialize it to 0 here.
6076 if (gs_compile
->control_data_header_size_bits
<= 32) {
6077 const fs_builder abld
= bld
.annotate("initialize control data bits");
6078 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6082 if (shader_time_index
>= 0)
6083 emit_shader_time_begin();
6087 emit_gs_thread_end();
6089 if (shader_time_index
>= 0)
6090 emit_shader_time_end();
6099 assign_curb_setup();
6100 assign_gs_urb_setup();
6102 fixup_3src_null_dest();
6103 allocate_registers(true);
6109 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6111 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
6112 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6114 assert(stage
== MESA_SHADER_FRAGMENT
);
6116 if (devinfo
->gen
>= 6)
6117 setup_fs_payload_gen6();
6119 setup_fs_payload_gen4();
6123 } else if (do_rep_send
) {
6124 assert(dispatch_width
== 16);
6125 emit_repclear_shader();
6127 if (shader_time_index
>= 0)
6128 emit_shader_time_begin();
6130 calculate_urb_setup();
6131 if (nir
->info
.inputs_read
> 0 ||
6132 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
6133 if (devinfo
->gen
< 6)
6134 emit_interpolation_setup_gen4();
6136 emit_interpolation_setup_gen6();
6139 /* We handle discards by keeping track of the still-live pixels in f0.1.
6140 * Initialize it with the dispatched pixels.
6142 if (wm_prog_data
->uses_kill
) {
6143 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6144 discard_init
->flag_subreg
= 1;
6147 /* Generate FS IR for main(). (the visitor only descends into
6148 * functions called "main").
6155 if (wm_prog_data
->uses_kill
)
6156 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6158 if (wm_key
->alpha_test_func
)
6163 if (shader_time_index
>= 0)
6164 emit_shader_time_end();
6170 assign_curb_setup();
6173 fixup_3src_null_dest();
6174 allocate_registers(allow_spilling
);
6184 fs_visitor::run_cs()
6186 assert(stage
== MESA_SHADER_COMPUTE
);
6190 if (shader_time_index
>= 0)
6191 emit_shader_time_begin();
6193 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6194 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6195 const fs_builder abld
= bld
.exec_all().group(1, 0);
6196 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
6197 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6205 emit_cs_terminate();
6207 if (shader_time_index
>= 0)
6208 emit_shader_time_end();
6214 assign_curb_setup();
6216 fixup_3src_null_dest();
6217 allocate_registers(true);
6226 * Return a bitfield where bit n is set if barycentric interpolation mode n
6227 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6229 * We examine the load_barycentric intrinsics rather than looking at input
6230 * variables so that we catch interpolateAtCentroid() messages too, which
6231 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6234 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
6235 const nir_shader
*shader
)
6237 unsigned barycentric_interp_modes
= 0;
6239 nir_foreach_function(f
, shader
) {
6243 nir_foreach_block(block
, f
->impl
) {
6244 nir_foreach_instr(instr
, block
) {
6245 if (instr
->type
!= nir_instr_type_intrinsic
)
6248 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6249 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6252 /* Ignore WPOS; it doesn't require interpolation. */
6253 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6256 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6257 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
6258 nir_intrinsic_interp_mode(intrin
);
6259 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
6260 enum brw_barycentric_mode bary
=
6261 brw_barycentric_mode(interp
, bary_op
);
6263 barycentric_interp_modes
|= 1 << bary
;
6265 if (devinfo
->needs_unlit_centroid_workaround
&&
6266 bary_op
== nir_intrinsic_load_barycentric_centroid
)
6267 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
6272 return barycentric_interp_modes
;
6276 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6277 const nir_shader
*shader
)
6279 prog_data
->flat_inputs
= 0;
6281 nir_foreach_variable(var
, &shader
->inputs
) {
6282 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6284 if (input_index
< 0)
6288 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6289 prog_data
->flat_inputs
|= (1 << input_index
);
6294 computed_depth_mode(const nir_shader
*shader
)
6296 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6297 switch (shader
->info
.fs
.depth_layout
) {
6298 case FRAG_DEPTH_LAYOUT_NONE
:
6299 case FRAG_DEPTH_LAYOUT_ANY
:
6300 return BRW_PSCDEPTH_ON
;
6301 case FRAG_DEPTH_LAYOUT_GREATER
:
6302 return BRW_PSCDEPTH_ON_GE
;
6303 case FRAG_DEPTH_LAYOUT_LESS
:
6304 return BRW_PSCDEPTH_ON_LE
;
6305 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6306 return BRW_PSCDEPTH_OFF
;
6309 return BRW_PSCDEPTH_OFF
;
6313 * Move load_interpolated_input with simple (payload-based) barycentric modes
6314 * to the top of the program so we don't emit multiple PLNs for the same input.
6316 * This works around CSE not being able to handle non-dominating cases
6322 * interpolate the same exact input
6325 * This should be replaced by global value numbering someday.
6328 move_interpolation_to_top(nir_shader
*nir
)
6330 nir_foreach_function(f
, nir
) {
6334 nir_block
*top
= nir_start_block(f
->impl
);
6335 exec_node
*cursor_node
= NULL
;
6337 nir_foreach_block(block
, f
->impl
) {
6341 nir_foreach_instr_safe(instr
, block
) {
6342 if (instr
->type
!= nir_instr_type_intrinsic
)
6345 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6346 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6348 nir_intrinsic_instr
*bary_intrinsic
=
6349 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6350 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
6352 /* Leave interpolateAtSample/Offset() where they are. */
6353 if (op
== nir_intrinsic_load_barycentric_at_sample
||
6354 op
== nir_intrinsic_load_barycentric_at_offset
)
6357 nir_instr
*move
[3] = {
6358 &bary_intrinsic
->instr
,
6359 intrin
->src
[1].ssa
->parent_instr
,
6363 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
6364 if (move
[i
]->block
!= top
) {
6365 move
[i
]->block
= top
;
6366 exec_node_remove(&move
[i
]->node
);
6368 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
6370 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
6372 cursor_node
= &move
[i
]->node
;
6377 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6378 ((unsigned) nir_metadata_block_index
|
6379 (unsigned) nir_metadata_dominance
));
6384 * Demote per-sample barycentric intrinsics to centroid.
6386 * Useful when rendering to a non-multisampled buffer.
6389 demote_sample_qualifiers(nir_shader
*nir
)
6391 nir_foreach_function(f
, nir
) {
6396 nir_builder_init(&b
, f
->impl
);
6398 nir_foreach_block(block
, f
->impl
) {
6399 nir_foreach_instr_safe(instr
, block
) {
6400 if (instr
->type
!= nir_instr_type_intrinsic
)
6403 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6404 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
6405 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
6408 b
.cursor
= nir_before_instr(instr
);
6409 nir_ssa_def
*centroid
=
6410 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
6411 nir_intrinsic_interp_mode(intrin
));
6412 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
6413 nir_src_for_ssa(centroid
));
6414 nir_instr_remove(instr
);
6418 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6419 ((unsigned) nir_metadata_block_index
|
6420 (unsigned) nir_metadata_dominance
));
6425 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6427 const struct brw_wm_prog_key
*key
,
6428 struct brw_wm_prog_data
*prog_data
,
6429 const nir_shader
*src_shader
,
6430 struct gl_program
*prog
,
6431 int shader_time_index8
, int shader_time_index16
,
6432 bool allow_spilling
,
6434 unsigned *final_assembly_size
,
6437 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6438 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6440 brw_nir_lower_fs_inputs(shader
, compiler
->devinfo
, key
);
6441 brw_nir_lower_fs_outputs(shader
);
6442 if (!key
->multisample_fbo
)
6443 NIR_PASS_V(shader
, demote_sample_qualifiers
);
6444 NIR_PASS_V(shader
, move_interpolation_to_top
);
6445 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6447 /* key->alpha_test_func means simulating alpha testing via discards,
6448 * so the shader definitely kills pixels.
6450 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
6451 prog_data
->uses_omask
= key
->multisample_fbo
&&
6452 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6453 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6454 prog_data
->computed_stencil
=
6455 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6457 prog_data
->persample_dispatch
=
6458 key
->multisample_fbo
&&
6459 (key
->persample_interp
||
6460 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6461 SYSTEM_BIT_SAMPLE_POS
)) ||
6462 shader
->info
.fs
.uses_sample_qualifier
||
6463 shader
->info
.outputs_read
);
6465 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
6467 prog_data
->barycentric_interp_modes
=
6468 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
6470 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6471 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6472 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6474 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6475 &prog_data
->base
, prog
, shader
, 8,
6476 shader_time_index8
);
6477 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6479 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6482 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6484 simd8_grf_start
= v8
.payload
.num_regs
;
6485 simd8_grf_used
= v8
.grf_used
;
6488 if (v8
.max_dispatch_width
>= 16 &&
6489 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6490 /* Try a SIMD16 compile */
6491 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6492 &prog_data
->base
, prog
, shader
, 16,
6493 shader_time_index16
);
6494 v16
.import_uniforms(&v8
);
6495 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6496 compiler
->shader_perf_log(log_data
,
6497 "SIMD16 shader failed to compile: %s",
6500 simd16_cfg
= v16
.cfg
;
6501 simd16_grf_start
= v16
.payload
.num_regs
;
6502 simd16_grf_used
= v16
.grf_used
;
6506 /* When the caller requests a repclear shader, they want SIMD16-only */
6510 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6511 * at the top to select the shader. We've never implemented that.
6512 * Instead, we just give them exactly one shader and we pick the widest one
6515 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6518 if (prog_data
->persample_dispatch
) {
6519 /* Starting with SandyBridge (where we first get MSAA), the different
6520 * pixel dispatch combinations are grouped into classifications A
6521 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6522 * generations, the only configurations supporting persample dispatch
6523 * are are this in which only one dispatch width is enabled.
6525 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6526 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6528 if (compiler
->devinfo
->gen
== 6 &&
6529 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6531 } else if (simd16_cfg
) {
6536 /* We have to compute the flat inputs after the visitor is finished running
6537 * because it relies on prog_data->urb_setup which is computed in
6538 * fs_visitor::calculate_urb_setup().
6540 brw_compute_flat_inputs(prog_data
, shader
);
6542 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6543 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6544 MESA_SHADER_FRAGMENT
);
6546 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6547 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6548 shader
->info
.label
? shader
->info
.label
:
6550 shader
->info
.name
));
6554 prog_data
->dispatch_8
= true;
6555 g
.generate_code(simd8_cfg
, 8);
6556 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6557 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6560 prog_data
->dispatch_16
= true;
6561 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6562 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6563 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6565 } else if (simd16_cfg
) {
6566 prog_data
->dispatch_16
= true;
6567 g
.generate_code(simd16_cfg
, 16);
6568 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6569 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6572 return g
.get_assembly(final_assembly_size
);
6576 fs_visitor::emit_cs_work_group_id_setup()
6578 assert(stage
== MESA_SHADER_COMPUTE
);
6580 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6582 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6583 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6584 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6586 bld
.MOV(*reg
, r0_1
);
6587 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6588 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6594 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
6596 block
->dwords
= dwords
;
6597 block
->regs
= DIV_ROUND_UP(dwords
, 8);
6598 block
->size
= block
->regs
* 32;
6602 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
6603 struct brw_cs_prog_data
*cs_prog_data
)
6605 const struct brw_stage_prog_data
*prog_data
=
6606 (struct brw_stage_prog_data
*) cs_prog_data
;
6607 bool fill_thread_id
=
6608 cs_prog_data
->thread_local_id_index
>= 0 &&
6609 cs_prog_data
->thread_local_id_index
< (int)prog_data
->nr_params
;
6610 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
6612 /* The thread ID should be stored in the last param dword */
6613 assert(prog_data
->nr_params
> 0 || !fill_thread_id
);
6614 assert(!fill_thread_id
||
6615 cs_prog_data
->thread_local_id_index
==
6616 (int)prog_data
->nr_params
- 1);
6618 unsigned cross_thread_dwords
, per_thread_dwords
;
6619 if (!cross_thread_supported
) {
6620 cross_thread_dwords
= 0u;
6621 per_thread_dwords
= prog_data
->nr_params
;
6622 } else if (fill_thread_id
) {
6623 /* Fill all but the last register with cross-thread payload */
6624 cross_thread_dwords
= 8 * (cs_prog_data
->thread_local_id_index
/ 8);
6625 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
6626 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
6628 /* Fill all data using cross-thread payload */
6629 cross_thread_dwords
= prog_data
->nr_params
;
6630 per_thread_dwords
= 0u;
6633 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
6634 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
6636 unsigned total_dwords
=
6637 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
6638 cs_prog_data
->push
.cross_thread
.size
) / 4;
6639 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
6641 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
6642 cs_prog_data
->push
.per_thread
.size
== 0);
6643 assert(cs_prog_data
->push
.cross_thread
.dwords
+
6644 cs_prog_data
->push
.per_thread
.dwords
==
6645 prog_data
->nr_params
);
6649 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
6651 cs_prog_data
->simd_size
= size
;
6652 unsigned group_size
= cs_prog_data
->local_size
[0] *
6653 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
6654 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
6658 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6660 const struct brw_cs_prog_key
*key
,
6661 struct brw_cs_prog_data
*prog_data
,
6662 const nir_shader
*src_shader
,
6663 int shader_time_index
,
6664 unsigned *final_assembly_size
,
6667 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6668 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6670 brw_nir_lower_cs_shared(shader
);
6671 prog_data
->base
.total_shared
+= shader
->num_shared
;
6673 /* Now that we cloned the nir_shader, we can update num_uniforms based on
6674 * the thread_local_id_index.
6676 assert(prog_data
->thread_local_id_index
>= 0);
6677 shader
->num_uniforms
=
6678 MAX2(shader
->num_uniforms
,
6679 (unsigned)4 * (prog_data
->thread_local_id_index
+ 1));
6681 brw_nir_lower_intrinsics(shader
, &prog_data
->base
);
6682 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6684 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
6685 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
6686 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
6687 unsigned local_workgroup_size
=
6688 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
6689 shader
->info
.cs
.local_size
[2];
6691 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
6692 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
6695 const char *fail_msg
= NULL
;
6697 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6699 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6700 NULL
, /* Never used in core profile */
6701 shader
, 8, shader_time_index
);
6702 if (simd_required
<= 8) {
6704 fail_msg
= v8
.fail_msg
;
6707 cs_set_simd_size(prog_data
, 8);
6708 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6709 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
6713 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6714 NULL
, /* Never used in core profile */
6715 shader
, 16, shader_time_index
);
6716 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6717 !fail_msg
&& v8
.max_dispatch_width
>= 16 &&
6718 simd_required
<= 16) {
6719 /* Try a SIMD16 compile */
6720 if (simd_required
<= 8)
6721 v16
.import_uniforms(&v8
);
6722 if (!v16
.run_cs()) {
6723 compiler
->shader_perf_log(log_data
,
6724 "SIMD16 shader failed to compile: %s",
6728 "Couldn't generate SIMD16 program and not "
6729 "enough threads for SIMD8";
6733 cs_set_simd_size(prog_data
, 16);
6734 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6735 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
6739 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6740 NULL
, /* Never used in core profile */
6741 shader
, 32, shader_time_index
);
6742 if (!fail_msg
&& v8
.max_dispatch_width
>= 32 &&
6743 (simd_required
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
6744 /* Try a SIMD32 compile */
6745 if (simd_required
<= 8)
6746 v32
.import_uniforms(&v8
);
6747 else if (simd_required
<= 16)
6748 v32
.import_uniforms(&v16
);
6750 if (!v32
.run_cs()) {
6751 compiler
->shader_perf_log(log_data
,
6752 "SIMD32 shader failed to compile: %s",
6756 "Couldn't generate SIMD32 program and not "
6757 "enough threads for SIMD16";
6761 cs_set_simd_size(prog_data
, 32);
6762 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6766 if (unlikely(cfg
== NULL
)) {
6769 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6774 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6775 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6776 MESA_SHADER_COMPUTE
);
6777 if (INTEL_DEBUG
& DEBUG_CS
) {
6778 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6779 shader
->info
.label
? shader
->info
.label
:
6782 g
.enable_debug(name
);
6785 g
.generate_code(cfg
, prog_data
->simd_size
);
6787 return g
.get_assembly(final_assembly_size
);
6791 * Test the dispatch mask packing assumptions of
6792 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
6793 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
6794 * executed with an unexpected dispatch mask.
6797 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
6799 const gl_shader_stage stage
= bld
.shader
->stage
;
6801 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
6802 bld
.shader
->stage_prog_data
)) {
6803 const fs_builder ubld
= bld
.exec_all().group(1, 0);
6804 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
6805 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
6808 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
6809 ubld
.AND(tmp
, mask
, tmp
);
6811 /* This will loop forever if the dispatch mask doesn't have the expected
6812 * form '2^n-1', in which case tmp will be non-zero.
6814 bld
.emit(BRW_OPCODE_DO
);
6815 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
6816 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));