2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "brw_dead_control_flow.h"
47 #include "main/uniforms.h"
48 #include "brw_fs_live_variables.h"
49 #include "glsl/glsl_types.h"
50 #include "program/sampler.h"
53 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
54 const fs_reg
*src
, unsigned sources
)
56 memset(this, 0, sizeof(*this));
58 this->src
= new fs_reg
[MAX2(sources
, 3)];
59 for (unsigned i
= 0; i
< sources
; i
++)
60 this->src
[i
] = src
[i
];
62 this->opcode
= opcode
;
64 this->sources
= sources
;
65 this->exec_size
= exec_size
;
67 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
69 /* If exec_size == 0, try to guess it from the registers. Since all
70 * manner of things may use hardware registers, we first try to guess
71 * based on GRF registers. If this fails, we will go ahead and take the
72 * width from the destination register.
74 if (this->exec_size
== 0) {
75 if (dst
.file
== GRF
) {
76 this->exec_size
= dst
.width
;
78 for (unsigned i
= 0; i
< sources
; ++i
) {
79 if (src
[i
].file
!= GRF
&& src
[i
].file
!= ATTR
)
82 if (this->exec_size
<= 1)
83 this->exec_size
= src
[i
].width
;
84 assert(src
[i
].width
== 1 || src
[i
].width
== this->exec_size
);
88 if (this->exec_size
== 0 && dst
.file
!= BAD_FILE
)
89 this->exec_size
= dst
.width
;
91 assert(this->exec_size
!= 0);
93 for (unsigned i
= 0; i
< sources
; ++i
) {
94 switch (this->src
[i
].file
) {
96 this->src
[i
].effective_width
= 8;
101 assert(this->src
[i
].width
> 0);
102 if (this->src
[i
].width
== 1) {
103 this->src
[i
].effective_width
= this->exec_size
;
105 this->src
[i
].effective_width
= this->src
[i
].width
;
110 this->src
[i
].effective_width
= this->exec_size
;
113 unreachable("Invalid source register file");
116 this->dst
.effective_width
= this->exec_size
;
118 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
120 /* This will be the case for almost all instructions. */
127 DIV_ROUND_UP(MAX2(dst
.width
* dst
.stride
, 1) * type_sz(dst
.type
), 32);
130 this->regs_written
= 0;
134 unreachable("Invalid destination register file");
136 unreachable("Invalid register file");
139 this->writes_accumulator
= false;
144 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
147 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
149 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
152 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
)
154 init(opcode
, 0, dst
, NULL
, 0);
157 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
160 const fs_reg src
[1] = { src0
};
161 init(opcode
, exec_size
, dst
, src
, 1);
164 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
)
166 const fs_reg src
[1] = { src0
};
167 init(opcode
, 0, dst
, src
, 1);
170 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
171 const fs_reg
&src0
, const fs_reg
&src1
)
173 const fs_reg src
[2] = { src0
, src1
};
174 init(opcode
, exec_size
, dst
, src
, 2);
177 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
180 const fs_reg src
[2] = { src0
, src1
};
181 init(opcode
, 0, dst
, src
, 2);
184 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
185 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
187 const fs_reg src
[3] = { src0
, src1
, src2
};
188 init(opcode
, exec_size
, dst
, src
, 3);
191 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
192 const fs_reg
&src1
, const fs_reg
&src2
)
194 const fs_reg src
[3] = { src0
, src1
, src2
};
195 init(opcode
, 0, dst
, src
, 3);
198 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
,
199 const fs_reg src
[], unsigned sources
)
201 init(opcode
, 0, dst
, src
, sources
);
204 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
205 const fs_reg src
[], unsigned sources
)
207 init(opcode
, exec_width
, dst
, src
, sources
);
210 fs_inst::fs_inst(const fs_inst
&that
)
212 memcpy(this, &that
, sizeof(that
));
214 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
216 for (unsigned i
= 0; i
< that
.sources
; i
++)
217 this->src
[i
] = that
.src
[i
];
226 fs_inst::resize_sources(uint8_t num_sources
)
228 if (this->sources
!= num_sources
) {
229 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
231 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
232 src
[i
] = this->src
[i
];
236 this->sources
= num_sources
;
242 fs_visitor::op(const fs_reg &dst, const fs_reg &src0) \
244 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0); \
249 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
250 const fs_reg &src1) \
252 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
255 #define ALU2_ACC(op) \
257 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
258 const fs_reg &src1) \
260 fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1);\
261 inst->writes_accumulator = true; \
267 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
268 const fs_reg &src1, const fs_reg &src2) \
270 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2);\
302 /** Gen4 predicated IF. */
304 fs_visitor::IF(enum brw_predicate predicate
)
306 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
, dispatch_width
);
307 inst
->predicate
= predicate
;
311 /** Gen6 IF with embedded comparison. */
313 fs_visitor::IF(const fs_reg
&src0
, const fs_reg
&src1
,
314 enum brw_conditional_mod condition
)
316 assert(devinfo
->gen
== 6);
317 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
, dispatch_width
,
318 reg_null_d
, src0
, src1
);
319 inst
->conditional_mod
= condition
;
324 * CMP: Sets the low bit of the destination channels with the result
325 * of the comparison, while the upper bits are undefined, and updates
326 * the flag register with the packed 16 bits of the result.
329 fs_visitor::CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
,
330 enum brw_conditional_mod condition
)
334 /* Take the instruction:
336 * CMP null<d> src0<f> src1<f>
338 * Original gen4 does type conversion to the destination type before
339 * comparison, producing garbage results for floating point comparisons.
341 * The destination type doesn't matter on newer generations, so we set the
342 * type to match src0 so we can compact the instruction.
344 dst
.type
= src0
.type
;
345 if (dst
.file
== HW_REG
)
346 dst
.fixed_hw_reg
.type
= dst
.type
;
348 resolve_ud_negate(&src0
);
349 resolve_ud_negate(&src1
);
351 inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_CMP
, dst
, src0
, src1
);
352 inst
->conditional_mod
= condition
;
358 fs_visitor::LOAD_PAYLOAD(const fs_reg
&dst
, fs_reg
*src
, int sources
)
360 uint8_t exec_size
= dst
.width
;
361 for (int i
= 0; i
< sources
; ++i
) {
362 assert(src
[i
].width
% dst
.width
== 0);
363 if (src
[i
].width
> exec_size
)
364 exec_size
= src
[i
].width
;
367 fs_inst
*inst
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
, exec_size
,
369 inst
->regs_written
= 0;
370 for (int i
= 0; i
< sources
; ++i
) {
371 /* The LOAD_PAYLOAD instruction only really makes sense if we are
372 * dealing with whole registers. If this ever changes, we can deal
375 int size
= inst
->src
[i
].effective_width
* type_sz(src
[i
].type
);
376 assert(size
% 32 == 0);
377 inst
->regs_written
+= (size
+ 31) / 32;
384 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_reg
&dst
,
385 const fs_reg
&surf_index
,
386 const fs_reg
&varying_offset
,
387 uint32_t const_offset
)
389 exec_list instructions
;
392 /* We have our constant surface use a pitch of 4 bytes, so our index can
393 * be any component of a vector, and then we load 4 contiguous
394 * components starting from that.
396 * We break down the const_offset to a portion added to the variable
397 * offset and a portion done using reg_offset, which means that if you
398 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
399 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
400 * CSE can later notice that those loads are all the same and eliminate
401 * the redundant ones.
403 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
404 instructions
.push_tail(ADD(vec4_offset
,
405 varying_offset
, fs_reg(const_offset
& ~3)));
408 if (devinfo
->gen
== 4 && dst
.width
== 8) {
409 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
410 * u, v, r) as parameters, or we can just use the SIMD16 message
411 * consisting of (header, u). We choose the second, at the cost of a
412 * longer return length.
418 if (devinfo
->gen
>= 7)
419 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
421 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
423 assert(dst
.width
% 8 == 0);
424 int regs_written
= 4 * (dst
.width
/ 8) * scale
;
425 fs_reg vec4_result
= fs_reg(GRF
, alloc
.allocate(regs_written
),
426 dst
.type
, dst
.width
);
427 inst
= new(mem_ctx
) fs_inst(op
, vec4_result
, surf_index
, vec4_offset
);
428 inst
->regs_written
= regs_written
;
429 instructions
.push_tail(inst
);
431 if (devinfo
->gen
< 7) {
433 inst
->header_present
= true;
434 if (devinfo
->gen
== 4)
437 inst
->mlen
= 1 + dispatch_width
/ 8;
440 fs_reg result
= offset(vec4_result
, (const_offset
& 3) * scale
);
441 instructions
.push_tail(MOV(dst
, result
));
447 * A helper for MOV generation for fixing up broken hardware SEND dependency
451 fs_visitor::DEP_RESOLVE_MOV(int grf
)
453 fs_inst
*inst
= MOV(brw_null_reg(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
456 inst
->annotation
= "send dependency resolve";
458 /* The caller always wants uncompressed to emit the minimal extra
459 * dependencies, and to avoid having to deal with aligning its regs to 2.
467 fs_inst::equals(fs_inst
*inst
) const
469 return (opcode
== inst
->opcode
&&
470 dst
.equals(inst
->dst
) &&
471 src
[0].equals(inst
->src
[0]) &&
472 src
[1].equals(inst
->src
[1]) &&
473 src
[2].equals(inst
->src
[2]) &&
474 saturate
== inst
->saturate
&&
475 predicate
== inst
->predicate
&&
476 conditional_mod
== inst
->conditional_mod
&&
477 mlen
== inst
->mlen
&&
478 base_mrf
== inst
->base_mrf
&&
479 target
== inst
->target
&&
481 header_present
== inst
->header_present
&&
482 shadow_compare
== inst
->shadow_compare
&&
483 exec_size
== inst
->exec_size
&&
484 offset
== inst
->offset
);
488 fs_inst::overwrites_reg(const fs_reg
®
) const
490 return reg
.in_range(dst
, regs_written
);
494 fs_inst::is_send_from_grf() const
497 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
498 case SHADER_OPCODE_SHADER_TIME_ADD
:
499 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
500 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
501 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
502 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
503 case SHADER_OPCODE_UNTYPED_ATOMIC
:
504 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
505 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
506 case SHADER_OPCODE_TYPED_ATOMIC
:
507 case SHADER_OPCODE_TYPED_SURFACE_READ
:
508 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
509 case SHADER_OPCODE_URB_WRITE_SIMD8
:
511 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
512 return src
[1].file
== GRF
;
513 case FS_OPCODE_FB_WRITE
:
514 return src
[0].file
== GRF
;
517 return src
[0].file
== GRF
;
524 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
526 if (devinfo
->gen
== 6 && is_math())
529 if (is_send_from_grf())
532 if (!backend_instruction::can_do_source_mods())
539 fs_inst::has_side_effects() const
541 return this->eot
|| backend_instruction::has_side_effects();
547 memset(this, 0, sizeof(*this));
551 /** Generic unset register constructor. */
555 this->file
= BAD_FILE
;
558 /** Immediate value constructor. */
559 fs_reg::fs_reg(float f
)
563 this->type
= BRW_REGISTER_TYPE_F
;
564 this->fixed_hw_reg
.dw1
.f
= f
;
568 /** Immediate value constructor. */
569 fs_reg::fs_reg(int32_t i
)
573 this->type
= BRW_REGISTER_TYPE_D
;
574 this->fixed_hw_reg
.dw1
.d
= i
;
578 /** Immediate value constructor. */
579 fs_reg::fs_reg(uint32_t u
)
583 this->type
= BRW_REGISTER_TYPE_UD
;
584 this->fixed_hw_reg
.dw1
.ud
= u
;
588 /** Vector float immediate value constructor. */
589 fs_reg::fs_reg(uint8_t vf
[4])
593 this->type
= BRW_REGISTER_TYPE_VF
;
594 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
597 /** Vector float immediate value constructor. */
598 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
602 this->type
= BRW_REGISTER_TYPE_VF
;
603 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
609 /** Fixed brw_reg. */
610 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
614 this->fixed_hw_reg
= fixed_hw_reg
;
615 this->type
= fixed_hw_reg
.type
;
616 this->width
= 1 << fixed_hw_reg
.width
;
620 fs_reg::equals(const fs_reg
&r
) const
622 return (file
== r
.file
&&
624 reg_offset
== r
.reg_offset
&&
625 subreg_offset
== r
.subreg_offset
&&
627 negate
== r
.negate
&&
629 !reladdr
&& !r
.reladdr
&&
630 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
, sizeof(fixed_hw_reg
)) == 0 &&
636 fs_reg::set_smear(unsigned subreg
)
638 assert(file
!= HW_REG
&& file
!= IMM
);
639 subreg_offset
= subreg
* type_sz(type
);
645 fs_reg::is_contiguous() const
651 fs_visitor::type_size(const struct glsl_type
*type
)
653 unsigned int size
, i
;
655 switch (type
->base_type
) {
658 case GLSL_TYPE_FLOAT
:
660 return type
->components();
661 case GLSL_TYPE_ARRAY
:
662 return type_size(type
->fields
.array
) * type
->length
;
663 case GLSL_TYPE_STRUCT
:
665 for (i
= 0; i
< type
->length
; i
++) {
666 size
+= type_size(type
->fields
.structure
[i
].type
);
669 case GLSL_TYPE_SAMPLER
:
670 /* Samplers take up no register space, since they're baked in at
674 case GLSL_TYPE_ATOMIC_UINT
:
676 case GLSL_TYPE_IMAGE
:
678 case GLSL_TYPE_ERROR
:
679 case GLSL_TYPE_INTERFACE
:
680 case GLSL_TYPE_DOUBLE
:
681 unreachable("not reached");
688 * Create a MOV to read the timestamp register.
690 * The caller is responsible for emitting the MOV. The return value is
691 * the destination of the MOV, with extra parameters set.
694 fs_visitor::get_timestamp(fs_inst
**out_mov
)
696 assert(devinfo
->gen
>= 7);
698 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
701 BRW_REGISTER_TYPE_UD
));
703 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
, 4);
705 fs_inst
*mov
= MOV(dst
, ts
);
706 /* We want to read the 3 fields we care about even if it's not enabled in
709 mov
->force_writemask_all
= true;
711 /* The caller wants the low 32 bits of the timestamp. Since it's running
712 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
713 * which is plenty of time for our purposes. It is identical across the
714 * EUs, but since it's tracking GPU core speed it will increment at a
715 * varying rate as render P-states change.
717 * The caller could also check if render P-states have changed (or anything
718 * else that might disrupt timing) by setting smear to 2 and checking if
719 * that field is != 0.
728 fs_visitor::emit_shader_time_begin()
730 current_annotation
= "shader time start";
732 shader_start_time
= get_timestamp(&mov
);
737 fs_visitor::emit_shader_time_end()
739 current_annotation
= "shader time end";
741 enum shader_time_shader_type type
, written_type
, reset_type
;
743 case MESA_SHADER_VERTEX
:
745 written_type
= ST_VS_WRITTEN
;
746 reset_type
= ST_VS_RESET
;
748 case MESA_SHADER_GEOMETRY
:
750 written_type
= ST_GS_WRITTEN
;
751 reset_type
= ST_GS_RESET
;
753 case MESA_SHADER_FRAGMENT
:
754 if (dispatch_width
== 8) {
756 written_type
= ST_FS8_WRITTEN
;
757 reset_type
= ST_FS8_RESET
;
759 assert(dispatch_width
== 16);
761 written_type
= ST_FS16_WRITTEN
;
762 reset_type
= ST_FS16_RESET
;
765 case MESA_SHADER_COMPUTE
:
767 written_type
= ST_CS_WRITTEN
;
768 reset_type
= ST_CS_RESET
;
771 unreachable("fs_visitor::emit_shader_time_end missing code");
774 /* Insert our code just before the final SEND with EOT. */
775 exec_node
*end
= this->instructions
.get_tail();
776 assert(end
&& ((fs_inst
*) end
)->eot
);
779 fs_reg shader_end_time
= get_timestamp(&tm_read
);
780 end
->insert_before(tm_read
);
782 /* Check that there weren't any timestamp reset events (assuming these
783 * were the only two timestamp reads that happened).
785 fs_reg reset
= shader_end_time
;
787 fs_inst
*test
= AND(reg_null_d
, reset
, fs_reg(1u));
788 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
789 test
->force_writemask_all
= true;
790 end
->insert_before(test
);
791 end
->insert_before(IF(BRW_PREDICATE_NORMAL
));
793 fs_reg start
= shader_start_time
;
795 fs_reg diff
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
, 1);
797 fs_inst
*add
= ADD(diff
, start
, shader_end_time
);
798 add
->force_writemask_all
= true;
799 end
->insert_before(add
);
801 /* If there were no instructions between the two timestamp gets, the diff
802 * is 2 cycles. Remove that overhead, so I can forget about that when
803 * trying to determine the time taken for single instructions.
805 add
= ADD(diff
, diff
, fs_reg(-2u));
806 add
->force_writemask_all
= true;
807 end
->insert_before(add
);
809 end
->insert_before(SHADER_TIME_ADD(type
, diff
));
810 end
->insert_before(SHADER_TIME_ADD(written_type
, fs_reg(1u)));
811 end
->insert_before(new(mem_ctx
) fs_inst(BRW_OPCODE_ELSE
, dispatch_width
));
812 end
->insert_before(SHADER_TIME_ADD(reset_type
, fs_reg(1u)));
813 end
->insert_before(new(mem_ctx
) fs_inst(BRW_OPCODE_ENDIF
, dispatch_width
));
817 fs_visitor::SHADER_TIME_ADD(enum shader_time_shader_type type
, fs_reg value
)
819 int shader_time_index
=
820 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
821 fs_reg offset
= fs_reg(shader_time_index
* SHADER_TIME_STRIDE
);
824 if (dispatch_width
== 8)
825 payload
= vgrf(glsl_type::uvec2_type
);
827 payload
= vgrf(glsl_type::uint_type
);
829 return new(mem_ctx
) fs_inst(SHADER_OPCODE_SHADER_TIME_ADD
,
830 fs_reg(), payload
, offset
, value
);
834 fs_visitor::vfail(const char *format
, va_list va
)
843 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
844 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
846 this->fail_msg
= msg
;
849 fprintf(stderr
, "%s", msg
);
854 fs_visitor::fail(const char *format
, ...)
858 va_start(va
, format
);
864 * Mark this program as impossible to compile in SIMD16 mode.
866 * During the SIMD8 compile (which happens first), we can detect and flag
867 * things that are unsupported in SIMD16 mode, so the compiler can skip
868 * the SIMD16 compile altogether.
870 * During a SIMD16 compile (if one happens anyway), this just calls fail().
873 fs_visitor::no16(const char *format
, ...)
877 va_start(va
, format
);
879 if (dispatch_width
== 16) {
882 simd16_unsupported
= true;
884 if (brw
->perf_debug
) {
886 ralloc_vasprintf_append(&no16_msg
, format
, va
);
888 no16_msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
896 fs_visitor::emit(enum opcode opcode
)
898 return emit(new(mem_ctx
) fs_inst(opcode
, dispatch_width
));
902 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
)
904 return emit(new(mem_ctx
) fs_inst(opcode
, dst
));
908 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
)
910 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
));
914 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
917 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
, src1
));
921 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
922 const fs_reg
&src1
, const fs_reg
&src2
)
924 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
, src1
, src2
));
928 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
,
929 fs_reg src
[], int sources
)
931 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src
, sources
));
935 * Returns true if the instruction has a flag that means it won't
936 * update an entire destination register.
938 * For example, dead code elimination and live variable analysis want to know
939 * when a write to a variable screens off any preceding values that were in
943 fs_inst::is_partial_write() const
945 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
946 (this->dst
.width
* type_sz(this->dst
.type
)) < 32 ||
947 !this->dst
.is_contiguous());
951 fs_inst::regs_read(int arg
) const
953 if (is_tex() && arg
== 0 && src
[0].file
== GRF
) {
955 } else if (opcode
== FS_OPCODE_FB_WRITE
&& arg
== 0) {
957 } else if (opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
&& arg
== 0) {
959 } else if (opcode
== SHADER_OPCODE_UNTYPED_ATOMIC
&& arg
== 0) {
961 } else if (opcode
== SHADER_OPCODE_UNTYPED_SURFACE_READ
&& arg
== 0) {
963 } else if (opcode
== SHADER_OPCODE_UNTYPED_SURFACE_WRITE
&& arg
== 0) {
965 } else if (opcode
== SHADER_OPCODE_TYPED_ATOMIC
&& arg
== 0) {
967 } else if (opcode
== SHADER_OPCODE_TYPED_SURFACE_READ
&& arg
== 0) {
969 } else if (opcode
== SHADER_OPCODE_TYPED_SURFACE_WRITE
&& arg
== 0) {
971 } else if (opcode
== FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
&& arg
== 0) {
973 } else if (opcode
== FS_OPCODE_LINTERP
&& arg
== 0) {
974 return exec_size
/ 4;
977 switch (src
[arg
].file
) {
984 if (src
[arg
].stride
== 0) {
987 int size
= src
[arg
].width
* src
[arg
].stride
* type_sz(src
[arg
].type
);
988 return (size
+ 31) / 32;
991 unreachable("MRF registers are not allowed as sources");
993 unreachable("Invalid register file");
998 fs_inst::reads_flag() const
1004 fs_inst::writes_flag() const
1006 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
1007 opcode
!= BRW_OPCODE_IF
&&
1008 opcode
!= BRW_OPCODE_WHILE
)) ||
1009 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
1013 * Returns how many MRFs an FS opcode will write over.
1015 * Note that this is not the 0 or 1 implied writes in an actual gen
1016 * instruction -- the FS opcodes often generate MOVs in addition.
1019 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
1021 if (inst
->mlen
== 0)
1024 if (inst
->base_mrf
== -1)
1027 switch (inst
->opcode
) {
1028 case SHADER_OPCODE_RCP
:
1029 case SHADER_OPCODE_RSQ
:
1030 case SHADER_OPCODE_SQRT
:
1031 case SHADER_OPCODE_EXP2
:
1032 case SHADER_OPCODE_LOG2
:
1033 case SHADER_OPCODE_SIN
:
1034 case SHADER_OPCODE_COS
:
1035 return 1 * dispatch_width
/ 8;
1036 case SHADER_OPCODE_POW
:
1037 case SHADER_OPCODE_INT_QUOTIENT
:
1038 case SHADER_OPCODE_INT_REMAINDER
:
1039 return 2 * dispatch_width
/ 8;
1040 case SHADER_OPCODE_TEX
:
1042 case SHADER_OPCODE_TXD
:
1043 case SHADER_OPCODE_TXF
:
1044 case SHADER_OPCODE_TXF_CMS
:
1045 case SHADER_OPCODE_TXF_MCS
:
1046 case SHADER_OPCODE_TG4
:
1047 case SHADER_OPCODE_TG4_OFFSET
:
1048 case SHADER_OPCODE_TXL
:
1049 case SHADER_OPCODE_TXS
:
1050 case SHADER_OPCODE_LOD
:
1052 case FS_OPCODE_FB_WRITE
:
1054 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1055 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1057 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
1059 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1061 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1062 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1063 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
1064 case SHADER_OPCODE_TYPED_ATOMIC
:
1065 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1066 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
1067 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1068 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
1069 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
1070 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
1071 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
1074 unreachable("not reached");
1079 fs_visitor::vgrf(const glsl_type
*const type
)
1081 int reg_width
= dispatch_width
/ 8;
1082 return fs_reg(GRF
, alloc
.allocate(type_size(type
) * reg_width
),
1083 brw_type_for_base_type(type
), dispatch_width
);
1087 fs_visitor::vgrf(int num_components
)
1089 int reg_width
= dispatch_width
/ 8;
1090 return fs_reg(GRF
, alloc
.allocate(num_components
* reg_width
),
1091 BRW_REGISTER_TYPE_F
, dispatch_width
);
1094 /** Fixed HW reg constructor. */
1095 fs_reg::fs_reg(enum register_file file
, int reg
)
1100 this->type
= BRW_REGISTER_TYPE_F
;
1111 /** Fixed HW reg constructor. */
1112 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
)
1128 /** Fixed HW reg constructor. */
1129 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
,
1136 this->width
= width
;
1140 fs_visitor::variable_storage(ir_variable
*var
)
1142 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
1146 import_uniforms_callback(const void *key
,
1150 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
1151 const fs_reg
*reg
= (const fs_reg
*)data
;
1153 if (reg
->file
!= UNIFORM
)
1156 hash_table_insert(dst_ht
, data
, key
);
1159 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1160 * This brings in those uniform definitions
1163 fs_visitor::import_uniforms(fs_visitor
*v
)
1165 hash_table_call_foreach(v
->variable_ht
,
1166 import_uniforms_callback
,
1168 this->push_constant_loc
= v
->push_constant_loc
;
1169 this->pull_constant_loc
= v
->pull_constant_loc
;
1170 this->uniforms
= v
->uniforms
;
1171 this->param_size
= v
->param_size
;
1174 /* Our support for uniforms is piggy-backed on the struct
1175 * gl_fragment_program, because that's where the values actually
1176 * get stored, rather than in some global gl_shader_program uniform
1180 fs_visitor::setup_uniform_values(ir_variable
*ir
)
1182 int namelen
= strlen(ir
->name
);
1184 /* The data for our (non-builtin) uniforms is stored in a series of
1185 * gl_uniform_driver_storage structs for each subcomponent that
1186 * glGetUniformLocation() could name. We know it's been set up in the same
1187 * order we'd walk the type, so walk the list of storage and find anything
1188 * with our name, or the prefix of a component that starts with our name.
1190 unsigned params_before
= uniforms
;
1191 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
1192 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
1194 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
1195 (storage
->name
[namelen
] != 0 &&
1196 storage
->name
[namelen
] != '.' &&
1197 storage
->name
[namelen
] != '[')) {
1201 unsigned slots
= storage
->type
->component_slots();
1202 if (storage
->array_elements
)
1203 slots
*= storage
->array_elements
;
1205 for (unsigned i
= 0; i
< slots
; i
++) {
1206 stage_prog_data
->param
[uniforms
++] = &storage
->storage
[i
];
1210 /* Make sure we actually initialized the right amount of stuff here. */
1211 assert(params_before
+ ir
->type
->component_slots() == uniforms
);
1212 (void)params_before
;
1216 /* Our support for builtin uniforms is even scarier than non-builtin.
1217 * It sits on top of the PROG_STATE_VAR parameters that are
1218 * automatically updated from GL context state.
1221 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
1223 const ir_state_slot
*const slots
= ir
->get_state_slots();
1224 assert(slots
!= NULL
);
1226 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1227 /* This state reference has already been setup by ir_to_mesa, but we'll
1228 * get the same index back here.
1230 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1231 (gl_state_index
*)slots
[i
].tokens
);
1233 /* Add each of the unique swizzles of the element as a parameter.
1234 * This'll end up matching the expected layout of the
1235 * array/matrix/structure we're trying to fill in.
1238 for (unsigned int j
= 0; j
< 4; j
++) {
1239 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
1240 if (swiz
== last_swiz
)
1244 stage_prog_data
->param
[uniforms
++] =
1245 &prog
->Parameters
->ParameterValues
[index
][swiz
];
1251 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
1252 bool origin_upper_left
)
1254 assert(stage
== MESA_SHADER_FRAGMENT
);
1255 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1256 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1258 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
1260 /* gl_FragCoord.x */
1261 if (pixel_center_integer
) {
1262 emit(MOV(wpos
, this->pixel_x
));
1264 emit(ADD(wpos
, this->pixel_x
, fs_reg(0.5f
)));
1266 wpos
= offset(wpos
, 1);
1268 /* gl_FragCoord.y */
1269 if (!flip
&& pixel_center_integer
) {
1270 emit(MOV(wpos
, this->pixel_y
));
1272 fs_reg pixel_y
= this->pixel_y
;
1273 float offset
= (pixel_center_integer
? 0.0 : 0.5);
1276 pixel_y
.negate
= true;
1277 offset
+= key
->drawable_height
- 1.0;
1280 emit(ADD(wpos
, pixel_y
, fs_reg(offset
)));
1282 wpos
= offset(wpos
, 1);
1284 /* gl_FragCoord.z */
1285 if (devinfo
->gen
>= 6) {
1286 emit(MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0))));
1288 emit(FS_OPCODE_LINTERP
, wpos
,
1289 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1290 interp_reg(VARYING_SLOT_POS
, 2));
1292 wpos
= offset(wpos
, 1);
1294 /* gl_FragCoord.w: Already set up in emit_interpolation */
1295 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
1301 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1302 glsl_interp_qualifier interpolation_mode
,
1303 bool is_centroid
, bool is_sample
)
1305 brw_wm_barycentric_interp_mode barycoord_mode
;
1306 if (devinfo
->gen
>= 6) {
1308 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1309 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1311 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1312 } else if (is_sample
) {
1313 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1314 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1316 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1318 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1319 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1321 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1324 /* On Ironlake and below, there is only one interpolation mode.
1325 * Centroid interpolation doesn't mean anything on this hardware --
1326 * there is no multisampling.
1328 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1330 return emit(FS_OPCODE_LINTERP
, attr
,
1331 this->delta_xy
[barycoord_mode
], interp
);
1335 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1336 const glsl_type
*type
,
1337 glsl_interp_qualifier interpolation_mode
,
1338 int location
, bool mod_centroid
,
1341 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1343 assert(stage
== MESA_SHADER_FRAGMENT
);
1344 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1345 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1347 unsigned int array_elements
;
1349 if (type
->is_array()) {
1350 array_elements
= type
->length
;
1351 if (array_elements
== 0) {
1352 fail("dereferenced array '%s' has length 0\n", name
);
1354 type
= type
->fields
.array
;
1359 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1361 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1362 if (key
->flat_shade
&& is_gl_Color
) {
1363 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1365 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1369 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1370 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1371 if (prog_data
->urb_setup
[location
] == -1) {
1372 /* If there's no incoming setup data for this slot, don't
1373 * emit interpolation for it.
1375 attr
= offset(attr
, type
->vector_elements
);
1380 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1381 /* Constant interpolation (flat shading) case. The SF has
1382 * handed us defined values in only the constant offset
1383 * field of the setup reg.
1385 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1386 struct brw_reg interp
= interp_reg(location
, k
);
1387 interp
= suboffset(interp
, 3);
1388 interp
.type
= attr
.type
;
1389 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1390 attr
= offset(attr
, 1);
1393 /* Smooth/noperspective interpolation case. */
1394 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1395 struct brw_reg interp
= interp_reg(location
, k
);
1396 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1397 /* Get the pixel/sample mask into f0 so that we know
1398 * which pixels are lit. Then, for each channel that is
1399 * unlit, replace the centroid data with non-centroid
1402 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1405 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1407 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1408 inst
->predicate_inverse
= true;
1409 if (devinfo
->has_pln
)
1410 inst
->no_dd_clear
= true;
1412 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1413 mod_centroid
&& !key
->persample_shading
,
1414 mod_sample
|| key
->persample_shading
);
1415 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1416 inst
->predicate_inverse
= false;
1417 if (devinfo
->has_pln
)
1418 inst
->no_dd_check
= true;
1421 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1422 mod_centroid
&& !key
->persample_shading
,
1423 mod_sample
|| key
->persample_shading
);
1425 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1426 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
1428 attr
= offset(attr
, 1);
1438 fs_visitor::emit_frontfacing_interpolation()
1440 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1442 if (devinfo
->gen
>= 6) {
1443 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1444 * a boolean result from this (~0/true or 0/false).
1446 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1447 * this task in only one instruction:
1448 * - a negation source modifier will flip the bit; and
1449 * - a W -> D type conversion will sign extend the bit into the high
1450 * word of the destination.
1452 * An ASR 15 fills the low word of the destination.
1454 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1457 emit(ASR(*reg
, g0
, fs_reg(15)));
1459 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1460 * a boolean result from this (1/true or 0/false).
1462 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1463 * the negation source modifier to flip it. Unfortunately the SHR
1464 * instruction only operates on UD (or D with an abs source modifier)
1465 * sources without negation.
1467 * Instead, use ASR (which will give ~0/true or 0/false).
1469 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1472 emit(ASR(*reg
, g1_6
, fs_reg(31)));
1479 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1481 assert(stage
== MESA_SHADER_FRAGMENT
);
1482 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1483 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1485 if (key
->compute_pos_offset
) {
1486 /* Convert int_sample_pos to floating point */
1487 emit(MOV(dst
, int_sample_pos
));
1488 /* Scale to the range [0, 1] */
1489 emit(MUL(dst
, dst
, fs_reg(1 / 16.0f
)));
1492 /* From ARB_sample_shading specification:
1493 * "When rendering to a non-multisample buffer, or if multisample
1494 * rasterization is disabled, gl_SamplePosition will always be
1497 emit(MOV(dst
, fs_reg(0.5f
)));
1502 fs_visitor::emit_samplepos_setup()
1504 assert(devinfo
->gen
>= 6);
1506 this->current_annotation
= "compute sample position";
1507 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1509 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1510 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1512 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1513 * mode will be enabled.
1515 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1516 * R31.1:0 Position Offset X/Y for Slot[3:0]
1517 * R31.3:2 Position Offset X/Y for Slot[7:4]
1520 * The X, Y sample positions come in as bytes in thread payload. So, read
1521 * the positions using vstride=16, width=8, hstride=2.
1523 struct brw_reg sample_pos_reg
=
1524 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1525 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1527 if (dispatch_width
== 8) {
1528 emit(MOV(int_sample_x
, fs_reg(sample_pos_reg
)));
1530 emit(MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
)));
1531 emit(MOV(half(int_sample_x
, 1), fs_reg(suboffset(sample_pos_reg
, 16))))
1532 ->force_sechalf
= true;
1534 /* Compute gl_SamplePosition.x */
1535 compute_sample_position(pos
, int_sample_x
);
1536 pos
= offset(pos
, 1);
1537 if (dispatch_width
== 8) {
1538 emit(MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1))));
1540 emit(MOV(half(int_sample_y
, 0),
1541 fs_reg(suboffset(sample_pos_reg
, 1))));
1542 emit(MOV(half(int_sample_y
, 1), fs_reg(suboffset(sample_pos_reg
, 17))))
1543 ->force_sechalf
= true;
1545 /* Compute gl_SamplePosition.y */
1546 compute_sample_position(pos
, int_sample_y
);
1551 fs_visitor::emit_sampleid_setup()
1553 assert(stage
== MESA_SHADER_FRAGMENT
);
1554 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1555 assert(devinfo
->gen
>= 6);
1557 this->current_annotation
= "compute sample id";
1558 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1560 if (key
->compute_sample_id
) {
1561 fs_reg t1
= vgrf(glsl_type::int_type
);
1562 fs_reg t2
= vgrf(glsl_type::int_type
);
1563 t2
.type
= BRW_REGISTER_TYPE_UW
;
1565 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1566 * 8x multisampling, subspan 0 will represent sample N (where N
1567 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1568 * 7. We can find the value of N by looking at R0.0 bits 7:6
1569 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1570 * (since samples are always delivered in pairs). That is, we
1571 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1572 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1573 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1574 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1575 * populating a temporary variable with the sequence (0, 1, 2, 3),
1576 * and then reading from it using vstride=1, width=4, hstride=0.
1577 * These computations hold good for 4x multisampling as well.
1579 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1580 * the first four slots are sample 0 of subspan 0; the next four
1581 * are sample 1 of subspan 0; the third group is sample 0 of
1582 * subspan 1, and finally sample 1 of subspan 1.
1585 inst
= emit(BRW_OPCODE_AND
, t1
,
1586 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1588 inst
->force_writemask_all
= true;
1589 inst
= emit(BRW_OPCODE_SHR
, t1
, t1
, fs_reg(5));
1590 inst
->force_writemask_all
= true;
1591 /* This works for both SIMD8 and SIMD16 */
1592 inst
= emit(MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210)));
1593 inst
->force_writemask_all
= true;
1594 /* This special instruction takes care of setting vstride=1,
1595 * width=4, hstride=0 of t2 during an ADD instruction.
1597 emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1599 /* As per GL_ARB_sample_shading specification:
1600 * "When rendering to a non-multisample buffer, or if multisample
1601 * rasterization is disabled, gl_SampleID will always be zero."
1603 emit(BRW_OPCODE_MOV
, *reg
, fs_reg(0));
1610 fs_visitor::resolve_source_modifiers(fs_reg
*src
)
1612 if (!src
->abs
&& !src
->negate
)
1615 fs_reg temp
= retype(vgrf(1), src
->type
);
1616 emit(MOV(temp
, *src
));
1621 fs_visitor::fix_math_operand(fs_reg src
)
1623 /* Can't do hstride == 0 args on gen6 math, so expand it out. We
1624 * might be able to do better by doing execsize = 1 math and then
1625 * expanding that result out, but we would need to be careful with
1628 * The hardware ignores source modifiers (negate and abs) on math
1629 * instructions, so we also move to a temp to set those up.
1631 if (devinfo
->gen
== 6 && src
.file
!= UNIFORM
&& src
.file
!= IMM
&&
1632 !src
.abs
&& !src
.negate
)
1635 /* Gen7 relaxes most of the above restrictions, but still can't use IMM
1638 if (devinfo
->gen
>= 7 && src
.file
!= IMM
)
1641 fs_reg expanded
= vgrf(glsl_type::float_type
);
1642 expanded
.type
= src
.type
;
1643 emit(BRW_OPCODE_MOV
, expanded
, src
);
1648 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src
)
1651 case SHADER_OPCODE_RCP
:
1652 case SHADER_OPCODE_RSQ
:
1653 case SHADER_OPCODE_SQRT
:
1654 case SHADER_OPCODE_EXP2
:
1655 case SHADER_OPCODE_LOG2
:
1656 case SHADER_OPCODE_SIN
:
1657 case SHADER_OPCODE_COS
:
1660 unreachable("not reached: bad math opcode");
1663 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
1664 * might be able to do better by doing execsize = 1 math and then
1665 * expanding that result out, but we would need to be careful with
1668 * Gen 6 hardware ignores source modifiers (negate and abs) on math
1669 * instructions, so we also move to a temp to set those up.
1671 if (devinfo
->gen
== 6 || devinfo
->gen
== 7)
1672 src
= fix_math_operand(src
);
1674 fs_inst
*inst
= emit(opcode
, dst
, src
);
1676 if (devinfo
->gen
< 6) {
1678 inst
->mlen
= dispatch_width
/ 8;
1685 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
1690 if (devinfo
->gen
>= 8) {
1691 inst
= emit(opcode
, dst
, src0
, src1
);
1692 } else if (devinfo
->gen
>= 6) {
1693 src0
= fix_math_operand(src0
);
1694 src1
= fix_math_operand(src1
);
1696 inst
= emit(opcode
, dst
, src0
, src1
);
1698 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
1699 * "Message Payload":
1701 * "Operand0[7]. For the INT DIV functions, this operand is the
1704 * "Operand1[7]. For the INT DIV functions, this operand is the
1707 bool is_int_div
= opcode
!= SHADER_OPCODE_POW
;
1708 fs_reg
&op0
= is_int_div
? src1
: src0
;
1709 fs_reg
&op1
= is_int_div
? src0
: src1
;
1711 emit(MOV(fs_reg(MRF
, base_mrf
+ 1, op1
.type
, dispatch_width
), op1
));
1712 inst
= emit(opcode
, dst
, op0
, reg_null_f
);
1714 inst
->base_mrf
= base_mrf
;
1715 inst
->mlen
= 2 * dispatch_width
/ 8;
1721 fs_visitor::emit_discard_jump()
1723 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1725 /* For performance, after a discard, jump to the end of the
1726 * shader if all relevant channels have been discarded.
1728 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1729 discard_jump
->flag_subreg
= 1;
1731 discard_jump
->predicate
= (dispatch_width
== 8)
1732 ? BRW_PREDICATE_ALIGN1_ANY8H
1733 : BRW_PREDICATE_ALIGN1_ANY16H
;
1734 discard_jump
->predicate_inverse
= true;
1738 fs_visitor::assign_curb_setup()
1740 if (dispatch_width
== 8) {
1741 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1743 if (stage
== MESA_SHADER_FRAGMENT
) {
1744 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1745 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1746 } else if (stage
== MESA_SHADER_COMPUTE
) {
1747 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1748 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1750 unreachable("Unsupported shader type!");
1754 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1756 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1757 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1758 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1759 if (inst
->src
[i
].file
== UNIFORM
) {
1760 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1762 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1763 constant_nr
= push_constant_loc
[uniform_nr
];
1765 /* Section 5.11 of the OpenGL 4.1 spec says:
1766 * "Out-of-bounds reads return undefined values, which include
1767 * values from other variables of the active program or zero."
1768 * Just return the first push constant.
1773 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1777 inst
->src
[i
].file
= HW_REG
;
1778 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1779 retype(brw_reg
, inst
->src
[i
].type
),
1780 inst
->src
[i
].subreg_offset
);
1787 fs_visitor::calculate_urb_setup()
1789 assert(stage
== MESA_SHADER_FRAGMENT
);
1790 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1791 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1793 memset(prog_data
->urb_setup
, -1,
1794 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1797 /* Figure out where each of the incoming setup attributes lands. */
1798 if (devinfo
->gen
>= 6) {
1799 if (_mesa_bitcount_64(prog
->InputsRead
&
1800 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1801 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1802 * first 16 varying inputs, so we can put them wherever we want.
1803 * Just put them in order.
1805 * This is useful because it means that (a) inputs not used by the
1806 * fragment shader won't take up valuable register space, and (b) we
1807 * won't have to recompile the fragment shader if it gets paired with
1808 * a different vertex (or geometry) shader.
1810 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1811 if (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1812 BITFIELD64_BIT(i
)) {
1813 prog_data
->urb_setup
[i
] = urb_next
++;
1817 /* We have enough input varyings that the SF/SBE pipeline stage can't
1818 * arbitrarily rearrange them to suit our whim; we have to put them
1819 * in an order that matches the output of the previous pipeline stage
1820 * (geometry or vertex shader).
1822 struct brw_vue_map prev_stage_vue_map
;
1823 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1824 key
->input_slots_valid
);
1825 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1826 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1827 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1829 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1830 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1833 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1834 (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1835 BITFIELD64_BIT(varying
))) {
1836 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1839 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1842 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1843 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1844 /* Point size is packed into the header, not as a general attribute */
1845 if (i
== VARYING_SLOT_PSIZ
)
1848 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1849 /* The back color slot is skipped when the front color is
1850 * also written to. In addition, some slots can be
1851 * written in the vertex shader and not read in the
1852 * fragment shader. So the register number must always be
1853 * incremented, mapped or not.
1855 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1856 prog_data
->urb_setup
[i
] = urb_next
;
1862 * It's a FS only attribute, and we did interpolation for this attribute
1863 * in SF thread. So, count it here, too.
1865 * See compile_sf_prog() for more info.
1867 if (prog
->InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1868 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1871 prog_data
->num_varying_inputs
= urb_next
;
1875 fs_visitor::assign_urb_setup()
1877 assert(stage
== MESA_SHADER_FRAGMENT
);
1878 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1880 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1882 /* Offset all the urb_setup[] index by the actual position of the
1883 * setup regs, now that the location of the constants has been chosen.
1885 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1886 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1887 assert(inst
->src
[1].file
== HW_REG
);
1888 inst
->src
[1].fixed_hw_reg
.nr
+= urb_start
;
1891 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1892 assert(inst
->src
[0].file
== HW_REG
);
1893 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1897 /* Each attribute is 4 setup channels, each of which is half a reg. */
1898 this->first_non_payload_grf
=
1899 urb_start
+ prog_data
->num_varying_inputs
* 2;
1903 fs_visitor::assign_vs_urb_setup()
1905 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1906 int grf
, count
, slot
, channel
, attr
;
1908 assert(stage
== MESA_SHADER_VERTEX
);
1909 count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1910 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1913 /* Each attribute is 4 regs. */
1914 this->first_non_payload_grf
=
1915 payload
.num_regs
+ prog_data
->curb_read_length
+ count
* 4;
1917 unsigned vue_entries
=
1918 MAX2(count
, vs_prog_data
->base
.vue_map
.num_slots
);
1920 vs_prog_data
->base
.urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1921 vs_prog_data
->base
.urb_read_length
= (count
+ 1) / 2;
1923 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1925 /* Rewrite all ATTR file references to the hw grf that they land in. */
1926 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1927 for (int i
= 0; i
< inst
->sources
; i
++) {
1928 if (inst
->src
[i
].file
== ATTR
) {
1930 if (inst
->src
[i
].reg
== VERT_ATTRIB_MAX
) {
1933 /* Attributes come in in a contiguous block, ordered by their
1934 * gl_vert_attrib value. That means we can compute the slot
1935 * number for an attribute by masking out the enabled
1936 * attributes before it and counting the bits.
1938 attr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
/ 4;
1939 slot
= _mesa_bitcount_64(vs_prog_data
->inputs_read
&
1940 BITFIELD64_MASK(attr
));
1943 channel
= inst
->src
[i
].reg_offset
& 3;
1945 grf
= payload
.num_regs
+
1946 prog_data
->curb_read_length
+
1949 inst
->src
[i
].file
= HW_REG
;
1950 inst
->src
[i
].fixed_hw_reg
=
1951 retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
);
1958 * Split large virtual GRFs into separate components if we can.
1960 * This is mostly duplicated with what brw_fs_vector_splitting does,
1961 * but that's really conservative because it's afraid of doing
1962 * splitting that doesn't result in real progress after the rest of
1963 * the optimization phases, which would cause infinite looping in
1964 * optimization. We can do it once here, safely. This also has the
1965 * opportunity to split interpolated values, or maybe even uniforms,
1966 * which we don't have at the IR level.
1968 * We want to split, because virtual GRFs are what we register
1969 * allocate and spill (due to contiguousness requirements for some
1970 * instructions), and they're what we naturally generate in the
1971 * codegen process, but most virtual GRFs don't actually need to be
1972 * contiguous sets of GRFs. If we split, we'll end up with reduced
1973 * live intervals and better dead code elimination and coalescing.
1976 fs_visitor::split_virtual_grfs()
1978 int num_vars
= this->alloc
.count
;
1980 /* Count the total number of registers */
1982 int vgrf_to_reg
[num_vars
];
1983 for (int i
= 0; i
< num_vars
; i
++) {
1984 vgrf_to_reg
[i
] = reg_count
;
1985 reg_count
+= alloc
.sizes
[i
];
1988 /* An array of "split points". For each register slot, this indicates
1989 * if this slot can be separated from the previous slot. Every time an
1990 * instruction uses multiple elements of a register (as a source or
1991 * destination), we mark the used slots as inseparable. Then we go
1992 * through and split the registers into the smallest pieces we can.
1994 bool split_points
[reg_count
];
1995 memset(split_points
, 0, sizeof(split_points
));
1997 /* Mark all used registers as fully splittable */
1998 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1999 if (inst
->dst
.file
== GRF
) {
2000 int reg
= vgrf_to_reg
[inst
->dst
.reg
];
2001 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.reg
]; j
++)
2002 split_points
[reg
+ j
] = true;
2005 for (int i
= 0; i
< inst
->sources
; i
++) {
2006 if (inst
->src
[i
].file
== GRF
) {
2007 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
];
2008 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].reg
]; j
++)
2009 split_points
[reg
+ j
] = true;
2014 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2015 if (inst
->dst
.file
== GRF
) {
2016 int reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
2017 for (int j
= 1; j
< inst
->regs_written
; j
++)
2018 split_points
[reg
+ j
] = false;
2020 for (int i
= 0; i
< inst
->sources
; i
++) {
2021 if (inst
->src
[i
].file
== GRF
) {
2022 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
2023 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
2024 split_points
[reg
+ j
] = false;
2029 int new_virtual_grf
[reg_count
];
2030 int new_reg_offset
[reg_count
];
2033 for (int i
= 0; i
< num_vars
; i
++) {
2034 /* The first one should always be 0 as a quick sanity check. */
2035 assert(split_points
[reg
] == false);
2038 new_reg_offset
[reg
] = 0;
2043 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
2044 /* If this is a split point, reset the offset to 0 and allocate a
2045 * new virtual GRF for the previous offset many registers
2047 if (split_points
[reg
]) {
2048 assert(offset
<= MAX_VGRF_SIZE
);
2049 int grf
= alloc
.allocate(offset
);
2050 for (int k
= reg
- offset
; k
< reg
; k
++)
2051 new_virtual_grf
[k
] = grf
;
2054 new_reg_offset
[reg
] = offset
;
2059 /* The last one gets the original register number */
2060 assert(offset
<= MAX_VGRF_SIZE
);
2061 alloc
.sizes
[i
] = offset
;
2062 for (int k
= reg
- offset
; k
< reg
; k
++)
2063 new_virtual_grf
[k
] = i
;
2065 assert(reg
== reg_count
);
2067 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2068 if (inst
->dst
.file
== GRF
) {
2069 reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
2070 inst
->dst
.reg
= new_virtual_grf
[reg
];
2071 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
2072 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2074 for (int i
= 0; i
< inst
->sources
; i
++) {
2075 if (inst
->src
[i
].file
== GRF
) {
2076 reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
2077 inst
->src
[i
].reg
= new_virtual_grf
[reg
];
2078 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
2079 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2083 invalidate_live_intervals();
2087 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
2089 * During code generation, we create tons of temporary variables, many of
2090 * which get immediately killed and are never used again. Yet, in later
2091 * optimization and analysis passes, such as compute_live_intervals, we need
2092 * to loop over all the virtual GRFs. Compacting them can save a lot of
2096 fs_visitor::compact_virtual_grfs()
2098 bool progress
= false;
2099 int remap_table
[this->alloc
.count
];
2100 memset(remap_table
, -1, sizeof(remap_table
));
2102 /* Mark which virtual GRFs are used. */
2103 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
2104 if (inst
->dst
.file
== GRF
)
2105 remap_table
[inst
->dst
.reg
] = 0;
2107 for (int i
= 0; i
< inst
->sources
; i
++) {
2108 if (inst
->src
[i
].file
== GRF
)
2109 remap_table
[inst
->src
[i
].reg
] = 0;
2113 /* Compact the GRF arrays. */
2115 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
2116 if (remap_table
[i
] == -1) {
2117 /* We just found an unused register. This means that we are
2118 * actually going to compact something.
2122 remap_table
[i
] = new_index
;
2123 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
2124 invalidate_live_intervals();
2129 this->alloc
.count
= new_index
;
2131 /* Patch all the instructions to use the newly renumbered registers */
2132 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2133 if (inst
->dst
.file
== GRF
)
2134 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
2136 for (int i
= 0; i
< inst
->sources
; i
++) {
2137 if (inst
->src
[i
].file
== GRF
)
2138 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
2142 /* Patch all the references to delta_xy, since they're used in register
2143 * allocation. If they're unused, switch them to BAD_FILE so we don't
2144 * think some random VGRF is delta_xy.
2146 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2147 if (delta_xy
[i
].file
== GRF
) {
2148 if (remap_table
[delta_xy
[i
].reg
] != -1) {
2149 delta_xy
[i
].reg
= remap_table
[delta_xy
[i
].reg
];
2151 delta_xy
[i
].file
= BAD_FILE
;
2160 * Implements array access of uniforms by inserting a
2161 * PULL_CONSTANT_LOAD instruction.
2163 * Unlike temporary GRF array access (where we don't support it due to
2164 * the difficulty of doing relative addressing on instruction
2165 * destinations), we could potentially do array access of uniforms
2166 * that were loaded in GRF space as push constants. In real-world
2167 * usage we've seen, though, the arrays being used are always larger
2168 * than we could load as push constants, so just always move all
2169 * uniform array access out to a pull constant buffer.
2172 fs_visitor::move_uniform_array_access_to_pull_constants()
2174 if (dispatch_width
!= 8)
2177 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2178 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
2180 /* Walk through and find array access of uniforms. Put a copy of that
2181 * uniform in the pull constant buffer.
2183 * Note that we don't move constant-indexed accesses to arrays. No
2184 * testing has been done of the performance impact of this choice.
2186 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2187 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2188 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
2191 int uniform
= inst
->src
[i
].reg
;
2193 /* If this array isn't already present in the pull constant buffer,
2196 if (pull_constant_loc
[uniform
] == -1) {
2197 const gl_constant_value
**values
= &stage_prog_data
->param
[uniform
];
2199 assert(param_size
[uniform
]);
2201 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
2202 pull_constant_loc
[uniform
+ j
] = stage_prog_data
->nr_pull_params
;
2204 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
2213 * Assign UNIFORM file registers to either push constants or pull constants.
2215 * We allow a fragment shader to have more than the specified minimum
2216 * maximum number of fragment shader uniform components (64). If
2217 * there are too many of these, they'd fill up all of register space.
2218 * So, this will push some of them out to the pull constant buffer and
2219 * update the program to load them.
2222 fs_visitor::assign_constant_locations()
2224 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
2225 if (dispatch_width
!= 8)
2228 /* Find which UNIFORM registers are still in use. */
2229 bool is_live
[uniforms
];
2230 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2234 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2235 for (int i
= 0; i
< inst
->sources
; i
++) {
2236 if (inst
->src
[i
].file
!= UNIFORM
)
2239 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
2240 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
2241 is_live
[constant_nr
] = true;
2245 /* Only allow 16 registers (128 uniform components) as push constants.
2247 * Just demote the end of the list. We could probably do better
2248 * here, demoting things that are rarely used in the program first.
2250 * If changing this value, note the limitation about total_regs in
2253 unsigned int max_push_components
= 16 * 8;
2254 unsigned int num_push_constants
= 0;
2256 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2258 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2259 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
2260 /* This UNIFORM register is either dead, or has already been demoted
2261 * to a pull const. Mark it as no longer living in the param[] array.
2263 push_constant_loc
[i
] = -1;
2267 if (num_push_constants
< max_push_components
) {
2268 /* Retain as a push constant. Record the location in the params[]
2271 push_constant_loc
[i
] = num_push_constants
++;
2273 /* Demote to a pull constant. */
2274 push_constant_loc
[i
] = -1;
2276 int pull_index
= stage_prog_data
->nr_pull_params
++;
2277 stage_prog_data
->pull_param
[pull_index
] = stage_prog_data
->param
[i
];
2278 pull_constant_loc
[i
] = pull_index
;
2282 stage_prog_data
->nr_params
= num_push_constants
;
2284 /* Up until now, the param[] array has been indexed by reg + reg_offset
2285 * of UNIFORM registers. Condense it to only contain the uniforms we
2286 * chose to upload as push constants.
2288 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2289 int remapped
= push_constant_loc
[i
];
2294 assert(remapped
<= (int)i
);
2295 stage_prog_data
->param
[remapped
] = stage_prog_data
->param
[i
];
2300 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2301 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2304 fs_visitor::demote_pull_constants()
2306 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2307 for (int i
= 0; i
< inst
->sources
; i
++) {
2308 if (inst
->src
[i
].file
!= UNIFORM
)
2312 unsigned location
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
2313 if (location
>= uniforms
) /* Out of bounds access */
2316 pull_index
= pull_constant_loc
[location
];
2318 if (pull_index
== -1)
2321 /* Set up the annotation tracking for new generated instructions. */
2323 current_annotation
= inst
->annotation
;
2325 fs_reg
surf_index(stage_prog_data
->binding_table
.pull_constants_start
);
2326 fs_reg dst
= vgrf(glsl_type::float_type
);
2328 /* Generate a pull load into dst. */
2329 if (inst
->src
[i
].reladdr
) {
2330 exec_list list
= VARYING_PULL_CONSTANT_LOAD(dst
,
2332 *inst
->src
[i
].reladdr
,
2334 inst
->insert_before(block
, &list
);
2335 inst
->src
[i
].reladdr
= NULL
;
2337 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
2339 new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, 8,
2340 dst
, surf_index
, offset
);
2341 inst
->insert_before(block
, pull
);
2342 inst
->src
[i
].set_smear(pull_index
& 3);
2345 /* Rewrite the instruction to use the temporary VGRF. */
2346 inst
->src
[i
].file
= GRF
;
2347 inst
->src
[i
].reg
= dst
.reg
;
2348 inst
->src
[i
].reg_offset
= 0;
2349 inst
->src
[i
].width
= dispatch_width
;
2352 invalidate_live_intervals();
2356 fs_visitor::opt_algebraic()
2358 bool progress
= false;
2360 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2361 switch (inst
->opcode
) {
2362 case BRW_OPCODE_MOV
:
2363 if (inst
->src
[0].file
!= IMM
)
2366 if (inst
->saturate
) {
2367 if (inst
->dst
.type
!= inst
->src
[0].type
)
2368 assert(!"unimplemented: saturate mixed types");
2370 if (brw_saturate_immediate(inst
->dst
.type
,
2371 &inst
->src
[0].fixed_hw_reg
)) {
2372 inst
->saturate
= false;
2378 case BRW_OPCODE_MUL
:
2379 if (inst
->src
[1].file
!= IMM
)
2383 if (inst
->src
[1].is_one()) {
2384 inst
->opcode
= BRW_OPCODE_MOV
;
2385 inst
->src
[1] = reg_undef
;
2391 if (inst
->src
[1].is_negative_one()) {
2392 inst
->opcode
= BRW_OPCODE_MOV
;
2393 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2394 inst
->src
[1] = reg_undef
;
2400 if (inst
->src
[1].is_zero()) {
2401 inst
->opcode
= BRW_OPCODE_MOV
;
2402 inst
->src
[0] = inst
->src
[1];
2403 inst
->src
[1] = reg_undef
;
2408 if (inst
->src
[0].file
== IMM
) {
2409 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2410 inst
->opcode
= BRW_OPCODE_MOV
;
2411 inst
->src
[0].fixed_hw_reg
.dw1
.f
*= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2412 inst
->src
[1] = reg_undef
;
2417 case BRW_OPCODE_ADD
:
2418 if (inst
->src
[1].file
!= IMM
)
2422 if (inst
->src
[1].is_zero()) {
2423 inst
->opcode
= BRW_OPCODE_MOV
;
2424 inst
->src
[1] = reg_undef
;
2429 if (inst
->src
[0].file
== IMM
) {
2430 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2431 inst
->opcode
= BRW_OPCODE_MOV
;
2432 inst
->src
[0].fixed_hw_reg
.dw1
.f
+= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2433 inst
->src
[1] = reg_undef
;
2439 if (inst
->src
[0].equals(inst
->src
[1])) {
2440 inst
->opcode
= BRW_OPCODE_MOV
;
2441 inst
->src
[1] = reg_undef
;
2446 case BRW_OPCODE_LRP
:
2447 if (inst
->src
[1].equals(inst
->src
[2])) {
2448 inst
->opcode
= BRW_OPCODE_MOV
;
2449 inst
->src
[0] = inst
->src
[1];
2450 inst
->src
[1] = reg_undef
;
2451 inst
->src
[2] = reg_undef
;
2456 case BRW_OPCODE_CMP
:
2457 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2459 inst
->src
[0].negate
&&
2460 inst
->src
[1].is_zero()) {
2461 inst
->src
[0].abs
= false;
2462 inst
->src
[0].negate
= false;
2463 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2468 case BRW_OPCODE_SEL
:
2469 if (inst
->src
[0].equals(inst
->src
[1])) {
2470 inst
->opcode
= BRW_OPCODE_MOV
;
2471 inst
->src
[1] = reg_undef
;
2472 inst
->predicate
= BRW_PREDICATE_NONE
;
2473 inst
->predicate_inverse
= false;
2475 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2476 switch (inst
->conditional_mod
) {
2477 case BRW_CONDITIONAL_LE
:
2478 case BRW_CONDITIONAL_L
:
2479 switch (inst
->src
[1].type
) {
2480 case BRW_REGISTER_TYPE_F
:
2481 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
>= 1.0f
) {
2482 inst
->opcode
= BRW_OPCODE_MOV
;
2483 inst
->src
[1] = reg_undef
;
2484 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2492 case BRW_CONDITIONAL_GE
:
2493 case BRW_CONDITIONAL_G
:
2494 switch (inst
->src
[1].type
) {
2495 case BRW_REGISTER_TYPE_F
:
2496 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
<= 0.0f
) {
2497 inst
->opcode
= BRW_OPCODE_MOV
;
2498 inst
->src
[1] = reg_undef
;
2499 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2511 case BRW_OPCODE_MAD
:
2512 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2513 inst
->opcode
= BRW_OPCODE_MOV
;
2514 inst
->src
[1] = reg_undef
;
2515 inst
->src
[2] = reg_undef
;
2517 } else if (inst
->src
[0].is_zero()) {
2518 inst
->opcode
= BRW_OPCODE_MUL
;
2519 inst
->src
[0] = inst
->src
[2];
2520 inst
->src
[2] = reg_undef
;
2522 } else if (inst
->src
[1].is_one()) {
2523 inst
->opcode
= BRW_OPCODE_ADD
;
2524 inst
->src
[1] = inst
->src
[2];
2525 inst
->src
[2] = reg_undef
;
2527 } else if (inst
->src
[2].is_one()) {
2528 inst
->opcode
= BRW_OPCODE_ADD
;
2529 inst
->src
[2] = reg_undef
;
2531 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2532 inst
->opcode
= BRW_OPCODE_ADD
;
2533 inst
->src
[1].fixed_hw_reg
.dw1
.f
*= inst
->src
[2].fixed_hw_reg
.dw1
.f
;
2534 inst
->src
[2] = reg_undef
;
2538 case SHADER_OPCODE_RCP
: {
2539 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2540 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2541 if (inst
->src
[0].equals(prev
->dst
)) {
2542 inst
->opcode
= SHADER_OPCODE_RSQ
;
2543 inst
->src
[0] = prev
->src
[0];
2549 case SHADER_OPCODE_BROADCAST
:
2550 if (is_uniform(inst
->src
[0])) {
2551 inst
->opcode
= BRW_OPCODE_MOV
;
2553 inst
->force_writemask_all
= true;
2555 } else if (inst
->src
[1].file
== IMM
) {
2556 inst
->opcode
= BRW_OPCODE_MOV
;
2557 inst
->src
[0] = component(inst
->src
[0],
2558 inst
->src
[1].fixed_hw_reg
.dw1
.ud
);
2560 inst
->force_writemask_all
= true;
2569 /* Swap if src[0] is immediate. */
2570 if (progress
&& inst
->is_commutative()) {
2571 if (inst
->src
[0].file
== IMM
) {
2572 fs_reg tmp
= inst
->src
[1];
2573 inst
->src
[1] = inst
->src
[0];
2582 * Optimize sample messages that have constant zero values for the trailing
2583 * texture coordinates. We can just reduce the message length for these
2584 * instructions instead of reserving a register for it. Trailing parameters
2585 * that aren't sent default to zero anyway. This will cause the dead code
2586 * eliminator to remove the MOV instruction that would otherwise be emitted to
2587 * set up the zero value.
2590 fs_visitor::opt_zero_samples()
2592 /* Gen4 infers the texturing opcode based on the message length so we can't
2595 if (devinfo
->gen
< 5)
2598 bool progress
= false;
2600 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2601 if (!inst
->is_tex())
2604 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2606 if (load_payload
->is_head_sentinel() ||
2607 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2610 /* We don't want to remove the message header. Removing all of the
2611 * parameters is avoided because it seems to cause a GPU hang but I
2612 * can't find any documentation indicating that this is expected.
2614 while (inst
->mlen
> inst
->header_present
+ dispatch_width
/ 8 &&
2615 load_payload
->src
[(inst
->mlen
- inst
->header_present
) /
2616 (dispatch_width
/ 8) +
2617 inst
->header_present
- 1].is_zero()) {
2618 inst
->mlen
-= dispatch_width
/ 8;
2624 invalidate_live_intervals();
2630 * Optimize sample messages which are followed by the final RT write.
2632 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2633 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2634 * final texturing results copied to the framebuffer write payload and modify
2635 * them to write to the framebuffer directly.
2638 fs_visitor::opt_sampler_eot()
2640 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2642 if (stage
!= MESA_SHADER_FRAGMENT
)
2645 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2648 /* FINISHME: It should be possible to implement this optimization when there
2649 * are multiple drawbuffers.
2651 if (key
->nr_color_regions
!= 1)
2654 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2655 fs_inst
*fb_write
= (fs_inst
*) cfg
->blocks
[cfg
->num_blocks
- 1]->end();
2656 assert(fb_write
->eot
);
2657 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2659 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2661 /* There wasn't one; nothing to do. */
2662 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2665 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2666 * It's very likely to be the previous instruction.
2668 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2669 if (load_payload
->is_head_sentinel() ||
2670 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2673 assert(!tex_inst
->eot
); /* We can't get here twice */
2674 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2676 tex_inst
->offset
|= fb_write
->target
<< 24;
2677 tex_inst
->eot
= true;
2678 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2680 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2681 * to create a new LOAD_PAYLOAD command with the same sources and a space
2682 * saved for the header. Using a new destination register not only makes sure
2683 * we have enough space, but it will make sure the dead code eliminator kills
2684 * the instruction that this will replace.
2686 if (tex_inst
->header_present
)
2689 fs_reg send_header
= vgrf(load_payload
->sources
+ 1);
2690 fs_reg
*new_sources
=
2691 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2693 new_sources
[0] = fs_reg();
2694 for (int i
= 0; i
< load_payload
->sources
; i
++)
2695 new_sources
[i
+1] = load_payload
->src
[i
];
2697 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2698 * requires a lot of information about the sources to appropriately figure
2699 * out the number of registers needed to be used. Given this stage in our
2700 * optimization, we may not have the appropriate GRFs required by
2701 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2702 * manually emit the instruction.
2704 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2705 load_payload
->exec_size
,
2708 load_payload
->sources
+ 1);
2710 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2712 tex_inst
->header_present
= true;
2713 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2714 tex_inst
->src
[0] = send_header
;
2715 tex_inst
->dst
= reg_null_ud
;
2721 fs_visitor::opt_register_renaming()
2723 bool progress
= false;
2726 int remap
[alloc
.count
];
2727 memset(remap
, -1, sizeof(int) * alloc
.count
);
2729 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2730 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2732 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2733 inst
->opcode
== BRW_OPCODE_WHILE
) {
2737 /* Rewrite instruction sources. */
2738 for (int i
= 0; i
< inst
->sources
; i
++) {
2739 if (inst
->src
[i
].file
== GRF
&&
2740 remap
[inst
->src
[i
].reg
] != -1 &&
2741 remap
[inst
->src
[i
].reg
] != inst
->src
[i
].reg
) {
2742 inst
->src
[i
].reg
= remap
[inst
->src
[i
].reg
];
2747 const int dst
= inst
->dst
.reg
;
2750 inst
->dst
.file
== GRF
&&
2751 alloc
.sizes
[inst
->dst
.reg
] == inst
->dst
.width
/ 8 &&
2752 !inst
->is_partial_write()) {
2753 if (remap
[dst
] == -1) {
2756 remap
[dst
] = alloc
.allocate(inst
->dst
.width
/ 8);
2757 inst
->dst
.reg
= remap
[dst
];
2760 } else if (inst
->dst
.file
== GRF
&&
2762 remap
[dst
] != dst
) {
2763 inst
->dst
.reg
= remap
[dst
];
2769 invalidate_live_intervals();
2771 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2772 if (delta_xy
[i
].file
== GRF
&& remap
[delta_xy
[i
].reg
] != -1) {
2773 delta_xy
[i
].reg
= remap
[delta_xy
[i
].reg
];
2782 * Remove redundant or useless discard jumps.
2784 * For example, we can eliminate jumps in the following sequence:
2786 * discard-jump (redundant with the next jump)
2787 * discard-jump (useless; jumps to the next instruction)
2791 fs_visitor::opt_redundant_discard_jumps()
2793 bool progress
= false;
2795 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2797 fs_inst
*placeholder_halt
= NULL
;
2798 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2799 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2800 placeholder_halt
= inst
;
2805 if (!placeholder_halt
)
2808 /* Delete any HALTs immediately before the placeholder halt. */
2809 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2810 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2811 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2812 prev
->remove(last_bblock
);
2817 invalidate_live_intervals();
2823 fs_visitor::compute_to_mrf()
2825 bool progress
= false;
2828 /* No MRFs on Gen >= 7. */
2829 if (devinfo
->gen
>= 7)
2832 calculate_live_intervals();
2834 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2838 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2839 inst
->is_partial_write() ||
2840 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2841 inst
->dst
.type
!= inst
->src
[0].type
||
2842 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2843 !inst
->src
[0].is_contiguous() ||
2844 inst
->src
[0].subreg_offset
)
2847 /* Work out which hardware MRF registers are written by this
2850 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2852 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2853 mrf_high
= mrf_low
+ 4;
2854 } else if (inst
->exec_size
== 16) {
2855 mrf_high
= mrf_low
+ 1;
2860 /* Can't compute-to-MRF this GRF if someone else was going to
2863 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2866 /* Found a move of a GRF to a MRF. Let's see if we can go
2867 * rewrite the thing that made this GRF to write into the MRF.
2869 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2870 if (scan_inst
->dst
.file
== GRF
&&
2871 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2872 /* Found the last thing to write our reg we want to turn
2873 * into a compute-to-MRF.
2876 /* If this one instruction didn't populate all the
2877 * channels, bail. We might be able to rewrite everything
2878 * that writes that reg, but it would require smarter
2879 * tracking to delay the rewriting until complete success.
2881 if (scan_inst
->is_partial_write())
2884 /* Things returning more than one register would need us to
2885 * understand coalescing out more than one MOV at a time.
2887 if (scan_inst
->regs_written
> scan_inst
->dst
.width
/ 8)
2890 /* SEND instructions can't have MRF as a destination. */
2891 if (scan_inst
->mlen
)
2894 if (devinfo
->gen
== 6) {
2895 /* gen6 math instructions must have the destination be
2896 * GRF, so no compute-to-MRF for them.
2898 if (scan_inst
->is_math()) {
2903 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2904 /* Found the creator of our MRF's source value. */
2905 scan_inst
->dst
.file
= MRF
;
2906 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2907 scan_inst
->saturate
|= inst
->saturate
;
2908 inst
->remove(block
);
2914 /* We don't handle control flow here. Most computation of
2915 * values that end up in MRFs are shortly before the MRF
2918 if (block
->start() == scan_inst
)
2921 /* You can't read from an MRF, so if someone else reads our
2922 * MRF's source GRF that we wanted to rewrite, that stops us.
2924 bool interfered
= false;
2925 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2926 if (scan_inst
->src
[i
].file
== GRF
&&
2927 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2928 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2935 if (scan_inst
->dst
.file
== MRF
) {
2936 /* If somebody else writes our MRF here, we can't
2937 * compute-to-MRF before that.
2939 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2942 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2943 scan_mrf_high
= scan_mrf_low
+ 4;
2944 } else if (scan_inst
->exec_size
== 16) {
2945 scan_mrf_high
= scan_mrf_low
+ 1;
2947 scan_mrf_high
= scan_mrf_low
;
2950 if (mrf_low
== scan_mrf_low
||
2951 mrf_low
== scan_mrf_high
||
2952 mrf_high
== scan_mrf_low
||
2953 mrf_high
== scan_mrf_high
) {
2958 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2959 /* Found a SEND instruction, which means that there are
2960 * live values in MRFs from base_mrf to base_mrf +
2961 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2964 if (mrf_low
>= scan_inst
->base_mrf
&&
2965 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2968 if (mrf_high
>= scan_inst
->base_mrf
&&
2969 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2977 invalidate_live_intervals();
2983 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2984 * instructions to FS_OPCODE_REP_FB_WRITE.
2987 fs_visitor::emit_repclear_shader()
2989 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2991 int color_mrf
= base_mrf
+ 2;
2993 fs_inst
*mov
= emit(MOV(vec4(brw_message_reg(color_mrf
)),
2994 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
)));
2995 mov
->force_writemask_all
= true;
2998 if (key
->nr_color_regions
== 1) {
2999 write
= emit(FS_OPCODE_REP_FB_WRITE
);
3000 write
->saturate
= key
->clamp_fragment_color
;
3001 write
->base_mrf
= color_mrf
;
3003 write
->header_present
= false;
3006 assume(key
->nr_color_regions
> 0);
3007 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3008 write
= emit(FS_OPCODE_REP_FB_WRITE
);
3009 write
->saturate
= key
->clamp_fragment_color
;
3010 write
->base_mrf
= base_mrf
;
3012 write
->header_present
= true;
3020 assign_constant_locations();
3021 assign_curb_setup();
3023 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3024 assert(mov
->src
[0].file
== HW_REG
);
3025 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].fixed_hw_reg
.nr
, 0);
3029 * Walks through basic blocks, looking for repeated MRF writes and
3030 * removing the later ones.
3033 fs_visitor::remove_duplicate_mrf_writes()
3035 fs_inst
*last_mrf_move
[16];
3036 bool progress
= false;
3038 /* Need to update the MRF tracking for compressed instructions. */
3039 if (dispatch_width
== 16)
3042 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3044 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3045 if (inst
->is_control_flow()) {
3046 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3049 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3050 inst
->dst
.file
== MRF
) {
3051 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
3052 if (prev_inst
&& inst
->equals(prev_inst
)) {
3053 inst
->remove(block
);
3059 /* Clear out the last-write records for MRFs that were overwritten. */
3060 if (inst
->dst
.file
== MRF
) {
3061 last_mrf_move
[inst
->dst
.reg
] = NULL
;
3064 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3065 /* Found a SEND instruction, which will include two or fewer
3066 * implied MRF writes. We could do better here.
3068 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3069 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3073 /* Clear out any MRF move records whose sources got overwritten. */
3074 if (inst
->dst
.file
== GRF
) {
3075 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3076 if (last_mrf_move
[i
] &&
3077 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
3078 last_mrf_move
[i
] = NULL
;
3083 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3084 inst
->dst
.file
== MRF
&&
3085 inst
->src
[0].file
== GRF
&&
3086 !inst
->is_partial_write()) {
3087 last_mrf_move
[inst
->dst
.reg
] = inst
;
3092 invalidate_live_intervals();
3098 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3100 /* Clear the flag for registers that actually got read (as expected). */
3101 for (int i
= 0; i
< inst
->sources
; i
++) {
3103 if (inst
->src
[i
].file
== GRF
) {
3104 grf
= inst
->src
[i
].reg
;
3105 } else if (inst
->src
[i
].file
== HW_REG
&&
3106 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
3107 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
3112 if (grf
>= first_grf
&&
3113 grf
< first_grf
+ grf_len
) {
3114 deps
[grf
- first_grf
] = false;
3115 if (inst
->exec_size
== 16)
3116 deps
[grf
- first_grf
+ 1] = false;
3122 * Implements this workaround for the original 965:
3124 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3125 * check for post destination dependencies on this instruction, software
3126 * must ensure that there is no destination hazard for the case of ‘write
3127 * followed by a posted write’ shown in the following example.
3130 * 2. send r3.xy <rest of send instruction>
3133 * Due to no post-destination dependency check on the ‘send’, the above
3134 * code sequence could have two instructions (1 and 2) in flight at the
3135 * same time that both consider ‘r3’ as the target of their final writes.
3138 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3141 int write_len
= inst
->regs_written
;
3142 int first_write_grf
= inst
->dst
.reg
;
3143 bool needs_dep
[BRW_MAX_MRF
];
3144 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3146 memset(needs_dep
, false, sizeof(needs_dep
));
3147 memset(needs_dep
, true, write_len
);
3149 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3151 /* Walk backwards looking for writes to registers we're writing which
3152 * aren't read since being written. If we hit the start of the program,
3153 * we assume that there are no outstanding dependencies on entry to the
3156 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
3157 /* If we hit control flow, assume that there *are* outstanding
3158 * dependencies, and force their cleanup before our instruction.
3160 if (block
->start() == scan_inst
) {
3161 for (int i
= 0; i
< write_len
; i
++) {
3163 inst
->insert_before(block
, DEP_RESOLVE_MOV(first_write_grf
+ i
));
3169 /* We insert our reads as late as possible on the assumption that any
3170 * instruction but a MOV that might have left us an outstanding
3171 * dependency has more latency than a MOV.
3173 if (scan_inst
->dst
.file
== GRF
) {
3174 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
3175 int reg
= scan_inst
->dst
.reg
+ i
;
3177 if (reg
>= first_write_grf
&&
3178 reg
< first_write_grf
+ write_len
&&
3179 needs_dep
[reg
- first_write_grf
]) {
3180 inst
->insert_before(block
, DEP_RESOLVE_MOV(reg
));
3181 needs_dep
[reg
- first_write_grf
] = false;
3182 if (scan_inst
->exec_size
== 16)
3183 needs_dep
[reg
- first_write_grf
+ 1] = false;
3188 /* Clear the flag for registers that actually got read (as expected). */
3189 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3191 /* Continue the loop only if we haven't resolved all the dependencies */
3193 for (i
= 0; i
< write_len
; i
++) {
3203 * Implements this workaround for the original 965:
3205 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3206 * used as a destination register until after it has been sourced by an
3207 * instruction with a different destination register.
3210 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3212 int write_len
= inst
->regs_written
;
3213 int first_write_grf
= inst
->dst
.reg
;
3214 bool needs_dep
[BRW_MAX_MRF
];
3215 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3217 memset(needs_dep
, false, sizeof(needs_dep
));
3218 memset(needs_dep
, true, write_len
);
3219 /* Walk forwards looking for writes to registers we're writing which aren't
3220 * read before being written.
3222 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
, block
) {
3223 /* If we hit control flow, force resolve all remaining dependencies. */
3224 if (block
->end() == scan_inst
) {
3225 for (int i
= 0; i
< write_len
; i
++) {
3227 scan_inst
->insert_before(block
,
3228 DEP_RESOLVE_MOV(first_write_grf
+ i
));
3233 /* Clear the flag for registers that actually got read (as expected). */
3234 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3236 /* We insert our reads as late as possible since they're reading the
3237 * result of a SEND, which has massive latency.
3239 if (scan_inst
->dst
.file
== GRF
&&
3240 scan_inst
->dst
.reg
>= first_write_grf
&&
3241 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
3242 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
3243 scan_inst
->insert_before(block
, DEP_RESOLVE_MOV(scan_inst
->dst
.reg
));
3244 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
3247 /* Continue the loop only if we haven't resolved all the dependencies */
3249 for (i
= 0; i
< write_len
; i
++) {
3259 fs_visitor::insert_gen4_send_dependency_workarounds()
3261 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3264 bool progress
= false;
3266 /* Note that we're done with register allocation, so GRF fs_regs always
3267 * have a .reg_offset of 0.
3270 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3271 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
3272 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3273 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3279 invalidate_live_intervals();
3283 * Turns the generic expression-style uniform pull constant load instruction
3284 * into a hardware-specific series of instructions for loading a pull
3287 * The expression style allows the CSE pass before this to optimize out
3288 * repeated loads from the same offset, and gives the pre-register-allocation
3289 * scheduling full flexibility, while the conversion to native instructions
3290 * allows the post-register-allocation scheduler the best information
3293 * Note that execution masking for setting up pull constant loads is special:
3294 * the channels that need to be written are unrelated to the current execution
3295 * mask, since a later instruction will use one of the result channels as a
3296 * source operand for all 8 or 16 of its channels.
3299 fs_visitor::lower_uniform_pull_constant_loads()
3301 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3302 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3305 if (devinfo
->gen
>= 7) {
3306 /* The offset arg before was a vec4-aligned byte offset. We need to
3307 * turn it into a dword offset.
3309 fs_reg const_offset_reg
= inst
->src
[1];
3310 assert(const_offset_reg
.file
== IMM
&&
3311 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3312 const_offset_reg
.fixed_hw_reg
.dw1
.ud
/= 4;
3313 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1));
3315 /* We have to use a message header on Skylake to get SIMD4x2 mode.
3316 * Reserve space for the register.
3318 if (devinfo
->gen
>= 9) {
3319 payload
.reg_offset
++;
3320 alloc
.sizes
[payload
.reg
] = 2;
3323 /* This is actually going to be a MOV, but since only the first dword
3324 * is accessed, we have a special opcode to do just that one. Note
3325 * that this needs to be an operation that will be considered a def
3326 * by live variable analysis, or register allocation will explode.
3328 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3329 8, payload
, const_offset_reg
);
3330 setup
->force_writemask_all
= true;
3332 setup
->ir
= inst
->ir
;
3333 setup
->annotation
= inst
->annotation
;
3334 inst
->insert_before(block
, setup
);
3336 /* Similarly, this will only populate the first 4 channels of the
3337 * result register (since we only use smear values from 0-3), but we
3338 * don't tell the optimizer.
3340 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3341 inst
->src
[1] = payload
;
3343 invalidate_live_intervals();
3345 /* Before register allocation, we didn't tell the scheduler about the
3346 * MRF we use. We know it's safe to use this MRF because nothing
3347 * else does except for register spill/unspill, which generates and
3348 * uses its MRF within a single IR instruction.
3350 inst
->base_mrf
= 14;
3357 fs_visitor::lower_load_payload()
3359 bool progress
= false;
3361 int vgrf_to_reg
[alloc
.count
];
3363 for (unsigned i
= 0; i
< alloc
.count
; ++i
) {
3364 vgrf_to_reg
[i
] = reg_count
;
3365 reg_count
+= alloc
.sizes
[i
];
3369 bool written
:1; /* Whether this register has ever been written */
3370 bool force_writemask_all
:1;
3371 bool force_sechalf
:1;
3372 } metadata
[reg_count
];
3373 memset(metadata
, 0, sizeof(metadata
));
3375 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3376 if (inst
->dst
.file
== GRF
) {
3377 const int dst_reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
3378 bool force_sechalf
= inst
->force_sechalf
&&
3379 !inst
->force_writemask_all
;
3380 bool toggle_sechalf
= inst
->dst
.width
== 16 &&
3381 type_sz(inst
->dst
.type
) == 4 &&
3382 !inst
->force_writemask_all
;
3383 for (int i
= 0; i
< inst
->regs_written
; ++i
) {
3384 metadata
[dst_reg
+ i
].written
= true;
3385 metadata
[dst_reg
+ i
].force_sechalf
= force_sechalf
;
3386 metadata
[dst_reg
+ i
].force_writemask_all
= inst
->force_writemask_all
;
3387 force_sechalf
= (toggle_sechalf
!= force_sechalf
);
3391 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
3392 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== GRF
);
3393 fs_reg dst
= inst
->dst
;
3395 for (int i
= 0; i
< inst
->sources
; i
++) {
3396 dst
.width
= inst
->src
[i
].effective_width
;
3397 dst
.type
= inst
->src
[i
].type
;
3399 if (inst
->src
[i
].file
== BAD_FILE
) {
3400 /* Do nothing but otherwise increment as normal */
3401 } else if (dst
.file
== MRF
&&
3403 devinfo
->has_compr4
&&
3404 i
+ 4 < inst
->sources
&&
3405 inst
->src
[i
+ 4].equals(horiz_offset(inst
->src
[i
], 8))) {
3406 fs_reg compr4_dst
= dst
;
3407 compr4_dst
.reg
+= BRW_MRF_COMPR4
;
3408 compr4_dst
.width
= 16;
3409 fs_reg compr4_src
= inst
->src
[i
];
3410 compr4_src
.width
= 16;
3411 fs_inst
*mov
= MOV(compr4_dst
, compr4_src
);
3412 mov
->force_writemask_all
= true;
3413 inst
->insert_before(block
, mov
);
3414 /* Mark i+4 as BAD_FILE so we don't emit a MOV for it */
3415 inst
->src
[i
+ 4].file
= BAD_FILE
;
3417 fs_inst
*mov
= MOV(dst
, inst
->src
[i
]);
3418 if (inst
->src
[i
].file
== GRF
) {
3419 int src_reg
= vgrf_to_reg
[inst
->src
[i
].reg
] +
3420 inst
->src
[i
].reg_offset
;
3421 mov
->force_sechalf
= metadata
[src_reg
].force_sechalf
;
3422 mov
->force_writemask_all
= metadata
[src_reg
].force_writemask_all
;
3424 /* We don't have any useful metadata for immediates or
3425 * uniforms. Assume that any of the channels of the
3426 * destination may be used.
3428 assert(inst
->src
[i
].file
== IMM
||
3429 inst
->src
[i
].file
== UNIFORM
);
3430 mov
->force_writemask_all
= true;
3433 if (dst
.file
== GRF
) {
3434 const int dst_reg
= vgrf_to_reg
[dst
.reg
] + dst
.reg_offset
;
3435 const bool force_writemask
= mov
->force_writemask_all
;
3436 metadata
[dst_reg
].force_writemask_all
= force_writemask
;
3437 metadata
[dst_reg
].force_sechalf
= mov
->force_sechalf
;
3438 if (dst
.width
* type_sz(dst
.type
) > 32) {
3439 assert(!mov
->force_sechalf
);
3440 metadata
[dst_reg
+ 1].force_writemask_all
= force_writemask
;
3441 metadata
[dst_reg
+ 1].force_sechalf
= !force_writemask
;
3445 inst
->insert_before(block
, mov
);
3448 dst
= offset(dst
, 1);
3451 inst
->remove(block
);
3457 invalidate_live_intervals();
3463 fs_visitor::dump_instructions()
3465 dump_instructions(NULL
);
3469 fs_visitor::dump_instructions(const char *name
)
3471 FILE *file
= stderr
;
3472 if (name
&& geteuid() != 0) {
3473 file
= fopen(name
, "w");
3479 calculate_register_pressure();
3480 int ip
= 0, max_pressure
= 0;
3481 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
3482 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
3483 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
3484 dump_instruction(inst
, file
);
3487 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
3490 foreach_in_list(backend_instruction
, inst
, &instructions
) {
3491 fprintf(file
, "%4d: ", ip
++);
3492 dump_instruction(inst
, file
);
3496 if (file
!= stderr
) {
3502 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
3504 dump_instruction(be_inst
, stderr
);
3508 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
3510 fs_inst
*inst
= (fs_inst
*)be_inst
;
3512 if (inst
->predicate
) {
3513 fprintf(file
, "(%cf0.%d) ",
3514 inst
->predicate_inverse
? '-' : '+',
3518 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
3520 fprintf(file
, ".sat");
3521 if (inst
->conditional_mod
) {
3522 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
3523 if (!inst
->predicate
&&
3524 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
3525 inst
->opcode
!= BRW_OPCODE_IF
&&
3526 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
3527 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
3530 fprintf(file
, "(%d) ", inst
->exec_size
);
3533 switch (inst
->dst
.file
) {
3535 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
3536 if (inst
->dst
.width
!= dispatch_width
)
3537 fprintf(file
, "@%d", inst
->dst
.width
);
3538 if (alloc
.sizes
[inst
->dst
.reg
] != inst
->dst
.width
/ 8 ||
3539 inst
->dst
.subreg_offset
)
3540 fprintf(file
, "+%d.%d",
3541 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
3544 fprintf(file
, "m%d", inst
->dst
.reg
);
3547 fprintf(file
, "(null)");
3550 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
3553 fprintf(file
, "***attr%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
3556 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3557 switch (inst
->dst
.fixed_hw_reg
.nr
) {
3559 fprintf(file
, "null");
3561 case BRW_ARF_ADDRESS
:
3562 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
3564 case BRW_ARF_ACCUMULATOR
:
3565 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
3568 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3569 inst
->dst
.fixed_hw_reg
.subnr
);
3572 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3573 inst
->dst
.fixed_hw_reg
.subnr
);
3577 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
3579 if (inst
->dst
.fixed_hw_reg
.subnr
)
3580 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
3583 fprintf(file
, "???");
3586 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
3588 for (int i
= 0; i
< inst
->sources
; i
++) {
3589 if (inst
->src
[i
].negate
)
3591 if (inst
->src
[i
].abs
)
3593 switch (inst
->src
[i
].file
) {
3595 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
3596 if (inst
->src
[i
].width
!= dispatch_width
)
3597 fprintf(file
, "@%d", inst
->src
[i
].width
);
3598 if (alloc
.sizes
[inst
->src
[i
].reg
] != inst
->src
[i
].width
/ 8 ||
3599 inst
->src
[i
].subreg_offset
)
3600 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
3601 inst
->src
[i
].subreg_offset
);
3604 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
3607 fprintf(file
, "attr%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
3610 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
3611 if (inst
->src
[i
].reladdr
) {
3612 fprintf(file
, "+reladdr");
3613 } else if (inst
->src
[i
].subreg_offset
) {
3614 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
3615 inst
->src
[i
].subreg_offset
);
3619 fprintf(file
, "(null)");
3622 switch (inst
->src
[i
].type
) {
3623 case BRW_REGISTER_TYPE_F
:
3624 fprintf(file
, "%ff", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
3626 case BRW_REGISTER_TYPE_W
:
3627 case BRW_REGISTER_TYPE_D
:
3628 fprintf(file
, "%dd", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
3630 case BRW_REGISTER_TYPE_UW
:
3631 case BRW_REGISTER_TYPE_UD
:
3632 fprintf(file
, "%uu", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
3634 case BRW_REGISTER_TYPE_VF
:
3635 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
3636 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
3637 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
3638 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
3639 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
3642 fprintf(file
, "???");
3647 if (inst
->src
[i
].fixed_hw_reg
.negate
)
3649 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3651 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3652 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
3654 fprintf(file
, "null");
3656 case BRW_ARF_ADDRESS
:
3657 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3659 case BRW_ARF_ACCUMULATOR
:
3660 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3663 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3664 inst
->src
[i
].fixed_hw_reg
.subnr
);
3667 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3668 inst
->src
[i
].fixed_hw_reg
.subnr
);
3672 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
3674 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
3675 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3676 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3680 fprintf(file
, "???");
3683 if (inst
->src
[i
].abs
)
3686 if (inst
->src
[i
].file
!= IMM
) {
3687 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
3690 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
3691 fprintf(file
, ", ");
3696 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
3697 if (inst
->force_sechalf
)
3698 fprintf(file
, "2ndhalf ");
3700 fprintf(file
, "1sthalf ");
3703 fprintf(file
, "\n");
3707 * Possibly returns an instruction that set up @param reg.
3709 * Sometimes we want to take the result of some expression/variable
3710 * dereference tree and rewrite the instruction generating the result
3711 * of the tree. When processing the tree, we know that the
3712 * instructions generated are all writing temporaries that are dead
3713 * outside of this tree. So, if we have some instructions that write
3714 * a temporary, we're free to point that temp write somewhere else.
3716 * Note that this doesn't guarantee that the instruction generated
3717 * only reg -- it might be the size=4 destination of a texture instruction.
3720 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
3725 end
->is_partial_write() ||
3727 !reg
.equals(end
->dst
)) {
3735 fs_visitor::setup_payload_gen6()
3738 (prog
->InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
3739 unsigned barycentric_interp_modes
=
3740 (stage
== MESA_SHADER_FRAGMENT
) ?
3741 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
3743 assert(devinfo
->gen
>= 6);
3745 /* R0-1: masks, pixel X/Y coordinates. */
3746 payload
.num_regs
= 2;
3747 /* R2: only for 32-pixel dispatch.*/
3749 /* R3-26: barycentric interpolation coordinates. These appear in the
3750 * same order that they appear in the brw_wm_barycentric_interp_mode
3751 * enum. Each set of coordinates occupies 2 registers if dispatch width
3752 * == 8 and 4 registers if dispatch width == 16. Coordinates only
3753 * appear if they were enabled using the "Barycentric Interpolation
3754 * Mode" bits in WM_STATE.
3756 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
3757 if (barycentric_interp_modes
& (1 << i
)) {
3758 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
3759 payload
.num_regs
+= 2;
3760 if (dispatch_width
== 16) {
3761 payload
.num_regs
+= 2;
3766 /* R27: interpolated depth if uses source depth */
3768 payload
.source_depth_reg
= payload
.num_regs
;
3770 if (dispatch_width
== 16) {
3771 /* R28: interpolated depth if not SIMD8. */
3775 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
3777 payload
.source_w_reg
= payload
.num_regs
;
3779 if (dispatch_width
== 16) {
3780 /* R30: interpolated W if not SIMD8. */
3785 if (stage
== MESA_SHADER_FRAGMENT
) {
3786 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3787 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3788 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
3789 /* R31: MSAA position offsets. */
3790 if (prog_data
->uses_pos_offset
) {
3791 payload
.sample_pos_reg
= payload
.num_regs
;
3796 /* R32: MSAA input coverage mask */
3797 if (prog
->SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
3798 assert(devinfo
->gen
>= 7);
3799 payload
.sample_mask_in_reg
= payload
.num_regs
;
3801 if (dispatch_width
== 16) {
3802 /* R33: input coverage mask if not SIMD8. */
3807 /* R34-: bary for 32-pixel. */
3808 /* R58-59: interp W for 32-pixel. */
3810 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3811 source_depth_to_render_target
= true;
3816 fs_visitor::setup_vs_payload()
3818 /* R0: thread header, R1: urb handles */
3819 payload
.num_regs
= 2;
3823 fs_visitor::setup_cs_payload()
3825 assert(brw
->gen
>= 7);
3827 payload
.num_regs
= 1;
3831 fs_visitor::assign_binding_table_offsets()
3833 assert(stage
== MESA_SHADER_FRAGMENT
);
3834 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3835 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3836 uint32_t next_binding_table_offset
= 0;
3838 /* If there are no color regions, we still perform an FB write to a null
3839 * renderbuffer, which we place at surface index 0.
3841 prog_data
->binding_table
.render_target_start
= next_binding_table_offset
;
3842 next_binding_table_offset
+= MAX2(key
->nr_color_regions
, 1);
3844 assign_common_binding_table_offsets(next_binding_table_offset
);
3848 fs_visitor::calculate_register_pressure()
3850 invalidate_live_intervals();
3851 calculate_live_intervals();
3853 unsigned num_instructions
= 0;
3854 foreach_block(block
, cfg
)
3855 num_instructions
+= block
->instructions
.length();
3857 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
3859 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
3860 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
3861 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
3866 fs_visitor::optimize()
3868 split_virtual_grfs();
3870 move_uniform_array_access_to_pull_constants();
3871 assign_constant_locations();
3872 demote_pull_constants();
3874 #define OPT(pass, args...) ({ \
3876 bool this_progress = pass(args); \
3878 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
3879 char filename[64]; \
3880 snprintf(filename, 64, "%s%d-%04d-%02d-%02d-" #pass, \
3881 stage_abbrev, dispatch_width, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
3883 backend_visitor::dump_instructions(filename); \
3886 progress = progress || this_progress; \
3890 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
3892 snprintf(filename
, 64, "%s%d-%04d-00-start",
3893 stage_abbrev
, dispatch_width
,
3894 shader_prog
? shader_prog
->Name
: 0);
3896 backend_visitor::dump_instructions(filename
);
3907 OPT(remove_duplicate_mrf_writes
);
3911 OPT(opt_copy_propagate
);
3912 OPT(opt_peephole_predicated_break
);
3913 OPT(opt_cmod_propagation
);
3914 OPT(dead_code_eliminate
);
3915 OPT(opt_peephole_sel
);
3916 OPT(dead_control_flow_eliminate
, this);
3917 OPT(opt_register_renaming
);
3918 OPT(opt_redundant_discard_jumps
);
3919 OPT(opt_saturate_propagation
);
3920 OPT(opt_zero_samples
);
3921 OPT(register_coalesce
);
3922 OPT(compute_to_mrf
);
3924 OPT(compact_virtual_grfs
);
3929 OPT(opt_sampler_eot
);
3931 if (OPT(lower_load_payload
)) {
3932 split_virtual_grfs();
3933 OPT(register_coalesce
);
3934 OPT(compute_to_mrf
);
3935 OPT(dead_code_eliminate
);
3938 OPT(opt_combine_constants
);
3940 lower_uniform_pull_constant_loads();
3944 * Three source instruction must have a GRF/MRF destination register.
3945 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
3948 fs_visitor::fixup_3src_null_dest()
3950 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3951 if (inst
->is_3src() && inst
->dst
.is_null()) {
3952 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
3959 fs_visitor::allocate_registers()
3961 bool allocated_without_spills
;
3963 static const enum instruction_scheduler_mode pre_modes
[] = {
3965 SCHEDULE_PRE_NON_LIFO
,
3969 /* Try each scheduling heuristic to see if it can successfully register
3970 * allocate without spilling. They should be ordered by decreasing
3971 * performance but increasing likelihood of allocating.
3973 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
3974 schedule_instructions(pre_modes
[i
]);
3977 assign_regs_trivial();
3978 allocated_without_spills
= true;
3980 allocated_without_spills
= assign_regs(false);
3982 if (allocated_without_spills
)
3986 if (!allocated_without_spills
) {
3987 /* We assume that any spilling is worse than just dropping back to
3988 * SIMD8. There's probably actually some intermediate point where
3989 * SIMD16 with a couple of spills is still better.
3991 if (dispatch_width
== 16) {
3992 fail("Failure to register allocate. Reduce number of "
3993 "live scalar values to avoid this.");
3995 perf_debug("%s shader triggered register spilling. "
3996 "Try reducing the number of live scalar values to "
3997 "improve performance.\n", stage_name
);
4000 /* Since we're out of heuristics, just go spill registers until we
4001 * get an allocation.
4003 while (!assign_regs(true)) {
4009 /* This must come after all optimization and register allocation, since
4010 * it inserts dead code that happens to have side effects, and it does
4011 * so based on the actual physical registers in use.
4013 insert_gen4_send_dependency_workarounds();
4018 if (!allocated_without_spills
)
4019 schedule_instructions(SCHEDULE_POST
);
4021 if (last_scratch
> 0)
4022 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
4026 fs_visitor::run_vs()
4028 assert(stage
== MESA_SHADER_VERTEX
);
4030 assign_common_binding_table_offsets(0);
4033 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
4034 emit_shader_time_begin();
4036 if (brw
->ctx
.Const
.ShaderCompilerOptions
[MESA_SHADER_VERTEX
].NirOptions
) {
4039 foreach_in_list(ir_instruction
, ir
, shader
->base
.ir
) {
4041 this->result
= reg_undef
;
4052 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
4053 emit_shader_time_end();
4059 assign_curb_setup();
4060 assign_vs_urb_setup();
4062 fixup_3src_null_dest();
4063 allocate_registers();
4069 fs_visitor::run_fs()
4071 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4072 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
4074 assert(stage
== MESA_SHADER_FRAGMENT
);
4076 sanity_param_count
= prog
->Parameters
->NumParameters
;
4078 assign_binding_table_offsets();
4080 if (devinfo
->gen
>= 6)
4081 setup_payload_gen6();
4083 setup_payload_gen4();
4087 } else if (brw
->use_rep_send
&& dispatch_width
== 16) {
4088 emit_repclear_shader();
4090 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
4091 emit_shader_time_begin();
4093 calculate_urb_setup();
4094 if (prog
->InputsRead
> 0) {
4095 if (devinfo
->gen
< 6)
4096 emit_interpolation_setup_gen4();
4098 emit_interpolation_setup_gen6();
4101 /* We handle discards by keeping track of the still-live pixels in f0.1.
4102 * Initialize it with the dispatched pixels.
4104 if (wm_prog_data
->uses_kill
) {
4105 fs_inst
*discard_init
= emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
4106 discard_init
->flag_subreg
= 1;
4109 /* Generate FS IR for main(). (the visitor only descends into
4110 * functions called "main").
4112 if (brw
->ctx
.Const
.ShaderCompilerOptions
[MESA_SHADER_FRAGMENT
].NirOptions
) {
4114 } else if (shader
) {
4115 foreach_in_list(ir_instruction
, ir
, shader
->base
.ir
) {
4117 this->result
= reg_undef
;
4121 emit_fragment_program_code();
4127 if (wm_prog_data
->uses_kill
)
4128 emit(FS_OPCODE_PLACEHOLDER_HALT
);
4130 if (wm_key
->alpha_test_func
)
4135 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
4136 emit_shader_time_end();
4142 assign_curb_setup();
4145 fixup_3src_null_dest();
4146 allocate_registers();
4152 if (dispatch_width
== 8)
4153 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
4155 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
4157 /* If any state parameters were appended, then ParameterValues could have
4158 * been realloced, in which case the driver uniform storage set up by
4159 * _mesa_associate_uniform_storage() would point to freed memory. Make
4160 * sure that didn't happen.
4162 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
4168 fs_visitor::run_cs()
4170 assert(stage
== MESA_SHADER_COMPUTE
);
4173 sanity_param_count
= prog
->Parameters
->NumParameters
;
4175 assign_common_binding_table_offsets(0);
4179 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
4180 emit_shader_time_begin();
4187 emit_cs_terminate();
4189 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
4190 emit_shader_time_end();
4196 assign_curb_setup();
4198 fixup_3src_null_dest();
4199 allocate_registers();
4204 /* If any state parameters were appended, then ParameterValues could have
4205 * been realloced, in which case the driver uniform storage set up by
4206 * _mesa_associate_uniform_storage() would point to freed memory. Make
4207 * sure that didn't happen.
4209 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
4215 brw_wm_fs_emit(struct brw_context
*brw
,
4217 const struct brw_wm_prog_key
*key
,
4218 struct brw_wm_prog_data
*prog_data
,
4219 struct gl_fragment_program
*fp
,
4220 struct gl_shader_program
*prog
,
4221 unsigned *final_assembly_size
)
4223 bool start_busy
= false;
4224 double start_time
= 0;
4226 if (unlikely(brw
->perf_debug
)) {
4227 start_busy
= (brw
->batch
.last_bo
&&
4228 drm_intel_bo_busy(brw
->batch
.last_bo
));
4229 start_time
= get_time();
4232 struct brw_shader
*shader
= NULL
;
4234 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
4236 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
4237 brw_dump_ir("fragment", prog
, &shader
->base
, &fp
->Base
);
4239 /* Now the main event: Visit the shader IR and generate our FS IR for it.
4241 fs_visitor
v(brw
, mem_ctx
, key
, prog_data
, prog
, fp
, 8);
4244 prog
->LinkStatus
= false;
4245 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
4248 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
4254 cfg_t
*simd16_cfg
= NULL
;
4255 fs_visitor
v2(brw
, mem_ctx
, key
, prog_data
, prog
, fp
, 16);
4256 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || brw
->use_rep_send
)) {
4257 if (!v
.simd16_unsupported
) {
4258 /* Try a SIMD16 compile */
4259 v2
.import_uniforms(&v
);
4261 perf_debug("SIMD16 shader failed to compile, falling back to "
4262 "SIMD8 at a 10-20%% performance cost: %s", v2
.fail_msg
);
4264 simd16_cfg
= v2
.cfg
;
4267 perf_debug("SIMD16 shader unsupported, falling back to "
4268 "SIMD8 at a 10-20%% performance cost: %s", v
.no16_msg
);
4273 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || brw
->no_simd8
;
4274 if ((no_simd8
|| brw
->gen
< 5) && simd16_cfg
) {
4276 prog_data
->no_8
= true;
4279 prog_data
->no_8
= false;
4282 fs_generator
g(brw
, mem_ctx
, (void *) key
, &prog_data
->base
,
4283 &fp
->Base
, v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
4285 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
4288 name
= ralloc_asprintf(mem_ctx
, "%s fragment shader %d",
4289 prog
->Label
? prog
->Label
: "unnamed",
4292 name
= ralloc_asprintf(mem_ctx
, "fragment program %d", fp
->Base
.Id
);
4294 g
.enable_debug(name
);
4298 g
.generate_code(simd8_cfg
, 8);
4300 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
4302 if (unlikely(brw
->perf_debug
) && shader
) {
4303 if (shader
->compiled_once
)
4304 brw_wm_debug_recompile(brw
, prog
, key
);
4305 shader
->compiled_once
= true;
4307 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
4308 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
4309 (get_time() - start_time
) * 1000);
4313 return g
.get_assembly(final_assembly_size
);
4317 brw_fs_precompile(struct gl_context
*ctx
,
4318 struct gl_shader_program
*shader_prog
,
4319 struct gl_program
*prog
)
4321 struct brw_context
*brw
= brw_context(ctx
);
4322 struct brw_wm_prog_key key
;
4324 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*) prog
;
4325 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
4326 bool program_uses_dfdy
= fp
->UsesDFdy
;
4328 memset(&key
, 0, sizeof(key
));
4332 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
4334 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
4335 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
4337 /* Just assume depth testing. */
4338 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
4339 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
4342 if (brw
->gen
< 6 || _mesa_bitcount_64(fp
->Base
.InputsRead
&
4343 BRW_FS_VARYING_INPUT_MASK
) > 16)
4344 key
.input_slots_valid
= fp
->Base
.InputsRead
| VARYING_BIT_POS
;
4346 brw_setup_tex_for_precompile(brw
, &key
.tex
, &fp
->Base
);
4348 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
) {
4349 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
4352 key
.nr_color_regions
= _mesa_bitcount_64(fp
->Base
.OutputsWritten
&
4353 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
4354 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
)));
4356 if ((fp
->Base
.InputsRead
& VARYING_BIT_POS
) || program_uses_dfdy
) {
4357 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
) ||
4358 key
.nr_color_regions
> 1;
4361 key
.program_string_id
= bfp
->id
;
4363 uint32_t old_prog_offset
= brw
->wm
.base
.prog_offset
;
4364 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
4366 bool success
= brw_codegen_wm_prog(brw
, shader_prog
, bfp
, &key
);
4368 brw
->wm
.base
.prog_offset
= old_prog_offset
;
4369 brw
->wm
.prog_data
= old_prog_data
;
4375 brw_setup_tex_for_precompile(struct brw_context
*brw
,
4376 struct brw_sampler_prog_key_data
*tex
,
4377 struct gl_program
*prog
)
4379 const bool has_shader_channel_select
= brw
->is_haswell
|| brw
->gen
>= 8;
4380 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
4381 for (unsigned i
= 0; i
< sampler_count
; i
++) {
4382 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
4383 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
4385 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
4387 /* Color sampler: assume no swizzling. */
4388 tex
->swizzles
[i
] = SWIZZLE_XYZW
;