2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "main/macros.h"
36 #include "main/shaderobj.h"
37 #include "main/uniforms.h"
38 #include "program/prog_parameter.h"
39 #include "program/prog_print.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
47 #include "brw_shader.h"
49 #include "glsl/glsl_types.h"
50 #include "glsl/ir_print_visitor.h"
52 #define MAX_INSTRUCTION (1 << 30)
55 fs_visitor::type_size(const struct glsl_type
*type
)
59 switch (type
->base_type
) {
64 return type
->components();
66 return type_size(type
->fields
.array
) * type
->length
;
67 case GLSL_TYPE_STRUCT
:
69 for (i
= 0; i
< type
->length
; i
++) {
70 size
+= type_size(type
->fields
.structure
[i
].type
);
73 case GLSL_TYPE_SAMPLER
:
74 /* Samplers take up no register space, since they're baked in at
79 assert(!"not reached");
85 fs_visitor::fail(const char *format
, ...)
96 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
98 msg
= ralloc_asprintf(mem_ctx
, "FS compile failed: %s\n", msg
);
100 this->fail_msg
= msg
;
102 if (INTEL_DEBUG
& DEBUG_WM
) {
103 fprintf(stderr
, "%s", msg
);
108 fs_visitor::push_force_uncompressed()
110 force_uncompressed_stack
++;
114 fs_visitor::pop_force_uncompressed()
116 force_uncompressed_stack
--;
117 assert(force_uncompressed_stack
>= 0);
121 fs_visitor::push_force_sechalf()
123 force_sechalf_stack
++;
127 fs_visitor::pop_force_sechalf()
129 force_sechalf_stack
--;
130 assert(force_sechalf_stack
>= 0);
134 * Returns how many MRFs an FS opcode will write over.
136 * Note that this is not the 0 or 1 implied writes in an actual gen
137 * instruction -- the FS opcodes often generate MOVs in addition.
140 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
145 switch (inst
->opcode
) {
146 case SHADER_OPCODE_RCP
:
147 case SHADER_OPCODE_RSQ
:
148 case SHADER_OPCODE_SQRT
:
149 case SHADER_OPCODE_EXP2
:
150 case SHADER_OPCODE_LOG2
:
151 case SHADER_OPCODE_SIN
:
152 case SHADER_OPCODE_COS
:
153 return 1 * c
->dispatch_width
/ 8;
154 case SHADER_OPCODE_POW
:
155 case SHADER_OPCODE_INT_QUOTIENT
:
156 case SHADER_OPCODE_INT_REMAINDER
:
157 return 2 * c
->dispatch_width
/ 8;
165 case FS_OPCODE_FB_WRITE
:
167 case FS_OPCODE_PULL_CONSTANT_LOAD
:
168 case FS_OPCODE_UNSPILL
:
170 case FS_OPCODE_SPILL
:
173 assert(!"not reached");
179 fs_visitor::virtual_grf_alloc(int size
)
181 if (virtual_grf_array_size
<= virtual_grf_next
) {
182 if (virtual_grf_array_size
== 0)
183 virtual_grf_array_size
= 16;
185 virtual_grf_array_size
*= 2;
186 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
187 virtual_grf_array_size
);
189 virtual_grf_sizes
[virtual_grf_next
] = size
;
190 return virtual_grf_next
++;
193 /** Fixed HW reg constructor. */
194 fs_reg::fs_reg(enum register_file file
, int reg
)
199 this->type
= BRW_REGISTER_TYPE_F
;
202 /** Fixed HW reg constructor. */
203 fs_reg::fs_reg(enum register_file file
, int reg
, uint32_t type
)
211 /** Automatic reg constructor. */
212 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
217 this->reg
= v
->virtual_grf_alloc(v
->type_size(type
));
218 this->reg_offset
= 0;
219 this->type
= brw_type_for_base_type(type
);
223 fs_visitor::variable_storage(ir_variable
*var
)
225 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
229 import_uniforms_callback(const void *key
,
233 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
234 const fs_reg
*reg
= (const fs_reg
*)data
;
236 if (reg
->file
!= UNIFORM
)
239 hash_table_insert(dst_ht
, data
, key
);
242 /* For 16-wide, we need to follow from the uniform setup of 8-wide dispatch.
243 * This brings in those uniform definitions
246 fs_visitor::import_uniforms(fs_visitor
*v
)
248 hash_table_call_foreach(v
->variable_ht
,
249 import_uniforms_callback
,
251 this->params_remap
= v
->params_remap
;
254 /* Our support for uniforms is piggy-backed on the struct
255 * gl_fragment_program, because that's where the values actually
256 * get stored, rather than in some global gl_shader_program uniform
260 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
262 unsigned int offset
= 0;
264 if (type
->is_matrix()) {
265 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
266 type
->vector_elements
,
269 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
270 offset
+= setup_uniform_values(loc
+ offset
, column
);
276 switch (type
->base_type
) {
277 case GLSL_TYPE_FLOAT
:
281 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
282 unsigned int param
= c
->prog_data
.nr_params
++;
284 assert(param
< ARRAY_SIZE(c
->prog_data
.param
));
286 if (ctx
->Const
.NativeIntegers
) {
287 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
289 switch (type
->base_type
) {
290 case GLSL_TYPE_FLOAT
:
291 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
294 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2U
;
297 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2I
;
300 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2B
;
303 assert(!"not reached");
304 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
308 this->param_index
[param
] = loc
;
309 this->param_offset
[param
] = i
;
313 case GLSL_TYPE_STRUCT
:
314 for (unsigned int i
= 0; i
< type
->length
; i
++) {
315 offset
+= setup_uniform_values(loc
+ offset
,
316 type
->fields
.structure
[i
].type
);
320 case GLSL_TYPE_ARRAY
:
321 for (unsigned int i
= 0; i
< type
->length
; i
++) {
322 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
326 case GLSL_TYPE_SAMPLER
:
327 /* The sampler takes up a slot, but we don't use any values from it. */
331 assert(!"not reached");
337 /* Our support for builtin uniforms is even scarier than non-builtin.
338 * It sits on top of the PROG_STATE_VAR parameters that are
339 * automatically updated from GL context state.
342 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
344 const ir_state_slot
*const slots
= ir
->state_slots
;
345 assert(ir
->state_slots
!= NULL
);
347 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
348 /* This state reference has already been setup by ir_to_mesa, but we'll
349 * get the same index back here.
351 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
352 (gl_state_index
*)slots
[i
].tokens
);
354 /* Add each of the unique swizzles of the element as a parameter.
355 * This'll end up matching the expected layout of the
356 * array/matrix/structure we're trying to fill in.
359 for (unsigned int j
= 0; j
< 4; j
++) {
360 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
361 if (swiz
== last_swiz
)
365 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
367 this->param_index
[c
->prog_data
.nr_params
] = index
;
368 this->param_offset
[c
->prog_data
.nr_params
] = swiz
;
369 c
->prog_data
.nr_params
++;
375 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
377 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
379 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
382 if (ir
->pixel_center_integer
) {
383 emit(BRW_OPCODE_MOV
, wpos
, this->pixel_x
);
385 emit(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
));
390 if (!flip
&& ir
->pixel_center_integer
) {
391 emit(BRW_OPCODE_MOV
, wpos
, this->pixel_y
);
393 fs_reg pixel_y
= this->pixel_y
;
394 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
397 pixel_y
.negate
= true;
398 offset
+= c
->key
.drawable_height
- 1.0;
401 emit(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
));
406 if (intel
->gen
>= 6) {
407 emit(BRW_OPCODE_MOV
, wpos
,
408 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0)));
410 emit(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
411 interp_reg(FRAG_ATTRIB_WPOS
, 2));
415 /* gl_FragCoord.w: Already set up in emit_interpolation */
416 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
422 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
424 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
425 /* Interpolation is always in floating point regs. */
426 reg
->type
= BRW_REGISTER_TYPE_F
;
429 unsigned int array_elements
;
430 const glsl_type
*type
;
432 if (ir
->type
->is_array()) {
433 array_elements
= ir
->type
->length
;
434 if (array_elements
== 0) {
435 fail("dereferenced array '%s' has length 0\n", ir
->name
);
437 type
= ir
->type
->fields
.array
;
443 int location
= ir
->location
;
444 for (unsigned int i
= 0; i
< array_elements
; i
++) {
445 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
446 if (urb_setup
[location
] == -1) {
447 /* If there's no incoming setup data for this slot, don't
448 * emit interpolation for it.
450 attr
.reg_offset
+= type
->vector_elements
;
456 location
== FRAG_ATTRIB_COL0
|| location
== FRAG_ATTRIB_COL1
;
458 if (c
->key
.flat_shade
&& is_gl_Color
) {
459 /* Constant interpolation (flat shading) case. The SF has
460 * handed us defined values in only the constant offset
461 * field of the setup reg.
463 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
464 struct brw_reg interp
= interp_reg(location
, k
);
465 interp
= suboffset(interp
, 3);
466 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
470 /* Perspective interpolation case. */
471 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
472 /* FINISHME: At some point we probably want to push
473 * this farther by giving similar treatment to the
474 * other potentially constant components of the
475 * attribute, as well as making brw_vs_constval.c
476 * handle varyings other than gl_TexCoord.
478 if (location
>= FRAG_ATTRIB_TEX0
&&
479 location
<= FRAG_ATTRIB_TEX7
&&
480 k
== 3 && !(c
->key
.proj_attrib_mask
& (1 << location
))) {
481 emit(BRW_OPCODE_MOV
, attr
, fs_reg(1.0f
));
483 struct brw_reg interp
= interp_reg(location
, k
);
484 emit(FS_OPCODE_LINTERP
, attr
,
485 this->delta_x
, this->delta_y
, fs_reg(interp
));
490 if (intel
->gen
< 6) {
491 attr
.reg_offset
-= type
->vector_elements
;
492 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
493 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
506 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
508 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
510 /* The frontfacing comes in as a bit in the thread payload. */
511 if (intel
->gen
>= 6) {
512 emit(BRW_OPCODE_ASR
, *reg
,
513 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
515 emit(BRW_OPCODE_NOT
, *reg
, *reg
);
516 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1));
518 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
519 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
522 fs_inst
*inst
= emit(BRW_OPCODE_CMP
, *reg
,
525 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
526 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u));
533 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src
)
536 case SHADER_OPCODE_RCP
:
537 case SHADER_OPCODE_RSQ
:
538 case SHADER_OPCODE_SQRT
:
539 case SHADER_OPCODE_EXP2
:
540 case SHADER_OPCODE_LOG2
:
541 case SHADER_OPCODE_SIN
:
542 case SHADER_OPCODE_COS
:
545 assert(!"not reached: bad math opcode");
549 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
550 * might be able to do better by doing execsize = 1 math and then
551 * expanding that result out, but we would need to be careful with
554 * The hardware ignores source modifiers (negate and abs) on math
555 * instructions, so we also move to a temp to set those up.
557 if (intel
->gen
>= 6 && (src
.file
== UNIFORM
||
560 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
561 emit(BRW_OPCODE_MOV
, expanded
, src
);
565 fs_inst
*inst
= emit(opcode
, dst
, src
);
567 if (intel
->gen
< 6) {
569 inst
->mlen
= c
->dispatch_width
/ 8;
576 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
582 case SHADER_OPCODE_POW
:
583 case SHADER_OPCODE_INT_QUOTIENT
:
584 case SHADER_OPCODE_INT_REMAINDER
:
587 assert(!"not reached: unsupported binary math opcode.");
591 if (intel
->gen
>= 6) {
592 /* Can't do hstride == 0 args to gen6 math, so expand it out.
594 * The hardware ignores source modifiers (negate and abs) on math
595 * instructions, so we also move to a temp to set those up.
597 if (src0
.file
== UNIFORM
|| src0
.abs
|| src0
.negate
) {
598 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
599 expanded
.type
= src0
.type
;
600 emit(BRW_OPCODE_MOV
, expanded
, src0
);
604 if (src1
.file
== UNIFORM
|| src1
.abs
|| src1
.negate
) {
605 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
606 expanded
.type
= src1
.type
;
607 emit(BRW_OPCODE_MOV
, expanded
, src1
);
611 inst
= emit(opcode
, dst
, src0
, src1
);
613 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
616 * "Operand0[7]. For the INT DIV functions, this operand is the
619 * "Operand1[7]. For the INT DIV functions, this operand is the
622 bool is_int_div
= opcode
!= SHADER_OPCODE_POW
;
623 fs_reg
&op0
= is_int_div
? src1
: src0
;
624 fs_reg
&op1
= is_int_div
? src0
: src1
;
626 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1, op1
.type
), op1
);
627 inst
= emit(opcode
, dst
, op0
, reg_null_f
);
629 inst
->base_mrf
= base_mrf
;
630 inst
->mlen
= 2 * c
->dispatch_width
/ 8;
636 * To be called after the last _mesa_add_state_reference() call, to
637 * set up prog_data.param[] for assign_curb_setup() and
638 * setup_pull_constants().
641 fs_visitor::setup_paramvalues_refs()
643 if (c
->dispatch_width
!= 8)
646 /* Set up the pointers to ParamValues now that that array is finalized. */
647 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
648 c
->prog_data
.param
[i
] =
649 (const float *)fp
->Base
.Parameters
->ParameterValues
[this->param_index
[i
]] +
650 this->param_offset
[i
];
655 fs_visitor::assign_curb_setup()
657 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
658 if (c
->dispatch_width
== 8) {
659 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
661 c
->prog_data
.first_curbe_grf_16
= c
->nr_payload_regs
;
664 /* Map the offsets in the UNIFORM file to fixed HW regs. */
665 foreach_list(node
, &this->instructions
) {
666 fs_inst
*inst
= (fs_inst
*)node
;
668 for (unsigned int i
= 0; i
< 3; i
++) {
669 if (inst
->src
[i
].file
== UNIFORM
) {
670 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
671 struct brw_reg brw_reg
= brw_vec1_grf(c
->nr_payload_regs
+
675 inst
->src
[i
].file
= FIXED_HW_REG
;
676 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
683 fs_visitor::calculate_urb_setup()
685 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
690 /* Figure out where each of the incoming setup attributes lands. */
691 if (intel
->gen
>= 6) {
692 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
693 if (fp
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
694 urb_setup
[i
] = urb_next
++;
698 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
699 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
700 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
701 int fp_index
= _mesa_vert_result_to_frag_attrib((gl_vert_result
) i
);
704 urb_setup
[fp_index
] = urb_next
++;
709 /* Each attribute is 4 setup channels, each of which is half a reg. */
710 c
->prog_data
.urb_read_length
= urb_next
* 2;
714 fs_visitor::assign_urb_setup()
716 int urb_start
= c
->nr_payload_regs
+ c
->prog_data
.curb_read_length
;
718 /* Offset all the urb_setup[] index by the actual position of the
719 * setup regs, now that the location of the constants has been chosen.
721 foreach_list(node
, &this->instructions
) {
722 fs_inst
*inst
= (fs_inst
*)node
;
724 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
725 assert(inst
->src
[2].file
== FIXED_HW_REG
);
726 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
729 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
730 assert(inst
->src
[0].file
== FIXED_HW_REG
);
731 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
735 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
739 * Split large virtual GRFs into separate components if we can.
741 * This is mostly duplicated with what brw_fs_vector_splitting does,
742 * but that's really conservative because it's afraid of doing
743 * splitting that doesn't result in real progress after the rest of
744 * the optimization phases, which would cause infinite looping in
745 * optimization. We can do it once here, safely. This also has the
746 * opportunity to split interpolated values, or maybe even uniforms,
747 * which we don't have at the IR level.
749 * We want to split, because virtual GRFs are what we register
750 * allocate and spill (due to contiguousness requirements for some
751 * instructions), and they're what we naturally generate in the
752 * codegen process, but most virtual GRFs don't actually need to be
753 * contiguous sets of GRFs. If we split, we'll end up with reduced
754 * live intervals and better dead code elimination and coalescing.
757 fs_visitor::split_virtual_grfs()
759 int num_vars
= this->virtual_grf_next
;
760 bool split_grf
[num_vars
];
761 int new_virtual_grf
[num_vars
];
763 /* Try to split anything > 0 sized. */
764 for (int i
= 0; i
< num_vars
; i
++) {
765 if (this->virtual_grf_sizes
[i
] != 1)
768 split_grf
[i
] = false;
772 /* PLN opcodes rely on the delta_xy being contiguous. */
773 split_grf
[this->delta_x
.reg
] = false;
776 foreach_list(node
, &this->instructions
) {
777 fs_inst
*inst
= (fs_inst
*)node
;
779 /* Texturing produces 4 contiguous registers, so no splitting. */
780 if (inst
->is_tex()) {
781 split_grf
[inst
->dst
.reg
] = false;
785 /* Allocate new space for split regs. Note that the virtual
786 * numbers will be contiguous.
788 for (int i
= 0; i
< num_vars
; i
++) {
790 new_virtual_grf
[i
] = virtual_grf_alloc(1);
791 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
792 int reg
= virtual_grf_alloc(1);
793 assert(reg
== new_virtual_grf
[i
] + j
- 1);
796 this->virtual_grf_sizes
[i
] = 1;
800 foreach_list(node
, &this->instructions
) {
801 fs_inst
*inst
= (fs_inst
*)node
;
803 if (inst
->dst
.file
== GRF
&&
804 split_grf
[inst
->dst
.reg
] &&
805 inst
->dst
.reg_offset
!= 0) {
806 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
807 inst
->dst
.reg_offset
- 1);
808 inst
->dst
.reg_offset
= 0;
810 for (int i
= 0; i
< 3; i
++) {
811 if (inst
->src
[i
].file
== GRF
&&
812 split_grf
[inst
->src
[i
].reg
] &&
813 inst
->src
[i
].reg_offset
!= 0) {
814 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
815 inst
->src
[i
].reg_offset
- 1);
816 inst
->src
[i
].reg_offset
= 0;
820 this->live_intervals_valid
= false;
824 fs_visitor::remove_dead_constants()
826 if (c
->dispatch_width
== 8) {
827 this->params_remap
= ralloc_array(mem_ctx
, int, c
->prog_data
.nr_params
);
829 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++)
830 this->params_remap
[i
] = -1;
832 /* Find which params are still in use. */
833 foreach_list(node
, &this->instructions
) {
834 fs_inst
*inst
= (fs_inst
*)node
;
836 for (int i
= 0; i
< 3; i
++) {
837 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
839 if (inst
->src
[i
].file
!= UNIFORM
)
842 assert(constant_nr
< (int)c
->prog_data
.nr_params
);
844 /* For now, set this to non-negative. We'll give it the
845 * actual new number in a moment, in order to keep the
846 * register numbers nicely ordered.
848 this->params_remap
[constant_nr
] = 0;
852 /* Figure out what the new numbers for the params will be. At some
853 * point when we're doing uniform array access, we're going to want
854 * to keep the distinction between .reg and .reg_offset, but for
857 unsigned int new_nr_params
= 0;
858 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
859 if (this->params_remap
[i
] != -1) {
860 this->params_remap
[i
] = new_nr_params
++;
864 /* Update the list of params to be uploaded to match our new numbering. */
865 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
866 int remapped
= this->params_remap
[i
];
871 /* We've already done setup_paramvalues_refs() so no need to worry
872 * about param_index and param_offset.
874 c
->prog_data
.param
[remapped
] = c
->prog_data
.param
[i
];
875 c
->prog_data
.param_convert
[remapped
] = c
->prog_data
.param_convert
[i
];
878 c
->prog_data
.nr_params
= new_nr_params
;
880 /* This should have been generated in the 8-wide pass already. */
881 assert(this->params_remap
);
884 /* Now do the renumbering of the shader to remove unused params. */
885 foreach_list(node
, &this->instructions
) {
886 fs_inst
*inst
= (fs_inst
*)node
;
888 for (int i
= 0; i
< 3; i
++) {
889 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
891 if (inst
->src
[i
].file
!= UNIFORM
)
894 assert(this->params_remap
[constant_nr
] != -1);
895 inst
->src
[i
].reg
= this->params_remap
[constant_nr
];
896 inst
->src
[i
].reg_offset
= 0;
904 * Choose accesses from the UNIFORM file to demote to using the pull
907 * We allow a fragment shader to have more than the specified minimum
908 * maximum number of fragment shader uniform components (64). If
909 * there are too many of these, they'd fill up all of register space.
910 * So, this will push some of them out to the pull constant buffer and
911 * update the program to load them.
914 fs_visitor::setup_pull_constants()
916 /* Only allow 16 registers (128 uniform components) as push constants. */
917 unsigned int max_uniform_components
= 16 * 8;
918 if (c
->prog_data
.nr_params
<= max_uniform_components
)
921 if (c
->dispatch_width
== 16) {
922 fail("Pull constants not supported in 16-wide\n");
926 /* Just demote the end of the list. We could probably do better
927 * here, demoting things that are rarely used in the program first.
929 int pull_uniform_base
= max_uniform_components
;
930 int pull_uniform_count
= c
->prog_data
.nr_params
- pull_uniform_base
;
932 foreach_list(node
, &this->instructions
) {
933 fs_inst
*inst
= (fs_inst
*)node
;
935 for (int i
= 0; i
< 3; i
++) {
936 if (inst
->src
[i
].file
!= UNIFORM
)
939 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
940 if (uniform_nr
< pull_uniform_base
)
943 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
944 fs_inst
*pull
= new(mem_ctx
) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
946 pull
->offset
= ((uniform_nr
- pull_uniform_base
) * 4) & ~15;
948 pull
->annotation
= inst
->annotation
;
952 inst
->insert_before(pull
);
954 inst
->src
[i
].file
= GRF
;
955 inst
->src
[i
].reg
= dst
.reg
;
956 inst
->src
[i
].reg_offset
= 0;
957 inst
->src
[i
].smear
= (uniform_nr
- pull_uniform_base
) & 3;
961 for (int i
= 0; i
< pull_uniform_count
; i
++) {
962 c
->prog_data
.pull_param
[i
] = c
->prog_data
.param
[pull_uniform_base
+ i
];
963 c
->prog_data
.pull_param_convert
[i
] =
964 c
->prog_data
.param_convert
[pull_uniform_base
+ i
];
966 c
->prog_data
.nr_params
-= pull_uniform_count
;
967 c
->prog_data
.nr_pull_params
= pull_uniform_count
;
971 fs_visitor::calculate_live_intervals()
973 int num_vars
= this->virtual_grf_next
;
974 int *def
= ralloc_array(mem_ctx
, int, num_vars
);
975 int *use
= ralloc_array(mem_ctx
, int, num_vars
);
979 if (this->live_intervals_valid
)
982 for (int i
= 0; i
< num_vars
; i
++) {
983 def
[i
] = MAX_INSTRUCTION
;
988 foreach_list(node
, &this->instructions
) {
989 fs_inst
*inst
= (fs_inst
*)node
;
991 if (inst
->opcode
== BRW_OPCODE_DO
) {
992 if (loop_depth
++ == 0)
994 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
997 if (loop_depth
== 0) {
998 /* Patches up the use of vars marked for being live across
1001 for (int i
= 0; i
< num_vars
; i
++) {
1002 if (use
[i
] == loop_start
) {
1008 for (unsigned int i
= 0; i
< 3; i
++) {
1009 if (inst
->src
[i
].file
== GRF
) {
1010 int reg
= inst
->src
[i
].reg
;
1015 def
[reg
] = MIN2(loop_start
, def
[reg
]);
1016 use
[reg
] = loop_start
;
1018 /* Nobody else is going to go smash our start to
1019 * later in the loop now, because def[reg] now
1020 * points before the bb header.
1025 if (inst
->dst
.file
== GRF
) {
1026 int reg
= inst
->dst
.reg
;
1029 def
[reg
] = MIN2(def
[reg
], ip
);
1031 def
[reg
] = MIN2(def
[reg
], loop_start
);
1039 ralloc_free(this->virtual_grf_def
);
1040 ralloc_free(this->virtual_grf_use
);
1041 this->virtual_grf_def
= def
;
1042 this->virtual_grf_use
= use
;
1044 this->live_intervals_valid
= true;
1048 * Attempts to move immediate constants into the immediate
1049 * constant slot of following instructions.
1051 * Immediate constants are a bit tricky -- they have to be in the last
1052 * operand slot, you can't do abs/negate on them,
1056 fs_visitor::propagate_constants()
1058 bool progress
= false;
1060 calculate_live_intervals();
1062 foreach_list(node
, &this->instructions
) {
1063 fs_inst
*inst
= (fs_inst
*)node
;
1065 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1067 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
1068 inst
->dst
.type
!= inst
->src
[0].type
||
1069 (c
->dispatch_width
== 16 &&
1070 (inst
->force_uncompressed
|| inst
->force_sechalf
)))
1073 /* Don't bother with cases where we should have had the
1074 * operation on the constant folded in GLSL already.
1079 /* Found a move of a constant to a GRF. Find anything else using the GRF
1080 * before it's written, and replace it with the constant if we can.
1082 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->next
;
1083 !scan_inst
->is_tail_sentinel();
1084 scan_inst
= (fs_inst
*)scan_inst
->next
) {
1085 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
1086 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
1087 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
1088 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
1092 for (int i
= 2; i
>= 0; i
--) {
1093 if (scan_inst
->src
[i
].file
!= GRF
||
1094 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
1095 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
1098 /* Don't bother with cases where we should have had the
1099 * operation on the constant folded in GLSL already.
1101 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
1104 switch (scan_inst
->opcode
) {
1105 case BRW_OPCODE_MOV
:
1106 scan_inst
->src
[i
] = inst
->src
[0];
1110 case BRW_OPCODE_MUL
:
1111 case BRW_OPCODE_ADD
:
1113 scan_inst
->src
[i
] = inst
->src
[0];
1115 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
1116 /* Fit this constant in by commuting the operands */
1117 scan_inst
->src
[0] = scan_inst
->src
[1];
1118 scan_inst
->src
[1] = inst
->src
[0];
1123 case BRW_OPCODE_CMP
:
1125 scan_inst
->src
[i
] = inst
->src
[0];
1127 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
1130 new_cmod
= brw_swap_cmod(scan_inst
->conditional_mod
);
1131 if (new_cmod
!= ~0u) {
1132 /* Fit this constant in by swapping the operands and
1135 scan_inst
->src
[0] = scan_inst
->src
[1];
1136 scan_inst
->src
[1] = inst
->src
[0];
1137 scan_inst
->conditional_mod
= new_cmod
;
1143 case BRW_OPCODE_SEL
:
1145 scan_inst
->src
[i
] = inst
->src
[0];
1147 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
1148 scan_inst
->src
[0] = scan_inst
->src
[1];
1149 scan_inst
->src
[1] = inst
->src
[0];
1151 /* If this was predicated, flipping operands means
1152 * we also need to flip the predicate.
1154 if (scan_inst
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
1155 scan_inst
->predicate_inverse
=
1156 !scan_inst
->predicate_inverse
;
1162 case SHADER_OPCODE_RCP
:
1163 /* The hardware doesn't do math on immediate values
1164 * (because why are you doing that, seriously?), but
1165 * the correct answer is to just constant fold it
1169 if (inst
->src
[0].imm
.f
!= 0.0f
) {
1170 scan_inst
->opcode
= BRW_OPCODE_MOV
;
1171 scan_inst
->src
[0] = inst
->src
[0];
1172 scan_inst
->src
[0].imm
.f
= 1.0f
/ scan_inst
->src
[0].imm
.f
;
1182 if (scan_inst
->dst
.file
== GRF
&&
1183 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
1184 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
1185 scan_inst
->is_tex())) {
1192 this->live_intervals_valid
= false;
1199 * Attempts to move immediate constants into the immediate
1200 * constant slot of following instructions.
1202 * Immediate constants are a bit tricky -- they have to be in the last
1203 * operand slot, you can't do abs/negate on them,
1207 fs_visitor::opt_algebraic()
1209 bool progress
= false;
1211 calculate_live_intervals();
1213 foreach_list(node
, &this->instructions
) {
1214 fs_inst
*inst
= (fs_inst
*)node
;
1216 switch (inst
->opcode
) {
1217 case BRW_OPCODE_MUL
:
1218 if (inst
->src
[1].file
!= IMM
)
1222 if (inst
->src
[1].type
== BRW_REGISTER_TYPE_F
&&
1223 inst
->src
[1].imm
.f
== 1.0) {
1224 inst
->opcode
= BRW_OPCODE_MOV
;
1225 inst
->src
[1] = reg_undef
;
1240 * Must be called after calculate_live_intervales() to remove unused
1241 * writes to registers -- register allocation will fail otherwise
1242 * because something deffed but not used won't be considered to
1243 * interfere with other regs.
1246 fs_visitor::dead_code_eliminate()
1248 bool progress
= false;
1251 calculate_live_intervals();
1253 foreach_list_safe(node
, &this->instructions
) {
1254 fs_inst
*inst
= (fs_inst
*)node
;
1256 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
1265 live_intervals_valid
= false;
1271 fs_visitor::register_coalesce()
1273 bool progress
= false;
1277 foreach_list_safe(node
, &this->instructions
) {
1278 fs_inst
*inst
= (fs_inst
*)node
;
1280 /* Make sure that we dominate the instructions we're going to
1281 * scan for interfering with our coalescing, or we won't have
1282 * scanned enough to see if anything interferes with our
1283 * coalescing. We don't dominate the following instructions if
1284 * we're in a loop or an if block.
1286 switch (inst
->opcode
) {
1290 case BRW_OPCODE_WHILE
:
1296 case BRW_OPCODE_ENDIF
:
1302 if (loop_depth
|| if_depth
)
1305 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1308 inst
->dst
.file
!= GRF
|| (inst
->src
[0].file
!= GRF
&&
1309 inst
->src
[0].file
!= UNIFORM
)||
1310 inst
->dst
.type
!= inst
->src
[0].type
)
1313 bool has_source_modifiers
= inst
->src
[0].abs
|| inst
->src
[0].negate
;
1315 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
1316 * them: check for no writes to either one until the exit of the
1319 bool interfered
= false;
1321 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->next
;
1322 !scan_inst
->is_tail_sentinel();
1323 scan_inst
= (fs_inst
*)scan_inst
->next
) {
1324 if (scan_inst
->dst
.file
== GRF
) {
1325 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
1326 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
1327 scan_inst
->is_tex())) {
1331 if (inst
->src
[0].file
== GRF
&&
1332 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1333 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
1334 scan_inst
->is_tex())) {
1340 /* The gen6 MATH instruction can't handle source modifiers or
1341 * unusual register regions, so avoid coalescing those for
1342 * now. We should do something more specific.
1344 if (intel
->gen
>= 6 &&
1345 scan_inst
->is_math() &&
1346 (has_source_modifiers
|| inst
->src
[0].file
== UNIFORM
)) {
1355 /* Rewrite the later usage to point at the source of the move to
1358 for (fs_inst
*scan_inst
= inst
;
1359 !scan_inst
->is_tail_sentinel();
1360 scan_inst
= (fs_inst
*)scan_inst
->next
) {
1361 for (int i
= 0; i
< 3; i
++) {
1362 if (scan_inst
->src
[i
].file
== GRF
&&
1363 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
1364 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
1365 fs_reg new_src
= inst
->src
[0];
1366 new_src
.negate
^= scan_inst
->src
[i
].negate
;
1367 new_src
.abs
|= scan_inst
->src
[i
].abs
;
1368 scan_inst
->src
[i
] = new_src
;
1378 live_intervals_valid
= false;
1385 fs_visitor::compute_to_mrf()
1387 bool progress
= false;
1390 calculate_live_intervals();
1392 foreach_list_safe(node
, &this->instructions
) {
1393 fs_inst
*inst
= (fs_inst
*)node
;
1398 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1400 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
1401 inst
->dst
.type
!= inst
->src
[0].type
||
1402 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
1405 /* Work out which hardware MRF registers are written by this
1408 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
1410 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
1411 mrf_high
= mrf_low
+ 4;
1412 } else if (c
->dispatch_width
== 16 &&
1413 (!inst
->force_uncompressed
&& !inst
->force_sechalf
)) {
1414 mrf_high
= mrf_low
+ 1;
1419 /* Can't compute-to-MRF this GRF if someone else was going to
1422 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
1425 /* Found a move of a GRF to a MRF. Let's see if we can go
1426 * rewrite the thing that made this GRF to write into the MRF.
1429 for (scan_inst
= (fs_inst
*)inst
->prev
;
1430 scan_inst
->prev
!= NULL
;
1431 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
1432 if (scan_inst
->dst
.file
== GRF
&&
1433 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
1434 /* Found the last thing to write our reg we want to turn
1435 * into a compute-to-MRF.
1438 if (scan_inst
->is_tex()) {
1439 /* texturing writes several continuous regs, so we can't
1440 * compute-to-mrf that.
1445 /* If it's predicated, it (probably) didn't populate all
1446 * the channels. We might be able to rewrite everything
1447 * that writes that reg, but it would require smarter
1448 * tracking to delay the rewriting until complete success.
1450 if (scan_inst
->predicated
)
1453 /* If it's half of register setup and not the same half as
1454 * our MOV we're trying to remove, bail for now.
1456 if (scan_inst
->force_uncompressed
!= inst
->force_uncompressed
||
1457 scan_inst
->force_sechalf
!= inst
->force_sechalf
) {
1461 /* SEND instructions can't have MRF as a destination. */
1462 if (scan_inst
->mlen
)
1465 if (intel
->gen
>= 6) {
1466 /* gen6 math instructions must have the destination be
1467 * GRF, so no compute-to-MRF for them.
1469 if (scan_inst
->is_math()) {
1474 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1475 /* Found the creator of our MRF's source value. */
1476 scan_inst
->dst
.file
= MRF
;
1477 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1478 scan_inst
->saturate
|= inst
->saturate
;
1485 /* We don't handle flow control here. Most computation of
1486 * values that end up in MRFs are shortly before the MRF
1489 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
1490 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
1491 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
1492 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
1496 /* You can't read from an MRF, so if someone else reads our
1497 * MRF's source GRF that we wanted to rewrite, that stops us.
1499 bool interfered
= false;
1500 for (int i
= 0; i
< 3; i
++) {
1501 if (scan_inst
->src
[i
].file
== GRF
&&
1502 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
1503 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1510 if (scan_inst
->dst
.file
== MRF
) {
1511 /* If somebody else writes our MRF here, we can't
1512 * compute-to-MRF before that.
1514 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
1517 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
1518 scan_mrf_high
= scan_mrf_low
+ 4;
1519 } else if (c
->dispatch_width
== 16 &&
1520 (!scan_inst
->force_uncompressed
&&
1521 !scan_inst
->force_sechalf
)) {
1522 scan_mrf_high
= scan_mrf_low
+ 1;
1524 scan_mrf_high
= scan_mrf_low
;
1527 if (mrf_low
== scan_mrf_low
||
1528 mrf_low
== scan_mrf_high
||
1529 mrf_high
== scan_mrf_low
||
1530 mrf_high
== scan_mrf_high
) {
1535 if (scan_inst
->mlen
> 0) {
1536 /* Found a SEND instruction, which means that there are
1537 * live values in MRFs from base_mrf to base_mrf +
1538 * scan_inst->mlen - 1. Don't go pushing our MRF write up
1541 if (mrf_low
>= scan_inst
->base_mrf
&&
1542 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1545 if (mrf_high
>= scan_inst
->base_mrf
&&
1546 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1557 * Walks through basic blocks, locking for repeated MRF writes and
1558 * removing the later ones.
1561 fs_visitor::remove_duplicate_mrf_writes()
1563 fs_inst
*last_mrf_move
[16];
1564 bool progress
= false;
1566 /* Need to update the MRF tracking for compressed instructions. */
1567 if (c
->dispatch_width
== 16)
1570 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
1572 foreach_list_safe(node
, &this->instructions
) {
1573 fs_inst
*inst
= (fs_inst
*)node
;
1575 switch (inst
->opcode
) {
1577 case BRW_OPCODE_WHILE
:
1579 case BRW_OPCODE_ELSE
:
1580 case BRW_OPCODE_ENDIF
:
1581 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
1587 if (inst
->opcode
== BRW_OPCODE_MOV
&&
1588 inst
->dst
.file
== MRF
) {
1589 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
1590 if (prev_inst
&& inst
->equals(prev_inst
)) {
1597 /* Clear out the last-write records for MRFs that were overwritten. */
1598 if (inst
->dst
.file
== MRF
) {
1599 last_mrf_move
[inst
->dst
.reg
] = NULL
;
1602 if (inst
->mlen
> 0) {
1603 /* Found a SEND instruction, which will include two or fewer
1604 * implied MRF writes. We could do better here.
1606 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
1607 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
1611 /* Clear out any MRF move records whose sources got overwritten. */
1612 if (inst
->dst
.file
== GRF
) {
1613 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
1614 if (last_mrf_move
[i
] &&
1615 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
1616 last_mrf_move
[i
] = NULL
;
1621 if (inst
->opcode
== BRW_OPCODE_MOV
&&
1622 inst
->dst
.file
== MRF
&&
1623 inst
->src
[0].file
== GRF
&&
1624 !inst
->predicated
) {
1625 last_mrf_move
[inst
->dst
.reg
] = inst
;
1633 fs_visitor::virtual_grf_interferes(int a
, int b
)
1635 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
1636 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
1638 /* We can't handle dead register writes here, without iterating
1639 * over the whole instruction stream to find every single dead
1640 * write to that register to compare to the live interval of the
1641 * other register. Just assert that dead_code_eliminate() has been
1644 assert((this->virtual_grf_use
[a
] != -1 ||
1645 this->virtual_grf_def
[a
] == MAX_INSTRUCTION
) &&
1646 (this->virtual_grf_use
[b
] != -1 ||
1647 this->virtual_grf_def
[b
] == MAX_INSTRUCTION
));
1649 /* If the register is used to store 16 values of less than float
1650 * size (only the case for pixel_[xy]), then we can't allocate
1651 * another dword-sized thing to that register that would be used in
1652 * the same instruction. This is because when the GPU decodes (for
1655 * (declare (in ) vec4 gl_FragCoord@0x97766a0)
1656 * add(16) g6<1>F g6<8,8,1>UW 0.5F { align1 compr };
1658 * it's actually processed as:
1659 * add(8) g6<1>F g6<8,8,1>UW 0.5F { align1 };
1660 * add(8) g7<1>F g6.8<8,8,1>UW 0.5F { align1 sechalf };
1662 * so our second half values in g6 got overwritten in the first
1665 if (c
->dispatch_width
== 16 && (this->pixel_x
.reg
== a
||
1666 this->pixel_x
.reg
== b
||
1667 this->pixel_y
.reg
== a
||
1668 this->pixel_y
.reg
== b
)) {
1669 return start
<= end
;
1678 uint32_t prog_offset_16
= 0;
1679 uint32_t orig_nr_params
= c
->prog_data
.nr_params
;
1681 brw_wm_payload_setup(brw
, c
);
1683 if (c
->dispatch_width
== 16) {
1684 /* align to 64 byte boundary. */
1685 while ((c
->func
.nr_insn
* sizeof(struct brw_instruction
)) % 64) {
1689 /* Save off the start of this 16-wide program in case we succeed. */
1690 prog_offset_16
= c
->func
.nr_insn
* sizeof(struct brw_instruction
);
1692 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1698 calculate_urb_setup();
1700 emit_interpolation_setup_gen4();
1702 emit_interpolation_setup_gen6();
1704 /* Generate FS IR for main(). (the visitor only descends into
1705 * functions called "main").
1707 foreach_list(node
, &*shader
->ir
) {
1708 ir_instruction
*ir
= (ir_instruction
*)node
;
1710 this->result
= reg_undef
;
1718 split_virtual_grfs();
1720 setup_paramvalues_refs();
1721 setup_pull_constants();
1727 progress
= remove_duplicate_mrf_writes() || progress
;
1729 progress
= propagate_constants() || progress
;
1730 progress
= opt_algebraic() || progress
;
1731 progress
= register_coalesce() || progress
;
1732 progress
= compute_to_mrf() || progress
;
1733 progress
= dead_code_eliminate() || progress
;
1736 remove_dead_constants();
1738 schedule_instructions();
1740 assign_curb_setup();
1744 /* Debug of register spilling: Go spill everything. */
1745 int virtual_grf_count
= virtual_grf_next
;
1746 for (int i
= 0; i
< virtual_grf_count
; i
++) {
1752 assign_regs_trivial();
1754 while (!assign_regs()) {
1760 assert(force_uncompressed_stack
== 0);
1761 assert(force_sechalf_stack
== 0);
1768 if (c
->dispatch_width
== 8) {
1769 c
->prog_data
.reg_blocks
= brw_register_blocks(grf_used
);
1771 c
->prog_data
.reg_blocks_16
= brw_register_blocks(grf_used
);
1772 c
->prog_data
.prog_offset_16
= prog_offset_16
;
1774 /* Make sure we didn't try to sneak in an extra uniform */
1775 assert(orig_nr_params
== c
->prog_data
.nr_params
);
1782 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
,
1783 struct gl_shader_program
*prog
)
1785 struct intel_context
*intel
= &brw
->intel
;
1790 struct brw_shader
*shader
=
1791 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
1795 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1796 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
1797 _mesa_print_ir(shader
->ir
, NULL
);
1801 /* Now the main event: Visit the shader IR and generate our FS IR for it.
1803 c
->dispatch_width
= 8;
1805 fs_visitor
v(c
, prog
, shader
);
1807 prog
->LinkStatus
= GL_FALSE
;
1808 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1813 if (intel
->gen
>= 5 && c
->prog_data
.nr_pull_params
== 0) {
1814 c
->dispatch_width
= 16;
1815 fs_visitor
v2(c
, prog
, shader
);
1816 v2
.import_uniforms(&v
);
1820 c
->prog_data
.dispatch_width
= 8;
1826 brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
1828 struct brw_context
*brw
= brw_context(ctx
);
1829 struct brw_wm_prog_key key
;
1830 struct gl_fragment_program
*fp
= prog
->FragmentProgram
;
1831 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
1836 memset(&key
, 0, sizeof(key
));
1839 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
1841 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
1842 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
1844 /* Just assume depth testing. */
1845 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
1846 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
1848 key
.vp_outputs_written
|= BITFIELD64_BIT(FRAG_ATTRIB_WPOS
);
1849 for (int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
1850 if (!(fp
->Base
.InputsRead
& BITFIELD64_BIT(i
)))
1853 key
.proj_attrib_mask
|= 1 << i
;
1855 int vp_index
= _mesa_vert_result_to_frag_attrib((gl_vert_result
) i
);
1858 key
.vp_outputs_written
|= BITFIELD64_BIT(vp_index
);
1861 key
.clamp_fragment_color
= true;
1863 for (int i
= 0; i
< BRW_MAX_TEX_UNIT
; i
++) {
1864 if (fp
->Base
.ShadowSamplers
& (1 << i
))
1865 key
.compare_funcs
[i
] = GL_LESS
;
1867 /* FINISHME: depth compares might use (0,0,0,W) for example */
1868 key
.tex_swizzles
[i
] = SWIZZLE_XYZW
;
1871 if (fp
->Base
.InputsRead
& FRAG_BIT_WPOS
) {
1872 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
1873 key
.render_to_fbo
= ctx
->DrawBuffer
->Name
!= 0;
1876 key
.nr_color_regions
= 1;
1878 key
.program_string_id
= bfp
->id
;
1880 uint32_t old_prog_offset
= brw
->wm
.prog_offset
;
1881 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
1883 bool success
= do_wm_prog(brw
, prog
, bfp
, &key
);
1885 brw
->wm
.prog_offset
= old_prog_offset
;
1886 brw
->wm
.prog_data
= old_prog_data
;