2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "../glsl/glsl_types.h"
48 #include "../glsl/ir_optimization.h"
49 #include "../glsl/ir_print_visitor.h"
51 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
54 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
56 struct brw_shader
*shader
;
58 shader
= talloc_zero(NULL
, struct brw_shader
);
60 shader
->base
.Type
= type
;
61 shader
->base
.Name
= name
;
62 _mesa_init_shader(ctx
, &shader
->base
);
68 struct gl_shader_program
*
69 brw_new_shader_program(struct gl_context
*ctx
, GLuint name
)
71 struct brw_shader_program
*prog
;
72 prog
= talloc_zero(NULL
, struct brw_shader_program
);
74 prog
->base
.Name
= name
;
75 _mesa_init_shader_program(ctx
, &prog
->base
);
81 brw_compile_shader(struct gl_context
*ctx
, struct gl_shader
*shader
)
83 if (!_mesa_ir_compile_shader(ctx
, shader
))
90 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
92 struct brw_shader
*shader
=
93 (struct brw_shader
*)prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
95 void *mem_ctx
= talloc_new(NULL
);
99 talloc_free(shader
->ir
);
100 shader
->ir
= new(shader
) exec_list
;
101 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
103 do_mat_op_to_vec(shader
->ir
);
104 do_mod_to_fract(shader
->ir
);
105 do_div_to_mul_rcp(shader
->ir
);
106 do_sub_to_add_neg(shader
->ir
);
107 do_explog_to_explog2(shader
->ir
);
108 do_lower_texture_projection(shader
->ir
);
109 brw_do_cubemap_normalize(shader
->ir
);
114 brw_do_channel_expressions(shader
->ir
);
115 brw_do_vector_splitting(shader
->ir
);
117 progress
= do_lower_jumps(shader
->ir
, true, true,
118 true, /* main return */
119 false, /* continue */
123 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
125 progress
= lower_noise(shader
->ir
) || progress
;
127 lower_variable_index_to_cond_assign(shader
->ir
,
129 GL_TRUE
, /* output */
131 GL_TRUE
/* uniform */
135 validate_ir_tree(shader
->ir
);
137 reparent_ir(shader
->ir
, shader
->ir
);
138 talloc_free(mem_ctx
);
141 if (!_mesa_ir_link_shader(ctx
, prog
))
148 type_size(const struct glsl_type
*type
)
150 unsigned int size
, i
;
152 switch (type
->base_type
) {
155 case GLSL_TYPE_FLOAT
:
157 return type
->components();
158 case GLSL_TYPE_ARRAY
:
159 return type_size(type
->fields
.array
) * type
->length
;
160 case GLSL_TYPE_STRUCT
:
162 for (i
= 0; i
< type
->length
; i
++) {
163 size
+= type_size(type
->fields
.structure
[i
].type
);
166 case GLSL_TYPE_SAMPLER
:
167 /* Samplers take up no register space, since they're baked in at
172 assert(!"not reached");
178 fs_visitor::virtual_grf_alloc(int size
)
180 if (virtual_grf_array_size
<= virtual_grf_next
) {
181 if (virtual_grf_array_size
== 0)
182 virtual_grf_array_size
= 16;
184 virtual_grf_array_size
*= 2;
185 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
186 int, virtual_grf_array_size
);
188 /* This slot is always unused. */
189 virtual_grf_sizes
[0] = 0;
191 virtual_grf_sizes
[virtual_grf_next
] = size
;
192 return virtual_grf_next
++;
195 /** Fixed HW reg constructor. */
196 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
200 this->hw_reg
= hw_reg
;
201 this->type
= BRW_REGISTER_TYPE_F
;
204 /** Fixed HW reg constructor. */
205 fs_reg::fs_reg(enum register_file file
, int hw_reg
, uint32_t type
)
209 this->hw_reg
= hw_reg
;
214 brw_type_for_base_type(const struct glsl_type
*type
)
216 switch (type
->base_type
) {
217 case GLSL_TYPE_FLOAT
:
218 return BRW_REGISTER_TYPE_F
;
221 return BRW_REGISTER_TYPE_D
;
223 return BRW_REGISTER_TYPE_UD
;
224 case GLSL_TYPE_ARRAY
:
225 case GLSL_TYPE_STRUCT
:
226 case GLSL_TYPE_SAMPLER
:
227 /* These should be overridden with the type of the member when
228 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
229 * way to trip up if we don't.
231 return BRW_REGISTER_TYPE_UD
;
233 assert(!"not reached");
234 return BRW_REGISTER_TYPE_F
;
238 /** Automatic reg constructor. */
239 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
244 this->reg
= v
->virtual_grf_alloc(type_size(type
));
245 this->reg_offset
= 0;
246 this->type
= brw_type_for_base_type(type
);
250 fs_visitor::variable_storage(ir_variable
*var
)
252 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
255 /* Our support for uniforms is piggy-backed on the struct
256 * gl_fragment_program, because that's where the values actually
257 * get stored, rather than in some global gl_shader_program uniform
261 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
263 unsigned int offset
= 0;
266 if (type
->is_matrix()) {
267 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
268 type
->vector_elements
,
271 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
272 offset
+= setup_uniform_values(loc
+ offset
, column
);
278 switch (type
->base_type
) {
279 case GLSL_TYPE_FLOAT
:
283 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
284 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
285 unsigned int param
= c
->prog_data
.nr_params
++;
287 assert(param
< ARRAY_SIZE(c
->prog_data
.param
));
289 switch (type
->base_type
) {
290 case GLSL_TYPE_FLOAT
:
291 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
294 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2U
;
297 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2I
;
300 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2B
;
304 c
->prog_data
.param
[param
] = &vec_values
[i
];
308 case GLSL_TYPE_STRUCT
:
309 for (unsigned int i
= 0; i
< type
->length
; i
++) {
310 offset
+= setup_uniform_values(loc
+ offset
,
311 type
->fields
.structure
[i
].type
);
315 case GLSL_TYPE_ARRAY
:
316 for (unsigned int i
= 0; i
< type
->length
; i
++) {
317 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
321 case GLSL_TYPE_SAMPLER
:
322 /* The sampler takes up a slot, but we don't use any values from it. */
326 assert(!"not reached");
332 /* Our support for builtin uniforms is even scarier than non-builtin.
333 * It sits on top of the PROG_STATE_VAR parameters that are
334 * automatically updated from GL context state.
337 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
339 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
341 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
342 statevar
= &_mesa_builtin_uniform_desc
[i
];
343 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
347 if (!statevar
->name
) {
349 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
354 if (ir
->type
->is_array()) {
355 array_count
= ir
->type
->length
;
360 for (int a
= 0; a
< array_count
; a
++) {
361 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
362 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
363 int tokens
[STATE_LENGTH
];
365 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
366 if (ir
->type
->is_array()) {
370 /* This state reference has already been setup by ir_to_mesa,
371 * but we'll get the same index back here.
373 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
374 (gl_state_index
*)tokens
);
375 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
377 /* Add each of the unique swizzles of the element as a
378 * parameter. This'll end up matching the expected layout of
379 * the array/matrix/structure we're trying to fill in.
382 for (unsigned int i
= 0; i
< 4; i
++) {
383 int swiz
= GET_SWZ(element
->swizzle
, i
);
384 if (swiz
== last_swiz
)
388 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
390 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
397 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
399 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
401 fs_reg neg_y
= this->pixel_y
;
405 if (ir
->pixel_center_integer
) {
406 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
408 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
413 if (ir
->origin_upper_left
&& ir
->pixel_center_integer
) {
414 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
416 fs_reg pixel_y
= this->pixel_y
;
417 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
419 if (!ir
->origin_upper_left
) {
420 pixel_y
.negate
= true;
421 offset
+= c
->key
.drawable_height
- 1.0;
424 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
429 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
430 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
433 /* gl_FragCoord.w: Already set up in emit_interpolation */
434 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
440 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
442 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
443 /* Interpolation is always in floating point regs. */
444 reg
->type
= BRW_REGISTER_TYPE_F
;
447 unsigned int array_elements
;
448 const glsl_type
*type
;
450 if (ir
->type
->is_array()) {
451 array_elements
= ir
->type
->length
;
452 if (array_elements
== 0) {
455 type
= ir
->type
->fields
.array
;
461 int location
= ir
->location
;
462 for (unsigned int i
= 0; i
< array_elements
; i
++) {
463 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
464 if (urb_setup
[location
] == -1) {
465 /* If there's no incoming setup data for this slot, don't
466 * emit interpolation for it.
468 attr
.reg_offset
+= type
->vector_elements
;
473 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
474 struct brw_reg interp
= interp_reg(location
, c
);
475 emit(fs_inst(FS_OPCODE_LINTERP
,
483 if (intel
->gen
< 6) {
484 attr
.reg_offset
-= type
->vector_elements
;
485 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
486 emit(fs_inst(BRW_OPCODE_MUL
,
501 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
503 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
505 /* The frontfacing comes in as a bit in the thread payload. */
506 if (intel
->gen
>= 6) {
507 emit(fs_inst(BRW_OPCODE_ASR
,
509 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
511 emit(fs_inst(BRW_OPCODE_NOT
,
514 emit(fs_inst(BRW_OPCODE_AND
,
519 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
520 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
523 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
527 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
528 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
535 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src
)
547 assert(!"not reached: bad math opcode");
551 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
552 * might be able to do better by doing execsize = 1 math and then
553 * expanding that result out, but we would need to be careful with
556 if (intel
->gen
>= 6 && src
.file
== UNIFORM
) {
557 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
558 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src
));
562 fs_inst
*inst
= emit(fs_inst(opcode
, dst
, src
));
564 if (intel
->gen
< 6) {
573 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
578 assert(opcode
== FS_OPCODE_POW
);
580 if (intel
->gen
>= 6) {
581 /* Can't do hstride == 0 args to gen6 math, so expand it out. */
582 if (src0
.file
== UNIFORM
) {
583 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
584 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src0
));
588 if (src1
.file
== UNIFORM
) {
589 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
590 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src1
));
594 inst
= emit(fs_inst(opcode
, dst
, src0
, src1
));
596 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1), src1
));
597 inst
= emit(fs_inst(opcode
, dst
, src0
, reg_null_f
));
599 inst
->base_mrf
= base_mrf
;
606 fs_visitor::visit(ir_variable
*ir
)
610 if (variable_storage(ir
))
613 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
614 this->frag_color
= ir
;
615 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
616 this->frag_data
= ir
;
617 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
618 this->frag_depth
= ir
;
621 if (ir
->mode
== ir_var_in
) {
622 if (!strcmp(ir
->name
, "gl_FragCoord")) {
623 reg
= emit_fragcoord_interpolation(ir
);
624 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
625 reg
= emit_frontfacing_interpolation(ir
);
627 reg
= emit_general_interpolation(ir
);
630 hash_table_insert(this->variable_ht
, reg
, ir
);
634 if (ir
->mode
== ir_var_uniform
) {
635 int param_index
= c
->prog_data
.nr_params
;
637 if (!strncmp(ir
->name
, "gl_", 3)) {
638 setup_builtin_uniform_values(ir
);
640 setup_uniform_values(ir
->location
, ir
->type
);
643 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
644 reg
->type
= brw_type_for_base_type(ir
->type
);
648 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
650 hash_table_insert(this->variable_ht
, reg
, ir
);
654 fs_visitor::visit(ir_dereference_variable
*ir
)
656 fs_reg
*reg
= variable_storage(ir
->var
);
661 fs_visitor::visit(ir_dereference_record
*ir
)
663 const glsl_type
*struct_type
= ir
->record
->type
;
665 ir
->record
->accept(this);
667 unsigned int offset
= 0;
668 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
669 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
671 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
673 this->result
.reg_offset
+= offset
;
674 this->result
.type
= brw_type_for_base_type(ir
->type
);
678 fs_visitor::visit(ir_dereference_array
*ir
)
683 ir
->array
->accept(this);
684 index
= ir
->array_index
->as_constant();
686 element_size
= type_size(ir
->type
);
687 this->result
.type
= brw_type_for_base_type(ir
->type
);
690 assert(this->result
.file
== UNIFORM
||
691 (this->result
.file
== GRF
&&
692 this->result
.reg
!= 0));
693 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
695 assert(!"FINISHME: non-constant array element");
700 fs_visitor::visit(ir_expression
*ir
)
702 unsigned int operand
;
706 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
707 ir
->operands
[operand
]->accept(this);
708 if (this->result
.file
== BAD_FILE
) {
710 printf("Failed to get tree for expression operand:\n");
711 ir
->operands
[operand
]->accept(&v
);
714 op
[operand
] = this->result
;
716 /* Matrix expression operands should have been broken down to vector
717 * operations already.
719 assert(!ir
->operands
[operand
]->type
->is_matrix());
720 /* And then those vector operands should have been broken down to scalar.
722 assert(!ir
->operands
[operand
]->type
->is_vector());
725 /* Storage for our result. If our result goes into an assignment, it will
726 * just get copy-propagated out, so no worries.
728 this->result
= fs_reg(this, ir
->type
);
730 switch (ir
->operation
) {
731 case ir_unop_logic_not
:
732 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
733 * ones complement of the whole register, not just bit 0.
735 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1)));
738 op
[0].negate
= !op
[0].negate
;
739 this->result
= op
[0];
743 this->result
= op
[0];
746 temp
= fs_reg(this, ir
->type
);
748 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
750 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
751 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
752 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
753 inst
->predicated
= true;
755 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
756 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
757 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
758 inst
->predicated
= true;
762 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
766 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
769 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
773 assert(!"not reached: should be handled by ir_explog_to_explog2");
776 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
779 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
783 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
786 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
790 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
793 assert(!"not reached: should be handled by ir_sub_to_add_neg");
797 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
800 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
803 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
807 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
808 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
809 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
811 case ir_binop_greater
:
812 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
813 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
814 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
816 case ir_binop_lequal
:
817 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
818 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
819 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
821 case ir_binop_gequal
:
822 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
823 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
824 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
827 case ir_binop_all_equal
: /* same as nequal for scalars */
828 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
829 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
830 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
832 case ir_binop_nequal
:
833 case ir_binop_any_nequal
: /* same as nequal for scalars */
834 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
835 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
836 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
839 case ir_binop_logic_xor
:
840 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
843 case ir_binop_logic_or
:
844 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
847 case ir_binop_logic_and
:
848 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
854 assert(!"not reached: should be handled by brw_fs_channel_expressions");
858 assert(!"not reached: should be handled by lower_noise");
862 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
866 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
873 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
877 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
878 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
879 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
,
880 this->result
, fs_reg(1)));
884 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
887 op
[0].negate
= !op
[0].negate
;
888 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
889 this->result
.negate
= true;
892 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
895 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
897 case ir_unop_round_even
:
898 emit(fs_inst(BRW_OPCODE_RNDE
, this->result
, op
[0]));
902 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
903 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
905 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
906 inst
->predicated
= true;
909 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
910 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
912 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
913 inst
->predicated
= true;
917 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
920 case ir_unop_bit_not
:
921 inst
= emit(fs_inst(BRW_OPCODE_NOT
, this->result
, op
[0]));
923 case ir_binop_bit_and
:
924 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
926 case ir_binop_bit_xor
:
927 inst
= emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
929 case ir_binop_bit_or
:
930 inst
= emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
934 case ir_binop_lshift
:
935 case ir_binop_rshift
:
936 assert(!"GLSL 1.30 features unsupported");
942 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
943 const glsl_type
*type
, bool predicated
)
945 switch (type
->base_type
) {
946 case GLSL_TYPE_FLOAT
:
950 for (unsigned int i
= 0; i
< type
->components(); i
++) {
951 l
.type
= brw_type_for_base_type(type
);
952 r
.type
= brw_type_for_base_type(type
);
954 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
955 inst
->predicated
= predicated
;
961 case GLSL_TYPE_ARRAY
:
962 for (unsigned int i
= 0; i
< type
->length
; i
++) {
963 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
967 case GLSL_TYPE_STRUCT
:
968 for (unsigned int i
= 0; i
< type
->length
; i
++) {
969 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
974 case GLSL_TYPE_SAMPLER
:
978 assert(!"not reached");
984 fs_visitor::visit(ir_assignment
*ir
)
989 /* FINISHME: arrays on the lhs */
990 ir
->lhs
->accept(this);
993 ir
->rhs
->accept(this);
996 assert(l
.file
!= BAD_FILE
);
997 assert(r
.file
!= BAD_FILE
);
1000 emit_bool_to_cond_code(ir
->condition
);
1003 if (ir
->lhs
->type
->is_scalar() ||
1004 ir
->lhs
->type
->is_vector()) {
1005 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1006 if (ir
->write_mask
& (1 << i
)) {
1007 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1009 inst
->predicated
= true;
1015 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1020 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1024 bool simd16
= false;
1030 if (ir
->shadow_comparitor
) {
1031 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1032 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1034 coordinate
.reg_offset
++;
1036 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1039 if (ir
->op
== ir_tex
) {
1040 /* There's no plain shadow compare message, so we use shadow
1041 * compare with a bias of 0.0.
1043 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1046 } else if (ir
->op
== ir_txb
) {
1047 ir
->lod_info
.bias
->accept(this);
1048 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1052 assert(ir
->op
== ir_txl
);
1053 ir
->lod_info
.lod
->accept(this);
1054 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1059 ir
->shadow_comparitor
->accept(this);
1060 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1062 } else if (ir
->op
== ir_tex
) {
1063 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1064 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1066 coordinate
.reg_offset
++;
1068 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1071 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1072 * instructions. We'll need to do SIMD16 here.
1074 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1076 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1077 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2),
1079 coordinate
.reg_offset
++;
1082 /* lod/bias appears after u/v/r. */
1085 if (ir
->op
== ir_txb
) {
1086 ir
->lod_info
.bias
->accept(this);
1087 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1091 ir
->lod_info
.lod
->accept(this);
1092 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1097 /* The unused upper half. */
1100 /* Now, since we're doing simd16, the return is 2 interleaved
1101 * vec4s where the odd-indexed ones are junk. We'll need to move
1102 * this weirdness around to the expected layout.
1106 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1108 dst
.type
= BRW_REGISTER_TYPE_F
;
1111 fs_inst
*inst
= NULL
;
1114 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1117 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1120 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1124 assert(!"GLSL 1.30 features unsupported");
1127 inst
->base_mrf
= base_mrf
;
1131 for (int i
= 0; i
< 4; i
++) {
1132 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1133 orig_dst
.reg_offset
++;
1134 dst
.reg_offset
+= 2;
1142 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1144 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1145 * optional parameters like shadow comparitor or LOD bias. If
1146 * optional parameters aren't present, those base slots are
1147 * optional and don't need to be included in the message.
1149 * We don't fill in the unnecessary slots regardless, which may
1150 * look surprising in the disassembly.
1152 int mlen
= 1; /* g0 header always present. */
1155 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1156 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1158 coordinate
.reg_offset
++;
1160 mlen
+= ir
->coordinate
->type
->vector_elements
;
1162 if (ir
->shadow_comparitor
) {
1163 mlen
= MAX2(mlen
, 5);
1165 ir
->shadow_comparitor
->accept(this);
1166 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1170 fs_inst
*inst
= NULL
;
1173 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1176 ir
->lod_info
.bias
->accept(this);
1177 mlen
= MAX2(mlen
, 5);
1178 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1181 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1184 ir
->lod_info
.lod
->accept(this);
1185 mlen
= MAX2(mlen
, 5);
1186 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1189 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1193 assert(!"GLSL 1.30 features unsupported");
1196 inst
->base_mrf
= base_mrf
;
1203 fs_visitor::visit(ir_texture
*ir
)
1206 fs_inst
*inst
= NULL
;
1208 ir
->coordinate
->accept(this);
1209 fs_reg coordinate
= this->result
;
1211 /* Should be lowered by do_lower_texture_projection */
1212 assert(!ir
->projector
);
1214 sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
1215 ctx
->Shader
.CurrentFragmentProgram
,
1216 &brw
->fragment_program
->Base
);
1217 sampler
= c
->fp
->program
.Base
.SamplerUnits
[sampler
];
1219 /* The 965 requires the EU to do the normalization of GL rectangle
1220 * texture coordinates. We use the program parameter state
1221 * tracking to get the scaling factor.
1223 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1224 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1225 int tokens
[STATE_LENGTH
] = {
1227 STATE_TEXRECT_SCALE
,
1233 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
1235 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
+ 1] =
1238 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1239 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1240 GLuint index
= _mesa_add_state_reference(params
,
1241 (gl_state_index
*)tokens
);
1242 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
1244 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[0];
1245 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[1];
1247 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1248 fs_reg src
= coordinate
;
1251 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_x
));
1254 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_y
));
1257 /* Writemasking doesn't eliminate channels on SIMD8 texture
1258 * samples, so don't worry about them.
1260 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1262 if (intel
->gen
< 5) {
1263 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1265 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1268 inst
->sampler
= sampler
;
1272 if (ir
->shadow_comparitor
)
1273 inst
->shadow_compare
= true;
1275 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1276 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1278 for (int i
= 0; i
< 4; i
++) {
1279 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1280 fs_reg l
= swizzle_dst
;
1283 if (swiz
== SWIZZLE_ZERO
) {
1284 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1285 } else if (swiz
== SWIZZLE_ONE
) {
1286 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1289 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1290 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1293 this->result
= swizzle_dst
;
1298 fs_visitor::visit(ir_swizzle
*ir
)
1300 ir
->val
->accept(this);
1301 fs_reg val
= this->result
;
1303 if (ir
->type
->vector_elements
== 1) {
1304 this->result
.reg_offset
+= ir
->mask
.x
;
1308 fs_reg result
= fs_reg(this, ir
->type
);
1309 this->result
= result
;
1311 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1312 fs_reg channel
= val
;
1330 channel
.reg_offset
+= swiz
;
1331 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1332 result
.reg_offset
++;
1337 fs_visitor::visit(ir_discard
*ir
)
1339 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1341 assert(ir
->condition
== NULL
); /* FINISHME */
1343 emit(fs_inst(FS_OPCODE_DISCARD_NOT
, temp
, reg_null_d
));
1344 emit(fs_inst(FS_OPCODE_DISCARD_AND
, reg_null_d
, temp
));
1345 kill_emitted
= true;
1349 fs_visitor::visit(ir_constant
*ir
)
1351 fs_reg
reg(this, ir
->type
);
1354 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1355 switch (ir
->type
->base_type
) {
1356 case GLSL_TYPE_FLOAT
:
1357 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1359 case GLSL_TYPE_UINT
:
1360 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1363 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1365 case GLSL_TYPE_BOOL
:
1366 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1369 assert(!"Non-float/uint/int/bool constant");
1376 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1378 ir_expression
*expr
= ir
->as_expression();
1384 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1385 assert(expr
->operands
[i
]->type
->is_scalar());
1387 expr
->operands
[i
]->accept(this);
1388 op
[i
] = this->result
;
1391 switch (expr
->operation
) {
1392 case ir_unop_logic_not
:
1393 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1)));
1394 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1397 case ir_binop_logic_xor
:
1398 inst
= emit(fs_inst(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]));
1399 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1402 case ir_binop_logic_or
:
1403 inst
= emit(fs_inst(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]));
1404 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1407 case ir_binop_logic_and
:
1408 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]));
1409 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1413 if (intel
->gen
>= 6) {
1414 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1415 op
[0], fs_reg(0.0f
)));
1417 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1419 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1423 if (intel
->gen
>= 6) {
1424 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0)));
1426 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1428 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1431 case ir_binop_greater
:
1432 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1433 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1435 case ir_binop_gequal
:
1436 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1437 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1440 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1441 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1443 case ir_binop_lequal
:
1444 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1445 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1447 case ir_binop_equal
:
1448 case ir_binop_all_equal
:
1449 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1450 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1452 case ir_binop_nequal
:
1453 case ir_binop_any_nequal
:
1454 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1455 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1458 assert(!"not reached");
1467 if (intel
->gen
>= 6) {
1468 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
,
1469 this->result
, fs_reg(1)));
1470 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1472 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, this->result
));
1473 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1478 * Emit a gen6 IF statement with the comparison folded into the IF
1482 fs_visitor::emit_if_gen6(ir_if
*ir
)
1484 ir_expression
*expr
= ir
->condition
->as_expression();
1491 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1492 assert(expr
->operands
[i
]->type
->is_scalar());
1494 expr
->operands
[i
]->accept(this);
1495 op
[i
] = this->result
;
1498 switch (expr
->operation
) {
1499 case ir_unop_logic_not
:
1500 inst
= emit(fs_inst(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(1)));
1501 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1504 case ir_binop_logic_xor
:
1505 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1506 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1509 case ir_binop_logic_or
:
1510 temp
= fs_reg(this, glsl_type::bool_type
);
1511 emit(fs_inst(BRW_OPCODE_OR
, temp
, op
[0], op
[1]));
1512 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1513 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1516 case ir_binop_logic_and
:
1517 temp
= fs_reg(this, glsl_type::bool_type
);
1518 emit(fs_inst(BRW_OPCODE_AND
, temp
, op
[0], op
[1]));
1519 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1520 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1524 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0)));
1525 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1529 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1530 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1533 case ir_binop_greater
:
1534 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1535 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1537 case ir_binop_gequal
:
1538 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1539 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1542 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1543 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1545 case ir_binop_lequal
:
1546 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1547 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1549 case ir_binop_equal
:
1550 case ir_binop_all_equal
:
1551 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1552 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1554 case ir_binop_nequal
:
1555 case ir_binop_any_nequal
:
1556 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1557 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1560 assert(!"not reached");
1561 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1562 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1569 ir
->condition
->accept(this);
1571 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0)));
1572 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1576 fs_visitor::visit(ir_if
*ir
)
1580 /* Don't point the annotation at the if statement, because then it plus
1581 * the then and else blocks get printed.
1583 this->base_ir
= ir
->condition
;
1585 if (intel
->gen
>= 6) {
1588 emit_bool_to_cond_code(ir
->condition
);
1590 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1591 inst
->predicated
= true;
1594 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1595 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1601 if (!ir
->else_instructions
.is_empty()) {
1602 emit(fs_inst(BRW_OPCODE_ELSE
));
1604 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1605 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1612 emit(fs_inst(BRW_OPCODE_ENDIF
));
1616 fs_visitor::visit(ir_loop
*ir
)
1618 fs_reg counter
= reg_undef
;
1621 this->base_ir
= ir
->counter
;
1622 ir
->counter
->accept(this);
1623 counter
= *(variable_storage(ir
->counter
));
1626 this->base_ir
= ir
->from
;
1627 ir
->from
->accept(this);
1629 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1633 emit(fs_inst(BRW_OPCODE_DO
));
1636 this->base_ir
= ir
->to
;
1637 ir
->to
->accept(this);
1639 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1640 counter
, this->result
));
1642 case ir_binop_equal
:
1643 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1645 case ir_binop_nequal
:
1646 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1648 case ir_binop_gequal
:
1649 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1651 case ir_binop_lequal
:
1652 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1654 case ir_binop_greater
:
1655 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1658 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1661 assert(!"not reached: unknown loop condition");
1666 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1667 inst
->predicated
= true;
1670 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1671 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1677 if (ir
->increment
) {
1678 this->base_ir
= ir
->increment
;
1679 ir
->increment
->accept(this);
1680 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1683 emit(fs_inst(BRW_OPCODE_WHILE
));
1687 fs_visitor::visit(ir_loop_jump
*ir
)
1690 case ir_loop_jump::jump_break
:
1691 emit(fs_inst(BRW_OPCODE_BREAK
));
1693 case ir_loop_jump::jump_continue
:
1694 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1700 fs_visitor::visit(ir_call
*ir
)
1702 assert(!"FINISHME");
1706 fs_visitor::visit(ir_return
*ir
)
1708 assert(!"FINISHME");
1712 fs_visitor::visit(ir_function
*ir
)
1714 /* Ignore function bodies other than main() -- we shouldn't see calls to
1715 * them since they should all be inlined before we get to ir_to_mesa.
1717 if (strcmp(ir
->name
, "main") == 0) {
1718 const ir_function_signature
*sig
;
1721 sig
= ir
->matching_signature(&empty
);
1725 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1726 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1735 fs_visitor::visit(ir_function_signature
*ir
)
1737 assert(!"not reached");
1742 fs_visitor::emit(fs_inst inst
)
1744 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1747 list_inst
->annotation
= this->current_annotation
;
1748 list_inst
->ir
= this->base_ir
;
1750 this->instructions
.push_tail(list_inst
);
1755 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1757 fs_visitor::emit_dummy_fs()
1759 /* Everyone's favorite color. */
1760 emit(fs_inst(BRW_OPCODE_MOV
,
1763 emit(fs_inst(BRW_OPCODE_MOV
,
1766 emit(fs_inst(BRW_OPCODE_MOV
,
1769 emit(fs_inst(BRW_OPCODE_MOV
,
1774 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1777 write
->base_mrf
= 0;
1780 /* The register location here is relative to the start of the URB
1781 * data. It will get adjusted to be a real location before
1782 * generate_code() time.
1785 fs_visitor::interp_reg(int location
, int channel
)
1787 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1788 int stride
= (channel
& 1) * 4;
1790 assert(urb_setup
[location
] != -1);
1792 return brw_vec1_grf(regnr
, stride
);
1795 /** Emits the interpolation for the varying inputs. */
1797 fs_visitor::emit_interpolation_setup_gen4()
1799 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1801 this->current_annotation
= "compute pixel centers";
1802 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1803 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1804 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1805 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1806 emit(fs_inst(BRW_OPCODE_ADD
,
1808 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1809 fs_reg(brw_imm_v(0x10101010))));
1810 emit(fs_inst(BRW_OPCODE_ADD
,
1812 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1813 fs_reg(brw_imm_v(0x11001100))));
1815 this->current_annotation
= "compute pixel deltas from v0";
1817 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1818 this->delta_y
= this->delta_x
;
1819 this->delta_y
.reg_offset
++;
1821 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1822 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1824 emit(fs_inst(BRW_OPCODE_ADD
,
1827 fs_reg(negate(brw_vec1_grf(1, 0)))));
1828 emit(fs_inst(BRW_OPCODE_ADD
,
1831 fs_reg(negate(brw_vec1_grf(1, 1)))));
1833 this->current_annotation
= "compute pos.w and 1/pos.w";
1834 /* Compute wpos.w. It's always in our setup, since it's needed to
1835 * interpolate the other attributes.
1837 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1838 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1839 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1840 /* Compute the pixel 1/W value from wpos.w. */
1841 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1842 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1843 this->current_annotation
= NULL
;
1846 /** Emits the interpolation for the varying inputs. */
1848 fs_visitor::emit_interpolation_setup_gen6()
1850 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1852 /* If the pixel centers end up used, the setup is the same as for gen4. */
1853 this->current_annotation
= "compute pixel centers";
1854 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1855 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1856 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1857 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1858 emit(fs_inst(BRW_OPCODE_ADD
,
1860 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1861 fs_reg(brw_imm_v(0x10101010))));
1862 emit(fs_inst(BRW_OPCODE_ADD
,
1864 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1865 fs_reg(brw_imm_v(0x11001100))));
1867 /* As of gen6, we can no longer mix float and int sources. We have
1868 * to turn the integer pixel centers into floats for their actual
1871 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1872 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1873 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
));
1874 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
));
1876 this->current_annotation
= "compute 1/pos.w";
1877 this->wpos_w
= fs_reg(brw_vec8_grf(c
->key
.source_w_reg
, 0));
1878 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1879 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1881 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1882 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1884 this->current_annotation
= NULL
;
1888 fs_visitor::emit_fb_writes()
1890 this->current_annotation
= "FB write header";
1891 GLboolean header_present
= GL_TRUE
;
1894 if (intel
->gen
>= 6 &&
1895 !this->kill_emitted
&&
1896 c
->key
.nr_color_regions
== 1) {
1897 header_present
= false;
1900 if (header_present
) {
1905 if (c
->key
.aa_dest_stencil_reg
) {
1906 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1907 fs_reg(brw_vec8_grf(c
->key
.aa_dest_stencil_reg
, 0))));
1910 /* Reserve space for color. It'll be filled in per MRT below. */
1914 if (c
->key
.source_depth_to_render_target
) {
1915 if (c
->key
.computes_depth
) {
1916 /* Hand over gl_FragDepth. */
1917 assert(this->frag_depth
);
1918 fs_reg depth
= *(variable_storage(this->frag_depth
));
1920 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
1922 /* Pass through the payload depth. */
1923 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1924 fs_reg(brw_vec8_grf(c
->key
.source_depth_reg
, 0))));
1928 if (c
->key
.dest_depth_reg
) {
1929 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1930 fs_reg(brw_vec8_grf(c
->key
.dest_depth_reg
, 0))));
1933 fs_reg color
= reg_undef
;
1934 if (this->frag_color
)
1935 color
= *(variable_storage(this->frag_color
));
1936 else if (this->frag_data
)
1937 color
= *(variable_storage(this->frag_data
));
1939 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1940 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1941 "FB write target %d",
1943 if (this->frag_color
|| this->frag_data
) {
1944 for (int i
= 0; i
< 4; i
++) {
1945 emit(fs_inst(BRW_OPCODE_MOV
,
1946 fs_reg(MRF
, color_mrf
+ i
),
1952 if (this->frag_color
)
1953 color
.reg_offset
-= 4;
1955 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1956 reg_undef
, reg_undef
));
1957 inst
->target
= target
;
1960 if (target
== c
->key
.nr_color_regions
- 1)
1962 inst
->header_present
= header_present
;
1965 if (c
->key
.nr_color_regions
== 0) {
1966 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1967 reg_undef
, reg_undef
));
1971 inst
->header_present
= header_present
;
1974 this->current_annotation
= NULL
;
1978 fs_visitor::generate_fb_write(fs_inst
*inst
)
1980 GLboolean eot
= inst
->eot
;
1981 struct brw_reg implied_header
;
1983 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1986 brw_push_insn_state(p
);
1987 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1988 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1990 if (inst
->header_present
) {
1991 if (intel
->gen
>= 6) {
1993 brw_message_reg(inst
->base_mrf
),
1994 brw_vec8_grf(0, 0));
1996 if (inst
->target
> 0) {
1997 /* Set the render target index for choosing BLEND_STATE. */
1998 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 2),
1999 BRW_REGISTER_TYPE_UD
),
2000 brw_imm_ud(inst
->target
));
2003 /* Clear viewport index, render target array index. */
2004 brw_AND(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 0),
2005 BRW_REGISTER_TYPE_UD
),
2006 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2007 brw_imm_ud(0xf7ff));
2009 implied_header
= brw_null_reg();
2011 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2015 brw_message_reg(inst
->base_mrf
+ 1),
2016 brw_vec8_grf(1, 0));
2018 implied_header
= brw_null_reg();
2021 brw_pop_insn_state(p
);
2024 8, /* dispatch_width */
2025 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
2035 fs_visitor::generate_linterp(fs_inst
*inst
,
2036 struct brw_reg dst
, struct brw_reg
*src
)
2038 struct brw_reg delta_x
= src
[0];
2039 struct brw_reg delta_y
= src
[1];
2040 struct brw_reg interp
= src
[2];
2043 delta_y
.nr
== delta_x
.nr
+ 1 &&
2044 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2045 brw_PLN(p
, dst
, interp
, delta_x
);
2047 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2048 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2053 fs_visitor::generate_math(fs_inst
*inst
,
2054 struct brw_reg dst
, struct brw_reg
*src
)
2058 switch (inst
->opcode
) {
2060 op
= BRW_MATH_FUNCTION_INV
;
2063 op
= BRW_MATH_FUNCTION_RSQ
;
2065 case FS_OPCODE_SQRT
:
2066 op
= BRW_MATH_FUNCTION_SQRT
;
2068 case FS_OPCODE_EXP2
:
2069 op
= BRW_MATH_FUNCTION_EXP
;
2071 case FS_OPCODE_LOG2
:
2072 op
= BRW_MATH_FUNCTION_LOG
;
2075 op
= BRW_MATH_FUNCTION_POW
;
2078 op
= BRW_MATH_FUNCTION_SIN
;
2081 op
= BRW_MATH_FUNCTION_COS
;
2084 assert(!"not reached: unknown math function");
2089 if (intel
->gen
>= 6) {
2090 assert(inst
->mlen
== 0);
2092 if (inst
->opcode
== FS_OPCODE_POW
) {
2093 brw_math2(p
, dst
, op
, src
[0], src
[1]);
2097 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2098 BRW_MATH_SATURATE_NONE
,
2100 BRW_MATH_DATA_VECTOR
,
2101 BRW_MATH_PRECISION_FULL
);
2104 assert(inst
->mlen
>= 1);
2108 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2109 BRW_MATH_SATURATE_NONE
,
2110 inst
->base_mrf
, src
[0],
2111 BRW_MATH_DATA_VECTOR
,
2112 BRW_MATH_PRECISION_FULL
);
2117 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
)
2121 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2123 if (intel
->gen
>= 5) {
2124 switch (inst
->opcode
) {
2126 if (inst
->shadow_compare
) {
2127 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2129 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2133 if (inst
->shadow_compare
) {
2134 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2136 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2141 switch (inst
->opcode
) {
2143 /* Note that G45 and older determines shadow compare and dispatch width
2144 * from message length for most messages.
2146 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2147 if (inst
->shadow_compare
) {
2148 assert(inst
->mlen
== 6);
2150 assert(inst
->mlen
<= 4);
2154 if (inst
->shadow_compare
) {
2155 assert(inst
->mlen
== 6);
2156 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2158 assert(inst
->mlen
== 9);
2159 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2160 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2165 assert(msg_type
!= -1);
2167 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2173 retype(dst
, BRW_REGISTER_TYPE_UW
),
2175 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2176 SURF_INDEX_TEXTURE(inst
->sampler
),
2188 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2191 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2193 * and we're trying to produce:
2196 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2197 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2198 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2199 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2200 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2201 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2202 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2203 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2205 * and add another set of two more subspans if in 16-pixel dispatch mode.
2207 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2208 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2209 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2210 * between each other. We could probably do it like ddx and swizzle the right
2211 * order later, but bail for now and just produce
2212 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2215 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2217 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2218 BRW_REGISTER_TYPE_F
,
2219 BRW_VERTICAL_STRIDE_2
,
2221 BRW_HORIZONTAL_STRIDE_0
,
2222 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2223 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2224 BRW_REGISTER_TYPE_F
,
2225 BRW_VERTICAL_STRIDE_2
,
2227 BRW_HORIZONTAL_STRIDE_0
,
2228 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2229 brw_ADD(p
, dst
, src0
, negate(src1
));
2233 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2235 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2236 BRW_REGISTER_TYPE_F
,
2237 BRW_VERTICAL_STRIDE_4
,
2239 BRW_HORIZONTAL_STRIDE_0
,
2240 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2241 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2242 BRW_REGISTER_TYPE_F
,
2243 BRW_VERTICAL_STRIDE_4
,
2245 BRW_HORIZONTAL_STRIDE_0
,
2246 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2247 brw_ADD(p
, dst
, src0
, negate(src1
));
2251 fs_visitor::generate_discard_not(fs_inst
*inst
, struct brw_reg mask
)
2253 if (intel
->gen
>= 6) {
2254 /* Gen6 no longer has the mask reg for us to just read the
2255 * active channels from. However, cmp updates just the channels
2256 * of the flag reg that are enabled, so we can get at the
2257 * channel enables that way. In this step, make a reg of ones
2260 brw_MOV(p
, mask
, brw_imm_ud(1));
2262 brw_push_insn_state(p
);
2263 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2264 brw_NOT(p
, mask
, brw_mask_reg(1)); /* IMASK */
2265 brw_pop_insn_state(p
);
2270 fs_visitor::generate_discard_and(fs_inst
*inst
, struct brw_reg mask
)
2272 if (intel
->gen
>= 6) {
2273 struct brw_reg f0
= brw_flag_reg();
2274 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
2276 brw_push_insn_state(p
);
2277 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2278 brw_MOV(p
, f0
, brw_imm_uw(0xffff)); /* inactive channels undiscarded */
2279 brw_pop_insn_state(p
);
2281 brw_CMP(p
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
2282 BRW_CONDITIONAL_Z
, mask
, brw_imm_ud(0)); /* active channels fail test */
2283 /* Undo CMP's whacking of predication*/
2284 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2286 brw_push_insn_state(p
);
2287 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2288 brw_AND(p
, g1
, f0
, g1
);
2289 brw_pop_insn_state(p
);
2291 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2293 mask
= brw_uw1_reg(mask
.file
, mask
.nr
, 0);
2295 brw_push_insn_state(p
);
2296 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2297 brw_AND(p
, g0
, mask
, g0
);
2298 brw_pop_insn_state(p
);
2303 fs_visitor::generate_spill(fs_inst
*inst
, struct brw_reg src
)
2305 assert(inst
->mlen
!= 0);
2308 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
2309 retype(src
, BRW_REGISTER_TYPE_UD
));
2310 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
), 1,
2315 fs_visitor::generate_unspill(fs_inst
*inst
, struct brw_reg dst
)
2317 assert(inst
->mlen
!= 0);
2319 /* Clear any post destination dependencies that would be ignored by
2320 * the block read. See the B-Spec for pre-gen5 send instruction.
2322 * This could use a better solution, since texture sampling and
2323 * math reads could potentially run into it as well -- anywhere
2324 * that we have a SEND with a destination that is a register that
2325 * was written but not read within the last N instructions (what's
2326 * N? unsure). This is rare because of dead code elimination, but
2329 if (intel
->gen
== 4 && !intel
->is_g4x
)
2330 brw_MOV(p
, brw_null_reg(), dst
);
2332 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
), 1,
2335 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2336 /* gen4 errata: destination from a send can't be used as a
2337 * destination until it's been read. Just read it so we don't
2340 brw_MOV(p
, brw_null_reg(), dst
);
2346 fs_visitor::generate_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
)
2348 assert(inst
->mlen
!= 0);
2350 /* Clear any post destination dependencies that would be ignored by
2351 * the block read. See the B-Spec for pre-gen5 send instruction.
2353 * This could use a better solution, since texture sampling and
2354 * math reads could potentially run into it as well -- anywhere
2355 * that we have a SEND with a destination that is a register that
2356 * was written but not read within the last N instructions (what's
2357 * N? unsure). This is rare because of dead code elimination, but
2360 if (intel
->gen
== 4 && !intel
->is_g4x
)
2361 brw_MOV(p
, brw_null_reg(), dst
);
2363 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
2364 inst
->offset
, SURF_INDEX_FRAG_CONST_BUFFER
);
2366 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2367 /* gen4 errata: destination from a send can't be used as a
2368 * destination until it's been read. Just read it so we don't
2371 brw_MOV(p
, brw_null_reg(), dst
);
2376 fs_visitor::assign_curb_setup()
2378 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
2379 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2381 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2382 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2383 fs_inst
*inst
= (fs_inst
*)iter
.get();
2385 for (unsigned int i
= 0; i
< 3; i
++) {
2386 if (inst
->src
[i
].file
== UNIFORM
) {
2387 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2388 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2392 inst
->src
[i
].file
= FIXED_HW_REG
;
2393 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
2400 fs_visitor::calculate_urb_setup()
2402 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2407 /* Figure out where each of the incoming setup attributes lands. */
2408 if (intel
->gen
>= 6) {
2409 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2410 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2411 urb_setup
[i
] = urb_next
++;
2415 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2416 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2417 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2420 if (i
>= VERT_RESULT_VAR0
)
2421 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2422 else if (i
<= VERT_RESULT_TEX7
)
2428 urb_setup
[fp_index
] = urb_next
++;
2433 /* Each attribute is 4 setup channels, each of which is half a reg. */
2434 c
->prog_data
.urb_read_length
= urb_next
* 2;
2438 fs_visitor::assign_urb_setup()
2440 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2442 /* Offset all the urb_setup[] index by the actual position of the
2443 * setup regs, now that the location of the constants has been chosen.
2445 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2446 fs_inst
*inst
= (fs_inst
*)iter
.get();
2448 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2451 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2453 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2456 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2460 * Split large virtual GRFs into separate components if we can.
2462 * This is mostly duplicated with what brw_fs_vector_splitting does,
2463 * but that's really conservative because it's afraid of doing
2464 * splitting that doesn't result in real progress after the rest of
2465 * the optimization phases, which would cause infinite looping in
2466 * optimization. We can do it once here, safely. This also has the
2467 * opportunity to split interpolated values, or maybe even uniforms,
2468 * which we don't have at the IR level.
2470 * We want to split, because virtual GRFs are what we register
2471 * allocate and spill (due to contiguousness requirements for some
2472 * instructions), and they're what we naturally generate in the
2473 * codegen process, but most virtual GRFs don't actually need to be
2474 * contiguous sets of GRFs. If we split, we'll end up with reduced
2475 * live intervals and better dead code elimination and coalescing.
2478 fs_visitor::split_virtual_grfs()
2480 int num_vars
= this->virtual_grf_next
;
2481 bool split_grf
[num_vars
];
2482 int new_virtual_grf
[num_vars
];
2484 /* Try to split anything > 0 sized. */
2485 for (int i
= 0; i
< num_vars
; i
++) {
2486 if (this->virtual_grf_sizes
[i
] != 1)
2487 split_grf
[i
] = true;
2489 split_grf
[i
] = false;
2493 /* PLN opcodes rely on the delta_xy being contiguous. */
2494 split_grf
[this->delta_x
.reg
] = false;
2497 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2498 fs_inst
*inst
= (fs_inst
*)iter
.get();
2500 /* Texturing produces 4 contiguous registers, so no splitting. */
2501 if ((inst
->opcode
== FS_OPCODE_TEX
||
2502 inst
->opcode
== FS_OPCODE_TXB
||
2503 inst
->opcode
== FS_OPCODE_TXL
) &&
2504 inst
->dst
.file
== GRF
) {
2505 split_grf
[inst
->dst
.reg
] = false;
2509 /* Allocate new space for split regs. Note that the virtual
2510 * numbers will be contiguous.
2512 for (int i
= 0; i
< num_vars
; i
++) {
2514 new_virtual_grf
[i
] = virtual_grf_alloc(1);
2515 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
2516 int reg
= virtual_grf_alloc(1);
2517 assert(reg
== new_virtual_grf
[i
] + j
- 1);
2519 this->virtual_grf_sizes
[i
] = 1;
2523 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2524 fs_inst
*inst
= (fs_inst
*)iter
.get();
2526 if (inst
->dst
.file
== GRF
&&
2527 split_grf
[inst
->dst
.reg
] &&
2528 inst
->dst
.reg_offset
!= 0) {
2529 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
2530 inst
->dst
.reg_offset
- 1);
2531 inst
->dst
.reg_offset
= 0;
2533 for (int i
= 0; i
< 3; i
++) {
2534 if (inst
->src
[i
].file
== GRF
&&
2535 split_grf
[inst
->src
[i
].reg
] &&
2536 inst
->src
[i
].reg_offset
!= 0) {
2537 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
2538 inst
->src
[i
].reg_offset
- 1);
2539 inst
->src
[i
].reg_offset
= 0;
2546 * Choose accesses from the UNIFORM file to demote to using the pull
2549 * We allow a fragment shader to have more than the specified minimum
2550 * maximum number of fragment shader uniform components (64). If
2551 * there are too many of these, they'd fill up all of register space.
2552 * So, this will push some of them out to the pull constant buffer and
2553 * update the program to load them.
2556 fs_visitor::setup_pull_constants()
2558 /* Only allow 16 registers (128 uniform components) as push constants. */
2559 unsigned int max_uniform_components
= 16 * 8;
2560 if (c
->prog_data
.nr_params
<= max_uniform_components
)
2563 /* Just demote the end of the list. We could probably do better
2564 * here, demoting things that are rarely used in the program first.
2566 int pull_uniform_base
= max_uniform_components
;
2567 int pull_uniform_count
= c
->prog_data
.nr_params
- pull_uniform_base
;
2569 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2570 fs_inst
*inst
= (fs_inst
*)iter
.get();
2572 for (int i
= 0; i
< 3; i
++) {
2573 if (inst
->src
[i
].file
!= UNIFORM
)
2576 int uniform_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2577 if (uniform_nr
< pull_uniform_base
)
2580 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
2581 fs_inst
*pull
= new(mem_ctx
) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
2583 pull
->offset
= ((uniform_nr
- pull_uniform_base
) * 4) & ~15;
2584 pull
->ir
= inst
->ir
;
2585 pull
->annotation
= inst
->annotation
;
2586 pull
->base_mrf
= 14;
2589 inst
->insert_before(pull
);
2591 inst
->src
[i
].file
= GRF
;
2592 inst
->src
[i
].reg
= dst
.reg
;
2593 inst
->src
[i
].reg_offset
= 0;
2594 inst
->src
[i
].smear
= (uniform_nr
- pull_uniform_base
) & 3;
2598 for (int i
= 0; i
< pull_uniform_count
; i
++) {
2599 c
->prog_data
.pull_param
[i
] = c
->prog_data
.param
[pull_uniform_base
+ i
];
2600 c
->prog_data
.pull_param_convert
[i
] =
2601 c
->prog_data
.param_convert
[pull_uniform_base
+ i
];
2603 c
->prog_data
.nr_params
-= pull_uniform_count
;
2604 c
->prog_data
.nr_pull_params
= pull_uniform_count
;
2608 fs_visitor::calculate_live_intervals()
2610 int num_vars
= this->virtual_grf_next
;
2611 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2612 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2615 int bb_header_ip
= 0;
2617 for (int i
= 0; i
< num_vars
; i
++) {
2623 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2624 fs_inst
*inst
= (fs_inst
*)iter
.get();
2626 if (inst
->opcode
== BRW_OPCODE_DO
) {
2627 if (loop_depth
++ == 0)
2629 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2632 if (loop_depth
== 0) {
2633 /* Patches up the use of vars marked for being live across
2636 for (int i
= 0; i
< num_vars
; i
++) {
2637 if (use
[i
] == loop_start
) {
2643 for (unsigned int i
= 0; i
< 3; i
++) {
2644 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2645 int reg
= inst
->src
[i
].reg
;
2647 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2648 def
[reg
] >= bb_header_ip
)) {
2651 def
[reg
] = MIN2(loop_start
, def
[reg
]);
2652 use
[reg
] = loop_start
;
2654 /* Nobody else is going to go smash our start to
2655 * later in the loop now, because def[reg] now
2656 * points before the bb header.
2661 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2662 int reg
= inst
->dst
.reg
;
2664 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2665 !inst
->predicated
)) {
2666 def
[reg
] = MIN2(def
[reg
], ip
);
2668 def
[reg
] = MIN2(def
[reg
], loop_start
);
2675 /* Set the basic block header IP. This is used for determining
2676 * if a complete def of single-register virtual GRF in a loop
2677 * dominates a use in the same basic block. It's a quick way to
2678 * reduce the live interval range of most register used in a
2681 if (inst
->opcode
== BRW_OPCODE_IF
||
2682 inst
->opcode
== BRW_OPCODE_ELSE
||
2683 inst
->opcode
== BRW_OPCODE_ENDIF
||
2684 inst
->opcode
== BRW_OPCODE_DO
||
2685 inst
->opcode
== BRW_OPCODE_WHILE
||
2686 inst
->opcode
== BRW_OPCODE_BREAK
||
2687 inst
->opcode
== BRW_OPCODE_CONTINUE
) {
2692 talloc_free(this->virtual_grf_def
);
2693 talloc_free(this->virtual_grf_use
);
2694 this->virtual_grf_def
= def
;
2695 this->virtual_grf_use
= use
;
2699 * Attempts to move immediate constants into the immediate
2700 * constant slot of following instructions.
2702 * Immediate constants are a bit tricky -- they have to be in the last
2703 * operand slot, you can't do abs/negate on them,
2707 fs_visitor::propagate_constants()
2709 bool progress
= false;
2711 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2712 fs_inst
*inst
= (fs_inst
*)iter
.get();
2714 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2716 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2717 inst
->dst
.type
!= inst
->src
[0].type
)
2720 /* Don't bother with cases where we should have had the
2721 * operation on the constant folded in GLSL already.
2726 /* Found a move of a constant to a GRF. Find anything else using the GRF
2727 * before it's written, and replace it with the constant if we can.
2729 exec_list_iterator scan_iter
= iter
;
2731 for (; scan_iter
.has_next(); scan_iter
.next()) {
2732 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2734 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2735 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2736 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2737 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2741 for (int i
= 2; i
>= 0; i
--) {
2742 if (scan_inst
->src
[i
].file
!= GRF
||
2743 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2744 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2747 /* Don't bother with cases where we should have had the
2748 * operation on the constant folded in GLSL already.
2750 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2753 switch (scan_inst
->opcode
) {
2754 case BRW_OPCODE_MOV
:
2755 scan_inst
->src
[i
] = inst
->src
[0];
2759 case BRW_OPCODE_MUL
:
2760 case BRW_OPCODE_ADD
:
2762 scan_inst
->src
[i
] = inst
->src
[0];
2764 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2765 /* Fit this constant in by commuting the operands */
2766 scan_inst
->src
[0] = scan_inst
->src
[1];
2767 scan_inst
->src
[1] = inst
->src
[0];
2770 case BRW_OPCODE_CMP
:
2772 scan_inst
->src
[i
] = inst
->src
[0];
2778 if (scan_inst
->dst
.file
== GRF
&&
2779 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2780 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2781 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2790 * Must be called after calculate_live_intervales() to remove unused
2791 * writes to registers -- register allocation will fail otherwise
2792 * because something deffed but not used won't be considered to
2793 * interfere with other regs.
2796 fs_visitor::dead_code_eliminate()
2798 bool progress
= false;
2799 int num_vars
= this->virtual_grf_next
;
2800 bool dead
[num_vars
];
2802 for (int i
= 0; i
< num_vars
; i
++) {
2803 dead
[i
] = this->virtual_grf_def
[i
] >= this->virtual_grf_use
[i
];
2806 /* Mark off its interval so it won't interfere with anything. */
2807 this->virtual_grf_def
[i
] = -1;
2808 this->virtual_grf_use
[i
] = -1;
2812 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2813 fs_inst
*inst
= (fs_inst
*)iter
.get();
2815 if (inst
->dst
.file
== GRF
&& dead
[inst
->dst
.reg
]) {
2825 fs_visitor::register_coalesce()
2827 bool progress
= false;
2829 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2830 fs_inst
*inst
= (fs_inst
*)iter
.get();
2832 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2835 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
2836 inst
->dst
.type
!= inst
->src
[0].type
)
2839 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
2840 * them: check for no writes to either one until the exit of the
2843 bool interfered
= false;
2844 exec_list_iterator scan_iter
= iter
;
2846 for (; scan_iter
.has_next(); scan_iter
.next()) {
2847 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2849 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2850 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2851 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2857 if (scan_inst
->dst
.file
== GRF
) {
2858 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2859 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2860 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2864 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
2865 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
2866 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2876 /* Update live interval so we don't have to recalculate. */
2877 this->virtual_grf_use
[inst
->src
[0].reg
] = MAX2(virtual_grf_use
[inst
->src
[0].reg
],
2878 virtual_grf_use
[inst
->dst
.reg
]);
2880 /* Rewrite the later usage to point at the source of the move to
2883 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
2885 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2887 for (int i
= 0; i
< 3; i
++) {
2888 if (scan_inst
->src
[i
].file
== GRF
&&
2889 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
2890 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
2891 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
2892 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
2893 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
2894 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
2895 scan_inst
->src
[i
].smear
= inst
->src
[0].smear
;
2909 fs_visitor::compute_to_mrf()
2911 bool progress
= false;
2914 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2915 fs_inst
*inst
= (fs_inst
*)iter
.get();
2920 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2922 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2923 inst
->dst
.type
!= inst
->src
[0].type
||
2924 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
2927 /* Can't compute-to-MRF this GRF if someone else was going to
2930 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
2933 /* Found a move of a GRF to a MRF. Let's see if we can go
2934 * rewrite the thing that made this GRF to write into the MRF.
2938 for (scan_inst
= (fs_inst
*)inst
->prev
;
2939 scan_inst
->prev
!= NULL
;
2940 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2941 /* We don't handle flow control here. Most computation of
2942 * values that end up in MRFs are shortly before the MRF
2945 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2946 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2947 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2951 /* You can't read from an MRF, so if someone else reads our
2952 * MRF's source GRF that we wanted to rewrite, that stops us.
2954 bool interfered
= false;
2955 for (int i
= 0; i
< 3; i
++) {
2956 if (scan_inst
->src
[i
].file
== GRF
&&
2957 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2958 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2965 if (scan_inst
->dst
.file
== MRF
&&
2966 scan_inst
->dst
.hw_reg
== inst
->dst
.hw_reg
) {
2967 /* Somebody else wrote our MRF here, so we can't can't
2968 * compute-to-MRF before that.
2973 if (scan_inst
->mlen
> 0) {
2974 /* Found a SEND instruction, which will do some amount of
2975 * implied write that may overwrite our MRF that we were
2976 * hoping to compute-to-MRF somewhere above it. Nothing
2977 * we have implied-writes more than 2 MRFs from base_mrf,
2980 int implied_write_len
= MIN2(scan_inst
->mlen
, 2);
2981 if (inst
->dst
.hw_reg
>= scan_inst
->base_mrf
&&
2982 inst
->dst
.hw_reg
< scan_inst
->base_mrf
+ implied_write_len
) {
2987 if (scan_inst
->dst
.file
== GRF
&&
2988 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2989 /* Found the last thing to write our reg we want to turn
2990 * into a compute-to-MRF.
2993 if (scan_inst
->opcode
== FS_OPCODE_TEX
) {
2994 /* texturing writes several continuous regs, so we can't
2995 * compute-to-mrf that.
3000 /* If it's predicated, it (probably) didn't populate all
3003 if (scan_inst
->predicated
)
3006 /* SEND instructions can't have MRF as a destination. */
3007 if (scan_inst
->mlen
)
3010 if (intel
->gen
>= 6) {
3011 /* gen6 math instructions must have the destination be
3012 * GRF, so no compute-to-MRF for them.
3014 if (scan_inst
->opcode
== FS_OPCODE_RCP
||
3015 scan_inst
->opcode
== FS_OPCODE_RSQ
||
3016 scan_inst
->opcode
== FS_OPCODE_SQRT
||
3017 scan_inst
->opcode
== FS_OPCODE_EXP2
||
3018 scan_inst
->opcode
== FS_OPCODE_LOG2
||
3019 scan_inst
->opcode
== FS_OPCODE_SIN
||
3020 scan_inst
->opcode
== FS_OPCODE_COS
||
3021 scan_inst
->opcode
== FS_OPCODE_POW
) {
3026 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
3027 /* Found the creator of our MRF's source value. */
3034 scan_inst
->dst
.file
= MRF
;
3035 scan_inst
->dst
.hw_reg
= inst
->dst
.hw_reg
;
3036 scan_inst
->saturate
|= inst
->saturate
;
3046 fs_visitor::virtual_grf_interferes(int a
, int b
)
3048 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
3049 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
3051 /* For dead code, just check if the def interferes with the other range. */
3052 if (this->virtual_grf_use
[a
] == -1) {
3053 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
3054 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
3056 if (this->virtual_grf_use
[b
] == -1) {
3057 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
3058 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
3064 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
3066 struct brw_reg brw_reg
;
3068 switch (reg
->file
) {
3072 if (reg
->smear
== -1) {
3073 brw_reg
= brw_vec8_reg(reg
->file
,
3076 brw_reg
= brw_vec1_reg(reg
->file
,
3077 reg
->hw_reg
, reg
->smear
);
3079 brw_reg
= retype(brw_reg
, reg
->type
);
3082 switch (reg
->type
) {
3083 case BRW_REGISTER_TYPE_F
:
3084 brw_reg
= brw_imm_f(reg
->imm
.f
);
3086 case BRW_REGISTER_TYPE_D
:
3087 brw_reg
= brw_imm_d(reg
->imm
.i
);
3089 case BRW_REGISTER_TYPE_UD
:
3090 brw_reg
= brw_imm_ud(reg
->imm
.u
);
3093 assert(!"not reached");
3098 brw_reg
= reg
->fixed_hw_reg
;
3101 /* Probably unused. */
3102 brw_reg
= brw_null_reg();
3105 assert(!"not reached");
3106 brw_reg
= brw_null_reg();
3110 brw_reg
= brw_abs(brw_reg
);
3112 brw_reg
= negate(brw_reg
);
3118 fs_visitor::generate_code()
3120 int last_native_inst
= 0;
3121 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
3122 int if_stack_depth
= 0, loop_stack_depth
= 0;
3123 int if_depth_in_loop
[16];
3124 const char *last_annotation_string
= NULL
;
3125 ir_instruction
*last_annotation_ir
= NULL
;
3127 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3128 printf("Native code for fragment shader %d:\n",
3129 ctx
->Shader
.CurrentFragmentProgram
->Name
);
3132 if_depth_in_loop
[loop_stack_depth
] = 0;
3134 memset(&if_stack
, 0, sizeof(if_stack
));
3135 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3136 fs_inst
*inst
= (fs_inst
*)iter
.get();
3137 struct brw_reg src
[3], dst
;
3139 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3140 if (last_annotation_ir
!= inst
->ir
) {
3141 last_annotation_ir
= inst
->ir
;
3142 if (last_annotation_ir
) {
3144 last_annotation_ir
->print();
3148 if (last_annotation_string
!= inst
->annotation
) {
3149 last_annotation_string
= inst
->annotation
;
3150 if (last_annotation_string
)
3151 printf(" %s\n", last_annotation_string
);
3155 for (unsigned int i
= 0; i
< 3; i
++) {
3156 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
3158 dst
= brw_reg_from_fs_reg(&inst
->dst
);
3160 brw_set_conditionalmod(p
, inst
->conditional_mod
);
3161 brw_set_predicate_control(p
, inst
->predicated
);
3163 switch (inst
->opcode
) {
3164 case BRW_OPCODE_MOV
:
3165 brw_MOV(p
, dst
, src
[0]);
3167 case BRW_OPCODE_ADD
:
3168 brw_ADD(p
, dst
, src
[0], src
[1]);
3170 case BRW_OPCODE_MUL
:
3171 brw_MUL(p
, dst
, src
[0], src
[1]);
3174 case BRW_OPCODE_FRC
:
3175 brw_FRC(p
, dst
, src
[0]);
3177 case BRW_OPCODE_RNDD
:
3178 brw_RNDD(p
, dst
, src
[0]);
3180 case BRW_OPCODE_RNDE
:
3181 brw_RNDE(p
, dst
, src
[0]);
3183 case BRW_OPCODE_RNDZ
:
3184 brw_RNDZ(p
, dst
, src
[0]);
3187 case BRW_OPCODE_AND
:
3188 brw_AND(p
, dst
, src
[0], src
[1]);
3191 brw_OR(p
, dst
, src
[0], src
[1]);
3193 case BRW_OPCODE_XOR
:
3194 brw_XOR(p
, dst
, src
[0], src
[1]);
3196 case BRW_OPCODE_NOT
:
3197 brw_NOT(p
, dst
, src
[0]);
3199 case BRW_OPCODE_ASR
:
3200 brw_ASR(p
, dst
, src
[0], src
[1]);
3202 case BRW_OPCODE_SHR
:
3203 brw_SHR(p
, dst
, src
[0], src
[1]);
3205 case BRW_OPCODE_SHL
:
3206 brw_SHL(p
, dst
, src
[0], src
[1]);
3209 case BRW_OPCODE_CMP
:
3210 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
3212 case BRW_OPCODE_SEL
:
3213 brw_SEL(p
, dst
, src
[0], src
[1]);
3217 assert(if_stack_depth
< 16);
3218 if (inst
->src
[0].file
!= BAD_FILE
) {
3219 assert(intel
->gen
>= 6);
3220 if_stack
[if_stack_depth
] = brw_IF_gen6(p
, inst
->conditional_mod
, src
[0], src
[1]);
3222 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
3224 if_depth_in_loop
[loop_stack_depth
]++;
3228 case BRW_OPCODE_ELSE
:
3229 if_stack
[if_stack_depth
- 1] =
3230 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
3232 case BRW_OPCODE_ENDIF
:
3234 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
3235 if_depth_in_loop
[loop_stack_depth
]--;
3239 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
3240 if_depth_in_loop
[loop_stack_depth
] = 0;
3243 case BRW_OPCODE_BREAK
:
3244 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
3245 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3247 case BRW_OPCODE_CONTINUE
:
3248 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
3249 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3252 case BRW_OPCODE_WHILE
: {
3253 struct brw_instruction
*inst0
, *inst1
;
3256 if (intel
->gen
>= 5)
3259 assert(loop_stack_depth
> 0);
3261 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
3262 /* patch all the BREAK/CONT instructions from last BGNLOOP */
3263 while (inst0
> loop_stack
[loop_stack_depth
]) {
3265 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
3266 inst0
->bits3
.if_else
.jump_count
== 0) {
3267 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
3269 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
3270 inst0
->bits3
.if_else
.jump_count
== 0) {
3271 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
3279 case FS_OPCODE_SQRT
:
3280 case FS_OPCODE_EXP2
:
3281 case FS_OPCODE_LOG2
:
3285 generate_math(inst
, dst
, src
);
3287 case FS_OPCODE_LINTERP
:
3288 generate_linterp(inst
, dst
, src
);
3293 generate_tex(inst
, dst
);
3295 case FS_OPCODE_DISCARD_NOT
:
3296 generate_discard_not(inst
, dst
);
3298 case FS_OPCODE_DISCARD_AND
:
3299 generate_discard_and(inst
, src
[0]);
3302 generate_ddx(inst
, dst
, src
[0]);
3305 generate_ddy(inst
, dst
, src
[0]);
3308 case FS_OPCODE_SPILL
:
3309 generate_spill(inst
, src
[0]);
3312 case FS_OPCODE_UNSPILL
:
3313 generate_unspill(inst
, dst
);
3316 case FS_OPCODE_PULL_CONSTANT_LOAD
:
3317 generate_pull_constant_load(inst
, dst
);
3320 case FS_OPCODE_FB_WRITE
:
3321 generate_fb_write(inst
);
3324 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
3325 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
3326 brw_opcodes
[inst
->opcode
].name
);
3328 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
3333 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3334 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
3336 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3337 ((uint32_t *)&p
->store
[i
])[3],
3338 ((uint32_t *)&p
->store
[i
])[2],
3339 ((uint32_t *)&p
->store
[i
])[1],
3340 ((uint32_t *)&p
->store
[i
])[0]);
3342 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3347 last_native_inst
= p
->nr_insn
;
3352 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
3354 struct intel_context
*intel
= &brw
->intel
;
3355 struct gl_context
*ctx
= &intel
->ctx
;
3356 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentFragmentProgram
;
3361 struct brw_shader
*shader
=
3362 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3366 /* We always use 8-wide mode, at least for now. For one, flow
3367 * control only works in 8-wide. Also, when we're fragment shader
3368 * bound, we're almost always under register pressure as well, so
3369 * 8-wide would save us from the performance cliff of spilling
3372 c
->dispatch_width
= 8;
3374 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3375 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3376 _mesa_print_ir(shader
->ir
, NULL
);
3380 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3382 fs_visitor
v(c
, shader
);
3387 v
.calculate_urb_setup();
3389 v
.emit_interpolation_setup_gen4();
3391 v
.emit_interpolation_setup_gen6();
3393 /* Generate FS IR for main(). (the visitor only descends into
3394 * functions called "main").
3396 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3397 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3404 v
.split_virtual_grfs();
3405 v
.setup_pull_constants();
3407 v
.assign_curb_setup();
3408 v
.assign_urb_setup();
3413 v
.calculate_live_intervals();
3414 progress
= v
.propagate_constants() || progress
;
3415 progress
= v
.register_coalesce() || progress
;
3416 progress
= v
.compute_to_mrf() || progress
;
3417 progress
= v
.dead_code_eliminate() || progress
;
3421 /* Debug of register spilling: Go spill everything. */
3422 int virtual_grf_count
= v
.virtual_grf_next
;
3423 for (int i
= 1; i
< virtual_grf_count
; i
++) {
3426 v
.calculate_live_intervals();
3430 v
.assign_regs_trivial();
3432 while (!v
.assign_regs()) {
3436 v
.calculate_live_intervals();
3444 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3449 c
->prog_data
.total_grf
= v
.grf_used
;