2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "brw_dead_control_flow.h"
47 #include "main/uniforms.h"
48 #include "brw_fs_live_variables.h"
49 #include "glsl/glsl_types.h"
50 #include "program/sampler.h"
55 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
56 const fs_reg
*src
, unsigned sources
)
58 memset(this, 0, sizeof(*this));
60 this->src
= new fs_reg
[MAX2(sources
, 3)];
61 for (unsigned i
= 0; i
< sources
; i
++)
62 this->src
[i
] = src
[i
];
64 this->opcode
= opcode
;
66 this->sources
= sources
;
67 this->exec_size
= exec_size
;
69 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
71 assert(this->exec_size
!= 0);
73 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
75 /* This will be the case for almost all instructions. */
81 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
85 this->regs_written
= 0;
89 unreachable("Invalid destination register file");
91 unreachable("Invalid register file");
94 this->writes_accumulator
= false;
99 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
104 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
107 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
109 init(opcode
, exec_size
, dst
, NULL
, 0);
112 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
115 const fs_reg src
[1] = { src0
};
116 init(opcode
, exec_size
, dst
, src
, 1);
119 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
120 const fs_reg
&src0
, const fs_reg
&src1
)
122 const fs_reg src
[2] = { src0
, src1
};
123 init(opcode
, exec_size
, dst
, src
, 2);
126 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
127 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
129 const fs_reg src
[3] = { src0
, src1
, src2
};
130 init(opcode
, exec_size
, dst
, src
, 3);
133 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
134 const fs_reg src
[], unsigned sources
)
136 init(opcode
, exec_width
, dst
, src
, sources
);
139 fs_inst::fs_inst(const fs_inst
&that
)
141 memcpy(this, &that
, sizeof(that
));
143 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
145 for (unsigned i
= 0; i
< that
.sources
; i
++)
146 this->src
[i
] = that
.src
[i
];
155 fs_inst::resize_sources(uint8_t num_sources
)
157 if (this->sources
!= num_sources
) {
158 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
160 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
161 src
[i
] = this->src
[i
];
165 this->sources
= num_sources
;
170 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
172 const fs_reg
&surf_index
,
173 const fs_reg
&varying_offset
,
174 uint32_t const_offset
)
176 /* We have our constant surface use a pitch of 4 bytes, so our index can
177 * be any component of a vector, and then we load 4 contiguous
178 * components starting from that.
180 * We break down the const_offset to a portion added to the variable
181 * offset and a portion done using reg_offset, which means that if you
182 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
183 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
184 * CSE can later notice that those loads are all the same and eliminate
185 * the redundant ones.
187 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
188 bld
.ADD(vec4_offset
, varying_offset
, fs_reg(const_offset
& ~3));
191 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
192 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
193 * u, v, r) as parameters, or we can just use the SIMD16 message
194 * consisting of (header, u). We choose the second, at the cost of a
195 * longer return length.
201 if (devinfo
->gen
>= 7)
202 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
204 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
206 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
207 fs_reg vec4_result
= fs_reg(GRF
, alloc
.allocate(regs_written
), dst
.type
);
208 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
209 inst
->regs_written
= regs_written
;
211 if (devinfo
->gen
< 7) {
213 inst
->header_size
= 1;
214 if (devinfo
->gen
== 4)
217 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
220 bld
.MOV(dst
, offset(vec4_result
, bld
, (const_offset
& 3) * scale
));
224 * A helper for MOV generation for fixing up broken hardware SEND dependency
228 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
230 /* The caller always wants uncompressed to emit the minimal extra
231 * dependencies, and to avoid having to deal with aligning its regs to 2.
233 const fs_builder ubld
= bld
.annotate("send dependency resolve")
236 ubld
.MOV(ubld
.null_reg_f(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
240 fs_inst::equals(fs_inst
*inst
) const
242 return (opcode
== inst
->opcode
&&
243 dst
.equals(inst
->dst
) &&
244 src
[0].equals(inst
->src
[0]) &&
245 src
[1].equals(inst
->src
[1]) &&
246 src
[2].equals(inst
->src
[2]) &&
247 saturate
== inst
->saturate
&&
248 predicate
== inst
->predicate
&&
249 conditional_mod
== inst
->conditional_mod
&&
250 mlen
== inst
->mlen
&&
251 base_mrf
== inst
->base_mrf
&&
252 target
== inst
->target
&&
254 header_size
== inst
->header_size
&&
255 shadow_compare
== inst
->shadow_compare
&&
256 exec_size
== inst
->exec_size
&&
257 offset
== inst
->offset
);
261 fs_inst::overwrites_reg(const fs_reg
®
) const
263 return reg
.in_range(dst
, regs_written
);
267 fs_inst::is_send_from_grf() const
270 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
271 case SHADER_OPCODE_SHADER_TIME_ADD
:
272 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
273 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
274 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
275 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
276 case SHADER_OPCODE_UNTYPED_ATOMIC
:
277 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
278 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
279 case SHADER_OPCODE_TYPED_ATOMIC
:
280 case SHADER_OPCODE_TYPED_SURFACE_READ
:
281 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
282 case SHADER_OPCODE_URB_WRITE_SIMD8
:
284 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
285 return src
[1].file
== GRF
;
286 case FS_OPCODE_FB_WRITE
:
287 return src
[0].file
== GRF
;
290 return src
[0].file
== GRF
;
297 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
299 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
302 fs_reg reg
= this->src
[0];
303 if (reg
.file
!= GRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
306 if (grf_alloc
.sizes
[reg
.reg
] != this->regs_written
)
309 for (int i
= 0; i
< this->sources
; i
++) {
310 reg
.type
= this->src
[i
].type
;
311 if (!this->src
[i
].equals(reg
))
314 if (i
< this->header_size
) {
317 reg
.reg_offset
+= this->exec_size
/ 8;
325 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
327 if (devinfo
->gen
== 6 && is_math())
330 if (is_send_from_grf())
333 if (!backend_instruction::can_do_source_mods())
340 fs_inst::has_side_effects() const
342 return this->eot
|| backend_instruction::has_side_effects();
348 memset(this, 0, sizeof(*this));
352 /** Generic unset register constructor. */
356 this->file
= BAD_FILE
;
359 /** Immediate value constructor. */
360 fs_reg::fs_reg(float f
)
364 this->type
= BRW_REGISTER_TYPE_F
;
366 this->fixed_hw_reg
.dw1
.f
= f
;
369 /** Immediate value constructor. */
370 fs_reg::fs_reg(int32_t i
)
374 this->type
= BRW_REGISTER_TYPE_D
;
376 this->fixed_hw_reg
.dw1
.d
= i
;
379 /** Immediate value constructor. */
380 fs_reg::fs_reg(uint32_t u
)
384 this->type
= BRW_REGISTER_TYPE_UD
;
386 this->fixed_hw_reg
.dw1
.ud
= u
;
389 /** Vector float immediate value constructor. */
390 fs_reg::fs_reg(uint8_t vf
[4])
394 this->type
= BRW_REGISTER_TYPE_VF
;
395 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
398 /** Vector float immediate value constructor. */
399 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
403 this->type
= BRW_REGISTER_TYPE_VF
;
404 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
410 /** Fixed brw_reg. */
411 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
415 this->fixed_hw_reg
= fixed_hw_reg
;
416 this->type
= fixed_hw_reg
.type
;
420 fs_reg::equals(const fs_reg
&r
) const
422 return (file
== r
.file
&&
424 reg_offset
== r
.reg_offset
&&
425 subreg_offset
== r
.subreg_offset
&&
427 negate
== r
.negate
&&
429 !reladdr
&& !r
.reladdr
&&
430 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
, sizeof(fixed_hw_reg
)) == 0 &&
435 fs_reg::set_smear(unsigned subreg
)
437 assert(file
!= HW_REG
&& file
!= IMM
);
438 subreg_offset
= subreg
* type_sz(type
);
444 fs_reg::is_contiguous() const
450 fs_reg::component_size(unsigned width
) const
452 const unsigned stride
= (file
!= HW_REG
? this->stride
:
453 fixed_hw_reg
.hstride
== 0 ? 0 :
454 1 << (fixed_hw_reg
.hstride
- 1));
455 return MAX2(width
* stride
, 1) * type_sz(type
);
459 fs_visitor::type_size(const struct glsl_type
*type
)
461 unsigned int size
, i
;
463 switch (type
->base_type
) {
466 case GLSL_TYPE_FLOAT
:
468 return type
->components();
469 case GLSL_TYPE_ARRAY
:
470 return type_size(type
->fields
.array
) * type
->length
;
471 case GLSL_TYPE_STRUCT
:
473 for (i
= 0; i
< type
->length
; i
++) {
474 size
+= type_size(type
->fields
.structure
[i
].type
);
477 case GLSL_TYPE_SAMPLER
:
478 /* Samplers take up no register space, since they're baked in at
482 case GLSL_TYPE_ATOMIC_UINT
:
484 case GLSL_TYPE_SUBROUTINE
:
486 case GLSL_TYPE_IMAGE
:
488 case GLSL_TYPE_ERROR
:
489 case GLSL_TYPE_INTERFACE
:
490 case GLSL_TYPE_DOUBLE
:
491 unreachable("not reached");
498 * Create a MOV to read the timestamp register.
500 * The caller is responsible for emitting the MOV. The return value is
501 * the destination of the MOV, with extra parameters set.
504 fs_visitor::get_timestamp(const fs_builder
&bld
)
506 assert(devinfo
->gen
>= 7);
508 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
511 BRW_REGISTER_TYPE_UD
));
513 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
515 /* We want to read the 3 fields we care about even if it's not enabled in
518 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
520 /* The caller wants the low 32 bits of the timestamp. Since it's running
521 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
522 * which is plenty of time for our purposes. It is identical across the
523 * EUs, but since it's tracking GPU core speed it will increment at a
524 * varying rate as render P-states change.
526 * The caller could also check if render P-states have changed (or anything
527 * else that might disrupt timing) by setting smear to 2 and checking if
528 * that field is != 0.
536 fs_visitor::emit_shader_time_begin()
538 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
542 fs_visitor::emit_shader_time_end()
544 /* Insert our code just before the final SEND with EOT. */
545 exec_node
*end
= this->instructions
.get_tail();
546 assert(end
&& ((fs_inst
*) end
)->eot
);
547 const fs_builder ibld
= bld
.annotate("shader time end")
548 .exec_all().at(NULL
, end
);
550 fs_reg shader_end_time
= get_timestamp(ibld
);
552 /* Check that there weren't any timestamp reset events (assuming these
553 * were the only two timestamp reads that happened).
555 fs_reg reset
= shader_end_time
;
557 set_condmod(BRW_CONDITIONAL_Z
,
558 ibld
.AND(ibld
.null_reg_ud(), reset
, fs_reg(1u)));
559 ibld
.IF(BRW_PREDICATE_NORMAL
);
561 fs_reg start
= shader_start_time
;
563 fs_reg diff
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
566 const fs_builder cbld
= ibld
.group(1, 0);
567 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
569 /* If there were no instructions between the two timestamp gets, the diff
570 * is 2 cycles. Remove that overhead, so I can forget about that when
571 * trying to determine the time taken for single instructions.
573 cbld
.ADD(diff
, diff
, fs_reg(-2u));
574 SHADER_TIME_ADD(cbld
, 0, diff
);
575 SHADER_TIME_ADD(cbld
, 1, fs_reg(1u));
576 ibld
.emit(BRW_OPCODE_ELSE
);
577 SHADER_TIME_ADD(cbld
, 2, fs_reg(1u));
578 ibld
.emit(BRW_OPCODE_ENDIF
);
582 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
583 int shader_time_subindex
,
586 int index
= shader_time_index
* 3 + shader_time_subindex
;
587 fs_reg offset
= fs_reg(index
* SHADER_TIME_STRIDE
);
590 if (dispatch_width
== 8)
591 payload
= vgrf(glsl_type::uvec2_type
);
593 payload
= vgrf(glsl_type::uint_type
);
595 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
599 fs_visitor::vfail(const char *format
, va_list va
)
608 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
609 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
611 this->fail_msg
= msg
;
614 fprintf(stderr
, "%s", msg
);
619 fs_visitor::fail(const char *format
, ...)
623 va_start(va
, format
);
629 * Mark this program as impossible to compile in SIMD16 mode.
631 * During the SIMD8 compile (which happens first), we can detect and flag
632 * things that are unsupported in SIMD16 mode, so the compiler can skip
633 * the SIMD16 compile altogether.
635 * During a SIMD16 compile (if one happens anyway), this just calls fail().
638 fs_visitor::no16(const char *msg
)
640 if (dispatch_width
== 16) {
643 simd16_unsupported
= true;
645 compiler
->shader_perf_log(log_data
,
646 "SIMD16 shader failed to compile: %s", msg
);
651 * Returns true if the instruction has a flag that means it won't
652 * update an entire destination register.
654 * For example, dead code elimination and live variable analysis want to know
655 * when a write to a variable screens off any preceding values that were in
659 fs_inst::is_partial_write() const
661 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
662 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
663 !this->dst
.is_contiguous());
667 fs_inst::components_read(unsigned i
) const
670 case FS_OPCODE_LINTERP
:
676 case FS_OPCODE_PIXEL_X
:
677 case FS_OPCODE_PIXEL_Y
:
681 case FS_OPCODE_FB_WRITE_LOGICAL
:
682 assert(src
[6].file
== IMM
);
683 /* First/second FB write color. */
685 return src
[6].fixed_hw_reg
.dw1
.ud
;
689 case SHADER_OPCODE_TEX_LOGICAL
:
690 case SHADER_OPCODE_TXD_LOGICAL
:
691 case SHADER_OPCODE_TXF_LOGICAL
:
692 case SHADER_OPCODE_TXL_LOGICAL
:
693 case SHADER_OPCODE_TXS_LOGICAL
:
694 case FS_OPCODE_TXB_LOGICAL
:
695 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
696 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
697 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
698 case SHADER_OPCODE_LOD_LOGICAL
:
699 case SHADER_OPCODE_TG4_LOGICAL
:
700 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
701 assert(src
[8].file
== IMM
&& src
[9].file
== IMM
);
702 /* Texture coordinates. */
704 return src
[8].fixed_hw_reg
.dw1
.ud
;
705 /* Texture derivatives. */
706 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
707 return src
[9].fixed_hw_reg
.dw1
.ud
;
708 /* Texture offset. */
720 fs_inst::regs_read(int arg
) const
723 case FS_OPCODE_FB_WRITE
:
724 case SHADER_OPCODE_URB_WRITE_SIMD8
:
725 case SHADER_OPCODE_UNTYPED_ATOMIC
:
726 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
727 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
728 case SHADER_OPCODE_TYPED_ATOMIC
:
729 case SHADER_OPCODE_TYPED_SURFACE_READ
:
730 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
731 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
736 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
737 /* The payload is actually stored in src1 */
742 case FS_OPCODE_LINTERP
:
747 case SHADER_OPCODE_LOAD_PAYLOAD
:
748 if (arg
< this->header_size
)
752 case CS_OPCODE_CS_TERMINATE
:
756 if (is_tex() && arg
== 0 && src
[0].file
== GRF
)
761 switch (src
[arg
].file
) {
769 return DIV_ROUND_UP(components_read(arg
) *
770 src
[arg
].component_size(exec_size
),
773 unreachable("MRF registers are not allowed as sources");
775 unreachable("Invalid register file");
780 fs_inst::reads_flag() const
786 fs_inst::writes_flag() const
788 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
789 opcode
!= BRW_OPCODE_IF
&&
790 opcode
!= BRW_OPCODE_WHILE
)) ||
791 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
795 * Returns how many MRFs an FS opcode will write over.
797 * Note that this is not the 0 or 1 implied writes in an actual gen
798 * instruction -- the FS opcodes often generate MOVs in addition.
801 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
806 if (inst
->base_mrf
== -1)
809 switch (inst
->opcode
) {
810 case SHADER_OPCODE_RCP
:
811 case SHADER_OPCODE_RSQ
:
812 case SHADER_OPCODE_SQRT
:
813 case SHADER_OPCODE_EXP2
:
814 case SHADER_OPCODE_LOG2
:
815 case SHADER_OPCODE_SIN
:
816 case SHADER_OPCODE_COS
:
817 return 1 * dispatch_width
/ 8;
818 case SHADER_OPCODE_POW
:
819 case SHADER_OPCODE_INT_QUOTIENT
:
820 case SHADER_OPCODE_INT_REMAINDER
:
821 return 2 * dispatch_width
/ 8;
822 case SHADER_OPCODE_TEX
:
824 case SHADER_OPCODE_TXD
:
825 case SHADER_OPCODE_TXF
:
826 case SHADER_OPCODE_TXF_CMS
:
827 case SHADER_OPCODE_TXF_MCS
:
828 case SHADER_OPCODE_TG4
:
829 case SHADER_OPCODE_TG4_OFFSET
:
830 case SHADER_OPCODE_TXL
:
831 case SHADER_OPCODE_TXS
:
832 case SHADER_OPCODE_LOD
:
834 case FS_OPCODE_FB_WRITE
:
836 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
837 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
839 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
841 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
843 case SHADER_OPCODE_UNTYPED_ATOMIC
:
844 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
845 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
846 case SHADER_OPCODE_TYPED_ATOMIC
:
847 case SHADER_OPCODE_TYPED_SURFACE_READ
:
848 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
849 case SHADER_OPCODE_URB_WRITE_SIMD8
:
850 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
851 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
852 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
853 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
856 unreachable("not reached");
861 fs_visitor::vgrf(const glsl_type
*const type
)
863 int reg_width
= dispatch_width
/ 8;
864 return fs_reg(GRF
, alloc
.allocate(type_size(type
) * reg_width
),
865 brw_type_for_base_type(type
));
868 /** Fixed HW reg constructor. */
869 fs_reg::fs_reg(enum register_file file
, int reg
)
874 this->type
= BRW_REGISTER_TYPE_F
;
875 this->stride
= (file
== UNIFORM
? 0 : 1);
878 /** Fixed HW reg constructor. */
879 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
)
885 this->stride
= (file
== UNIFORM
? 0 : 1);
888 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
889 * This brings in those uniform definitions
892 fs_visitor::import_uniforms(fs_visitor
*v
)
894 this->push_constant_loc
= v
->push_constant_loc
;
895 this->pull_constant_loc
= v
->pull_constant_loc
;
896 this->uniforms
= v
->uniforms
;
897 this->param_size
= v
->param_size
;
901 fs_visitor::setup_vector_uniform_values(const gl_constant_value
*values
, unsigned n
)
903 static const gl_constant_value zero
= { 0 };
905 for (unsigned i
= 0; i
< n
; ++i
)
906 stage_prog_data
->param
[uniforms
++] = &values
[i
];
908 for (unsigned i
= n
; i
< 4; ++i
)
909 stage_prog_data
->param
[uniforms
++] = &zero
;
913 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
914 bool origin_upper_left
)
916 assert(stage
== MESA_SHADER_FRAGMENT
);
917 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
918 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
920 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
923 if (pixel_center_integer
) {
924 bld
.MOV(wpos
, this->pixel_x
);
926 bld
.ADD(wpos
, this->pixel_x
, fs_reg(0.5f
));
928 wpos
= offset(wpos
, bld
, 1);
931 if (!flip
&& pixel_center_integer
) {
932 bld
.MOV(wpos
, this->pixel_y
);
934 fs_reg pixel_y
= this->pixel_y
;
935 float offset
= (pixel_center_integer
? 0.0 : 0.5);
938 pixel_y
.negate
= true;
939 offset
+= key
->drawable_height
- 1.0;
942 bld
.ADD(wpos
, pixel_y
, fs_reg(offset
));
944 wpos
= offset(wpos
, bld
, 1);
947 if (devinfo
->gen
>= 6) {
948 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
950 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
951 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
952 interp_reg(VARYING_SLOT_POS
, 2));
954 wpos
= offset(wpos
, bld
, 1);
956 /* gl_FragCoord.w: Already set up in emit_interpolation */
957 bld
.MOV(wpos
, this->wpos_w
);
963 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
964 glsl_interp_qualifier interpolation_mode
,
965 bool is_centroid
, bool is_sample
)
967 brw_wm_barycentric_interp_mode barycoord_mode
;
968 if (devinfo
->gen
>= 6) {
970 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
971 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
973 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
974 } else if (is_sample
) {
975 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
976 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
978 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
980 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
981 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
983 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
986 /* On Ironlake and below, there is only one interpolation mode.
987 * Centroid interpolation doesn't mean anything on this hardware --
988 * there is no multisampling.
990 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
992 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
993 this->delta_xy
[barycoord_mode
], interp
);
997 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
998 const glsl_type
*type
,
999 glsl_interp_qualifier interpolation_mode
,
1000 int location
, bool mod_centroid
,
1003 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1005 assert(stage
== MESA_SHADER_FRAGMENT
);
1006 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1007 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1009 unsigned int array_elements
;
1011 if (type
->is_array()) {
1012 array_elements
= type
->length
;
1013 if (array_elements
== 0) {
1014 fail("dereferenced array '%s' has length 0\n", name
);
1016 type
= type
->fields
.array
;
1021 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1023 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1024 if (key
->flat_shade
&& is_gl_Color
) {
1025 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1027 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1031 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1032 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1033 if (prog_data
->urb_setup
[location
] == -1) {
1034 /* If there's no incoming setup data for this slot, don't
1035 * emit interpolation for it.
1037 attr
= offset(attr
, bld
, type
->vector_elements
);
1042 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1043 /* Constant interpolation (flat shading) case. The SF has
1044 * handed us defined values in only the constant offset
1045 * field of the setup reg.
1047 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1048 struct brw_reg interp
= interp_reg(location
, k
);
1049 interp
= suboffset(interp
, 3);
1050 interp
.type
= attr
.type
;
1051 bld
.emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1052 attr
= offset(attr
, bld
, 1);
1055 /* Smooth/noperspective interpolation case. */
1056 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1057 struct brw_reg interp
= interp_reg(location
, k
);
1058 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1059 /* Get the pixel/sample mask into f0 so that we know
1060 * which pixels are lit. Then, for each channel that is
1061 * unlit, replace the centroid data with non-centroid
1064 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1067 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1069 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1070 inst
->predicate_inverse
= true;
1071 if (devinfo
->has_pln
)
1072 inst
->no_dd_clear
= true;
1074 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1075 mod_centroid
&& !key
->persample_shading
,
1076 mod_sample
|| key
->persample_shading
);
1077 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1078 inst
->predicate_inverse
= false;
1079 if (devinfo
->has_pln
)
1080 inst
->no_dd_check
= true;
1083 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1084 mod_centroid
&& !key
->persample_shading
,
1085 mod_sample
|| key
->persample_shading
);
1087 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1088 bld
.MUL(attr
, attr
, this->pixel_w
);
1090 attr
= offset(attr
, bld
, 1);
1100 fs_visitor::emit_frontfacing_interpolation()
1102 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1104 if (devinfo
->gen
>= 6) {
1105 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1106 * a boolean result from this (~0/true or 0/false).
1108 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1109 * this task in only one instruction:
1110 * - a negation source modifier will flip the bit; and
1111 * - a W -> D type conversion will sign extend the bit into the high
1112 * word of the destination.
1114 * An ASR 15 fills the low word of the destination.
1116 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1119 bld
.ASR(*reg
, g0
, fs_reg(15));
1121 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1122 * a boolean result from this (1/true or 0/false).
1124 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1125 * the negation source modifier to flip it. Unfortunately the SHR
1126 * instruction only operates on UD (or D with an abs source modifier)
1127 * sources without negation.
1129 * Instead, use ASR (which will give ~0/true or 0/false).
1131 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1134 bld
.ASR(*reg
, g1_6
, fs_reg(31));
1141 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1143 assert(stage
== MESA_SHADER_FRAGMENT
);
1144 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1145 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1147 if (key
->compute_pos_offset
) {
1148 /* Convert int_sample_pos to floating point */
1149 bld
.MOV(dst
, int_sample_pos
);
1150 /* Scale to the range [0, 1] */
1151 bld
.MUL(dst
, dst
, fs_reg(1 / 16.0f
));
1154 /* From ARB_sample_shading specification:
1155 * "When rendering to a non-multisample buffer, or if multisample
1156 * rasterization is disabled, gl_SamplePosition will always be
1159 bld
.MOV(dst
, fs_reg(0.5f
));
1164 fs_visitor::emit_samplepos_setup()
1166 assert(devinfo
->gen
>= 6);
1168 const fs_builder abld
= bld
.annotate("compute sample position");
1169 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1171 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1172 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1174 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1175 * mode will be enabled.
1177 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1178 * R31.1:0 Position Offset X/Y for Slot[3:0]
1179 * R31.3:2 Position Offset X/Y for Slot[7:4]
1182 * The X, Y sample positions come in as bytes in thread payload. So, read
1183 * the positions using vstride=16, width=8, hstride=2.
1185 struct brw_reg sample_pos_reg
=
1186 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1187 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1189 if (dispatch_width
== 8) {
1190 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1192 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1193 abld
.half(1).MOV(half(int_sample_x
, 1),
1194 fs_reg(suboffset(sample_pos_reg
, 16)));
1196 /* Compute gl_SamplePosition.x */
1197 compute_sample_position(pos
, int_sample_x
);
1198 pos
= offset(pos
, abld
, 1);
1199 if (dispatch_width
== 8) {
1200 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1202 abld
.half(0).MOV(half(int_sample_y
, 0),
1203 fs_reg(suboffset(sample_pos_reg
, 1)));
1204 abld
.half(1).MOV(half(int_sample_y
, 1),
1205 fs_reg(suboffset(sample_pos_reg
, 17)));
1207 /* Compute gl_SamplePosition.y */
1208 compute_sample_position(pos
, int_sample_y
);
1213 fs_visitor::emit_sampleid_setup()
1215 assert(stage
== MESA_SHADER_FRAGMENT
);
1216 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1217 assert(devinfo
->gen
>= 6);
1219 const fs_builder abld
= bld
.annotate("compute sample id");
1220 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1222 if (key
->compute_sample_id
) {
1223 fs_reg t1
= vgrf(glsl_type::int_type
);
1224 fs_reg t2
= vgrf(glsl_type::int_type
);
1225 t2
.type
= BRW_REGISTER_TYPE_UW
;
1227 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1228 * 8x multisampling, subspan 0 will represent sample N (where N
1229 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1230 * 7. We can find the value of N by looking at R0.0 bits 7:6
1231 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1232 * (since samples are always delivered in pairs). That is, we
1233 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1234 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1235 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1236 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1237 * populating a temporary variable with the sequence (0, 1, 2, 3),
1238 * and then reading from it using vstride=1, width=4, hstride=0.
1239 * These computations hold good for 4x multisampling as well.
1241 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1242 * the first four slots are sample 0 of subspan 0; the next four
1243 * are sample 1 of subspan 0; the third group is sample 0 of
1244 * subspan 1, and finally sample 1 of subspan 1.
1247 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1249 abld
.exec_all().SHR(t1
, t1
, fs_reg(5));
1251 /* This works for both SIMD8 and SIMD16 */
1253 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1255 /* This special instruction takes care of setting vstride=1,
1256 * width=4, hstride=0 of t2 during an ADD instruction.
1258 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1260 /* As per GL_ARB_sample_shading specification:
1261 * "When rendering to a non-multisample buffer, or if multisample
1262 * rasterization is disabled, gl_SampleID will always be zero."
1264 abld
.MOV(*reg
, fs_reg(0));
1271 fs_visitor::resolve_source_modifiers(fs_reg
*src
)
1273 if (!src
->abs
&& !src
->negate
)
1276 fs_reg temp
= bld
.vgrf(src
->type
);
1277 bld
.MOV(temp
, *src
);
1282 fs_visitor::emit_discard_jump()
1284 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1286 /* For performance, after a discard, jump to the end of the
1287 * shader if all relevant channels have been discarded.
1289 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1290 discard_jump
->flag_subreg
= 1;
1292 discard_jump
->predicate
= (dispatch_width
== 8)
1293 ? BRW_PREDICATE_ALIGN1_ANY8H
1294 : BRW_PREDICATE_ALIGN1_ANY16H
;
1295 discard_jump
->predicate_inverse
= true;
1299 fs_visitor::assign_curb_setup()
1301 if (dispatch_width
== 8) {
1302 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1304 if (stage
== MESA_SHADER_FRAGMENT
) {
1305 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1306 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1307 } else if (stage
== MESA_SHADER_COMPUTE
) {
1308 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1309 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1311 unreachable("Unsupported shader type!");
1315 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1317 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1318 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1319 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1320 if (inst
->src
[i
].file
== UNIFORM
) {
1321 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1323 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1324 constant_nr
= push_constant_loc
[uniform_nr
];
1326 /* Section 5.11 of the OpenGL 4.1 spec says:
1327 * "Out-of-bounds reads return undefined values, which include
1328 * values from other variables of the active program or zero."
1329 * Just return the first push constant.
1334 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1338 assert(inst
->src
[i
].stride
== 0);
1339 inst
->src
[i
].file
= HW_REG
;
1340 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1341 retype(brw_reg
, inst
->src
[i
].type
),
1342 inst
->src
[i
].subreg_offset
);
1349 fs_visitor::calculate_urb_setup()
1351 assert(stage
== MESA_SHADER_FRAGMENT
);
1352 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1353 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1355 memset(prog_data
->urb_setup
, -1,
1356 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1359 /* Figure out where each of the incoming setup attributes lands. */
1360 if (devinfo
->gen
>= 6) {
1361 if (_mesa_bitcount_64(prog
->InputsRead
&
1362 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1363 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1364 * first 16 varying inputs, so we can put them wherever we want.
1365 * Just put them in order.
1367 * This is useful because it means that (a) inputs not used by the
1368 * fragment shader won't take up valuable register space, and (b) we
1369 * won't have to recompile the fragment shader if it gets paired with
1370 * a different vertex (or geometry) shader.
1372 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1373 if (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1374 BITFIELD64_BIT(i
)) {
1375 prog_data
->urb_setup
[i
] = urb_next
++;
1379 /* We have enough input varyings that the SF/SBE pipeline stage can't
1380 * arbitrarily rearrange them to suit our whim; we have to put them
1381 * in an order that matches the output of the previous pipeline stage
1382 * (geometry or vertex shader).
1384 struct brw_vue_map prev_stage_vue_map
;
1385 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1386 key
->input_slots_valid
);
1387 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1388 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1389 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1391 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1392 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1395 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1396 (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1397 BITFIELD64_BIT(varying
))) {
1398 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1401 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1404 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1405 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1406 /* Point size is packed into the header, not as a general attribute */
1407 if (i
== VARYING_SLOT_PSIZ
)
1410 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1411 /* The back color slot is skipped when the front color is
1412 * also written to. In addition, some slots can be
1413 * written in the vertex shader and not read in the
1414 * fragment shader. So the register number must always be
1415 * incremented, mapped or not.
1417 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1418 prog_data
->urb_setup
[i
] = urb_next
;
1424 * It's a FS only attribute, and we did interpolation for this attribute
1425 * in SF thread. So, count it here, too.
1427 * See compile_sf_prog() for more info.
1429 if (prog
->InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1430 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1433 prog_data
->num_varying_inputs
= urb_next
;
1437 fs_visitor::assign_urb_setup()
1439 assert(stage
== MESA_SHADER_FRAGMENT
);
1440 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1442 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1444 /* Offset all the urb_setup[] index by the actual position of the
1445 * setup regs, now that the location of the constants has been chosen.
1447 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1448 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1449 assert(inst
->src
[1].file
== HW_REG
);
1450 inst
->src
[1].fixed_hw_reg
.nr
+= urb_start
;
1453 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1454 assert(inst
->src
[0].file
== HW_REG
);
1455 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1459 /* Each attribute is 4 setup channels, each of which is half a reg. */
1460 this->first_non_payload_grf
=
1461 urb_start
+ prog_data
->num_varying_inputs
* 2;
1465 fs_visitor::assign_vs_urb_setup()
1467 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1468 int grf
, count
, slot
, channel
, attr
;
1470 assert(stage
== MESA_SHADER_VERTEX
);
1471 count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1472 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1475 /* Each attribute is 4 regs. */
1476 this->first_non_payload_grf
=
1477 payload
.num_regs
+ prog_data
->curb_read_length
+ count
* 4;
1479 unsigned vue_entries
=
1480 MAX2(count
, vs_prog_data
->base
.vue_map
.num_slots
);
1482 vs_prog_data
->base
.urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1483 vs_prog_data
->base
.urb_read_length
= (count
+ 1) / 2;
1485 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1487 /* Rewrite all ATTR file references to the hw grf that they land in. */
1488 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1489 for (int i
= 0; i
< inst
->sources
; i
++) {
1490 if (inst
->src
[i
].file
== ATTR
) {
1492 if (inst
->src
[i
].reg
== VERT_ATTRIB_MAX
) {
1495 /* Attributes come in in a contiguous block, ordered by their
1496 * gl_vert_attrib value. That means we can compute the slot
1497 * number for an attribute by masking out the enabled
1498 * attributes before it and counting the bits.
1500 attr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
/ 4;
1501 slot
= _mesa_bitcount_64(vs_prog_data
->inputs_read
&
1502 BITFIELD64_MASK(attr
));
1505 channel
= inst
->src
[i
].reg_offset
& 3;
1507 grf
= payload
.num_regs
+
1508 prog_data
->curb_read_length
+
1511 inst
->src
[i
].file
= HW_REG
;
1512 inst
->src
[i
].fixed_hw_reg
=
1513 retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
);
1520 * Split large virtual GRFs into separate components if we can.
1522 * This is mostly duplicated with what brw_fs_vector_splitting does,
1523 * but that's really conservative because it's afraid of doing
1524 * splitting that doesn't result in real progress after the rest of
1525 * the optimization phases, which would cause infinite looping in
1526 * optimization. We can do it once here, safely. This also has the
1527 * opportunity to split interpolated values, or maybe even uniforms,
1528 * which we don't have at the IR level.
1530 * We want to split, because virtual GRFs are what we register
1531 * allocate and spill (due to contiguousness requirements for some
1532 * instructions), and they're what we naturally generate in the
1533 * codegen process, but most virtual GRFs don't actually need to be
1534 * contiguous sets of GRFs. If we split, we'll end up with reduced
1535 * live intervals and better dead code elimination and coalescing.
1538 fs_visitor::split_virtual_grfs()
1540 int num_vars
= this->alloc
.count
;
1542 /* Count the total number of registers */
1544 int vgrf_to_reg
[num_vars
];
1545 for (int i
= 0; i
< num_vars
; i
++) {
1546 vgrf_to_reg
[i
] = reg_count
;
1547 reg_count
+= alloc
.sizes
[i
];
1550 /* An array of "split points". For each register slot, this indicates
1551 * if this slot can be separated from the previous slot. Every time an
1552 * instruction uses multiple elements of a register (as a source or
1553 * destination), we mark the used slots as inseparable. Then we go
1554 * through and split the registers into the smallest pieces we can.
1556 bool split_points
[reg_count
];
1557 memset(split_points
, 0, sizeof(split_points
));
1559 /* Mark all used registers as fully splittable */
1560 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1561 if (inst
->dst
.file
== GRF
) {
1562 int reg
= vgrf_to_reg
[inst
->dst
.reg
];
1563 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.reg
]; j
++)
1564 split_points
[reg
+ j
] = true;
1567 for (int i
= 0; i
< inst
->sources
; i
++) {
1568 if (inst
->src
[i
].file
== GRF
) {
1569 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
];
1570 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].reg
]; j
++)
1571 split_points
[reg
+ j
] = true;
1576 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1577 if (inst
->dst
.file
== GRF
) {
1578 int reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1579 for (int j
= 1; j
< inst
->regs_written
; j
++)
1580 split_points
[reg
+ j
] = false;
1582 for (int i
= 0; i
< inst
->sources
; i
++) {
1583 if (inst
->src
[i
].file
== GRF
) {
1584 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1585 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1586 split_points
[reg
+ j
] = false;
1591 int new_virtual_grf
[reg_count
];
1592 int new_reg_offset
[reg_count
];
1595 for (int i
= 0; i
< num_vars
; i
++) {
1596 /* The first one should always be 0 as a quick sanity check. */
1597 assert(split_points
[reg
] == false);
1600 new_reg_offset
[reg
] = 0;
1605 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1606 /* If this is a split point, reset the offset to 0 and allocate a
1607 * new virtual GRF for the previous offset many registers
1609 if (split_points
[reg
]) {
1610 assert(offset
<= MAX_VGRF_SIZE
);
1611 int grf
= alloc
.allocate(offset
);
1612 for (int k
= reg
- offset
; k
< reg
; k
++)
1613 new_virtual_grf
[k
] = grf
;
1616 new_reg_offset
[reg
] = offset
;
1621 /* The last one gets the original register number */
1622 assert(offset
<= MAX_VGRF_SIZE
);
1623 alloc
.sizes
[i
] = offset
;
1624 for (int k
= reg
- offset
; k
< reg
; k
++)
1625 new_virtual_grf
[k
] = i
;
1627 assert(reg
== reg_count
);
1629 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1630 if (inst
->dst
.file
== GRF
) {
1631 reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1632 inst
->dst
.reg
= new_virtual_grf
[reg
];
1633 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1634 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1636 for (int i
= 0; i
< inst
->sources
; i
++) {
1637 if (inst
->src
[i
].file
== GRF
) {
1638 reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1639 inst
->src
[i
].reg
= new_virtual_grf
[reg
];
1640 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1641 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1645 invalidate_live_intervals();
1649 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1651 * During code generation, we create tons of temporary variables, many of
1652 * which get immediately killed and are never used again. Yet, in later
1653 * optimization and analysis passes, such as compute_live_intervals, we need
1654 * to loop over all the virtual GRFs. Compacting them can save a lot of
1658 fs_visitor::compact_virtual_grfs()
1660 bool progress
= false;
1661 int remap_table
[this->alloc
.count
];
1662 memset(remap_table
, -1, sizeof(remap_table
));
1664 /* Mark which virtual GRFs are used. */
1665 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1666 if (inst
->dst
.file
== GRF
)
1667 remap_table
[inst
->dst
.reg
] = 0;
1669 for (int i
= 0; i
< inst
->sources
; i
++) {
1670 if (inst
->src
[i
].file
== GRF
)
1671 remap_table
[inst
->src
[i
].reg
] = 0;
1675 /* Compact the GRF arrays. */
1677 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1678 if (remap_table
[i
] == -1) {
1679 /* We just found an unused register. This means that we are
1680 * actually going to compact something.
1684 remap_table
[i
] = new_index
;
1685 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1686 invalidate_live_intervals();
1691 this->alloc
.count
= new_index
;
1693 /* Patch all the instructions to use the newly renumbered registers */
1694 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1695 if (inst
->dst
.file
== GRF
)
1696 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1698 for (int i
= 0; i
< inst
->sources
; i
++) {
1699 if (inst
->src
[i
].file
== GRF
)
1700 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1704 /* Patch all the references to delta_xy, since they're used in register
1705 * allocation. If they're unused, switch them to BAD_FILE so we don't
1706 * think some random VGRF is delta_xy.
1708 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1709 if (delta_xy
[i
].file
== GRF
) {
1710 if (remap_table
[delta_xy
[i
].reg
] != -1) {
1711 delta_xy
[i
].reg
= remap_table
[delta_xy
[i
].reg
];
1713 delta_xy
[i
].file
= BAD_FILE
;
1722 * Implements array access of uniforms by inserting a
1723 * PULL_CONSTANT_LOAD instruction.
1725 * Unlike temporary GRF array access (where we don't support it due to
1726 * the difficulty of doing relative addressing on instruction
1727 * destinations), we could potentially do array access of uniforms
1728 * that were loaded in GRF space as push constants. In real-world
1729 * usage we've seen, though, the arrays being used are always larger
1730 * than we could load as push constants, so just always move all
1731 * uniform array access out to a pull constant buffer.
1734 fs_visitor::move_uniform_array_access_to_pull_constants()
1736 if (dispatch_width
!= 8)
1739 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1740 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1742 /* Walk through and find array access of uniforms. Put a copy of that
1743 * uniform in the pull constant buffer.
1745 * Note that we don't move constant-indexed accesses to arrays. No
1746 * testing has been done of the performance impact of this choice.
1748 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1749 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1750 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
1753 int uniform
= inst
->src
[i
].reg
;
1755 /* If this array isn't already present in the pull constant buffer,
1758 if (pull_constant_loc
[uniform
] == -1) {
1759 const gl_constant_value
**values
= &stage_prog_data
->param
[uniform
];
1761 assert(param_size
[uniform
]);
1763 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
1764 pull_constant_loc
[uniform
+ j
] = stage_prog_data
->nr_pull_params
;
1766 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
1775 * Assign UNIFORM file registers to either push constants or pull constants.
1777 * We allow a fragment shader to have more than the specified minimum
1778 * maximum number of fragment shader uniform components (64). If
1779 * there are too many of these, they'd fill up all of register space.
1780 * So, this will push some of them out to the pull constant buffer and
1781 * update the program to load them.
1784 fs_visitor::assign_constant_locations()
1786 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1787 if (dispatch_width
!= 8)
1790 /* Find which UNIFORM registers are still in use. */
1791 bool is_live
[uniforms
];
1792 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1796 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1797 for (int i
= 0; i
< inst
->sources
; i
++) {
1798 if (inst
->src
[i
].file
!= UNIFORM
)
1801 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1802 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1803 is_live
[constant_nr
] = true;
1807 /* Only allow 16 registers (128 uniform components) as push constants.
1809 * Just demote the end of the list. We could probably do better
1810 * here, demoting things that are rarely used in the program first.
1812 * If changing this value, note the limitation about total_regs in
1815 unsigned int max_push_components
= 16 * 8;
1816 unsigned int num_push_constants
= 0;
1818 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1820 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1821 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1822 /* This UNIFORM register is either dead, or has already been demoted
1823 * to a pull const. Mark it as no longer living in the param[] array.
1825 push_constant_loc
[i
] = -1;
1829 if (num_push_constants
< max_push_components
) {
1830 /* Retain as a push constant. Record the location in the params[]
1833 push_constant_loc
[i
] = num_push_constants
++;
1835 /* Demote to a pull constant. */
1836 push_constant_loc
[i
] = -1;
1838 int pull_index
= stage_prog_data
->nr_pull_params
++;
1839 stage_prog_data
->pull_param
[pull_index
] = stage_prog_data
->param
[i
];
1840 pull_constant_loc
[i
] = pull_index
;
1844 stage_prog_data
->nr_params
= num_push_constants
;
1846 /* Up until now, the param[] array has been indexed by reg + reg_offset
1847 * of UNIFORM registers. Condense it to only contain the uniforms we
1848 * chose to upload as push constants.
1850 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1851 int remapped
= push_constant_loc
[i
];
1856 assert(remapped
<= (int)i
);
1857 stage_prog_data
->param
[remapped
] = stage_prog_data
->param
[i
];
1862 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
1863 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
1866 fs_visitor::demote_pull_constants()
1868 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1869 for (int i
= 0; i
< inst
->sources
; i
++) {
1870 if (inst
->src
[i
].file
!= UNIFORM
)
1874 unsigned location
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1875 if (location
>= uniforms
) /* Out of bounds access */
1878 pull_index
= pull_constant_loc
[location
];
1880 if (pull_index
== -1)
1883 /* Set up the annotation tracking for new generated instructions. */
1884 const fs_builder ibld
= bld
.annotate(inst
->annotation
, inst
->ir
)
1886 fs_reg
surf_index(stage_prog_data
->binding_table
.pull_constants_start
);
1887 fs_reg dst
= vgrf(glsl_type::float_type
);
1889 assert(inst
->src
[i
].stride
== 0);
1891 /* Generate a pull load into dst. */
1892 if (inst
->src
[i
].reladdr
) {
1893 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
1895 *inst
->src
[i
].reladdr
,
1897 inst
->src
[i
].reladdr
= NULL
;
1898 inst
->src
[i
].stride
= 1;
1900 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
1901 ibld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
1902 dst
, surf_index
, offset
);
1903 inst
->src
[i
].set_smear(pull_index
& 3);
1906 /* Rewrite the instruction to use the temporary VGRF. */
1907 inst
->src
[i
].file
= GRF
;
1908 inst
->src
[i
].reg
= dst
.reg
;
1909 inst
->src
[i
].reg_offset
= 0;
1912 invalidate_live_intervals();
1916 fs_visitor::opt_algebraic()
1918 bool progress
= false;
1920 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1921 switch (inst
->opcode
) {
1922 case BRW_OPCODE_MOV
:
1923 if (inst
->src
[0].file
!= IMM
)
1926 if (inst
->saturate
) {
1927 if (inst
->dst
.type
!= inst
->src
[0].type
)
1928 assert(!"unimplemented: saturate mixed types");
1930 if (brw_saturate_immediate(inst
->dst
.type
,
1931 &inst
->src
[0].fixed_hw_reg
)) {
1932 inst
->saturate
= false;
1938 case BRW_OPCODE_MUL
:
1939 if (inst
->src
[1].file
!= IMM
)
1943 if (inst
->src
[1].is_one()) {
1944 inst
->opcode
= BRW_OPCODE_MOV
;
1945 inst
->src
[1] = reg_undef
;
1951 if (inst
->src
[1].is_negative_one()) {
1952 inst
->opcode
= BRW_OPCODE_MOV
;
1953 inst
->src
[0].negate
= !inst
->src
[0].negate
;
1954 inst
->src
[1] = reg_undef
;
1960 if (inst
->src
[1].is_zero()) {
1961 inst
->opcode
= BRW_OPCODE_MOV
;
1962 inst
->src
[0] = inst
->src
[1];
1963 inst
->src
[1] = reg_undef
;
1968 if (inst
->src
[0].file
== IMM
) {
1969 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
1970 inst
->opcode
= BRW_OPCODE_MOV
;
1971 inst
->src
[0].fixed_hw_reg
.dw1
.f
*= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
1972 inst
->src
[1] = reg_undef
;
1977 case BRW_OPCODE_ADD
:
1978 if (inst
->src
[1].file
!= IMM
)
1982 if (inst
->src
[1].is_zero()) {
1983 inst
->opcode
= BRW_OPCODE_MOV
;
1984 inst
->src
[1] = reg_undef
;
1989 if (inst
->src
[0].file
== IMM
) {
1990 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
1991 inst
->opcode
= BRW_OPCODE_MOV
;
1992 inst
->src
[0].fixed_hw_reg
.dw1
.f
+= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
1993 inst
->src
[1] = reg_undef
;
1999 if (inst
->src
[0].equals(inst
->src
[1])) {
2000 inst
->opcode
= BRW_OPCODE_MOV
;
2001 inst
->src
[1] = reg_undef
;
2006 case BRW_OPCODE_LRP
:
2007 if (inst
->src
[1].equals(inst
->src
[2])) {
2008 inst
->opcode
= BRW_OPCODE_MOV
;
2009 inst
->src
[0] = inst
->src
[1];
2010 inst
->src
[1] = reg_undef
;
2011 inst
->src
[2] = reg_undef
;
2016 case BRW_OPCODE_CMP
:
2017 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2019 inst
->src
[0].negate
&&
2020 inst
->src
[1].is_zero()) {
2021 inst
->src
[0].abs
= false;
2022 inst
->src
[0].negate
= false;
2023 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2028 case BRW_OPCODE_SEL
:
2029 if (inst
->src
[0].equals(inst
->src
[1])) {
2030 inst
->opcode
= BRW_OPCODE_MOV
;
2031 inst
->src
[1] = reg_undef
;
2032 inst
->predicate
= BRW_PREDICATE_NONE
;
2033 inst
->predicate_inverse
= false;
2035 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2036 switch (inst
->conditional_mod
) {
2037 case BRW_CONDITIONAL_LE
:
2038 case BRW_CONDITIONAL_L
:
2039 switch (inst
->src
[1].type
) {
2040 case BRW_REGISTER_TYPE_F
:
2041 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
>= 1.0f
) {
2042 inst
->opcode
= BRW_OPCODE_MOV
;
2043 inst
->src
[1] = reg_undef
;
2044 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2052 case BRW_CONDITIONAL_GE
:
2053 case BRW_CONDITIONAL_G
:
2054 switch (inst
->src
[1].type
) {
2055 case BRW_REGISTER_TYPE_F
:
2056 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
<= 0.0f
) {
2057 inst
->opcode
= BRW_OPCODE_MOV
;
2058 inst
->src
[1] = reg_undef
;
2059 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2071 case BRW_OPCODE_MAD
:
2072 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2073 inst
->opcode
= BRW_OPCODE_MOV
;
2074 inst
->src
[1] = reg_undef
;
2075 inst
->src
[2] = reg_undef
;
2077 } else if (inst
->src
[0].is_zero()) {
2078 inst
->opcode
= BRW_OPCODE_MUL
;
2079 inst
->src
[0] = inst
->src
[2];
2080 inst
->src
[2] = reg_undef
;
2082 } else if (inst
->src
[1].is_one()) {
2083 inst
->opcode
= BRW_OPCODE_ADD
;
2084 inst
->src
[1] = inst
->src
[2];
2085 inst
->src
[2] = reg_undef
;
2087 } else if (inst
->src
[2].is_one()) {
2088 inst
->opcode
= BRW_OPCODE_ADD
;
2089 inst
->src
[2] = reg_undef
;
2091 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2092 inst
->opcode
= BRW_OPCODE_ADD
;
2093 inst
->src
[1].fixed_hw_reg
.dw1
.f
*= inst
->src
[2].fixed_hw_reg
.dw1
.f
;
2094 inst
->src
[2] = reg_undef
;
2098 case SHADER_OPCODE_RCP
: {
2099 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2100 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2101 if (inst
->src
[0].equals(prev
->dst
)) {
2102 inst
->opcode
= SHADER_OPCODE_RSQ
;
2103 inst
->src
[0] = prev
->src
[0];
2109 case SHADER_OPCODE_BROADCAST
:
2110 if (is_uniform(inst
->src
[0])) {
2111 inst
->opcode
= BRW_OPCODE_MOV
;
2113 inst
->force_writemask_all
= true;
2115 } else if (inst
->src
[1].file
== IMM
) {
2116 inst
->opcode
= BRW_OPCODE_MOV
;
2117 inst
->src
[0] = component(inst
->src
[0],
2118 inst
->src
[1].fixed_hw_reg
.dw1
.ud
);
2120 inst
->force_writemask_all
= true;
2129 /* Swap if src[0] is immediate. */
2130 if (progress
&& inst
->is_commutative()) {
2131 if (inst
->src
[0].file
== IMM
) {
2132 fs_reg tmp
= inst
->src
[1];
2133 inst
->src
[1] = inst
->src
[0];
2142 * Optimize sample messages that have constant zero values for the trailing
2143 * texture coordinates. We can just reduce the message length for these
2144 * instructions instead of reserving a register for it. Trailing parameters
2145 * that aren't sent default to zero anyway. This will cause the dead code
2146 * eliminator to remove the MOV instruction that would otherwise be emitted to
2147 * set up the zero value.
2150 fs_visitor::opt_zero_samples()
2152 /* Gen4 infers the texturing opcode based on the message length so we can't
2155 if (devinfo
->gen
< 5)
2158 bool progress
= false;
2160 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2161 if (!inst
->is_tex())
2164 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2166 if (load_payload
->is_head_sentinel() ||
2167 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2170 /* We don't want to remove the message header or the first parameter.
2171 * Removing the first parameter is not allowed, see the Haswell PRM
2172 * volume 7, page 149:
2174 * "Parameter 0 is required except for the sampleinfo message, which
2175 * has no parameter 0"
2177 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2178 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2179 (inst
->exec_size
/ 8) +
2180 inst
->header_size
- 1].is_zero()) {
2181 inst
->mlen
-= inst
->exec_size
/ 8;
2187 invalidate_live_intervals();
2193 * Optimize sample messages which are followed by the final RT write.
2195 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2196 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2197 * final texturing results copied to the framebuffer write payload and modify
2198 * them to write to the framebuffer directly.
2201 fs_visitor::opt_sampler_eot()
2203 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2205 if (stage
!= MESA_SHADER_FRAGMENT
)
2208 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2211 /* FINISHME: It should be possible to implement this optimization when there
2212 * are multiple drawbuffers.
2214 if (key
->nr_color_regions
!= 1)
2217 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2218 fs_inst
*fb_write
= (fs_inst
*) cfg
->blocks
[cfg
->num_blocks
- 1]->end();
2219 assert(fb_write
->eot
);
2220 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2222 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2224 /* There wasn't one; nothing to do. */
2225 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2228 /* This optimisation doesn't seem to work for textureGather for some
2229 * reason. I can't find any documentation or known workarounds to indicate
2230 * that this is expected, but considering that it is probably pretty
2231 * unlikely that a shader would directly write out the results from
2232 * textureGather we might as well just disable it.
2234 if (tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2235 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2238 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2239 * It's very likely to be the previous instruction.
2241 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2242 if (load_payload
->is_head_sentinel() ||
2243 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2246 assert(!tex_inst
->eot
); /* We can't get here twice */
2247 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2249 tex_inst
->offset
|= fb_write
->target
<< 24;
2250 tex_inst
->eot
= true;
2251 tex_inst
->dst
= bld
.null_reg_ud();
2252 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2254 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2255 * to create a new LOAD_PAYLOAD command with the same sources and a space
2256 * saved for the header. Using a new destination register not only makes sure
2257 * we have enough space, but it will make sure the dead code eliminator kills
2258 * the instruction that this will replace.
2260 if (tex_inst
->header_size
!= 0)
2263 fs_reg send_header
= bld
.vgrf(BRW_REGISTER_TYPE_F
,
2264 load_payload
->sources
+ 1);
2265 fs_reg
*new_sources
=
2266 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2268 new_sources
[0] = fs_reg();
2269 for (int i
= 0; i
< load_payload
->sources
; i
++)
2270 new_sources
[i
+1] = load_payload
->src
[i
];
2272 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2273 * requires a lot of information about the sources to appropriately figure
2274 * out the number of registers needed to be used. Given this stage in our
2275 * optimization, we may not have the appropriate GRFs required by
2276 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2277 * manually emit the instruction.
2279 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2280 load_payload
->exec_size
,
2283 load_payload
->sources
+ 1);
2285 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2286 new_load_payload
->header_size
= 1;
2288 tex_inst
->header_size
= 1;
2289 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2290 tex_inst
->src
[0] = send_header
;
2296 fs_visitor::opt_register_renaming()
2298 bool progress
= false;
2301 int remap
[alloc
.count
];
2302 memset(remap
, -1, sizeof(int) * alloc
.count
);
2304 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2305 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2307 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2308 inst
->opcode
== BRW_OPCODE_WHILE
) {
2312 /* Rewrite instruction sources. */
2313 for (int i
= 0; i
< inst
->sources
; i
++) {
2314 if (inst
->src
[i
].file
== GRF
&&
2315 remap
[inst
->src
[i
].reg
] != -1 &&
2316 remap
[inst
->src
[i
].reg
] != inst
->src
[i
].reg
) {
2317 inst
->src
[i
].reg
= remap
[inst
->src
[i
].reg
];
2322 const int dst
= inst
->dst
.reg
;
2325 inst
->dst
.file
== GRF
&&
2326 alloc
.sizes
[inst
->dst
.reg
] == inst
->exec_size
/ 8 &&
2327 !inst
->is_partial_write()) {
2328 if (remap
[dst
] == -1) {
2331 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2332 inst
->dst
.reg
= remap
[dst
];
2335 } else if (inst
->dst
.file
== GRF
&&
2337 remap
[dst
] != dst
) {
2338 inst
->dst
.reg
= remap
[dst
];
2344 invalidate_live_intervals();
2346 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2347 if (delta_xy
[i
].file
== GRF
&& remap
[delta_xy
[i
].reg
] != -1) {
2348 delta_xy
[i
].reg
= remap
[delta_xy
[i
].reg
];
2357 * Remove redundant or useless discard jumps.
2359 * For example, we can eliminate jumps in the following sequence:
2361 * discard-jump (redundant with the next jump)
2362 * discard-jump (useless; jumps to the next instruction)
2366 fs_visitor::opt_redundant_discard_jumps()
2368 bool progress
= false;
2370 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2372 fs_inst
*placeholder_halt
= NULL
;
2373 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2374 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2375 placeholder_halt
= inst
;
2380 if (!placeholder_halt
)
2383 /* Delete any HALTs immediately before the placeholder halt. */
2384 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2385 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2386 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2387 prev
->remove(last_bblock
);
2392 invalidate_live_intervals();
2398 fs_visitor::compute_to_mrf()
2400 bool progress
= false;
2403 /* No MRFs on Gen >= 7. */
2404 if (devinfo
->gen
>= 7)
2407 calculate_live_intervals();
2409 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2413 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2414 inst
->is_partial_write() ||
2415 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2416 inst
->dst
.type
!= inst
->src
[0].type
||
2417 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2418 !inst
->src
[0].is_contiguous() ||
2419 inst
->src
[0].subreg_offset
)
2422 /* Work out which hardware MRF registers are written by this
2425 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2427 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2428 mrf_high
= mrf_low
+ 4;
2429 } else if (inst
->exec_size
== 16) {
2430 mrf_high
= mrf_low
+ 1;
2435 /* Can't compute-to-MRF this GRF if someone else was going to
2438 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2441 /* Found a move of a GRF to a MRF. Let's see if we can go
2442 * rewrite the thing that made this GRF to write into the MRF.
2444 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2445 if (scan_inst
->dst
.file
== GRF
&&
2446 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2447 /* Found the last thing to write our reg we want to turn
2448 * into a compute-to-MRF.
2451 /* If this one instruction didn't populate all the
2452 * channels, bail. We might be able to rewrite everything
2453 * that writes that reg, but it would require smarter
2454 * tracking to delay the rewriting until complete success.
2456 if (scan_inst
->is_partial_write())
2459 /* Things returning more than one register would need us to
2460 * understand coalescing out more than one MOV at a time.
2462 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2465 /* SEND instructions can't have MRF as a destination. */
2466 if (scan_inst
->mlen
)
2469 if (devinfo
->gen
== 6) {
2470 /* gen6 math instructions must have the destination be
2471 * GRF, so no compute-to-MRF for them.
2473 if (scan_inst
->is_math()) {
2478 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2479 /* Found the creator of our MRF's source value. */
2480 scan_inst
->dst
.file
= MRF
;
2481 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2482 scan_inst
->saturate
|= inst
->saturate
;
2483 inst
->remove(block
);
2489 /* We don't handle control flow here. Most computation of
2490 * values that end up in MRFs are shortly before the MRF
2493 if (block
->start() == scan_inst
)
2496 /* You can't read from an MRF, so if someone else reads our
2497 * MRF's source GRF that we wanted to rewrite, that stops us.
2499 bool interfered
= false;
2500 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2501 if (scan_inst
->src
[i
].file
== GRF
&&
2502 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2503 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2510 if (scan_inst
->dst
.file
== MRF
) {
2511 /* If somebody else writes our MRF here, we can't
2512 * compute-to-MRF before that.
2514 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2517 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2518 scan_mrf_high
= scan_mrf_low
+ 4;
2519 } else if (scan_inst
->exec_size
== 16) {
2520 scan_mrf_high
= scan_mrf_low
+ 1;
2522 scan_mrf_high
= scan_mrf_low
;
2525 if (mrf_low
== scan_mrf_low
||
2526 mrf_low
== scan_mrf_high
||
2527 mrf_high
== scan_mrf_low
||
2528 mrf_high
== scan_mrf_high
) {
2533 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2534 /* Found a SEND instruction, which means that there are
2535 * live values in MRFs from base_mrf to base_mrf +
2536 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2539 if (mrf_low
>= scan_inst
->base_mrf
&&
2540 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2543 if (mrf_high
>= scan_inst
->base_mrf
&&
2544 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2552 invalidate_live_intervals();
2558 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2559 * flow. We could probably do better here with some form of divergence
2563 fs_visitor::eliminate_find_live_channel()
2565 bool progress
= false;
2568 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2569 switch (inst
->opcode
) {
2575 case BRW_OPCODE_ENDIF
:
2576 case BRW_OPCODE_WHILE
:
2580 case FS_OPCODE_DISCARD_JUMP
:
2581 /* This can potentially make control flow non-uniform until the end
2586 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2588 inst
->opcode
= BRW_OPCODE_MOV
;
2589 inst
->src
[0] = fs_reg(0);
2591 inst
->force_writemask_all
= true;
2605 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2606 * instructions to FS_OPCODE_REP_FB_WRITE.
2609 fs_visitor::emit_repclear_shader()
2611 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2613 int color_mrf
= base_mrf
+ 2;
2615 fs_inst
*mov
= bld
.exec_all().MOV(vec4(brw_message_reg(color_mrf
)),
2616 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2619 if (key
->nr_color_regions
== 1) {
2620 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2621 write
->saturate
= key
->clamp_fragment_color
;
2622 write
->base_mrf
= color_mrf
;
2624 write
->header_size
= 0;
2627 assume(key
->nr_color_regions
> 0);
2628 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2629 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2630 write
->saturate
= key
->clamp_fragment_color
;
2631 write
->base_mrf
= base_mrf
;
2633 write
->header_size
= 2;
2641 assign_constant_locations();
2642 assign_curb_setup();
2644 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2645 assert(mov
->src
[0].file
== HW_REG
);
2646 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].fixed_hw_reg
.nr
, 0);
2650 * Walks through basic blocks, looking for repeated MRF writes and
2651 * removing the later ones.
2654 fs_visitor::remove_duplicate_mrf_writes()
2656 fs_inst
*last_mrf_move
[16];
2657 bool progress
= false;
2659 /* Need to update the MRF tracking for compressed instructions. */
2660 if (dispatch_width
== 16)
2663 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2665 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2666 if (inst
->is_control_flow()) {
2667 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2670 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2671 inst
->dst
.file
== MRF
) {
2672 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2673 if (prev_inst
&& inst
->equals(prev_inst
)) {
2674 inst
->remove(block
);
2680 /* Clear out the last-write records for MRFs that were overwritten. */
2681 if (inst
->dst
.file
== MRF
) {
2682 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2685 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2686 /* Found a SEND instruction, which will include two or fewer
2687 * implied MRF writes. We could do better here.
2689 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2690 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2694 /* Clear out any MRF move records whose sources got overwritten. */
2695 if (inst
->dst
.file
== GRF
) {
2696 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2697 if (last_mrf_move
[i
] &&
2698 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2699 last_mrf_move
[i
] = NULL
;
2704 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2705 inst
->dst
.file
== MRF
&&
2706 inst
->src
[0].file
== GRF
&&
2707 !inst
->is_partial_write()) {
2708 last_mrf_move
[inst
->dst
.reg
] = inst
;
2713 invalidate_live_intervals();
2719 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2721 /* Clear the flag for registers that actually got read (as expected). */
2722 for (int i
= 0; i
< inst
->sources
; i
++) {
2724 if (inst
->src
[i
].file
== GRF
) {
2725 grf
= inst
->src
[i
].reg
;
2726 } else if (inst
->src
[i
].file
== HW_REG
&&
2727 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2728 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2733 if (grf
>= first_grf
&&
2734 grf
< first_grf
+ grf_len
) {
2735 deps
[grf
- first_grf
] = false;
2736 if (inst
->exec_size
== 16)
2737 deps
[grf
- first_grf
+ 1] = false;
2743 * Implements this workaround for the original 965:
2745 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2746 * check for post destination dependencies on this instruction, software
2747 * must ensure that there is no destination hazard for the case of ‘write
2748 * followed by a posted write’ shown in the following example.
2751 * 2. send r3.xy <rest of send instruction>
2754 * Due to no post-destination dependency check on the ‘send’, the above
2755 * code sequence could have two instructions (1 and 2) in flight at the
2756 * same time that both consider ‘r3’ as the target of their final writes.
2759 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2762 int write_len
= inst
->regs_written
;
2763 int first_write_grf
= inst
->dst
.reg
;
2764 bool needs_dep
[BRW_MAX_MRF
];
2765 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2767 memset(needs_dep
, false, sizeof(needs_dep
));
2768 memset(needs_dep
, true, write_len
);
2770 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2772 /* Walk backwards looking for writes to registers we're writing which
2773 * aren't read since being written. If we hit the start of the program,
2774 * we assume that there are no outstanding dependencies on entry to the
2777 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2778 /* If we hit control flow, assume that there *are* outstanding
2779 * dependencies, and force their cleanup before our instruction.
2781 if (block
->start() == scan_inst
) {
2782 for (int i
= 0; i
< write_len
; i
++) {
2784 DEP_RESOLVE_MOV(bld
.at(block
, inst
), first_write_grf
+ i
);
2789 /* We insert our reads as late as possible on the assumption that any
2790 * instruction but a MOV that might have left us an outstanding
2791 * dependency has more latency than a MOV.
2793 if (scan_inst
->dst
.file
== GRF
) {
2794 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2795 int reg
= scan_inst
->dst
.reg
+ i
;
2797 if (reg
>= first_write_grf
&&
2798 reg
< first_write_grf
+ write_len
&&
2799 needs_dep
[reg
- first_write_grf
]) {
2800 DEP_RESOLVE_MOV(bld
.at(block
, inst
), reg
);
2801 needs_dep
[reg
- first_write_grf
] = false;
2802 if (scan_inst
->exec_size
== 16)
2803 needs_dep
[reg
- first_write_grf
+ 1] = false;
2808 /* Clear the flag for registers that actually got read (as expected). */
2809 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2811 /* Continue the loop only if we haven't resolved all the dependencies */
2813 for (i
= 0; i
< write_len
; i
++) {
2823 * Implements this workaround for the original 965:
2825 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2826 * used as a destination register until after it has been sourced by an
2827 * instruction with a different destination register.
2830 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2832 int write_len
= inst
->regs_written
;
2833 int first_write_grf
= inst
->dst
.reg
;
2834 bool needs_dep
[BRW_MAX_MRF
];
2835 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2837 memset(needs_dep
, false, sizeof(needs_dep
));
2838 memset(needs_dep
, true, write_len
);
2839 /* Walk forwards looking for writes to registers we're writing which aren't
2840 * read before being written.
2842 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2843 /* If we hit control flow, force resolve all remaining dependencies. */
2844 if (block
->end() == scan_inst
) {
2845 for (int i
= 0; i
< write_len
; i
++) {
2847 DEP_RESOLVE_MOV(bld
.at(block
, scan_inst
), first_write_grf
+ i
);
2852 /* Clear the flag for registers that actually got read (as expected). */
2853 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2855 /* We insert our reads as late as possible since they're reading the
2856 * result of a SEND, which has massive latency.
2858 if (scan_inst
->dst
.file
== GRF
&&
2859 scan_inst
->dst
.reg
>= first_write_grf
&&
2860 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
2861 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
2862 DEP_RESOLVE_MOV(bld
.at(block
, scan_inst
), scan_inst
->dst
.reg
);
2863 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
2866 /* Continue the loop only if we haven't resolved all the dependencies */
2868 for (i
= 0; i
< write_len
; i
++) {
2878 fs_visitor::insert_gen4_send_dependency_workarounds()
2880 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
2883 bool progress
= false;
2885 /* Note that we're done with register allocation, so GRF fs_regs always
2886 * have a .reg_offset of 0.
2889 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2890 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
2891 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
2892 insert_gen4_post_send_dependency_workarounds(block
, inst
);
2898 invalidate_live_intervals();
2902 * Turns the generic expression-style uniform pull constant load instruction
2903 * into a hardware-specific series of instructions for loading a pull
2906 * The expression style allows the CSE pass before this to optimize out
2907 * repeated loads from the same offset, and gives the pre-register-allocation
2908 * scheduling full flexibility, while the conversion to native instructions
2909 * allows the post-register-allocation scheduler the best information
2912 * Note that execution masking for setting up pull constant loads is special:
2913 * the channels that need to be written are unrelated to the current execution
2914 * mask, since a later instruction will use one of the result channels as a
2915 * source operand for all 8 or 16 of its channels.
2918 fs_visitor::lower_uniform_pull_constant_loads()
2920 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2921 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
2924 if (devinfo
->gen
>= 7) {
2925 /* The offset arg before was a vec4-aligned byte offset. We need to
2926 * turn it into a dword offset.
2928 fs_reg const_offset_reg
= inst
->src
[1];
2929 assert(const_offset_reg
.file
== IMM
&&
2930 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
2931 const_offset_reg
.fixed_hw_reg
.dw1
.ud
/= 4;
2933 fs_reg payload
, offset
;
2934 if (devinfo
->gen
>= 9) {
2935 /* We have to use a message header on Skylake to get SIMD4x2
2936 * mode. Reserve space for the register.
2938 offset
= payload
= fs_reg(GRF
, alloc
.allocate(2));
2939 offset
.reg_offset
++;
2942 offset
= payload
= fs_reg(GRF
, alloc
.allocate(1));
2946 /* This is actually going to be a MOV, but since only the first dword
2947 * is accessed, we have a special opcode to do just that one. Note
2948 * that this needs to be an operation that will be considered a def
2949 * by live variable analysis, or register allocation will explode.
2951 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
2952 8, offset
, const_offset_reg
);
2953 setup
->force_writemask_all
= true;
2955 setup
->ir
= inst
->ir
;
2956 setup
->annotation
= inst
->annotation
;
2957 inst
->insert_before(block
, setup
);
2959 /* Similarly, this will only populate the first 4 channels of the
2960 * result register (since we only use smear values from 0-3), but we
2961 * don't tell the optimizer.
2963 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
2964 inst
->src
[1] = payload
;
2965 inst
->base_mrf
= -1;
2967 invalidate_live_intervals();
2969 /* Before register allocation, we didn't tell the scheduler about the
2970 * MRF we use. We know it's safe to use this MRF because nothing
2971 * else does except for register spill/unspill, which generates and
2972 * uses its MRF within a single IR instruction.
2974 inst
->base_mrf
= 14;
2981 fs_visitor::lower_load_payload()
2983 bool progress
= false;
2985 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2986 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2989 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== GRF
);
2990 assert(inst
->saturate
== false);
2991 fs_reg dst
= inst
->dst
;
2993 /* Get rid of COMPR4. We'll add it back in if we need it */
2994 if (dst
.file
== MRF
)
2995 dst
.reg
= dst
.reg
& ~BRW_MRF_COMPR4
;
2997 const fs_builder hbld
= bld
.exec_all().group(8, 0).at(block
, inst
);
2999 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3000 if (inst
->src
[i
].file
!= BAD_FILE
) {
3001 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3002 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3003 hbld
.MOV(mov_dst
, mov_src
);
3005 dst
= offset(dst
, hbld
, 1);
3008 const fs_builder ibld
= bld
.exec_all(inst
->force_writemask_all
)
3009 .group(inst
->exec_size
, inst
->force_sechalf
)
3012 if (inst
->dst
.file
== MRF
&& (inst
->dst
.reg
& BRW_MRF_COMPR4
) &&
3013 inst
->exec_size
> 8) {
3014 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3015 * a straightforward copy. Instead, the result of the
3016 * LOAD_PAYLOAD is treated as interleaved and the first four
3017 * non-header sources are unpacked as:
3028 * This is used for gen <= 5 fb writes.
3030 assert(inst
->exec_size
== 16);
3031 assert(inst
->header_size
+ 4 <= inst
->sources
);
3032 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3033 if (inst
->src
[i
].file
!= BAD_FILE
) {
3034 if (devinfo
->has_compr4
) {
3035 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3036 compr4_dst
.reg
|= BRW_MRF_COMPR4
;
3037 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3039 /* Platform doesn't have COMPR4. We have to fake it */
3040 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3041 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3043 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3050 /* The loop above only ever incremented us through the first set
3051 * of 4 registers. However, thanks to the magic of COMPR4, we
3052 * actually wrote to the first 8 registers, so we need to take
3053 * that into account now.
3057 /* The COMPR4 code took care of the first 4 sources. We'll let
3058 * the regular path handle any remaining sources. Yes, we are
3059 * modifying the instruction but we're about to delete it so
3060 * this really doesn't hurt anything.
3062 inst
->header_size
+= 4;
3065 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3066 if (inst
->src
[i
].file
!= BAD_FILE
)
3067 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3068 dst
= offset(dst
, ibld
, 1);
3071 inst
->remove(block
);
3076 invalidate_live_intervals();
3082 fs_visitor::lower_integer_multiplication()
3084 bool progress
= false;
3086 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit operation
3087 * directly, but Cherryview cannot.
3089 if (devinfo
->gen
>= 8 && !devinfo
->is_cherryview
)
3092 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3093 if (inst
->opcode
!= BRW_OPCODE_MUL
||
3094 inst
->dst
.is_accumulator() ||
3095 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3096 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3099 const fs_builder ibld
= bld
.at(block
, inst
);
3101 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3102 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3105 * If multiplying by an immediate value that fits in 16-bits, do a
3106 * single MUL instruction with that value in the proper location.
3108 if (inst
->src
[1].file
== IMM
&&
3109 inst
->src
[1].fixed_hw_reg
.dw1
.ud
< (1 << 16)) {
3110 if (devinfo
->gen
< 7) {
3111 fs_reg
imm(GRF
, alloc
.allocate(dispatch_width
/ 8),
3113 ibld
.MOV(imm
, inst
->src
[1]);
3114 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3116 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3119 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3120 * do 32-bit integer multiplication in one instruction, but instead
3121 * must do a sequence (which actually calculates a 64-bit result):
3123 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3124 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3125 * mov(8) g2<1>D acc0<8,8,1>D
3127 * But on Gen > 6, the ability to use second accumulator register
3128 * (acc1) for non-float data types was removed, preventing a simple
3129 * implementation in SIMD16. A 16-channel result can be calculated by
3130 * executing the three instructions twice in SIMD8, once with quarter
3131 * control of 1Q for the first eight channels and again with 2Q for
3132 * the second eight channels.
3134 * Which accumulator register is implicitly accessed (by AccWrEnable
3135 * for instance) is determined by the quarter control. Unfortunately
3136 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3137 * implicit accumulator access by an instruction with 2Q will access
3138 * acc1 regardless of whether the data type is usable in acc1.
3140 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3141 * integer data types.
3143 * Since we only want the low 32-bits of the result, we can do two
3144 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3145 * adjust the high result and add them (like the mach is doing):
3147 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3148 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3149 * shl(8) g9<1>D g8<8,8,1>D 16D
3150 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3152 * We avoid the shl instruction by realizing that we only want to add
3153 * the low 16-bits of the "high" result to the high 16-bits of the
3154 * "low" result and using proper regioning on the add:
3156 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3157 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3158 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3160 * Since it does not use the (single) accumulator register, we can
3161 * schedule multi-component multiplications much better.
3164 if (inst
->conditional_mod
&& inst
->dst
.is_null()) {
3165 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
3168 fs_reg low
= inst
->dst
;
3169 fs_reg
high(GRF
, alloc
.allocate(dispatch_width
/ 8),
3172 if (devinfo
->gen
>= 7) {
3173 fs_reg src1_0_w
= inst
->src
[1];
3174 fs_reg src1_1_w
= inst
->src
[1];
3176 if (inst
->src
[1].file
== IMM
) {
3177 src1_0_w
.fixed_hw_reg
.dw1
.ud
&= 0xffff;
3178 src1_1_w
.fixed_hw_reg
.dw1
.ud
>>= 16;
3180 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3181 if (src1_0_w
.stride
!= 0) {
3182 assert(src1_0_w
.stride
== 1);
3183 src1_0_w
.stride
= 2;
3186 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3187 if (src1_1_w
.stride
!= 0) {
3188 assert(src1_1_w
.stride
== 1);
3189 src1_1_w
.stride
= 2;
3191 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3193 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3194 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3196 fs_reg src0_0_w
= inst
->src
[0];
3197 fs_reg src0_1_w
= inst
->src
[0];
3199 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3200 if (src0_0_w
.stride
!= 0) {
3201 assert(src0_0_w
.stride
== 1);
3202 src0_0_w
.stride
= 2;
3205 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3206 if (src0_1_w
.stride
!= 0) {
3207 assert(src0_1_w
.stride
== 1);
3208 src0_1_w
.stride
= 2;
3210 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3212 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3213 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3216 fs_reg dst
= inst
->dst
;
3217 dst
.type
= BRW_REGISTER_TYPE_UW
;
3218 dst
.subreg_offset
= 2;
3221 high
.type
= BRW_REGISTER_TYPE_UW
;
3224 low
.type
= BRW_REGISTER_TYPE_UW
;
3225 low
.subreg_offset
= 2;
3228 ibld
.ADD(dst
, low
, high
);
3230 if (inst
->conditional_mod
) {
3231 fs_reg
null(retype(ibld
.null_reg_f(), inst
->dst
.type
));
3232 set_condmod(inst
->conditional_mod
,
3233 ibld
.MOV(null
, inst
->dst
));
3237 inst
->remove(block
);
3242 invalidate_live_intervals();
3248 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3249 fs_reg
*dst
, fs_reg color
, unsigned components
)
3251 if (key
->clamp_fragment_color
) {
3252 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3253 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3255 for (unsigned i
= 0; i
< components
; i
++)
3257 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3262 for (unsigned i
= 0; i
< components
; i
++)
3263 dst
[i
] = offset(color
, bld
, i
);
3267 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3268 const brw_wm_prog_data
*prog_data
,
3269 const brw_wm_prog_key
*key
,
3270 const fs_visitor::thread_payload
&payload
)
3272 assert(inst
->src
[6].file
== IMM
);
3273 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3274 const fs_reg
&color0
= inst
->src
[0];
3275 const fs_reg
&color1
= inst
->src
[1];
3276 const fs_reg
&src0_alpha
= inst
->src
[2];
3277 const fs_reg
&src_depth
= inst
->src
[3];
3278 const fs_reg
&dst_depth
= inst
->src
[4];
3279 fs_reg sample_mask
= inst
->src
[5];
3280 const unsigned components
= inst
->src
[6].fixed_hw_reg
.dw1
.ud
;
3282 /* We can potentially have a message length of up to 15, so we have to set
3283 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3286 int header_size
= 2, payload_header_size
;
3287 unsigned length
= 0;
3289 /* From the Sandy Bridge PRM, volume 4, page 198:
3291 * "Dispatched Pixel Enables. One bit per pixel indicating
3292 * which pixels were originally enabled when the thread was
3293 * dispatched. This field is only required for the end-of-
3294 * thread message and on all dual-source messages."
3296 if (devinfo
->gen
>= 6 &&
3297 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3298 color1
.file
== BAD_FILE
&&
3299 key
->nr_color_regions
== 1) {
3303 if (header_size
!= 0) {
3304 assert(header_size
== 2);
3305 /* Allocate 2 registers for a header */
3309 if (payload
.aa_dest_stencil_reg
) {
3310 sources
[length
] = fs_reg(GRF
, bld
.shader
->alloc
.allocate(1));
3311 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3312 .MOV(sources
[length
],
3313 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3317 if (prog_data
->uses_omask
) {
3318 sources
[length
] = fs_reg(GRF
, bld
.shader
->alloc
.allocate(1),
3319 BRW_REGISTER_TYPE_UD
);
3321 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3322 * relevant. Since it's unsigned single words one vgrf is always
3323 * 16-wide, but only the lower or higher 8 channels will be used by the
3324 * hardware when doing a SIMD8 write depending on whether we have
3325 * selected the subspans for the first or second half respectively.
3327 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3328 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3329 sample_mask
.stride
*= 2;
3331 bld
.exec_all().annotate("FB write oMask")
3332 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3333 inst
->force_sechalf
),
3338 payload_header_size
= length
;
3340 if (src0_alpha
.file
!= BAD_FILE
) {
3341 /* FIXME: This is being passed at the wrong location in the payload and
3342 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3343 * It's supposed to be immediately before oMask but there seems to be no
3344 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3345 * requires header sources to form a contiguous segment at the beginning
3346 * of the message and src0_alpha has per-channel semantics.
3348 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3352 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3355 if (color1
.file
!= BAD_FILE
) {
3356 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3360 if (src_depth
.file
!= BAD_FILE
) {
3361 sources
[length
] = src_depth
;
3365 if (dst_depth
.file
!= BAD_FILE
) {
3366 sources
[length
] = dst_depth
;
3371 if (devinfo
->gen
>= 7) {
3372 /* Send from the GRF */
3373 fs_reg payload
= fs_reg(GRF
, -1, BRW_REGISTER_TYPE_F
);
3374 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3375 payload
.reg
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3376 load
->dst
= payload
;
3378 inst
->src
[0] = payload
;
3379 inst
->resize_sources(1);
3380 inst
->base_mrf
= -1;
3382 /* Send from the MRF */
3383 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3384 sources
, length
, payload_header_size
);
3386 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3387 * will do this for us if we just give it a COMPR4 destination.
3389 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3390 load
->dst
.reg
|= BRW_MRF_COMPR4
;
3392 inst
->resize_sources(0);
3396 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3397 inst
->mlen
= load
->regs_written
;
3398 inst
->header_size
= header_size
;
3402 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3403 const fs_reg
&coordinate
,
3404 const fs_reg
&shadow_c
,
3405 const fs_reg
&lod
, const fs_reg
&lod2
,
3406 const fs_reg
&sampler
,
3407 unsigned coord_components
,
3408 unsigned grad_components
)
3410 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3411 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3412 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3413 fs_reg msg_end
= msg_begin
;
3416 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3418 for (unsigned i
= 0; i
< coord_components
; i
++)
3419 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3420 offset(coordinate
, bld
, i
));
3422 msg_end
= offset(msg_end
, bld
, coord_components
);
3424 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3425 * require all three components to be present and zero if they are unused.
3427 if (coord_components
> 0 &&
3428 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3429 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3430 for (unsigned i
= coord_components
; i
< 3; i
++)
3431 bld
.MOV(offset(msg_end
, bld
, i
), fs_reg(0.0f
));
3433 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3436 if (op
== SHADER_OPCODE_TXD
) {
3437 /* TXD unsupported in SIMD16 mode. */
3438 assert(bld
.dispatch_width() == 8);
3440 /* the slots for u and v are always present, but r is optional */
3441 if (coord_components
< 2)
3442 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3445 * dPdx = dudx, dvdx, drdx
3446 * dPdy = dudy, dvdy, drdy
3448 * 1-arg: Does not exist.
3450 * 2-arg: dudx dvdx dudy dvdy
3451 * dPdx.x dPdx.y dPdy.x dPdy.y
3454 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3455 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3456 * m5 m6 m7 m8 m9 m10
3458 for (unsigned i
= 0; i
< grad_components
; i
++)
3459 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3461 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3463 for (unsigned i
= 0; i
< grad_components
; i
++)
3464 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3466 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3470 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3471 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3473 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3474 bld
.dispatch_width() == 16);
3476 const brw_reg_type type
=
3477 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3478 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3479 bld
.MOV(retype(msg_end
, type
), lod
);
3480 msg_end
= offset(msg_end
, bld
, 1);
3483 if (shadow_c
.file
!= BAD_FILE
) {
3484 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3485 /* There's no plain shadow compare message, so we use shadow
3486 * compare with a bias of 0.0.
3488 bld
.MOV(msg_end
, fs_reg(0.0f
));
3489 msg_end
= offset(msg_end
, bld
, 1);
3492 bld
.MOV(msg_end
, shadow_c
);
3493 msg_end
= offset(msg_end
, bld
, 1);
3497 inst
->src
[0] = reg_undef
;
3498 inst
->src
[1] = sampler
;
3499 inst
->resize_sources(2);
3500 inst
->base_mrf
= msg_begin
.reg
;
3501 inst
->mlen
= msg_end
.reg
- msg_begin
.reg
;
3502 inst
->header_size
= 1;
3506 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3508 const fs_reg
&shadow_c
,
3509 fs_reg lod
, fs_reg lod2
,
3510 const fs_reg
&sample_index
,
3511 const fs_reg
&sampler
,
3512 const fs_reg
&offset_value
,
3513 unsigned coord_components
,
3514 unsigned grad_components
)
3516 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3517 fs_reg msg_coords
= message
;
3518 unsigned header_size
= 0;
3520 if (offset_value
.file
!= BAD_FILE
) {
3521 /* The offsets set up by the visitor are in the m1 header, so we can't
3528 for (unsigned i
= 0; i
< coord_components
; i
++) {
3529 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3530 coordinate
= offset(coordinate
, bld
, 1);
3532 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3533 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3535 if (shadow_c
.file
!= BAD_FILE
) {
3536 fs_reg msg_shadow
= msg_lod
;
3537 bld
.MOV(msg_shadow
, shadow_c
);
3538 msg_lod
= offset(msg_shadow
, bld
, 1);
3543 case SHADER_OPCODE_TXL
:
3545 bld
.MOV(msg_lod
, lod
);
3546 msg_end
= offset(msg_lod
, bld
, 1);
3548 case SHADER_OPCODE_TXD
:
3551 * dPdx = dudx, dvdx, drdx
3552 * dPdy = dudy, dvdy, drdy
3554 * Load up these values:
3555 * - dudx dudy dvdx dvdy drdx drdy
3556 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3559 for (unsigned i
= 0; i
< grad_components
; i
++) {
3560 bld
.MOV(msg_end
, lod
);
3561 lod
= offset(lod
, bld
, 1);
3562 msg_end
= offset(msg_end
, bld
, 1);
3564 bld
.MOV(msg_end
, lod2
);
3565 lod2
= offset(lod2
, bld
, 1);
3566 msg_end
= offset(msg_end
, bld
, 1);
3569 case SHADER_OPCODE_TXS
:
3570 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3571 bld
.MOV(msg_lod
, lod
);
3572 msg_end
= offset(msg_lod
, bld
, 1);
3574 case SHADER_OPCODE_TXF
:
3575 msg_lod
= offset(msg_coords
, bld
, 3);
3576 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3577 msg_end
= offset(msg_lod
, bld
, 1);
3579 case SHADER_OPCODE_TXF_CMS
:
3580 msg_lod
= offset(msg_coords
, bld
, 3);
3582 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
3584 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3585 msg_end
= offset(msg_lod
, bld
, 2);
3592 inst
->src
[0] = reg_undef
;
3593 inst
->src
[1] = sampler
;
3594 inst
->resize_sources(2);
3595 inst
->base_mrf
= message
.reg
;
3596 inst
->mlen
= msg_end
.reg
- message
.reg
;
3597 inst
->header_size
= header_size
;
3599 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3600 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3604 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3606 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3609 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
3613 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3615 const fs_reg
&shadow_c
,
3616 fs_reg lod
, fs_reg lod2
,
3617 const fs_reg
&sample_index
,
3618 const fs_reg
&mcs
, const fs_reg
&sampler
,
3619 fs_reg offset_value
,
3620 unsigned coord_components
,
3621 unsigned grad_components
)
3623 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3624 int reg_width
= bld
.dispatch_width() / 8;
3625 unsigned header_size
= 0, length
= 0;
3626 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3627 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3628 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3630 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3631 offset_value
.file
!= BAD_FILE
||
3632 is_high_sampler(devinfo
, sampler
)) {
3633 /* For general texture offsets (no txf workaround), we need a header to
3634 * put them in. Note that we're only reserving space for it in the
3635 * message payload as it will be initialized implicitly by the
3638 * TG4 needs to place its channel select in the header, for interaction
3639 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3640 * larger sampler numbers we need to offset the Sampler State Pointer in
3644 sources
[0] = fs_reg();
3648 if (shadow_c
.file
!= BAD_FILE
) {
3649 bld
.MOV(sources
[length
], shadow_c
);
3653 bool coordinate_done
= false;
3655 /* The sampler can only meaningfully compute LOD for fragment shader
3656 * messages. For all other stages, we change the opcode to TXL and
3657 * hardcode the LOD to 0.
3659 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3660 op
== SHADER_OPCODE_TEX
) {
3661 op
= SHADER_OPCODE_TXL
;
3665 /* Set up the LOD info */
3668 case SHADER_OPCODE_TXL
:
3669 bld
.MOV(sources
[length
], lod
);
3672 case SHADER_OPCODE_TXD
:
3673 /* TXD should have been lowered in SIMD16 mode. */
3674 assert(bld
.dispatch_width() == 8);
3676 /* Load dPdx and the coordinate together:
3677 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3679 for (unsigned i
= 0; i
< coord_components
; i
++) {
3680 bld
.MOV(sources
[length
], coordinate
);
3681 coordinate
= offset(coordinate
, bld
, 1);
3684 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3685 * only derivatives for (u, v, r).
3687 if (i
< grad_components
) {
3688 bld
.MOV(sources
[length
], lod
);
3689 lod
= offset(lod
, bld
, 1);
3692 bld
.MOV(sources
[length
], lod2
);
3693 lod2
= offset(lod2
, bld
, 1);
3698 coordinate_done
= true;
3700 case SHADER_OPCODE_TXS
:
3701 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3704 case SHADER_OPCODE_TXF
:
3705 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3706 * On Gen9 they are u, v, lod, r
3708 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3709 coordinate
= offset(coordinate
, bld
, 1);
3712 if (devinfo
->gen
>= 9) {
3713 if (coord_components
>= 2) {
3714 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3715 coordinate
= offset(coordinate
, bld
, 1);
3720 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
3723 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
3724 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3725 coordinate
= offset(coordinate
, bld
, 1);
3729 coordinate_done
= true;
3731 case SHADER_OPCODE_TXF_CMS
:
3732 case SHADER_OPCODE_TXF_UMS
:
3733 case SHADER_OPCODE_TXF_MCS
:
3734 if (op
== SHADER_OPCODE_TXF_UMS
|| op
== SHADER_OPCODE_TXF_CMS
) {
3735 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
3739 if (op
== SHADER_OPCODE_TXF_CMS
) {
3740 /* Data from the multisample control surface. */
3741 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
3745 /* There is no offsetting for this message; just copy in the integer
3746 * texture coordinates.
3748 for (unsigned i
= 0; i
< coord_components
; i
++) {
3749 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3750 coordinate
= offset(coordinate
, bld
, 1);
3754 coordinate_done
= true;
3756 case SHADER_OPCODE_TG4_OFFSET
:
3757 /* gather4_po_c should have been lowered in SIMD16 mode. */
3758 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
3760 /* More crazy intermixing */
3761 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
3762 bld
.MOV(sources
[length
], coordinate
);
3763 coordinate
= offset(coordinate
, bld
, 1);
3767 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
3768 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
3769 offset_value
= offset(offset_value
, bld
, 1);
3773 if (coord_components
== 3) { /* r if present */
3774 bld
.MOV(sources
[length
], coordinate
);
3775 coordinate
= offset(coordinate
, bld
, 1);
3779 coordinate_done
= true;
3785 /* Set up the coordinate (except for cases where it was done above) */
3786 if (!coordinate_done
) {
3787 for (unsigned i
= 0; i
< coord_components
; i
++) {
3788 bld
.MOV(sources
[length
], coordinate
);
3789 coordinate
= offset(coordinate
, bld
, 1);
3796 mlen
= length
* reg_width
- header_size
;
3798 mlen
= length
* reg_width
;
3800 const fs_reg src_payload
= fs_reg(GRF
, bld
.shader
->alloc
.allocate(mlen
),
3801 BRW_REGISTER_TYPE_F
);
3802 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
3804 /* Generate the SEND. */
3806 inst
->src
[0] = src_payload
;
3807 inst
->src
[1] = sampler
;
3808 inst
->resize_sources(2);
3809 inst
->base_mrf
= -1;
3811 inst
->header_size
= header_size
;
3813 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3814 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3818 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
3820 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3821 const fs_reg
&coordinate
= inst
->src
[0];
3822 const fs_reg
&shadow_c
= inst
->src
[1];
3823 const fs_reg
&lod
= inst
->src
[2];
3824 const fs_reg
&lod2
= inst
->src
[3];
3825 const fs_reg
&sample_index
= inst
->src
[4];
3826 const fs_reg
&mcs
= inst
->src
[5];
3827 const fs_reg
&sampler
= inst
->src
[6];
3828 const fs_reg
&offset_value
= inst
->src
[7];
3829 assert(inst
->src
[8].file
== IMM
&& inst
->src
[9].file
== IMM
);
3830 const unsigned coord_components
= inst
->src
[8].fixed_hw_reg
.dw1
.ud
;
3831 const unsigned grad_components
= inst
->src
[9].fixed_hw_reg
.dw1
.ud
;
3833 if (devinfo
->gen
>= 7) {
3834 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
3835 shadow_c
, lod
, lod2
, sample_index
,
3836 mcs
, sampler
, offset_value
,
3837 coord_components
, grad_components
);
3838 } else if (devinfo
->gen
>= 5) {
3839 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
3840 shadow_c
, lod
, lod2
, sample_index
,
3841 sampler
, offset_value
,
3842 coord_components
, grad_components
);
3844 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
3845 shadow_c
, lod
, lod2
, sampler
,
3846 coord_components
, grad_components
);
3851 fs_visitor::lower_logical_sends()
3853 bool progress
= false;
3855 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3856 const fs_builder ibld
= bld
.exec_all(inst
->force_writemask_all
)
3857 .group(inst
->exec_size
, inst
->force_sechalf
)
3860 switch (inst
->opcode
) {
3861 case FS_OPCODE_FB_WRITE_LOGICAL
:
3862 assert(stage
== MESA_SHADER_FRAGMENT
);
3863 lower_fb_write_logical_send(ibld
, inst
,
3864 (const brw_wm_prog_data
*)prog_data
,
3865 (const brw_wm_prog_key
*)key
,
3869 case SHADER_OPCODE_TEX_LOGICAL
:
3870 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
3873 case SHADER_OPCODE_TXD_LOGICAL
:
3874 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
3877 case SHADER_OPCODE_TXF_LOGICAL
:
3878 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
3881 case SHADER_OPCODE_TXL_LOGICAL
:
3882 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
3885 case SHADER_OPCODE_TXS_LOGICAL
:
3886 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
3889 case FS_OPCODE_TXB_LOGICAL
:
3890 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
3893 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
3894 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
3897 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
3898 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
3901 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
3902 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
3905 case SHADER_OPCODE_LOD_LOGICAL
:
3906 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
3909 case SHADER_OPCODE_TG4_LOGICAL
:
3910 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
3913 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
3914 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
3925 invalidate_live_intervals();
3931 * Get the closest native SIMD width supported by the hardware for instruction
3932 * \p inst. The instruction will be left untouched by
3933 * fs_visitor::lower_simd_width() if the returned value is equal to the
3934 * original execution size.
3937 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
3938 const fs_inst
*inst
)
3940 switch (inst
->opcode
) {
3941 case FS_OPCODE_FB_WRITE_LOGICAL
:
3942 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
3945 assert(devinfo
->gen
!= 6 || inst
->src
[3].file
== BAD_FILE
||
3946 inst
->exec_size
== 8);
3947 /* Dual-source FB writes are unsupported in SIMD16 mode. */
3948 return (inst
->src
[1].file
!= BAD_FILE
? 8 : inst
->exec_size
);
3950 case SHADER_OPCODE_TXD_LOGICAL
:
3951 /* TXD is unsupported in SIMD16 mode. */
3954 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
3955 /* gather4_po_c is unsupported in SIMD16 mode. */
3956 const fs_reg
&shadow_c
= inst
->src
[1];
3957 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
3959 case SHADER_OPCODE_TXL_LOGICAL
:
3960 case FS_OPCODE_TXB_LOGICAL
: {
3961 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
3962 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
3963 * mode because the message exceeds the maximum length of 11.
3965 const fs_reg
&shadow_c
= inst
->src
[1];
3966 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
3968 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
3971 return inst
->exec_size
;
3973 case SHADER_OPCODE_TXF_LOGICAL
:
3974 case SHADER_OPCODE_TXS_LOGICAL
:
3975 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
3976 * messages. Use SIMD16 instead.
3978 if (devinfo
->gen
== 4)
3981 return inst
->exec_size
;
3984 return inst
->exec_size
;
3989 * The \p rows array of registers represents a \p num_rows by \p num_columns
3990 * matrix in row-major order, write it in column-major order into the register
3991 * passed as destination. \p stride gives the separation between matrix
3992 * elements in the input in fs_builder::dispatch_width() units.
3995 emit_transpose(const fs_builder
&bld
,
3996 const fs_reg
&dst
, const fs_reg
*rows
,
3997 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
3999 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4001 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4002 for (unsigned j
= 0; j
< num_rows
; ++j
)
4003 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4006 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4008 delete[] components
;
4012 fs_visitor::lower_simd_width()
4014 bool progress
= false;
4016 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4017 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4019 if (lower_width
!= inst
->exec_size
) {
4020 /* Builder matching the original instruction. */
4021 const fs_builder ibld
= bld
.at(block
, inst
)
4022 .exec_all(inst
->force_writemask_all
)
4023 .group(inst
->exec_size
, inst
->force_sechalf
);
4025 /* Split the copies in chunks of the execution width of either the
4026 * original or the lowered instruction, whichever is lower.
4028 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4029 const unsigned n
= inst
->exec_size
/ copy_width
;
4030 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4031 inst
->dst
.component_size(inst
->exec_size
);
4034 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4035 !inst
->writes_accumulator
&& !inst
->mlen
);
4037 for (unsigned i
= 0; i
< n
; i
++) {
4038 /* Emit a copy of the original instruction with the lowered width.
4039 * If the EOT flag was set throw it away except for the last
4040 * instruction to avoid killing the thread prematurely.
4042 fs_inst split_inst
= *inst
;
4043 split_inst
.exec_size
= lower_width
;
4044 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4046 /* Set exec_all if the lowered width is higher than the original
4047 * to avoid breaking the compiler invariant that no control
4048 * flow-masked instruction is wider than the shader's
4049 * dispatch_width. Then transform the sources and destination and
4050 * emit the lowered instruction.
4052 const fs_builder lbld
= ibld
.exec_all(lower_width
> inst
->exec_size
)
4053 .group(lower_width
, i
);
4055 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4056 if (inst
->src
[j
].file
!= BAD_FILE
&&
4057 !is_uniform(inst
->src
[j
])) {
4058 /* Get the i-th copy_width-wide chunk of the source. */
4059 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4060 const unsigned src_size
= inst
->components_read(j
);
4062 /* Use a trivial transposition to copy one every n
4063 * copy_width-wide components of the register into a
4064 * temporary passed as source to the lowered instruction.
4066 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4067 emit_transpose(lbld
.group(copy_width
, 0),
4068 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4072 if (inst
->regs_written
) {
4073 /* Allocate enough space to hold the result of the lowered
4074 * instruction and fix up the number of registers written.
4076 split_inst
.dst
= dsts
[i
] =
4077 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4078 split_inst
.regs_written
=
4079 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4083 lbld
.emit(split_inst
);
4086 if (inst
->regs_written
) {
4087 /* Distance between useful channels in the temporaries, skipping
4088 * garbage if the lowered instruction is wider than the original.
4090 const unsigned m
= lower_width
/ copy_width
;
4092 /* Interleave the components of the result from the lowered
4093 * instructions. We need to set exec_all() when copying more than
4094 * one half per component, because LOAD_PAYLOAD (in terms of which
4095 * emit_transpose is implemented) can only use the same channel
4096 * enable signals for all of its non-header sources.
4098 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4099 .group(copy_width
, 0),
4100 inst
->dst
, dsts
, n
, dst_size
, m
);
4103 inst
->remove(block
);
4109 invalidate_live_intervals();
4115 fs_visitor::dump_instructions()
4117 dump_instructions(NULL
);
4121 fs_visitor::dump_instructions(const char *name
)
4123 FILE *file
= stderr
;
4124 if (name
&& geteuid() != 0) {
4125 file
= fopen(name
, "w");
4131 calculate_register_pressure();
4132 int ip
= 0, max_pressure
= 0;
4133 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4134 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4135 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4136 dump_instruction(inst
, file
);
4139 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4142 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4143 fprintf(file
, "%4d: ", ip
++);
4144 dump_instruction(inst
, file
);
4148 if (file
!= stderr
) {
4154 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4156 dump_instruction(be_inst
, stderr
);
4160 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4162 fs_inst
*inst
= (fs_inst
*)be_inst
;
4164 if (inst
->predicate
) {
4165 fprintf(file
, "(%cf0.%d) ",
4166 inst
->predicate_inverse
? '-' : '+',
4170 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4172 fprintf(file
, ".sat");
4173 if (inst
->conditional_mod
) {
4174 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4175 if (!inst
->predicate
&&
4176 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4177 inst
->opcode
!= BRW_OPCODE_IF
&&
4178 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4179 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4182 fprintf(file
, "(%d) ", inst
->exec_size
);
4185 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4188 switch (inst
->dst
.file
) {
4190 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
4191 if (alloc
.sizes
[inst
->dst
.reg
] != inst
->regs_written
||
4192 inst
->dst
.subreg_offset
)
4193 fprintf(file
, "+%d.%d",
4194 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4197 fprintf(file
, "m%d", inst
->dst
.reg
);
4200 fprintf(file
, "(null)");
4203 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
4206 fprintf(file
, "***attr%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
4209 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
4210 switch (inst
->dst
.fixed_hw_reg
.nr
) {
4212 fprintf(file
, "null");
4214 case BRW_ARF_ADDRESS
:
4215 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
4217 case BRW_ARF_ACCUMULATOR
:
4218 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
4221 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
4222 inst
->dst
.fixed_hw_reg
.subnr
);
4225 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
4226 inst
->dst
.fixed_hw_reg
.subnr
);
4230 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
4232 if (inst
->dst
.fixed_hw_reg
.subnr
)
4233 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
4236 fprintf(file
, "???");
4239 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4241 for (int i
= 0; i
< inst
->sources
; i
++) {
4242 if (inst
->src
[i
].negate
)
4244 if (inst
->src
[i
].abs
)
4246 switch (inst
->src
[i
].file
) {
4248 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
4249 if (alloc
.sizes
[inst
->src
[i
].reg
] != (unsigned)inst
->regs_read(i
) ||
4250 inst
->src
[i
].subreg_offset
)
4251 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4252 inst
->src
[i
].subreg_offset
);
4255 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
4258 fprintf(file
, "attr%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
4261 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
4262 if (inst
->src
[i
].reladdr
) {
4263 fprintf(file
, "+reladdr");
4264 } else if (inst
->src
[i
].subreg_offset
) {
4265 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4266 inst
->src
[i
].subreg_offset
);
4270 fprintf(file
, "(null)");
4273 switch (inst
->src
[i
].type
) {
4274 case BRW_REGISTER_TYPE_F
:
4275 fprintf(file
, "%ff", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
4277 case BRW_REGISTER_TYPE_W
:
4278 case BRW_REGISTER_TYPE_D
:
4279 fprintf(file
, "%dd", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
4281 case BRW_REGISTER_TYPE_UW
:
4282 case BRW_REGISTER_TYPE_UD
:
4283 fprintf(file
, "%uu", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
4285 case BRW_REGISTER_TYPE_VF
:
4286 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4287 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
4288 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
4289 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
4290 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
4293 fprintf(file
, "???");
4298 if (inst
->src
[i
].fixed_hw_reg
.negate
)
4300 if (inst
->src
[i
].fixed_hw_reg
.abs
)
4302 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
4303 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
4305 fprintf(file
, "null");
4307 case BRW_ARF_ADDRESS
:
4308 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4310 case BRW_ARF_ACCUMULATOR
:
4311 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4314 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
4315 inst
->src
[i
].fixed_hw_reg
.subnr
);
4318 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
4319 inst
->src
[i
].fixed_hw_reg
.subnr
);
4323 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
4325 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
4326 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4327 if (inst
->src
[i
].fixed_hw_reg
.abs
)
4331 fprintf(file
, "???");
4334 if (inst
->src
[i
].abs
)
4337 if (inst
->src
[i
].file
!= IMM
) {
4338 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4341 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4342 fprintf(file
, ", ");
4347 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4348 if (inst
->force_sechalf
)
4349 fprintf(file
, "2ndhalf ");
4351 fprintf(file
, "1sthalf ");
4354 fprintf(file
, "\n");
4358 * Possibly returns an instruction that set up @param reg.
4360 * Sometimes we want to take the result of some expression/variable
4361 * dereference tree and rewrite the instruction generating the result
4362 * of the tree. When processing the tree, we know that the
4363 * instructions generated are all writing temporaries that are dead
4364 * outside of this tree. So, if we have some instructions that write
4365 * a temporary, we're free to point that temp write somewhere else.
4367 * Note that this doesn't guarantee that the instruction generated
4368 * only reg -- it might be the size=4 destination of a texture instruction.
4371 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4376 end
->is_partial_write() ||
4378 !reg
.equals(end
->dst
)) {
4386 fs_visitor::setup_payload_gen6()
4389 (prog
->InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
4390 unsigned barycentric_interp_modes
=
4391 (stage
== MESA_SHADER_FRAGMENT
) ?
4392 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4394 assert(devinfo
->gen
>= 6);
4396 /* R0-1: masks, pixel X/Y coordinates. */
4397 payload
.num_regs
= 2;
4398 /* R2: only for 32-pixel dispatch.*/
4400 /* R3-26: barycentric interpolation coordinates. These appear in the
4401 * same order that they appear in the brw_wm_barycentric_interp_mode
4402 * enum. Each set of coordinates occupies 2 registers if dispatch width
4403 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4404 * appear if they were enabled using the "Barycentric Interpolation
4405 * Mode" bits in WM_STATE.
4407 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4408 if (barycentric_interp_modes
& (1 << i
)) {
4409 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4410 payload
.num_regs
+= 2;
4411 if (dispatch_width
== 16) {
4412 payload
.num_regs
+= 2;
4417 /* R27: interpolated depth if uses source depth */
4419 payload
.source_depth_reg
= payload
.num_regs
;
4421 if (dispatch_width
== 16) {
4422 /* R28: interpolated depth if not SIMD8. */
4426 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4428 payload
.source_w_reg
= payload
.num_regs
;
4430 if (dispatch_width
== 16) {
4431 /* R30: interpolated W if not SIMD8. */
4436 if (stage
== MESA_SHADER_FRAGMENT
) {
4437 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4438 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4439 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4440 /* R31: MSAA position offsets. */
4441 if (prog_data
->uses_pos_offset
) {
4442 payload
.sample_pos_reg
= payload
.num_regs
;
4447 /* R32: MSAA input coverage mask */
4448 if (prog
->SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4449 assert(devinfo
->gen
>= 7);
4450 payload
.sample_mask_in_reg
= payload
.num_regs
;
4452 if (dispatch_width
== 16) {
4453 /* R33: input coverage mask if not SIMD8. */
4458 /* R34-: bary for 32-pixel. */
4459 /* R58-59: interp W for 32-pixel. */
4461 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4462 source_depth_to_render_target
= true;
4467 fs_visitor::setup_vs_payload()
4469 /* R0: thread header, R1: urb handles */
4470 payload
.num_regs
= 2;
4474 fs_visitor::setup_cs_payload()
4476 assert(devinfo
->gen
>= 7);
4478 payload
.num_regs
= 1;
4482 fs_visitor::assign_binding_table_offsets()
4484 assert(stage
== MESA_SHADER_FRAGMENT
);
4485 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4486 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4487 uint32_t next_binding_table_offset
= 0;
4489 /* If there are no color regions, we still perform an FB write to a null
4490 * renderbuffer, which we place at surface index 0.
4492 prog_data
->binding_table
.render_target_start
= next_binding_table_offset
;
4493 next_binding_table_offset
+= MAX2(key
->nr_color_regions
, 1);
4495 assign_common_binding_table_offsets(next_binding_table_offset
);
4499 fs_visitor::calculate_register_pressure()
4501 invalidate_live_intervals();
4502 calculate_live_intervals();
4504 unsigned num_instructions
= 0;
4505 foreach_block(block
, cfg
)
4506 num_instructions
+= block
->instructions
.length();
4508 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
4510 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
4511 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
4512 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
4517 fs_visitor::optimize()
4519 /* bld is the common builder object pointing at the end of the program we
4520 * used to translate it into i965 IR. For the optimization and lowering
4521 * passes coming next, any code added after the end of the program without
4522 * having explicitly called fs_builder::at() clearly points at a mistake.
4523 * Ideally optimization passes wouldn't be part of the visitor so they
4524 * wouldn't have access to bld at all, but they do, so just in case some
4525 * pass forgets to ask for a location explicitly set it to NULL here to
4528 bld
= bld
.at(NULL
, NULL
);
4530 split_virtual_grfs();
4532 move_uniform_array_access_to_pull_constants();
4533 assign_constant_locations();
4534 demote_pull_constants();
4536 #define OPT(pass, args...) ({ \
4538 bool this_progress = pass(args); \
4540 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
4541 char filename[64]; \
4542 snprintf(filename, 64, "%s%d-%04d-%02d-%02d-" #pass, \
4543 stage_abbrev, dispatch_width, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
4545 backend_shader::dump_instructions(filename); \
4548 progress = progress || this_progress; \
4552 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
4554 snprintf(filename
, 64, "%s%d-%04d-00-start",
4555 stage_abbrev
, dispatch_width
,
4556 shader_prog
? shader_prog
->Name
: 0);
4558 backend_shader::dump_instructions(filename
);
4561 bool progress
= false;
4565 OPT(lower_simd_width
);
4566 OPT(lower_logical_sends
);
4573 OPT(remove_duplicate_mrf_writes
);
4577 OPT(opt_copy_propagate
);
4578 OPT(opt_peephole_predicated_break
);
4579 OPT(opt_cmod_propagation
);
4580 OPT(dead_code_eliminate
);
4581 OPT(opt_peephole_sel
);
4582 OPT(dead_control_flow_eliminate
, this);
4583 OPT(opt_register_renaming
);
4584 OPT(opt_redundant_discard_jumps
);
4585 OPT(opt_saturate_propagation
);
4586 OPT(opt_zero_samples
);
4587 OPT(register_coalesce
);
4588 OPT(compute_to_mrf
);
4589 OPT(eliminate_find_live_channel
);
4591 OPT(compact_virtual_grfs
);
4596 OPT(opt_sampler_eot
);
4598 if (OPT(lower_load_payload
)) {
4599 split_virtual_grfs();
4600 OPT(register_coalesce
);
4601 OPT(compute_to_mrf
);
4602 OPT(dead_code_eliminate
);
4605 OPT(opt_combine_constants
);
4606 OPT(lower_integer_multiplication
);
4608 lower_uniform_pull_constant_loads();
4612 * Three source instruction must have a GRF/MRF destination register.
4613 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
4616 fs_visitor::fixup_3src_null_dest()
4618 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
4619 if (inst
->is_3src() && inst
->dst
.is_null()) {
4620 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
4627 fs_visitor::allocate_registers()
4629 bool allocated_without_spills
;
4631 static const enum instruction_scheduler_mode pre_modes
[] = {
4633 SCHEDULE_PRE_NON_LIFO
,
4637 /* Try each scheduling heuristic to see if it can successfully register
4638 * allocate without spilling. They should be ordered by decreasing
4639 * performance but increasing likelihood of allocating.
4641 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
4642 schedule_instructions(pre_modes
[i
]);
4645 assign_regs_trivial();
4646 allocated_without_spills
= true;
4648 allocated_without_spills
= assign_regs(false);
4650 if (allocated_without_spills
)
4654 if (!allocated_without_spills
) {
4655 /* We assume that any spilling is worse than just dropping back to
4656 * SIMD8. There's probably actually some intermediate point where
4657 * SIMD16 with a couple of spills is still better.
4659 if (dispatch_width
== 16) {
4660 fail("Failure to register allocate. Reduce number of "
4661 "live scalar values to avoid this.");
4663 compiler
->shader_perf_log(log_data
,
4664 "%s shader triggered register spilling. "
4665 "Try reducing the number of live scalar "
4666 "values to improve performance.\n",
4670 /* Since we're out of heuristics, just go spill registers until we
4671 * get an allocation.
4673 while (!assign_regs(true)) {
4679 /* This must come after all optimization and register allocation, since
4680 * it inserts dead code that happens to have side effects, and it does
4681 * so based on the actual physical registers in use.
4683 insert_gen4_send_dependency_workarounds();
4688 if (!allocated_without_spills
)
4689 schedule_instructions(SCHEDULE_POST
);
4691 if (last_scratch
> 0)
4692 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
4696 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
4698 assert(stage
== MESA_SHADER_VERTEX
);
4700 assign_common_binding_table_offsets(0);
4703 if (shader_time_index
>= 0)
4704 emit_shader_time_begin();
4711 compute_clip_distance(clip_planes
);
4715 if (shader_time_index
>= 0)
4716 emit_shader_time_end();
4722 assign_curb_setup();
4723 assign_vs_urb_setup();
4725 fixup_3src_null_dest();
4726 allocate_registers();
4732 fs_visitor::run_fs(bool do_rep_send
)
4734 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4735 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
4737 assert(stage
== MESA_SHADER_FRAGMENT
);
4739 sanity_param_count
= prog
->Parameters
->NumParameters
;
4741 assign_binding_table_offsets();
4743 if (devinfo
->gen
>= 6)
4744 setup_payload_gen6();
4746 setup_payload_gen4();
4750 } else if (do_rep_send
) {
4751 assert(dispatch_width
== 16);
4752 emit_repclear_shader();
4754 if (shader_time_index
>= 0)
4755 emit_shader_time_begin();
4757 calculate_urb_setup();
4758 if (prog
->InputsRead
> 0) {
4759 if (devinfo
->gen
< 6)
4760 emit_interpolation_setup_gen4();
4762 emit_interpolation_setup_gen6();
4765 /* We handle discards by keeping track of the still-live pixels in f0.1.
4766 * Initialize it with the dispatched pixels.
4768 if (wm_prog_data
->uses_kill
) {
4769 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
4770 discard_init
->flag_subreg
= 1;
4773 /* Generate FS IR for main(). (the visitor only descends into
4774 * functions called "main").
4781 if (wm_prog_data
->uses_kill
)
4782 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
4784 if (wm_key
->alpha_test_func
)
4789 if (shader_time_index
>= 0)
4790 emit_shader_time_end();
4796 assign_curb_setup();
4799 fixup_3src_null_dest();
4800 allocate_registers();
4806 if (dispatch_width
== 8)
4807 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
4809 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
4811 /* If any state parameters were appended, then ParameterValues could have
4812 * been realloced, in which case the driver uniform storage set up by
4813 * _mesa_associate_uniform_storage() would point to freed memory. Make
4814 * sure that didn't happen.
4816 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
4822 fs_visitor::run_cs()
4824 assert(stage
== MESA_SHADER_COMPUTE
);
4827 sanity_param_count
= prog
->Parameters
->NumParameters
;
4829 assign_common_binding_table_offsets(0);
4833 if (shader_time_index
>= 0)
4834 emit_shader_time_begin();
4841 emit_cs_terminate();
4843 if (shader_time_index
>= 0)
4844 emit_shader_time_end();
4850 assign_curb_setup();
4852 fixup_3src_null_dest();
4853 allocate_registers();
4858 /* If any state parameters were appended, then ParameterValues could have
4859 * been realloced, in which case the driver uniform storage set up by
4860 * _mesa_associate_uniform_storage() would point to freed memory. Make
4861 * sure that didn't happen.
4863 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
4869 brw_wm_fs_emit(struct brw_context
*brw
,
4871 const struct brw_wm_prog_key
*key
,
4872 struct brw_wm_prog_data
*prog_data
,
4873 struct gl_fragment_program
*fp
,
4874 struct gl_shader_program
*prog
,
4875 unsigned *final_assembly_size
)
4877 bool start_busy
= false;
4878 double start_time
= 0;
4880 if (unlikely(brw
->perf_debug
)) {
4881 start_busy
= (brw
->batch
.last_bo
&&
4882 drm_intel_bo_busy(brw
->batch
.last_bo
));
4883 start_time
= get_time();
4886 struct brw_shader
*shader
= NULL
;
4888 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
4890 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
4891 brw_dump_ir("fragment", prog
, &shader
->base
, &fp
->Base
);
4893 int st_index8
= -1, st_index16
= -1;
4894 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
4895 st_index8
= brw_get_shader_time_index(brw
, prog
, &fp
->Base
, ST_FS8
);
4896 st_index16
= brw_get_shader_time_index(brw
, prog
, &fp
->Base
, ST_FS16
);
4899 /* Now the main event: Visit the shader IR and generate our FS IR for it.
4901 fs_visitor
v(brw
->intelScreen
->compiler
, brw
,
4902 mem_ctx
, MESA_SHADER_FRAGMENT
, key
, &prog_data
->base
,
4903 prog
, &fp
->Base
, 8, st_index8
);
4904 if (!v
.run_fs(false /* do_rep_send */)) {
4906 prog
->LinkStatus
= false;
4907 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
4910 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
4916 cfg_t
*simd16_cfg
= NULL
;
4917 fs_visitor
v2(brw
->intelScreen
->compiler
, brw
,
4918 mem_ctx
, MESA_SHADER_FRAGMENT
, key
, &prog_data
->base
,
4919 prog
, &fp
->Base
, 16, st_index16
);
4920 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || brw
->use_rep_send
)) {
4921 if (!v
.simd16_unsupported
) {
4922 /* Try a SIMD16 compile */
4923 v2
.import_uniforms(&v
);
4924 if (!v2
.run_fs(brw
->use_rep_send
)) {
4925 perf_debug("SIMD16 shader failed to compile: %s", v2
.fail_msg
);
4927 simd16_cfg
= v2
.cfg
;
4933 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || brw
->no_simd8
;
4934 if ((no_simd8
|| brw
->gen
< 5) && simd16_cfg
) {
4936 prog_data
->no_8
= true;
4939 prog_data
->no_8
= false;
4942 fs_generator
g(brw
->intelScreen
->compiler
, brw
,
4943 mem_ctx
, (void *) key
, &prog_data
->base
,
4944 &fp
->Base
, v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
4946 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
4949 name
= ralloc_asprintf(mem_ctx
, "%s fragment shader %d",
4950 prog
->Label
? prog
->Label
: "unnamed",
4953 name
= ralloc_asprintf(mem_ctx
, "fragment program %d", fp
->Base
.Id
);
4955 g
.enable_debug(name
);
4959 g
.generate_code(simd8_cfg
, 8);
4961 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
4963 if (unlikely(brw
->perf_debug
) && shader
) {
4964 if (shader
->compiled_once
)
4965 brw_wm_debug_recompile(brw
, prog
, key
);
4966 shader
->compiled_once
= true;
4968 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
4969 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
4970 (get_time() - start_time
) * 1000);
4974 return g
.get_assembly(final_assembly_size
);
4978 brw_fs_precompile(struct gl_context
*ctx
,
4979 struct gl_shader_program
*shader_prog
,
4980 struct gl_program
*prog
)
4982 struct brw_context
*brw
= brw_context(ctx
);
4983 struct brw_wm_prog_key key
;
4985 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*) prog
;
4986 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
4987 bool program_uses_dfdy
= fp
->UsesDFdy
;
4989 memset(&key
, 0, sizeof(key
));
4993 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
4995 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
4996 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
4998 /* Just assume depth testing. */
4999 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
5000 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
5003 if (brw
->gen
< 6 || _mesa_bitcount_64(fp
->Base
.InputsRead
&
5004 BRW_FS_VARYING_INPUT_MASK
) > 16)
5005 key
.input_slots_valid
= fp
->Base
.InputsRead
| VARYING_BIT_POS
;
5007 brw_setup_tex_for_precompile(brw
, &key
.tex
, &fp
->Base
);
5009 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
) {
5010 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
5013 key
.nr_color_regions
= _mesa_bitcount_64(fp
->Base
.OutputsWritten
&
5014 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
5015 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
)));
5017 if ((fp
->Base
.InputsRead
& VARYING_BIT_POS
) || program_uses_dfdy
) {
5018 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
) ||
5019 key
.nr_color_regions
> 1;
5022 key
.program_string_id
= bfp
->id
;
5024 uint32_t old_prog_offset
= brw
->wm
.base
.prog_offset
;
5025 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
5027 bool success
= brw_codegen_wm_prog(brw
, shader_prog
, bfp
, &key
);
5029 brw
->wm
.base
.prog_offset
= old_prog_offset
;
5030 brw
->wm
.prog_data
= old_prog_data
;
5036 brw_setup_tex_for_precompile(struct brw_context
*brw
,
5037 struct brw_sampler_prog_key_data
*tex
,
5038 struct gl_program
*prog
)
5040 const bool has_shader_channel_select
= brw
->is_haswell
|| brw
->gen
>= 8;
5041 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
5042 for (unsigned i
= 0; i
< sampler_count
; i
++) {
5043 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
5044 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
5046 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
5048 /* Color sampler: assume no swizzling. */
5049 tex
->swizzles
[i
] = SWIZZLE_XYZW
;