2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "../glsl/glsl_types.h"
48 #include "../glsl/ir_optimization.h"
49 #include "../glsl/ir_print_visitor.h"
51 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
54 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
56 struct brw_shader
*shader
;
58 shader
= talloc_zero(NULL
, struct brw_shader
);
60 shader
->base
.Type
= type
;
61 shader
->base
.Name
= name
;
62 _mesa_init_shader(ctx
, &shader
->base
);
68 struct gl_shader_program
*
69 brw_new_shader_program(struct gl_context
*ctx
, GLuint name
)
71 struct brw_shader_program
*prog
;
72 prog
= talloc_zero(NULL
, struct brw_shader_program
);
74 prog
->base
.Name
= name
;
75 _mesa_init_shader_program(ctx
, &prog
->base
);
81 brw_compile_shader(struct gl_context
*ctx
, struct gl_shader
*shader
)
83 if (!_mesa_ir_compile_shader(ctx
, shader
))
90 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
92 struct brw_shader
*shader
=
93 (struct brw_shader
*)prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
95 void *mem_ctx
= talloc_new(NULL
);
99 talloc_free(shader
->ir
);
100 shader
->ir
= new(shader
) exec_list
;
101 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
103 do_mat_op_to_vec(shader
->ir
);
104 lower_instructions(shader
->ir
,
110 do_lower_texture_projection(shader
->ir
);
111 brw_do_cubemap_normalize(shader
->ir
);
116 brw_do_channel_expressions(shader
->ir
);
117 brw_do_vector_splitting(shader
->ir
);
119 progress
= do_lower_jumps(shader
->ir
, true, true,
120 true, /* main return */
121 false, /* continue */
125 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
127 progress
= lower_noise(shader
->ir
) || progress
;
129 lower_variable_index_to_cond_assign(shader
->ir
,
131 GL_TRUE
, /* output */
133 GL_TRUE
/* uniform */
135 progress
= lower_quadop_vector(shader
->ir
, false) || progress
;
138 validate_ir_tree(shader
->ir
);
140 reparent_ir(shader
->ir
, shader
->ir
);
141 talloc_free(mem_ctx
);
144 if (!_mesa_ir_link_shader(ctx
, prog
))
151 type_size(const struct glsl_type
*type
)
153 unsigned int size
, i
;
155 switch (type
->base_type
) {
158 case GLSL_TYPE_FLOAT
:
160 return type
->components();
161 case GLSL_TYPE_ARRAY
:
162 return type_size(type
->fields
.array
) * type
->length
;
163 case GLSL_TYPE_STRUCT
:
165 for (i
= 0; i
< type
->length
; i
++) {
166 size
+= type_size(type
->fields
.structure
[i
].type
);
169 case GLSL_TYPE_SAMPLER
:
170 /* Samplers take up no register space, since they're baked in at
175 assert(!"not reached");
181 * Returns how many MRFs an FS opcode will write over.
183 * Note that this is not the 0 or 1 implied writes in an actual gen
184 * instruction -- the FS opcodes often generate MOVs in addition.
187 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
192 switch (inst
->opcode
) {
207 case FS_OPCODE_FB_WRITE
:
209 case FS_OPCODE_PULL_CONSTANT_LOAD
:
210 case FS_OPCODE_UNSPILL
:
212 case FS_OPCODE_SPILL
:
215 assert(!"not reached");
221 fs_visitor::virtual_grf_alloc(int size
)
223 if (virtual_grf_array_size
<= virtual_grf_next
) {
224 if (virtual_grf_array_size
== 0)
225 virtual_grf_array_size
= 16;
227 virtual_grf_array_size
*= 2;
228 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
229 int, virtual_grf_array_size
);
231 /* This slot is always unused. */
232 virtual_grf_sizes
[0] = 0;
234 virtual_grf_sizes
[virtual_grf_next
] = size
;
235 return virtual_grf_next
++;
238 /** Fixed HW reg constructor. */
239 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
243 this->hw_reg
= hw_reg
;
244 this->type
= BRW_REGISTER_TYPE_F
;
247 /** Fixed HW reg constructor. */
248 fs_reg::fs_reg(enum register_file file
, int hw_reg
, uint32_t type
)
252 this->hw_reg
= hw_reg
;
257 brw_type_for_base_type(const struct glsl_type
*type
)
259 switch (type
->base_type
) {
260 case GLSL_TYPE_FLOAT
:
261 return BRW_REGISTER_TYPE_F
;
264 return BRW_REGISTER_TYPE_D
;
266 return BRW_REGISTER_TYPE_UD
;
267 case GLSL_TYPE_ARRAY
:
268 case GLSL_TYPE_STRUCT
:
269 case GLSL_TYPE_SAMPLER
:
270 /* These should be overridden with the type of the member when
271 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
272 * way to trip up if we don't.
274 return BRW_REGISTER_TYPE_UD
;
276 assert(!"not reached");
277 return BRW_REGISTER_TYPE_F
;
281 /** Automatic reg constructor. */
282 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
287 this->reg
= v
->virtual_grf_alloc(type_size(type
));
288 this->reg_offset
= 0;
289 this->type
= brw_type_for_base_type(type
);
293 fs_visitor::variable_storage(ir_variable
*var
)
295 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
298 /* Our support for uniforms is piggy-backed on the struct
299 * gl_fragment_program, because that's where the values actually
300 * get stored, rather than in some global gl_shader_program uniform
304 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
306 unsigned int offset
= 0;
309 if (type
->is_matrix()) {
310 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
311 type
->vector_elements
,
314 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
315 offset
+= setup_uniform_values(loc
+ offset
, column
);
321 switch (type
->base_type
) {
322 case GLSL_TYPE_FLOAT
:
326 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
327 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
328 unsigned int param
= c
->prog_data
.nr_params
++;
330 assert(param
< ARRAY_SIZE(c
->prog_data
.param
));
332 switch (type
->base_type
) {
333 case GLSL_TYPE_FLOAT
:
334 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
337 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2U
;
340 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2I
;
343 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2B
;
346 assert(!"not reached");
347 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
351 c
->prog_data
.param
[param
] = &vec_values
[i
];
355 case GLSL_TYPE_STRUCT
:
356 for (unsigned int i
= 0; i
< type
->length
; i
++) {
357 offset
+= setup_uniform_values(loc
+ offset
,
358 type
->fields
.structure
[i
].type
);
362 case GLSL_TYPE_ARRAY
:
363 for (unsigned int i
= 0; i
< type
->length
; i
++) {
364 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
368 case GLSL_TYPE_SAMPLER
:
369 /* The sampler takes up a slot, but we don't use any values from it. */
373 assert(!"not reached");
379 /* Our support for builtin uniforms is even scarier than non-builtin.
380 * It sits on top of the PROG_STATE_VAR parameters that are
381 * automatically updated from GL context state.
384 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
386 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
388 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
389 statevar
= &_mesa_builtin_uniform_desc
[i
];
390 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
394 if (!statevar
->name
) {
396 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
401 if (ir
->type
->is_array()) {
402 array_count
= ir
->type
->length
;
407 for (int a
= 0; a
< array_count
; a
++) {
408 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
409 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
410 int tokens
[STATE_LENGTH
];
412 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
413 if (ir
->type
->is_array()) {
417 /* This state reference has already been setup by ir_to_mesa,
418 * but we'll get the same index back here.
420 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
421 (gl_state_index
*)tokens
);
422 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
424 /* Add each of the unique swizzles of the element as a
425 * parameter. This'll end up matching the expected layout of
426 * the array/matrix/structure we're trying to fill in.
429 for (unsigned int i
= 0; i
< 4; i
++) {
430 int swiz
= GET_SWZ(element
->swizzle
, i
);
431 if (swiz
== last_swiz
)
435 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
437 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
444 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
446 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
448 fs_reg neg_y
= this->pixel_y
;
450 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
453 if (ir
->pixel_center_integer
) {
454 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
456 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
461 if (!flip
&& ir
->pixel_center_integer
) {
462 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
464 fs_reg pixel_y
= this->pixel_y
;
465 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
468 pixel_y
.negate
= true;
469 offset
+= c
->key
.drawable_height
- 1.0;
472 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
477 if (intel
->gen
>= 6) {
478 emit(fs_inst(BRW_OPCODE_MOV
, wpos
,
479 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
481 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
482 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
486 /* gl_FragCoord.w: Already set up in emit_interpolation */
487 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
493 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
495 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
496 /* Interpolation is always in floating point regs. */
497 reg
->type
= BRW_REGISTER_TYPE_F
;
500 unsigned int array_elements
;
501 const glsl_type
*type
;
503 if (ir
->type
->is_array()) {
504 array_elements
= ir
->type
->length
;
505 if (array_elements
== 0) {
508 type
= ir
->type
->fields
.array
;
514 int location
= ir
->location
;
515 for (unsigned int i
= 0; i
< array_elements
; i
++) {
516 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
517 if (urb_setup
[location
] == -1) {
518 /* If there's no incoming setup data for this slot, don't
519 * emit interpolation for it.
521 attr
.reg_offset
+= type
->vector_elements
;
526 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
527 struct brw_reg interp
= interp_reg(location
, c
);
528 emit(fs_inst(FS_OPCODE_LINTERP
,
536 if (intel
->gen
< 6) {
537 attr
.reg_offset
-= type
->vector_elements
;
538 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
539 emit(fs_inst(BRW_OPCODE_MUL
,
554 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
556 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
558 /* The frontfacing comes in as a bit in the thread payload. */
559 if (intel
->gen
>= 6) {
560 emit(fs_inst(BRW_OPCODE_ASR
,
562 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
564 emit(fs_inst(BRW_OPCODE_NOT
,
567 emit(fs_inst(BRW_OPCODE_AND
,
572 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
573 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
576 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
580 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
581 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
588 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src
)
600 assert(!"not reached: bad math opcode");
604 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
605 * might be able to do better by doing execsize = 1 math and then
606 * expanding that result out, but we would need to be careful with
609 * The hardware ignores source modifiers (negate and abs) on math
610 * instructions, so we also move to a temp to set those up.
612 if (intel
->gen
>= 6 && (src
.file
== UNIFORM
||
615 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
616 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src
));
620 fs_inst
*inst
= emit(fs_inst(opcode
, dst
, src
));
622 if (intel
->gen
< 6) {
631 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
636 assert(opcode
== FS_OPCODE_POW
);
638 if (intel
->gen
>= 6) {
639 /* Can't do hstride == 0 args to gen6 math, so expand it out. */
640 if (src0
.file
== UNIFORM
) {
641 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
642 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src0
));
646 if (src1
.file
== UNIFORM
) {
647 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
648 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src1
));
652 inst
= emit(fs_inst(opcode
, dst
, src0
, src1
));
654 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1), src1
));
655 inst
= emit(fs_inst(opcode
, dst
, src0
, reg_null_f
));
657 inst
->base_mrf
= base_mrf
;
664 fs_visitor::visit(ir_variable
*ir
)
668 if (variable_storage(ir
))
671 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
672 this->frag_color
= ir
;
673 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
674 this->frag_data
= ir
;
675 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
676 this->frag_depth
= ir
;
679 if (ir
->mode
== ir_var_in
) {
680 if (!strcmp(ir
->name
, "gl_FragCoord")) {
681 reg
= emit_fragcoord_interpolation(ir
);
682 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
683 reg
= emit_frontfacing_interpolation(ir
);
685 reg
= emit_general_interpolation(ir
);
688 hash_table_insert(this->variable_ht
, reg
, ir
);
692 if (ir
->mode
== ir_var_uniform
) {
693 int param_index
= c
->prog_data
.nr_params
;
695 if (!strncmp(ir
->name
, "gl_", 3)) {
696 setup_builtin_uniform_values(ir
);
698 setup_uniform_values(ir
->location
, ir
->type
);
701 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
702 reg
->type
= brw_type_for_base_type(ir
->type
);
706 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
708 hash_table_insert(this->variable_ht
, reg
, ir
);
712 fs_visitor::visit(ir_dereference_variable
*ir
)
714 fs_reg
*reg
= variable_storage(ir
->var
);
719 fs_visitor::visit(ir_dereference_record
*ir
)
721 const glsl_type
*struct_type
= ir
->record
->type
;
723 ir
->record
->accept(this);
725 unsigned int offset
= 0;
726 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
727 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
729 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
731 this->result
.reg_offset
+= offset
;
732 this->result
.type
= brw_type_for_base_type(ir
->type
);
736 fs_visitor::visit(ir_dereference_array
*ir
)
741 ir
->array
->accept(this);
742 index
= ir
->array_index
->as_constant();
744 element_size
= type_size(ir
->type
);
745 this->result
.type
= brw_type_for_base_type(ir
->type
);
748 assert(this->result
.file
== UNIFORM
||
749 (this->result
.file
== GRF
&&
750 this->result
.reg
!= 0));
751 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
753 assert(!"FINISHME: non-constant array element");
757 /* Instruction selection: Produce a MOV.sat instead of
758 * MIN(MAX(val, 0), 1) when possible.
761 fs_visitor::try_emit_saturate(ir_expression
*ir
)
763 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
768 sat_val
->accept(this);
769 fs_reg src
= this->result
;
771 this->result
= fs_reg(this, ir
->type
);
772 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, src
));
773 inst
->saturate
= true;
779 fs_visitor::visit(ir_expression
*ir
)
781 unsigned int operand
;
785 assert(ir
->get_num_operands() <= 2);
787 if (try_emit_saturate(ir
))
790 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
791 ir
->operands
[operand
]->accept(this);
792 if (this->result
.file
== BAD_FILE
) {
794 printf("Failed to get tree for expression operand:\n");
795 ir
->operands
[operand
]->accept(&v
);
798 op
[operand
] = this->result
;
800 /* Matrix expression operands should have been broken down to vector
801 * operations already.
803 assert(!ir
->operands
[operand
]->type
->is_matrix());
804 /* And then those vector operands should have been broken down to scalar.
806 assert(!ir
->operands
[operand
]->type
->is_vector());
809 /* Storage for our result. If our result goes into an assignment, it will
810 * just get copy-propagated out, so no worries.
812 this->result
= fs_reg(this, ir
->type
);
814 switch (ir
->operation
) {
815 case ir_unop_logic_not
:
816 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
817 * ones complement of the whole register, not just bit 0.
819 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1)));
822 op
[0].negate
= !op
[0].negate
;
823 this->result
= op
[0];
827 this->result
= op
[0];
830 temp
= fs_reg(this, ir
->type
);
832 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
834 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
835 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
836 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
837 inst
->predicated
= true;
839 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
840 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
841 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
842 inst
->predicated
= true;
846 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
850 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
853 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
857 assert(!"not reached: should be handled by ir_explog_to_explog2");
860 case ir_unop_sin_reduced
:
861 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
864 case ir_unop_cos_reduced
:
865 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
869 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
872 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
876 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
879 assert(!"not reached: should be handled by ir_sub_to_add_neg");
883 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
886 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
889 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
893 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
894 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
895 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
897 case ir_binop_greater
:
898 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
899 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
900 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
902 case ir_binop_lequal
:
903 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
904 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
905 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
907 case ir_binop_gequal
:
908 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
909 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
910 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
913 case ir_binop_all_equal
: /* same as nequal for scalars */
914 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
915 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
916 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
918 case ir_binop_nequal
:
919 case ir_binop_any_nequal
: /* same as nequal for scalars */
920 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
921 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
922 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
925 case ir_binop_logic_xor
:
926 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
929 case ir_binop_logic_or
:
930 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
933 case ir_binop_logic_and
:
934 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
939 assert(!"not reached: should be handled by brw_fs_channel_expressions");
943 assert(!"not reached: should be handled by lower_noise");
946 case ir_quadop_vector
:
947 assert(!"not reached: should be handled by lower_quadop_vector");
951 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
955 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
962 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
966 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
967 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
968 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
,
969 this->result
, fs_reg(1)));
973 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
976 op
[0].negate
= !op
[0].negate
;
977 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
978 this->result
.negate
= true;
981 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
984 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
986 case ir_unop_round_even
:
987 emit(fs_inst(BRW_OPCODE_RNDE
, this->result
, op
[0]));
991 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
992 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
994 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
995 inst
->predicated
= true;
998 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
999 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1001 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1002 inst
->predicated
= true;
1006 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
1009 case ir_unop_bit_not
:
1010 inst
= emit(fs_inst(BRW_OPCODE_NOT
, this->result
, op
[0]));
1012 case ir_binop_bit_and
:
1013 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
1015 case ir_binop_bit_xor
:
1016 inst
= emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
1018 case ir_binop_bit_or
:
1019 inst
= emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
1023 case ir_binop_lshift
:
1024 case ir_binop_rshift
:
1025 assert(!"GLSL 1.30 features unsupported");
1031 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1032 const glsl_type
*type
, bool predicated
)
1034 switch (type
->base_type
) {
1035 case GLSL_TYPE_FLOAT
:
1036 case GLSL_TYPE_UINT
:
1038 case GLSL_TYPE_BOOL
:
1039 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1040 l
.type
= brw_type_for_base_type(type
);
1041 r
.type
= brw_type_for_base_type(type
);
1043 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1044 inst
->predicated
= predicated
;
1050 case GLSL_TYPE_ARRAY
:
1051 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1052 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1056 case GLSL_TYPE_STRUCT
:
1057 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1058 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1063 case GLSL_TYPE_SAMPLER
:
1067 assert(!"not reached");
1073 fs_visitor::visit(ir_assignment
*ir
)
1078 /* FINISHME: arrays on the lhs */
1079 ir
->lhs
->accept(this);
1082 ir
->rhs
->accept(this);
1085 assert(l
.file
!= BAD_FILE
);
1086 assert(r
.file
!= BAD_FILE
);
1088 if (ir
->condition
) {
1089 emit_bool_to_cond_code(ir
->condition
);
1092 if (ir
->lhs
->type
->is_scalar() ||
1093 ir
->lhs
->type
->is_vector()) {
1094 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1095 if (ir
->write_mask
& (1 << i
)) {
1096 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1098 inst
->predicated
= true;
1104 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1109 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1113 bool simd16
= false;
1119 if (ir
->shadow_comparitor
) {
1120 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1121 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1123 coordinate
.reg_offset
++;
1125 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1128 if (ir
->op
== ir_tex
) {
1129 /* There's no plain shadow compare message, so we use shadow
1130 * compare with a bias of 0.0.
1132 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1135 } else if (ir
->op
== ir_txb
) {
1136 ir
->lod_info
.bias
->accept(this);
1137 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1141 assert(ir
->op
== ir_txl
);
1142 ir
->lod_info
.lod
->accept(this);
1143 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1148 ir
->shadow_comparitor
->accept(this);
1149 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1151 } else if (ir
->op
== ir_tex
) {
1152 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1153 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1155 coordinate
.reg_offset
++;
1157 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1160 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1161 * instructions. We'll need to do SIMD16 here.
1163 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1165 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1166 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2),
1168 coordinate
.reg_offset
++;
1171 /* lod/bias appears after u/v/r. */
1174 if (ir
->op
== ir_txb
) {
1175 ir
->lod_info
.bias
->accept(this);
1176 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1180 ir
->lod_info
.lod
->accept(this);
1181 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1186 /* The unused upper half. */
1189 /* Now, since we're doing simd16, the return is 2 interleaved
1190 * vec4s where the odd-indexed ones are junk. We'll need to move
1191 * this weirdness around to the expected layout.
1195 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1197 dst
.type
= BRW_REGISTER_TYPE_F
;
1200 fs_inst
*inst
= NULL
;
1203 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1206 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1209 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1213 assert(!"GLSL 1.30 features unsupported");
1216 inst
->base_mrf
= base_mrf
;
1220 for (int i
= 0; i
< 4; i
++) {
1221 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1222 orig_dst
.reg_offset
++;
1223 dst
.reg_offset
+= 2;
1231 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1233 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1234 * optional parameters like shadow comparitor or LOD bias. If
1235 * optional parameters aren't present, those base slots are
1236 * optional and don't need to be included in the message.
1238 * We don't fill in the unnecessary slots regardless, which may
1239 * look surprising in the disassembly.
1241 int mlen
= 1; /* g0 header always present. */
1244 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1245 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1247 coordinate
.reg_offset
++;
1249 mlen
+= ir
->coordinate
->type
->vector_elements
;
1251 if (ir
->shadow_comparitor
) {
1252 mlen
= MAX2(mlen
, 5);
1254 ir
->shadow_comparitor
->accept(this);
1255 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1259 fs_inst
*inst
= NULL
;
1262 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1265 ir
->lod_info
.bias
->accept(this);
1266 mlen
= MAX2(mlen
, 5);
1267 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1270 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1273 ir
->lod_info
.lod
->accept(this);
1274 mlen
= MAX2(mlen
, 5);
1275 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1278 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1282 assert(!"GLSL 1.30 features unsupported");
1285 inst
->base_mrf
= base_mrf
;
1292 fs_visitor::visit(ir_texture
*ir
)
1295 fs_inst
*inst
= NULL
;
1297 ir
->coordinate
->accept(this);
1298 fs_reg coordinate
= this->result
;
1300 /* Should be lowered by do_lower_texture_projection */
1301 assert(!ir
->projector
);
1303 sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
1304 ctx
->Shader
.CurrentFragmentProgram
,
1305 &brw
->fragment_program
->Base
);
1306 sampler
= c
->fp
->program
.Base
.SamplerUnits
[sampler
];
1308 /* The 965 requires the EU to do the normalization of GL rectangle
1309 * texture coordinates. We use the program parameter state
1310 * tracking to get the scaling factor.
1312 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1313 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1314 int tokens
[STATE_LENGTH
] = {
1316 STATE_TEXRECT_SCALE
,
1322 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
1324 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
+ 1] =
1327 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1328 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1329 GLuint index
= _mesa_add_state_reference(params
,
1330 (gl_state_index
*)tokens
);
1331 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
1333 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[0];
1334 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[1];
1336 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1337 fs_reg src
= coordinate
;
1340 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_x
));
1343 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_y
));
1346 /* Writemasking doesn't eliminate channels on SIMD8 texture
1347 * samples, so don't worry about them.
1349 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1351 if (intel
->gen
< 5) {
1352 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1354 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1357 inst
->sampler
= sampler
;
1361 if (ir
->shadow_comparitor
)
1362 inst
->shadow_compare
= true;
1364 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1365 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1367 for (int i
= 0; i
< 4; i
++) {
1368 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1369 fs_reg l
= swizzle_dst
;
1372 if (swiz
== SWIZZLE_ZERO
) {
1373 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1374 } else if (swiz
== SWIZZLE_ONE
) {
1375 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1378 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1379 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1382 this->result
= swizzle_dst
;
1387 fs_visitor::visit(ir_swizzle
*ir
)
1389 ir
->val
->accept(this);
1390 fs_reg val
= this->result
;
1392 if (ir
->type
->vector_elements
== 1) {
1393 this->result
.reg_offset
+= ir
->mask
.x
;
1397 fs_reg result
= fs_reg(this, ir
->type
);
1398 this->result
= result
;
1400 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1401 fs_reg channel
= val
;
1419 channel
.reg_offset
+= swiz
;
1420 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1421 result
.reg_offset
++;
1426 fs_visitor::visit(ir_discard
*ir
)
1428 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1430 assert(ir
->condition
== NULL
); /* FINISHME */
1432 emit(fs_inst(FS_OPCODE_DISCARD_NOT
, temp
, reg_null_d
));
1433 emit(fs_inst(FS_OPCODE_DISCARD_AND
, reg_null_d
, temp
));
1434 kill_emitted
= true;
1438 fs_visitor::visit(ir_constant
*ir
)
1440 /* Set this->result to reg at the bottom of the function because some code
1441 * paths will cause this visitor to be applied to other fields. This will
1442 * cause the value stored in this->result to be modified.
1444 * Make reg constant so that it doesn't get accidentally modified along the
1445 * way. Yes, I actually had this problem. :(
1447 const fs_reg
reg(this, ir
->type
);
1448 fs_reg dst_reg
= reg
;
1450 if (ir
->type
->is_array()) {
1451 const unsigned size
= type_size(ir
->type
->fields
.array
);
1453 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1454 ir
->array_elements
[i
]->accept(this);
1455 fs_reg src_reg
= this->result
;
1457 dst_reg
.type
= src_reg
.type
;
1458 for (unsigned j
= 0; j
< size
; j
++) {
1459 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, src_reg
));
1460 src_reg
.reg_offset
++;
1461 dst_reg
.reg_offset
++;
1464 } else if (ir
->type
->is_record()) {
1465 foreach_list(node
, &ir
->components
) {
1466 ir_instruction
*const field
= (ir_instruction
*) node
;
1467 const unsigned size
= type_size(field
->type
);
1469 field
->accept(this);
1470 fs_reg src_reg
= this->result
;
1472 dst_reg
.type
= src_reg
.type
;
1473 for (unsigned j
= 0; j
< size
; j
++) {
1474 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, src_reg
));
1475 src_reg
.reg_offset
++;
1476 dst_reg
.reg_offset
++;
1480 const unsigned size
= type_size(ir
->type
);
1482 for (unsigned i
= 0; i
< size
; i
++) {
1483 switch (ir
->type
->base_type
) {
1484 case GLSL_TYPE_FLOAT
:
1485 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.f
[i
])));
1487 case GLSL_TYPE_UINT
:
1488 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.u
[i
])));
1491 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.i
[i
])));
1493 case GLSL_TYPE_BOOL
:
1494 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg((int)ir
->value
.b
[i
])));
1497 assert(!"Non-float/uint/int/bool constant");
1499 dst_reg
.reg_offset
++;
1507 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1509 ir_expression
*expr
= ir
->as_expression();
1515 assert(expr
->get_num_operands() <= 2);
1516 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1517 assert(expr
->operands
[i
]->type
->is_scalar());
1519 expr
->operands
[i
]->accept(this);
1520 op
[i
] = this->result
;
1523 switch (expr
->operation
) {
1524 case ir_unop_logic_not
:
1525 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1)));
1526 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1529 case ir_binop_logic_xor
:
1530 inst
= emit(fs_inst(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]));
1531 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1534 case ir_binop_logic_or
:
1535 inst
= emit(fs_inst(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]));
1536 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1539 case ir_binop_logic_and
:
1540 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]));
1541 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1545 if (intel
->gen
>= 6) {
1546 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1547 op
[0], fs_reg(0.0f
)));
1549 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1551 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1555 if (intel
->gen
>= 6) {
1556 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0)));
1558 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1560 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1563 case ir_binop_greater
:
1564 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1565 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1567 case ir_binop_gequal
:
1568 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1569 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1572 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1573 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1575 case ir_binop_lequal
:
1576 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1577 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1579 case ir_binop_equal
:
1580 case ir_binop_all_equal
:
1581 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1582 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1584 case ir_binop_nequal
:
1585 case ir_binop_any_nequal
:
1586 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1587 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1590 assert(!"not reached");
1599 if (intel
->gen
>= 6) {
1600 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
,
1601 this->result
, fs_reg(1)));
1602 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1604 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, this->result
));
1605 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1610 * Emit a gen6 IF statement with the comparison folded into the IF
1614 fs_visitor::emit_if_gen6(ir_if
*ir
)
1616 ir_expression
*expr
= ir
->condition
->as_expression();
1623 assert(expr
->get_num_operands() <= 2);
1624 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1625 assert(expr
->operands
[i
]->type
->is_scalar());
1627 expr
->operands
[i
]->accept(this);
1628 op
[i
] = this->result
;
1631 switch (expr
->operation
) {
1632 case ir_unop_logic_not
:
1633 inst
= emit(fs_inst(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(0)));
1634 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1637 case ir_binop_logic_xor
:
1638 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1639 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1642 case ir_binop_logic_or
:
1643 temp
= fs_reg(this, glsl_type::bool_type
);
1644 emit(fs_inst(BRW_OPCODE_OR
, temp
, op
[0], op
[1]));
1645 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1646 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1649 case ir_binop_logic_and
:
1650 temp
= fs_reg(this, glsl_type::bool_type
);
1651 emit(fs_inst(BRW_OPCODE_AND
, temp
, op
[0], op
[1]));
1652 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1653 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1657 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0)));
1658 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1662 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1663 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1666 case ir_binop_greater
:
1667 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1668 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1670 case ir_binop_gequal
:
1671 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1672 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1675 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1676 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1678 case ir_binop_lequal
:
1679 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1680 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1682 case ir_binop_equal
:
1683 case ir_binop_all_equal
:
1684 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1685 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1687 case ir_binop_nequal
:
1688 case ir_binop_any_nequal
:
1689 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1690 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1693 assert(!"not reached");
1694 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1695 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1702 ir
->condition
->accept(this);
1704 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0)));
1705 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1709 fs_visitor::visit(ir_if
*ir
)
1713 /* Don't point the annotation at the if statement, because then it plus
1714 * the then and else blocks get printed.
1716 this->base_ir
= ir
->condition
;
1718 if (intel
->gen
>= 6) {
1721 emit_bool_to_cond_code(ir
->condition
);
1723 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1724 inst
->predicated
= true;
1727 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1728 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1734 if (!ir
->else_instructions
.is_empty()) {
1735 emit(fs_inst(BRW_OPCODE_ELSE
));
1737 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1738 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1745 emit(fs_inst(BRW_OPCODE_ENDIF
));
1749 fs_visitor::visit(ir_loop
*ir
)
1751 fs_reg counter
= reg_undef
;
1754 this->base_ir
= ir
->counter
;
1755 ir
->counter
->accept(this);
1756 counter
= *(variable_storage(ir
->counter
));
1759 this->base_ir
= ir
->from
;
1760 ir
->from
->accept(this);
1762 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1766 emit(fs_inst(BRW_OPCODE_DO
));
1769 this->base_ir
= ir
->to
;
1770 ir
->to
->accept(this);
1772 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1773 counter
, this->result
));
1775 case ir_binop_equal
:
1776 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1778 case ir_binop_nequal
:
1779 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1781 case ir_binop_gequal
:
1782 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1784 case ir_binop_lequal
:
1785 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1787 case ir_binop_greater
:
1788 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1791 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1794 assert(!"not reached: unknown loop condition");
1799 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1800 inst
->predicated
= true;
1803 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1804 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1810 if (ir
->increment
) {
1811 this->base_ir
= ir
->increment
;
1812 ir
->increment
->accept(this);
1813 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1816 emit(fs_inst(BRW_OPCODE_WHILE
));
1820 fs_visitor::visit(ir_loop_jump
*ir
)
1823 case ir_loop_jump::jump_break
:
1824 emit(fs_inst(BRW_OPCODE_BREAK
));
1826 case ir_loop_jump::jump_continue
:
1827 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1833 fs_visitor::visit(ir_call
*ir
)
1835 assert(!"FINISHME");
1839 fs_visitor::visit(ir_return
*ir
)
1841 assert(!"FINISHME");
1845 fs_visitor::visit(ir_function
*ir
)
1847 /* Ignore function bodies other than main() -- we shouldn't see calls to
1848 * them since they should all be inlined before we get to ir_to_mesa.
1850 if (strcmp(ir
->name
, "main") == 0) {
1851 const ir_function_signature
*sig
;
1854 sig
= ir
->matching_signature(&empty
);
1858 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1859 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1868 fs_visitor::visit(ir_function_signature
*ir
)
1870 assert(!"not reached");
1875 fs_visitor::emit(fs_inst inst
)
1877 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1880 list_inst
->annotation
= this->current_annotation
;
1881 list_inst
->ir
= this->base_ir
;
1883 this->instructions
.push_tail(list_inst
);
1888 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1890 fs_visitor::emit_dummy_fs()
1892 /* Everyone's favorite color. */
1893 emit(fs_inst(BRW_OPCODE_MOV
,
1896 emit(fs_inst(BRW_OPCODE_MOV
,
1899 emit(fs_inst(BRW_OPCODE_MOV
,
1902 emit(fs_inst(BRW_OPCODE_MOV
,
1907 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1910 write
->base_mrf
= 0;
1913 /* The register location here is relative to the start of the URB
1914 * data. It will get adjusted to be a real location before
1915 * generate_code() time.
1918 fs_visitor::interp_reg(int location
, int channel
)
1920 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1921 int stride
= (channel
& 1) * 4;
1923 assert(urb_setup
[location
] != -1);
1925 return brw_vec1_grf(regnr
, stride
);
1928 /** Emits the interpolation for the varying inputs. */
1930 fs_visitor::emit_interpolation_setup_gen4()
1932 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1934 this->current_annotation
= "compute pixel centers";
1935 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1936 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1937 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1938 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1939 emit(fs_inst(BRW_OPCODE_ADD
,
1941 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1942 fs_reg(brw_imm_v(0x10101010))));
1943 emit(fs_inst(BRW_OPCODE_ADD
,
1945 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1946 fs_reg(brw_imm_v(0x11001100))));
1948 this->current_annotation
= "compute pixel deltas from v0";
1950 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1951 this->delta_y
= this->delta_x
;
1952 this->delta_y
.reg_offset
++;
1954 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1955 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1957 emit(fs_inst(BRW_OPCODE_ADD
,
1960 fs_reg(negate(brw_vec1_grf(1, 0)))));
1961 emit(fs_inst(BRW_OPCODE_ADD
,
1964 fs_reg(negate(brw_vec1_grf(1, 1)))));
1966 this->current_annotation
= "compute pos.w and 1/pos.w";
1967 /* Compute wpos.w. It's always in our setup, since it's needed to
1968 * interpolate the other attributes.
1970 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1971 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1972 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1973 /* Compute the pixel 1/W value from wpos.w. */
1974 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1975 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1976 this->current_annotation
= NULL
;
1979 /** Emits the interpolation for the varying inputs. */
1981 fs_visitor::emit_interpolation_setup_gen6()
1983 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1985 /* If the pixel centers end up used, the setup is the same as for gen4. */
1986 this->current_annotation
= "compute pixel centers";
1987 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1988 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1989 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1990 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1991 emit(fs_inst(BRW_OPCODE_ADD
,
1993 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1994 fs_reg(brw_imm_v(0x10101010))));
1995 emit(fs_inst(BRW_OPCODE_ADD
,
1997 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1998 fs_reg(brw_imm_v(0x11001100))));
2000 /* As of gen6, we can no longer mix float and int sources. We have
2001 * to turn the integer pixel centers into floats for their actual
2004 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
2005 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
2006 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
));
2007 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
));
2009 this->current_annotation
= "compute 1/pos.w";
2010 this->wpos_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
2011 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
2012 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
2014 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
2015 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
2017 this->current_annotation
= NULL
;
2021 fs_visitor::emit_fb_writes()
2023 this->current_annotation
= "FB write header";
2024 GLboolean header_present
= GL_TRUE
;
2027 if (intel
->gen
>= 6 &&
2028 !this->kill_emitted
&&
2029 c
->key
.nr_color_regions
== 1) {
2030 header_present
= false;
2033 if (header_present
) {
2038 if (c
->aa_dest_stencil_reg
) {
2039 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2040 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0))));
2043 /* Reserve space for color. It'll be filled in per MRT below. */
2047 if (c
->source_depth_to_render_target
) {
2048 if (c
->computes_depth
) {
2049 /* Hand over gl_FragDepth. */
2050 assert(this->frag_depth
);
2051 fs_reg depth
= *(variable_storage(this->frag_depth
));
2053 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
2055 /* Pass through the payload depth. */
2056 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2057 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
2061 if (c
->dest_depth_reg
) {
2062 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2063 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0))));
2066 fs_reg color
= reg_undef
;
2067 if (this->frag_color
)
2068 color
= *(variable_storage(this->frag_color
));
2069 else if (this->frag_data
) {
2070 color
= *(variable_storage(this->frag_data
));
2071 color
.type
= BRW_REGISTER_TYPE_F
;
2074 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2075 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
2076 "FB write target %d",
2078 if (this->frag_color
|| this->frag_data
) {
2079 for (int i
= 0; i
< 4; i
++) {
2080 emit(fs_inst(BRW_OPCODE_MOV
,
2081 fs_reg(MRF
, color_mrf
+ i
),
2087 if (this->frag_color
)
2088 color
.reg_offset
-= 4;
2090 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
2091 reg_undef
, reg_undef
));
2092 inst
->target
= target
;
2095 if (target
== c
->key
.nr_color_regions
- 1)
2097 inst
->header_present
= header_present
;
2100 if (c
->key
.nr_color_regions
== 0) {
2101 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
2102 reg_undef
, reg_undef
));
2106 inst
->header_present
= header_present
;
2109 this->current_annotation
= NULL
;
2113 fs_visitor::generate_fb_write(fs_inst
*inst
)
2115 GLboolean eot
= inst
->eot
;
2116 struct brw_reg implied_header
;
2118 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
2121 brw_push_insn_state(p
);
2122 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2123 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2125 if (inst
->header_present
) {
2126 if (intel
->gen
>= 6) {
2128 brw_message_reg(inst
->base_mrf
),
2129 brw_vec8_grf(0, 0));
2131 if (inst
->target
> 0) {
2132 /* Set the render target index for choosing BLEND_STATE. */
2133 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 2),
2134 BRW_REGISTER_TYPE_UD
),
2135 brw_imm_ud(inst
->target
));
2138 /* Clear viewport index, render target array index. */
2139 brw_AND(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 0),
2140 BRW_REGISTER_TYPE_UD
),
2141 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2142 brw_imm_ud(0xf7ff));
2144 implied_header
= brw_null_reg();
2146 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2150 brw_message_reg(inst
->base_mrf
+ 1),
2151 brw_vec8_grf(1, 0));
2153 implied_header
= brw_null_reg();
2156 brw_pop_insn_state(p
);
2159 8, /* dispatch_width */
2160 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
2167 inst
->header_present
);
2171 fs_visitor::generate_linterp(fs_inst
*inst
,
2172 struct brw_reg dst
, struct brw_reg
*src
)
2174 struct brw_reg delta_x
= src
[0];
2175 struct brw_reg delta_y
= src
[1];
2176 struct brw_reg interp
= src
[2];
2179 delta_y
.nr
== delta_x
.nr
+ 1 &&
2180 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2181 brw_PLN(p
, dst
, interp
, delta_x
);
2183 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2184 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2189 fs_visitor::generate_math(fs_inst
*inst
,
2190 struct brw_reg dst
, struct brw_reg
*src
)
2194 switch (inst
->opcode
) {
2196 op
= BRW_MATH_FUNCTION_INV
;
2199 op
= BRW_MATH_FUNCTION_RSQ
;
2201 case FS_OPCODE_SQRT
:
2202 op
= BRW_MATH_FUNCTION_SQRT
;
2204 case FS_OPCODE_EXP2
:
2205 op
= BRW_MATH_FUNCTION_EXP
;
2207 case FS_OPCODE_LOG2
:
2208 op
= BRW_MATH_FUNCTION_LOG
;
2211 op
= BRW_MATH_FUNCTION_POW
;
2214 op
= BRW_MATH_FUNCTION_SIN
;
2217 op
= BRW_MATH_FUNCTION_COS
;
2220 assert(!"not reached: unknown math function");
2225 if (intel
->gen
>= 6) {
2226 assert(inst
->mlen
== 0);
2228 if (inst
->opcode
== FS_OPCODE_POW
) {
2229 brw_math2(p
, dst
, op
, src
[0], src
[1]);
2233 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2234 BRW_MATH_SATURATE_NONE
,
2236 BRW_MATH_DATA_VECTOR
,
2237 BRW_MATH_PRECISION_FULL
);
2240 assert(inst
->mlen
>= 1);
2244 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2245 BRW_MATH_SATURATE_NONE
,
2246 inst
->base_mrf
, src
[0],
2247 BRW_MATH_DATA_VECTOR
,
2248 BRW_MATH_PRECISION_FULL
);
2253 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
)
2257 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2259 if (intel
->gen
>= 5) {
2260 switch (inst
->opcode
) {
2262 if (inst
->shadow_compare
) {
2263 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2265 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2269 if (inst
->shadow_compare
) {
2270 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2272 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2277 switch (inst
->opcode
) {
2279 /* Note that G45 and older determines shadow compare and dispatch width
2280 * from message length for most messages.
2282 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2283 if (inst
->shadow_compare
) {
2284 assert(inst
->mlen
== 6);
2286 assert(inst
->mlen
<= 4);
2290 if (inst
->shadow_compare
) {
2291 assert(inst
->mlen
== 6);
2292 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2294 assert(inst
->mlen
== 9);
2295 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2296 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2301 assert(msg_type
!= -1);
2303 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2309 retype(dst
, BRW_REGISTER_TYPE_UW
),
2311 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2312 SURF_INDEX_TEXTURE(inst
->sampler
),
2324 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2327 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2329 * and we're trying to produce:
2332 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2333 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2334 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2335 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2336 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2337 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2338 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2339 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2341 * and add another set of two more subspans if in 16-pixel dispatch mode.
2343 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2344 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2345 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2346 * between each other. We could probably do it like ddx and swizzle the right
2347 * order later, but bail for now and just produce
2348 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2351 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2353 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2354 BRW_REGISTER_TYPE_F
,
2355 BRW_VERTICAL_STRIDE_2
,
2357 BRW_HORIZONTAL_STRIDE_0
,
2358 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2359 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2360 BRW_REGISTER_TYPE_F
,
2361 BRW_VERTICAL_STRIDE_2
,
2363 BRW_HORIZONTAL_STRIDE_0
,
2364 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2365 brw_ADD(p
, dst
, src0
, negate(src1
));
2369 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2371 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2372 BRW_REGISTER_TYPE_F
,
2373 BRW_VERTICAL_STRIDE_4
,
2375 BRW_HORIZONTAL_STRIDE_0
,
2376 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2377 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2378 BRW_REGISTER_TYPE_F
,
2379 BRW_VERTICAL_STRIDE_4
,
2381 BRW_HORIZONTAL_STRIDE_0
,
2382 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2383 brw_ADD(p
, dst
, src0
, negate(src1
));
2387 fs_visitor::generate_discard_not(fs_inst
*inst
, struct brw_reg mask
)
2389 if (intel
->gen
>= 6) {
2390 /* Gen6 no longer has the mask reg for us to just read the
2391 * active channels from. However, cmp updates just the channels
2392 * of the flag reg that are enabled, so we can get at the
2393 * channel enables that way. In this step, make a reg of ones
2396 brw_MOV(p
, mask
, brw_imm_ud(1));
2398 brw_push_insn_state(p
);
2399 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2400 brw_NOT(p
, mask
, brw_mask_reg(1)); /* IMASK */
2401 brw_pop_insn_state(p
);
2406 fs_visitor::generate_discard_and(fs_inst
*inst
, struct brw_reg mask
)
2408 if (intel
->gen
>= 6) {
2409 struct brw_reg f0
= brw_flag_reg();
2410 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
2412 brw_push_insn_state(p
);
2413 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2414 brw_MOV(p
, f0
, brw_imm_uw(0xffff)); /* inactive channels undiscarded */
2415 brw_pop_insn_state(p
);
2417 brw_CMP(p
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
2418 BRW_CONDITIONAL_Z
, mask
, brw_imm_ud(0)); /* active channels fail test */
2419 /* Undo CMP's whacking of predication*/
2420 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2422 brw_push_insn_state(p
);
2423 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2424 brw_AND(p
, g1
, f0
, g1
);
2425 brw_pop_insn_state(p
);
2427 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2429 mask
= brw_uw1_reg(mask
.file
, mask
.nr
, 0);
2431 brw_push_insn_state(p
);
2432 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2433 brw_AND(p
, g0
, mask
, g0
);
2434 brw_pop_insn_state(p
);
2439 fs_visitor::generate_spill(fs_inst
*inst
, struct brw_reg src
)
2441 assert(inst
->mlen
!= 0);
2444 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
2445 retype(src
, BRW_REGISTER_TYPE_UD
));
2446 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
), 1,
2451 fs_visitor::generate_unspill(fs_inst
*inst
, struct brw_reg dst
)
2453 assert(inst
->mlen
!= 0);
2455 /* Clear any post destination dependencies that would be ignored by
2456 * the block read. See the B-Spec for pre-gen5 send instruction.
2458 * This could use a better solution, since texture sampling and
2459 * math reads could potentially run into it as well -- anywhere
2460 * that we have a SEND with a destination that is a register that
2461 * was written but not read within the last N instructions (what's
2462 * N? unsure). This is rare because of dead code elimination, but
2465 if (intel
->gen
== 4 && !intel
->is_g4x
)
2466 brw_MOV(p
, brw_null_reg(), dst
);
2468 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
), 1,
2471 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2472 /* gen4 errata: destination from a send can't be used as a
2473 * destination until it's been read. Just read it so we don't
2476 brw_MOV(p
, brw_null_reg(), dst
);
2482 fs_visitor::generate_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
)
2484 assert(inst
->mlen
!= 0);
2486 /* Clear any post destination dependencies that would be ignored by
2487 * the block read. See the B-Spec for pre-gen5 send instruction.
2489 * This could use a better solution, since texture sampling and
2490 * math reads could potentially run into it as well -- anywhere
2491 * that we have a SEND with a destination that is a register that
2492 * was written but not read within the last N instructions (what's
2493 * N? unsure). This is rare because of dead code elimination, but
2496 if (intel
->gen
== 4 && !intel
->is_g4x
)
2497 brw_MOV(p
, brw_null_reg(), dst
);
2499 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
2500 inst
->offset
, SURF_INDEX_FRAG_CONST_BUFFER
);
2502 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2503 /* gen4 errata: destination from a send can't be used as a
2504 * destination until it's been read. Just read it so we don't
2507 brw_MOV(p
, brw_null_reg(), dst
);
2512 fs_visitor::assign_curb_setup()
2514 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
2515 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2517 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2518 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2519 fs_inst
*inst
= (fs_inst
*)iter
.get();
2521 for (unsigned int i
= 0; i
< 3; i
++) {
2522 if (inst
->src
[i
].file
== UNIFORM
) {
2523 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2524 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2528 inst
->src
[i
].file
= FIXED_HW_REG
;
2529 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
2536 fs_visitor::calculate_urb_setup()
2538 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2543 /* Figure out where each of the incoming setup attributes lands. */
2544 if (intel
->gen
>= 6) {
2545 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2546 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2547 urb_setup
[i
] = urb_next
++;
2551 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2552 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2553 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2556 if (i
>= VERT_RESULT_VAR0
)
2557 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2558 else if (i
<= VERT_RESULT_TEX7
)
2564 urb_setup
[fp_index
] = urb_next
++;
2569 /* Each attribute is 4 setup channels, each of which is half a reg. */
2570 c
->prog_data
.urb_read_length
= urb_next
* 2;
2574 fs_visitor::assign_urb_setup()
2576 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2578 /* Offset all the urb_setup[] index by the actual position of the
2579 * setup regs, now that the location of the constants has been chosen.
2581 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2582 fs_inst
*inst
= (fs_inst
*)iter
.get();
2584 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2587 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2589 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2592 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2596 * Split large virtual GRFs into separate components if we can.
2598 * This is mostly duplicated with what brw_fs_vector_splitting does,
2599 * but that's really conservative because it's afraid of doing
2600 * splitting that doesn't result in real progress after the rest of
2601 * the optimization phases, which would cause infinite looping in
2602 * optimization. We can do it once here, safely. This also has the
2603 * opportunity to split interpolated values, or maybe even uniforms,
2604 * which we don't have at the IR level.
2606 * We want to split, because virtual GRFs are what we register
2607 * allocate and spill (due to contiguousness requirements for some
2608 * instructions), and they're what we naturally generate in the
2609 * codegen process, but most virtual GRFs don't actually need to be
2610 * contiguous sets of GRFs. If we split, we'll end up with reduced
2611 * live intervals and better dead code elimination and coalescing.
2614 fs_visitor::split_virtual_grfs()
2616 int num_vars
= this->virtual_grf_next
;
2617 bool split_grf
[num_vars
];
2618 int new_virtual_grf
[num_vars
];
2620 /* Try to split anything > 0 sized. */
2621 for (int i
= 0; i
< num_vars
; i
++) {
2622 if (this->virtual_grf_sizes
[i
] != 1)
2623 split_grf
[i
] = true;
2625 split_grf
[i
] = false;
2629 /* PLN opcodes rely on the delta_xy being contiguous. */
2630 split_grf
[this->delta_x
.reg
] = false;
2633 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2634 fs_inst
*inst
= (fs_inst
*)iter
.get();
2636 /* Texturing produces 4 contiguous registers, so no splitting. */
2637 if ((inst
->opcode
== FS_OPCODE_TEX
||
2638 inst
->opcode
== FS_OPCODE_TXB
||
2639 inst
->opcode
== FS_OPCODE_TXL
) &&
2640 inst
->dst
.file
== GRF
) {
2641 split_grf
[inst
->dst
.reg
] = false;
2645 /* Allocate new space for split regs. Note that the virtual
2646 * numbers will be contiguous.
2648 for (int i
= 0; i
< num_vars
; i
++) {
2650 new_virtual_grf
[i
] = virtual_grf_alloc(1);
2651 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
2652 int reg
= virtual_grf_alloc(1);
2653 assert(reg
== new_virtual_grf
[i
] + j
- 1);
2656 this->virtual_grf_sizes
[i
] = 1;
2660 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2661 fs_inst
*inst
= (fs_inst
*)iter
.get();
2663 if (inst
->dst
.file
== GRF
&&
2664 split_grf
[inst
->dst
.reg
] &&
2665 inst
->dst
.reg_offset
!= 0) {
2666 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
2667 inst
->dst
.reg_offset
- 1);
2668 inst
->dst
.reg_offset
= 0;
2670 for (int i
= 0; i
< 3; i
++) {
2671 if (inst
->src
[i
].file
== GRF
&&
2672 split_grf
[inst
->src
[i
].reg
] &&
2673 inst
->src
[i
].reg_offset
!= 0) {
2674 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
2675 inst
->src
[i
].reg_offset
- 1);
2676 inst
->src
[i
].reg_offset
= 0;
2683 * Choose accesses from the UNIFORM file to demote to using the pull
2686 * We allow a fragment shader to have more than the specified minimum
2687 * maximum number of fragment shader uniform components (64). If
2688 * there are too many of these, they'd fill up all of register space.
2689 * So, this will push some of them out to the pull constant buffer and
2690 * update the program to load them.
2693 fs_visitor::setup_pull_constants()
2695 /* Only allow 16 registers (128 uniform components) as push constants. */
2696 unsigned int max_uniform_components
= 16 * 8;
2697 if (c
->prog_data
.nr_params
<= max_uniform_components
)
2700 /* Just demote the end of the list. We could probably do better
2701 * here, demoting things that are rarely used in the program first.
2703 int pull_uniform_base
= max_uniform_components
;
2704 int pull_uniform_count
= c
->prog_data
.nr_params
- pull_uniform_base
;
2706 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2707 fs_inst
*inst
= (fs_inst
*)iter
.get();
2709 for (int i
= 0; i
< 3; i
++) {
2710 if (inst
->src
[i
].file
!= UNIFORM
)
2713 int uniform_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2714 if (uniform_nr
< pull_uniform_base
)
2717 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
2718 fs_inst
*pull
= new(mem_ctx
) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
2720 pull
->offset
= ((uniform_nr
- pull_uniform_base
) * 4) & ~15;
2721 pull
->ir
= inst
->ir
;
2722 pull
->annotation
= inst
->annotation
;
2723 pull
->base_mrf
= 14;
2726 inst
->insert_before(pull
);
2728 inst
->src
[i
].file
= GRF
;
2729 inst
->src
[i
].reg
= dst
.reg
;
2730 inst
->src
[i
].reg_offset
= 0;
2731 inst
->src
[i
].smear
= (uniform_nr
- pull_uniform_base
) & 3;
2735 for (int i
= 0; i
< pull_uniform_count
; i
++) {
2736 c
->prog_data
.pull_param
[i
] = c
->prog_data
.param
[pull_uniform_base
+ i
];
2737 c
->prog_data
.pull_param_convert
[i
] =
2738 c
->prog_data
.param_convert
[pull_uniform_base
+ i
];
2740 c
->prog_data
.nr_params
-= pull_uniform_count
;
2741 c
->prog_data
.nr_pull_params
= pull_uniform_count
;
2745 fs_visitor::calculate_live_intervals()
2747 int num_vars
= this->virtual_grf_next
;
2748 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2749 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2752 int bb_header_ip
= 0;
2754 for (int i
= 0; i
< num_vars
; i
++) {
2760 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2761 fs_inst
*inst
= (fs_inst
*)iter
.get();
2763 if (inst
->opcode
== BRW_OPCODE_DO
) {
2764 if (loop_depth
++ == 0)
2766 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2769 if (loop_depth
== 0) {
2770 /* Patches up the use of vars marked for being live across
2773 for (int i
= 0; i
< num_vars
; i
++) {
2774 if (use
[i
] == loop_start
) {
2780 for (unsigned int i
= 0; i
< 3; i
++) {
2781 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2782 int reg
= inst
->src
[i
].reg
;
2784 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2785 def
[reg
] >= bb_header_ip
)) {
2788 def
[reg
] = MIN2(loop_start
, def
[reg
]);
2789 use
[reg
] = loop_start
;
2791 /* Nobody else is going to go smash our start to
2792 * later in the loop now, because def[reg] now
2793 * points before the bb header.
2798 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2799 int reg
= inst
->dst
.reg
;
2801 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2802 !inst
->predicated
)) {
2803 def
[reg
] = MIN2(def
[reg
], ip
);
2805 def
[reg
] = MIN2(def
[reg
], loop_start
);
2812 /* Set the basic block header IP. This is used for determining
2813 * if a complete def of single-register virtual GRF in a loop
2814 * dominates a use in the same basic block. It's a quick way to
2815 * reduce the live interval range of most register used in a
2818 if (inst
->opcode
== BRW_OPCODE_IF
||
2819 inst
->opcode
== BRW_OPCODE_ELSE
||
2820 inst
->opcode
== BRW_OPCODE_ENDIF
||
2821 inst
->opcode
== BRW_OPCODE_DO
||
2822 inst
->opcode
== BRW_OPCODE_WHILE
||
2823 inst
->opcode
== BRW_OPCODE_BREAK
||
2824 inst
->opcode
== BRW_OPCODE_CONTINUE
) {
2829 talloc_free(this->virtual_grf_def
);
2830 talloc_free(this->virtual_grf_use
);
2831 this->virtual_grf_def
= def
;
2832 this->virtual_grf_use
= use
;
2836 * Attempts to move immediate constants into the immediate
2837 * constant slot of following instructions.
2839 * Immediate constants are a bit tricky -- they have to be in the last
2840 * operand slot, you can't do abs/negate on them,
2844 fs_visitor::propagate_constants()
2846 bool progress
= false;
2848 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2849 fs_inst
*inst
= (fs_inst
*)iter
.get();
2851 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2853 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2854 inst
->dst
.type
!= inst
->src
[0].type
)
2857 /* Don't bother with cases where we should have had the
2858 * operation on the constant folded in GLSL already.
2863 /* Found a move of a constant to a GRF. Find anything else using the GRF
2864 * before it's written, and replace it with the constant if we can.
2866 exec_list_iterator scan_iter
= iter
;
2868 for (; scan_iter
.has_next(); scan_iter
.next()) {
2869 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2871 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2872 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2873 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2874 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2878 for (int i
= 2; i
>= 0; i
--) {
2879 if (scan_inst
->src
[i
].file
!= GRF
||
2880 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2881 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2884 /* Don't bother with cases where we should have had the
2885 * operation on the constant folded in GLSL already.
2887 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2890 switch (scan_inst
->opcode
) {
2891 case BRW_OPCODE_MOV
:
2892 scan_inst
->src
[i
] = inst
->src
[0];
2896 case BRW_OPCODE_MUL
:
2897 case BRW_OPCODE_ADD
:
2899 scan_inst
->src
[i
] = inst
->src
[0];
2901 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2902 /* Fit this constant in by commuting the operands */
2903 scan_inst
->src
[0] = scan_inst
->src
[1];
2904 scan_inst
->src
[1] = inst
->src
[0];
2907 case BRW_OPCODE_CMP
:
2908 case BRW_OPCODE_SEL
:
2910 scan_inst
->src
[i
] = inst
->src
[0];
2916 if (scan_inst
->dst
.file
== GRF
&&
2917 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2918 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2919 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2928 * Must be called after calculate_live_intervales() to remove unused
2929 * writes to registers -- register allocation will fail otherwise
2930 * because something deffed but not used won't be considered to
2931 * interfere with other regs.
2934 fs_visitor::dead_code_eliminate()
2936 bool progress
= false;
2939 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2940 fs_inst
*inst
= (fs_inst
*)iter
.get();
2942 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
2954 fs_visitor::register_coalesce()
2956 bool progress
= false;
2958 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2959 fs_inst
*inst
= (fs_inst
*)iter
.get();
2961 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2964 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
2965 inst
->dst
.type
!= inst
->src
[0].type
)
2968 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
2969 * them: check for no writes to either one until the exit of the
2972 bool interfered
= false;
2973 exec_list_iterator scan_iter
= iter
;
2975 for (; scan_iter
.has_next(); scan_iter
.next()) {
2976 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2978 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2979 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2980 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2986 if (scan_inst
->dst
.file
== GRF
) {
2987 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2988 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2989 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2993 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
2994 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
2995 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
3005 /* Update live interval so we don't have to recalculate. */
3006 this->virtual_grf_use
[inst
->src
[0].reg
] = MAX2(virtual_grf_use
[inst
->src
[0].reg
],
3007 virtual_grf_use
[inst
->dst
.reg
]);
3009 /* Rewrite the later usage to point at the source of the move to
3012 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
3014 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
3016 for (int i
= 0; i
< 3; i
++) {
3017 if (scan_inst
->src
[i
].file
== GRF
&&
3018 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
3019 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
3020 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
3021 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
3022 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
3023 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
3024 scan_inst
->src
[i
].smear
= inst
->src
[0].smear
;
3038 fs_visitor::compute_to_mrf()
3040 bool progress
= false;
3043 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3044 fs_inst
*inst
= (fs_inst
*)iter
.get();
3049 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3051 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
3052 inst
->dst
.type
!= inst
->src
[0].type
||
3053 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
3056 /* Can't compute-to-MRF this GRF if someone else was going to
3059 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
3062 /* Found a move of a GRF to a MRF. Let's see if we can go
3063 * rewrite the thing that made this GRF to write into the MRF.
3066 for (scan_inst
= (fs_inst
*)inst
->prev
;
3067 scan_inst
->prev
!= NULL
;
3068 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
3069 if (scan_inst
->dst
.file
== GRF
&&
3070 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
3071 /* Found the last thing to write our reg we want to turn
3072 * into a compute-to-MRF.
3075 if (scan_inst
->opcode
== FS_OPCODE_TEX
) {
3076 /* texturing writes several continuous regs, so we can't
3077 * compute-to-mrf that.
3082 /* If it's predicated, it (probably) didn't populate all
3085 if (scan_inst
->predicated
)
3088 /* SEND instructions can't have MRF as a destination. */
3089 if (scan_inst
->mlen
)
3092 if (intel
->gen
>= 6) {
3093 /* gen6 math instructions must have the destination be
3094 * GRF, so no compute-to-MRF for them.
3096 if (scan_inst
->opcode
== FS_OPCODE_RCP
||
3097 scan_inst
->opcode
== FS_OPCODE_RSQ
||
3098 scan_inst
->opcode
== FS_OPCODE_SQRT
||
3099 scan_inst
->opcode
== FS_OPCODE_EXP2
||
3100 scan_inst
->opcode
== FS_OPCODE_LOG2
||
3101 scan_inst
->opcode
== FS_OPCODE_SIN
||
3102 scan_inst
->opcode
== FS_OPCODE_COS
||
3103 scan_inst
->opcode
== FS_OPCODE_POW
) {
3108 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
3109 /* Found the creator of our MRF's source value. */
3110 scan_inst
->dst
.file
= MRF
;
3111 scan_inst
->dst
.hw_reg
= inst
->dst
.hw_reg
;
3112 scan_inst
->saturate
|= inst
->saturate
;
3119 /* We don't handle flow control here. Most computation of
3120 * values that end up in MRFs are shortly before the MRF
3123 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
3124 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
3125 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
3129 /* You can't read from an MRF, so if someone else reads our
3130 * MRF's source GRF that we wanted to rewrite, that stops us.
3132 bool interfered
= false;
3133 for (int i
= 0; i
< 3; i
++) {
3134 if (scan_inst
->src
[i
].file
== GRF
&&
3135 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
3136 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
3143 if (scan_inst
->dst
.file
== MRF
&&
3144 scan_inst
->dst
.hw_reg
== inst
->dst
.hw_reg
) {
3145 /* Somebody else wrote our MRF here, so we can't can't
3146 * compute-to-MRF before that.
3151 if (scan_inst
->mlen
> 0) {
3152 /* Found a SEND instruction, which means that there are
3153 * live values in MRFs from base_mrf to base_mrf +
3154 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3157 if (inst
->dst
.hw_reg
>= scan_inst
->base_mrf
&&
3158 inst
->dst
.hw_reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
3169 * Walks through basic blocks, locking for repeated MRF writes and
3170 * removing the later ones.
3173 fs_visitor::remove_duplicate_mrf_writes()
3175 fs_inst
*last_mrf_move
[16];
3176 bool progress
= false;
3178 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3180 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3181 fs_inst
*inst
= (fs_inst
*)iter
.get();
3183 switch (inst
->opcode
) {
3185 case BRW_OPCODE_WHILE
:
3187 case BRW_OPCODE_ELSE
:
3188 case BRW_OPCODE_ENDIF
:
3189 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3195 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3196 inst
->dst
.file
== MRF
) {
3197 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.hw_reg
];
3198 if (prev_inst
&& inst
->equals(prev_inst
)) {
3205 /* Clear out the last-write records for MRFs that were overwritten. */
3206 if (inst
->dst
.file
== MRF
) {
3207 last_mrf_move
[inst
->dst
.hw_reg
] = NULL
;
3210 if (inst
->mlen
> 0) {
3211 /* Found a SEND instruction, which will include two of fewer
3212 * implied MRF writes. We could do better here.
3214 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3215 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3219 /* Clear out any MRF move records whose sources got overwritten. */
3220 if (inst
->dst
.file
== GRF
) {
3221 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
3222 if (last_mrf_move
[i
] &&
3223 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
3224 last_mrf_move
[i
] = NULL
;
3229 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3230 inst
->dst
.file
== MRF
&&
3231 inst
->src
[0].file
== GRF
&&
3232 !inst
->predicated
) {
3233 last_mrf_move
[inst
->dst
.hw_reg
] = inst
;
3241 fs_visitor::virtual_grf_interferes(int a
, int b
)
3243 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
3244 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
3246 /* For dead code, just check if the def interferes with the other range. */
3247 if (this->virtual_grf_use
[a
] == -1) {
3248 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
3249 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
3251 if (this->virtual_grf_use
[b
] == -1) {
3252 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
3253 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
3259 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
3261 struct brw_reg brw_reg
;
3263 switch (reg
->file
) {
3267 if (reg
->smear
== -1) {
3268 brw_reg
= brw_vec8_reg(reg
->file
,
3271 brw_reg
= brw_vec1_reg(reg
->file
,
3272 reg
->hw_reg
, reg
->smear
);
3274 brw_reg
= retype(brw_reg
, reg
->type
);
3277 switch (reg
->type
) {
3278 case BRW_REGISTER_TYPE_F
:
3279 brw_reg
= brw_imm_f(reg
->imm
.f
);
3281 case BRW_REGISTER_TYPE_D
:
3282 brw_reg
= brw_imm_d(reg
->imm
.i
);
3284 case BRW_REGISTER_TYPE_UD
:
3285 brw_reg
= brw_imm_ud(reg
->imm
.u
);
3288 assert(!"not reached");
3289 brw_reg
= brw_null_reg();
3294 brw_reg
= reg
->fixed_hw_reg
;
3297 /* Probably unused. */
3298 brw_reg
= brw_null_reg();
3301 assert(!"not reached");
3302 brw_reg
= brw_null_reg();
3305 assert(!"not reached");
3306 brw_reg
= brw_null_reg();
3310 brw_reg
= brw_abs(brw_reg
);
3312 brw_reg
= negate(brw_reg
);
3318 fs_visitor::generate_code()
3320 int last_native_inst
= 0;
3321 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
3322 int if_stack_depth
= 0, loop_stack_depth
= 0;
3323 int if_depth_in_loop
[16];
3324 const char *last_annotation_string
= NULL
;
3325 ir_instruction
*last_annotation_ir
= NULL
;
3327 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3328 printf("Native code for fragment shader %d:\n",
3329 ctx
->Shader
.CurrentFragmentProgram
->Name
);
3332 if_depth_in_loop
[loop_stack_depth
] = 0;
3334 memset(&if_stack
, 0, sizeof(if_stack
));
3335 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3336 fs_inst
*inst
= (fs_inst
*)iter
.get();
3337 struct brw_reg src
[3], dst
;
3339 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3340 if (last_annotation_ir
!= inst
->ir
) {
3341 last_annotation_ir
= inst
->ir
;
3342 if (last_annotation_ir
) {
3344 last_annotation_ir
->print();
3348 if (last_annotation_string
!= inst
->annotation
) {
3349 last_annotation_string
= inst
->annotation
;
3350 if (last_annotation_string
)
3351 printf(" %s\n", last_annotation_string
);
3355 for (unsigned int i
= 0; i
< 3; i
++) {
3356 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
3358 dst
= brw_reg_from_fs_reg(&inst
->dst
);
3360 brw_set_conditionalmod(p
, inst
->conditional_mod
);
3361 brw_set_predicate_control(p
, inst
->predicated
);
3362 brw_set_saturate(p
, inst
->saturate
);
3364 switch (inst
->opcode
) {
3365 case BRW_OPCODE_MOV
:
3366 brw_MOV(p
, dst
, src
[0]);
3368 case BRW_OPCODE_ADD
:
3369 brw_ADD(p
, dst
, src
[0], src
[1]);
3371 case BRW_OPCODE_MUL
:
3372 brw_MUL(p
, dst
, src
[0], src
[1]);
3375 case BRW_OPCODE_FRC
:
3376 brw_FRC(p
, dst
, src
[0]);
3378 case BRW_OPCODE_RNDD
:
3379 brw_RNDD(p
, dst
, src
[0]);
3381 case BRW_OPCODE_RNDE
:
3382 brw_RNDE(p
, dst
, src
[0]);
3384 case BRW_OPCODE_RNDZ
:
3385 brw_RNDZ(p
, dst
, src
[0]);
3388 case BRW_OPCODE_AND
:
3389 brw_AND(p
, dst
, src
[0], src
[1]);
3392 brw_OR(p
, dst
, src
[0], src
[1]);
3394 case BRW_OPCODE_XOR
:
3395 brw_XOR(p
, dst
, src
[0], src
[1]);
3397 case BRW_OPCODE_NOT
:
3398 brw_NOT(p
, dst
, src
[0]);
3400 case BRW_OPCODE_ASR
:
3401 brw_ASR(p
, dst
, src
[0], src
[1]);
3403 case BRW_OPCODE_SHR
:
3404 brw_SHR(p
, dst
, src
[0], src
[1]);
3406 case BRW_OPCODE_SHL
:
3407 brw_SHL(p
, dst
, src
[0], src
[1]);
3410 case BRW_OPCODE_CMP
:
3411 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
3413 case BRW_OPCODE_SEL
:
3414 brw_SEL(p
, dst
, src
[0], src
[1]);
3418 assert(if_stack_depth
< 16);
3419 if (inst
->src
[0].file
!= BAD_FILE
) {
3420 assert(intel
->gen
>= 6);
3421 if_stack
[if_stack_depth
] = brw_IF_gen6(p
, inst
->conditional_mod
, src
[0], src
[1]);
3423 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
3425 if_depth_in_loop
[loop_stack_depth
]++;
3429 case BRW_OPCODE_ELSE
:
3430 if_stack
[if_stack_depth
- 1] =
3431 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
3433 case BRW_OPCODE_ENDIF
:
3435 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
3436 if_depth_in_loop
[loop_stack_depth
]--;
3440 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
3441 if_depth_in_loop
[loop_stack_depth
] = 0;
3444 case BRW_OPCODE_BREAK
:
3445 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
3446 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3448 case BRW_OPCODE_CONTINUE
:
3449 /* FINISHME: We need to write the loop instruction support still. */
3450 if (intel
->gen
>= 6)
3451 brw_CONT_gen6(p
, loop_stack
[loop_stack_depth
- 1]);
3453 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
3454 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3457 case BRW_OPCODE_WHILE
: {
3458 struct brw_instruction
*inst0
, *inst1
;
3461 if (intel
->gen
>= 5)
3464 assert(loop_stack_depth
> 0);
3466 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
3467 if (intel
->gen
< 6) {
3468 /* patch all the BREAK/CONT instructions from last BGNLOOP */
3469 while (inst0
> loop_stack
[loop_stack_depth
]) {
3471 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
3472 inst0
->bits3
.if_else
.jump_count
== 0) {
3473 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
3475 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
3476 inst0
->bits3
.if_else
.jump_count
== 0) {
3477 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
3486 case FS_OPCODE_SQRT
:
3487 case FS_OPCODE_EXP2
:
3488 case FS_OPCODE_LOG2
:
3492 generate_math(inst
, dst
, src
);
3494 case FS_OPCODE_LINTERP
:
3495 generate_linterp(inst
, dst
, src
);
3500 generate_tex(inst
, dst
);
3502 case FS_OPCODE_DISCARD_NOT
:
3503 generate_discard_not(inst
, dst
);
3505 case FS_OPCODE_DISCARD_AND
:
3506 generate_discard_and(inst
, src
[0]);
3509 generate_ddx(inst
, dst
, src
[0]);
3512 generate_ddy(inst
, dst
, src
[0]);
3515 case FS_OPCODE_SPILL
:
3516 generate_spill(inst
, src
[0]);
3519 case FS_OPCODE_UNSPILL
:
3520 generate_unspill(inst
, dst
);
3523 case FS_OPCODE_PULL_CONSTANT_LOAD
:
3524 generate_pull_constant_load(inst
, dst
);
3527 case FS_OPCODE_FB_WRITE
:
3528 generate_fb_write(inst
);
3531 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
3532 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
3533 brw_opcodes
[inst
->opcode
].name
);
3535 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
3540 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3541 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
3543 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3544 ((uint32_t *)&p
->store
[i
])[3],
3545 ((uint32_t *)&p
->store
[i
])[2],
3546 ((uint32_t *)&p
->store
[i
])[1],
3547 ((uint32_t *)&p
->store
[i
])[0]);
3549 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3553 last_native_inst
= p
->nr_insn
;
3558 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
3559 * emit issues, it doesn't get the jump distances into the output,
3560 * which is often something we want to debug. So this is here in
3561 * case you're doing that.
3564 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3565 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3566 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3567 ((uint32_t *)&p
->store
[i
])[3],
3568 ((uint32_t *)&p
->store
[i
])[2],
3569 ((uint32_t *)&p
->store
[i
])[1],
3570 ((uint32_t *)&p
->store
[i
])[0]);
3571 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3578 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
3580 struct intel_context
*intel
= &brw
->intel
;
3581 struct gl_context
*ctx
= &intel
->ctx
;
3582 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentFragmentProgram
;
3587 struct brw_shader
*shader
=
3588 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3592 /* We always use 8-wide mode, at least for now. For one, flow
3593 * control only works in 8-wide. Also, when we're fragment shader
3594 * bound, we're almost always under register pressure as well, so
3595 * 8-wide would save us from the performance cliff of spilling
3598 c
->dispatch_width
= 8;
3600 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3601 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3602 _mesa_print_ir(shader
->ir
, NULL
);
3606 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3608 fs_visitor
v(c
, shader
);
3613 v
.calculate_urb_setup();
3615 v
.emit_interpolation_setup_gen4();
3617 v
.emit_interpolation_setup_gen6();
3619 /* Generate FS IR for main(). (the visitor only descends into
3620 * functions called "main").
3622 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3623 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3630 v
.split_virtual_grfs();
3631 v
.setup_pull_constants();
3633 v
.assign_curb_setup();
3634 v
.assign_urb_setup();
3640 progress
= v
.remove_duplicate_mrf_writes() || progress
;
3642 v
.calculate_live_intervals();
3643 progress
= v
.propagate_constants() || progress
;
3644 progress
= v
.register_coalesce() || progress
;
3645 progress
= v
.compute_to_mrf() || progress
;
3646 progress
= v
.dead_code_eliminate() || progress
;
3650 /* Debug of register spilling: Go spill everything. */
3651 int virtual_grf_count
= v
.virtual_grf_next
;
3652 for (int i
= 1; i
< virtual_grf_count
; i
++) {
3655 v
.calculate_live_intervals();
3659 v
.assign_regs_trivial();
3661 while (!v
.assign_regs()) {
3665 v
.calculate_live_intervals();
3673 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3678 c
->prog_data
.total_grf
= v
.grf_used
;