2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "brw_vec4_gs_visitor.h"
48 #include "brw_dead_control_flow.h"
49 #include "main/uniforms.h"
50 #include "brw_fs_live_variables.h"
51 #include "glsl/nir/glsl_types.h"
52 #include "program/sampler.h"
57 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
58 const fs_reg
*src
, unsigned sources
)
60 memset(this, 0, sizeof(*this));
62 this->src
= new fs_reg
[MAX2(sources
, 3)];
63 for (unsigned i
= 0; i
< sources
; i
++)
64 this->src
[i
] = src
[i
];
66 this->opcode
= opcode
;
68 this->sources
= sources
;
69 this->exec_size
= exec_size
;
71 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
73 assert(this->exec_size
!= 0);
75 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
77 /* This will be the case for almost all instructions. */
84 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
88 this->regs_written
= 0;
92 unreachable("Invalid destination register file");
95 this->writes_accumulator
= false;
100 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
103 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
105 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
108 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
110 init(opcode
, exec_size
, dst
, NULL
, 0);
113 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
116 const fs_reg src
[1] = { src0
};
117 init(opcode
, exec_size
, dst
, src
, 1);
120 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
121 const fs_reg
&src0
, const fs_reg
&src1
)
123 const fs_reg src
[2] = { src0
, src1
};
124 init(opcode
, exec_size
, dst
, src
, 2);
127 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
128 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
130 const fs_reg src
[3] = { src0
, src1
, src2
};
131 init(opcode
, exec_size
, dst
, src
, 3);
134 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
135 const fs_reg src
[], unsigned sources
)
137 init(opcode
, exec_width
, dst
, src
, sources
);
140 fs_inst::fs_inst(const fs_inst
&that
)
142 memcpy(this, &that
, sizeof(that
));
144 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
146 for (unsigned i
= 0; i
< that
.sources
; i
++)
147 this->src
[i
] = that
.src
[i
];
156 fs_inst::resize_sources(uint8_t num_sources
)
158 if (this->sources
!= num_sources
) {
159 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
161 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
162 src
[i
] = this->src
[i
];
166 this->sources
= num_sources
;
171 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
173 const fs_reg
&surf_index
,
174 const fs_reg
&varying_offset
,
175 uint32_t const_offset
)
177 /* We have our constant surface use a pitch of 4 bytes, so our index can
178 * be any component of a vector, and then we load 4 contiguous
179 * components starting from that.
181 * We break down the const_offset to a portion added to the variable
182 * offset and a portion done using reg_offset, which means that if you
183 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
184 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
185 * CSE can later notice that those loads are all the same and eliminate
186 * the redundant ones.
188 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
189 bld
.ADD(vec4_offset
, varying_offset
, fs_reg(const_offset
& ~3));
192 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
193 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
194 * u, v, r) as parameters, or we can just use the SIMD16 message
195 * consisting of (header, u). We choose the second, at the cost of a
196 * longer return length.
202 if (devinfo
->gen
>= 7)
203 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
205 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
207 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
208 fs_reg vec4_result
= fs_reg(VGRF
, alloc
.allocate(regs_written
), dst
.type
);
209 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
210 inst
->regs_written
= regs_written
;
212 if (devinfo
->gen
< 7) {
213 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
214 inst
->header_size
= 1;
215 if (devinfo
->gen
== 4)
218 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
221 bld
.MOV(dst
, offset(vec4_result
, bld
, (const_offset
& 3) * scale
));
225 * A helper for MOV generation for fixing up broken hardware SEND dependency
229 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
231 /* The caller always wants uncompressed to emit the minimal extra
232 * dependencies, and to avoid having to deal with aligning its regs to 2.
234 const fs_builder ubld
= bld
.annotate("send dependency resolve")
237 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
241 fs_inst::equals(fs_inst
*inst
) const
243 return (opcode
== inst
->opcode
&&
244 dst
.equals(inst
->dst
) &&
245 src
[0].equals(inst
->src
[0]) &&
246 src
[1].equals(inst
->src
[1]) &&
247 src
[2].equals(inst
->src
[2]) &&
248 saturate
== inst
->saturate
&&
249 predicate
== inst
->predicate
&&
250 conditional_mod
== inst
->conditional_mod
&&
251 mlen
== inst
->mlen
&&
252 base_mrf
== inst
->base_mrf
&&
253 target
== inst
->target
&&
255 header_size
== inst
->header_size
&&
256 shadow_compare
== inst
->shadow_compare
&&
257 exec_size
== inst
->exec_size
&&
258 offset
== inst
->offset
);
262 fs_inst::overwrites_reg(const fs_reg
®
) const
264 return reg
.in_range(dst
, regs_written
);
268 fs_inst::is_send_from_grf() const
271 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
272 case SHADER_OPCODE_SHADER_TIME_ADD
:
273 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
274 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
275 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
276 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
277 case SHADER_OPCODE_UNTYPED_ATOMIC
:
278 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
279 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
280 case SHADER_OPCODE_TYPED_ATOMIC
:
281 case SHADER_OPCODE_TYPED_SURFACE_READ
:
282 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
283 case SHADER_OPCODE_URB_WRITE_SIMD8
:
284 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
285 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
286 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
287 case SHADER_OPCODE_URB_READ_SIMD8
:
288 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
290 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
291 return src
[1].file
== VGRF
;
292 case FS_OPCODE_FB_WRITE
:
293 return src
[0].file
== VGRF
;
296 return src
[0].file
== VGRF
;
303 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
305 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
308 fs_reg reg
= this->src
[0];
309 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
312 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
315 for (int i
= 0; i
< this->sources
; i
++) {
316 reg
.type
= this->src
[i
].type
;
317 if (!this->src
[i
].equals(reg
))
320 if (i
< this->header_size
) {
323 reg
.reg_offset
+= this->exec_size
/ 8;
331 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
333 if (devinfo
->gen
== 6 && is_math())
336 if (is_send_from_grf())
339 if (!backend_instruction::can_do_source_mods())
346 fs_inst::can_change_types() const
348 return dst
.type
== src
[0].type
&&
349 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
350 (opcode
== BRW_OPCODE_MOV
||
351 (opcode
== BRW_OPCODE_SEL
&&
352 dst
.type
== src
[1].type
&&
353 predicate
!= BRW_PREDICATE_NONE
&&
354 !src
[1].abs
&& !src
[1].negate
));
358 fs_inst::has_side_effects() const
360 return this->eot
|| backend_instruction::has_side_effects();
366 memset(this, 0, sizeof(*this));
370 /** Generic unset register constructor. */
374 this->file
= BAD_FILE
;
377 /** Immediate value constructor. */
378 fs_reg::fs_reg(float f
)
382 this->type
= BRW_REGISTER_TYPE_F
;
387 /** Immediate value constructor. */
388 fs_reg::fs_reg(int32_t i
)
392 this->type
= BRW_REGISTER_TYPE_D
;
397 /** Immediate value constructor. */
398 fs_reg::fs_reg(uint32_t u
)
402 this->type
= BRW_REGISTER_TYPE_UD
;
407 /** Vector float immediate value constructor. */
408 fs_reg::fs_reg(uint8_t vf
[4])
412 this->type
= BRW_REGISTER_TYPE_VF
;
413 memcpy(&this->ud
, vf
, sizeof(unsigned));
416 /** Vector float immediate value constructor. */
417 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
421 this->type
= BRW_REGISTER_TYPE_VF
;
422 this->ud
= (vf0
<< 0) | (vf1
<< 8) | (vf2
<< 16) | (vf3
<< 24);
425 fs_reg::fs_reg(struct brw_reg reg
) :
428 this->reg_offset
= 0;
429 this->subreg_offset
= 0;
430 this->reladdr
= NULL
;
432 if (this->file
== IMM
&&
433 (this->type
!= BRW_REGISTER_TYPE_V
&&
434 this->type
!= BRW_REGISTER_TYPE_UV
&&
435 this->type
!= BRW_REGISTER_TYPE_VF
)) {
441 fs_reg::equals(const fs_reg
&r
) const
443 return (memcmp((brw_reg
*)this, (brw_reg
*)&r
, sizeof(brw_reg
)) == 0 &&
444 reg_offset
== r
.reg_offset
&&
445 subreg_offset
== r
.subreg_offset
&&
446 !reladdr
&& !r
.reladdr
&&
451 fs_reg::set_smear(unsigned subreg
)
453 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
454 subreg_offset
= subreg
* type_sz(type
);
460 fs_reg::is_contiguous() const
466 fs_reg::component_size(unsigned width
) const
468 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
471 return MAX2(width
* stride
, 1) * type_sz(type
);
475 type_size_scalar(const struct glsl_type
*type
)
477 unsigned int size
, i
;
479 switch (type
->base_type
) {
482 case GLSL_TYPE_FLOAT
:
484 return type
->components();
485 case GLSL_TYPE_ARRAY
:
486 return type_size_scalar(type
->fields
.array
) * type
->length
;
487 case GLSL_TYPE_STRUCT
:
489 for (i
= 0; i
< type
->length
; i
++) {
490 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
493 case GLSL_TYPE_SAMPLER
:
494 /* Samplers take up no register space, since they're baked in at
498 case GLSL_TYPE_ATOMIC_UINT
:
500 case GLSL_TYPE_SUBROUTINE
:
502 case GLSL_TYPE_IMAGE
:
503 return BRW_IMAGE_PARAM_SIZE
;
505 case GLSL_TYPE_ERROR
:
506 case GLSL_TYPE_INTERFACE
:
507 case GLSL_TYPE_DOUBLE
:
508 case GLSL_TYPE_FUNCTION
:
509 unreachable("not reached");
516 * Returns the number of scalar components needed to store type, assuming
517 * that vectors are padded out to vec4.
519 * This has the packing rules of type_size_vec4(), but counts components
520 * similar to type_size_scalar().
523 type_size_vec4_times_4(const struct glsl_type
*type
)
525 return 4 * type_size_vec4(type
);
529 * Create a MOV to read the timestamp register.
531 * The caller is responsible for emitting the MOV. The return value is
532 * the destination of the MOV, with extra parameters set.
535 fs_visitor::get_timestamp(const fs_builder
&bld
)
537 assert(devinfo
->gen
>= 7);
539 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
542 BRW_REGISTER_TYPE_UD
));
544 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
546 /* We want to read the 3 fields we care about even if it's not enabled in
549 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
555 fs_visitor::emit_shader_time_begin()
557 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
559 /* We want only the low 32 bits of the timestamp. Since it's running
560 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
561 * which is plenty of time for our purposes. It is identical across the
562 * EUs, but since it's tracking GPU core speed it will increment at a
563 * varying rate as render P-states change.
565 shader_start_time
.set_smear(0);
569 fs_visitor::emit_shader_time_end()
571 /* Insert our code just before the final SEND with EOT. */
572 exec_node
*end
= this->instructions
.get_tail();
573 assert(end
&& ((fs_inst
*) end
)->eot
);
574 const fs_builder ibld
= bld
.annotate("shader time end")
575 .exec_all().at(NULL
, end
);
577 fs_reg shader_end_time
= get_timestamp(ibld
);
579 /* We only use the low 32 bits of the timestamp - see
580 * emit_shader_time_begin()).
582 * We could also check if render P-states have changed (or anything
583 * else that might disrupt timing) by setting smear to 2 and checking if
584 * that field is != 0.
586 shader_end_time
.set_smear(0);
588 /* Check that there weren't any timestamp reset events (assuming these
589 * were the only two timestamp reads that happened).
591 fs_reg reset
= shader_end_time
;
593 set_condmod(BRW_CONDITIONAL_Z
,
594 ibld
.AND(ibld
.null_reg_ud(), reset
, fs_reg(1u)));
595 ibld
.IF(BRW_PREDICATE_NORMAL
);
597 fs_reg start
= shader_start_time
;
599 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
602 const fs_builder cbld
= ibld
.group(1, 0);
603 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
605 /* If there were no instructions between the two timestamp gets, the diff
606 * is 2 cycles. Remove that overhead, so I can forget about that when
607 * trying to determine the time taken for single instructions.
609 cbld
.ADD(diff
, diff
, fs_reg(-2u));
610 SHADER_TIME_ADD(cbld
, 0, diff
);
611 SHADER_TIME_ADD(cbld
, 1, fs_reg(1u));
612 ibld
.emit(BRW_OPCODE_ELSE
);
613 SHADER_TIME_ADD(cbld
, 2, fs_reg(1u));
614 ibld
.emit(BRW_OPCODE_ENDIF
);
618 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
619 int shader_time_subindex
,
622 int index
= shader_time_index
* 3 + shader_time_subindex
;
623 fs_reg offset
= fs_reg(index
* SHADER_TIME_STRIDE
);
626 if (dispatch_width
== 8)
627 payload
= vgrf(glsl_type::uvec2_type
);
629 payload
= vgrf(glsl_type::uint_type
);
631 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
635 fs_visitor::vfail(const char *format
, va_list va
)
644 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
645 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
647 this->fail_msg
= msg
;
650 fprintf(stderr
, "%s", msg
);
655 fs_visitor::fail(const char *format
, ...)
659 va_start(va
, format
);
665 * Mark this program as impossible to compile in SIMD16 mode.
667 * During the SIMD8 compile (which happens first), we can detect and flag
668 * things that are unsupported in SIMD16 mode, so the compiler can skip
669 * the SIMD16 compile altogether.
671 * During a SIMD16 compile (if one happens anyway), this just calls fail().
674 fs_visitor::no16(const char *msg
)
676 if (dispatch_width
== 16) {
679 simd16_unsupported
= true;
681 compiler
->shader_perf_log(log_data
,
682 "SIMD16 shader failed to compile: %s", msg
);
687 * Returns true if the instruction has a flag that means it won't
688 * update an entire destination register.
690 * For example, dead code elimination and live variable analysis want to know
691 * when a write to a variable screens off any preceding values that were in
695 fs_inst::is_partial_write() const
697 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
698 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
699 !this->dst
.is_contiguous());
703 fs_inst::components_read(unsigned i
) const
706 case FS_OPCODE_LINTERP
:
712 case FS_OPCODE_PIXEL_X
:
713 case FS_OPCODE_PIXEL_Y
:
717 case FS_OPCODE_FB_WRITE_LOGICAL
:
718 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
719 /* First/second FB write color. */
721 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
725 case SHADER_OPCODE_TEX_LOGICAL
:
726 case SHADER_OPCODE_TXD_LOGICAL
:
727 case SHADER_OPCODE_TXF_LOGICAL
:
728 case SHADER_OPCODE_TXL_LOGICAL
:
729 case SHADER_OPCODE_TXS_LOGICAL
:
730 case FS_OPCODE_TXB_LOGICAL
:
731 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
732 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
733 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
734 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
735 case SHADER_OPCODE_LOD_LOGICAL
:
736 case SHADER_OPCODE_TG4_LOGICAL
:
737 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
738 assert(src
[8].file
== IMM
&& src
[9].file
== IMM
);
739 /* Texture coordinates. */
742 /* Texture derivatives. */
743 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
745 /* Texture offset. */
749 else if (i
== 5 && opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
754 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
755 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
756 assert(src
[3].file
== IMM
);
757 /* Surface coordinates. */
760 /* Surface operation source (ignored for reads). */
766 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
767 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
768 assert(src
[3].file
== IMM
&&
770 /* Surface coordinates. */
773 /* Surface operation source. */
779 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
780 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
781 assert(src
[3].file
== IMM
&&
783 const unsigned op
= src
[4].ud
;
784 /* Surface coordinates. */
787 /* Surface operation source. */
788 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
790 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
791 op
== BRW_AOP_PREDEC
))
803 fs_inst::regs_read(int arg
) const
806 case FS_OPCODE_FB_WRITE
:
807 case SHADER_OPCODE_URB_WRITE_SIMD8
:
808 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
809 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
810 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
811 case SHADER_OPCODE_URB_READ_SIMD8
:
812 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
813 case SHADER_OPCODE_UNTYPED_ATOMIC
:
814 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
815 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
816 case SHADER_OPCODE_TYPED_ATOMIC
:
817 case SHADER_OPCODE_TYPED_SURFACE_READ
:
818 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
819 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
824 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
825 /* The payload is actually stored in src1 */
830 case FS_OPCODE_LINTERP
:
835 case SHADER_OPCODE_LOAD_PAYLOAD
:
836 if (arg
< this->header_size
)
840 case CS_OPCODE_CS_TERMINATE
:
841 case SHADER_OPCODE_BARRIER
:
845 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
850 switch (src
[arg
].file
) {
860 return DIV_ROUND_UP(components_read(arg
) *
861 src
[arg
].component_size(exec_size
),
864 unreachable("MRF registers are not allowed as sources");
870 fs_inst::reads_flag() const
876 fs_inst::writes_flag() const
878 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
879 opcode
!= BRW_OPCODE_IF
&&
880 opcode
!= BRW_OPCODE_WHILE
)) ||
881 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
885 * Returns how many MRFs an FS opcode will write over.
887 * Note that this is not the 0 or 1 implied writes in an actual gen
888 * instruction -- the FS opcodes often generate MOVs in addition.
891 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
896 if (inst
->base_mrf
== -1)
899 switch (inst
->opcode
) {
900 case SHADER_OPCODE_RCP
:
901 case SHADER_OPCODE_RSQ
:
902 case SHADER_OPCODE_SQRT
:
903 case SHADER_OPCODE_EXP2
:
904 case SHADER_OPCODE_LOG2
:
905 case SHADER_OPCODE_SIN
:
906 case SHADER_OPCODE_COS
:
907 return 1 * dispatch_width
/ 8;
908 case SHADER_OPCODE_POW
:
909 case SHADER_OPCODE_INT_QUOTIENT
:
910 case SHADER_OPCODE_INT_REMAINDER
:
911 return 2 * dispatch_width
/ 8;
912 case SHADER_OPCODE_TEX
:
914 case SHADER_OPCODE_TXD
:
915 case SHADER_OPCODE_TXF
:
916 case SHADER_OPCODE_TXF_CMS
:
917 case SHADER_OPCODE_TXF_CMS_W
:
918 case SHADER_OPCODE_TXF_MCS
:
919 case SHADER_OPCODE_TG4
:
920 case SHADER_OPCODE_TG4_OFFSET
:
921 case SHADER_OPCODE_TXL
:
922 case SHADER_OPCODE_TXS
:
923 case SHADER_OPCODE_LOD
:
924 case SHADER_OPCODE_SAMPLEINFO
:
926 case FS_OPCODE_FB_WRITE
:
928 case FS_OPCODE_GET_BUFFER_SIZE
:
929 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
930 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
932 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
934 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
936 case SHADER_OPCODE_UNTYPED_ATOMIC
:
937 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
938 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
939 case SHADER_OPCODE_TYPED_ATOMIC
:
940 case SHADER_OPCODE_TYPED_SURFACE_READ
:
941 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
942 case SHADER_OPCODE_URB_WRITE_SIMD8
:
943 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
944 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
945 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
946 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
947 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
948 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
949 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
952 unreachable("not reached");
957 fs_visitor::vgrf(const glsl_type
*const type
)
959 int reg_width
= dispatch_width
/ 8;
960 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
961 brw_type_for_base_type(type
));
964 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
969 this->type
= BRW_REGISTER_TYPE_F
;
970 this->stride
= (file
== UNIFORM
? 0 : 1);
973 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
979 this->stride
= (file
== UNIFORM
? 0 : 1);
982 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
983 * This brings in those uniform definitions
986 fs_visitor::import_uniforms(fs_visitor
*v
)
988 this->push_constant_loc
= v
->push_constant_loc
;
989 this->pull_constant_loc
= v
->pull_constant_loc
;
990 this->uniforms
= v
->uniforms
;
991 this->param_size
= v
->param_size
;
995 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
996 bool origin_upper_left
)
998 assert(stage
== MESA_SHADER_FRAGMENT
);
999 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1000 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1002 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
1004 /* gl_FragCoord.x */
1005 if (pixel_center_integer
) {
1006 bld
.MOV(wpos
, this->pixel_x
);
1008 bld
.ADD(wpos
, this->pixel_x
, fs_reg(0.5f
));
1010 wpos
= offset(wpos
, bld
, 1);
1012 /* gl_FragCoord.y */
1013 if (!flip
&& pixel_center_integer
) {
1014 bld
.MOV(wpos
, this->pixel_y
);
1016 fs_reg pixel_y
= this->pixel_y
;
1017 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
1020 pixel_y
.negate
= true;
1021 offset
+= key
->drawable_height
- 1.0f
;
1024 bld
.ADD(wpos
, pixel_y
, fs_reg(offset
));
1026 wpos
= offset(wpos
, bld
, 1);
1028 /* gl_FragCoord.z */
1029 if (devinfo
->gen
>= 6) {
1030 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1032 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1033 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1034 interp_reg(VARYING_SLOT_POS
, 2));
1036 wpos
= offset(wpos
, bld
, 1);
1038 /* gl_FragCoord.w: Already set up in emit_interpolation */
1039 bld
.MOV(wpos
, this->wpos_w
);
1045 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1046 glsl_interp_qualifier interpolation_mode
,
1047 bool is_centroid
, bool is_sample
)
1049 brw_wm_barycentric_interp_mode barycoord_mode
;
1050 if (devinfo
->gen
>= 6) {
1052 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1053 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1055 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1056 } else if (is_sample
) {
1057 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1058 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1060 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1062 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1063 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1065 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1068 /* On Ironlake and below, there is only one interpolation mode.
1069 * Centroid interpolation doesn't mean anything on this hardware --
1070 * there is no multisampling.
1072 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1074 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1075 this->delta_xy
[barycoord_mode
], interp
);
1079 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1080 const glsl_type
*type
,
1081 glsl_interp_qualifier interpolation_mode
,
1082 int location
, bool mod_centroid
,
1085 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1087 assert(stage
== MESA_SHADER_FRAGMENT
);
1088 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1089 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1091 unsigned int array_elements
;
1093 if (type
->is_array()) {
1094 array_elements
= type
->arrays_of_arrays_size();
1095 if (array_elements
== 0) {
1096 fail("dereferenced array '%s' has length 0\n", name
);
1098 type
= type
->without_array();
1103 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1105 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1106 if (key
->flat_shade
&& is_gl_Color
) {
1107 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1109 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1113 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1114 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1115 if (prog_data
->urb_setup
[location
] == -1) {
1116 /* If there's no incoming setup data for this slot, don't
1117 * emit interpolation for it.
1119 attr
= offset(attr
, bld
, type
->vector_elements
);
1124 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1125 /* Constant interpolation (flat shading) case. The SF has
1126 * handed us defined values in only the constant offset
1127 * field of the setup reg.
1129 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1130 struct brw_reg interp
= interp_reg(location
, k
);
1131 interp
= suboffset(interp
, 3);
1132 interp
.type
= attr
.type
;
1133 bld
.emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1134 attr
= offset(attr
, bld
, 1);
1137 /* Smooth/noperspective interpolation case. */
1138 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1139 struct brw_reg interp
= interp_reg(location
, k
);
1140 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1141 /* Get the pixel/sample mask into f0 so that we know
1142 * which pixels are lit. Then, for each channel that is
1143 * unlit, replace the centroid data with non-centroid
1146 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1149 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1151 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1152 inst
->predicate_inverse
= true;
1153 if (devinfo
->has_pln
)
1154 inst
->no_dd_clear
= true;
1156 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1157 mod_centroid
&& !key
->persample_shading
,
1158 mod_sample
|| key
->persample_shading
);
1159 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1160 inst
->predicate_inverse
= false;
1161 if (devinfo
->has_pln
)
1162 inst
->no_dd_check
= true;
1165 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1166 mod_centroid
&& !key
->persample_shading
,
1167 mod_sample
|| key
->persample_shading
);
1169 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1170 bld
.MUL(attr
, attr
, this->pixel_w
);
1172 attr
= offset(attr
, bld
, 1);
1182 fs_visitor::emit_frontfacing_interpolation()
1184 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1186 if (devinfo
->gen
>= 6) {
1187 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1188 * a boolean result from this (~0/true or 0/false).
1190 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1191 * this task in only one instruction:
1192 * - a negation source modifier will flip the bit; and
1193 * - a W -> D type conversion will sign extend the bit into the high
1194 * word of the destination.
1196 * An ASR 15 fills the low word of the destination.
1198 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1201 bld
.ASR(*reg
, g0
, fs_reg(15));
1203 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1204 * a boolean result from this (1/true or 0/false).
1206 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1207 * the negation source modifier to flip it. Unfortunately the SHR
1208 * instruction only operates on UD (or D with an abs source modifier)
1209 * sources without negation.
1211 * Instead, use ASR (which will give ~0/true or 0/false).
1213 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1216 bld
.ASR(*reg
, g1_6
, fs_reg(31));
1223 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1225 assert(stage
== MESA_SHADER_FRAGMENT
);
1226 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1227 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1229 if (key
->compute_pos_offset
) {
1230 /* Convert int_sample_pos to floating point */
1231 bld
.MOV(dst
, int_sample_pos
);
1232 /* Scale to the range [0, 1] */
1233 bld
.MUL(dst
, dst
, fs_reg(1 / 16.0f
));
1236 /* From ARB_sample_shading specification:
1237 * "When rendering to a non-multisample buffer, or if multisample
1238 * rasterization is disabled, gl_SamplePosition will always be
1241 bld
.MOV(dst
, fs_reg(0.5f
));
1246 fs_visitor::emit_samplepos_setup()
1248 assert(devinfo
->gen
>= 6);
1250 const fs_builder abld
= bld
.annotate("compute sample position");
1251 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1253 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1254 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1256 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1257 * mode will be enabled.
1259 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1260 * R31.1:0 Position Offset X/Y for Slot[3:0]
1261 * R31.3:2 Position Offset X/Y for Slot[7:4]
1264 * The X, Y sample positions come in as bytes in thread payload. So, read
1265 * the positions using vstride=16, width=8, hstride=2.
1267 struct brw_reg sample_pos_reg
=
1268 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1269 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1271 if (dispatch_width
== 8) {
1272 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1274 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1275 abld
.half(1).MOV(half(int_sample_x
, 1),
1276 fs_reg(suboffset(sample_pos_reg
, 16)));
1278 /* Compute gl_SamplePosition.x */
1279 compute_sample_position(pos
, int_sample_x
);
1280 pos
= offset(pos
, abld
, 1);
1281 if (dispatch_width
== 8) {
1282 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1284 abld
.half(0).MOV(half(int_sample_y
, 0),
1285 fs_reg(suboffset(sample_pos_reg
, 1)));
1286 abld
.half(1).MOV(half(int_sample_y
, 1),
1287 fs_reg(suboffset(sample_pos_reg
, 17)));
1289 /* Compute gl_SamplePosition.y */
1290 compute_sample_position(pos
, int_sample_y
);
1295 fs_visitor::emit_sampleid_setup()
1297 assert(stage
== MESA_SHADER_FRAGMENT
);
1298 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1299 assert(devinfo
->gen
>= 6);
1301 const fs_builder abld
= bld
.annotate("compute sample id");
1302 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1304 if (key
->compute_sample_id
) {
1305 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1307 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1309 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1310 * 8x multisampling, subspan 0 will represent sample N (where N
1311 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1312 * 7. We can find the value of N by looking at R0.0 bits 7:6
1313 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1314 * (since samples are always delivered in pairs). That is, we
1315 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1316 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1317 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1318 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1319 * populating a temporary variable with the sequence (0, 1, 2, 3),
1320 * and then reading from it using vstride=1, width=4, hstride=0.
1321 * These computations hold good for 4x multisampling as well.
1323 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1324 * the first four slots are sample 0 of subspan 0; the next four
1325 * are sample 1 of subspan 0; the third group is sample 0 of
1326 * subspan 1, and finally sample 1 of subspan 1.
1329 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1330 * accomodate 16x MSAA.
1332 unsigned sspi_mask
= devinfo
->gen
>= 9 ? 0x1c0 : 0xc0;
1334 abld
.exec_all().group(1, 0)
1335 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1337 abld
.exec_all().group(1, 0).SHR(t1
, t1
, fs_reg(5));
1339 /* This works for both SIMD8 and SIMD16 */
1340 abld
.exec_all().group(4, 0)
1341 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1343 /* This special instruction takes care of setting vstride=1,
1344 * width=4, hstride=0 of t2 during an ADD instruction.
1346 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1348 /* As per GL_ARB_sample_shading specification:
1349 * "When rendering to a non-multisample buffer, or if multisample
1350 * rasterization is disabled, gl_SampleID will always be zero."
1352 abld
.MOV(*reg
, fs_reg(0));
1359 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1361 if (!src
.abs
&& !src
.negate
)
1364 fs_reg temp
= bld
.vgrf(src
.type
);
1371 fs_visitor::emit_discard_jump()
1373 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1375 /* For performance, after a discard, jump to the end of the
1376 * shader if all relevant channels have been discarded.
1378 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1379 discard_jump
->flag_subreg
= 1;
1381 discard_jump
->predicate
= (dispatch_width
== 8)
1382 ? BRW_PREDICATE_ALIGN1_ANY8H
1383 : BRW_PREDICATE_ALIGN1_ANY16H
;
1384 discard_jump
->predicate_inverse
= true;
1388 fs_visitor::emit_gs_thread_end()
1390 assert(stage
== MESA_SHADER_GEOMETRY
);
1392 struct brw_gs_prog_data
*gs_prog_data
=
1393 (struct brw_gs_prog_data
*) prog_data
;
1395 if (gs_compile
->control_data_header_size_bits
> 0) {
1396 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1399 const fs_builder abld
= bld
.annotate("thread end");
1402 if (gs_prog_data
->static_vertex_count
!= -1) {
1403 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1404 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1405 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1406 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1407 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1410 /* Delete now dead instructions. */
1411 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1417 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1421 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1422 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1423 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1426 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1427 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1428 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1429 sources
[1] = this->final_gs_vertex_count
;
1430 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1431 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1439 fs_visitor::assign_curb_setup()
1441 if (dispatch_width
== 8) {
1442 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1444 if (stage
== MESA_SHADER_FRAGMENT
) {
1445 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1446 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1447 } else if (stage
== MESA_SHADER_COMPUTE
) {
1448 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1449 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1451 unreachable("Unsupported shader type!");
1455 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1457 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1458 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1459 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1460 if (inst
->src
[i
].file
== UNIFORM
) {
1461 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1463 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1464 constant_nr
= push_constant_loc
[uniform_nr
];
1466 /* Section 5.11 of the OpenGL 4.1 spec says:
1467 * "Out-of-bounds reads return undefined values, which include
1468 * values from other variables of the active program or zero."
1469 * Just return the first push constant.
1474 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1477 brw_reg
.abs
= inst
->src
[i
].abs
;
1478 brw_reg
.negate
= inst
->src
[i
].negate
;
1480 assert(inst
->src
[i
].stride
== 0);
1481 inst
->src
[i
] = byte_offset(
1482 retype(brw_reg
, inst
->src
[i
].type
),
1483 inst
->src
[i
].subreg_offset
);
1488 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1489 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1493 fs_visitor::calculate_urb_setup()
1495 assert(stage
== MESA_SHADER_FRAGMENT
);
1496 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1497 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1499 memset(prog_data
->urb_setup
, -1,
1500 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1503 /* Figure out where each of the incoming setup attributes lands. */
1504 if (devinfo
->gen
>= 6) {
1505 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1506 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1507 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1508 * first 16 varying inputs, so we can put them wherever we want.
1509 * Just put them in order.
1511 * This is useful because it means that (a) inputs not used by the
1512 * fragment shader won't take up valuable register space, and (b) we
1513 * won't have to recompile the fragment shader if it gets paired with
1514 * a different vertex (or geometry) shader.
1516 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1517 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1518 BITFIELD64_BIT(i
)) {
1519 prog_data
->urb_setup
[i
] = urb_next
++;
1523 bool include_vue_header
=
1524 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1526 /* We have enough input varyings that the SF/SBE pipeline stage can't
1527 * arbitrarily rearrange them to suit our whim; we have to put them
1528 * in an order that matches the output of the previous pipeline stage
1529 * (geometry or vertex shader).
1531 struct brw_vue_map prev_stage_vue_map
;
1532 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1533 key
->input_slots_valid
,
1534 nir
->info
.separate_shader
);
1536 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1538 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1539 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1541 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1542 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1543 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1544 BITFIELD64_BIT(varying
))) {
1545 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1548 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1551 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1552 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1553 /* Point size is packed into the header, not as a general attribute */
1554 if (i
== VARYING_SLOT_PSIZ
)
1557 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1558 /* The back color slot is skipped when the front color is
1559 * also written to. In addition, some slots can be
1560 * written in the vertex shader and not read in the
1561 * fragment shader. So the register number must always be
1562 * incremented, mapped or not.
1564 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1565 prog_data
->urb_setup
[i
] = urb_next
;
1571 * It's a FS only attribute, and we did interpolation for this attribute
1572 * in SF thread. So, count it here, too.
1574 * See compile_sf_prog() for more info.
1576 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1577 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1580 prog_data
->num_varying_inputs
= urb_next
;
1584 fs_visitor::assign_urb_setup()
1586 assert(stage
== MESA_SHADER_FRAGMENT
);
1587 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1589 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1591 /* Offset all the urb_setup[] index by the actual position of the
1592 * setup regs, now that the location of the constants has been chosen.
1594 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1595 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1596 assert(inst
->src
[1].file
== FIXED_GRF
);
1597 inst
->src
[1].nr
+= urb_start
;
1600 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1601 assert(inst
->src
[0].file
== FIXED_GRF
);
1602 inst
->src
[0].nr
+= urb_start
;
1606 /* Each attribute is 4 setup channels, each of which is half a reg. */
1607 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1611 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1613 for (int i
= 0; i
< inst
->sources
; i
++) {
1614 if (inst
->src
[i
].file
== ATTR
) {
1615 int grf
= payload
.num_regs
+
1616 prog_data
->curb_read_length
+
1618 inst
->src
[i
].reg_offset
;
1620 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : inst
->exec_size
;
1621 struct brw_reg reg
=
1622 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1623 inst
->src
[i
].subreg_offset
),
1624 inst
->exec_size
* inst
->src
[i
].stride
,
1625 width
, inst
->src
[i
].stride
);
1626 reg
.abs
= inst
->src
[i
].abs
;
1627 reg
.negate
= inst
->src
[i
].negate
;
1635 fs_visitor::assign_vs_urb_setup()
1637 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1639 assert(stage
== MESA_SHADER_VERTEX
);
1640 int count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1641 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1644 /* Each attribute is 4 regs. */
1645 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1647 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1649 /* Rewrite all ATTR file references to the hw grf that they land in. */
1650 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1651 convert_attr_sources_to_hw_regs(inst
);
1656 fs_visitor::assign_gs_urb_setup()
1658 assert(stage
== MESA_SHADER_GEOMETRY
);
1660 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1662 first_non_payload_grf
+=
1663 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1665 const unsigned first_icp_handle
= payload
.num_regs
-
1666 (vue_prog_data
->include_vue_handles
? nir
->info
.gs
.vertices_in
: 0);
1668 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1669 /* Lower URB_READ_SIMD8 opcodes into real messages. */
1670 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8
) {
1671 assert(inst
->src
[0].file
== IMM
);
1672 inst
->src
[0] = retype(brw_vec8_grf(first_icp_handle
+
1674 0), BRW_REGISTER_TYPE_UD
);
1675 /* for now, assume constant - we can do per-slot offsets later */
1676 assert(inst
->src
[1].file
== IMM
);
1677 inst
->offset
= inst
->src
[1].ud
;
1678 inst
->src
[1] = fs_reg();
1680 inst
->base_mrf
= -1;
1683 /* Rewrite all ATTR file references to GRFs. */
1684 convert_attr_sources_to_hw_regs(inst
);
1690 * Split large virtual GRFs into separate components if we can.
1692 * This is mostly duplicated with what brw_fs_vector_splitting does,
1693 * but that's really conservative because it's afraid of doing
1694 * splitting that doesn't result in real progress after the rest of
1695 * the optimization phases, which would cause infinite looping in
1696 * optimization. We can do it once here, safely. This also has the
1697 * opportunity to split interpolated values, or maybe even uniforms,
1698 * which we don't have at the IR level.
1700 * We want to split, because virtual GRFs are what we register
1701 * allocate and spill (due to contiguousness requirements for some
1702 * instructions), and they're what we naturally generate in the
1703 * codegen process, but most virtual GRFs don't actually need to be
1704 * contiguous sets of GRFs. If we split, we'll end up with reduced
1705 * live intervals and better dead code elimination and coalescing.
1708 fs_visitor::split_virtual_grfs()
1710 int num_vars
= this->alloc
.count
;
1712 /* Count the total number of registers */
1714 int vgrf_to_reg
[num_vars
];
1715 for (int i
= 0; i
< num_vars
; i
++) {
1716 vgrf_to_reg
[i
] = reg_count
;
1717 reg_count
+= alloc
.sizes
[i
];
1720 /* An array of "split points". For each register slot, this indicates
1721 * if this slot can be separated from the previous slot. Every time an
1722 * instruction uses multiple elements of a register (as a source or
1723 * destination), we mark the used slots as inseparable. Then we go
1724 * through and split the registers into the smallest pieces we can.
1726 bool split_points
[reg_count
];
1727 memset(split_points
, 0, sizeof(split_points
));
1729 /* Mark all used registers as fully splittable */
1730 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1731 if (inst
->dst
.file
== VGRF
) {
1732 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1733 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1734 split_points
[reg
+ j
] = true;
1737 for (int i
= 0; i
< inst
->sources
; i
++) {
1738 if (inst
->src
[i
].file
== VGRF
) {
1739 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1740 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1741 split_points
[reg
+ j
] = true;
1746 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1747 if (inst
->dst
.file
== VGRF
) {
1748 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1749 for (int j
= 1; j
< inst
->regs_written
; j
++)
1750 split_points
[reg
+ j
] = false;
1752 for (int i
= 0; i
< inst
->sources
; i
++) {
1753 if (inst
->src
[i
].file
== VGRF
) {
1754 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1755 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1756 split_points
[reg
+ j
] = false;
1761 int new_virtual_grf
[reg_count
];
1762 int new_reg_offset
[reg_count
];
1765 for (int i
= 0; i
< num_vars
; i
++) {
1766 /* The first one should always be 0 as a quick sanity check. */
1767 assert(split_points
[reg
] == false);
1770 new_reg_offset
[reg
] = 0;
1775 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1776 /* If this is a split point, reset the offset to 0 and allocate a
1777 * new virtual GRF for the previous offset many registers
1779 if (split_points
[reg
]) {
1780 assert(offset
<= MAX_VGRF_SIZE
);
1781 int grf
= alloc
.allocate(offset
);
1782 for (int k
= reg
- offset
; k
< reg
; k
++)
1783 new_virtual_grf
[k
] = grf
;
1786 new_reg_offset
[reg
] = offset
;
1791 /* The last one gets the original register number */
1792 assert(offset
<= MAX_VGRF_SIZE
);
1793 alloc
.sizes
[i
] = offset
;
1794 for (int k
= reg
- offset
; k
< reg
; k
++)
1795 new_virtual_grf
[k
] = i
;
1797 assert(reg
== reg_count
);
1799 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1800 if (inst
->dst
.file
== VGRF
) {
1801 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1802 inst
->dst
.nr
= new_virtual_grf
[reg
];
1803 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1804 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1806 for (int i
= 0; i
< inst
->sources
; i
++) {
1807 if (inst
->src
[i
].file
== VGRF
) {
1808 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1809 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1810 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1811 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1815 invalidate_live_intervals();
1819 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1821 * During code generation, we create tons of temporary variables, many of
1822 * which get immediately killed and are never used again. Yet, in later
1823 * optimization and analysis passes, such as compute_live_intervals, we need
1824 * to loop over all the virtual GRFs. Compacting them can save a lot of
1828 fs_visitor::compact_virtual_grfs()
1830 bool progress
= false;
1831 int remap_table
[this->alloc
.count
];
1832 memset(remap_table
, -1, sizeof(remap_table
));
1834 /* Mark which virtual GRFs are used. */
1835 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1836 if (inst
->dst
.file
== VGRF
)
1837 remap_table
[inst
->dst
.nr
] = 0;
1839 for (int i
= 0; i
< inst
->sources
; i
++) {
1840 if (inst
->src
[i
].file
== VGRF
)
1841 remap_table
[inst
->src
[i
].nr
] = 0;
1845 /* Compact the GRF arrays. */
1847 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1848 if (remap_table
[i
] == -1) {
1849 /* We just found an unused register. This means that we are
1850 * actually going to compact something.
1854 remap_table
[i
] = new_index
;
1855 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1856 invalidate_live_intervals();
1861 this->alloc
.count
= new_index
;
1863 /* Patch all the instructions to use the newly renumbered registers */
1864 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1865 if (inst
->dst
.file
== VGRF
)
1866 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1868 for (int i
= 0; i
< inst
->sources
; i
++) {
1869 if (inst
->src
[i
].file
== VGRF
)
1870 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1874 /* Patch all the references to delta_xy, since they're used in register
1875 * allocation. If they're unused, switch them to BAD_FILE so we don't
1876 * think some random VGRF is delta_xy.
1878 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1879 if (delta_xy
[i
].file
== VGRF
) {
1880 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1881 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1883 delta_xy
[i
].file
= BAD_FILE
;
1892 * Assign UNIFORM file registers to either push constants or pull constants.
1894 * We allow a fragment shader to have more than the specified minimum
1895 * maximum number of fragment shader uniform components (64). If
1896 * there are too many of these, they'd fill up all of register space.
1897 * So, this will push some of them out to the pull constant buffer and
1898 * update the program to load them. We also use pull constants for all
1899 * indirect constant loads because we don't support indirect accesses in
1903 fs_visitor::assign_constant_locations()
1905 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1906 if (dispatch_width
!= 8)
1909 unsigned int num_pull_constants
= 0;
1911 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1912 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1914 bool is_live
[uniforms
];
1915 memset(is_live
, 0, sizeof(is_live
));
1917 /* First, we walk through the instructions and do two things:
1919 * 1) Figure out which uniforms are live.
1921 * 2) Find all indirect access of uniform arrays and flag them as needing
1922 * to go into the pull constant buffer.
1924 * Note that we don't move constant-indexed accesses to arrays. No
1925 * testing has been done of the performance impact of this choice.
1927 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1928 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1929 if (inst
->src
[i
].file
!= UNIFORM
)
1932 if (inst
->src
[i
].reladdr
) {
1933 int uniform
= inst
->src
[i
].nr
;
1935 /* If this array isn't already present in the pull constant buffer,
1938 if (pull_constant_loc
[uniform
] == -1) {
1939 assert(param_size
[uniform
]);
1940 for (int j
= 0; j
< param_size
[uniform
]; j
++)
1941 pull_constant_loc
[uniform
+ j
] = num_pull_constants
++;
1944 /* Mark the the one accessed uniform as live */
1945 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1946 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1947 is_live
[constant_nr
] = true;
1952 /* Only allow 16 registers (128 uniform components) as push constants.
1954 * Just demote the end of the list. We could probably do better
1955 * here, demoting things that are rarely used in the program first.
1957 * If changing this value, note the limitation about total_regs in
1960 unsigned int max_push_components
= 16 * 8;
1961 unsigned int num_push_constants
= 0;
1963 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1965 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1966 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1967 /* This UNIFORM register is either dead, or has already been demoted
1968 * to a pull const. Mark it as no longer living in the param[] array.
1970 push_constant_loc
[i
] = -1;
1974 if (num_push_constants
< max_push_components
) {
1975 /* Retain as a push constant. Record the location in the params[]
1978 push_constant_loc
[i
] = num_push_constants
++;
1980 /* Demote to a pull constant. */
1981 push_constant_loc
[i
] = -1;
1982 pull_constant_loc
[i
] = num_pull_constants
++;
1986 stage_prog_data
->nr_params
= num_push_constants
;
1987 stage_prog_data
->nr_pull_params
= num_pull_constants
;
1989 /* Up until now, the param[] array has been indexed by reg + reg_offset
1990 * of UNIFORM registers. Move pull constants into pull_param[] and
1991 * condense param[] to only contain the uniforms we chose to push.
1993 * NOTE: Because we are condensing the params[] array, we know that
1994 * push_constant_loc[i] <= i and we can do it in one smooth loop without
1995 * having to make a copy.
1997 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1998 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
2000 if (pull_constant_loc
[i
] != -1) {
2001 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2002 } else if (push_constant_loc
[i
] != -1) {
2003 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2009 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2010 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2013 fs_visitor::demote_pull_constants()
2015 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2016 for (int i
= 0; i
< inst
->sources
; i
++) {
2017 if (inst
->src
[i
].file
!= UNIFORM
)
2021 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2022 if (location
>= uniforms
) /* Out of bounds access */
2025 pull_index
= pull_constant_loc
[location
];
2027 if (pull_index
== -1)
2030 /* Set up the annotation tracking for new generated instructions. */
2031 const fs_builder
ibld(this, block
, inst
);
2032 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2033 fs_reg dst
= vgrf(glsl_type::float_type
);
2035 assert(inst
->src
[i
].stride
== 0);
2037 /* Generate a pull load into dst. */
2038 if (inst
->src
[i
].reladdr
) {
2039 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
2041 *inst
->src
[i
].reladdr
,
2043 inst
->src
[i
].reladdr
= NULL
;
2044 inst
->src
[i
].stride
= 1;
2046 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2047 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
2048 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2049 dst
, fs_reg(index
), offset
);
2050 inst
->src
[i
].set_smear(pull_index
& 3);
2052 brw_mark_surface_used(prog_data
, index
);
2054 /* Rewrite the instruction to use the temporary VGRF. */
2055 inst
->src
[i
].file
= VGRF
;
2056 inst
->src
[i
].nr
= dst
.nr
;
2057 inst
->src
[i
].reg_offset
= 0;
2060 invalidate_live_intervals();
2064 fs_visitor::opt_algebraic()
2066 bool progress
= false;
2068 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2069 switch (inst
->opcode
) {
2070 case BRW_OPCODE_MOV
:
2071 if (inst
->src
[0].file
!= IMM
)
2074 if (inst
->saturate
) {
2075 if (inst
->dst
.type
!= inst
->src
[0].type
)
2076 assert(!"unimplemented: saturate mixed types");
2078 if (brw_saturate_immediate(inst
->dst
.type
, &inst
->src
[0])) {
2079 inst
->saturate
= false;
2085 case BRW_OPCODE_MUL
:
2086 if (inst
->src
[1].file
!= IMM
)
2090 if (inst
->src
[1].is_one()) {
2091 inst
->opcode
= BRW_OPCODE_MOV
;
2092 inst
->src
[1] = reg_undef
;
2098 if (inst
->src
[1].is_negative_one()) {
2099 inst
->opcode
= BRW_OPCODE_MOV
;
2100 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2101 inst
->src
[1] = reg_undef
;
2107 if (inst
->src
[1].is_zero()) {
2108 inst
->opcode
= BRW_OPCODE_MOV
;
2109 inst
->src
[0] = inst
->src
[1];
2110 inst
->src
[1] = reg_undef
;
2115 if (inst
->src
[0].file
== IMM
) {
2116 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2117 inst
->opcode
= BRW_OPCODE_MOV
;
2118 inst
->src
[0].f
*= inst
->src
[1].f
;
2119 inst
->src
[1] = reg_undef
;
2124 case BRW_OPCODE_ADD
:
2125 if (inst
->src
[1].file
!= IMM
)
2129 if (inst
->src
[1].is_zero()) {
2130 inst
->opcode
= BRW_OPCODE_MOV
;
2131 inst
->src
[1] = reg_undef
;
2136 if (inst
->src
[0].file
== IMM
) {
2137 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2138 inst
->opcode
= BRW_OPCODE_MOV
;
2139 inst
->src
[0].f
+= inst
->src
[1].f
;
2140 inst
->src
[1] = reg_undef
;
2146 if (inst
->src
[0].equals(inst
->src
[1])) {
2147 inst
->opcode
= BRW_OPCODE_MOV
;
2148 inst
->src
[1] = reg_undef
;
2153 case BRW_OPCODE_LRP
:
2154 if (inst
->src
[1].equals(inst
->src
[2])) {
2155 inst
->opcode
= BRW_OPCODE_MOV
;
2156 inst
->src
[0] = inst
->src
[1];
2157 inst
->src
[1] = reg_undef
;
2158 inst
->src
[2] = reg_undef
;
2163 case BRW_OPCODE_CMP
:
2164 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2166 inst
->src
[0].negate
&&
2167 inst
->src
[1].is_zero()) {
2168 inst
->src
[0].abs
= false;
2169 inst
->src
[0].negate
= false;
2170 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2175 case BRW_OPCODE_SEL
:
2176 if (inst
->src
[0].equals(inst
->src
[1])) {
2177 inst
->opcode
= BRW_OPCODE_MOV
;
2178 inst
->src
[1] = reg_undef
;
2179 inst
->predicate
= BRW_PREDICATE_NONE
;
2180 inst
->predicate_inverse
= false;
2182 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2183 switch (inst
->conditional_mod
) {
2184 case BRW_CONDITIONAL_LE
:
2185 case BRW_CONDITIONAL_L
:
2186 switch (inst
->src
[1].type
) {
2187 case BRW_REGISTER_TYPE_F
:
2188 if (inst
->src
[1].f
>= 1.0f
) {
2189 inst
->opcode
= BRW_OPCODE_MOV
;
2190 inst
->src
[1] = reg_undef
;
2191 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2199 case BRW_CONDITIONAL_GE
:
2200 case BRW_CONDITIONAL_G
:
2201 switch (inst
->src
[1].type
) {
2202 case BRW_REGISTER_TYPE_F
:
2203 if (inst
->src
[1].f
<= 0.0f
) {
2204 inst
->opcode
= BRW_OPCODE_MOV
;
2205 inst
->src
[1] = reg_undef
;
2206 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2218 case BRW_OPCODE_MAD
:
2219 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2220 inst
->opcode
= BRW_OPCODE_MOV
;
2221 inst
->src
[1] = reg_undef
;
2222 inst
->src
[2] = reg_undef
;
2224 } else if (inst
->src
[0].is_zero()) {
2225 inst
->opcode
= BRW_OPCODE_MUL
;
2226 inst
->src
[0] = inst
->src
[2];
2227 inst
->src
[2] = reg_undef
;
2229 } else if (inst
->src
[1].is_one()) {
2230 inst
->opcode
= BRW_OPCODE_ADD
;
2231 inst
->src
[1] = inst
->src
[2];
2232 inst
->src
[2] = reg_undef
;
2234 } else if (inst
->src
[2].is_one()) {
2235 inst
->opcode
= BRW_OPCODE_ADD
;
2236 inst
->src
[2] = reg_undef
;
2238 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2239 inst
->opcode
= BRW_OPCODE_ADD
;
2240 inst
->src
[1].f
*= inst
->src
[2].f
;
2241 inst
->src
[2] = reg_undef
;
2245 case SHADER_OPCODE_RCP
: {
2246 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2247 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2248 if (inst
->src
[0].equals(prev
->dst
)) {
2249 inst
->opcode
= SHADER_OPCODE_RSQ
;
2250 inst
->src
[0] = prev
->src
[0];
2256 case SHADER_OPCODE_BROADCAST
:
2257 if (is_uniform(inst
->src
[0])) {
2258 inst
->opcode
= BRW_OPCODE_MOV
;
2260 inst
->force_writemask_all
= true;
2262 } else if (inst
->src
[1].file
== IMM
) {
2263 inst
->opcode
= BRW_OPCODE_MOV
;
2264 inst
->src
[0] = component(inst
->src
[0],
2267 inst
->force_writemask_all
= true;
2276 /* Swap if src[0] is immediate. */
2277 if (progress
&& inst
->is_commutative()) {
2278 if (inst
->src
[0].file
== IMM
) {
2279 fs_reg tmp
= inst
->src
[1];
2280 inst
->src
[1] = inst
->src
[0];
2289 * Optimize sample messages that have constant zero values for the trailing
2290 * texture coordinates. We can just reduce the message length for these
2291 * instructions instead of reserving a register for it. Trailing parameters
2292 * that aren't sent default to zero anyway. This will cause the dead code
2293 * eliminator to remove the MOV instruction that would otherwise be emitted to
2294 * set up the zero value.
2297 fs_visitor::opt_zero_samples()
2299 /* Gen4 infers the texturing opcode based on the message length so we can't
2302 if (devinfo
->gen
< 5)
2305 bool progress
= false;
2307 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2308 if (!inst
->is_tex())
2311 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2313 if (load_payload
->is_head_sentinel() ||
2314 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2317 /* We don't want to remove the message header or the first parameter.
2318 * Removing the first parameter is not allowed, see the Haswell PRM
2319 * volume 7, page 149:
2321 * "Parameter 0 is required except for the sampleinfo message, which
2322 * has no parameter 0"
2324 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2325 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2326 (inst
->exec_size
/ 8) +
2327 inst
->header_size
- 1].is_zero()) {
2328 inst
->mlen
-= inst
->exec_size
/ 8;
2334 invalidate_live_intervals();
2340 * Optimize sample messages which are followed by the final RT write.
2342 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2343 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2344 * final texturing results copied to the framebuffer write payload and modify
2345 * them to write to the framebuffer directly.
2348 fs_visitor::opt_sampler_eot()
2350 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2352 if (stage
!= MESA_SHADER_FRAGMENT
)
2355 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2358 /* FINISHME: It should be possible to implement this optimization when there
2359 * are multiple drawbuffers.
2361 if (key
->nr_color_regions
!= 1)
2364 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2365 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2366 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2367 assert(fb_write
->eot
);
2368 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2370 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2372 /* There wasn't one; nothing to do. */
2373 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2376 /* 3D Sampler » Messages » Message Format
2378 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2379 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2381 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2382 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2383 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2384 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2385 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2388 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2389 * It's very likely to be the previous instruction.
2391 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2392 if (load_payload
->is_head_sentinel() ||
2393 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2396 assert(!tex_inst
->eot
); /* We can't get here twice */
2397 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2399 const fs_builder
ibld(this, block
, tex_inst
);
2401 tex_inst
->offset
|= fb_write
->target
<< 24;
2402 tex_inst
->eot
= true;
2403 tex_inst
->dst
= ibld
.null_reg_ud();
2404 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2406 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2407 * to create a new LOAD_PAYLOAD command with the same sources and a space
2408 * saved for the header. Using a new destination register not only makes sure
2409 * we have enough space, but it will make sure the dead code eliminator kills
2410 * the instruction that this will replace.
2412 if (tex_inst
->header_size
!= 0)
2415 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2416 load_payload
->sources
+ 1);
2417 fs_reg
*new_sources
=
2418 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2420 new_sources
[0] = fs_reg();
2421 for (int i
= 0; i
< load_payload
->sources
; i
++)
2422 new_sources
[i
+1] = load_payload
->src
[i
];
2424 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2425 * requires a lot of information about the sources to appropriately figure
2426 * out the number of registers needed to be used. Given this stage in our
2427 * optimization, we may not have the appropriate GRFs required by
2428 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2429 * manually emit the instruction.
2431 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2432 load_payload
->exec_size
,
2435 load_payload
->sources
+ 1);
2437 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2438 new_load_payload
->header_size
= 1;
2440 tex_inst
->header_size
= 1;
2441 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2442 tex_inst
->src
[0] = send_header
;
2448 fs_visitor::opt_register_renaming()
2450 bool progress
= false;
2453 int remap
[alloc
.count
];
2454 memset(remap
, -1, sizeof(int) * alloc
.count
);
2456 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2457 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2459 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2460 inst
->opcode
== BRW_OPCODE_WHILE
) {
2464 /* Rewrite instruction sources. */
2465 for (int i
= 0; i
< inst
->sources
; i
++) {
2466 if (inst
->src
[i
].file
== VGRF
&&
2467 remap
[inst
->src
[i
].nr
] != -1 &&
2468 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2469 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2474 const int dst
= inst
->dst
.nr
;
2477 inst
->dst
.file
== VGRF
&&
2478 alloc
.sizes
[inst
->dst
.nr
] == inst
->exec_size
/ 8 &&
2479 !inst
->is_partial_write()) {
2480 if (remap
[dst
] == -1) {
2483 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2484 inst
->dst
.nr
= remap
[dst
];
2487 } else if (inst
->dst
.file
== VGRF
&&
2489 remap
[dst
] != dst
) {
2490 inst
->dst
.nr
= remap
[dst
];
2496 invalidate_live_intervals();
2498 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2499 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2500 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2509 * Remove redundant or useless discard jumps.
2511 * For example, we can eliminate jumps in the following sequence:
2513 * discard-jump (redundant with the next jump)
2514 * discard-jump (useless; jumps to the next instruction)
2518 fs_visitor::opt_redundant_discard_jumps()
2520 bool progress
= false;
2522 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2524 fs_inst
*placeholder_halt
= NULL
;
2525 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2526 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2527 placeholder_halt
= inst
;
2532 if (!placeholder_halt
)
2535 /* Delete any HALTs immediately before the placeholder halt. */
2536 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2537 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2538 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2539 prev
->remove(last_bblock
);
2544 invalidate_live_intervals();
2550 fs_visitor::compute_to_mrf()
2552 bool progress
= false;
2555 /* No MRFs on Gen >= 7. */
2556 if (devinfo
->gen
>= 7)
2559 calculate_live_intervals();
2561 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2565 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2566 inst
->is_partial_write() ||
2567 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2568 inst
->dst
.type
!= inst
->src
[0].type
||
2569 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2570 !inst
->src
[0].is_contiguous() ||
2571 inst
->src
[0].subreg_offset
)
2574 /* Work out which hardware MRF registers are written by this
2577 int mrf_low
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2579 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2580 mrf_high
= mrf_low
+ 4;
2581 } else if (inst
->exec_size
== 16) {
2582 mrf_high
= mrf_low
+ 1;
2587 /* Can't compute-to-MRF this GRF if someone else was going to
2590 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2593 /* Found a move of a GRF to a MRF. Let's see if we can go
2594 * rewrite the thing that made this GRF to write into the MRF.
2596 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2597 if (scan_inst
->dst
.file
== VGRF
&&
2598 scan_inst
->dst
.nr
== inst
->src
[0].nr
) {
2599 /* Found the last thing to write our reg we want to turn
2600 * into a compute-to-MRF.
2603 /* If this one instruction didn't populate all the
2604 * channels, bail. We might be able to rewrite everything
2605 * that writes that reg, but it would require smarter
2606 * tracking to delay the rewriting until complete success.
2608 if (scan_inst
->is_partial_write())
2611 /* Things returning more than one register would need us to
2612 * understand coalescing out more than one MOV at a time.
2614 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2617 /* SEND instructions can't have MRF as a destination. */
2618 if (scan_inst
->mlen
)
2621 if (devinfo
->gen
== 6) {
2622 /* gen6 math instructions must have the destination be
2623 * GRF, so no compute-to-MRF for them.
2625 if (scan_inst
->is_math()) {
2630 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2631 /* Found the creator of our MRF's source value. */
2632 scan_inst
->dst
.file
= MRF
;
2633 scan_inst
->dst
.nr
= inst
->dst
.nr
;
2634 scan_inst
->saturate
|= inst
->saturate
;
2635 inst
->remove(block
);
2641 /* We don't handle control flow here. Most computation of
2642 * values that end up in MRFs are shortly before the MRF
2645 if (block
->start() == scan_inst
)
2648 /* You can't read from an MRF, so if someone else reads our
2649 * MRF's source GRF that we wanted to rewrite, that stops us.
2651 bool interfered
= false;
2652 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2653 if (scan_inst
->src
[i
].file
== VGRF
&&
2654 scan_inst
->src
[i
].nr
== inst
->src
[0].nr
&&
2655 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2662 if (scan_inst
->dst
.file
== MRF
) {
2663 /* If somebody else writes our MRF here, we can't
2664 * compute-to-MRF before that.
2666 int scan_mrf_low
= scan_inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2669 if (scan_inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2670 scan_mrf_high
= scan_mrf_low
+ 4;
2671 } else if (scan_inst
->exec_size
== 16) {
2672 scan_mrf_high
= scan_mrf_low
+ 1;
2674 scan_mrf_high
= scan_mrf_low
;
2677 if (mrf_low
== scan_mrf_low
||
2678 mrf_low
== scan_mrf_high
||
2679 mrf_high
== scan_mrf_low
||
2680 mrf_high
== scan_mrf_high
) {
2685 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2686 /* Found a SEND instruction, which means that there are
2687 * live values in MRFs from base_mrf to base_mrf +
2688 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2691 if (mrf_low
>= scan_inst
->base_mrf
&&
2692 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2695 if (mrf_high
>= scan_inst
->base_mrf
&&
2696 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2704 invalidate_live_intervals();
2710 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2711 * flow. We could probably do better here with some form of divergence
2715 fs_visitor::eliminate_find_live_channel()
2717 bool progress
= false;
2720 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2721 switch (inst
->opcode
) {
2727 case BRW_OPCODE_ENDIF
:
2728 case BRW_OPCODE_WHILE
:
2732 case FS_OPCODE_DISCARD_JUMP
:
2733 /* This can potentially make control flow non-uniform until the end
2738 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2740 inst
->opcode
= BRW_OPCODE_MOV
;
2741 inst
->src
[0] = fs_reg(0u);
2743 inst
->force_writemask_all
= true;
2757 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2758 * instructions to FS_OPCODE_REP_FB_WRITE.
2761 fs_visitor::emit_repclear_shader()
2763 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2765 int color_mrf
= base_mrf
+ 2;
2768 if (uniforms
== 1) {
2769 mov
= bld
.exec_all().group(4, 0)
2770 .MOV(brw_message_reg(color_mrf
),
2771 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2773 struct brw_reg reg
=
2774 brw_reg(BRW_GENERAL_REGISTER_FILE
,
2775 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2776 BRW_VERTICAL_STRIDE_8
,
2778 BRW_HORIZONTAL_STRIDE_4
, BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2780 mov
= bld
.exec_all().group(4, 0)
2781 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2785 if (key
->nr_color_regions
== 1) {
2786 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2787 write
->saturate
= key
->clamp_fragment_color
;
2788 write
->base_mrf
= color_mrf
;
2790 write
->header_size
= 0;
2793 assume(key
->nr_color_regions
> 0);
2794 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2795 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2796 write
->saturate
= key
->clamp_fragment_color
;
2797 write
->base_mrf
= base_mrf
;
2799 write
->header_size
= 2;
2807 assign_constant_locations();
2808 assign_curb_setup();
2810 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2811 if (uniforms
== 1) {
2812 assert(mov
->src
[0].file
== FIXED_GRF
);
2813 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2818 * Walks through basic blocks, looking for repeated MRF writes and
2819 * removing the later ones.
2822 fs_visitor::remove_duplicate_mrf_writes()
2824 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2825 bool progress
= false;
2827 /* Need to update the MRF tracking for compressed instructions. */
2828 if (dispatch_width
== 16)
2831 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2833 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2834 if (inst
->is_control_flow()) {
2835 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2838 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2839 inst
->dst
.file
== MRF
) {
2840 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2841 if (prev_inst
&& inst
->equals(prev_inst
)) {
2842 inst
->remove(block
);
2848 /* Clear out the last-write records for MRFs that were overwritten. */
2849 if (inst
->dst
.file
== MRF
) {
2850 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2853 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2854 /* Found a SEND instruction, which will include two or fewer
2855 * implied MRF writes. We could do better here.
2857 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2858 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2862 /* Clear out any MRF move records whose sources got overwritten. */
2863 if (inst
->dst
.file
== VGRF
) {
2864 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2865 if (last_mrf_move
[i
] &&
2866 last_mrf_move
[i
]->src
[0].nr
== inst
->dst
.nr
) {
2867 last_mrf_move
[i
] = NULL
;
2872 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2873 inst
->dst
.file
== MRF
&&
2874 inst
->src
[0].file
== VGRF
&&
2875 !inst
->is_partial_write()) {
2876 last_mrf_move
[inst
->dst
.nr
] = inst
;
2881 invalidate_live_intervals();
2887 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2889 /* Clear the flag for registers that actually got read (as expected). */
2890 for (int i
= 0; i
< inst
->sources
; i
++) {
2892 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
2893 grf
= inst
->src
[i
].nr
;
2898 if (grf
>= first_grf
&&
2899 grf
< first_grf
+ grf_len
) {
2900 deps
[grf
- first_grf
] = false;
2901 if (inst
->exec_size
== 16)
2902 deps
[grf
- first_grf
+ 1] = false;
2908 * Implements this workaround for the original 965:
2910 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2911 * check for post destination dependencies on this instruction, software
2912 * must ensure that there is no destination hazard for the case of ‘write
2913 * followed by a posted write’ shown in the following example.
2916 * 2. send r3.xy <rest of send instruction>
2919 * Due to no post-destination dependency check on the ‘send’, the above
2920 * code sequence could have two instructions (1 and 2) in flight at the
2921 * same time that both consider ‘r3’ as the target of their final writes.
2924 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2927 int write_len
= inst
->regs_written
;
2928 int first_write_grf
= inst
->dst
.nr
;
2929 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2930 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2932 memset(needs_dep
, false, sizeof(needs_dep
));
2933 memset(needs_dep
, true, write_len
);
2935 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2937 /* Walk backwards looking for writes to registers we're writing which
2938 * aren't read since being written. If we hit the start of the program,
2939 * we assume that there are no outstanding dependencies on entry to the
2942 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2943 /* If we hit control flow, assume that there *are* outstanding
2944 * dependencies, and force their cleanup before our instruction.
2946 if (block
->start() == scan_inst
) {
2947 for (int i
= 0; i
< write_len
; i
++) {
2949 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
2950 first_write_grf
+ i
);
2955 /* We insert our reads as late as possible on the assumption that any
2956 * instruction but a MOV that might have left us an outstanding
2957 * dependency has more latency than a MOV.
2959 if (scan_inst
->dst
.file
== VGRF
) {
2960 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2961 int reg
= scan_inst
->dst
.nr
+ i
;
2963 if (reg
>= first_write_grf
&&
2964 reg
< first_write_grf
+ write_len
&&
2965 needs_dep
[reg
- first_write_grf
]) {
2966 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
2967 needs_dep
[reg
- first_write_grf
] = false;
2968 if (scan_inst
->exec_size
== 16)
2969 needs_dep
[reg
- first_write_grf
+ 1] = false;
2974 /* Clear the flag for registers that actually got read (as expected). */
2975 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2977 /* Continue the loop only if we haven't resolved all the dependencies */
2979 for (i
= 0; i
< write_len
; i
++) {
2989 * Implements this workaround for the original 965:
2991 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2992 * used as a destination register until after it has been sourced by an
2993 * instruction with a different destination register.
2996 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2998 int write_len
= inst
->regs_written
;
2999 int first_write_grf
= inst
->dst
.nr
;
3000 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3001 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3003 memset(needs_dep
, false, sizeof(needs_dep
));
3004 memset(needs_dep
, true, write_len
);
3005 /* Walk forwards looking for writes to registers we're writing which aren't
3006 * read before being written.
3008 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3009 /* If we hit control flow, force resolve all remaining dependencies. */
3010 if (block
->end() == scan_inst
) {
3011 for (int i
= 0; i
< write_len
; i
++) {
3013 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3014 first_write_grf
+ i
);
3019 /* Clear the flag for registers that actually got read (as expected). */
3020 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3022 /* We insert our reads as late as possible since they're reading the
3023 * result of a SEND, which has massive latency.
3025 if (scan_inst
->dst
.file
== VGRF
&&
3026 scan_inst
->dst
.nr
>= first_write_grf
&&
3027 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3028 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3029 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3031 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3034 /* Continue the loop only if we haven't resolved all the dependencies */
3036 for (i
= 0; i
< write_len
; i
++) {
3046 fs_visitor::insert_gen4_send_dependency_workarounds()
3048 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3051 bool progress
= false;
3053 /* Note that we're done with register allocation, so GRF fs_regs always
3054 * have a .reg_offset of 0.
3057 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3058 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3059 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3060 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3066 invalidate_live_intervals();
3070 * Turns the generic expression-style uniform pull constant load instruction
3071 * into a hardware-specific series of instructions for loading a pull
3074 * The expression style allows the CSE pass before this to optimize out
3075 * repeated loads from the same offset, and gives the pre-register-allocation
3076 * scheduling full flexibility, while the conversion to native instructions
3077 * allows the post-register-allocation scheduler the best information
3080 * Note that execution masking for setting up pull constant loads is special:
3081 * the channels that need to be written are unrelated to the current execution
3082 * mask, since a later instruction will use one of the result channels as a
3083 * source operand for all 8 or 16 of its channels.
3086 fs_visitor::lower_uniform_pull_constant_loads()
3088 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3089 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3092 if (devinfo
->gen
>= 7) {
3093 /* The offset arg before was a vec4-aligned byte offset. We need to
3094 * turn it into a dword offset.
3096 fs_reg const_offset_reg
= inst
->src
[1];
3097 assert(const_offset_reg
.file
== IMM
&&
3098 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3099 const_offset_reg
.ud
/= 4;
3101 fs_reg payload
, offset
;
3102 if (devinfo
->gen
>= 9) {
3103 /* We have to use a message header on Skylake to get SIMD4x2
3104 * mode. Reserve space for the register.
3106 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3107 offset
.reg_offset
++;
3110 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3114 /* This is actually going to be a MOV, but since only the first dword
3115 * is accessed, we have a special opcode to do just that one. Note
3116 * that this needs to be an operation that will be considered a def
3117 * by live variable analysis, or register allocation will explode.
3119 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3120 8, offset
, const_offset_reg
);
3121 setup
->force_writemask_all
= true;
3123 setup
->ir
= inst
->ir
;
3124 setup
->annotation
= inst
->annotation
;
3125 inst
->insert_before(block
, setup
);
3127 /* Similarly, this will only populate the first 4 channels of the
3128 * result register (since we only use smear values from 0-3), but we
3129 * don't tell the optimizer.
3131 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3132 inst
->src
[1] = payload
;
3133 inst
->base_mrf
= -1;
3135 invalidate_live_intervals();
3137 /* Before register allocation, we didn't tell the scheduler about the
3138 * MRF we use. We know it's safe to use this MRF because nothing
3139 * else does except for register spill/unspill, which generates and
3140 * uses its MRF within a single IR instruction.
3142 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3149 fs_visitor::lower_load_payload()
3151 bool progress
= false;
3153 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3154 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3157 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3158 assert(inst
->saturate
== false);
3159 fs_reg dst
= inst
->dst
;
3161 /* Get rid of COMPR4. We'll add it back in if we need it */
3162 if (dst
.file
== MRF
)
3163 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3165 const fs_builder
ibld(this, block
, inst
);
3166 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3168 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3169 if (inst
->src
[i
].file
!= BAD_FILE
) {
3170 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3171 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3172 hbld
.MOV(mov_dst
, mov_src
);
3174 dst
= offset(dst
, hbld
, 1);
3177 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3178 inst
->exec_size
> 8) {
3179 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3180 * a straightforward copy. Instead, the result of the
3181 * LOAD_PAYLOAD is treated as interleaved and the first four
3182 * non-header sources are unpacked as:
3193 * This is used for gen <= 5 fb writes.
3195 assert(inst
->exec_size
== 16);
3196 assert(inst
->header_size
+ 4 <= inst
->sources
);
3197 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3198 if (inst
->src
[i
].file
!= BAD_FILE
) {
3199 if (devinfo
->has_compr4
) {
3200 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3201 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3202 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3204 /* Platform doesn't have COMPR4. We have to fake it */
3205 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3206 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3208 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3215 /* The loop above only ever incremented us through the first set
3216 * of 4 registers. However, thanks to the magic of COMPR4, we
3217 * actually wrote to the first 8 registers, so we need to take
3218 * that into account now.
3222 /* The COMPR4 code took care of the first 4 sources. We'll let
3223 * the regular path handle any remaining sources. Yes, we are
3224 * modifying the instruction but we're about to delete it so
3225 * this really doesn't hurt anything.
3227 inst
->header_size
+= 4;
3230 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3231 if (inst
->src
[i
].file
!= BAD_FILE
)
3232 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3233 dst
= offset(dst
, ibld
, 1);
3236 inst
->remove(block
);
3241 invalidate_live_intervals();
3247 fs_visitor::lower_integer_multiplication()
3249 bool progress
= false;
3251 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3252 const fs_builder
ibld(this, block
, inst
);
3254 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3255 if (inst
->dst
.is_accumulator() ||
3256 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3257 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3260 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3261 * operation directly, but CHV/BXT cannot.
3263 if (devinfo
->gen
>= 8 &&
3264 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3267 if (inst
->src
[1].file
== IMM
&&
3268 inst
->src
[1].ud
< (1 << 16)) {
3269 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3270 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3273 * If multiplying by an immediate value that fits in 16-bits, do a
3274 * single MUL instruction with that value in the proper location.
3276 if (devinfo
->gen
< 7) {
3277 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3279 ibld
.MOV(imm
, inst
->src
[1]);
3280 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3282 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3285 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3286 * do 32-bit integer multiplication in one instruction, but instead
3287 * must do a sequence (which actually calculates a 64-bit result):
3289 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3290 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3291 * mov(8) g2<1>D acc0<8,8,1>D
3293 * But on Gen > 6, the ability to use second accumulator register
3294 * (acc1) for non-float data types was removed, preventing a simple
3295 * implementation in SIMD16. A 16-channel result can be calculated by
3296 * executing the three instructions twice in SIMD8, once with quarter
3297 * control of 1Q for the first eight channels and again with 2Q for
3298 * the second eight channels.
3300 * Which accumulator register is implicitly accessed (by AccWrEnable
3301 * for instance) is determined by the quarter control. Unfortunately
3302 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3303 * implicit accumulator access by an instruction with 2Q will access
3304 * acc1 regardless of whether the data type is usable in acc1.
3306 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3307 * integer data types.
3309 * Since we only want the low 32-bits of the result, we can do two
3310 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3311 * adjust the high result and add them (like the mach is doing):
3313 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3314 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3315 * shl(8) g9<1>D g8<8,8,1>D 16D
3316 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3318 * We avoid the shl instruction by realizing that we only want to add
3319 * the low 16-bits of the "high" result to the high 16-bits of the
3320 * "low" result and using proper regioning on the add:
3322 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3323 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3324 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3326 * Since it does not use the (single) accumulator register, we can
3327 * schedule multi-component multiplications much better.
3330 fs_reg orig_dst
= inst
->dst
;
3331 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3332 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3335 fs_reg low
= inst
->dst
;
3336 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3339 if (devinfo
->gen
>= 7) {
3340 fs_reg src1_0_w
= inst
->src
[1];
3341 fs_reg src1_1_w
= inst
->src
[1];
3343 if (inst
->src
[1].file
== IMM
) {
3344 src1_0_w
.ud
&= 0xffff;
3347 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3348 if (src1_0_w
.stride
!= 0) {
3349 assert(src1_0_w
.stride
== 1);
3350 src1_0_w
.stride
= 2;
3353 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3354 if (src1_1_w
.stride
!= 0) {
3355 assert(src1_1_w
.stride
== 1);
3356 src1_1_w
.stride
= 2;
3358 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3360 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3361 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3363 fs_reg src0_0_w
= inst
->src
[0];
3364 fs_reg src0_1_w
= inst
->src
[0];
3366 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3367 if (src0_0_w
.stride
!= 0) {
3368 assert(src0_0_w
.stride
== 1);
3369 src0_0_w
.stride
= 2;
3372 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3373 if (src0_1_w
.stride
!= 0) {
3374 assert(src0_1_w
.stride
== 1);
3375 src0_1_w
.stride
= 2;
3377 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3379 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3380 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3383 fs_reg dst
= inst
->dst
;
3384 dst
.type
= BRW_REGISTER_TYPE_UW
;
3385 dst
.subreg_offset
= 2;
3388 high
.type
= BRW_REGISTER_TYPE_UW
;
3391 low
.type
= BRW_REGISTER_TYPE_UW
;
3392 low
.subreg_offset
= 2;
3395 ibld
.ADD(dst
, low
, high
);
3397 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3398 set_condmod(inst
->conditional_mod
,
3399 ibld
.MOV(orig_dst
, inst
->dst
));
3403 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3404 /* Should have been lowered to 8-wide. */
3405 assert(inst
->exec_size
<= 8);
3406 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3408 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3409 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3411 if (devinfo
->gen
>= 8) {
3412 /* Until Gen8, integer multiplies read 32-bits from one source,
3413 * and 16-bits from the other, and relying on the MACH instruction
3414 * to generate the high bits of the result.
3416 * On Gen8, the multiply instruction does a full 32x32-bit
3417 * multiply, but in order to do a 64-bit multiply we can simulate
3418 * the previous behavior and then use a MACH instruction.
3420 * FINISHME: Don't use source modifiers on src1.
3422 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3423 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3424 mul
->src
[1].type
= (type_is_signed(mul
->src
[1].type
) ?
3425 BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
3426 mul
->src
[1].stride
*= 2;
3428 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3429 inst
->force_sechalf
) {
3430 /* Among other things the quarter control bits influence which
3431 * accumulator register is used by the hardware for instructions
3432 * that access the accumulator implicitly (e.g. MACH). A
3433 * second-half instruction would normally map to acc1, which
3434 * doesn't exist on Gen7 and up (the hardware does emulate it for
3435 * floating-point instructions *only* by taking advantage of the
3436 * extra precision of acc0 not normally used for floating point
3439 * HSW and up are careful enough not to try to access an
3440 * accumulator register that doesn't exist, but on earlier Gen7
3441 * hardware we need to make sure that the quarter control bits are
3442 * zero to avoid non-deterministic behaviour and emit an extra MOV
3443 * to get the result masked correctly according to the current
3446 mach
->force_sechalf
= false;
3447 mach
->force_writemask_all
= true;
3448 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3449 ibld
.MOV(inst
->dst
, mach
->dst
);
3455 inst
->remove(block
);
3460 invalidate_live_intervals();
3466 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3467 fs_reg
*dst
, fs_reg color
, unsigned components
)
3469 if (key
->clamp_fragment_color
) {
3470 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3471 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3473 for (unsigned i
= 0; i
< components
; i
++)
3475 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3480 for (unsigned i
= 0; i
< components
; i
++)
3481 dst
[i
] = offset(color
, bld
, i
);
3485 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3486 const brw_wm_prog_data
*prog_data
,
3487 const brw_wm_prog_key
*key
,
3488 const fs_visitor::thread_payload
&payload
)
3490 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3491 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3492 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3493 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3494 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3495 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3496 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3497 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3498 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3499 const unsigned components
=
3500 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3502 /* We can potentially have a message length of up to 15, so we have to set
3503 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3506 int header_size
= 2, payload_header_size
;
3507 unsigned length
= 0;
3509 /* From the Sandy Bridge PRM, volume 4, page 198:
3511 * "Dispatched Pixel Enables. One bit per pixel indicating
3512 * which pixels were originally enabled when the thread was
3513 * dispatched. This field is only required for the end-of-
3514 * thread message and on all dual-source messages."
3516 if (devinfo
->gen
>= 6 &&
3517 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3518 color1
.file
== BAD_FILE
&&
3519 key
->nr_color_regions
== 1) {
3523 if (header_size
!= 0) {
3524 assert(header_size
== 2);
3525 /* Allocate 2 registers for a header */
3529 if (payload
.aa_dest_stencil_reg
) {
3530 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3531 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3532 .MOV(sources
[length
],
3533 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3537 if (prog_data
->uses_omask
) {
3538 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3539 BRW_REGISTER_TYPE_UD
);
3541 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3542 * relevant. Since it's unsigned single words one vgrf is always
3543 * 16-wide, but only the lower or higher 8 channels will be used by the
3544 * hardware when doing a SIMD8 write depending on whether we have
3545 * selected the subspans for the first or second half respectively.
3547 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3548 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3549 sample_mask
.stride
*= 2;
3551 bld
.exec_all().annotate("FB write oMask")
3552 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3553 inst
->force_sechalf
),
3558 payload_header_size
= length
;
3560 if (src0_alpha
.file
!= BAD_FILE
) {
3561 /* FIXME: This is being passed at the wrong location in the payload and
3562 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3563 * It's supposed to be immediately before oMask but there seems to be no
3564 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3565 * requires header sources to form a contiguous segment at the beginning
3566 * of the message and src0_alpha has per-channel semantics.
3568 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3572 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3575 if (color1
.file
!= BAD_FILE
) {
3576 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3580 if (src_depth
.file
!= BAD_FILE
) {
3581 sources
[length
] = src_depth
;
3585 if (dst_depth
.file
!= BAD_FILE
) {
3586 sources
[length
] = dst_depth
;
3590 if (src_stencil
.file
!= BAD_FILE
) {
3591 assert(devinfo
->gen
>= 9);
3592 assert(bld
.dispatch_width() != 16);
3594 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3595 bld
.exec_all().annotate("FB write OS")
3596 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3597 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3602 if (devinfo
->gen
>= 7) {
3603 /* Send from the GRF */
3604 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3605 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3606 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3607 load
->dst
= payload
;
3609 inst
->src
[0] = payload
;
3610 inst
->resize_sources(1);
3611 inst
->base_mrf
= -1;
3613 /* Send from the MRF */
3614 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3615 sources
, length
, payload_header_size
);
3617 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3618 * will do this for us if we just give it a COMPR4 destination.
3620 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3621 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3623 inst
->resize_sources(0);
3627 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3628 inst
->mlen
= load
->regs_written
;
3629 inst
->header_size
= header_size
;
3633 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3634 const fs_reg
&coordinate
,
3635 const fs_reg
&shadow_c
,
3636 const fs_reg
&lod
, const fs_reg
&lod2
,
3637 const fs_reg
&sampler
,
3638 unsigned coord_components
,
3639 unsigned grad_components
)
3641 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3642 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3643 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3644 fs_reg msg_end
= msg_begin
;
3647 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3649 for (unsigned i
= 0; i
< coord_components
; i
++)
3650 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3651 offset(coordinate
, bld
, i
));
3653 msg_end
= offset(msg_end
, bld
, coord_components
);
3655 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3656 * require all three components to be present and zero if they are unused.
3658 if (coord_components
> 0 &&
3659 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3660 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3661 for (unsigned i
= coord_components
; i
< 3; i
++)
3662 bld
.MOV(offset(msg_end
, bld
, i
), fs_reg(0.0f
));
3664 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3667 if (op
== SHADER_OPCODE_TXD
) {
3668 /* TXD unsupported in SIMD16 mode. */
3669 assert(bld
.dispatch_width() == 8);
3671 /* the slots for u and v are always present, but r is optional */
3672 if (coord_components
< 2)
3673 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3676 * dPdx = dudx, dvdx, drdx
3677 * dPdy = dudy, dvdy, drdy
3679 * 1-arg: Does not exist.
3681 * 2-arg: dudx dvdx dudy dvdy
3682 * dPdx.x dPdx.y dPdy.x dPdy.y
3685 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3686 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3687 * m5 m6 m7 m8 m9 m10
3689 for (unsigned i
= 0; i
< grad_components
; i
++)
3690 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3692 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3694 for (unsigned i
= 0; i
< grad_components
; i
++)
3695 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3697 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3701 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3702 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3704 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3705 bld
.dispatch_width() == 16);
3707 const brw_reg_type type
=
3708 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3709 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3710 bld
.MOV(retype(msg_end
, type
), lod
);
3711 msg_end
= offset(msg_end
, bld
, 1);
3714 if (shadow_c
.file
!= BAD_FILE
) {
3715 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3716 /* There's no plain shadow compare message, so we use shadow
3717 * compare with a bias of 0.0.
3719 bld
.MOV(msg_end
, fs_reg(0.0f
));
3720 msg_end
= offset(msg_end
, bld
, 1);
3723 bld
.MOV(msg_end
, shadow_c
);
3724 msg_end
= offset(msg_end
, bld
, 1);
3728 inst
->src
[0] = reg_undef
;
3729 inst
->src
[1] = sampler
;
3730 inst
->resize_sources(2);
3731 inst
->base_mrf
= msg_begin
.nr
;
3732 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3733 inst
->header_size
= 1;
3737 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3739 const fs_reg
&shadow_c
,
3740 fs_reg lod
, fs_reg lod2
,
3741 const fs_reg
&sample_index
,
3742 const fs_reg
&sampler
,
3743 const fs_reg
&offset_value
,
3744 unsigned coord_components
,
3745 unsigned grad_components
)
3747 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3748 fs_reg msg_coords
= message
;
3749 unsigned header_size
= 0;
3751 if (offset_value
.file
!= BAD_FILE
) {
3752 /* The offsets set up by the visitor are in the m1 header, so we can't
3759 for (unsigned i
= 0; i
< coord_components
; i
++) {
3760 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3761 coordinate
= offset(coordinate
, bld
, 1);
3763 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3764 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3766 if (shadow_c
.file
!= BAD_FILE
) {
3767 fs_reg msg_shadow
= msg_lod
;
3768 bld
.MOV(msg_shadow
, shadow_c
);
3769 msg_lod
= offset(msg_shadow
, bld
, 1);
3774 case SHADER_OPCODE_TXL
:
3776 bld
.MOV(msg_lod
, lod
);
3777 msg_end
= offset(msg_lod
, bld
, 1);
3779 case SHADER_OPCODE_TXD
:
3782 * dPdx = dudx, dvdx, drdx
3783 * dPdy = dudy, dvdy, drdy
3785 * Load up these values:
3786 * - dudx dudy dvdx dvdy drdx drdy
3787 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3790 for (unsigned i
= 0; i
< grad_components
; i
++) {
3791 bld
.MOV(msg_end
, lod
);
3792 lod
= offset(lod
, bld
, 1);
3793 msg_end
= offset(msg_end
, bld
, 1);
3795 bld
.MOV(msg_end
, lod2
);
3796 lod2
= offset(lod2
, bld
, 1);
3797 msg_end
= offset(msg_end
, bld
, 1);
3800 case SHADER_OPCODE_TXS
:
3801 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3802 bld
.MOV(msg_lod
, lod
);
3803 msg_end
= offset(msg_lod
, bld
, 1);
3805 case SHADER_OPCODE_TXF
:
3806 msg_lod
= offset(msg_coords
, bld
, 3);
3807 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3808 msg_end
= offset(msg_lod
, bld
, 1);
3810 case SHADER_OPCODE_TXF_CMS
:
3811 msg_lod
= offset(msg_coords
, bld
, 3);
3813 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
3815 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3816 msg_end
= offset(msg_lod
, bld
, 2);
3823 inst
->src
[0] = reg_undef
;
3824 inst
->src
[1] = sampler
;
3825 inst
->resize_sources(2);
3826 inst
->base_mrf
= message
.nr
;
3827 inst
->mlen
= msg_end
.nr
- message
.nr
;
3828 inst
->header_size
= header_size
;
3830 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3831 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3835 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3837 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3840 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
3844 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3846 const fs_reg
&shadow_c
,
3847 fs_reg lod
, fs_reg lod2
,
3848 const fs_reg
&sample_index
,
3849 const fs_reg
&mcs
, const fs_reg
&sampler
,
3850 fs_reg offset_value
,
3851 unsigned coord_components
,
3852 unsigned grad_components
)
3854 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3855 int reg_width
= bld
.dispatch_width() / 8;
3856 unsigned header_size
= 0, length
= 0;
3857 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3858 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3859 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3861 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3862 offset_value
.file
!= BAD_FILE
||
3863 is_high_sampler(devinfo
, sampler
)) {
3864 /* For general texture offsets (no txf workaround), we need a header to
3865 * put them in. Note that we're only reserving space for it in the
3866 * message payload as it will be initialized implicitly by the
3869 * TG4 needs to place its channel select in the header, for interaction
3870 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3871 * larger sampler numbers we need to offset the Sampler State Pointer in
3875 sources
[0] = fs_reg();
3879 if (shadow_c
.file
!= BAD_FILE
) {
3880 bld
.MOV(sources
[length
], shadow_c
);
3884 bool coordinate_done
= false;
3886 /* The sampler can only meaningfully compute LOD for fragment shader
3887 * messages. For all other stages, we change the opcode to TXL and
3888 * hardcode the LOD to 0.
3890 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3891 op
== SHADER_OPCODE_TEX
) {
3892 op
= SHADER_OPCODE_TXL
;
3896 /* Set up the LOD info */
3899 case SHADER_OPCODE_TXL
:
3900 bld
.MOV(sources
[length
], lod
);
3903 case SHADER_OPCODE_TXD
:
3904 /* TXD should have been lowered in SIMD16 mode. */
3905 assert(bld
.dispatch_width() == 8);
3907 /* Load dPdx and the coordinate together:
3908 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3910 for (unsigned i
= 0; i
< coord_components
; i
++) {
3911 bld
.MOV(sources
[length
], coordinate
);
3912 coordinate
= offset(coordinate
, bld
, 1);
3915 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3916 * only derivatives for (u, v, r).
3918 if (i
< grad_components
) {
3919 bld
.MOV(sources
[length
], lod
);
3920 lod
= offset(lod
, bld
, 1);
3923 bld
.MOV(sources
[length
], lod2
);
3924 lod2
= offset(lod2
, bld
, 1);
3929 coordinate_done
= true;
3931 case SHADER_OPCODE_TXS
:
3932 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3935 case SHADER_OPCODE_TXF
:
3936 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3937 * On Gen9 they are u, v, lod, r
3939 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3940 coordinate
= offset(coordinate
, bld
, 1);
3943 if (devinfo
->gen
>= 9) {
3944 if (coord_components
>= 2) {
3945 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3946 coordinate
= offset(coordinate
, bld
, 1);
3951 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
3954 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
3955 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3956 coordinate
= offset(coordinate
, bld
, 1);
3960 coordinate_done
= true;
3962 case SHADER_OPCODE_TXF_CMS
:
3963 case SHADER_OPCODE_TXF_CMS_W
:
3964 case SHADER_OPCODE_TXF_UMS
:
3965 case SHADER_OPCODE_TXF_MCS
:
3966 if (op
== SHADER_OPCODE_TXF_UMS
||
3967 op
== SHADER_OPCODE_TXF_CMS
||
3968 op
== SHADER_OPCODE_TXF_CMS_W
) {
3969 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
3973 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
3974 /* Data from the multisample control surface. */
3975 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
3978 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
3981 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
3982 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
3985 offset(mcs
, bld
, 1));
3990 /* There is no offsetting for this message; just copy in the integer
3991 * texture coordinates.
3993 for (unsigned i
= 0; i
< coord_components
; i
++) {
3994 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3995 coordinate
= offset(coordinate
, bld
, 1);
3999 coordinate_done
= true;
4001 case SHADER_OPCODE_TG4_OFFSET
:
4002 /* gather4_po_c should have been lowered in SIMD16 mode. */
4003 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
4005 /* More crazy intermixing */
4006 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
4007 bld
.MOV(sources
[length
], coordinate
);
4008 coordinate
= offset(coordinate
, bld
, 1);
4012 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
4013 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
4014 offset_value
= offset(offset_value
, bld
, 1);
4018 if (coord_components
== 3) { /* r if present */
4019 bld
.MOV(sources
[length
], coordinate
);
4020 coordinate
= offset(coordinate
, bld
, 1);
4024 coordinate_done
= true;
4030 /* Set up the coordinate (except for cases where it was done above) */
4031 if (!coordinate_done
) {
4032 for (unsigned i
= 0; i
< coord_components
; i
++) {
4033 bld
.MOV(sources
[length
], coordinate
);
4034 coordinate
= offset(coordinate
, bld
, 1);
4041 mlen
= length
* reg_width
- header_size
;
4043 mlen
= length
* reg_width
;
4045 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4046 BRW_REGISTER_TYPE_F
);
4047 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4049 /* Generate the SEND. */
4051 inst
->src
[0] = src_payload
;
4052 inst
->src
[1] = sampler
;
4053 inst
->resize_sources(2);
4054 inst
->base_mrf
= -1;
4056 inst
->header_size
= header_size
;
4058 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4059 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4063 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4065 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4066 const fs_reg
&coordinate
= inst
->src
[0];
4067 const fs_reg
&shadow_c
= inst
->src
[1];
4068 const fs_reg
&lod
= inst
->src
[2];
4069 const fs_reg
&lod2
= inst
->src
[3];
4070 const fs_reg
&sample_index
= inst
->src
[4];
4071 const fs_reg
&mcs
= inst
->src
[5];
4072 const fs_reg
&sampler
= inst
->src
[6];
4073 const fs_reg
&offset_value
= inst
->src
[7];
4074 assert(inst
->src
[8].file
== IMM
&& inst
->src
[9].file
== IMM
);
4075 const unsigned coord_components
= inst
->src
[8].ud
;
4076 const unsigned grad_components
= inst
->src
[9].ud
;
4078 if (devinfo
->gen
>= 7) {
4079 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4080 shadow_c
, lod
, lod2
, sample_index
,
4081 mcs
, sampler
, offset_value
,
4082 coord_components
, grad_components
);
4083 } else if (devinfo
->gen
>= 5) {
4084 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4085 shadow_c
, lod
, lod2
, sample_index
,
4086 sampler
, offset_value
,
4087 coord_components
, grad_components
);
4089 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4090 shadow_c
, lod
, lod2
, sampler
,
4091 coord_components
, grad_components
);
4096 * Initialize the header present in some typed and untyped surface
4100 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4102 fs_builder ubld
= bld
.exec_all().group(8, 0);
4103 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4104 ubld
.MOV(dst
, fs_reg(0));
4105 ubld
.MOV(component(dst
, 7), sample_mask
);
4110 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4111 const fs_reg
&sample_mask
)
4113 /* Get the logical send arguments. */
4114 const fs_reg
&addr
= inst
->src
[0];
4115 const fs_reg
&src
= inst
->src
[1];
4116 const fs_reg
&surface
= inst
->src
[2];
4117 const UNUSED fs_reg
&dims
= inst
->src
[3];
4118 const fs_reg
&arg
= inst
->src
[4];
4120 /* Calculate the total number of components of the payload. */
4121 const unsigned addr_sz
= inst
->components_read(0);
4122 const unsigned src_sz
= inst
->components_read(1);
4123 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4124 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4126 /* Allocate space for the payload. */
4127 fs_reg
*const components
= new fs_reg
[sz
];
4128 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4131 /* Construct the payload. */
4133 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4135 for (unsigned i
= 0; i
< addr_sz
; i
++)
4136 components
[n
++] = offset(addr
, bld
, i
);
4138 for (unsigned i
= 0; i
< src_sz
; i
++)
4139 components
[n
++] = offset(src
, bld
, i
);
4141 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4143 /* Update the original instruction. */
4145 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4146 inst
->header_size
= header_sz
;
4148 inst
->src
[0] = payload
;
4149 inst
->src
[1] = surface
;
4151 inst
->resize_sources(3);
4153 delete[] components
;
4157 fs_visitor::lower_logical_sends()
4159 bool progress
= false;
4161 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4162 const fs_builder
ibld(this, block
, inst
);
4164 switch (inst
->opcode
) {
4165 case FS_OPCODE_FB_WRITE_LOGICAL
:
4166 assert(stage
== MESA_SHADER_FRAGMENT
);
4167 lower_fb_write_logical_send(ibld
, inst
,
4168 (const brw_wm_prog_data
*)prog_data
,
4169 (const brw_wm_prog_key
*)key
,
4173 case SHADER_OPCODE_TEX_LOGICAL
:
4174 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4177 case SHADER_OPCODE_TXD_LOGICAL
:
4178 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4181 case SHADER_OPCODE_TXF_LOGICAL
:
4182 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4185 case SHADER_OPCODE_TXL_LOGICAL
:
4186 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4189 case SHADER_OPCODE_TXS_LOGICAL
:
4190 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4193 case FS_OPCODE_TXB_LOGICAL
:
4194 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4197 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4198 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4201 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4202 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4205 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4206 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4209 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4210 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4213 case SHADER_OPCODE_LOD_LOGICAL
:
4214 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4217 case SHADER_OPCODE_TG4_LOGICAL
:
4218 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4221 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4222 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4225 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4226 lower_surface_logical_send(ibld
, inst
,
4227 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4231 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4232 lower_surface_logical_send(ibld
, inst
,
4233 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4234 ibld
.sample_mask_reg());
4237 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4238 lower_surface_logical_send(ibld
, inst
,
4239 SHADER_OPCODE_UNTYPED_ATOMIC
,
4240 ibld
.sample_mask_reg());
4243 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4244 lower_surface_logical_send(ibld
, inst
,
4245 SHADER_OPCODE_TYPED_SURFACE_READ
,
4249 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4250 lower_surface_logical_send(ibld
, inst
,
4251 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4252 ibld
.sample_mask_reg());
4255 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4256 lower_surface_logical_send(ibld
, inst
,
4257 SHADER_OPCODE_TYPED_ATOMIC
,
4258 ibld
.sample_mask_reg());
4269 invalidate_live_intervals();
4275 * Get the closest native SIMD width supported by the hardware for instruction
4276 * \p inst. The instruction will be left untouched by
4277 * fs_visitor::lower_simd_width() if the returned value is equal to the
4278 * original execution size.
4281 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4282 const fs_inst
*inst
)
4284 switch (inst
->opcode
) {
4285 case BRW_OPCODE_MOV
:
4286 case BRW_OPCODE_SEL
:
4287 case BRW_OPCODE_NOT
:
4288 case BRW_OPCODE_AND
:
4290 case BRW_OPCODE_XOR
:
4291 case BRW_OPCODE_SHR
:
4292 case BRW_OPCODE_SHL
:
4293 case BRW_OPCODE_ASR
:
4294 case BRW_OPCODE_CMP
:
4295 case BRW_OPCODE_CMPN
:
4296 case BRW_OPCODE_CSEL
:
4297 case BRW_OPCODE_F32TO16
:
4298 case BRW_OPCODE_F16TO32
:
4299 case BRW_OPCODE_BFREV
:
4300 case BRW_OPCODE_BFE
:
4301 case BRW_OPCODE_BFI1
:
4302 case BRW_OPCODE_BFI2
:
4303 case BRW_OPCODE_ADD
:
4304 case BRW_OPCODE_MUL
:
4305 case BRW_OPCODE_AVG
:
4306 case BRW_OPCODE_FRC
:
4307 case BRW_OPCODE_RNDU
:
4308 case BRW_OPCODE_RNDD
:
4309 case BRW_OPCODE_RNDE
:
4310 case BRW_OPCODE_RNDZ
:
4311 case BRW_OPCODE_LZD
:
4312 case BRW_OPCODE_FBH
:
4313 case BRW_OPCODE_FBL
:
4314 case BRW_OPCODE_CBIT
:
4315 case BRW_OPCODE_SAD2
:
4316 case BRW_OPCODE_MAD
:
4317 case BRW_OPCODE_LRP
:
4318 case SHADER_OPCODE_RCP
:
4319 case SHADER_OPCODE_RSQ
:
4320 case SHADER_OPCODE_SQRT
:
4321 case SHADER_OPCODE_EXP2
:
4322 case SHADER_OPCODE_LOG2
:
4323 case SHADER_OPCODE_POW
:
4324 case SHADER_OPCODE_INT_QUOTIENT
:
4325 case SHADER_OPCODE_INT_REMAINDER
:
4326 case SHADER_OPCODE_SIN
:
4327 case SHADER_OPCODE_COS
: {
4328 /* According to the PRMs:
4329 * "A. In Direct Addressing mode, a source cannot span more than 2
4330 * adjacent GRF registers.
4331 * B. A destination cannot span more than 2 adjacent GRF registers."
4333 * Look for the source or destination with the largest register region
4334 * which is the one that is going to limit the overal execution size of
4335 * the instruction due to this rule.
4337 unsigned reg_count
= inst
->regs_written
;
4339 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4340 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4342 /* Calculate the maximum execution size of the instruction based on the
4343 * factor by which it goes over the hardware limit of 2 GRFs.
4345 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4347 case SHADER_OPCODE_MULH
:
4348 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4349 * is 8-wide on Gen7+.
4351 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4353 case FS_OPCODE_FB_WRITE_LOGICAL
:
4354 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4357 assert(devinfo
->gen
!= 6 ||
4358 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4359 inst
->exec_size
== 8);
4360 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4361 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4362 8 : inst
->exec_size
);
4364 case SHADER_OPCODE_TXD_LOGICAL
:
4365 /* TXD is unsupported in SIMD16 mode. */
4368 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4369 /* gather4_po_c is unsupported in SIMD16 mode. */
4370 const fs_reg
&shadow_c
= inst
->src
[1];
4371 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4373 case SHADER_OPCODE_TXL_LOGICAL
:
4374 case FS_OPCODE_TXB_LOGICAL
: {
4375 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4376 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4377 * mode because the message exceeds the maximum length of 11.
4379 const fs_reg
&shadow_c
= inst
->src
[1];
4380 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4382 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4385 return inst
->exec_size
;
4387 case SHADER_OPCODE_TXF_LOGICAL
:
4388 case SHADER_OPCODE_TXS_LOGICAL
:
4389 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4390 * messages. Use SIMD16 instead.
4392 if (devinfo
->gen
== 4)
4395 return inst
->exec_size
;
4397 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4398 /* This opcode can take up to 6 arguments which means that in some
4399 * circumstances it can end up with a message that is too long in SIMD16
4402 const unsigned coord_components
= inst
->src
[8].ud
;
4403 /* First three arguments are the sample index and the two arguments for
4406 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4409 return inst
->exec_size
;
4412 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4413 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4414 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4418 return inst
->exec_size
;
4423 * The \p rows array of registers represents a \p num_rows by \p num_columns
4424 * matrix in row-major order, write it in column-major order into the register
4425 * passed as destination. \p stride gives the separation between matrix
4426 * elements in the input in fs_builder::dispatch_width() units.
4429 emit_transpose(const fs_builder
&bld
,
4430 const fs_reg
&dst
, const fs_reg
*rows
,
4431 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4433 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4435 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4436 for (unsigned j
= 0; j
< num_rows
; ++j
)
4437 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4440 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4442 delete[] components
;
4446 fs_visitor::lower_simd_width()
4448 bool progress
= false;
4450 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4451 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4453 if (lower_width
!= inst
->exec_size
) {
4454 /* Builder matching the original instruction. We may also need to
4455 * emit an instruction of width larger than the original, set the
4456 * execution size of the builder to the highest of both for now so
4457 * we're sure that both cases can be handled.
4459 const fs_builder ibld
= bld
.at(block
, inst
)
4460 .exec_all(inst
->force_writemask_all
)
4461 .group(MAX2(inst
->exec_size
, lower_width
),
4462 inst
->force_sechalf
);
4464 /* Split the copies in chunks of the execution width of either the
4465 * original or the lowered instruction, whichever is lower.
4467 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4468 const unsigned n
= inst
->exec_size
/ copy_width
;
4469 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4470 inst
->dst
.component_size(inst
->exec_size
);
4473 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4474 !inst
->writes_accumulator
&& !inst
->mlen
);
4476 for (unsigned i
= 0; i
< n
; i
++) {
4477 /* Emit a copy of the original instruction with the lowered width.
4478 * If the EOT flag was set throw it away except for the last
4479 * instruction to avoid killing the thread prematurely.
4481 fs_inst split_inst
= *inst
;
4482 split_inst
.exec_size
= lower_width
;
4483 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4485 /* Select the correct channel enables for the i-th group, then
4486 * transform the sources and destination and emit the lowered
4489 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4491 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4492 if (inst
->src
[j
].file
!= BAD_FILE
&&
4493 !is_uniform(inst
->src
[j
])) {
4494 /* Get the i-th copy_width-wide chunk of the source. */
4495 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4496 const unsigned src_size
= inst
->components_read(j
);
4498 /* Use a trivial transposition to copy one every n
4499 * copy_width-wide components of the register into a
4500 * temporary passed as source to the lowered instruction.
4502 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4503 emit_transpose(lbld
.group(copy_width
, 0),
4504 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4508 if (inst
->regs_written
) {
4509 /* Allocate enough space to hold the result of the lowered
4510 * instruction and fix up the number of registers written.
4512 split_inst
.dst
= dsts
[i
] =
4513 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4514 split_inst
.regs_written
=
4515 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4519 lbld
.emit(split_inst
);
4522 if (inst
->regs_written
) {
4523 /* Distance between useful channels in the temporaries, skipping
4524 * garbage if the lowered instruction is wider than the original.
4526 const unsigned m
= lower_width
/ copy_width
;
4528 /* Interleave the components of the result from the lowered
4529 * instructions. We need to set exec_all() when copying more than
4530 * one half per component, because LOAD_PAYLOAD (in terms of which
4531 * emit_transpose is implemented) can only use the same channel
4532 * enable signals for all of its non-header sources.
4534 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4535 .group(copy_width
, 0),
4536 inst
->dst
, dsts
, n
, dst_size
, m
);
4539 inst
->remove(block
);
4545 invalidate_live_intervals();
4551 fs_visitor::dump_instructions()
4553 dump_instructions(NULL
);
4557 fs_visitor::dump_instructions(const char *name
)
4559 FILE *file
= stderr
;
4560 if (name
&& geteuid() != 0) {
4561 file
= fopen(name
, "w");
4567 calculate_register_pressure();
4568 int ip
= 0, max_pressure
= 0;
4569 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4570 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4571 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4572 dump_instruction(inst
, file
);
4575 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4578 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4579 fprintf(file
, "%4d: ", ip
++);
4580 dump_instruction(inst
, file
);
4584 if (file
!= stderr
) {
4590 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4592 dump_instruction(be_inst
, stderr
);
4596 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4598 fs_inst
*inst
= (fs_inst
*)be_inst
;
4600 if (inst
->predicate
) {
4601 fprintf(file
, "(%cf0.%d) ",
4602 inst
->predicate_inverse
? '-' : '+',
4606 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4608 fprintf(file
, ".sat");
4609 if (inst
->conditional_mod
) {
4610 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4611 if (!inst
->predicate
&&
4612 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4613 inst
->opcode
!= BRW_OPCODE_IF
&&
4614 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4615 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4618 fprintf(file
, "(%d) ", inst
->exec_size
);
4621 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4624 switch (inst
->dst
.file
) {
4626 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
4627 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
4628 inst
->dst
.subreg_offset
)
4629 fprintf(file
, "+%d.%d",
4630 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4633 fprintf(file
, "g%d", inst
->dst
.nr
);
4636 fprintf(file
, "m%d", inst
->dst
.nr
);
4639 fprintf(file
, "(null)");
4642 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4645 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4648 switch (inst
->dst
.nr
) {
4650 fprintf(file
, "null");
4652 case BRW_ARF_ADDRESS
:
4653 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
4655 case BRW_ARF_ACCUMULATOR
:
4656 fprintf(file
, "acc%d", inst
->dst
.subnr
);
4659 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4662 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4665 if (inst
->dst
.subnr
)
4666 fprintf(file
, "+%d", inst
->dst
.subnr
);
4669 unreachable("not reached");
4671 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4673 for (int i
= 0; i
< inst
->sources
; i
++) {
4674 if (inst
->src
[i
].negate
)
4676 if (inst
->src
[i
].abs
)
4678 switch (inst
->src
[i
].file
) {
4680 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
4681 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
4682 inst
->src
[i
].subreg_offset
)
4683 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4684 inst
->src
[i
].subreg_offset
);
4687 fprintf(file
, "g%d", inst
->src
[i
].nr
);
4690 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
4693 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
4696 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
4697 if (inst
->src
[i
].reladdr
) {
4698 fprintf(file
, "+reladdr");
4699 } else if (inst
->src
[i
].subreg_offset
) {
4700 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4701 inst
->src
[i
].subreg_offset
);
4705 fprintf(file
, "(null)");
4708 switch (inst
->src
[i
].type
) {
4709 case BRW_REGISTER_TYPE_F
:
4710 fprintf(file
, "%ff", inst
->src
[i
].f
);
4712 case BRW_REGISTER_TYPE_W
:
4713 case BRW_REGISTER_TYPE_D
:
4714 fprintf(file
, "%dd", inst
->src
[i
].d
);
4716 case BRW_REGISTER_TYPE_UW
:
4717 case BRW_REGISTER_TYPE_UD
:
4718 fprintf(file
, "%uu", inst
->src
[i
].ud
);
4720 case BRW_REGISTER_TYPE_VF
:
4721 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4722 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
4723 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
4724 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
4725 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
4728 fprintf(file
, "???");
4733 switch (inst
->src
[i
].nr
) {
4735 fprintf(file
, "null");
4737 case BRW_ARF_ADDRESS
:
4738 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
4740 case BRW_ARF_ACCUMULATOR
:
4741 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
4744 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4747 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4750 if (inst
->src
[i
].subnr
)
4751 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
4754 if (inst
->src
[i
].abs
)
4757 if (inst
->src
[i
].file
!= IMM
) {
4758 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4761 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4762 fprintf(file
, ", ");
4767 if (inst
->force_writemask_all
)
4768 fprintf(file
, "NoMask ");
4770 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4771 if (inst
->force_sechalf
)
4772 fprintf(file
, "2ndhalf ");
4774 fprintf(file
, "1sthalf ");
4777 fprintf(file
, "\n");
4781 * Possibly returns an instruction that set up @param reg.
4783 * Sometimes we want to take the result of some expression/variable
4784 * dereference tree and rewrite the instruction generating the result
4785 * of the tree. When processing the tree, we know that the
4786 * instructions generated are all writing temporaries that are dead
4787 * outside of this tree. So, if we have some instructions that write
4788 * a temporary, we're free to point that temp write somewhere else.
4790 * Note that this doesn't guarantee that the instruction generated
4791 * only reg -- it might be the size=4 destination of a texture instruction.
4794 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4799 end
->is_partial_write() ||
4801 !reg
.equals(end
->dst
)) {
4809 fs_visitor::setup_payload_gen6()
4812 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4813 unsigned barycentric_interp_modes
=
4814 (stage
== MESA_SHADER_FRAGMENT
) ?
4815 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4817 assert(devinfo
->gen
>= 6);
4819 /* R0-1: masks, pixel X/Y coordinates. */
4820 payload
.num_regs
= 2;
4821 /* R2: only for 32-pixel dispatch.*/
4823 /* R3-26: barycentric interpolation coordinates. These appear in the
4824 * same order that they appear in the brw_wm_barycentric_interp_mode
4825 * enum. Each set of coordinates occupies 2 registers if dispatch width
4826 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4827 * appear if they were enabled using the "Barycentric Interpolation
4828 * Mode" bits in WM_STATE.
4830 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4831 if (barycentric_interp_modes
& (1 << i
)) {
4832 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4833 payload
.num_regs
+= 2;
4834 if (dispatch_width
== 16) {
4835 payload
.num_regs
+= 2;
4840 /* R27: interpolated depth if uses source depth */
4842 payload
.source_depth_reg
= payload
.num_regs
;
4844 if (dispatch_width
== 16) {
4845 /* R28: interpolated depth if not SIMD8. */
4849 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4851 payload
.source_w_reg
= payload
.num_regs
;
4853 if (dispatch_width
== 16) {
4854 /* R30: interpolated W if not SIMD8. */
4859 if (stage
== MESA_SHADER_FRAGMENT
) {
4860 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4861 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4862 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4863 /* R31: MSAA position offsets. */
4864 if (prog_data
->uses_pos_offset
) {
4865 payload
.sample_pos_reg
= payload
.num_regs
;
4870 /* R32: MSAA input coverage mask */
4871 if (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4872 assert(devinfo
->gen
>= 7);
4873 payload
.sample_mask_in_reg
= payload
.num_regs
;
4875 if (dispatch_width
== 16) {
4876 /* R33: input coverage mask if not SIMD8. */
4881 /* R34-: bary for 32-pixel. */
4882 /* R58-59: interp W for 32-pixel. */
4884 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4885 source_depth_to_render_target
= true;
4890 fs_visitor::setup_vs_payload()
4892 /* R0: thread header, R1: urb handles */
4893 payload
.num_regs
= 2;
4897 * We are building the local ID push constant data using the simplest possible
4898 * method. We simply push the local IDs directly as they should appear in the
4899 * registers for the uvec3 gl_LocalInvocationID variable.
4901 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4902 * registers worth of push constant space.
4904 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
4905 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
4908 * FINISHME: There are a few easy optimizations to consider.
4910 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
4911 * no need for using push constant space for that dimension.
4913 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
4914 * easily use 16-bit words rather than 32-bit dwords in the push constant
4917 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
4918 * conveying the data, and thereby reduce push constant usage.
4922 fs_visitor::setup_gs_payload()
4924 assert(stage
== MESA_SHADER_GEOMETRY
);
4926 struct brw_gs_prog_data
*gs_prog_data
=
4927 (struct brw_gs_prog_data
*) prog_data
;
4928 struct brw_vue_prog_data
*vue_prog_data
=
4929 (struct brw_vue_prog_data
*) prog_data
;
4931 /* R0: thread header, R1: output URB handles */
4932 payload
.num_regs
= 2;
4934 if (gs_prog_data
->include_primitive_id
) {
4935 /* R2: Primitive ID 0..7 */
4939 /* Use a maximum of 32 registers for push-model inputs. */
4940 const unsigned max_push_components
= 32;
4942 /* If pushing our inputs would take too many registers, reduce the URB read
4943 * length (which is in HWords, or 8 registers), and resort to pulling.
4945 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
4946 * have to multiply by VerticesIn to obtain the total storage requirement.
4948 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
4949 max_push_components
) {
4950 gs_prog_data
->base
.include_vue_handles
= true;
4952 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
4953 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
4955 vue_prog_data
->urb_read_length
=
4956 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
4961 fs_visitor::setup_cs_payload()
4963 assert(devinfo
->gen
>= 7);
4964 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
4966 payload
.num_regs
= 1;
4968 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
4969 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
4970 payload
.local_invocation_id_reg
= payload
.num_regs
;
4971 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
4976 fs_visitor::calculate_register_pressure()
4978 invalidate_live_intervals();
4979 calculate_live_intervals();
4981 unsigned num_instructions
= 0;
4982 foreach_block(block
, cfg
)
4983 num_instructions
+= block
->instructions
.length();
4985 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
4987 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
4988 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
4989 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
4994 fs_visitor::optimize()
4996 /* Start by validating the shader we currently have. */
4999 /* bld is the common builder object pointing at the end of the program we
5000 * used to translate it into i965 IR. For the optimization and lowering
5001 * passes coming next, any code added after the end of the program without
5002 * having explicitly called fs_builder::at() clearly points at a mistake.
5003 * Ideally optimization passes wouldn't be part of the visitor so they
5004 * wouldn't have access to bld at all, but they do, so just in case some
5005 * pass forgets to ask for a location explicitly set it to NULL here to
5006 * make it trip. The dispatch width is initialized to a bogus value to
5007 * make sure that optimizations set the execution controls explicitly to
5008 * match the code they are manipulating instead of relying on the defaults.
5010 bld
= fs_builder(this, 64);
5012 assign_constant_locations();
5013 demote_pull_constants();
5017 split_virtual_grfs();
5020 #define OPT(pass, args...) ({ \
5022 bool this_progress = pass(args); \
5024 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5025 char filename[64]; \
5026 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5027 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5029 backend_shader::dump_instructions(filename); \
5034 progress = progress || this_progress; \
5038 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5040 snprintf(filename
, 64, "%s%d-%s-00-start",
5041 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5043 backend_shader::dump_instructions(filename
);
5046 bool progress
= false;
5050 OPT(lower_simd_width
);
5051 OPT(lower_logical_sends
);
5058 OPT(remove_duplicate_mrf_writes
);
5062 OPT(opt_copy_propagate
);
5063 OPT(opt_predicated_break
, this);
5064 OPT(opt_cmod_propagation
);
5065 OPT(dead_code_eliminate
);
5066 OPT(opt_peephole_sel
);
5067 OPT(dead_control_flow_eliminate
, this);
5068 OPT(opt_register_renaming
);
5069 OPT(opt_redundant_discard_jumps
);
5070 OPT(opt_saturate_propagation
);
5071 OPT(opt_zero_samples
);
5072 OPT(register_coalesce
);
5073 OPT(compute_to_mrf
);
5074 OPT(eliminate_find_live_channel
);
5076 OPT(compact_virtual_grfs
);
5081 OPT(opt_sampler_eot
);
5083 if (OPT(lower_load_payload
)) {
5084 split_virtual_grfs();
5085 OPT(register_coalesce
);
5086 OPT(compute_to_mrf
);
5087 OPT(dead_code_eliminate
);
5090 OPT(opt_combine_constants
);
5091 OPT(lower_integer_multiplication
);
5093 lower_uniform_pull_constant_loads();
5099 * Three source instruction must have a GRF/MRF destination register.
5100 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5103 fs_visitor::fixup_3src_null_dest()
5105 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5106 if (inst
->is_3src() && inst
->dst
.is_null()) {
5107 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5114 fs_visitor::allocate_registers()
5116 bool allocated_without_spills
;
5118 static const enum instruction_scheduler_mode pre_modes
[] = {
5120 SCHEDULE_PRE_NON_LIFO
,
5124 /* Try each scheduling heuristic to see if it can successfully register
5125 * allocate without spilling. They should be ordered by decreasing
5126 * performance but increasing likelihood of allocating.
5128 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5129 schedule_instructions(pre_modes
[i
]);
5132 assign_regs_trivial();
5133 allocated_without_spills
= true;
5135 allocated_without_spills
= assign_regs(false);
5137 if (allocated_without_spills
)
5141 if (!allocated_without_spills
) {
5142 /* We assume that any spilling is worse than just dropping back to
5143 * SIMD8. There's probably actually some intermediate point where
5144 * SIMD16 with a couple of spills is still better.
5146 if (dispatch_width
== 16) {
5147 fail("Failure to register allocate. Reduce number of "
5148 "live scalar values to avoid this.");
5150 compiler
->shader_perf_log(log_data
,
5151 "%s shader triggered register spilling. "
5152 "Try reducing the number of live scalar "
5153 "values to improve performance.\n",
5157 /* Since we're out of heuristics, just go spill registers until we
5158 * get an allocation.
5160 while (!assign_regs(true)) {
5166 /* This must come after all optimization and register allocation, since
5167 * it inserts dead code that happens to have side effects, and it does
5168 * so based on the actual physical registers in use.
5170 insert_gen4_send_dependency_workarounds();
5175 schedule_instructions(SCHEDULE_POST
);
5177 if (last_scratch
> 0)
5178 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5182 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5184 assert(stage
== MESA_SHADER_VERTEX
);
5188 if (shader_time_index
>= 0)
5189 emit_shader_time_begin();
5196 compute_clip_distance(clip_planes
);
5200 if (shader_time_index
>= 0)
5201 emit_shader_time_end();
5207 assign_curb_setup();
5208 assign_vs_urb_setup();
5210 fixup_3src_null_dest();
5211 allocate_registers();
5217 fs_visitor::run_gs()
5219 assert(stage
== MESA_SHADER_GEOMETRY
);
5223 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
5225 if (gs_compile
->control_data_header_size_bits
> 0) {
5226 /* Create a VGRF to store accumulated control data bits. */
5227 this->control_data_bits
= vgrf(glsl_type::uint_type
);
5229 /* If we're outputting more than 32 control data bits, then EmitVertex()
5230 * will set control_data_bits to 0 after emitting the first vertex.
5231 * Otherwise, we need to initialize it to 0 here.
5233 if (gs_compile
->control_data_header_size_bits
<= 32) {
5234 const fs_builder abld
= bld
.annotate("initialize control data bits");
5235 abld
.MOV(this->control_data_bits
, fs_reg(0u));
5239 if (shader_time_index
>= 0)
5240 emit_shader_time_begin();
5244 emit_gs_thread_end();
5246 if (shader_time_index
>= 0)
5247 emit_shader_time_end();
5256 assign_curb_setup();
5257 assign_gs_urb_setup();
5259 fixup_3src_null_dest();
5260 allocate_registers();
5266 fs_visitor::run_fs(bool do_rep_send
)
5268 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5269 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5271 assert(stage
== MESA_SHADER_FRAGMENT
);
5273 if (devinfo
->gen
>= 6)
5274 setup_payload_gen6();
5276 setup_payload_gen4();
5280 } else if (do_rep_send
) {
5281 assert(dispatch_width
== 16);
5282 emit_repclear_shader();
5284 if (shader_time_index
>= 0)
5285 emit_shader_time_begin();
5287 calculate_urb_setup();
5288 if (nir
->info
.inputs_read
> 0) {
5289 if (devinfo
->gen
< 6)
5290 emit_interpolation_setup_gen4();
5292 emit_interpolation_setup_gen6();
5295 /* We handle discards by keeping track of the still-live pixels in f0.1.
5296 * Initialize it with the dispatched pixels.
5298 if (wm_prog_data
->uses_kill
) {
5299 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5300 discard_init
->flag_subreg
= 1;
5303 /* Generate FS IR for main(). (the visitor only descends into
5304 * functions called "main").
5311 if (wm_prog_data
->uses_kill
)
5312 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5314 if (wm_key
->alpha_test_func
)
5319 if (shader_time_index
>= 0)
5320 emit_shader_time_end();
5326 assign_curb_setup();
5329 fixup_3src_null_dest();
5330 allocate_registers();
5336 if (dispatch_width
== 8)
5337 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5339 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5345 fs_visitor::run_cs()
5347 assert(stage
== MESA_SHADER_COMPUTE
);
5351 if (shader_time_index
>= 0)
5352 emit_shader_time_begin();
5359 emit_cs_terminate();
5361 if (shader_time_index
>= 0)
5362 emit_shader_time_end();
5368 assign_curb_setup();
5370 fixup_3src_null_dest();
5371 allocate_registers();
5380 * Return a bitfield where bit n is set if barycentric interpolation mode n
5381 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5384 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5385 bool shade_model_flat
,
5386 bool persample_shading
,
5387 const nir_shader
*shader
)
5389 unsigned barycentric_interp_modes
= 0;
5391 nir_foreach_variable(var
, &shader
->inputs
) {
5392 enum glsl_interp_qualifier interp_qualifier
=
5393 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5394 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5395 bool is_sample
= var
->data
.sample
|| persample_shading
;
5396 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5397 (var
->data
.location
== VARYING_SLOT_COL1
);
5399 /* Ignore WPOS and FACE, because they don't require interpolation. */
5400 if (var
->data
.location
== VARYING_SLOT_POS
||
5401 var
->data
.location
== VARYING_SLOT_FACE
)
5404 /* Determine the set (or sets) of barycentric coordinates needed to
5405 * interpolate this variable. Note that when
5406 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5407 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5408 * for lit pixels, so we need both sets of barycentric coordinates.
5410 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5412 barycentric_interp_modes
|=
5413 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5414 } else if (is_sample
) {
5415 barycentric_interp_modes
|=
5416 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5418 if ((!is_centroid
&& !is_sample
) ||
5419 devinfo
->needs_unlit_centroid_workaround
) {
5420 barycentric_interp_modes
|=
5421 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5423 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5424 (!(shade_model_flat
&& is_gl_Color
) &&
5425 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5427 barycentric_interp_modes
|=
5428 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5429 } else if (is_sample
) {
5430 barycentric_interp_modes
|=
5431 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5433 if ((!is_centroid
&& !is_sample
) ||
5434 devinfo
->needs_unlit_centroid_workaround
) {
5435 barycentric_interp_modes
|=
5436 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5441 return barycentric_interp_modes
;
5445 computed_depth_mode(const nir_shader
*shader
)
5447 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5448 switch (shader
->info
.fs
.depth_layout
) {
5449 case FRAG_DEPTH_LAYOUT_NONE
:
5450 case FRAG_DEPTH_LAYOUT_ANY
:
5451 return BRW_PSCDEPTH_ON
;
5452 case FRAG_DEPTH_LAYOUT_GREATER
:
5453 return BRW_PSCDEPTH_ON_GE
;
5454 case FRAG_DEPTH_LAYOUT_LESS
:
5455 return BRW_PSCDEPTH_ON_LE
;
5456 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5457 return BRW_PSCDEPTH_OFF
;
5460 return BRW_PSCDEPTH_OFF
;
5464 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5466 const struct brw_wm_prog_key
*key
,
5467 struct brw_wm_prog_data
*prog_data
,
5468 const nir_shader
*shader
,
5469 struct gl_program
*prog
,
5470 int shader_time_index8
, int shader_time_index16
,
5472 unsigned *final_assembly_size
,
5475 /* key->alpha_test_func means simulating alpha testing via discards,
5476 * so the shader definitely kills pixels.
5478 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5479 prog_data
->uses_omask
=
5480 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5481 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5482 prog_data
->computed_stencil
=
5483 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5485 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5487 prog_data
->barycentric_interp_modes
=
5488 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5490 key
->persample_shading
,
5493 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5494 &prog_data
->base
, prog
, shader
, 8,
5495 shader_time_index8
);
5496 if (!v
.run_fs(false /* do_rep_send */)) {
5498 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5503 cfg_t
*simd16_cfg
= NULL
;
5504 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5505 &prog_data
->base
, prog
, shader
, 16,
5506 shader_time_index16
);
5507 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5508 if (!v
.simd16_unsupported
) {
5509 /* Try a SIMD16 compile */
5510 v2
.import_uniforms(&v
);
5511 if (!v2
.run_fs(use_rep_send
)) {
5512 compiler
->shader_perf_log(log_data
,
5513 "SIMD16 shader failed to compile: %s",
5516 simd16_cfg
= v2
.cfg
;
5522 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5523 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5525 prog_data
->no_8
= true;
5528 prog_data
->no_8
= false;
5531 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5532 v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
5534 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5535 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5536 shader
->info
.label
? shader
->info
.label
:
5538 shader
->info
.name
));
5542 g
.generate_code(simd8_cfg
, 8);
5544 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5546 return g
.get_assembly(final_assembly_size
);
5550 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
5551 void *buffer
, uint32_t threads
, uint32_t stride
)
5553 if (prog_data
->local_invocation_id_regs
== 0)
5556 /* 'stride' should be an integer number of registers, that is, a multiple
5559 assert(stride
% 32 == 0);
5561 unsigned x
= 0, y
= 0, z
= 0;
5562 for (unsigned t
= 0; t
< threads
; t
++) {
5563 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
5565 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
5566 param
[0 * prog_data
->simd_size
+ i
] = x
;
5567 param
[1 * prog_data
->simd_size
+ i
] = y
;
5568 param
[2 * prog_data
->simd_size
+ i
] = z
;
5571 if (x
== prog_data
->local_size
[0]) {
5574 if (y
== prog_data
->local_size
[1]) {
5577 if (z
== prog_data
->local_size
[2])
5586 fs_visitor::emit_cs_local_invocation_id_setup()
5588 assert(stage
== MESA_SHADER_COMPUTE
);
5590 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5592 struct brw_reg src
=
5593 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5594 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5596 src
.nr
+= dispatch_width
/ 8;
5597 bld
.MOV(offset(*reg
, bld
, 1), src
);
5598 src
.nr
+= dispatch_width
/ 8;
5599 bld
.MOV(offset(*reg
, bld
, 2), src
);
5605 fs_visitor::emit_cs_work_group_id_setup()
5607 assert(stage
== MESA_SHADER_COMPUTE
);
5609 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5611 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5612 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5613 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5615 bld
.MOV(*reg
, r0_1
);
5616 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5617 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5623 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5625 const struct brw_cs_prog_key
*key
,
5626 struct brw_cs_prog_data
*prog_data
,
5627 const nir_shader
*shader
,
5628 int shader_time_index
,
5629 unsigned *final_assembly_size
,
5632 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5633 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5634 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5635 unsigned local_workgroup_size
=
5636 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5637 shader
->info
.cs
.local_size
[2];
5639 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5642 const char *fail_msg
= NULL
;
5644 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5646 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5647 NULL
, /* Never used in core profile */
5648 shader
, 8, shader_time_index
);
5650 fail_msg
= v8
.fail_msg
;
5651 } else if (local_workgroup_size
<= 8 * max_cs_threads
) {
5653 prog_data
->simd_size
= 8;
5656 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5657 NULL
, /* Never used in core profile */
5658 shader
, 16, shader_time_index
);
5659 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5660 !fail_msg
&& !v8
.simd16_unsupported
&&
5661 local_workgroup_size
<= 16 * max_cs_threads
) {
5662 /* Try a SIMD16 compile */
5663 v16
.import_uniforms(&v8
);
5664 if (!v16
.run_cs()) {
5665 compiler
->shader_perf_log(log_data
,
5666 "SIMD16 shader failed to compile: %s",
5670 "Couldn't generate SIMD16 program and not "
5671 "enough threads for SIMD8";
5675 prog_data
->simd_size
= 16;
5679 if (unlikely(cfg
== NULL
)) {
5682 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5687 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5688 v8
.promoted_constants
, v8
.runtime_check_aads_emit
, "CS");
5689 if (INTEL_DEBUG
& DEBUG_CS
) {
5690 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5691 shader
->info
.label
? shader
->info
.label
:
5694 g
.enable_debug(name
);
5697 g
.generate_code(cfg
, prog_data
->simd_size
);
5699 return g
.get_assembly(final_assembly_size
);