2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "compiler/glsl_types.h"
42 #include "compiler/nir/nir_builder.h"
43 #include "program/prog_parameter.h"
47 static unsigned get_lowered_simd_width(const struct brw_device_info
*devinfo
,
51 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
52 const fs_reg
*src
, unsigned sources
)
54 memset(this, 0, sizeof(*this));
56 this->src
= new fs_reg
[MAX2(sources
, 3)];
57 for (unsigned i
= 0; i
< sources
; i
++)
58 this->src
[i
] = src
[i
];
60 this->opcode
= opcode
;
62 this->sources
= sources
;
63 this->exec_size
= exec_size
;
66 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
68 assert(this->exec_size
!= 0);
70 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
72 /* This will be the case for almost all instructions. */
79 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
83 this->regs_written
= 0;
87 unreachable("Invalid destination register file");
90 this->writes_accumulator
= false;
95 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
98 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
100 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
103 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
105 init(opcode
, exec_size
, dst
, NULL
, 0);
108 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
111 const fs_reg src
[1] = { src0
};
112 init(opcode
, exec_size
, dst
, src
, 1);
115 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
116 const fs_reg
&src0
, const fs_reg
&src1
)
118 const fs_reg src
[2] = { src0
, src1
};
119 init(opcode
, exec_size
, dst
, src
, 2);
122 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
123 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
125 const fs_reg src
[3] = { src0
, src1
, src2
};
126 init(opcode
, exec_size
, dst
, src
, 3);
129 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
130 const fs_reg src
[], unsigned sources
)
132 init(opcode
, exec_width
, dst
, src
, sources
);
135 fs_inst::fs_inst(const fs_inst
&that
)
137 memcpy(this, &that
, sizeof(that
));
139 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
141 for (unsigned i
= 0; i
< that
.sources
; i
++)
142 this->src
[i
] = that
.src
[i
];
151 fs_inst::resize_sources(uint8_t num_sources
)
153 if (this->sources
!= num_sources
) {
154 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
156 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
157 src
[i
] = this->src
[i
];
161 this->sources
= num_sources
;
166 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
168 const fs_reg
&surf_index
,
169 const fs_reg
&varying_offset
,
170 uint32_t const_offset
)
172 /* We have our constant surface use a pitch of 4 bytes, so our index can
173 * be any component of a vector, and then we load 4 contiguous
174 * components starting from that.
176 * We break down the const_offset to a portion added to the variable
177 * offset and a portion done using reg_offset, which means that if you
178 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
179 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
180 * CSE can later notice that those loads are all the same and eliminate
181 * the redundant ones.
183 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
184 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
186 /* The pull load message will load a vec4 (16 bytes). If we are loading
187 * a double this means we are only loading 2 elements worth of data.
188 * We also want to use a 32-bit data type for the dst of the load operation
189 * so other parts of the driver don't get confused about the size of the
192 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
193 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
194 vec4_result
, surf_index
, vec4_offset
);
195 inst
->regs_written
= 4 * bld
.dispatch_width() / 8;
197 if (type_sz(dst
.type
) == 8) {
198 shuffle_32bit_load_result_to_64bit_data(
199 bld
, retype(vec4_result
, dst
.type
), vec4_result
, 2);
202 vec4_result
.type
= dst
.type
;
203 bld
.MOV(dst
, offset(vec4_result
, bld
,
204 (const_offset
& 0xf) / type_sz(vec4_result
.type
)));
208 * A helper for MOV generation for fixing up broken hardware SEND dependency
212 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
214 /* The caller always wants uncompressed to emit the minimal extra
215 * dependencies, and to avoid having to deal with aligning its regs to 2.
217 const fs_builder ubld
= bld
.annotate("send dependency resolve")
220 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
224 fs_inst::equals(fs_inst
*inst
) const
226 return (opcode
== inst
->opcode
&&
227 dst
.equals(inst
->dst
) &&
228 src
[0].equals(inst
->src
[0]) &&
229 src
[1].equals(inst
->src
[1]) &&
230 src
[2].equals(inst
->src
[2]) &&
231 saturate
== inst
->saturate
&&
232 predicate
== inst
->predicate
&&
233 conditional_mod
== inst
->conditional_mod
&&
234 mlen
== inst
->mlen
&&
235 base_mrf
== inst
->base_mrf
&&
236 target
== inst
->target
&&
238 header_size
== inst
->header_size
&&
239 shadow_compare
== inst
->shadow_compare
&&
240 exec_size
== inst
->exec_size
&&
241 offset
== inst
->offset
);
245 fs_inst::overwrites_reg(const fs_reg
®
) const
247 return reg
.in_range(dst
, regs_written
);
251 fs_inst::is_send_from_grf() const
254 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
255 case SHADER_OPCODE_SHADER_TIME_ADD
:
256 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
257 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
258 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
259 case SHADER_OPCODE_UNTYPED_ATOMIC
:
260 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
261 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
262 case SHADER_OPCODE_TYPED_ATOMIC
:
263 case SHADER_OPCODE_TYPED_SURFACE_READ
:
264 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
265 case SHADER_OPCODE_URB_WRITE_SIMD8
:
266 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
267 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
268 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
269 case SHADER_OPCODE_URB_READ_SIMD8
:
270 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
272 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
273 return src
[1].file
== VGRF
;
274 case FS_OPCODE_FB_WRITE
:
275 return src
[0].file
== VGRF
;
278 return src
[0].file
== VGRF
;
285 * Returns true if this instruction's sources and destinations cannot
286 * safely be the same register.
288 * In most cases, a register can be written over safely by the same
289 * instruction that is its last use. For a single instruction, the
290 * sources are dereferenced before writing of the destination starts
293 * However, there are a few cases where this can be problematic:
295 * - Virtual opcodes that translate to multiple instructions in the
296 * code generator: if src == dst and one instruction writes the
297 * destination before a later instruction reads the source, then
298 * src will have been clobbered.
300 * - SIMD16 compressed instructions with certain regioning (see below).
302 * The register allocator uses this information to set up conflicts between
303 * GRF sources and the destination.
306 fs_inst::has_source_and_destination_hazard() const
309 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
310 /* Multiple partial writes to the destination */
313 /* The SIMD16 compressed instruction
315 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
317 * is actually decoded in hardware as:
319 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
320 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
322 * Which is safe. However, if we have uniform accesses
323 * happening, we get into trouble:
325 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
326 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
328 * Now our destination for the first instruction overwrote the
329 * second instruction's src0, and we get garbage for those 8
330 * pixels. There's a similar issue for the pre-gen6
331 * pixel_x/pixel_y, which are registers of 16-bit values and thus
332 * would get stomped by the first decode as well.
334 if (exec_size
== 16) {
335 for (int i
= 0; i
< sources
; i
++) {
336 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
337 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
338 src
[i
].type
== BRW_REGISTER_TYPE_W
||
339 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
340 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
350 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
352 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
355 fs_reg reg
= this->src
[0];
356 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
359 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
362 for (int i
= 0; i
< this->sources
; i
++) {
363 reg
.type
= this->src
[i
].type
;
364 if (!this->src
[i
].equals(reg
))
367 if (i
< this->header_size
) {
370 reg
= horiz_offset(reg
, this->exec_size
);
378 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
380 if (devinfo
->gen
== 6 && is_math())
383 if (is_send_from_grf())
386 if (!backend_instruction::can_do_source_mods())
393 fs_inst::can_change_types() const
395 return dst
.type
== src
[0].type
&&
396 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
397 (opcode
== BRW_OPCODE_MOV
||
398 (opcode
== BRW_OPCODE_SEL
&&
399 dst
.type
== src
[1].type
&&
400 predicate
!= BRW_PREDICATE_NONE
&&
401 !src
[1].abs
&& !src
[1].negate
));
405 fs_inst::has_side_effects() const
407 return this->eot
|| backend_instruction::has_side_effects();
413 memset(this, 0, sizeof(*this));
417 /** Generic unset register constructor. */
421 this->file
= BAD_FILE
;
424 fs_reg::fs_reg(struct ::brw_reg reg
) :
427 this->reg_offset
= 0;
428 this->subreg_offset
= 0;
430 if (this->file
== IMM
&&
431 (this->type
!= BRW_REGISTER_TYPE_V
&&
432 this->type
!= BRW_REGISTER_TYPE_UV
&&
433 this->type
!= BRW_REGISTER_TYPE_VF
)) {
439 fs_reg::equals(const fs_reg
&r
) const
441 return (this->backend_reg::equals(r
) &&
442 subreg_offset
== r
.subreg_offset
&&
447 fs_reg::set_smear(unsigned subreg
)
449 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
450 subreg_offset
= subreg
* type_sz(type
);
456 fs_reg::is_contiguous() const
462 fs_reg::component_size(unsigned width
) const
464 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
467 return MAX2(width
* stride
, 1) * type_sz(type
);
471 type_size_scalar(const struct glsl_type
*type
)
473 unsigned int size
, i
;
475 switch (type
->base_type
) {
478 case GLSL_TYPE_FLOAT
:
480 return type
->components();
481 case GLSL_TYPE_DOUBLE
:
482 return type
->components() * 2;
483 case GLSL_TYPE_ARRAY
:
484 return type_size_scalar(type
->fields
.array
) * type
->length
;
485 case GLSL_TYPE_STRUCT
:
487 for (i
= 0; i
< type
->length
; i
++) {
488 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
491 case GLSL_TYPE_SAMPLER
:
492 /* Samplers take up no register space, since they're baked in at
496 case GLSL_TYPE_ATOMIC_UINT
:
498 case GLSL_TYPE_SUBROUTINE
:
500 case GLSL_TYPE_IMAGE
:
501 return BRW_IMAGE_PARAM_SIZE
;
503 case GLSL_TYPE_ERROR
:
504 case GLSL_TYPE_INTERFACE
:
505 case GLSL_TYPE_FUNCTION
:
506 unreachable("not reached");
512 /* Attribute arrays are loaded as one vec4 per element (or matrix column),
513 * except for double-precision types, which are loaded as one dvec4.
516 type_size_vs_input(const struct glsl_type
*type
)
518 if (type
->is_double()) {
519 return type_size_dvec4(type
);
521 return type_size_vec4(type
);
526 * Create a MOV to read the timestamp register.
528 * The caller is responsible for emitting the MOV. The return value is
529 * the destination of the MOV, with extra parameters set.
532 fs_visitor::get_timestamp(const fs_builder
&bld
)
534 assert(devinfo
->gen
>= 7);
536 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
539 BRW_REGISTER_TYPE_UD
));
541 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
543 /* We want to read the 3 fields we care about even if it's not enabled in
546 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
552 fs_visitor::emit_shader_time_begin()
554 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
556 /* We want only the low 32 bits of the timestamp. Since it's running
557 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
558 * which is plenty of time for our purposes. It is identical across the
559 * EUs, but since it's tracking GPU core speed it will increment at a
560 * varying rate as render P-states change.
562 shader_start_time
.set_smear(0);
566 fs_visitor::emit_shader_time_end()
568 /* Insert our code just before the final SEND with EOT. */
569 exec_node
*end
= this->instructions
.get_tail();
570 assert(end
&& ((fs_inst
*) end
)->eot
);
571 const fs_builder ibld
= bld
.annotate("shader time end")
572 .exec_all().at(NULL
, end
);
574 fs_reg shader_end_time
= get_timestamp(ibld
);
576 /* We only use the low 32 bits of the timestamp - see
577 * emit_shader_time_begin()).
579 * We could also check if render P-states have changed (or anything
580 * else that might disrupt timing) by setting smear to 2 and checking if
581 * that field is != 0.
583 shader_end_time
.set_smear(0);
585 /* Check that there weren't any timestamp reset events (assuming these
586 * were the only two timestamp reads that happened).
588 fs_reg reset
= shader_end_time
;
590 set_condmod(BRW_CONDITIONAL_Z
,
591 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
592 ibld
.IF(BRW_PREDICATE_NORMAL
);
594 fs_reg start
= shader_start_time
;
596 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
599 const fs_builder cbld
= ibld
.group(1, 0);
600 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
602 /* If there were no instructions between the two timestamp gets, the diff
603 * is 2 cycles. Remove that overhead, so I can forget about that when
604 * trying to determine the time taken for single instructions.
606 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
607 SHADER_TIME_ADD(cbld
, 0, diff
);
608 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
609 ibld
.emit(BRW_OPCODE_ELSE
);
610 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
611 ibld
.emit(BRW_OPCODE_ENDIF
);
615 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
616 int shader_time_subindex
,
619 int index
= shader_time_index
* 3 + shader_time_subindex
;
620 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
623 if (dispatch_width
== 8)
624 payload
= vgrf(glsl_type::uvec2_type
);
626 payload
= vgrf(glsl_type::uint_type
);
628 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
632 fs_visitor::vfail(const char *format
, va_list va
)
641 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
642 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
644 this->fail_msg
= msg
;
647 fprintf(stderr
, "%s", msg
);
652 fs_visitor::fail(const char *format
, ...)
656 va_start(va
, format
);
662 * Mark this program as impossible to compile with dispatch width greater
665 * During the SIMD8 compile (which happens first), we can detect and flag
666 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
667 * SIMD16+ compile altogether.
669 * During a compile of dispatch width greater than n (if one happens anyway),
670 * this just calls fail().
673 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
675 if (dispatch_width
> n
) {
678 max_dispatch_width
= n
;
679 compiler
->shader_perf_log(log_data
,
680 "Shader dispatch width limited to SIMD%d: %s",
686 * Returns true if the instruction has a flag that means it won't
687 * update an entire destination register.
689 * For example, dead code elimination and live variable analysis want to know
690 * when a write to a variable screens off any preceding values that were in
694 fs_inst::is_partial_write() const
696 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
697 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
698 !this->dst
.is_contiguous() ||
699 this->dst
.subreg_offset
> 0);
703 fs_inst::components_read(unsigned i
) const
706 case FS_OPCODE_LINTERP
:
712 case FS_OPCODE_PIXEL_X
:
713 case FS_OPCODE_PIXEL_Y
:
717 case FS_OPCODE_FB_WRITE_LOGICAL
:
718 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
719 /* First/second FB write color. */
721 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
725 case SHADER_OPCODE_TEX_LOGICAL
:
726 case SHADER_OPCODE_TXD_LOGICAL
:
727 case SHADER_OPCODE_TXF_LOGICAL
:
728 case SHADER_OPCODE_TXL_LOGICAL
:
729 case SHADER_OPCODE_TXS_LOGICAL
:
730 case FS_OPCODE_TXB_LOGICAL
:
731 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
732 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
733 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
734 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
735 case SHADER_OPCODE_LOD_LOGICAL
:
736 case SHADER_OPCODE_TG4_LOGICAL
:
737 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
738 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
739 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
740 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
741 /* Texture coordinates. */
742 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
743 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
744 /* Texture derivatives. */
745 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
746 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
747 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
748 /* Texture offset. */
749 else if (i
== TEX_LOGICAL_SRC_OFFSET_VALUE
)
752 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
757 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
758 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
759 assert(src
[3].file
== IMM
);
760 /* Surface coordinates. */
763 /* Surface operation source (ignored for reads). */
769 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
770 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
771 assert(src
[3].file
== IMM
&&
773 /* Surface coordinates. */
776 /* Surface operation source. */
782 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
783 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
784 assert(src
[3].file
== IMM
&&
786 const unsigned op
= src
[4].ud
;
787 /* Surface coordinates. */
790 /* Surface operation source. */
791 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
793 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
794 op
== BRW_AOP_PREDEC
))
806 fs_inst::regs_read(int arg
) const
809 case FS_OPCODE_FB_WRITE
:
810 case SHADER_OPCODE_URB_WRITE_SIMD8
:
811 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
812 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
813 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
814 case SHADER_OPCODE_URB_READ_SIMD8
:
815 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
816 case SHADER_OPCODE_UNTYPED_ATOMIC
:
817 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
818 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
819 case SHADER_OPCODE_TYPED_ATOMIC
:
820 case SHADER_OPCODE_TYPED_SURFACE_READ
:
821 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
822 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
827 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
828 /* The payload is actually stored in src1 */
833 case FS_OPCODE_LINTERP
:
838 case SHADER_OPCODE_LOAD_PAYLOAD
:
839 if (arg
< this->header_size
)
843 case CS_OPCODE_CS_TERMINATE
:
844 case SHADER_OPCODE_BARRIER
:
847 case SHADER_OPCODE_MOV_INDIRECT
:
849 assert(src
[2].file
== IMM
);
850 unsigned region_length
= src
[2].ud
;
852 if (src
[0].file
== UNIFORM
) {
853 assert(region_length
% 4 == 0);
854 return region_length
/ 4;
855 } else if (src
[0].file
== FIXED_GRF
) {
856 /* If the start of the region is not register aligned, then
857 * there's some portion of the register that's technically
858 * unread at the beginning.
860 * However, the register allocator works in terms of whole
861 * registers, and does not use subnr. It assumes that the
862 * read starts at the beginning of the register, and extends
863 * regs_read() whole registers beyond that.
865 * To compensate, we extend the region length to include this
866 * unread portion at the beginning.
869 region_length
+= src
[0].subnr
;
871 return DIV_ROUND_UP(region_length
, REG_SIZE
);
873 assert(!"Invalid register file");
879 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
884 switch (src
[arg
].file
) {
894 return DIV_ROUND_UP(components_read(arg
) *
895 src
[arg
].component_size(exec_size
),
898 unreachable("MRF registers are not allowed as sources");
904 /* Return the subset of flag registers that an instruction could
905 * potentially read or write based on the execution controls and flag
906 * subregister number of the instruction.
909 flag_mask(const fs_inst
*inst
)
911 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
912 const unsigned end
= start
+ inst
->exec_size
;
913 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
918 fs_inst::flags_read(const brw_device_info
*devinfo
) const
920 /* XXX - This doesn't consider explicit uses of the flag register as source
923 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
924 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
925 /* The vertical predication modes combine corresponding bits from
926 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
928 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
929 return flag_mask(this) << shift
| flag_mask(this);
930 } else if (predicate
) {
931 return flag_mask(this);
938 fs_inst::flags_written() const
940 /* XXX - This doesn't consider explicit uses of the flag register as
941 * destination region.
943 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
944 opcode
!= BRW_OPCODE_IF
&&
945 opcode
!= BRW_OPCODE_WHILE
)) ||
946 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
947 return flag_mask(this);
954 * Returns how many MRFs an FS opcode will write over.
956 * Note that this is not the 0 or 1 implied writes in an actual gen
957 * instruction -- the FS opcodes often generate MOVs in addition.
960 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
965 if (inst
->base_mrf
== -1)
968 switch (inst
->opcode
) {
969 case SHADER_OPCODE_RCP
:
970 case SHADER_OPCODE_RSQ
:
971 case SHADER_OPCODE_SQRT
:
972 case SHADER_OPCODE_EXP2
:
973 case SHADER_OPCODE_LOG2
:
974 case SHADER_OPCODE_SIN
:
975 case SHADER_OPCODE_COS
:
976 return 1 * dispatch_width
/ 8;
977 case SHADER_OPCODE_POW
:
978 case SHADER_OPCODE_INT_QUOTIENT
:
979 case SHADER_OPCODE_INT_REMAINDER
:
980 return 2 * dispatch_width
/ 8;
981 case SHADER_OPCODE_TEX
:
983 case SHADER_OPCODE_TXD
:
984 case SHADER_OPCODE_TXF
:
985 case SHADER_OPCODE_TXF_CMS
:
986 case SHADER_OPCODE_TXF_MCS
:
987 case SHADER_OPCODE_TG4
:
988 case SHADER_OPCODE_TG4_OFFSET
:
989 case SHADER_OPCODE_TXL
:
990 case SHADER_OPCODE_TXS
:
991 case SHADER_OPCODE_LOD
:
992 case SHADER_OPCODE_SAMPLEINFO
:
994 case FS_OPCODE_FB_WRITE
:
996 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
997 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
999 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1001 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1004 unreachable("not reached");
1009 fs_visitor::vgrf(const glsl_type
*const type
)
1011 int reg_width
= dispatch_width
/ 8;
1012 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
1013 brw_type_for_base_type(type
));
1016 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1021 this->type
= BRW_REGISTER_TYPE_F
;
1022 this->stride
= (file
== UNIFORM
? 0 : 1);
1025 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1031 this->stride
= (file
== UNIFORM
? 0 : 1);
1034 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1035 * This brings in those uniform definitions
1038 fs_visitor::import_uniforms(fs_visitor
*v
)
1040 this->push_constant_loc
= v
->push_constant_loc
;
1041 this->pull_constant_loc
= v
->pull_constant_loc
;
1042 this->uniforms
= v
->uniforms
;
1046 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1048 assert(stage
== MESA_SHADER_FRAGMENT
);
1050 /* gl_FragCoord.x */
1051 bld
.MOV(wpos
, this->pixel_x
);
1052 wpos
= offset(wpos
, bld
, 1);
1054 /* gl_FragCoord.y */
1055 bld
.MOV(wpos
, this->pixel_y
);
1056 wpos
= offset(wpos
, bld
, 1);
1058 /* gl_FragCoord.z */
1059 if (devinfo
->gen
>= 6) {
1060 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1062 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1063 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1064 interp_reg(VARYING_SLOT_POS
, 2));
1066 wpos
= offset(wpos
, bld
, 1);
1068 /* gl_FragCoord.w: Already set up in emit_interpolation */
1069 bld
.MOV(wpos
, this->wpos_w
);
1072 enum brw_barycentric_mode
1073 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1075 /* Barycentric modes don't make sense for flat inputs. */
1076 assert(mode
!= INTERP_MODE_FLAT
);
1080 case nir_intrinsic_load_barycentric_pixel
:
1081 case nir_intrinsic_load_barycentric_at_offset
:
1082 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1084 case nir_intrinsic_load_barycentric_centroid
:
1085 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1087 case nir_intrinsic_load_barycentric_sample
:
1088 case nir_intrinsic_load_barycentric_at_sample
:
1089 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1092 unreachable("invalid intrinsic");
1095 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1098 return (enum brw_barycentric_mode
) bary
;
1102 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1104 static enum brw_barycentric_mode
1105 centroid_to_pixel(enum brw_barycentric_mode bary
)
1107 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1108 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1109 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1113 fs_visitor::emit_frontfacing_interpolation()
1115 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1117 if (devinfo
->gen
>= 6) {
1118 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1119 * a boolean result from this (~0/true or 0/false).
1121 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1122 * this task in only one instruction:
1123 * - a negation source modifier will flip the bit; and
1124 * - a W -> D type conversion will sign extend the bit into the high
1125 * word of the destination.
1127 * An ASR 15 fills the low word of the destination.
1129 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1132 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1134 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1135 * a boolean result from this (1/true or 0/false).
1137 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1138 * the negation source modifier to flip it. Unfortunately the SHR
1139 * instruction only operates on UD (or D with an abs source modifier)
1140 * sources without negation.
1142 * Instead, use ASR (which will give ~0/true or 0/false).
1144 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1147 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1154 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1156 assert(stage
== MESA_SHADER_FRAGMENT
);
1157 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1158 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1160 if (wm_prog_data
->persample_dispatch
) {
1161 /* Convert int_sample_pos to floating point */
1162 bld
.MOV(dst
, int_sample_pos
);
1163 /* Scale to the range [0, 1] */
1164 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1167 /* From ARB_sample_shading specification:
1168 * "When rendering to a non-multisample buffer, or if multisample
1169 * rasterization is disabled, gl_SamplePosition will always be
1172 bld
.MOV(dst
, brw_imm_f(0.5f
));
1177 fs_visitor::emit_samplepos_setup()
1179 assert(devinfo
->gen
>= 6);
1181 const fs_builder abld
= bld
.annotate("compute sample position");
1182 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1184 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1185 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1187 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1188 * mode will be enabled.
1190 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1191 * R31.1:0 Position Offset X/Y for Slot[3:0]
1192 * R31.3:2 Position Offset X/Y for Slot[7:4]
1195 * The X, Y sample positions come in as bytes in thread payload. So, read
1196 * the positions using vstride=16, width=8, hstride=2.
1198 struct brw_reg sample_pos_reg
=
1199 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1200 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1202 if (dispatch_width
== 8) {
1203 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1205 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1206 abld
.half(1).MOV(half(int_sample_x
, 1),
1207 fs_reg(suboffset(sample_pos_reg
, 16)));
1209 /* Compute gl_SamplePosition.x */
1210 compute_sample_position(pos
, int_sample_x
);
1211 pos
= offset(pos
, abld
, 1);
1212 if (dispatch_width
== 8) {
1213 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1215 abld
.half(0).MOV(half(int_sample_y
, 0),
1216 fs_reg(suboffset(sample_pos_reg
, 1)));
1217 abld
.half(1).MOV(half(int_sample_y
, 1),
1218 fs_reg(suboffset(sample_pos_reg
, 17)));
1220 /* Compute gl_SamplePosition.y */
1221 compute_sample_position(pos
, int_sample_y
);
1226 fs_visitor::emit_sampleid_setup()
1228 assert(stage
== MESA_SHADER_FRAGMENT
);
1229 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1230 assert(devinfo
->gen
>= 6);
1232 const fs_builder abld
= bld
.annotate("compute sample id");
1233 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1235 if (!key
->multisample_fbo
) {
1236 /* As per GL_ARB_sample_shading specification:
1237 * "When rendering to a non-multisample buffer, or if multisample
1238 * rasterization is disabled, gl_SampleID will always be zero."
1240 abld
.MOV(*reg
, brw_imm_d(0));
1241 } else if (devinfo
->gen
>= 8) {
1242 /* Sample ID comes in as 4-bit numbers in g1.0:
1244 * 15:12 Slot 3 SampleID (only used in SIMD16)
1245 * 11:8 Slot 2 SampleID (only used in SIMD16)
1246 * 7:4 Slot 1 SampleID
1247 * 3:0 Slot 0 SampleID
1249 * Each slot corresponds to four channels, so we want to replicate each
1250 * half-byte value to 4 channels in a row:
1252 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1253 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1255 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1256 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1258 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1259 * channels to read the first byte (7:0), and the second group of 8
1260 * channels to read the second byte (15:8). Then, we shift right by
1261 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1262 * values into place. Finally, we AND with 0xf to keep the low nibble.
1264 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1265 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1267 * TODO: These payload bits exist on Gen7 too, but they appear to always
1268 * be zero, so this code fails to work. We should find out why.
1270 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1272 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1273 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1274 brw_imm_v(0x44440000));
1275 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1277 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1279 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1281 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1282 * 8x multisampling, subspan 0 will represent sample N (where N
1283 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1284 * 7. We can find the value of N by looking at R0.0 bits 7:6
1285 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1286 * (since samples are always delivered in pairs). That is, we
1287 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1288 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1289 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1290 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1291 * populating a temporary variable with the sequence (0, 1, 2, 3),
1292 * and then reading from it using vstride=1, width=4, hstride=0.
1293 * These computations hold good for 4x multisampling as well.
1295 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1296 * the first four slots are sample 0 of subspan 0; the next four
1297 * are sample 1 of subspan 0; the third group is sample 0 of
1298 * subspan 1, and finally sample 1 of subspan 1.
1301 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1302 * accomodate 16x MSAA.
1304 abld
.exec_all().group(1, 0)
1305 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1307 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1309 /* This works for both SIMD8 and SIMD16 */
1310 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1312 /* This special instruction takes care of setting vstride=1,
1313 * width=4, hstride=0 of t2 during an ADD instruction.
1315 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1322 fs_visitor::emit_samplemaskin_setup()
1324 assert(stage
== MESA_SHADER_FRAGMENT
);
1325 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1326 assert(devinfo
->gen
>= 6);
1328 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1330 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1331 BRW_REGISTER_TYPE_D
));
1333 if (wm_prog_data
->persample_dispatch
) {
1334 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1335 * and a mask representing which sample is being processed by the
1336 * current shader invocation.
1338 * From the OES_sample_variables specification:
1339 * "When per-sample shading is active due to the use of a fragment input
1340 * qualified by "sample" or due to the use of the gl_SampleID or
1341 * gl_SamplePosition variables, only the bit for the current sample is
1342 * set in gl_SampleMaskIn."
1344 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1346 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1347 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1349 fs_reg one
= vgrf(glsl_type::int_type
);
1350 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1351 abld
.MOV(one
, brw_imm_d(1));
1352 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1353 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1355 /* In per-pixel mode, the coverage mask is sufficient. */
1356 *reg
= coverage_mask
;
1362 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1364 if (!src
.abs
&& !src
.negate
)
1367 fs_reg temp
= bld
.vgrf(src
.type
);
1374 fs_visitor::emit_discard_jump()
1376 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1378 /* For performance, after a discard, jump to the end of the
1379 * shader if all relevant channels have been discarded.
1381 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1382 discard_jump
->flag_subreg
= 1;
1384 discard_jump
->predicate
= (dispatch_width
== 8)
1385 ? BRW_PREDICATE_ALIGN1_ANY8H
1386 : BRW_PREDICATE_ALIGN1_ANY16H
;
1387 discard_jump
->predicate_inverse
= true;
1391 fs_visitor::emit_gs_thread_end()
1393 assert(stage
== MESA_SHADER_GEOMETRY
);
1395 struct brw_gs_prog_data
*gs_prog_data
=
1396 (struct brw_gs_prog_data
*) prog_data
;
1398 if (gs_compile
->control_data_header_size_bits
> 0) {
1399 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1402 const fs_builder abld
= bld
.annotate("thread end");
1405 if (gs_prog_data
->static_vertex_count
!= -1) {
1406 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1407 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1408 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1409 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1410 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1413 /* Delete now dead instructions. */
1414 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1420 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1424 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1425 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1426 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1429 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1430 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1431 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1432 sources
[1] = this->final_gs_vertex_count
;
1433 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1434 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1442 fs_visitor::assign_curb_setup()
1444 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1446 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1447 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1448 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1449 if (inst
->src
[i
].file
== UNIFORM
) {
1450 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1452 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1453 constant_nr
= push_constant_loc
[uniform_nr
];
1455 /* Section 5.11 of the OpenGL 4.1 spec says:
1456 * "Out-of-bounds reads return undefined values, which include
1457 * values from other variables of the active program or zero."
1458 * Just return the first push constant.
1463 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1466 brw_reg
.abs
= inst
->src
[i
].abs
;
1467 brw_reg
.negate
= inst
->src
[i
].negate
;
1469 assert(inst
->src
[i
].stride
== 0);
1470 inst
->src
[i
] = byte_offset(
1471 retype(brw_reg
, inst
->src
[i
].type
),
1472 inst
->src
[i
].subreg_offset
);
1477 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1478 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1482 fs_visitor::calculate_urb_setup()
1484 assert(stage
== MESA_SHADER_FRAGMENT
);
1485 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1486 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1488 memset(prog_data
->urb_setup
, -1,
1489 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1492 /* Figure out where each of the incoming setup attributes lands. */
1493 if (devinfo
->gen
>= 6) {
1494 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1495 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1496 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1497 * first 16 varying inputs, so we can put them wherever we want.
1498 * Just put them in order.
1500 * This is useful because it means that (a) inputs not used by the
1501 * fragment shader won't take up valuable register space, and (b) we
1502 * won't have to recompile the fragment shader if it gets paired with
1503 * a different vertex (or geometry) shader.
1505 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1506 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1507 BITFIELD64_BIT(i
)) {
1508 prog_data
->urb_setup
[i
] = urb_next
++;
1512 bool include_vue_header
=
1513 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1515 /* We have enough input varyings that the SF/SBE pipeline stage can't
1516 * arbitrarily rearrange them to suit our whim; we have to put them
1517 * in an order that matches the output of the previous pipeline stage
1518 * (geometry or vertex shader).
1520 struct brw_vue_map prev_stage_vue_map
;
1521 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1522 key
->input_slots_valid
,
1523 nir
->info
.separate_shader
);
1525 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1527 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1528 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1530 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1531 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1532 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1533 BITFIELD64_BIT(varying
))) {
1534 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1537 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1540 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1541 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1542 /* Point size is packed into the header, not as a general attribute */
1543 if (i
== VARYING_SLOT_PSIZ
)
1546 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1547 /* The back color slot is skipped when the front color is
1548 * also written to. In addition, some slots can be
1549 * written in the vertex shader and not read in the
1550 * fragment shader. So the register number must always be
1551 * incremented, mapped or not.
1553 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1554 prog_data
->urb_setup
[i
] = urb_next
;
1560 * It's a FS only attribute, and we did interpolation for this attribute
1561 * in SF thread. So, count it here, too.
1563 * See compile_sf_prog() for more info.
1565 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1566 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1569 prog_data
->num_varying_inputs
= urb_next
;
1573 fs_visitor::assign_urb_setup()
1575 assert(stage
== MESA_SHADER_FRAGMENT
);
1576 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1578 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1580 /* Offset all the urb_setup[] index by the actual position of the
1581 * setup regs, now that the location of the constants has been chosen.
1583 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1584 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1585 assert(inst
->src
[1].file
== FIXED_GRF
);
1586 inst
->src
[1].nr
+= urb_start
;
1589 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1590 assert(inst
->src
[0].file
== FIXED_GRF
);
1591 inst
->src
[0].nr
+= urb_start
;
1595 /* Each attribute is 4 setup channels, each of which is half a reg. */
1596 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1600 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1602 for (int i
= 0; i
< inst
->sources
; i
++) {
1603 if (inst
->src
[i
].file
== ATTR
) {
1604 int grf
= payload
.num_regs
+
1605 prog_data
->curb_read_length
+
1607 inst
->src
[i
].reg_offset
;
1609 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1611 * VertStride must be used to cross GRF register boundaries. This
1612 * rule implies that elements within a 'Width' cannot cross GRF
1615 * So, for registers that are large enough, we have to split the exec
1616 * size in two and trust the compression state to sort it out.
1618 unsigned total_size
= inst
->exec_size
*
1619 inst
->src
[i
].stride
*
1620 type_sz(inst
->src
[i
].type
);
1622 assert(total_size
<= 2 * REG_SIZE
);
1623 const unsigned exec_size
=
1624 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1626 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1627 struct brw_reg reg
=
1628 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1629 inst
->src
[i
].subreg_offset
),
1630 exec_size
* inst
->src
[i
].stride
,
1631 width
, inst
->src
[i
].stride
);
1632 reg
.abs
= inst
->src
[i
].abs
;
1633 reg
.negate
= inst
->src
[i
].negate
;
1641 fs_visitor::assign_vs_urb_setup()
1643 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1645 assert(stage
== MESA_SHADER_VERTEX
);
1647 /* Each attribute is 4 regs. */
1648 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1650 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1652 /* Rewrite all ATTR file references to the hw grf that they land in. */
1653 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1654 convert_attr_sources_to_hw_regs(inst
);
1659 fs_visitor::assign_tcs_single_patch_urb_setup()
1661 assert(stage
== MESA_SHADER_TESS_CTRL
);
1663 /* Rewrite all ATTR file references to HW_REGs. */
1664 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1665 convert_attr_sources_to_hw_regs(inst
);
1670 fs_visitor::assign_tes_urb_setup()
1672 assert(stage
== MESA_SHADER_TESS_EVAL
);
1674 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1676 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1678 /* Rewrite all ATTR file references to HW_REGs. */
1679 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1680 convert_attr_sources_to_hw_regs(inst
);
1685 fs_visitor::assign_gs_urb_setup()
1687 assert(stage
== MESA_SHADER_GEOMETRY
);
1689 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1691 first_non_payload_grf
+=
1692 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1694 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1695 /* Rewrite all ATTR file references to GRFs. */
1696 convert_attr_sources_to_hw_regs(inst
);
1702 * Split large virtual GRFs into separate components if we can.
1704 * This is mostly duplicated with what brw_fs_vector_splitting does,
1705 * but that's really conservative because it's afraid of doing
1706 * splitting that doesn't result in real progress after the rest of
1707 * the optimization phases, which would cause infinite looping in
1708 * optimization. We can do it once here, safely. This also has the
1709 * opportunity to split interpolated values, or maybe even uniforms,
1710 * which we don't have at the IR level.
1712 * We want to split, because virtual GRFs are what we register
1713 * allocate and spill (due to contiguousness requirements for some
1714 * instructions), and they're what we naturally generate in the
1715 * codegen process, but most virtual GRFs don't actually need to be
1716 * contiguous sets of GRFs. If we split, we'll end up with reduced
1717 * live intervals and better dead code elimination and coalescing.
1720 fs_visitor::split_virtual_grfs()
1722 int num_vars
= this->alloc
.count
;
1724 /* Count the total number of registers */
1726 int vgrf_to_reg
[num_vars
];
1727 for (int i
= 0; i
< num_vars
; i
++) {
1728 vgrf_to_reg
[i
] = reg_count
;
1729 reg_count
+= alloc
.sizes
[i
];
1732 /* An array of "split points". For each register slot, this indicates
1733 * if this slot can be separated from the previous slot. Every time an
1734 * instruction uses multiple elements of a register (as a source or
1735 * destination), we mark the used slots as inseparable. Then we go
1736 * through and split the registers into the smallest pieces we can.
1738 bool split_points
[reg_count
];
1739 memset(split_points
, 0, sizeof(split_points
));
1741 /* Mark all used registers as fully splittable */
1742 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1743 if (inst
->dst
.file
== VGRF
) {
1744 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1745 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1746 split_points
[reg
+ j
] = true;
1749 for (int i
= 0; i
< inst
->sources
; i
++) {
1750 if (inst
->src
[i
].file
== VGRF
) {
1751 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1752 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1753 split_points
[reg
+ j
] = true;
1758 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1759 if (inst
->dst
.file
== VGRF
) {
1760 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1761 for (int j
= 1; j
< inst
->regs_written
; j
++)
1762 split_points
[reg
+ j
] = false;
1764 for (int i
= 0; i
< inst
->sources
; i
++) {
1765 if (inst
->src
[i
].file
== VGRF
) {
1766 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1767 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1768 split_points
[reg
+ j
] = false;
1773 int new_virtual_grf
[reg_count
];
1774 int new_reg_offset
[reg_count
];
1777 for (int i
= 0; i
< num_vars
; i
++) {
1778 /* The first one should always be 0 as a quick sanity check. */
1779 assert(split_points
[reg
] == false);
1782 new_reg_offset
[reg
] = 0;
1787 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1788 /* If this is a split point, reset the offset to 0 and allocate a
1789 * new virtual GRF for the previous offset many registers
1791 if (split_points
[reg
]) {
1792 assert(offset
<= MAX_VGRF_SIZE
);
1793 int grf
= alloc
.allocate(offset
);
1794 for (int k
= reg
- offset
; k
< reg
; k
++)
1795 new_virtual_grf
[k
] = grf
;
1798 new_reg_offset
[reg
] = offset
;
1803 /* The last one gets the original register number */
1804 assert(offset
<= MAX_VGRF_SIZE
);
1805 alloc
.sizes
[i
] = offset
;
1806 for (int k
= reg
- offset
; k
< reg
; k
++)
1807 new_virtual_grf
[k
] = i
;
1809 assert(reg
== reg_count
);
1811 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1812 if (inst
->dst
.file
== VGRF
) {
1813 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1814 inst
->dst
.nr
= new_virtual_grf
[reg
];
1815 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1816 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1818 for (int i
= 0; i
< inst
->sources
; i
++) {
1819 if (inst
->src
[i
].file
== VGRF
) {
1820 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1821 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1822 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1823 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1827 invalidate_live_intervals();
1831 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1833 * During code generation, we create tons of temporary variables, many of
1834 * which get immediately killed and are never used again. Yet, in later
1835 * optimization and analysis passes, such as compute_live_intervals, we need
1836 * to loop over all the virtual GRFs. Compacting them can save a lot of
1840 fs_visitor::compact_virtual_grfs()
1842 bool progress
= false;
1843 int remap_table
[this->alloc
.count
];
1844 memset(remap_table
, -1, sizeof(remap_table
));
1846 /* Mark which virtual GRFs are used. */
1847 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1848 if (inst
->dst
.file
== VGRF
)
1849 remap_table
[inst
->dst
.nr
] = 0;
1851 for (int i
= 0; i
< inst
->sources
; i
++) {
1852 if (inst
->src
[i
].file
== VGRF
)
1853 remap_table
[inst
->src
[i
].nr
] = 0;
1857 /* Compact the GRF arrays. */
1859 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1860 if (remap_table
[i
] == -1) {
1861 /* We just found an unused register. This means that we are
1862 * actually going to compact something.
1866 remap_table
[i
] = new_index
;
1867 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1868 invalidate_live_intervals();
1873 this->alloc
.count
= new_index
;
1875 /* Patch all the instructions to use the newly renumbered registers */
1876 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1877 if (inst
->dst
.file
== VGRF
)
1878 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1880 for (int i
= 0; i
< inst
->sources
; i
++) {
1881 if (inst
->src
[i
].file
== VGRF
)
1882 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1886 /* Patch all the references to delta_xy, since they're used in register
1887 * allocation. If they're unused, switch them to BAD_FILE so we don't
1888 * think some random VGRF is delta_xy.
1890 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1891 if (delta_xy
[i
].file
== VGRF
) {
1892 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1893 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1895 delta_xy
[i
].file
= BAD_FILE
;
1904 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
, bool contiguous
,
1905 int *push_constant_loc
, int *pull_constant_loc
,
1906 unsigned *num_push_constants
,
1907 unsigned *num_pull_constants
,
1908 const unsigned max_push_components
,
1909 const unsigned max_chunk_size
,
1910 struct brw_stage_prog_data
*stage_prog_data
)
1912 /* This is the first live uniform in the chunk */
1913 if (*chunk_start
< 0)
1914 *chunk_start
= uniform
;
1916 /* If this element does not need to be contiguous with the next, we
1917 * split at this point and everything between chunk_start and u forms a
1921 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
1923 /* Decide whether we should push or pull this parameter. In the
1924 * Vulkan driver, push constants are explicitly exposed via the API
1925 * so we push everything. In GL, we only push small arrays.
1927 if (stage_prog_data
->pull_param
== NULL
||
1928 (*num_push_constants
+ chunk_size
<= max_push_components
&&
1929 chunk_size
<= max_chunk_size
)) {
1930 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
1931 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1932 push_constant_loc
[j
] = (*num_push_constants
)++;
1934 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1935 pull_constant_loc
[j
] = (*num_pull_constants
)++;
1943 * Assign UNIFORM file registers to either push constants or pull constants.
1945 * We allow a fragment shader to have more than the specified minimum
1946 * maximum number of fragment shader uniform components (64). If
1947 * there are too many of these, they'd fill up all of register space.
1948 * So, this will push some of them out to the pull constant buffer and
1949 * update the program to load them.
1952 fs_visitor::assign_constant_locations()
1954 /* Only the first compile gets to decide on locations. */
1955 if (dispatch_width
!= min_dispatch_width
)
1958 bool is_live
[uniforms
];
1959 memset(is_live
, 0, sizeof(is_live
));
1960 bool is_live_64bit
[uniforms
];
1961 memset(is_live_64bit
, 0, sizeof(is_live_64bit
));
1963 /* For each uniform slot, a value of true indicates that the given slot and
1964 * the next slot must remain contiguous. This is used to keep us from
1965 * splitting arrays apart.
1967 bool contiguous
[uniforms
];
1968 memset(contiguous
, 0, sizeof(contiguous
));
1970 int thread_local_id_index
=
1971 (stage
== MESA_SHADER_COMPUTE
) ?
1972 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
: -1;
1974 /* First, we walk through the instructions and do two things:
1976 * 1) Figure out which uniforms are live.
1978 * 2) Mark any indirectly used ranges of registers as contiguous.
1980 * Note that we don't move constant-indexed accesses to arrays. No
1981 * testing has been done of the performance impact of this choice.
1983 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1984 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1985 if (inst
->src
[i
].file
!= UNIFORM
)
1988 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1990 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
1991 assert(inst
->src
[2].ud
% 4 == 0);
1992 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
1993 assert(last
< uniforms
);
1995 for (unsigned j
= constant_nr
; j
< last
; j
++) {
1997 contiguous
[j
] = true;
1998 if (type_sz(inst
->src
[i
].type
) == 8) {
1999 is_live_64bit
[j
] = true;
2002 is_live
[last
] = true;
2004 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
2005 int regs_read
= inst
->components_read(i
) *
2006 type_sz(inst
->src
[i
].type
) / 4;
2007 for (int j
= 0; j
< regs_read
; j
++) {
2008 is_live
[constant_nr
+ j
] = true;
2009 if (type_sz(inst
->src
[i
].type
) == 8) {
2010 is_live_64bit
[constant_nr
+ j
] = true;
2018 if (thread_local_id_index
>= 0 && !is_live
[thread_local_id_index
])
2019 thread_local_id_index
= -1;
2021 /* Only allow 16 registers (128 uniform components) as push constants.
2023 * Just demote the end of the list. We could probably do better
2024 * here, demoting things that are rarely used in the program first.
2026 * If changing this value, note the limitation about total_regs in
2029 unsigned int max_push_components
= 16 * 8;
2030 if (thread_local_id_index
>= 0)
2031 max_push_components
--; /* Save a slot for the thread ID */
2033 /* We push small arrays, but no bigger than 16 floats. This is big enough
2034 * for a vec4 but hopefully not large enough to push out other stuff. We
2035 * should probably use a better heuristic at some point.
2037 const unsigned int max_chunk_size
= 16;
2039 unsigned int num_push_constants
= 0;
2040 unsigned int num_pull_constants
= 0;
2042 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2043 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2045 /* Default to -1 meaning no location */
2046 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2047 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2049 int chunk_start
= -1;
2051 /* First push 64-bit uniforms to ensure they are properly aligned */
2052 for (unsigned u
= 0; u
< uniforms
; u
++) {
2053 if (!is_live
[u
] || !is_live_64bit
[u
])
2056 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2057 push_constant_loc
, pull_constant_loc
,
2058 &num_push_constants
, &num_pull_constants
,
2059 max_push_components
, max_chunk_size
,
2064 /* Then push the rest of uniforms */
2065 for (unsigned u
= 0; u
< uniforms
; u
++) {
2066 if (!is_live
[u
] || is_live_64bit
[u
])
2069 /* Skip thread_local_id_index to put it in the last push register. */
2070 if (thread_local_id_index
== (int)u
)
2073 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2074 push_constant_loc
, pull_constant_loc
,
2075 &num_push_constants
, &num_pull_constants
,
2076 max_push_components
, max_chunk_size
,
2080 /* Add the CS local thread ID uniform at the end of the push constants */
2081 if (thread_local_id_index
>= 0)
2082 push_constant_loc
[thread_local_id_index
] = num_push_constants
++;
2084 /* As the uniforms are going to be reordered, take the data from a temporary
2085 * copy of the original param[].
2087 gl_constant_value
**param
= ralloc_array(NULL
, gl_constant_value
*,
2088 stage_prog_data
->nr_params
);
2089 memcpy(param
, stage_prog_data
->param
,
2090 sizeof(gl_constant_value
*) * stage_prog_data
->nr_params
);
2091 stage_prog_data
->nr_params
= num_push_constants
;
2092 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2094 /* Up until now, the param[] array has been indexed by reg + reg_offset
2095 * of UNIFORM registers. Move pull constants into pull_param[] and
2096 * condense param[] to only contain the uniforms we chose to push.
2098 * NOTE: Because we are condensing the params[] array, we know that
2099 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2100 * having to make a copy.
2102 int new_thread_local_id_index
= -1;
2103 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2104 const gl_constant_value
*value
= param
[i
];
2106 if (pull_constant_loc
[i
] != -1) {
2107 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2108 } else if (push_constant_loc
[i
] != -1) {
2109 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2110 if (thread_local_id_index
== (int)i
)
2111 new_thread_local_id_index
= push_constant_loc
[i
];
2116 if (stage
== MESA_SHADER_COMPUTE
)
2117 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
=
2118 new_thread_local_id_index
;
2122 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2123 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2126 fs_visitor::lower_constant_loads()
2128 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2130 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2131 /* Set up the annotation tracking for new generated instructions. */
2132 const fs_builder
ibld(this, block
, inst
);
2134 for (int i
= 0; i
< inst
->sources
; i
++) {
2135 if (inst
->src
[i
].file
!= UNIFORM
)
2138 /* We'll handle this case later */
2139 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2142 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2143 if (location
>= uniforms
)
2144 continue; /* Out of bounds access */
2146 int pull_index
= pull_constant_loc
[location
];
2148 if (pull_index
== -1)
2151 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2154 if (type_sz(inst
->src
[i
].type
) <= 4)
2155 dst
= vgrf(glsl_type::float_type
);
2157 dst
= vgrf(glsl_type::double_type
);
2159 assert(inst
->src
[i
].stride
== 0);
2161 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2162 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2163 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2164 dst
, brw_imm_ud(index
), offset
);
2166 /* Rewrite the instruction to use the temporary VGRF. */
2167 inst
->src
[i
].file
= VGRF
;
2168 inst
->src
[i
].nr
= dst
.nr
;
2169 inst
->src
[i
].reg_offset
= 0;
2170 inst
->src
[i
].set_smear((pull_index
& 3) * 4 /
2171 type_sz(inst
->src
[i
].type
));
2173 brw_mark_surface_used(prog_data
, index
);
2176 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2177 inst
->src
[0].file
== UNIFORM
) {
2179 unsigned location
= inst
->src
[0].nr
+ inst
->src
[0].reg_offset
;
2180 if (location
>= uniforms
)
2181 continue; /* Out of bounds access */
2183 int pull_index
= pull_constant_loc
[location
];
2185 if (pull_index
== -1)
2188 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2192 inst
->remove(block
);
2194 brw_mark_surface_used(prog_data
, index
);
2197 invalidate_live_intervals();
2201 fs_visitor::opt_algebraic()
2203 bool progress
= false;
2205 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2206 switch (inst
->opcode
) {
2207 case BRW_OPCODE_MOV
:
2208 if (inst
->src
[0].file
!= IMM
)
2211 if (inst
->saturate
) {
2212 if (inst
->dst
.type
!= inst
->src
[0].type
)
2213 assert(!"unimplemented: saturate mixed types");
2215 if (brw_saturate_immediate(inst
->dst
.type
,
2216 &inst
->src
[0].as_brw_reg())) {
2217 inst
->saturate
= false;
2223 case BRW_OPCODE_MUL
:
2224 if (inst
->src
[1].file
!= IMM
)
2228 if (inst
->src
[1].is_one()) {
2229 inst
->opcode
= BRW_OPCODE_MOV
;
2230 inst
->src
[1] = reg_undef
;
2236 if (inst
->src
[1].is_negative_one()) {
2237 inst
->opcode
= BRW_OPCODE_MOV
;
2238 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2239 inst
->src
[1] = reg_undef
;
2245 if (inst
->src
[1].is_zero()) {
2246 inst
->opcode
= BRW_OPCODE_MOV
;
2247 inst
->src
[0] = inst
->src
[1];
2248 inst
->src
[1] = reg_undef
;
2253 if (inst
->src
[0].file
== IMM
) {
2254 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2255 inst
->opcode
= BRW_OPCODE_MOV
;
2256 inst
->src
[0].f
*= inst
->src
[1].f
;
2257 inst
->src
[1] = reg_undef
;
2262 case BRW_OPCODE_ADD
:
2263 if (inst
->src
[1].file
!= IMM
)
2267 if (inst
->src
[1].is_zero()) {
2268 inst
->opcode
= BRW_OPCODE_MOV
;
2269 inst
->src
[1] = reg_undef
;
2274 if (inst
->src
[0].file
== IMM
) {
2275 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2276 inst
->opcode
= BRW_OPCODE_MOV
;
2277 inst
->src
[0].f
+= inst
->src
[1].f
;
2278 inst
->src
[1] = reg_undef
;
2284 if (inst
->src
[0].equals(inst
->src
[1])) {
2285 inst
->opcode
= BRW_OPCODE_MOV
;
2286 inst
->src
[1] = reg_undef
;
2291 case BRW_OPCODE_LRP
:
2292 if (inst
->src
[1].equals(inst
->src
[2])) {
2293 inst
->opcode
= BRW_OPCODE_MOV
;
2294 inst
->src
[0] = inst
->src
[1];
2295 inst
->src
[1] = reg_undef
;
2296 inst
->src
[2] = reg_undef
;
2301 case BRW_OPCODE_CMP
:
2302 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2304 inst
->src
[0].negate
&&
2305 inst
->src
[1].is_zero()) {
2306 inst
->src
[0].abs
= false;
2307 inst
->src
[0].negate
= false;
2308 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2313 case BRW_OPCODE_SEL
:
2314 if (inst
->src
[0].equals(inst
->src
[1])) {
2315 inst
->opcode
= BRW_OPCODE_MOV
;
2316 inst
->src
[1] = reg_undef
;
2317 inst
->predicate
= BRW_PREDICATE_NONE
;
2318 inst
->predicate_inverse
= false;
2320 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2321 switch (inst
->conditional_mod
) {
2322 case BRW_CONDITIONAL_LE
:
2323 case BRW_CONDITIONAL_L
:
2324 switch (inst
->src
[1].type
) {
2325 case BRW_REGISTER_TYPE_F
:
2326 if (inst
->src
[1].f
>= 1.0f
) {
2327 inst
->opcode
= BRW_OPCODE_MOV
;
2328 inst
->src
[1] = reg_undef
;
2329 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2337 case BRW_CONDITIONAL_GE
:
2338 case BRW_CONDITIONAL_G
:
2339 switch (inst
->src
[1].type
) {
2340 case BRW_REGISTER_TYPE_F
:
2341 if (inst
->src
[1].f
<= 0.0f
) {
2342 inst
->opcode
= BRW_OPCODE_MOV
;
2343 inst
->src
[1] = reg_undef
;
2344 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2356 case BRW_OPCODE_MAD
:
2357 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2358 inst
->opcode
= BRW_OPCODE_MOV
;
2359 inst
->src
[1] = reg_undef
;
2360 inst
->src
[2] = reg_undef
;
2362 } else if (inst
->src
[0].is_zero()) {
2363 inst
->opcode
= BRW_OPCODE_MUL
;
2364 inst
->src
[0] = inst
->src
[2];
2365 inst
->src
[2] = reg_undef
;
2367 } else if (inst
->src
[1].is_one()) {
2368 inst
->opcode
= BRW_OPCODE_ADD
;
2369 inst
->src
[1] = inst
->src
[2];
2370 inst
->src
[2] = reg_undef
;
2372 } else if (inst
->src
[2].is_one()) {
2373 inst
->opcode
= BRW_OPCODE_ADD
;
2374 inst
->src
[2] = reg_undef
;
2376 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2377 inst
->opcode
= BRW_OPCODE_ADD
;
2378 inst
->src
[1].f
*= inst
->src
[2].f
;
2379 inst
->src
[2] = reg_undef
;
2383 case SHADER_OPCODE_BROADCAST
:
2384 if (is_uniform(inst
->src
[0])) {
2385 inst
->opcode
= BRW_OPCODE_MOV
;
2387 inst
->force_writemask_all
= true;
2389 } else if (inst
->src
[1].file
== IMM
) {
2390 inst
->opcode
= BRW_OPCODE_MOV
;
2391 inst
->src
[0] = component(inst
->src
[0],
2394 inst
->force_writemask_all
= true;
2403 /* Swap if src[0] is immediate. */
2404 if (progress
&& inst
->is_commutative()) {
2405 if (inst
->src
[0].file
== IMM
) {
2406 fs_reg tmp
= inst
->src
[1];
2407 inst
->src
[1] = inst
->src
[0];
2416 * Optimize sample messages that have constant zero values for the trailing
2417 * texture coordinates. We can just reduce the message length for these
2418 * instructions instead of reserving a register for it. Trailing parameters
2419 * that aren't sent default to zero anyway. This will cause the dead code
2420 * eliminator to remove the MOV instruction that would otherwise be emitted to
2421 * set up the zero value.
2424 fs_visitor::opt_zero_samples()
2426 /* Gen4 infers the texturing opcode based on the message length so we can't
2429 if (devinfo
->gen
< 5)
2432 bool progress
= false;
2434 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2435 if (!inst
->is_tex())
2438 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2440 if (load_payload
->is_head_sentinel() ||
2441 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2444 /* We don't want to remove the message header or the first parameter.
2445 * Removing the first parameter is not allowed, see the Haswell PRM
2446 * volume 7, page 149:
2448 * "Parameter 0 is required except for the sampleinfo message, which
2449 * has no parameter 0"
2451 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2452 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2453 (inst
->exec_size
/ 8) +
2454 inst
->header_size
- 1].is_zero()) {
2455 inst
->mlen
-= inst
->exec_size
/ 8;
2461 invalidate_live_intervals();
2467 * Optimize sample messages which are followed by the final RT write.
2469 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2470 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2471 * final texturing results copied to the framebuffer write payload and modify
2472 * them to write to the framebuffer directly.
2475 fs_visitor::opt_sampler_eot()
2477 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2479 if (stage
!= MESA_SHADER_FRAGMENT
)
2482 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2485 /* FINISHME: It should be possible to implement this optimization when there
2486 * are multiple drawbuffers.
2488 if (key
->nr_color_regions
!= 1)
2491 /* Requires emitting a bunch of saturating MOV instructions during logical
2492 * send lowering to clamp the color payload, which the sampler unit isn't
2493 * going to do for us.
2495 if (key
->clamp_fragment_color
)
2498 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2499 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2500 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2501 assert(fb_write
->eot
);
2502 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2504 /* There wasn't one; nothing to do. */
2505 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2508 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2510 /* 3D Sampler » Messages » Message Format
2512 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2513 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2515 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2516 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2517 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2518 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2519 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2520 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2521 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2522 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2525 /* XXX - This shouldn't be necessary. */
2526 if (tex_inst
->prev
->is_head_sentinel())
2529 /* Check that the FB write sources are fully initialized by the single
2530 * texturing instruction.
2532 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2533 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2534 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2535 fb_write
->regs_read(i
) != tex_inst
->regs_written
)
2537 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2538 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2543 assert(!tex_inst
->eot
); /* We can't get here twice */
2544 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2546 const fs_builder
ibld(this, block
, tex_inst
);
2548 tex_inst
->offset
|= fb_write
->target
<< 24;
2549 tex_inst
->eot
= true;
2550 tex_inst
->dst
= ibld
.null_reg_ud();
2551 tex_inst
->regs_written
= 0;
2552 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2554 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2555 * flag and submit a header together with the sampler message as required
2558 invalidate_live_intervals();
2563 fs_visitor::opt_register_renaming()
2565 bool progress
= false;
2568 int remap
[alloc
.count
];
2569 memset(remap
, -1, sizeof(int) * alloc
.count
);
2571 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2572 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2574 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2575 inst
->opcode
== BRW_OPCODE_WHILE
) {
2579 /* Rewrite instruction sources. */
2580 for (int i
= 0; i
< inst
->sources
; i
++) {
2581 if (inst
->src
[i
].file
== VGRF
&&
2582 remap
[inst
->src
[i
].nr
] != -1 &&
2583 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2584 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2589 const int dst
= inst
->dst
.nr
;
2592 inst
->dst
.file
== VGRF
&&
2593 alloc
.sizes
[inst
->dst
.nr
] == inst
->regs_written
&&
2594 !inst
->is_partial_write()) {
2595 if (remap
[dst
] == -1) {
2598 remap
[dst
] = alloc
.allocate(inst
->regs_written
);
2599 inst
->dst
.nr
= remap
[dst
];
2602 } else if (inst
->dst
.file
== VGRF
&&
2604 remap
[dst
] != dst
) {
2605 inst
->dst
.nr
= remap
[dst
];
2611 invalidate_live_intervals();
2613 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2614 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2615 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2624 * Remove redundant or useless discard jumps.
2626 * For example, we can eliminate jumps in the following sequence:
2628 * discard-jump (redundant with the next jump)
2629 * discard-jump (useless; jumps to the next instruction)
2633 fs_visitor::opt_redundant_discard_jumps()
2635 bool progress
= false;
2637 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2639 fs_inst
*placeholder_halt
= NULL
;
2640 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2641 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2642 placeholder_halt
= inst
;
2647 if (!placeholder_halt
)
2650 /* Delete any HALTs immediately before the placeholder halt. */
2651 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2652 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2653 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2654 prev
->remove(last_bblock
);
2659 invalidate_live_intervals();
2665 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2666 * from \p r which overlaps the region starting at \p r and spanning \p n GRF
2669 static inline unsigned
2670 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned n
)
2672 const int rel_offset
= (reg_offset(s
) - reg_offset(r
)) / REG_SIZE
;
2673 assert(reg_space(r
) == reg_space(s
) &&
2674 rel_offset
>= 0 && rel_offset
< int(8 * sizeof(unsigned)));
2675 return ((1 << n
) - 1) << rel_offset
;
2679 fs_visitor::compute_to_mrf()
2681 bool progress
= false;
2684 /* No MRFs on Gen >= 7. */
2685 if (devinfo
->gen
>= 7)
2688 calculate_live_intervals();
2690 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2694 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2695 inst
->is_partial_write() ||
2696 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2697 inst
->dst
.type
!= inst
->src
[0].type
||
2698 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2699 !inst
->src
[0].is_contiguous() ||
2700 inst
->src
[0].subreg_offset
)
2703 /* Can't compute-to-MRF this GRF if someone else was going to
2706 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2709 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2710 * things that computed the value of all GRFs of the source region. The
2711 * regs_left bitset keeps track of the registers we haven't yet found a
2712 * generating instruction for.
2714 unsigned regs_left
= (1 << inst
->regs_read(0)) - 1;
2716 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2717 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2718 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2719 /* Found the last thing to write our reg we want to turn
2720 * into a compute-to-MRF.
2723 /* If this one instruction didn't populate all the
2724 * channels, bail. We might be able to rewrite everything
2725 * that writes that reg, but it would require smarter
2728 if (scan_inst
->is_partial_write())
2731 /* Handling things not fully contained in the source of the copy
2732 * would need us to understand coalescing out more than one MOV at
2735 if (scan_inst
->dst
.reg_offset
< inst
->src
[0].reg_offset
||
2736 scan_inst
->dst
.reg_offset
+ scan_inst
->regs_written
>
2737 inst
->src
[0].reg_offset
+ inst
->regs_read(0))
2740 /* SEND instructions can't have MRF as a destination. */
2741 if (scan_inst
->mlen
)
2744 if (devinfo
->gen
== 6) {
2745 /* gen6 math instructions must have the destination be
2746 * GRF, so no compute-to-MRF for them.
2748 if (scan_inst
->is_math()) {
2753 /* Clear the bits for any registers this instruction overwrites. */
2754 regs_left
&= ~mask_relative_to(
2755 inst
->src
[0], scan_inst
->dst
, scan_inst
->regs_written
);
2760 /* We don't handle control flow here. Most computation of
2761 * values that end up in MRFs are shortly before the MRF
2764 if (block
->start() == scan_inst
)
2767 /* You can't read from an MRF, so if someone else reads our
2768 * MRF's source GRF that we wanted to rewrite, that stops us.
2770 bool interfered
= false;
2771 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2772 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->regs_read(i
) * REG_SIZE
,
2773 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2780 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2781 inst
->dst
, inst
->regs_written
* REG_SIZE
)) {
2782 /* If somebody else writes our MRF here, we can't
2783 * compute-to-MRF before that.
2788 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2789 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2790 inst
->dst
, inst
->regs_written
* REG_SIZE
)) {
2791 /* Found a SEND instruction, which means that there are
2792 * live values in MRFs from base_mrf to base_mrf +
2793 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2803 /* Found all generating instructions of our MRF's source value, so it
2804 * should be safe to rewrite them to point to the MRF directly.
2806 regs_left
= (1 << inst
->regs_read(0)) - 1;
2808 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2809 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2810 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2811 /* Clear the bits for any registers this instruction overwrites. */
2812 regs_left
&= ~mask_relative_to(
2813 inst
->src
[0], scan_inst
->dst
, scan_inst
->regs_written
);
2815 const unsigned rel_offset
= (reg_offset(scan_inst
->dst
) -
2816 reg_offset(inst
->src
[0])) / REG_SIZE
;
2818 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2819 /* Apply the same address transformation done by the hardware
2820 * for COMPR4 MRF writes.
2822 assert(rel_offset
< 2);
2823 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
* 4;
2825 /* Clear the COMPR4 bit if the generating instruction is not
2828 if (scan_inst
->regs_written
< 2)
2829 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2832 /* Calculate the MRF number the result of this instruction is
2833 * ultimately written to.
2835 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
;
2838 scan_inst
->dst
.file
= MRF
;
2839 scan_inst
->dst
.reg_offset
= 0;
2840 scan_inst
->saturate
|= inst
->saturate
;
2847 inst
->remove(block
);
2852 invalidate_live_intervals();
2858 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2859 * flow. We could probably do better here with some form of divergence
2863 fs_visitor::eliminate_find_live_channel()
2865 bool progress
= false;
2868 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2869 switch (inst
->opcode
) {
2875 case BRW_OPCODE_ENDIF
:
2876 case BRW_OPCODE_WHILE
:
2880 case FS_OPCODE_DISCARD_JUMP
:
2881 /* This can potentially make control flow non-uniform until the end
2886 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2888 inst
->opcode
= BRW_OPCODE_MOV
;
2889 inst
->src
[0] = brw_imm_ud(0u);
2891 inst
->force_writemask_all
= true;
2905 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2906 * instructions to FS_OPCODE_REP_FB_WRITE.
2909 fs_visitor::emit_repclear_shader()
2911 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2913 int color_mrf
= base_mrf
+ 2;
2917 mov
= bld
.exec_all().group(4, 0)
2918 .MOV(brw_message_reg(color_mrf
),
2919 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2921 struct brw_reg reg
=
2922 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2923 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
2924 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2926 mov
= bld
.exec_all().group(4, 0)
2927 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2931 if (key
->nr_color_regions
== 1) {
2932 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2933 write
->saturate
= key
->clamp_fragment_color
;
2934 write
->base_mrf
= color_mrf
;
2936 write
->header_size
= 0;
2939 assume(key
->nr_color_regions
> 0);
2940 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2941 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2942 write
->saturate
= key
->clamp_fragment_color
;
2943 write
->base_mrf
= base_mrf
;
2945 write
->header_size
= 2;
2953 assign_constant_locations();
2954 assign_curb_setup();
2956 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2958 assert(mov
->src
[0].file
== FIXED_GRF
);
2959 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2964 * Walks through basic blocks, looking for repeated MRF writes and
2965 * removing the later ones.
2968 fs_visitor::remove_duplicate_mrf_writes()
2970 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2971 bool progress
= false;
2973 /* Need to update the MRF tracking for compressed instructions. */
2974 if (dispatch_width
>= 16)
2977 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2979 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2980 if (inst
->is_control_flow()) {
2981 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2984 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2985 inst
->dst
.file
== MRF
) {
2986 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2987 if (prev_inst
&& inst
->equals(prev_inst
)) {
2988 inst
->remove(block
);
2994 /* Clear out the last-write records for MRFs that were overwritten. */
2995 if (inst
->dst
.file
== MRF
) {
2996 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2999 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3000 /* Found a SEND instruction, which will include two or fewer
3001 * implied MRF writes. We could do better here.
3003 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3004 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3008 /* Clear out any MRF move records whose sources got overwritten. */
3009 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3010 if (last_mrf_move
[i
] &&
3011 regions_overlap(inst
->dst
, inst
->regs_written
* REG_SIZE
,
3012 last_mrf_move
[i
]->src
[0],
3013 last_mrf_move
[i
]->regs_read(0) * REG_SIZE
)) {
3014 last_mrf_move
[i
] = NULL
;
3018 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3019 inst
->dst
.file
== MRF
&&
3020 inst
->src
[0].file
!= ARF
&&
3021 !inst
->is_partial_write()) {
3022 last_mrf_move
[inst
->dst
.nr
] = inst
;
3027 invalidate_live_intervals();
3033 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3035 /* Clear the flag for registers that actually got read (as expected). */
3036 for (int i
= 0; i
< inst
->sources
; i
++) {
3038 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3039 grf
= inst
->src
[i
].nr
;
3044 if (grf
>= first_grf
&&
3045 grf
< first_grf
+ grf_len
) {
3046 deps
[grf
- first_grf
] = false;
3047 if (inst
->exec_size
== 16)
3048 deps
[grf
- first_grf
+ 1] = false;
3054 * Implements this workaround for the original 965:
3056 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3057 * check for post destination dependencies on this instruction, software
3058 * must ensure that there is no destination hazard for the case of ‘write
3059 * followed by a posted write’ shown in the following example.
3062 * 2. send r3.xy <rest of send instruction>
3065 * Due to no post-destination dependency check on the ‘send’, the above
3066 * code sequence could have two instructions (1 and 2) in flight at the
3067 * same time that both consider ‘r3’ as the target of their final writes.
3070 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3073 int write_len
= inst
->regs_written
;
3074 int first_write_grf
= inst
->dst
.nr
;
3075 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3076 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3078 memset(needs_dep
, false, sizeof(needs_dep
));
3079 memset(needs_dep
, true, write_len
);
3081 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3083 /* Walk backwards looking for writes to registers we're writing which
3084 * aren't read since being written. If we hit the start of the program,
3085 * we assume that there are no outstanding dependencies on entry to the
3088 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3089 /* If we hit control flow, assume that there *are* outstanding
3090 * dependencies, and force their cleanup before our instruction.
3092 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3093 for (int i
= 0; i
< write_len
; i
++) {
3095 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3096 first_write_grf
+ i
);
3101 /* We insert our reads as late as possible on the assumption that any
3102 * instruction but a MOV that might have left us an outstanding
3103 * dependency has more latency than a MOV.
3105 if (scan_inst
->dst
.file
== VGRF
) {
3106 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
3107 int reg
= scan_inst
->dst
.nr
+ i
;
3109 if (reg
>= first_write_grf
&&
3110 reg
< first_write_grf
+ write_len
&&
3111 needs_dep
[reg
- first_write_grf
]) {
3112 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3113 needs_dep
[reg
- first_write_grf
] = false;
3114 if (scan_inst
->exec_size
== 16)
3115 needs_dep
[reg
- first_write_grf
+ 1] = false;
3120 /* Clear the flag for registers that actually got read (as expected). */
3121 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3123 /* Continue the loop only if we haven't resolved all the dependencies */
3125 for (i
= 0; i
< write_len
; i
++) {
3135 * Implements this workaround for the original 965:
3137 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3138 * used as a destination register until after it has been sourced by an
3139 * instruction with a different destination register.
3142 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3144 int write_len
= inst
->regs_written
;
3145 int first_write_grf
= inst
->dst
.nr
;
3146 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3147 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3149 memset(needs_dep
, false, sizeof(needs_dep
));
3150 memset(needs_dep
, true, write_len
);
3151 /* Walk forwards looking for writes to registers we're writing which aren't
3152 * read before being written.
3154 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3155 /* If we hit control flow, force resolve all remaining dependencies. */
3156 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3157 for (int i
= 0; i
< write_len
; i
++) {
3159 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3160 first_write_grf
+ i
);
3165 /* Clear the flag for registers that actually got read (as expected). */
3166 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3168 /* We insert our reads as late as possible since they're reading the
3169 * result of a SEND, which has massive latency.
3171 if (scan_inst
->dst
.file
== VGRF
&&
3172 scan_inst
->dst
.nr
>= first_write_grf
&&
3173 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3174 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3175 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3177 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3180 /* Continue the loop only if we haven't resolved all the dependencies */
3182 for (i
= 0; i
< write_len
; i
++) {
3192 fs_visitor::insert_gen4_send_dependency_workarounds()
3194 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3197 bool progress
= false;
3199 /* Note that we're done with register allocation, so GRF fs_regs always
3200 * have a .reg_offset of 0.
3203 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3204 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3205 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3206 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3212 invalidate_live_intervals();
3216 * Turns the generic expression-style uniform pull constant load instruction
3217 * into a hardware-specific series of instructions for loading a pull
3220 * The expression style allows the CSE pass before this to optimize out
3221 * repeated loads from the same offset, and gives the pre-register-allocation
3222 * scheduling full flexibility, while the conversion to native instructions
3223 * allows the post-register-allocation scheduler the best information
3226 * Note that execution masking for setting up pull constant loads is special:
3227 * the channels that need to be written are unrelated to the current execution
3228 * mask, since a later instruction will use one of the result channels as a
3229 * source operand for all 8 or 16 of its channels.
3232 fs_visitor::lower_uniform_pull_constant_loads()
3234 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3235 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3238 if (devinfo
->gen
>= 7) {
3239 /* The offset arg is a vec4-aligned immediate byte offset. */
3240 fs_reg const_offset_reg
= inst
->src
[1];
3241 assert(const_offset_reg
.file
== IMM
&&
3242 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3243 assert(const_offset_reg
.ud
% 16 == 0);
3245 fs_reg payload
, offset
;
3246 if (devinfo
->gen
>= 9) {
3247 /* We have to use a message header on Skylake to get SIMD4x2
3248 * mode. Reserve space for the register.
3250 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3251 offset
.reg_offset
++;
3254 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3258 /* This is actually going to be a MOV, but since only the first dword
3259 * is accessed, we have a special opcode to do just that one. Note
3260 * that this needs to be an operation that will be considered a def
3261 * by live variable analysis, or register allocation will explode.
3263 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3264 8, offset
, const_offset_reg
);
3265 setup
->force_writemask_all
= true;
3267 setup
->ir
= inst
->ir
;
3268 setup
->annotation
= inst
->annotation
;
3269 inst
->insert_before(block
, setup
);
3271 /* Similarly, this will only populate the first 4 channels of the
3272 * result register (since we only use smear values from 0-3), but we
3273 * don't tell the optimizer.
3275 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3276 inst
->src
[1] = payload
;
3278 invalidate_live_intervals();
3280 /* Before register allocation, we didn't tell the scheduler about the
3281 * MRF we use. We know it's safe to use this MRF because nothing
3282 * else does except for register spill/unspill, which generates and
3283 * uses its MRF within a single IR instruction.
3285 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3292 fs_visitor::lower_load_payload()
3294 bool progress
= false;
3296 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3297 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3300 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3301 assert(inst
->saturate
== false);
3302 fs_reg dst
= inst
->dst
;
3304 /* Get rid of COMPR4. We'll add it back in if we need it */
3305 if (dst
.file
== MRF
)
3306 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3308 const fs_builder
ibld(this, block
, inst
);
3309 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3311 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3312 if (inst
->src
[i
].file
!= BAD_FILE
) {
3313 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3314 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3315 hbld
.MOV(mov_dst
, mov_src
);
3317 dst
= offset(dst
, hbld
, 1);
3320 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3321 inst
->exec_size
> 8) {
3322 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3323 * a straightforward copy. Instead, the result of the
3324 * LOAD_PAYLOAD is treated as interleaved and the first four
3325 * non-header sources are unpacked as:
3336 * This is used for gen <= 5 fb writes.
3338 assert(inst
->exec_size
== 16);
3339 assert(inst
->header_size
+ 4 <= inst
->sources
);
3340 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3341 if (inst
->src
[i
].file
!= BAD_FILE
) {
3342 if (devinfo
->has_compr4
) {
3343 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3344 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3345 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3347 /* Platform doesn't have COMPR4. We have to fake it */
3348 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3349 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3351 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3358 /* The loop above only ever incremented us through the first set
3359 * of 4 registers. However, thanks to the magic of COMPR4, we
3360 * actually wrote to the first 8 registers, so we need to take
3361 * that into account now.
3365 /* The COMPR4 code took care of the first 4 sources. We'll let
3366 * the regular path handle any remaining sources. Yes, we are
3367 * modifying the instruction but we're about to delete it so
3368 * this really doesn't hurt anything.
3370 inst
->header_size
+= 4;
3373 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3374 if (inst
->src
[i
].file
!= BAD_FILE
)
3375 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3376 dst
= offset(dst
, ibld
, 1);
3379 inst
->remove(block
);
3384 invalidate_live_intervals();
3390 fs_visitor::lower_integer_multiplication()
3392 bool progress
= false;
3394 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3395 const fs_builder
ibld(this, block
, inst
);
3397 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3398 if (inst
->dst
.is_accumulator() ||
3399 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3400 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3403 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3404 * operation directly, but CHV/BXT cannot.
3406 if (devinfo
->gen
>= 8 &&
3407 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3410 if (inst
->src
[1].file
== IMM
&&
3411 inst
->src
[1].ud
< (1 << 16)) {
3412 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3413 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3416 * If multiplying by an immediate value that fits in 16-bits, do a
3417 * single MUL instruction with that value in the proper location.
3419 if (devinfo
->gen
< 7) {
3420 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3422 ibld
.MOV(imm
, inst
->src
[1]);
3423 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3425 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3426 ibld
.MUL(inst
->dst
, inst
->src
[0],
3427 ud
? brw_imm_uw(inst
->src
[1].ud
)
3428 : brw_imm_w(inst
->src
[1].d
));
3431 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3432 * do 32-bit integer multiplication in one instruction, but instead
3433 * must do a sequence (which actually calculates a 64-bit result):
3435 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3436 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3437 * mov(8) g2<1>D acc0<8,8,1>D
3439 * But on Gen > 6, the ability to use second accumulator register
3440 * (acc1) for non-float data types was removed, preventing a simple
3441 * implementation in SIMD16. A 16-channel result can be calculated by
3442 * executing the three instructions twice in SIMD8, once with quarter
3443 * control of 1Q for the first eight channels and again with 2Q for
3444 * the second eight channels.
3446 * Which accumulator register is implicitly accessed (by AccWrEnable
3447 * for instance) is determined by the quarter control. Unfortunately
3448 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3449 * implicit accumulator access by an instruction with 2Q will access
3450 * acc1 regardless of whether the data type is usable in acc1.
3452 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3453 * integer data types.
3455 * Since we only want the low 32-bits of the result, we can do two
3456 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3457 * adjust the high result and add them (like the mach is doing):
3459 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3460 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3461 * shl(8) g9<1>D g8<8,8,1>D 16D
3462 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3464 * We avoid the shl instruction by realizing that we only want to add
3465 * the low 16-bits of the "high" result to the high 16-bits of the
3466 * "low" result and using proper regioning on the add:
3468 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3469 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3470 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3472 * Since it does not use the (single) accumulator register, we can
3473 * schedule multi-component multiplications much better.
3476 fs_reg orig_dst
= inst
->dst
;
3477 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3478 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3481 fs_reg low
= inst
->dst
;
3482 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3485 if (devinfo
->gen
>= 7) {
3486 fs_reg src1_0_w
= inst
->src
[1];
3487 fs_reg src1_1_w
= inst
->src
[1];
3489 if (inst
->src
[1].file
== IMM
) {
3490 src1_0_w
.ud
&= 0xffff;
3493 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3494 if (src1_0_w
.stride
!= 0) {
3495 assert(src1_0_w
.stride
== 1);
3496 src1_0_w
.stride
= 2;
3499 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3500 if (src1_1_w
.stride
!= 0) {
3501 assert(src1_1_w
.stride
== 1);
3502 src1_1_w
.stride
= 2;
3504 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3506 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3507 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3509 fs_reg src0_0_w
= inst
->src
[0];
3510 fs_reg src0_1_w
= inst
->src
[0];
3512 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3513 if (src0_0_w
.stride
!= 0) {
3514 assert(src0_0_w
.stride
== 1);
3515 src0_0_w
.stride
= 2;
3518 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3519 if (src0_1_w
.stride
!= 0) {
3520 assert(src0_1_w
.stride
== 1);
3521 src0_1_w
.stride
= 2;
3523 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3525 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3526 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3529 fs_reg dst
= inst
->dst
;
3530 dst
.type
= BRW_REGISTER_TYPE_UW
;
3531 dst
.subreg_offset
= 2;
3534 high
.type
= BRW_REGISTER_TYPE_UW
;
3537 low
.type
= BRW_REGISTER_TYPE_UW
;
3538 low
.subreg_offset
= 2;
3541 ibld
.ADD(dst
, low
, high
);
3543 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3544 set_condmod(inst
->conditional_mod
,
3545 ibld
.MOV(orig_dst
, inst
->dst
));
3549 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3550 /* Should have been lowered to 8-wide. */
3551 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3552 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3554 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3555 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3557 if (devinfo
->gen
>= 8) {
3558 /* Until Gen8, integer multiplies read 32-bits from one source,
3559 * and 16-bits from the other, and relying on the MACH instruction
3560 * to generate the high bits of the result.
3562 * On Gen8, the multiply instruction does a full 32x32-bit
3563 * multiply, but in order to do a 64-bit multiply we can simulate
3564 * the previous behavior and then use a MACH instruction.
3566 * FINISHME: Don't use source modifiers on src1.
3568 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3569 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3570 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3571 mul
->src
[1].stride
*= 2;
3573 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3575 /* Among other things the quarter control bits influence which
3576 * accumulator register is used by the hardware for instructions
3577 * that access the accumulator implicitly (e.g. MACH). A
3578 * second-half instruction would normally map to acc1, which
3579 * doesn't exist on Gen7 and up (the hardware does emulate it for
3580 * floating-point instructions *only* by taking advantage of the
3581 * extra precision of acc0 not normally used for floating point
3584 * HSW and up are careful enough not to try to access an
3585 * accumulator register that doesn't exist, but on earlier Gen7
3586 * hardware we need to make sure that the quarter control bits are
3587 * zero to avoid non-deterministic behaviour and emit an extra MOV
3588 * to get the result masked correctly according to the current
3592 mach
->force_writemask_all
= true;
3593 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3594 ibld
.MOV(inst
->dst
, mach
->dst
);
3600 inst
->remove(block
);
3605 invalidate_live_intervals();
3611 fs_visitor::lower_minmax()
3613 assert(devinfo
->gen
< 6);
3615 bool progress
= false;
3617 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3618 const fs_builder
ibld(this, block
, inst
);
3620 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3621 inst
->predicate
== BRW_PREDICATE_NONE
) {
3622 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3623 * the original SEL.L/GE instruction
3625 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3626 inst
->conditional_mod
);
3627 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3628 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3635 invalidate_live_intervals();
3641 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3642 fs_reg
*dst
, fs_reg color
, unsigned components
)
3644 if (key
->clamp_fragment_color
) {
3645 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3646 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3648 for (unsigned i
= 0; i
< components
; i
++)
3650 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3655 for (unsigned i
= 0; i
< components
; i
++)
3656 dst
[i
] = offset(color
, bld
, i
);
3660 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3661 const brw_wm_prog_data
*prog_data
,
3662 const brw_wm_prog_key
*key
,
3663 const fs_visitor::thread_payload
&payload
)
3665 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3666 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3667 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3668 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3669 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3670 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3671 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3672 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3673 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3674 const unsigned components
=
3675 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3677 /* We can potentially have a message length of up to 15, so we have to set
3678 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3681 int header_size
= 2, payload_header_size
;
3682 unsigned length
= 0;
3684 /* From the Sandy Bridge PRM, volume 4, page 198:
3686 * "Dispatched Pixel Enables. One bit per pixel indicating
3687 * which pixels were originally enabled when the thread was
3688 * dispatched. This field is only required for the end-of-
3689 * thread message and on all dual-source messages."
3691 if (devinfo
->gen
>= 6 &&
3692 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3693 color1
.file
== BAD_FILE
&&
3694 key
->nr_color_regions
== 1) {
3698 if (header_size
!= 0) {
3699 assert(header_size
== 2);
3700 /* Allocate 2 registers for a header */
3704 if (payload
.aa_dest_stencil_reg
) {
3705 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3706 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3707 .MOV(sources
[length
],
3708 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3712 if (sample_mask
.file
!= BAD_FILE
) {
3713 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3714 BRW_REGISTER_TYPE_UD
);
3716 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3717 * relevant. Since it's unsigned single words one vgrf is always
3718 * 16-wide, but only the lower or higher 8 channels will be used by the
3719 * hardware when doing a SIMD8 write depending on whether we have
3720 * selected the subspans for the first or second half respectively.
3722 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3723 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3724 sample_mask
.stride
*= 2;
3726 bld
.exec_all().annotate("FB write oMask")
3727 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3733 payload_header_size
= length
;
3735 if (src0_alpha
.file
!= BAD_FILE
) {
3736 /* FIXME: This is being passed at the wrong location in the payload and
3737 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3738 * It's supposed to be immediately before oMask but there seems to be no
3739 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3740 * requires header sources to form a contiguous segment at the beginning
3741 * of the message and src0_alpha has per-channel semantics.
3743 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3747 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3750 if (color1
.file
!= BAD_FILE
) {
3751 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3755 if (src_depth
.file
!= BAD_FILE
) {
3756 sources
[length
] = src_depth
;
3760 if (dst_depth
.file
!= BAD_FILE
) {
3761 sources
[length
] = dst_depth
;
3765 if (src_stencil
.file
!= BAD_FILE
) {
3766 assert(devinfo
->gen
>= 9);
3767 assert(bld
.dispatch_width() != 16);
3769 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3770 * available on gen9+. As such it's impossible to have both enabled at the
3771 * same time and therefore length cannot overrun the array.
3773 assert(length
< 15);
3775 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3776 bld
.exec_all().annotate("FB write OS")
3777 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3778 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3783 if (devinfo
->gen
>= 7) {
3784 /* Send from the GRF */
3785 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3786 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3787 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3788 load
->dst
= payload
;
3790 inst
->src
[0] = payload
;
3791 inst
->resize_sources(1);
3793 /* Send from the MRF */
3794 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3795 sources
, length
, payload_header_size
);
3797 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3798 * will do this for us if we just give it a COMPR4 destination.
3800 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3801 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3803 inst
->resize_sources(0);
3807 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3808 inst
->mlen
= load
->regs_written
;
3809 inst
->header_size
= header_size
;
3813 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3814 const fs_reg
&coordinate
,
3815 const fs_reg
&shadow_c
,
3816 const fs_reg
&lod
, const fs_reg
&lod2
,
3817 const fs_reg
&surface
,
3818 const fs_reg
&sampler
,
3819 unsigned coord_components
,
3820 unsigned grad_components
)
3822 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3823 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3824 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3825 fs_reg msg_end
= msg_begin
;
3828 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3830 for (unsigned i
= 0; i
< coord_components
; i
++)
3831 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3832 offset(coordinate
, bld
, i
));
3834 msg_end
= offset(msg_end
, bld
, coord_components
);
3836 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3837 * require all three components to be present and zero if they are unused.
3839 if (coord_components
> 0 &&
3840 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3841 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3842 for (unsigned i
= coord_components
; i
< 3; i
++)
3843 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3845 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3848 if (op
== SHADER_OPCODE_TXD
) {
3849 /* TXD unsupported in SIMD16 mode. */
3850 assert(bld
.dispatch_width() == 8);
3852 /* the slots for u and v are always present, but r is optional */
3853 if (coord_components
< 2)
3854 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3857 * dPdx = dudx, dvdx, drdx
3858 * dPdy = dudy, dvdy, drdy
3860 * 1-arg: Does not exist.
3862 * 2-arg: dudx dvdx dudy dvdy
3863 * dPdx.x dPdx.y dPdy.x dPdy.y
3866 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3867 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3868 * m5 m6 m7 m8 m9 m10
3870 for (unsigned i
= 0; i
< grad_components
; i
++)
3871 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3873 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3875 for (unsigned i
= 0; i
< grad_components
; i
++)
3876 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3878 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3882 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3883 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3885 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3886 bld
.dispatch_width() == 16);
3888 const brw_reg_type type
=
3889 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3890 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3891 bld
.MOV(retype(msg_end
, type
), lod
);
3892 msg_end
= offset(msg_end
, bld
, 1);
3895 if (shadow_c
.file
!= BAD_FILE
) {
3896 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3897 /* There's no plain shadow compare message, so we use shadow
3898 * compare with a bias of 0.0.
3900 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3901 msg_end
= offset(msg_end
, bld
, 1);
3904 bld
.MOV(msg_end
, shadow_c
);
3905 msg_end
= offset(msg_end
, bld
, 1);
3909 inst
->src
[0] = reg_undef
;
3910 inst
->src
[1] = surface
;
3911 inst
->src
[2] = sampler
;
3912 inst
->resize_sources(3);
3913 inst
->base_mrf
= msg_begin
.nr
;
3914 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3915 inst
->header_size
= 1;
3919 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3920 const fs_reg
&coordinate
,
3921 const fs_reg
&shadow_c
,
3922 const fs_reg
&lod
, const fs_reg
&lod2
,
3923 const fs_reg
&sample_index
,
3924 const fs_reg
&surface
,
3925 const fs_reg
&sampler
,
3926 const fs_reg
&offset_value
,
3927 unsigned coord_components
,
3928 unsigned grad_components
)
3930 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3931 fs_reg msg_coords
= message
;
3932 unsigned header_size
= 0;
3934 if (offset_value
.file
!= BAD_FILE
) {
3935 /* The offsets set up by the visitor are in the m1 header, so we can't
3942 for (unsigned i
= 0; i
< coord_components
; i
++)
3943 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
3944 offset(coordinate
, bld
, i
));
3946 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3947 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3949 if (shadow_c
.file
!= BAD_FILE
) {
3950 fs_reg msg_shadow
= msg_lod
;
3951 bld
.MOV(msg_shadow
, shadow_c
);
3952 msg_lod
= offset(msg_shadow
, bld
, 1);
3957 case SHADER_OPCODE_TXL
:
3959 bld
.MOV(msg_lod
, lod
);
3960 msg_end
= offset(msg_lod
, bld
, 1);
3962 case SHADER_OPCODE_TXD
:
3965 * dPdx = dudx, dvdx, drdx
3966 * dPdy = dudy, dvdy, drdy
3968 * Load up these values:
3969 * - dudx dudy dvdx dvdy drdx drdy
3970 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3973 for (unsigned i
= 0; i
< grad_components
; i
++) {
3974 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
3975 msg_end
= offset(msg_end
, bld
, 1);
3977 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
3978 msg_end
= offset(msg_end
, bld
, 1);
3981 case SHADER_OPCODE_TXS
:
3982 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3983 bld
.MOV(msg_lod
, lod
);
3984 msg_end
= offset(msg_lod
, bld
, 1);
3986 case SHADER_OPCODE_TXF
:
3987 msg_lod
= offset(msg_coords
, bld
, 3);
3988 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3989 msg_end
= offset(msg_lod
, bld
, 1);
3991 case SHADER_OPCODE_TXF_CMS
:
3992 msg_lod
= offset(msg_coords
, bld
, 3);
3994 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3996 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3997 msg_end
= offset(msg_lod
, bld
, 2);
4004 inst
->src
[0] = reg_undef
;
4005 inst
->src
[1] = surface
;
4006 inst
->src
[2] = sampler
;
4007 inst
->resize_sources(3);
4008 inst
->base_mrf
= message
.nr
;
4009 inst
->mlen
= msg_end
.nr
- message
.nr
;
4010 inst
->header_size
= header_size
;
4012 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4013 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4017 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
4019 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4022 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4026 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4027 const fs_reg
&coordinate
,
4028 const fs_reg
&shadow_c
,
4029 fs_reg lod
, const fs_reg
&lod2
,
4030 const fs_reg
&sample_index
,
4032 const fs_reg
&surface
,
4033 const fs_reg
&sampler
,
4034 const fs_reg
&offset_value
,
4035 unsigned coord_components
,
4036 unsigned grad_components
)
4038 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4039 int reg_width
= bld
.dispatch_width() / 8;
4040 unsigned header_size
= 0, length
= 0;
4041 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4042 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4043 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4045 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4046 offset_value
.file
!= BAD_FILE
|| inst
->eot
||
4047 op
== SHADER_OPCODE_SAMPLEINFO
||
4048 is_high_sampler(devinfo
, sampler
)) {
4049 /* For general texture offsets (no txf workaround), we need a header to
4050 * put them in. Note that we're only reserving space for it in the
4051 * message payload as it will be initialized implicitly by the
4054 * TG4 needs to place its channel select in the header, for interaction
4055 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4056 * larger sampler numbers we need to offset the Sampler State Pointer in
4060 sources
[0] = fs_reg();
4063 /* If we're requesting fewer than four channels worth of response,
4064 * and we have an explicit header, we need to set up the sampler
4065 * writemask. It's reversed from normal: 1 means "don't write".
4067 if (!inst
->eot
&& inst
->regs_written
!= 4 * reg_width
) {
4068 assert((inst
->regs_written
% reg_width
) == 0);
4069 unsigned mask
= ~((1 << (inst
->regs_written
/ reg_width
)) - 1) & 0xf;
4070 inst
->offset
|= mask
<< 12;
4074 if (shadow_c
.file
!= BAD_FILE
) {
4075 bld
.MOV(sources
[length
], shadow_c
);
4079 bool coordinate_done
= false;
4081 /* The sampler can only meaningfully compute LOD for fragment shader
4082 * messages. For all other stages, we change the opcode to TXL and
4083 * hardcode the LOD to 0.
4085 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
4086 op
== SHADER_OPCODE_TEX
) {
4087 op
= SHADER_OPCODE_TXL
;
4088 lod
= brw_imm_f(0.0f
);
4091 /* Set up the LOD info */
4094 case SHADER_OPCODE_TXL
:
4095 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4096 op
= SHADER_OPCODE_TXL_LZ
;
4099 bld
.MOV(sources
[length
], lod
);
4102 case SHADER_OPCODE_TXD
:
4103 /* TXD should have been lowered in SIMD16 mode. */
4104 assert(bld
.dispatch_width() == 8);
4106 /* Load dPdx and the coordinate together:
4107 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4109 for (unsigned i
= 0; i
< coord_components
; i
++) {
4110 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4112 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4113 * only derivatives for (u, v, r).
4115 if (i
< grad_components
) {
4116 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4117 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4121 coordinate_done
= true;
4123 case SHADER_OPCODE_TXS
:
4124 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4127 case SHADER_OPCODE_TXF
:
4128 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4129 * On Gen9 they are u, v, lod, r
4131 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4133 if (devinfo
->gen
>= 9) {
4134 if (coord_components
>= 2) {
4135 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4136 offset(coordinate
, bld
, 1));
4138 sources
[length
] = brw_imm_d(0);
4143 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4144 op
= SHADER_OPCODE_TXF_LZ
;
4146 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4150 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4151 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4152 offset(coordinate
, bld
, i
));
4154 coordinate_done
= true;
4157 case SHADER_OPCODE_TXF_CMS
:
4158 case SHADER_OPCODE_TXF_CMS_W
:
4159 case SHADER_OPCODE_TXF_UMS
:
4160 case SHADER_OPCODE_TXF_MCS
:
4161 if (op
== SHADER_OPCODE_TXF_UMS
||
4162 op
== SHADER_OPCODE_TXF_CMS
||
4163 op
== SHADER_OPCODE_TXF_CMS_W
) {
4164 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4168 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4169 /* Data from the multisample control surface. */
4170 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4173 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4176 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4177 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4180 offset(mcs
, bld
, 1));
4185 /* There is no offsetting for this message; just copy in the integer
4186 * texture coordinates.
4188 for (unsigned i
= 0; i
< coord_components
; i
++)
4189 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4190 offset(coordinate
, bld
, i
));
4192 coordinate_done
= true;
4194 case SHADER_OPCODE_TG4_OFFSET
:
4195 /* gather4_po_c should have been lowered in SIMD16 mode. */
4196 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
4198 /* More crazy intermixing */
4199 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4200 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4202 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4203 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4204 offset(offset_value
, bld
, i
));
4206 if (coord_components
== 3) /* r if present */
4207 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4209 coordinate_done
= true;
4215 /* Set up the coordinate (except for cases where it was done above) */
4216 if (!coordinate_done
) {
4217 for (unsigned i
= 0; i
< coord_components
; i
++)
4218 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4223 mlen
= length
* reg_width
- header_size
;
4225 mlen
= length
* reg_width
;
4227 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4228 BRW_REGISTER_TYPE_F
);
4229 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4231 /* Generate the SEND. */
4233 inst
->src
[0] = src_payload
;
4234 inst
->src
[1] = surface
;
4235 inst
->src
[2] = sampler
;
4236 inst
->resize_sources(3);
4238 inst
->header_size
= header_size
;
4240 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4241 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4245 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4247 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4248 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4249 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4250 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4251 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4252 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4253 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4254 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4255 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4256 const fs_reg
&offset_value
= inst
->src
[TEX_LOGICAL_SRC_OFFSET_VALUE
];
4257 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4258 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4259 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4260 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4262 if (devinfo
->gen
>= 7) {
4263 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4264 shadow_c
, lod
, lod2
, sample_index
,
4265 mcs
, surface
, sampler
, offset_value
,
4266 coord_components
, grad_components
);
4267 } else if (devinfo
->gen
>= 5) {
4268 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4269 shadow_c
, lod
, lod2
, sample_index
,
4270 surface
, sampler
, offset_value
,
4271 coord_components
, grad_components
);
4273 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4274 shadow_c
, lod
, lod2
,
4276 coord_components
, grad_components
);
4281 * Initialize the header present in some typed and untyped surface
4285 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4287 fs_builder ubld
= bld
.exec_all().group(8, 0);
4288 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4289 ubld
.MOV(dst
, brw_imm_d(0));
4290 ubld
.MOV(component(dst
, 7), sample_mask
);
4295 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4296 const fs_reg
&sample_mask
)
4298 /* Get the logical send arguments. */
4299 const fs_reg
&addr
= inst
->src
[0];
4300 const fs_reg
&src
= inst
->src
[1];
4301 const fs_reg
&surface
= inst
->src
[2];
4302 const UNUSED fs_reg
&dims
= inst
->src
[3];
4303 const fs_reg
&arg
= inst
->src
[4];
4305 /* Calculate the total number of components of the payload. */
4306 const unsigned addr_sz
= inst
->components_read(0);
4307 const unsigned src_sz
= inst
->components_read(1);
4308 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4309 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4311 /* Allocate space for the payload. */
4312 fs_reg
*const components
= new fs_reg
[sz
];
4313 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4316 /* Construct the payload. */
4318 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4320 for (unsigned i
= 0; i
< addr_sz
; i
++)
4321 components
[n
++] = offset(addr
, bld
, i
);
4323 for (unsigned i
= 0; i
< src_sz
; i
++)
4324 components
[n
++] = offset(src
, bld
, i
);
4326 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4328 /* Update the original instruction. */
4330 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4331 inst
->header_size
= header_sz
;
4333 inst
->src
[0] = payload
;
4334 inst
->src
[1] = surface
;
4336 inst
->resize_sources(3);
4338 delete[] components
;
4342 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4344 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4346 if (devinfo
->gen
>= 7) {
4347 /* We are switching the instruction from an ALU-like instruction to a
4348 * send-from-grf instruction. Since sends can't handle strides or
4349 * source modifiers, we have to make a copy of the offset source.
4351 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4352 bld
.MOV(tmp
, inst
->src
[1]);
4355 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4358 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4359 BRW_REGISTER_TYPE_UD
);
4361 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4363 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4364 inst
->resize_sources(1);
4365 inst
->base_mrf
= payload
.nr
;
4366 inst
->header_size
= 1;
4367 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4372 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4374 assert(bld
.shader
->devinfo
->gen
< 6);
4377 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4379 if (inst
->sources
> 1) {
4380 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4381 * "Message Payload":
4383 * "Operand0[7]. For the INT DIV functions, this operand is the
4386 * "Operand1[7]. For the INT DIV functions, this operand is the
4389 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4390 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4391 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4393 inst
->resize_sources(1);
4394 inst
->src
[0] = src0
;
4396 assert(inst
->exec_size
== 8);
4397 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4402 fs_visitor::lower_logical_sends()
4404 bool progress
= false;
4406 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4407 const fs_builder
ibld(this, block
, inst
);
4409 switch (inst
->opcode
) {
4410 case FS_OPCODE_FB_WRITE_LOGICAL
:
4411 assert(stage
== MESA_SHADER_FRAGMENT
);
4412 lower_fb_write_logical_send(ibld
, inst
,
4413 (const brw_wm_prog_data
*)prog_data
,
4414 (const brw_wm_prog_key
*)key
,
4418 case SHADER_OPCODE_TEX_LOGICAL
:
4419 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4422 case SHADER_OPCODE_TXD_LOGICAL
:
4423 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4426 case SHADER_OPCODE_TXF_LOGICAL
:
4427 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4430 case SHADER_OPCODE_TXL_LOGICAL
:
4431 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4434 case SHADER_OPCODE_TXS_LOGICAL
:
4435 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4438 case FS_OPCODE_TXB_LOGICAL
:
4439 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4442 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4443 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4446 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4447 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4450 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4451 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4454 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4455 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4458 case SHADER_OPCODE_LOD_LOGICAL
:
4459 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4462 case SHADER_OPCODE_TG4_LOGICAL
:
4463 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4466 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4467 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4470 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4471 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4474 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4475 lower_surface_logical_send(ibld
, inst
,
4476 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4480 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4481 lower_surface_logical_send(ibld
, inst
,
4482 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4483 ibld
.sample_mask_reg());
4486 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4487 lower_surface_logical_send(ibld
, inst
,
4488 SHADER_OPCODE_UNTYPED_ATOMIC
,
4489 ibld
.sample_mask_reg());
4492 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4493 lower_surface_logical_send(ibld
, inst
,
4494 SHADER_OPCODE_TYPED_SURFACE_READ
,
4498 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4499 lower_surface_logical_send(ibld
, inst
,
4500 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4501 ibld
.sample_mask_reg());
4504 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4505 lower_surface_logical_send(ibld
, inst
,
4506 SHADER_OPCODE_TYPED_ATOMIC
,
4507 ibld
.sample_mask_reg());
4510 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4511 lower_varying_pull_constant_logical_send(ibld
, inst
);
4514 case SHADER_OPCODE_RCP
:
4515 case SHADER_OPCODE_RSQ
:
4516 case SHADER_OPCODE_SQRT
:
4517 case SHADER_OPCODE_EXP2
:
4518 case SHADER_OPCODE_LOG2
:
4519 case SHADER_OPCODE_SIN
:
4520 case SHADER_OPCODE_COS
:
4521 case SHADER_OPCODE_POW
:
4522 case SHADER_OPCODE_INT_QUOTIENT
:
4523 case SHADER_OPCODE_INT_REMAINDER
:
4524 /* The math opcodes are overloaded for the send-like and
4525 * expression-like instructions which seems kind of icky. Gen6+ has
4526 * a native (but rather quirky) MATH instruction so we don't need to
4527 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4528 * logical instructions (which we can easily recognize because they
4529 * have mlen = 0) into send-like virtual instructions.
4531 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4532 lower_math_logical_send(ibld
, inst
);
4547 invalidate_live_intervals();
4553 * Get the closest allowed SIMD width for instruction \p inst accounting for
4554 * some common regioning and execution control restrictions that apply to FPU
4555 * instructions. These restrictions don't necessarily have any relevance to
4556 * instructions not executed by the FPU pipeline like extended math, control
4557 * flow or send message instructions.
4559 * For virtual opcodes it's really up to the instruction -- In some cases
4560 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4561 * instructions) it may simplify virtual instruction lowering if we can
4562 * enforce FPU-like regioning restrictions already on the virtual instruction,
4563 * in other cases (e.g. virtual send-like instructions) this may be
4564 * excessively restrictive.
4567 get_fpu_lowered_simd_width(const struct brw_device_info
*devinfo
,
4568 const fs_inst
*inst
)
4570 /* Maximum execution size representable in the instruction controls. */
4571 unsigned max_width
= MIN2(32, inst
->exec_size
);
4573 /* According to the PRMs:
4574 * "A. In Direct Addressing mode, a source cannot span more than 2
4575 * adjacent GRF registers.
4576 * B. A destination cannot span more than 2 adjacent GRF registers."
4578 * Look for the source or destination with the largest register region
4579 * which is the one that is going to limit the overall execution size of
4580 * the instruction due to this rule.
4582 unsigned reg_count
= inst
->regs_written
;
4584 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4585 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4587 /* Calculate the maximum execution size of the instruction based on the
4588 * factor by which it goes over the hardware limit of 2 GRFs.
4591 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4593 /* According to the IVB PRMs:
4594 * "When destination spans two registers, the source MUST span two
4595 * registers. The exception to the above rule:
4597 * - When source is scalar, the source registers are not incremented.
4598 * - When source is packed integer Word and destination is packed
4599 * integer DWord, the source register is not incremented but the
4600 * source sub register is incremented."
4602 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4603 * restrictions. The code below intentionally doesn't check whether the
4604 * destination type is integer because empirically the hardware doesn't
4605 * seem to care what the actual type is as long as it's dword-aligned.
4607 if (devinfo
->gen
< 8) {
4608 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4609 if (inst
->regs_written
== 2 &&
4610 inst
->regs_read(i
) != 0 && inst
->regs_read(i
) != 2 &&
4611 !is_uniform(inst
->src
[i
]) &&
4612 !(type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4613 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1))
4614 max_width
= MIN2(max_width
, inst
->exec_size
/
4615 inst
->regs_written
);
4619 /* From the IVB PRMs:
4620 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4621 * are applied for both halves of the SIMD32 instruction. If different
4622 * execution mask channels are required, split the instruction into two
4623 * SIMD16 instructions."
4625 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4626 * 32-wide control flow support in hardware and will behave similarly.
4628 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4629 max_width
= MIN2(max_width
, 16);
4631 /* From the IVB PRMs (applies to HSW too):
4632 * "Instructions with condition modifiers must not use SIMD32."
4634 * From the BDW PRMs (applies to later hardware too):
4635 * "Ternary instruction with condition modifiers must not use SIMD32."
4637 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4638 max_width
= MIN2(max_width
, 16);
4640 /* From the IVB PRMs (applies to other devices that don't have the
4641 * brw_device_info::supports_simd16_3src flag set):
4642 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4643 * SIMD8 is not allowed for DF operations."
4645 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4646 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4648 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
4649 * the 8-bit quarter of the execution mask signals specified in the
4650 * instruction control fields) for the second compressed half of any
4651 * single-precision instruction (for double-precision instructions
4652 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
4653 * the EU will apply the wrong execution controls for the second
4654 * sequential GRF write if the number of channels per GRF is not exactly
4655 * eight in single-precision mode (or four in double-float mode).
4657 * In this situation we calculate the maximum size of the split
4658 * instructions so they only ever write to a single register.
4660 if (devinfo
->gen
< 8 && inst
->regs_written
> 1 &&
4661 !inst
->force_writemask_all
) {
4662 const unsigned channels_per_grf
= inst
->exec_size
/ inst
->regs_written
;
4663 unsigned exec_type_size
= 0;
4664 for (int i
= 0; i
< inst
->sources
; i
++) {
4665 if (inst
->src
[i
].file
!= BAD_FILE
)
4666 exec_type_size
= MAX2(exec_type_size
, type_sz(inst
->src
[i
].type
));
4668 assert(exec_type_size
);
4670 /* The hardware shifts exactly 8 channels per compressed half of the
4671 * instruction in single-precision mode and exactly 4 in double-precision.
4673 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
4674 max_width
= MIN2(max_width
, channels_per_grf
);
4677 /* Only power-of-two execution sizes are representable in the instruction
4680 return 1 << _mesa_logbase2(max_width
);
4684 * Get the closest native SIMD width supported by the hardware for instruction
4685 * \p inst. The instruction will be left untouched by
4686 * fs_visitor::lower_simd_width() if the returned value is equal to the
4687 * original execution size.
4690 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4691 const fs_inst
*inst
)
4693 switch (inst
->opcode
) {
4694 case BRW_OPCODE_MOV
:
4695 case BRW_OPCODE_SEL
:
4696 case BRW_OPCODE_NOT
:
4697 case BRW_OPCODE_AND
:
4699 case BRW_OPCODE_XOR
:
4700 case BRW_OPCODE_SHR
:
4701 case BRW_OPCODE_SHL
:
4702 case BRW_OPCODE_ASR
:
4703 case BRW_OPCODE_CMPN
:
4704 case BRW_OPCODE_CSEL
:
4705 case BRW_OPCODE_F32TO16
:
4706 case BRW_OPCODE_F16TO32
:
4707 case BRW_OPCODE_BFREV
:
4708 case BRW_OPCODE_BFE
:
4709 case BRW_OPCODE_ADD
:
4710 case BRW_OPCODE_MUL
:
4711 case BRW_OPCODE_AVG
:
4712 case BRW_OPCODE_FRC
:
4713 case BRW_OPCODE_RNDU
:
4714 case BRW_OPCODE_RNDD
:
4715 case BRW_OPCODE_RNDE
:
4716 case BRW_OPCODE_RNDZ
:
4717 case BRW_OPCODE_LZD
:
4718 case BRW_OPCODE_FBH
:
4719 case BRW_OPCODE_FBL
:
4720 case BRW_OPCODE_CBIT
:
4721 case BRW_OPCODE_SAD2
:
4722 case BRW_OPCODE_MAD
:
4723 case BRW_OPCODE_LRP
:
4724 case FS_OPCODE_PACK
:
4725 return get_fpu_lowered_simd_width(devinfo
, inst
);
4727 case BRW_OPCODE_CMP
: {
4728 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4729 * when the destination is a GRF the dependency-clear bit on the flag
4730 * register is cleared early.
4732 * Suggested workarounds are to disable coissuing CMP instructions
4733 * or to split CMP(16) instructions into two CMP(8) instructions.
4735 * We choose to split into CMP(8) instructions since disabling
4736 * coissuing would affect CMP instructions not otherwise affected by
4739 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4740 !inst
->dst
.is_null() ? 8 : ~0);
4741 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4743 case BRW_OPCODE_BFI1
:
4744 case BRW_OPCODE_BFI2
:
4745 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4747 * "Force BFI instructions to be executed always in SIMD8."
4749 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4750 get_fpu_lowered_simd_width(devinfo
, inst
));
4753 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4754 return inst
->exec_size
;
4756 case SHADER_OPCODE_RCP
:
4757 case SHADER_OPCODE_RSQ
:
4758 case SHADER_OPCODE_SQRT
:
4759 case SHADER_OPCODE_EXP2
:
4760 case SHADER_OPCODE_LOG2
:
4761 case SHADER_OPCODE_SIN
:
4762 case SHADER_OPCODE_COS
:
4763 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4766 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4767 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4768 MIN2(8, inst
->exec_size
));
4770 case SHADER_OPCODE_POW
:
4771 /* SIMD16 is only allowed on Gen7+. */
4772 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4773 MIN2(8, inst
->exec_size
));
4775 case SHADER_OPCODE_INT_QUOTIENT
:
4776 case SHADER_OPCODE_INT_REMAINDER
:
4777 /* Integer division is limited to SIMD8 on all generations. */
4778 return MIN2(8, inst
->exec_size
);
4780 case FS_OPCODE_LINTERP
:
4781 case FS_OPCODE_GET_BUFFER_SIZE
:
4782 case FS_OPCODE_DDX_COARSE
:
4783 case FS_OPCODE_DDX_FINE
:
4784 case FS_OPCODE_DDY_COARSE
:
4785 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4786 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4787 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4788 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4789 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4790 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4791 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4792 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4793 return MIN2(16, inst
->exec_size
);
4795 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4796 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4797 * message used to implement varying pull constant loads, so expand it
4798 * to SIMD16. An alternative with longer message payload length but
4799 * shorter return payload would be to use the SIMD8 sampler message that
4800 * takes (header, u, v, r) as parameters instead of (header, u).
4802 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4804 case FS_OPCODE_DDY_FINE
:
4805 /* The implementation of this virtual opcode may require emitting
4806 * compressed Align16 instructions, which are severely limited on some
4809 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4810 * Region Restrictions):
4812 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4813 * and SIMD8 is not allowed for DF operations."
4815 * In this context, "DW operations" means "operations acting on 32-bit
4816 * values", so it includes operations on floats.
4818 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4819 * (Instruction Compression -> Rules and Restrictions):
4821 * "A compressed instruction must be in Align1 access mode. Align16
4822 * mode instructions cannot be compressed."
4824 * Similar text exists in the g45 PRM.
4826 * Empirically, compressed align16 instructions using odd register
4827 * numbers don't appear to work on Sandybridge either.
4829 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4830 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4831 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
4833 case SHADER_OPCODE_MULH
:
4834 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4835 * is 8-wide on Gen7+.
4837 return (devinfo
->gen
>= 7 ? 8 :
4838 get_fpu_lowered_simd_width(devinfo
, inst
));
4840 case FS_OPCODE_FB_WRITE_LOGICAL
:
4841 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4844 assert(devinfo
->gen
!= 6 ||
4845 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4846 inst
->exec_size
== 8);
4847 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4848 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4849 8 : MIN2(16, inst
->exec_size
));
4851 case SHADER_OPCODE_TEX_LOGICAL
:
4852 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4853 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4854 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4855 case SHADER_OPCODE_LOD_LOGICAL
:
4856 case SHADER_OPCODE_TG4_LOGICAL
:
4857 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4858 return MIN2(16, inst
->exec_size
);
4860 case SHADER_OPCODE_TXD_LOGICAL
:
4861 /* TXD is unsupported in SIMD16 mode. */
4864 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4865 /* gather4_po_c is unsupported in SIMD16 mode. */
4866 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4867 return (shadow_c
.file
!= BAD_FILE
? 8 : MIN2(16, inst
->exec_size
));
4869 case SHADER_OPCODE_TXL_LOGICAL
:
4870 case FS_OPCODE_TXB_LOGICAL
: {
4871 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4872 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4873 * mode because the message exceeds the maximum length of 11.
4875 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4876 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4878 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4881 return MIN2(16, inst
->exec_size
);
4883 case SHADER_OPCODE_TXF_LOGICAL
:
4884 case SHADER_OPCODE_TXS_LOGICAL
:
4885 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4886 * messages. Use SIMD16 instead.
4888 if (devinfo
->gen
== 4)
4891 return MIN2(16, inst
->exec_size
);
4893 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4894 /* This opcode can take up to 6 arguments which means that in some
4895 * circumstances it can end up with a message that is too long in SIMD16
4898 const unsigned coord_components
=
4899 inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4900 /* First three arguments are the sample index and the two arguments for
4903 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4906 return MIN2(16, inst
->exec_size
);
4909 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4910 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4911 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4914 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4915 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4916 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4917 return MIN2(16, inst
->exec_size
);
4919 case SHADER_OPCODE_URB_READ_SIMD8
:
4920 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
4921 case SHADER_OPCODE_URB_WRITE_SIMD8
:
4922 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
4923 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
4924 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
4925 return MIN2(8, inst
->exec_size
);
4927 case SHADER_OPCODE_MOV_INDIRECT
:
4928 /* Prior to Broadwell, we only have 8 address subregisters */
4929 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
4930 2 * REG_SIZE
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
4933 case SHADER_OPCODE_LOAD_PAYLOAD
: {
4934 const unsigned reg_count
=
4935 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
4937 if (reg_count
> 2) {
4938 /* Only LOAD_PAYLOAD instructions with per-channel destination region
4939 * can be easily lowered (which excludes headers and heterogeneous
4942 assert(!inst
->header_size
);
4943 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4944 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
4945 inst
->src
[i
].file
== BAD_FILE
);
4947 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4949 return inst
->exec_size
;
4953 return inst
->exec_size
;
4958 * Return true if splitting out the group of channels of instruction \p inst
4959 * given by lbld.group() requires allocating a temporary for the i-th source
4960 * of the lowered instruction.
4963 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
4965 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
4966 (inst
->components_read(i
) == 1 &&
4967 lbld
.dispatch_width() <= inst
->exec_size
));
4971 * Extract the data that would be consumed by the channel group given by
4972 * lbld.group() from the i-th source region of instruction \p inst and return
4973 * it as result in packed form. If any copy instructions are required they
4974 * will be emitted before the given \p inst in \p block.
4977 emit_unzip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
,
4980 /* Specified channel group from the source region. */
4981 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
4983 if (needs_src_copy(lbld
, inst
, i
)) {
4984 /* Builder of the right width to perform the copy avoiding uninitialized
4985 * data if the lowered execution size is greater than the original
4986 * execution size of the instruction.
4988 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
4989 inst
->exec_size
), 0);
4990 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
4992 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
4993 cbld
.at(block
, inst
)
4994 .MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
4998 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
4999 /* The source is invariant for all dispatch_width-wide groups of the
5002 return inst
->src
[i
];
5005 /* We can just point the lowered instruction at the right channel group
5006 * from the original region.
5013 * Return true if splitting out the group of channels of instruction \p inst
5014 * given by lbld.group() requires allocating a temporary for the destination
5015 * of the lowered instruction and copying the data back to the original
5016 * destination region.
5019 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5021 /* If the instruction writes more than one component we'll have to shuffle
5022 * the results of multiple lowered instructions in order to make sure that
5023 * they end up arranged correctly in the original destination region.
5025 if (inst
->regs_written
* REG_SIZE
>
5026 inst
->dst
.component_size(inst
->exec_size
))
5029 /* If the lowered execution size is larger than the original the result of
5030 * the instruction won't fit in the original destination, so we'll have to
5031 * allocate a temporary in any case.
5033 if (lbld
.dispatch_width() > inst
->exec_size
)
5036 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5037 /* If we already made a copy of the source for other reasons there won't
5038 * be any overlap with the destination.
5040 if (needs_src_copy(lbld
, inst
, i
))
5043 /* In order to keep the logic simple we emit a copy whenever the
5044 * destination region doesn't exactly match an overlapping source, which
5045 * may point at the source and destination not being aligned group by
5046 * group which could cause one of the lowered instructions to overwrite
5047 * the data read from the same source by other lowered instructions.
5049 if (regions_overlap(inst
->dst
, inst
->regs_written
* REG_SIZE
,
5050 inst
->src
[i
], inst
->regs_read(i
) * REG_SIZE
) &&
5051 !inst
->dst
.equals(inst
->src
[i
]))
5059 * Insert data from a packed temporary into the channel group given by
5060 * lbld.group() of the destination region of instruction \p inst and return
5061 * the temporary as result. If any copy instructions are required they will
5062 * be emitted around the given \p inst in \p block.
5065 emit_zip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
)
5067 /* Builder of the right width to perform the copy avoiding uninitialized
5068 * data if the lowered execution size is greater than the original
5069 * execution size of the instruction.
5071 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5072 inst
->exec_size
), 0);
5074 /* Specified channel group from the destination region. */
5075 const fs_reg dst
= horiz_offset(inst
->dst
, lbld
.group());
5076 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
5077 inst
->dst
.component_size(inst
->exec_size
);
5079 if (needs_dst_copy(lbld
, inst
)) {
5080 const fs_reg tmp
= lbld
.vgrf(inst
->dst
.type
, dst_size
);
5082 if (inst
->predicate
) {
5083 /* Handle predication by copying the original contents of
5084 * the destination into the temporary before emitting the
5085 * lowered instruction.
5087 for (unsigned k
= 0; k
< dst_size
; ++k
)
5088 cbld
.at(block
, inst
)
5089 .MOV(offset(tmp
, lbld
, k
), offset(dst
, inst
->exec_size
, k
));
5092 for (unsigned k
= 0; k
< dst_size
; ++k
)
5093 cbld
.at(block
, inst
->next
)
5094 .MOV(offset(dst
, inst
->exec_size
, k
), offset(tmp
, lbld
, k
));
5099 /* No need to allocate a temporary for the lowered instruction, just
5100 * take the right group of channels from the original region.
5107 fs_visitor::lower_simd_width()
5109 bool progress
= false;
5111 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5112 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5114 if (lower_width
!= inst
->exec_size
) {
5115 /* Builder matching the original instruction. We may also need to
5116 * emit an instruction of width larger than the original, set the
5117 * execution size of the builder to the highest of both for now so
5118 * we're sure that both cases can be handled.
5120 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5121 const fs_builder ibld
= bld
.at(block
, inst
)
5122 .exec_all(inst
->force_writemask_all
)
5123 .group(max_width
, inst
->group
/ max_width
);
5125 /* Split the copies in chunks of the execution width of either the
5126 * original or the lowered instruction, whichever is lower.
5128 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5129 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
5130 inst
->dst
.component_size(inst
->exec_size
);
5132 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5134 for (unsigned i
= 0; i
< n
; i
++) {
5135 /* Emit a copy of the original instruction with the lowered width.
5136 * If the EOT flag was set throw it away except for the last
5137 * instruction to avoid killing the thread prematurely.
5139 fs_inst split_inst
= *inst
;
5140 split_inst
.exec_size
= lower_width
;
5141 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
5143 /* Select the correct channel enables for the i-th group, then
5144 * transform the sources and destination and emit the lowered
5147 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5149 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5150 split_inst
.src
[j
] = emit_unzip(lbld
, block
, inst
, j
);
5152 split_inst
.dst
= emit_zip(lbld
, block
, inst
);
5153 split_inst
.regs_written
= DIV_ROUND_UP(
5154 split_inst
.dst
.component_size(lower_width
) * dst_size
,
5157 lbld
.emit(split_inst
);
5160 inst
->remove(block
);
5166 invalidate_live_intervals();
5172 fs_visitor::dump_instructions()
5174 dump_instructions(NULL
);
5178 fs_visitor::dump_instructions(const char *name
)
5180 FILE *file
= stderr
;
5181 if (name
&& geteuid() != 0) {
5182 file
= fopen(name
, "w");
5188 calculate_register_pressure();
5189 int ip
= 0, max_pressure
= 0;
5190 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5191 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5192 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5193 dump_instruction(inst
, file
);
5196 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5199 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5200 fprintf(file
, "%4d: ", ip
++);
5201 dump_instruction(inst
, file
);
5205 if (file
!= stderr
) {
5211 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5213 dump_instruction(be_inst
, stderr
);
5217 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5219 fs_inst
*inst
= (fs_inst
*)be_inst
;
5221 if (inst
->predicate
) {
5222 fprintf(file
, "(%cf0.%d) ",
5223 inst
->predicate_inverse
? '-' : '+',
5227 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5229 fprintf(file
, ".sat");
5230 if (inst
->conditional_mod
) {
5231 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5232 if (!inst
->predicate
&&
5233 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5234 inst
->opcode
!= BRW_OPCODE_IF
&&
5235 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5236 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5239 fprintf(file
, "(%d) ", inst
->exec_size
);
5242 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5246 fprintf(file
, "(EOT) ");
5249 switch (inst
->dst
.file
) {
5251 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5252 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
5253 inst
->dst
.subreg_offset
)
5254 fprintf(file
, "+%d.%d",
5255 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
5258 fprintf(file
, "g%d", inst
->dst
.nr
);
5261 fprintf(file
, "m%d", inst
->dst
.nr
);
5264 fprintf(file
, "(null)");
5267 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
5270 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
5273 switch (inst
->dst
.nr
) {
5275 fprintf(file
, "null");
5277 case BRW_ARF_ADDRESS
:
5278 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5280 case BRW_ARF_ACCUMULATOR
:
5281 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5284 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5287 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5290 if (inst
->dst
.subnr
)
5291 fprintf(file
, "+%d", inst
->dst
.subnr
);
5294 unreachable("not reached");
5296 if (inst
->dst
.stride
!= 1)
5297 fprintf(file
, "<%u>", inst
->dst
.stride
);
5298 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
5300 for (int i
= 0; i
< inst
->sources
; i
++) {
5301 if (inst
->src
[i
].negate
)
5303 if (inst
->src
[i
].abs
)
5305 switch (inst
->src
[i
].file
) {
5307 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5308 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
5309 inst
->src
[i
].subreg_offset
)
5310 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
5311 inst
->src
[i
].subreg_offset
);
5314 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5317 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5320 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
5323 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
5324 if (inst
->src
[i
].subreg_offset
) {
5325 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
5326 inst
->src
[i
].subreg_offset
);
5330 fprintf(file
, "(null)");
5333 switch (inst
->src
[i
].type
) {
5334 case BRW_REGISTER_TYPE_F
:
5335 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5337 case BRW_REGISTER_TYPE_DF
:
5338 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5340 case BRW_REGISTER_TYPE_W
:
5341 case BRW_REGISTER_TYPE_D
:
5342 fprintf(file
, "%dd", inst
->src
[i
].d
);
5344 case BRW_REGISTER_TYPE_UW
:
5345 case BRW_REGISTER_TYPE_UD
:
5346 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5348 case BRW_REGISTER_TYPE_VF
:
5349 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5350 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5351 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5352 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5353 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5356 fprintf(file
, "???");
5361 switch (inst
->src
[i
].nr
) {
5363 fprintf(file
, "null");
5365 case BRW_ARF_ADDRESS
:
5366 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5368 case BRW_ARF_ACCUMULATOR
:
5369 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5372 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5375 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5378 if (inst
->src
[i
].subnr
)
5379 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
5382 if (inst
->src
[i
].abs
)
5385 if (inst
->src
[i
].file
!= IMM
) {
5387 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5388 unsigned hstride
= inst
->src
[i
].hstride
;
5389 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5391 stride
= inst
->src
[i
].stride
;
5394 fprintf(file
, "<%u>", stride
);
5396 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
5399 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5400 fprintf(file
, ", ");
5405 if (inst
->force_writemask_all
)
5406 fprintf(file
, "NoMask ");
5408 if (inst
->exec_size
!= dispatch_width
)
5409 fprintf(file
, "group%d ", inst
->group
);
5411 fprintf(file
, "\n");
5415 * Possibly returns an instruction that set up @param reg.
5417 * Sometimes we want to take the result of some expression/variable
5418 * dereference tree and rewrite the instruction generating the result
5419 * of the tree. When processing the tree, we know that the
5420 * instructions generated are all writing temporaries that are dead
5421 * outside of this tree. So, if we have some instructions that write
5422 * a temporary, we're free to point that temp write somewhere else.
5424 * Note that this doesn't guarantee that the instruction generated
5425 * only reg -- it might be the size=4 destination of a texture instruction.
5428 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5433 end
->is_partial_write() ||
5434 !reg
.equals(end
->dst
)) {
5442 fs_visitor::setup_fs_payload_gen6()
5444 assert(stage
== MESA_SHADER_FRAGMENT
);
5445 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5447 unsigned barycentric_interp_modes
=
5448 (stage
== MESA_SHADER_FRAGMENT
) ?
5449 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
5451 assert(devinfo
->gen
>= 6);
5453 /* R0-1: masks, pixel X/Y coordinates. */
5454 payload
.num_regs
= 2;
5455 /* R2: only for 32-pixel dispatch.*/
5457 /* R3-26: barycentric interpolation coordinates. These appear in the
5458 * same order that they appear in the brw_barycentric_mode
5459 * enum. Each set of coordinates occupies 2 registers if dispatch width
5460 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5461 * appear if they were enabled using the "Barycentric Interpolation
5462 * Mode" bits in WM_STATE.
5464 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5465 if (barycentric_interp_modes
& (1 << i
)) {
5466 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5467 payload
.num_regs
+= 2;
5468 if (dispatch_width
== 16) {
5469 payload
.num_regs
+= 2;
5474 /* R27: interpolated depth if uses source depth */
5475 prog_data
->uses_src_depth
=
5476 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5477 if (prog_data
->uses_src_depth
) {
5478 payload
.source_depth_reg
= payload
.num_regs
;
5480 if (dispatch_width
== 16) {
5481 /* R28: interpolated depth if not SIMD8. */
5486 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5487 prog_data
->uses_src_w
=
5488 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5489 if (prog_data
->uses_src_w
) {
5490 payload
.source_w_reg
= payload
.num_regs
;
5492 if (dispatch_width
== 16) {
5493 /* R30: interpolated W if not SIMD8. */
5498 /* R31: MSAA position offsets. */
5499 if (prog_data
->persample_dispatch
&&
5500 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5501 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5503 * "MSDISPMODE_PERSAMPLE is required in order to select
5506 * So we can only really get sample positions if we are doing real
5507 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5508 * persample dispatch, we hard-code it to 0.5.
5510 prog_data
->uses_pos_offset
= true;
5511 payload
.sample_pos_reg
= payload
.num_regs
;
5515 /* R32: MSAA input coverage mask */
5516 prog_data
->uses_sample_mask
=
5517 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5518 if (prog_data
->uses_sample_mask
) {
5519 assert(devinfo
->gen
>= 7);
5520 payload
.sample_mask_in_reg
= payload
.num_regs
;
5522 if (dispatch_width
== 16) {
5523 /* R33: input coverage mask if not SIMD8. */
5528 /* R34-: bary for 32-pixel. */
5529 /* R58-59: interp W for 32-pixel. */
5531 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5532 source_depth_to_render_target
= true;
5537 fs_visitor::setup_vs_payload()
5539 /* R0: thread header, R1: urb handles */
5540 payload
.num_regs
= 2;
5544 fs_visitor::setup_gs_payload()
5546 assert(stage
== MESA_SHADER_GEOMETRY
);
5548 struct brw_gs_prog_data
*gs_prog_data
=
5549 (struct brw_gs_prog_data
*) prog_data
;
5550 struct brw_vue_prog_data
*vue_prog_data
=
5551 (struct brw_vue_prog_data
*) prog_data
;
5553 /* R0: thread header, R1: output URB handles */
5554 payload
.num_regs
= 2;
5556 if (gs_prog_data
->include_primitive_id
) {
5557 /* R2: Primitive ID 0..7 */
5561 /* Use a maximum of 24 registers for push-model inputs. */
5562 const unsigned max_push_components
= 24;
5564 /* If pushing our inputs would take too many registers, reduce the URB read
5565 * length (which is in HWords, or 8 registers), and resort to pulling.
5567 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5568 * have to multiply by VerticesIn to obtain the total storage requirement.
5570 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5571 max_push_components
) {
5572 gs_prog_data
->base
.include_vue_handles
= true;
5574 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5575 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5577 vue_prog_data
->urb_read_length
=
5578 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5583 fs_visitor::setup_cs_payload()
5585 assert(devinfo
->gen
>= 7);
5586 payload
.num_regs
= 1;
5590 fs_visitor::calculate_register_pressure()
5592 invalidate_live_intervals();
5593 calculate_live_intervals();
5595 unsigned num_instructions
= 0;
5596 foreach_block(block
, cfg
)
5597 num_instructions
+= block
->instructions
.length();
5599 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5601 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5602 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5603 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5608 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5610 * The needs_unlit_centroid_workaround ends up producing one of these per
5611 * channel of centroid input, so it's good to clean them up.
5613 * An assumption here is that nothing ever modifies the dispatched pixels
5614 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5615 * dictates that anyway.
5618 fs_visitor::opt_drop_redundant_mov_to_flags()
5620 bool flag_mov_found
[2] = {false};
5621 bool progress
= false;
5623 /* Instructions removed by this pass can only be added if this were true */
5624 if (!devinfo
->needs_unlit_centroid_workaround
)
5627 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5628 if (inst
->is_control_flow()) {
5629 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5630 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5631 if (!flag_mov_found
[inst
->flag_subreg
]) {
5632 flag_mov_found
[inst
->flag_subreg
] = true;
5634 inst
->remove(block
);
5637 } else if (inst
->flags_written()) {
5638 flag_mov_found
[inst
->flag_subreg
] = false;
5646 fs_visitor::optimize()
5648 /* Start by validating the shader we currently have. */
5651 /* bld is the common builder object pointing at the end of the program we
5652 * used to translate it into i965 IR. For the optimization and lowering
5653 * passes coming next, any code added after the end of the program without
5654 * having explicitly called fs_builder::at() clearly points at a mistake.
5655 * Ideally optimization passes wouldn't be part of the visitor so they
5656 * wouldn't have access to bld at all, but they do, so just in case some
5657 * pass forgets to ask for a location explicitly set it to NULL here to
5658 * make it trip. The dispatch width is initialized to a bogus value to
5659 * make sure that optimizations set the execution controls explicitly to
5660 * match the code they are manipulating instead of relying on the defaults.
5662 bld
= fs_builder(this, 64);
5664 assign_constant_locations();
5665 lower_constant_loads();
5669 split_virtual_grfs();
5672 #define OPT(pass, args...) ({ \
5674 bool this_progress = pass(args); \
5676 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5677 char filename[64]; \
5678 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5679 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5681 backend_shader::dump_instructions(filename); \
5686 progress = progress || this_progress; \
5690 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5692 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5693 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5695 backend_shader::dump_instructions(filename
);
5698 bool progress
= false;
5702 OPT(opt_drop_redundant_mov_to_flags
);
5709 OPT(remove_duplicate_mrf_writes
);
5713 OPT(opt_copy_propagate
);
5714 OPT(opt_predicated_break
, this);
5715 OPT(opt_cmod_propagation
);
5716 OPT(dead_code_eliminate
);
5717 OPT(opt_peephole_sel
);
5718 OPT(dead_control_flow_eliminate
, this);
5719 OPT(opt_register_renaming
);
5720 OPT(opt_saturate_propagation
);
5721 OPT(register_coalesce
);
5722 OPT(compute_to_mrf
);
5723 OPT(eliminate_find_live_channel
);
5725 OPT(compact_virtual_grfs
);
5731 if (OPT(lower_pack
)) {
5732 OPT(register_coalesce
);
5733 OPT(dead_code_eliminate
);
5736 if (OPT(lower_d2x
)) {
5737 OPT(opt_copy_propagate
);
5738 OPT(dead_code_eliminate
);
5741 OPT(lower_simd_width
);
5743 /* After SIMD lowering just in case we had to unroll the EOT send. */
5744 OPT(opt_sampler_eot
);
5746 OPT(lower_logical_sends
);
5749 OPT(opt_copy_propagate
);
5750 /* Only run after logical send lowering because it's easier to implement
5751 * in terms of physical sends.
5753 if (OPT(opt_zero_samples
))
5754 OPT(opt_copy_propagate
);
5755 /* Run after logical send lowering to give it a chance to CSE the
5756 * LOAD_PAYLOAD instructions created to construct the payloads of
5757 * e.g. texturing messages in cases where it wasn't possible to CSE the
5758 * whole logical instruction.
5761 OPT(register_coalesce
);
5762 OPT(compute_to_mrf
);
5763 OPT(dead_code_eliminate
);
5764 OPT(remove_duplicate_mrf_writes
);
5765 OPT(opt_peephole_sel
);
5768 OPT(opt_redundant_discard_jumps
);
5770 if (OPT(lower_load_payload
)) {
5771 split_virtual_grfs();
5772 OPT(register_coalesce
);
5773 OPT(compute_to_mrf
);
5774 OPT(dead_code_eliminate
);
5777 OPT(opt_combine_constants
);
5778 OPT(lower_integer_multiplication
);
5780 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5781 OPT(opt_cmod_propagation
);
5783 OPT(opt_copy_propagate
);
5784 OPT(dead_code_eliminate
);
5787 lower_uniform_pull_constant_loads();
5793 * Three source instruction must have a GRF/MRF destination register.
5794 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5797 fs_visitor::fixup_3src_null_dest()
5799 bool progress
= false;
5801 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5802 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5803 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5810 invalidate_live_intervals();
5814 fs_visitor::allocate_registers(bool allow_spilling
)
5816 bool allocated_without_spills
;
5818 static const enum instruction_scheduler_mode pre_modes
[] = {
5820 SCHEDULE_PRE_NON_LIFO
,
5824 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
5826 /* Try each scheduling heuristic to see if it can successfully register
5827 * allocate without spilling. They should be ordered by decreasing
5828 * performance but increasing likelihood of allocating.
5830 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5831 schedule_instructions(pre_modes
[i
]);
5834 assign_regs_trivial();
5835 allocated_without_spills
= true;
5837 allocated_without_spills
= assign_regs(false, spill_all
);
5839 if (allocated_without_spills
)
5843 if (!allocated_without_spills
) {
5844 /* We assume that any spilling is worse than just dropping back to
5845 * SIMD8. There's probably actually some intermediate point where
5846 * SIMD16 with a couple of spills is still better.
5848 if (dispatch_width
> min_dispatch_width
) {
5849 fail("Failure to register allocate. Reduce number of "
5850 "live scalar values to avoid this.");
5852 compiler
->shader_perf_log(log_data
,
5853 "%s shader triggered register spilling. "
5854 "Try reducing the number of live scalar "
5855 "values to improve performance.\n",
5859 /* Since we're out of heuristics, just go spill registers until we
5860 * get an allocation.
5862 while (!assign_regs(true, spill_all
)) {
5868 assert(last_scratch
== 0 || allow_spilling
);
5870 /* This must come after all optimization and register allocation, since
5871 * it inserts dead code that happens to have side effects, and it does
5872 * so based on the actual physical registers in use.
5874 insert_gen4_send_dependency_workarounds();
5879 schedule_instructions(SCHEDULE_POST
);
5881 if (last_scratch
> 0) {
5882 unsigned max_scratch_size
= 2 * 1024 * 1024;
5884 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5886 if (stage
== MESA_SHADER_COMPUTE
) {
5887 if (devinfo
->is_haswell
) {
5888 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5889 * field documentation, Haswell supports a minimum of 2kB of
5890 * scratch space for compute shaders, unlike every other stage
5893 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
5894 } else if (devinfo
->gen
<= 7) {
5895 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5896 * field documentation, platforms prior to Haswell measure scratch
5897 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
5899 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
5900 max_scratch_size
= 12 * 1024;
5904 /* We currently only support up to 2MB of scratch space. If we
5905 * need to support more eventually, the documentation suggests
5906 * that we could allocate a larger buffer, and partition it out
5907 * ourselves. We'd just have to undo the hardware's address
5908 * calculation by subtracting (FFTID * Per Thread Scratch Space)
5909 * and then add FFTID * (Larger Per Thread Scratch Space).
5911 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
5912 * Thread Group Tracking > Local Memory/Scratch Space.
5914 assert(prog_data
->total_scratch
< max_scratch_size
);
5919 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5921 assert(stage
== MESA_SHADER_VERTEX
);
5925 if (shader_time_index
>= 0)
5926 emit_shader_time_begin();
5933 compute_clip_distance(clip_planes
);
5937 if (shader_time_index
>= 0)
5938 emit_shader_time_end();
5944 assign_curb_setup();
5945 assign_vs_urb_setup();
5947 fixup_3src_null_dest();
5948 allocate_registers(true);
5954 fs_visitor::run_tcs_single_patch()
5956 assert(stage
== MESA_SHADER_TESS_CTRL
);
5958 struct brw_tcs_prog_data
*tcs_prog_data
=
5959 (struct brw_tcs_prog_data
*) prog_data
;
5961 /* r1-r4 contain the ICP handles. */
5962 payload
.num_regs
= 5;
5964 if (shader_time_index
>= 0)
5965 emit_shader_time_begin();
5967 /* Initialize gl_InvocationID */
5968 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
5969 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5970 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
5971 bld
.MOV(channels_ud
, channels_uw
);
5973 if (tcs_prog_data
->instances
== 1) {
5974 invocation_id
= channels_ud
;
5976 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5978 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
5979 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5980 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5981 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
5982 brw_imm_ud(INTEL_MASK(23, 17)));
5983 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
5985 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
5988 /* Fix the disptach mask */
5989 if (nir
->info
.tcs
.vertices_out
% 8) {
5990 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
5991 brw_imm_ud(nir
->info
.tcs
.vertices_out
), BRW_CONDITIONAL_L
);
5992 bld
.IF(BRW_PREDICATE_NORMAL
);
5997 if (nir
->info
.tcs
.vertices_out
% 8) {
5998 bld
.emit(BRW_OPCODE_ENDIF
);
6001 /* Emit EOT write; set TR DS Cache bit */
6003 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6004 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6005 fs_reg(brw_imm_ud(0)),
6007 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6008 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6010 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6011 bld
.null_reg_ud(), payload
);
6015 if (shader_time_index
>= 0)
6016 emit_shader_time_end();
6025 assign_curb_setup();
6026 assign_tcs_single_patch_urb_setup();
6028 fixup_3src_null_dest();
6029 allocate_registers(true);
6035 fs_visitor::run_tes()
6037 assert(stage
== MESA_SHADER_TESS_EVAL
);
6039 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6040 payload
.num_regs
= 5;
6042 if (shader_time_index
>= 0)
6043 emit_shader_time_begin();
6052 if (shader_time_index
>= 0)
6053 emit_shader_time_end();
6059 assign_curb_setup();
6060 assign_tes_urb_setup();
6062 fixup_3src_null_dest();
6063 allocate_registers(true);
6069 fs_visitor::run_gs()
6071 assert(stage
== MESA_SHADER_GEOMETRY
);
6075 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6077 if (gs_compile
->control_data_header_size_bits
> 0) {
6078 /* Create a VGRF to store accumulated control data bits. */
6079 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6081 /* If we're outputting more than 32 control data bits, then EmitVertex()
6082 * will set control_data_bits to 0 after emitting the first vertex.
6083 * Otherwise, we need to initialize it to 0 here.
6085 if (gs_compile
->control_data_header_size_bits
<= 32) {
6086 const fs_builder abld
= bld
.annotate("initialize control data bits");
6087 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6091 if (shader_time_index
>= 0)
6092 emit_shader_time_begin();
6096 emit_gs_thread_end();
6098 if (shader_time_index
>= 0)
6099 emit_shader_time_end();
6108 assign_curb_setup();
6109 assign_gs_urb_setup();
6111 fixup_3src_null_dest();
6112 allocate_registers(true);
6118 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6120 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
6121 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6123 assert(stage
== MESA_SHADER_FRAGMENT
);
6125 if (devinfo
->gen
>= 6)
6126 setup_fs_payload_gen6();
6128 setup_fs_payload_gen4();
6132 } else if (do_rep_send
) {
6133 assert(dispatch_width
== 16);
6134 emit_repclear_shader();
6136 if (shader_time_index
>= 0)
6137 emit_shader_time_begin();
6139 calculate_urb_setup();
6140 if (nir
->info
.inputs_read
> 0) {
6141 if (devinfo
->gen
< 6)
6142 emit_interpolation_setup_gen4();
6144 emit_interpolation_setup_gen6();
6147 /* We handle discards by keeping track of the still-live pixels in f0.1.
6148 * Initialize it with the dispatched pixels.
6150 if (wm_prog_data
->uses_kill
) {
6151 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6152 discard_init
->flag_subreg
= 1;
6155 /* Generate FS IR for main(). (the visitor only descends into
6156 * functions called "main").
6163 if (wm_prog_data
->uses_kill
)
6164 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6166 if (wm_key
->alpha_test_func
)
6171 if (shader_time_index
>= 0)
6172 emit_shader_time_end();
6178 assign_curb_setup();
6181 fixup_3src_null_dest();
6182 allocate_registers(allow_spilling
);
6192 fs_visitor::run_cs()
6194 assert(stage
== MESA_SHADER_COMPUTE
);
6198 if (shader_time_index
>= 0)
6199 emit_shader_time_begin();
6201 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6202 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6203 const fs_builder abld
= bld
.exec_all().group(1, 0);
6204 abld
.MOV(retype(suboffset(brw_sr0_reg(), 1), BRW_REGISTER_TYPE_UW
),
6205 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6213 emit_cs_terminate();
6215 if (shader_time_index
>= 0)
6216 emit_shader_time_end();
6222 assign_curb_setup();
6224 fixup_3src_null_dest();
6225 allocate_registers(true);
6234 * Return a bitfield where bit n is set if barycentric interpolation mode n
6235 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6237 * We examine the load_barycentric intrinsics rather than looking at input
6238 * variables so that we catch interpolateAtCentroid() messages too, which
6239 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6242 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
6243 const nir_shader
*shader
)
6245 unsigned barycentric_interp_modes
= 0;
6247 nir_foreach_function(f
, shader
) {
6251 nir_foreach_block(block
, f
->impl
) {
6252 nir_foreach_instr(instr
, block
) {
6253 if (instr
->type
!= nir_instr_type_intrinsic
)
6256 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6257 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6260 /* Ignore WPOS; it doesn't require interpolation. */
6261 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6264 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6265 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
6266 nir_intrinsic_interp_mode(intrin
);
6267 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
6268 enum brw_barycentric_mode bary
=
6269 brw_barycentric_mode(interp
, bary_op
);
6271 barycentric_interp_modes
|= 1 << bary
;
6273 if (devinfo
->needs_unlit_centroid_workaround
&&
6274 bary_op
== nir_intrinsic_load_barycentric_centroid
)
6275 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
6280 return barycentric_interp_modes
;
6284 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6285 const nir_shader
*shader
)
6287 prog_data
->flat_inputs
= 0;
6289 nir_foreach_variable(var
, &shader
->inputs
) {
6290 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6292 if (input_index
< 0)
6296 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6297 prog_data
->flat_inputs
|= (1 << input_index
);
6302 computed_depth_mode(const nir_shader
*shader
)
6304 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6305 switch (shader
->info
.fs
.depth_layout
) {
6306 case FRAG_DEPTH_LAYOUT_NONE
:
6307 case FRAG_DEPTH_LAYOUT_ANY
:
6308 return BRW_PSCDEPTH_ON
;
6309 case FRAG_DEPTH_LAYOUT_GREATER
:
6310 return BRW_PSCDEPTH_ON_GE
;
6311 case FRAG_DEPTH_LAYOUT_LESS
:
6312 return BRW_PSCDEPTH_ON_LE
;
6313 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6314 return BRW_PSCDEPTH_OFF
;
6317 return BRW_PSCDEPTH_OFF
;
6321 * Move load_interpolated_input with simple (payload-based) barycentric modes
6322 * to the top of the program so we don't emit multiple PLNs for the same input.
6324 * This works around CSE not being able to handle non-dominating cases
6330 * interpolate the same exact input
6333 * This should be replaced by global value numbering someday.
6336 move_interpolation_to_top(nir_shader
*nir
)
6338 nir_foreach_function(f
, nir
) {
6342 nir_block
*top
= nir_start_block(f
->impl
);
6344 nir_foreach_block(block
, f
->impl
) {
6348 nir_foreach_instr_reverse_safe(instr
, block
) {
6349 if (instr
->type
!= nir_instr_type_intrinsic
)
6352 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6353 switch (intrin
->intrinsic
) {
6354 case nir_intrinsic_load_barycentric_pixel
:
6355 case nir_intrinsic_load_barycentric_centroid
:
6356 case nir_intrinsic_load_barycentric_sample
:
6358 case nir_intrinsic_load_interpolated_input
: {
6359 nir_intrinsic_instr
*bary_intrinsic
=
6360 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6361 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
6363 /* Leave interpolateAtSample/Offset() where it is. */
6364 if (op
== nir_intrinsic_load_barycentric_at_sample
||
6365 op
== nir_intrinsic_load_barycentric_at_offset
)
6372 exec_node_remove(&instr
->node
);
6373 exec_list_push_head(&top
->instr_list
, &instr
->node
);
6377 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6378 ((unsigned) nir_metadata_block_index
|
6379 (unsigned) nir_metadata_dominance
));
6384 * Apply default interpolation settings to FS inputs which don't specify any.
6387 brw_nir_set_default_interpolation(const struct brw_device_info
*devinfo
,
6388 struct nir_shader
*nir
,
6389 bool api_flat_shade
,
6390 bool per_sample_interpolation
)
6392 assert(nir
->stage
== MESA_SHADER_FRAGMENT
);
6394 nir_foreach_variable(var
, &nir
->inputs
) {
6395 /* Apply default interpolation mode.
6397 * Everything defaults to smooth except for the legacy GL color
6398 * built-in variables, which might be flat depending on API state.
6400 if (var
->data
.interpolation
== INTERP_MODE_NONE
) {
6401 const bool flat
= api_flat_shade
&&
6402 (var
->data
.location
== VARYING_SLOT_COL0
||
6403 var
->data
.location
== VARYING_SLOT_COL1
);
6405 var
->data
.interpolation
= flat
? INTERP_MODE_FLAT
6406 : INTERP_MODE_SMOOTH
;
6409 /* Apply 'sample' if necessary for API state. */
6410 if (per_sample_interpolation
&&
6411 var
->data
.interpolation
!= INTERP_MODE_FLAT
) {
6412 var
->data
.centroid
= false;
6413 var
->data
.sample
= true;
6416 /* On Ironlake and below, there is only one interpolation mode.
6417 * Centroid interpolation doesn't mean anything on this hardware --
6418 * there is no multisampling.
6420 if (devinfo
->gen
< 6) {
6421 var
->data
.centroid
= false;
6422 var
->data
.sample
= false;
6428 * Demote per-sample barycentric intrinsics to centroid.
6430 * Useful when rendering to a non-multisampled buffer.
6433 demote_sample_qualifiers(nir_shader
*nir
)
6435 nir_foreach_function(f
, nir
) {
6440 nir_builder_init(&b
, f
->impl
);
6442 nir_foreach_block(block
, f
->impl
) {
6443 nir_foreach_instr_safe(instr
, block
) {
6444 if (instr
->type
!= nir_instr_type_intrinsic
)
6447 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6448 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
6449 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
6452 b
.cursor
= nir_before_instr(instr
);
6453 nir_ssa_def
*centroid
=
6454 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
6455 nir_intrinsic_interp_mode(intrin
));
6456 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
6457 nir_src_for_ssa(centroid
));
6458 nir_instr_remove(instr
);
6462 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6463 ((unsigned) nir_metadata_block_index
|
6464 (unsigned) nir_metadata_dominance
));
6469 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6471 const struct brw_wm_prog_key
*key
,
6472 struct brw_wm_prog_data
*prog_data
,
6473 const nir_shader
*src_shader
,
6474 struct gl_program
*prog
,
6475 int shader_time_index8
, int shader_time_index16
,
6476 bool allow_spilling
,
6478 unsigned *final_assembly_size
,
6481 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6482 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6484 brw_nir_set_default_interpolation(compiler
->devinfo
, shader
,
6485 key
->flat_shade
, key
->persample_interp
);
6486 brw_nir_lower_fs_inputs(shader
);
6487 brw_nir_lower_fs_outputs(shader
);
6488 if (!key
->multisample_fbo
)
6489 NIR_PASS_V(shader
, demote_sample_qualifiers
);
6490 NIR_PASS_V(shader
, move_interpolation_to_top
);
6491 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6493 /* key->alpha_test_func means simulating alpha testing via discards,
6494 * so the shader definitely kills pixels.
6496 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
6497 prog_data
->uses_omask
= key
->multisample_fbo
&&
6498 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6499 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6500 prog_data
->computed_stencil
=
6501 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6503 prog_data
->persample_dispatch
=
6504 key
->multisample_fbo
&&
6505 (key
->persample_interp
||
6506 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6507 SYSTEM_BIT_SAMPLE_POS
)) ||
6508 shader
->info
.fs
.uses_sample_qualifier
);
6510 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
6512 prog_data
->barycentric_interp_modes
=
6513 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
6515 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6516 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6517 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6519 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6520 &prog_data
->base
, prog
, shader
, 8,
6521 shader_time_index8
);
6522 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6524 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6527 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6529 simd8_grf_start
= v8
.payload
.num_regs
;
6530 simd8_grf_used
= v8
.grf_used
;
6533 if (v8
.max_dispatch_width
>= 16 &&
6534 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6535 /* Try a SIMD16 compile */
6536 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6537 &prog_data
->base
, prog
, shader
, 16,
6538 shader_time_index16
);
6539 v16
.import_uniforms(&v8
);
6540 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6541 compiler
->shader_perf_log(log_data
,
6542 "SIMD16 shader failed to compile: %s",
6545 simd16_cfg
= v16
.cfg
;
6546 simd16_grf_start
= v16
.payload
.num_regs
;
6547 simd16_grf_used
= v16
.grf_used
;
6551 /* When the caller requests a repclear shader, they want SIMD16-only */
6555 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6556 * at the top to select the shader. We've never implemented that.
6557 * Instead, we just give them exactly one shader and we pick the widest one
6560 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6563 if (prog_data
->persample_dispatch
) {
6564 /* Starting with SandyBridge (where we first get MSAA), the different
6565 * pixel dispatch combinations are grouped into classifications A
6566 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6567 * generations, the only configurations supporting persample dispatch
6568 * are are this in which only one dispatch width is enabled.
6570 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6571 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6573 if (compiler
->devinfo
->gen
== 6 &&
6574 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6576 } else if (simd16_cfg
) {
6581 /* We have to compute the flat inputs after the visitor is finished running
6582 * because it relies on prog_data->urb_setup which is computed in
6583 * fs_visitor::calculate_urb_setup().
6585 brw_compute_flat_inputs(prog_data
, shader
);
6587 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6588 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6589 MESA_SHADER_FRAGMENT
);
6591 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6592 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6593 shader
->info
.label
? shader
->info
.label
:
6595 shader
->info
.name
));
6599 prog_data
->dispatch_8
= true;
6600 g
.generate_code(simd8_cfg
, 8);
6601 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6602 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6605 prog_data
->dispatch_16
= true;
6606 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6607 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6608 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6610 } else if (simd16_cfg
) {
6611 prog_data
->dispatch_16
= true;
6612 g
.generate_code(simd16_cfg
, 16);
6613 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6614 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6617 return g
.get_assembly(final_assembly_size
);
6621 fs_visitor::emit_cs_work_group_id_setup()
6623 assert(stage
== MESA_SHADER_COMPUTE
);
6625 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6627 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6628 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6629 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6631 bld
.MOV(*reg
, r0_1
);
6632 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6633 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6639 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
6641 block
->dwords
= dwords
;
6642 block
->regs
= DIV_ROUND_UP(dwords
, 8);
6643 block
->size
= block
->regs
* 32;
6647 cs_fill_push_const_info(const struct brw_device_info
*devinfo
,
6648 struct brw_cs_prog_data
*cs_prog_data
)
6650 const struct brw_stage_prog_data
*prog_data
=
6651 (struct brw_stage_prog_data
*) cs_prog_data
;
6652 bool fill_thread_id
=
6653 cs_prog_data
->thread_local_id_index
>= 0 &&
6654 cs_prog_data
->thread_local_id_index
< (int)prog_data
->nr_params
;
6655 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
6657 /* The thread ID should be stored in the last param dword */
6658 assert(prog_data
->nr_params
> 0 || !fill_thread_id
);
6659 assert(!fill_thread_id
||
6660 cs_prog_data
->thread_local_id_index
==
6661 (int)prog_data
->nr_params
- 1);
6663 unsigned cross_thread_dwords
, per_thread_dwords
;
6664 if (!cross_thread_supported
) {
6665 cross_thread_dwords
= 0u;
6666 per_thread_dwords
= prog_data
->nr_params
;
6667 } else if (fill_thread_id
) {
6668 /* Fill all but the last register with cross-thread payload */
6669 cross_thread_dwords
= 8 * (cs_prog_data
->thread_local_id_index
/ 8);
6670 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
6671 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
6673 /* Fill all data using cross-thread payload */
6674 cross_thread_dwords
= prog_data
->nr_params
;
6675 per_thread_dwords
= 0u;
6678 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
6679 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
6681 unsigned total_dwords
=
6682 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
6683 cs_prog_data
->push
.cross_thread
.size
) / 4;
6684 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
6686 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
6687 cs_prog_data
->push
.per_thread
.size
== 0);
6688 assert(cs_prog_data
->push
.cross_thread
.dwords
+
6689 cs_prog_data
->push
.per_thread
.dwords
==
6690 prog_data
->nr_params
);
6694 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
6696 cs_prog_data
->simd_size
= size
;
6697 unsigned group_size
= cs_prog_data
->local_size
[0] *
6698 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
6699 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
6703 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6705 const struct brw_cs_prog_key
*key
,
6706 struct brw_cs_prog_data
*prog_data
,
6707 const nir_shader
*src_shader
,
6708 int shader_time_index
,
6709 unsigned *final_assembly_size
,
6712 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6713 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6715 brw_nir_lower_cs_shared(shader
);
6716 prog_data
->base
.total_shared
+= shader
->num_shared
;
6718 /* Now that we cloned the nir_shader, we can update num_uniforms based on
6719 * the thread_local_id_index.
6721 assert(prog_data
->thread_local_id_index
>= 0);
6722 shader
->num_uniforms
=
6723 MAX2(shader
->num_uniforms
,
6724 (unsigned)4 * (prog_data
->thread_local_id_index
+ 1));
6726 brw_nir_lower_intrinsics(shader
, &prog_data
->base
);
6727 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6729 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
6730 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
6731 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
6732 unsigned local_workgroup_size
=
6733 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
6734 shader
->info
.cs
.local_size
[2];
6736 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
6737 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
6740 const char *fail_msg
= NULL
;
6742 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6744 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6745 NULL
, /* Never used in core profile */
6746 shader
, 8, shader_time_index
);
6747 if (simd_required
<= 8) {
6749 fail_msg
= v8
.fail_msg
;
6752 cs_set_simd_size(prog_data
, 8);
6753 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6754 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
6758 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6759 NULL
, /* Never used in core profile */
6760 shader
, 16, shader_time_index
);
6761 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6762 !fail_msg
&& v8
.max_dispatch_width
>= 16 &&
6763 simd_required
<= 16) {
6764 /* Try a SIMD16 compile */
6765 if (simd_required
<= 8)
6766 v16
.import_uniforms(&v8
);
6767 if (!v16
.run_cs()) {
6768 compiler
->shader_perf_log(log_data
,
6769 "SIMD16 shader failed to compile: %s",
6773 "Couldn't generate SIMD16 program and not "
6774 "enough threads for SIMD8";
6778 cs_set_simd_size(prog_data
, 16);
6779 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6780 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
6784 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6785 NULL
, /* Never used in core profile */
6786 shader
, 32, shader_time_index
);
6787 if (!fail_msg
&& v8
.max_dispatch_width
>= 32 &&
6788 (simd_required
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
6789 /* Try a SIMD32 compile */
6790 if (simd_required
<= 8)
6791 v32
.import_uniforms(&v8
);
6792 else if (simd_required
<= 16)
6793 v32
.import_uniforms(&v16
);
6795 if (!v32
.run_cs()) {
6796 compiler
->shader_perf_log(log_data
,
6797 "SIMD32 shader failed to compile: %s",
6801 "Couldn't generate SIMD32 program and not "
6802 "enough threads for SIMD16";
6806 cs_set_simd_size(prog_data
, 32);
6807 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6811 if (unlikely(cfg
== NULL
)) {
6814 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6819 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6820 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6821 MESA_SHADER_COMPUTE
);
6822 if (INTEL_DEBUG
& DEBUG_CS
) {
6823 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6824 shader
->info
.label
? shader
->info
.label
:
6827 g
.enable_debug(name
);
6830 g
.generate_code(cfg
, prog_data
->simd_size
);
6832 return g
.get_assembly(final_assembly_size
);