2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "compiler/glsl_types.h"
42 #include "program/prog_parameter.h"
46 static unsigned get_lowered_simd_width(const struct brw_device_info
*devinfo
,
50 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
51 const fs_reg
*src
, unsigned sources
)
53 memset(this, 0, sizeof(*this));
55 this->src
= new fs_reg
[MAX2(sources
, 3)];
56 for (unsigned i
= 0; i
< sources
; i
++)
57 this->src
[i
] = src
[i
];
59 this->opcode
= opcode
;
61 this->sources
= sources
;
62 this->exec_size
= exec_size
;
65 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
67 assert(this->exec_size
!= 0);
69 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
71 /* This will be the case for almost all instructions. */
78 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
82 this->regs_written
= 0;
86 unreachable("Invalid destination register file");
89 this->writes_accumulator
= false;
94 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
99 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
104 init(opcode
, exec_size
, dst
, NULL
, 0);
107 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg src
[1] = { src0
};
111 init(opcode
, exec_size
, dst
, src
, 1);
114 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
115 const fs_reg
&src0
, const fs_reg
&src1
)
117 const fs_reg src
[2] = { src0
, src1
};
118 init(opcode
, exec_size
, dst
, src
, 2);
121 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
122 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
124 const fs_reg src
[3] = { src0
, src1
, src2
};
125 init(opcode
, exec_size
, dst
, src
, 3);
128 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
129 const fs_reg src
[], unsigned sources
)
131 init(opcode
, exec_width
, dst
, src
, sources
);
134 fs_inst::fs_inst(const fs_inst
&that
)
136 memcpy(this, &that
, sizeof(that
));
138 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
140 for (unsigned i
= 0; i
< that
.sources
; i
++)
141 this->src
[i
] = that
.src
[i
];
150 fs_inst::resize_sources(uint8_t num_sources
)
152 if (this->sources
!= num_sources
) {
153 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
155 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
156 src
[i
] = this->src
[i
];
160 this->sources
= num_sources
;
165 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
167 const fs_reg
&surf_index
,
168 const fs_reg
&varying_offset
,
169 uint32_t const_offset
)
171 /* We have our constant surface use a pitch of 4 bytes, so our index can
172 * be any component of a vector, and then we load 4 contiguous
173 * components starting from that.
175 * We break down the const_offset to a portion added to the variable
176 * offset and a portion done using reg_offset, which means that if you
177 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
178 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
179 * CSE can later notice that those loads are all the same and eliminate
180 * the redundant ones.
182 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
183 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
185 /* The pull load message will load a vec4 (16 bytes). If we are loading
186 * a double this means we are only loading 2 elements worth of data.
187 * We also want to use a 32-bit data type for the dst of the load operation
188 * so other parts of the driver don't get confused about the size of the
191 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
192 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
193 vec4_result
, surf_index
, vec4_offset
);
194 inst
->regs_written
= 4 * bld
.dispatch_width() / 8;
196 if (type_sz(dst
.type
) == 8) {
197 shuffle_32bit_load_result_to_64bit_data(
198 bld
, retype(vec4_result
, dst
.type
), vec4_result
, 2);
201 vec4_result
.type
= dst
.type
;
202 bld
.MOV(dst
, offset(vec4_result
, bld
,
203 (const_offset
& 0xf) / type_sz(vec4_result
.type
)));
207 * A helper for MOV generation for fixing up broken hardware SEND dependency
211 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
213 /* The caller always wants uncompressed to emit the minimal extra
214 * dependencies, and to avoid having to deal with aligning its regs to 2.
216 const fs_builder ubld
= bld
.annotate("send dependency resolve")
219 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
223 fs_inst::equals(fs_inst
*inst
) const
225 return (opcode
== inst
->opcode
&&
226 dst
.equals(inst
->dst
) &&
227 src
[0].equals(inst
->src
[0]) &&
228 src
[1].equals(inst
->src
[1]) &&
229 src
[2].equals(inst
->src
[2]) &&
230 saturate
== inst
->saturate
&&
231 predicate
== inst
->predicate
&&
232 conditional_mod
== inst
->conditional_mod
&&
233 mlen
== inst
->mlen
&&
234 base_mrf
== inst
->base_mrf
&&
235 target
== inst
->target
&&
237 header_size
== inst
->header_size
&&
238 shadow_compare
== inst
->shadow_compare
&&
239 exec_size
== inst
->exec_size
&&
240 offset
== inst
->offset
);
244 fs_inst::overwrites_reg(const fs_reg
®
) const
246 return reg
.in_range(dst
, regs_written
);
250 fs_inst::is_send_from_grf() const
253 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
254 case SHADER_OPCODE_SHADER_TIME_ADD
:
255 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
256 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
257 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
258 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
259 case SHADER_OPCODE_UNTYPED_ATOMIC
:
260 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
261 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
262 case SHADER_OPCODE_TYPED_ATOMIC
:
263 case SHADER_OPCODE_TYPED_SURFACE_READ
:
264 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
265 case SHADER_OPCODE_URB_WRITE_SIMD8
:
266 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
267 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
268 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
269 case SHADER_OPCODE_URB_READ_SIMD8
:
270 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
272 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
273 return src
[1].file
== VGRF
;
274 case FS_OPCODE_FB_WRITE
:
275 return src
[0].file
== VGRF
;
278 return src
[0].file
== VGRF
;
285 * Returns true if this instruction's sources and destinations cannot
286 * safely be the same register.
288 * In most cases, a register can be written over safely by the same
289 * instruction that is its last use. For a single instruction, the
290 * sources are dereferenced before writing of the destination starts
293 * However, there are a few cases where this can be problematic:
295 * - Virtual opcodes that translate to multiple instructions in the
296 * code generator: if src == dst and one instruction writes the
297 * destination before a later instruction reads the source, then
298 * src will have been clobbered.
300 * - SIMD16 compressed instructions with certain regioning (see below).
302 * The register allocator uses this information to set up conflicts between
303 * GRF sources and the destination.
306 fs_inst::has_source_and_destination_hazard() const
309 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
310 /* Multiple partial writes to the destination */
313 /* The SIMD16 compressed instruction
315 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
317 * is actually decoded in hardware as:
319 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
320 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
322 * Which is safe. However, if we have uniform accesses
323 * happening, we get into trouble:
325 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
326 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
328 * Now our destination for the first instruction overwrote the
329 * second instruction's src0, and we get garbage for those 8
330 * pixels. There's a similar issue for the pre-gen6
331 * pixel_x/pixel_y, which are registers of 16-bit values and thus
332 * would get stomped by the first decode as well.
334 if (exec_size
== 16) {
335 for (int i
= 0; i
< sources
; i
++) {
336 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
337 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
338 src
[i
].type
== BRW_REGISTER_TYPE_W
||
339 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
340 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
350 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
352 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
355 fs_reg reg
= this->src
[0];
356 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
359 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
362 for (int i
= 0; i
< this->sources
; i
++) {
363 reg
.type
= this->src
[i
].type
;
364 if (!this->src
[i
].equals(reg
))
367 if (i
< this->header_size
) {
370 reg
= horiz_offset(reg
, this->exec_size
);
378 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
380 if (devinfo
->gen
== 6 && is_math())
383 if (is_send_from_grf())
386 if (!backend_instruction::can_do_source_mods())
393 fs_inst::can_change_types() const
395 return dst
.type
== src
[0].type
&&
396 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
397 (opcode
== BRW_OPCODE_MOV
||
398 (opcode
== BRW_OPCODE_SEL
&&
399 dst
.type
== src
[1].type
&&
400 predicate
!= BRW_PREDICATE_NONE
&&
401 !src
[1].abs
&& !src
[1].negate
));
405 fs_inst::has_side_effects() const
407 return this->eot
|| backend_instruction::has_side_effects();
413 memset(this, 0, sizeof(*this));
417 /** Generic unset register constructor. */
421 this->file
= BAD_FILE
;
424 fs_reg::fs_reg(struct ::brw_reg reg
) :
427 this->reg_offset
= 0;
428 this->subreg_offset
= 0;
430 if (this->file
== IMM
&&
431 (this->type
!= BRW_REGISTER_TYPE_V
&&
432 this->type
!= BRW_REGISTER_TYPE_UV
&&
433 this->type
!= BRW_REGISTER_TYPE_VF
)) {
439 fs_reg::equals(const fs_reg
&r
) const
441 return (this->backend_reg::equals(r
) &&
442 subreg_offset
== r
.subreg_offset
&&
447 fs_reg::set_smear(unsigned subreg
)
449 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
450 subreg_offset
= subreg
* type_sz(type
);
456 fs_reg::is_contiguous() const
462 fs_reg::component_size(unsigned width
) const
464 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
467 return MAX2(width
* stride
, 1) * type_sz(type
);
471 type_size_scalar(const struct glsl_type
*type
)
473 unsigned int size
, i
;
475 switch (type
->base_type
) {
478 case GLSL_TYPE_FLOAT
:
480 return type
->components();
481 case GLSL_TYPE_DOUBLE
:
482 return type
->components() * 2;
483 case GLSL_TYPE_ARRAY
:
484 return type_size_scalar(type
->fields
.array
) * type
->length
;
485 case GLSL_TYPE_STRUCT
:
487 for (i
= 0; i
< type
->length
; i
++) {
488 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
491 case GLSL_TYPE_SAMPLER
:
492 /* Samplers take up no register space, since they're baked in at
496 case GLSL_TYPE_ATOMIC_UINT
:
498 case GLSL_TYPE_SUBROUTINE
:
500 case GLSL_TYPE_IMAGE
:
501 return BRW_IMAGE_PARAM_SIZE
;
503 case GLSL_TYPE_ERROR
:
504 case GLSL_TYPE_INTERFACE
:
505 case GLSL_TYPE_FUNCTION
:
506 unreachable("not reached");
512 /* Attribute arrays are loaded as one vec4 per element (or matrix column),
513 * except for double-precision types, which are loaded as one dvec4.
516 type_size_vs_input(const struct glsl_type
*type
)
518 if (type
->is_double()) {
519 return type_size_dvec4(type
);
521 return type_size_vec4(type
);
526 * Create a MOV to read the timestamp register.
528 * The caller is responsible for emitting the MOV. The return value is
529 * the destination of the MOV, with extra parameters set.
532 fs_visitor::get_timestamp(const fs_builder
&bld
)
534 assert(devinfo
->gen
>= 7);
536 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
539 BRW_REGISTER_TYPE_UD
));
541 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
543 /* We want to read the 3 fields we care about even if it's not enabled in
546 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
552 fs_visitor::emit_shader_time_begin()
554 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
556 /* We want only the low 32 bits of the timestamp. Since it's running
557 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
558 * which is plenty of time for our purposes. It is identical across the
559 * EUs, but since it's tracking GPU core speed it will increment at a
560 * varying rate as render P-states change.
562 shader_start_time
.set_smear(0);
566 fs_visitor::emit_shader_time_end()
568 /* Insert our code just before the final SEND with EOT. */
569 exec_node
*end
= this->instructions
.get_tail();
570 assert(end
&& ((fs_inst
*) end
)->eot
);
571 const fs_builder ibld
= bld
.annotate("shader time end")
572 .exec_all().at(NULL
, end
);
574 fs_reg shader_end_time
= get_timestamp(ibld
);
576 /* We only use the low 32 bits of the timestamp - see
577 * emit_shader_time_begin()).
579 * We could also check if render P-states have changed (or anything
580 * else that might disrupt timing) by setting smear to 2 and checking if
581 * that field is != 0.
583 shader_end_time
.set_smear(0);
585 /* Check that there weren't any timestamp reset events (assuming these
586 * were the only two timestamp reads that happened).
588 fs_reg reset
= shader_end_time
;
590 set_condmod(BRW_CONDITIONAL_Z
,
591 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
592 ibld
.IF(BRW_PREDICATE_NORMAL
);
594 fs_reg start
= shader_start_time
;
596 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
599 const fs_builder cbld
= ibld
.group(1, 0);
600 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
602 /* If there were no instructions between the two timestamp gets, the diff
603 * is 2 cycles. Remove that overhead, so I can forget about that when
604 * trying to determine the time taken for single instructions.
606 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
607 SHADER_TIME_ADD(cbld
, 0, diff
);
608 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
609 ibld
.emit(BRW_OPCODE_ELSE
);
610 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
611 ibld
.emit(BRW_OPCODE_ENDIF
);
615 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
616 int shader_time_subindex
,
619 int index
= shader_time_index
* 3 + shader_time_subindex
;
620 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
623 if (dispatch_width
== 8)
624 payload
= vgrf(glsl_type::uvec2_type
);
626 payload
= vgrf(glsl_type::uint_type
);
628 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
632 fs_visitor::vfail(const char *format
, va_list va
)
641 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
642 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
644 this->fail_msg
= msg
;
647 fprintf(stderr
, "%s", msg
);
652 fs_visitor::fail(const char *format
, ...)
656 va_start(va
, format
);
662 * Mark this program as impossible to compile with dispatch width greater
665 * During the SIMD8 compile (which happens first), we can detect and flag
666 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
667 * SIMD16+ compile altogether.
669 * During a compile of dispatch width greater than n (if one happens anyway),
670 * this just calls fail().
673 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
675 if (dispatch_width
> n
) {
678 max_dispatch_width
= n
;
679 compiler
->shader_perf_log(log_data
,
680 "Shader dispatch width limited to SIMD%d: %s",
686 * Returns true if the instruction has a flag that means it won't
687 * update an entire destination register.
689 * For example, dead code elimination and live variable analysis want to know
690 * when a write to a variable screens off any preceding values that were in
694 fs_inst::is_partial_write() const
696 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
697 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
698 !this->dst
.is_contiguous() ||
699 this->dst
.subreg_offset
> 0);
703 fs_inst::components_read(unsigned i
) const
706 case FS_OPCODE_LINTERP
:
712 case FS_OPCODE_PIXEL_X
:
713 case FS_OPCODE_PIXEL_Y
:
717 case FS_OPCODE_FB_WRITE_LOGICAL
:
718 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
719 /* First/second FB write color. */
721 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
725 case SHADER_OPCODE_TEX_LOGICAL
:
726 case SHADER_OPCODE_TXD_LOGICAL
:
727 case SHADER_OPCODE_TXF_LOGICAL
:
728 case SHADER_OPCODE_TXL_LOGICAL
:
729 case SHADER_OPCODE_TXS_LOGICAL
:
730 case FS_OPCODE_TXB_LOGICAL
:
731 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
732 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
733 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
734 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
735 case SHADER_OPCODE_LOD_LOGICAL
:
736 case SHADER_OPCODE_TG4_LOGICAL
:
737 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
738 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
739 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
740 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
741 /* Texture coordinates. */
742 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
743 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
744 /* Texture derivatives. */
745 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
746 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
747 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
748 /* Texture offset. */
749 else if (i
== TEX_LOGICAL_SRC_OFFSET_VALUE
)
752 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
757 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
758 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
759 assert(src
[3].file
== IMM
);
760 /* Surface coordinates. */
763 /* Surface operation source (ignored for reads). */
769 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
770 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
771 assert(src
[3].file
== IMM
&&
773 /* Surface coordinates. */
776 /* Surface operation source. */
782 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
783 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
784 assert(src
[3].file
== IMM
&&
786 const unsigned op
= src
[4].ud
;
787 /* Surface coordinates. */
790 /* Surface operation source. */
791 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
793 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
794 op
== BRW_AOP_PREDEC
))
806 fs_inst::regs_read(int arg
) const
809 case FS_OPCODE_FB_WRITE
:
810 case SHADER_OPCODE_URB_WRITE_SIMD8
:
811 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
812 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
813 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
814 case SHADER_OPCODE_URB_READ_SIMD8
:
815 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
816 case SHADER_OPCODE_UNTYPED_ATOMIC
:
817 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
818 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
819 case SHADER_OPCODE_TYPED_ATOMIC
:
820 case SHADER_OPCODE_TYPED_SURFACE_READ
:
821 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
822 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
827 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
828 /* The payload is actually stored in src1 */
833 case FS_OPCODE_LINTERP
:
838 case SHADER_OPCODE_LOAD_PAYLOAD
:
839 if (arg
< this->header_size
)
843 case CS_OPCODE_CS_TERMINATE
:
844 case SHADER_OPCODE_BARRIER
:
847 case SHADER_OPCODE_MOV_INDIRECT
:
849 assert(src
[2].file
== IMM
);
850 unsigned region_length
= src
[2].ud
;
852 if (src
[0].file
== UNIFORM
) {
853 assert(region_length
% 4 == 0);
854 return region_length
/ 4;
855 } else if (src
[0].file
== FIXED_GRF
) {
856 /* If the start of the region is not register aligned, then
857 * there's some portion of the register that's technically
858 * unread at the beginning.
860 * However, the register allocator works in terms of whole
861 * registers, and does not use subnr. It assumes that the
862 * read starts at the beginning of the register, and extends
863 * regs_read() whole registers beyond that.
865 * To compensate, we extend the region length to include this
866 * unread portion at the beginning.
869 region_length
+= src
[0].subnr
;
871 return DIV_ROUND_UP(region_length
, REG_SIZE
);
873 assert(!"Invalid register file");
879 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
884 switch (src
[arg
].file
) {
894 return DIV_ROUND_UP(components_read(arg
) *
895 src
[arg
].component_size(exec_size
),
898 unreachable("MRF registers are not allowed as sources");
904 /* Return the subset of flag registers that an instruction could
905 * potentially read or write based on the execution controls and flag
906 * subregister number of the instruction.
909 flag_mask(const fs_inst
*inst
)
911 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
912 const unsigned end
= start
+ inst
->exec_size
;
913 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
918 fs_inst::flags_read(const brw_device_info
*devinfo
) const
920 /* XXX - This doesn't consider explicit uses of the flag register as source
923 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
924 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
925 /* The vertical predication modes combine corresponding bits from
926 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
928 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
929 return flag_mask(this) << shift
| flag_mask(this);
930 } else if (predicate
) {
931 return flag_mask(this);
938 fs_inst::flags_written() const
940 /* XXX - This doesn't consider explicit uses of the flag register as
941 * destination region.
943 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
944 opcode
!= BRW_OPCODE_IF
&&
945 opcode
!= BRW_OPCODE_WHILE
)) ||
946 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
947 return flag_mask(this);
954 * Returns how many MRFs an FS opcode will write over.
956 * Note that this is not the 0 or 1 implied writes in an actual gen
957 * instruction -- the FS opcodes often generate MOVs in addition.
960 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
965 if (inst
->base_mrf
== -1)
968 switch (inst
->opcode
) {
969 case SHADER_OPCODE_RCP
:
970 case SHADER_OPCODE_RSQ
:
971 case SHADER_OPCODE_SQRT
:
972 case SHADER_OPCODE_EXP2
:
973 case SHADER_OPCODE_LOG2
:
974 case SHADER_OPCODE_SIN
:
975 case SHADER_OPCODE_COS
:
976 return 1 * dispatch_width
/ 8;
977 case SHADER_OPCODE_POW
:
978 case SHADER_OPCODE_INT_QUOTIENT
:
979 case SHADER_OPCODE_INT_REMAINDER
:
980 return 2 * dispatch_width
/ 8;
981 case SHADER_OPCODE_TEX
:
983 case SHADER_OPCODE_TXD
:
984 case SHADER_OPCODE_TXF
:
985 case SHADER_OPCODE_TXF_CMS
:
986 case SHADER_OPCODE_TXF_MCS
:
987 case SHADER_OPCODE_TG4
:
988 case SHADER_OPCODE_TG4_OFFSET
:
989 case SHADER_OPCODE_TXL
:
990 case SHADER_OPCODE_TXS
:
991 case SHADER_OPCODE_LOD
:
992 case SHADER_OPCODE_SAMPLEINFO
:
994 case FS_OPCODE_FB_WRITE
:
996 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
997 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
999 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1001 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1004 unreachable("not reached");
1009 fs_visitor::vgrf(const glsl_type
*const type
)
1011 int reg_width
= dispatch_width
/ 8;
1012 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
1013 brw_type_for_base_type(type
));
1016 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1021 this->type
= BRW_REGISTER_TYPE_F
;
1022 this->stride
= (file
== UNIFORM
? 0 : 1);
1025 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1031 this->stride
= (file
== UNIFORM
? 0 : 1);
1034 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1035 * This brings in those uniform definitions
1038 fs_visitor::import_uniforms(fs_visitor
*v
)
1040 this->push_constant_loc
= v
->push_constant_loc
;
1041 this->pull_constant_loc
= v
->pull_constant_loc
;
1042 this->uniforms
= v
->uniforms
;
1046 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1048 assert(stage
== MESA_SHADER_FRAGMENT
);
1050 /* gl_FragCoord.x */
1051 bld
.MOV(wpos
, this->pixel_x
);
1052 wpos
= offset(wpos
, bld
, 1);
1054 /* gl_FragCoord.y */
1055 bld
.MOV(wpos
, this->pixel_y
);
1056 wpos
= offset(wpos
, bld
, 1);
1058 /* gl_FragCoord.z */
1059 if (devinfo
->gen
>= 6) {
1060 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1062 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1063 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1064 interp_reg(VARYING_SLOT_POS
, 2));
1066 wpos
= offset(wpos
, bld
, 1);
1068 /* gl_FragCoord.w: Already set up in emit_interpolation */
1069 bld
.MOV(wpos
, this->wpos_w
);
1072 static enum brw_barycentric_mode
1073 barycentric_mode(enum glsl_interp_mode mode
,
1074 bool is_centroid
, bool is_sample
)
1078 /* Barycentric modes don't make sense for flat inputs. */
1079 assert(mode
!= INTERP_MODE_FLAT
);
1082 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1083 } else if (is_centroid
) {
1084 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1086 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1089 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1092 return (enum brw_barycentric_mode
) bary
;
1096 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1098 static enum brw_barycentric_mode
1099 centroid_to_pixel(enum brw_barycentric_mode bary
)
1101 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1102 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1103 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1107 fs_visitor::emit_general_interpolation(fs_reg
*attr
, const char *name
,
1108 const glsl_type
*type
,
1109 glsl_interp_mode interpolation_mode
,
1110 int *location
, bool mod_centroid
,
1113 assert(stage
== MESA_SHADER_FRAGMENT
);
1114 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1116 if (type
->is_array() || type
->is_matrix()) {
1117 const glsl_type
*elem_type
= glsl_get_array_element(type
);
1118 const unsigned length
= glsl_get_length(type
);
1120 for (unsigned i
= 0; i
< length
; i
++) {
1121 emit_general_interpolation(attr
, name
, elem_type
, interpolation_mode
,
1122 location
, mod_centroid
, mod_sample
);
1124 } else if (type
->is_record()) {
1125 for (unsigned i
= 0; i
< type
->length
; i
++) {
1126 const glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
1127 emit_general_interpolation(attr
, name
, field_type
, interpolation_mode
,
1128 location
, mod_centroid
, mod_sample
);
1131 assert(type
->is_scalar() || type
->is_vector());
1133 if (prog_data
->urb_setup
[*location
] == -1) {
1134 /* If there's no incoming setup data for this slot, don't
1135 * emit interpolation for it.
1137 *attr
= offset(*attr
, bld
, type
->vector_elements
);
1142 attr
->type
= brw_type_for_base_type(type
->get_scalar_type());
1144 if (interpolation_mode
== INTERP_MODE_FLAT
) {
1145 /* Constant interpolation (flat shading) case. The SF has
1146 * handed us defined values in only the constant offset
1147 * field of the setup reg.
1149 unsigned vector_elements
= type
->vector_elements
;
1151 /* Data starts at suboffet 3 in 32-bit units (12 bytes), so it is not
1152 * 64-bit aligned and the current implementation fails to read the
1153 * data properly. Instead, when there is a double input varying,
1154 * read it as vector of floats with twice the number of components.
1156 if (attr
->type
== BRW_REGISTER_TYPE_DF
) {
1157 vector_elements
*= 2;
1158 attr
->type
= BRW_REGISTER_TYPE_F
;
1160 for (unsigned int i
= 0; i
< vector_elements
; i
++) {
1161 struct brw_reg interp
= interp_reg(*location
, i
);
1162 interp
= suboffset(interp
, 3);
1163 interp
.type
= attr
->type
;
1164 bld
.emit(FS_OPCODE_CINTERP
, *attr
, fs_reg(interp
));
1165 *attr
= offset(*attr
, bld
, 1);
1168 /* Smooth/noperspective interpolation case. */
1169 enum brw_barycentric_mode bary
=
1170 barycentric_mode(interpolation_mode
, mod_centroid
, mod_sample
);
1172 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1173 fs_reg
interp(interp_reg(*location
, i
));
1174 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1175 /* Get the pixel/sample mask into f0 so that we know
1176 * which pixels are lit. Then, for each channel that is
1177 * unlit, replace the centroid data with non-centroid
1180 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1183 inst
= bld
.emit(FS_OPCODE_LINTERP
, *attr
,
1184 delta_xy
[centroid_to_pixel(bary
)], interp
);
1185 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1186 inst
->predicate_inverse
= true;
1187 inst
->no_dd_clear
= true;
1189 inst
= bld
.emit(FS_OPCODE_LINTERP
, *attr
,
1190 delta_xy
[bary
], interp
);
1191 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1192 inst
->predicate_inverse
= false;
1193 inst
->no_dd_check
= true;
1195 bld
.emit(FS_OPCODE_LINTERP
, *attr
, delta_xy
[bary
], interp
);
1197 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_MODE_SMOOTH
) {
1198 bld
.MUL(*attr
, *attr
, this->pixel_w
);
1200 *attr
= offset(*attr
, bld
, 1);
1208 fs_visitor::emit_frontfacing_interpolation()
1210 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1212 if (devinfo
->gen
>= 6) {
1213 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1214 * a boolean result from this (~0/true or 0/false).
1216 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1217 * this task in only one instruction:
1218 * - a negation source modifier will flip the bit; and
1219 * - a W -> D type conversion will sign extend the bit into the high
1220 * word of the destination.
1222 * An ASR 15 fills the low word of the destination.
1224 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1227 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1229 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1230 * a boolean result from this (1/true or 0/false).
1232 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1233 * the negation source modifier to flip it. Unfortunately the SHR
1234 * instruction only operates on UD (or D with an abs source modifier)
1235 * sources without negation.
1237 * Instead, use ASR (which will give ~0/true or 0/false).
1239 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1242 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1249 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1251 assert(stage
== MESA_SHADER_FRAGMENT
);
1252 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1253 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1255 if (wm_prog_data
->persample_dispatch
) {
1256 /* Convert int_sample_pos to floating point */
1257 bld
.MOV(dst
, int_sample_pos
);
1258 /* Scale to the range [0, 1] */
1259 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1262 /* From ARB_sample_shading specification:
1263 * "When rendering to a non-multisample buffer, or if multisample
1264 * rasterization is disabled, gl_SamplePosition will always be
1267 bld
.MOV(dst
, brw_imm_f(0.5f
));
1272 fs_visitor::emit_samplepos_setup()
1274 assert(devinfo
->gen
>= 6);
1276 const fs_builder abld
= bld
.annotate("compute sample position");
1277 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1279 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1280 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1282 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1283 * mode will be enabled.
1285 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1286 * R31.1:0 Position Offset X/Y for Slot[3:0]
1287 * R31.3:2 Position Offset X/Y for Slot[7:4]
1290 * The X, Y sample positions come in as bytes in thread payload. So, read
1291 * the positions using vstride=16, width=8, hstride=2.
1293 struct brw_reg sample_pos_reg
=
1294 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1295 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1297 if (dispatch_width
== 8) {
1298 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1300 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1301 abld
.half(1).MOV(half(int_sample_x
, 1),
1302 fs_reg(suboffset(sample_pos_reg
, 16)));
1304 /* Compute gl_SamplePosition.x */
1305 compute_sample_position(pos
, int_sample_x
);
1306 pos
= offset(pos
, abld
, 1);
1307 if (dispatch_width
== 8) {
1308 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1310 abld
.half(0).MOV(half(int_sample_y
, 0),
1311 fs_reg(suboffset(sample_pos_reg
, 1)));
1312 abld
.half(1).MOV(half(int_sample_y
, 1),
1313 fs_reg(suboffset(sample_pos_reg
, 17)));
1315 /* Compute gl_SamplePosition.y */
1316 compute_sample_position(pos
, int_sample_y
);
1321 fs_visitor::emit_sampleid_setup()
1323 assert(stage
== MESA_SHADER_FRAGMENT
);
1324 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1325 assert(devinfo
->gen
>= 6);
1327 const fs_builder abld
= bld
.annotate("compute sample id");
1328 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1330 if (!key
->multisample_fbo
) {
1331 /* As per GL_ARB_sample_shading specification:
1332 * "When rendering to a non-multisample buffer, or if multisample
1333 * rasterization is disabled, gl_SampleID will always be zero."
1335 abld
.MOV(*reg
, brw_imm_d(0));
1336 } else if (devinfo
->gen
>= 8) {
1337 /* Sample ID comes in as 4-bit numbers in g1.0:
1339 * 15:12 Slot 3 SampleID (only used in SIMD16)
1340 * 11:8 Slot 2 SampleID (only used in SIMD16)
1341 * 7:4 Slot 1 SampleID
1342 * 3:0 Slot 0 SampleID
1344 * Each slot corresponds to four channels, so we want to replicate each
1345 * half-byte value to 4 channels in a row:
1347 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1348 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1350 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1351 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1353 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1354 * channels to read the first byte (7:0), and the second group of 8
1355 * channels to read the second byte (15:8). Then, we shift right by
1356 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1357 * values into place. Finally, we AND with 0xf to keep the low nibble.
1359 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1360 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1362 * TODO: These payload bits exist on Gen7 too, but they appear to always
1363 * be zero, so this code fails to work. We should find out why.
1365 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1367 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1368 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1369 brw_imm_v(0x44440000));
1370 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1372 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1374 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1376 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1377 * 8x multisampling, subspan 0 will represent sample N (where N
1378 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1379 * 7. We can find the value of N by looking at R0.0 bits 7:6
1380 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1381 * (since samples are always delivered in pairs). That is, we
1382 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1383 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1384 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1385 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1386 * populating a temporary variable with the sequence (0, 1, 2, 3),
1387 * and then reading from it using vstride=1, width=4, hstride=0.
1388 * These computations hold good for 4x multisampling as well.
1390 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1391 * the first four slots are sample 0 of subspan 0; the next four
1392 * are sample 1 of subspan 0; the third group is sample 0 of
1393 * subspan 1, and finally sample 1 of subspan 1.
1396 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1397 * accomodate 16x MSAA.
1399 abld
.exec_all().group(1, 0)
1400 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1402 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1404 /* This works for both SIMD8 and SIMD16 */
1405 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1407 /* This special instruction takes care of setting vstride=1,
1408 * width=4, hstride=0 of t2 during an ADD instruction.
1410 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1417 fs_visitor::emit_samplemaskin_setup()
1419 assert(stage
== MESA_SHADER_FRAGMENT
);
1420 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1421 assert(devinfo
->gen
>= 6);
1423 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1425 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1426 BRW_REGISTER_TYPE_D
));
1428 if (wm_prog_data
->persample_dispatch
) {
1429 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1430 * and a mask representing which sample is being processed by the
1431 * current shader invocation.
1433 * From the OES_sample_variables specification:
1434 * "When per-sample shading is active due to the use of a fragment input
1435 * qualified by "sample" or due to the use of the gl_SampleID or
1436 * gl_SamplePosition variables, only the bit for the current sample is
1437 * set in gl_SampleMaskIn."
1439 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1441 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1442 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1444 fs_reg one
= vgrf(glsl_type::int_type
);
1445 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1446 abld
.MOV(one
, brw_imm_d(1));
1447 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1448 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1450 /* In per-pixel mode, the coverage mask is sufficient. */
1451 *reg
= coverage_mask
;
1457 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1459 if (!src
.abs
&& !src
.negate
)
1462 fs_reg temp
= bld
.vgrf(src
.type
);
1469 fs_visitor::emit_discard_jump()
1471 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1473 /* For performance, after a discard, jump to the end of the
1474 * shader if all relevant channels have been discarded.
1476 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1477 discard_jump
->flag_subreg
= 1;
1479 discard_jump
->predicate
= (dispatch_width
== 8)
1480 ? BRW_PREDICATE_ALIGN1_ANY8H
1481 : BRW_PREDICATE_ALIGN1_ANY16H
;
1482 discard_jump
->predicate_inverse
= true;
1486 fs_visitor::emit_gs_thread_end()
1488 assert(stage
== MESA_SHADER_GEOMETRY
);
1490 struct brw_gs_prog_data
*gs_prog_data
=
1491 (struct brw_gs_prog_data
*) prog_data
;
1493 if (gs_compile
->control_data_header_size_bits
> 0) {
1494 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1497 const fs_builder abld
= bld
.annotate("thread end");
1500 if (gs_prog_data
->static_vertex_count
!= -1) {
1501 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1502 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1503 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1504 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1505 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1508 /* Delete now dead instructions. */
1509 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1515 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1519 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1520 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1521 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1524 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1525 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1526 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1527 sources
[1] = this->final_gs_vertex_count
;
1528 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1529 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1537 fs_visitor::assign_curb_setup()
1539 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1541 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1542 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1543 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1544 if (inst
->src
[i
].file
== UNIFORM
) {
1545 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1547 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1548 constant_nr
= push_constant_loc
[uniform_nr
];
1550 /* Section 5.11 of the OpenGL 4.1 spec says:
1551 * "Out-of-bounds reads return undefined values, which include
1552 * values from other variables of the active program or zero."
1553 * Just return the first push constant.
1558 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1561 brw_reg
.abs
= inst
->src
[i
].abs
;
1562 brw_reg
.negate
= inst
->src
[i
].negate
;
1564 assert(inst
->src
[i
].stride
== 0);
1565 inst
->src
[i
] = byte_offset(
1566 retype(brw_reg
, inst
->src
[i
].type
),
1567 inst
->src
[i
].subreg_offset
);
1572 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1573 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1577 fs_visitor::calculate_urb_setup()
1579 assert(stage
== MESA_SHADER_FRAGMENT
);
1580 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1581 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1583 memset(prog_data
->urb_setup
, -1,
1584 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1587 /* Figure out where each of the incoming setup attributes lands. */
1588 if (devinfo
->gen
>= 6) {
1589 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1590 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1591 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1592 * first 16 varying inputs, so we can put them wherever we want.
1593 * Just put them in order.
1595 * This is useful because it means that (a) inputs not used by the
1596 * fragment shader won't take up valuable register space, and (b) we
1597 * won't have to recompile the fragment shader if it gets paired with
1598 * a different vertex (or geometry) shader.
1600 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1601 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1602 BITFIELD64_BIT(i
)) {
1603 prog_data
->urb_setup
[i
] = urb_next
++;
1607 bool include_vue_header
=
1608 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1610 /* We have enough input varyings that the SF/SBE pipeline stage can't
1611 * arbitrarily rearrange them to suit our whim; we have to put them
1612 * in an order that matches the output of the previous pipeline stage
1613 * (geometry or vertex shader).
1615 struct brw_vue_map prev_stage_vue_map
;
1616 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1617 key
->input_slots_valid
,
1618 nir
->info
.separate_shader
);
1620 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1622 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1623 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1625 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1626 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1627 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1628 BITFIELD64_BIT(varying
))) {
1629 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1632 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1635 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1636 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1637 /* Point size is packed into the header, not as a general attribute */
1638 if (i
== VARYING_SLOT_PSIZ
)
1641 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1642 /* The back color slot is skipped when the front color is
1643 * also written to. In addition, some slots can be
1644 * written in the vertex shader and not read in the
1645 * fragment shader. So the register number must always be
1646 * incremented, mapped or not.
1648 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1649 prog_data
->urb_setup
[i
] = urb_next
;
1655 * It's a FS only attribute, and we did interpolation for this attribute
1656 * in SF thread. So, count it here, too.
1658 * See compile_sf_prog() for more info.
1660 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1661 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1664 prog_data
->num_varying_inputs
= urb_next
;
1668 fs_visitor::assign_urb_setup()
1670 assert(stage
== MESA_SHADER_FRAGMENT
);
1671 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1673 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1675 /* Offset all the urb_setup[] index by the actual position of the
1676 * setup regs, now that the location of the constants has been chosen.
1678 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1679 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1680 assert(inst
->src
[1].file
== FIXED_GRF
);
1681 inst
->src
[1].nr
+= urb_start
;
1684 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1685 assert(inst
->src
[0].file
== FIXED_GRF
);
1686 inst
->src
[0].nr
+= urb_start
;
1690 /* Each attribute is 4 setup channels, each of which is half a reg. */
1691 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1695 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1697 for (int i
= 0; i
< inst
->sources
; i
++) {
1698 if (inst
->src
[i
].file
== ATTR
) {
1699 int grf
= payload
.num_regs
+
1700 prog_data
->curb_read_length
+
1702 inst
->src
[i
].reg_offset
;
1704 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1706 * VertStride must be used to cross GRF register boundaries. This
1707 * rule implies that elements within a 'Width' cannot cross GRF
1710 * So, for registers that are large enough, we have to split the exec
1711 * size in two and trust the compression state to sort it out.
1713 unsigned total_size
= inst
->exec_size
*
1714 inst
->src
[i
].stride
*
1715 type_sz(inst
->src
[i
].type
);
1717 assert(total_size
<= 2 * REG_SIZE
);
1718 const unsigned exec_size
=
1719 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1721 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1722 struct brw_reg reg
=
1723 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1724 inst
->src
[i
].subreg_offset
),
1725 exec_size
* inst
->src
[i
].stride
,
1726 width
, inst
->src
[i
].stride
);
1727 reg
.abs
= inst
->src
[i
].abs
;
1728 reg
.negate
= inst
->src
[i
].negate
;
1736 fs_visitor::assign_vs_urb_setup()
1738 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1740 assert(stage
== MESA_SHADER_VERTEX
);
1742 /* Each attribute is 4 regs. */
1743 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1745 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1747 /* Rewrite all ATTR file references to the hw grf that they land in. */
1748 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1749 convert_attr_sources_to_hw_regs(inst
);
1754 fs_visitor::assign_tcs_single_patch_urb_setup()
1756 assert(stage
== MESA_SHADER_TESS_CTRL
);
1758 /* Rewrite all ATTR file references to HW_REGs. */
1759 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1760 convert_attr_sources_to_hw_regs(inst
);
1765 fs_visitor::assign_tes_urb_setup()
1767 assert(stage
== MESA_SHADER_TESS_EVAL
);
1769 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1771 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1773 /* Rewrite all ATTR file references to HW_REGs. */
1774 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1775 convert_attr_sources_to_hw_regs(inst
);
1780 fs_visitor::assign_gs_urb_setup()
1782 assert(stage
== MESA_SHADER_GEOMETRY
);
1784 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1786 first_non_payload_grf
+=
1787 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1789 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1790 /* Rewrite all ATTR file references to GRFs. */
1791 convert_attr_sources_to_hw_regs(inst
);
1797 * Split large virtual GRFs into separate components if we can.
1799 * This is mostly duplicated with what brw_fs_vector_splitting does,
1800 * but that's really conservative because it's afraid of doing
1801 * splitting that doesn't result in real progress after the rest of
1802 * the optimization phases, which would cause infinite looping in
1803 * optimization. We can do it once here, safely. This also has the
1804 * opportunity to split interpolated values, or maybe even uniforms,
1805 * which we don't have at the IR level.
1807 * We want to split, because virtual GRFs are what we register
1808 * allocate and spill (due to contiguousness requirements for some
1809 * instructions), and they're what we naturally generate in the
1810 * codegen process, but most virtual GRFs don't actually need to be
1811 * contiguous sets of GRFs. If we split, we'll end up with reduced
1812 * live intervals and better dead code elimination and coalescing.
1815 fs_visitor::split_virtual_grfs()
1817 int num_vars
= this->alloc
.count
;
1819 /* Count the total number of registers */
1821 int vgrf_to_reg
[num_vars
];
1822 for (int i
= 0; i
< num_vars
; i
++) {
1823 vgrf_to_reg
[i
] = reg_count
;
1824 reg_count
+= alloc
.sizes
[i
];
1827 /* An array of "split points". For each register slot, this indicates
1828 * if this slot can be separated from the previous slot. Every time an
1829 * instruction uses multiple elements of a register (as a source or
1830 * destination), we mark the used slots as inseparable. Then we go
1831 * through and split the registers into the smallest pieces we can.
1833 bool split_points
[reg_count
];
1834 memset(split_points
, 0, sizeof(split_points
));
1836 /* Mark all used registers as fully splittable */
1837 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1838 if (inst
->dst
.file
== VGRF
) {
1839 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1840 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1841 split_points
[reg
+ j
] = true;
1844 for (int i
= 0; i
< inst
->sources
; i
++) {
1845 if (inst
->src
[i
].file
== VGRF
) {
1846 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1847 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1848 split_points
[reg
+ j
] = true;
1853 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1854 if (inst
->dst
.file
== VGRF
) {
1855 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1856 for (int j
= 1; j
< inst
->regs_written
; j
++)
1857 split_points
[reg
+ j
] = false;
1859 for (int i
= 0; i
< inst
->sources
; i
++) {
1860 if (inst
->src
[i
].file
== VGRF
) {
1861 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1862 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1863 split_points
[reg
+ j
] = false;
1868 int new_virtual_grf
[reg_count
];
1869 int new_reg_offset
[reg_count
];
1872 for (int i
= 0; i
< num_vars
; i
++) {
1873 /* The first one should always be 0 as a quick sanity check. */
1874 assert(split_points
[reg
] == false);
1877 new_reg_offset
[reg
] = 0;
1882 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1883 /* If this is a split point, reset the offset to 0 and allocate a
1884 * new virtual GRF for the previous offset many registers
1886 if (split_points
[reg
]) {
1887 assert(offset
<= MAX_VGRF_SIZE
);
1888 int grf
= alloc
.allocate(offset
);
1889 for (int k
= reg
- offset
; k
< reg
; k
++)
1890 new_virtual_grf
[k
] = grf
;
1893 new_reg_offset
[reg
] = offset
;
1898 /* The last one gets the original register number */
1899 assert(offset
<= MAX_VGRF_SIZE
);
1900 alloc
.sizes
[i
] = offset
;
1901 for (int k
= reg
- offset
; k
< reg
; k
++)
1902 new_virtual_grf
[k
] = i
;
1904 assert(reg
== reg_count
);
1906 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1907 if (inst
->dst
.file
== VGRF
) {
1908 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1909 inst
->dst
.nr
= new_virtual_grf
[reg
];
1910 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1911 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1913 for (int i
= 0; i
< inst
->sources
; i
++) {
1914 if (inst
->src
[i
].file
== VGRF
) {
1915 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1916 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1917 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1918 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1922 invalidate_live_intervals();
1926 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1928 * During code generation, we create tons of temporary variables, many of
1929 * which get immediately killed and are never used again. Yet, in later
1930 * optimization and analysis passes, such as compute_live_intervals, we need
1931 * to loop over all the virtual GRFs. Compacting them can save a lot of
1935 fs_visitor::compact_virtual_grfs()
1937 bool progress
= false;
1938 int remap_table
[this->alloc
.count
];
1939 memset(remap_table
, -1, sizeof(remap_table
));
1941 /* Mark which virtual GRFs are used. */
1942 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1943 if (inst
->dst
.file
== VGRF
)
1944 remap_table
[inst
->dst
.nr
] = 0;
1946 for (int i
= 0; i
< inst
->sources
; i
++) {
1947 if (inst
->src
[i
].file
== VGRF
)
1948 remap_table
[inst
->src
[i
].nr
] = 0;
1952 /* Compact the GRF arrays. */
1954 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1955 if (remap_table
[i
] == -1) {
1956 /* We just found an unused register. This means that we are
1957 * actually going to compact something.
1961 remap_table
[i
] = new_index
;
1962 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1963 invalidate_live_intervals();
1968 this->alloc
.count
= new_index
;
1970 /* Patch all the instructions to use the newly renumbered registers */
1971 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1972 if (inst
->dst
.file
== VGRF
)
1973 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1975 for (int i
= 0; i
< inst
->sources
; i
++) {
1976 if (inst
->src
[i
].file
== VGRF
)
1977 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1981 /* Patch all the references to delta_xy, since they're used in register
1982 * allocation. If they're unused, switch them to BAD_FILE so we don't
1983 * think some random VGRF is delta_xy.
1985 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1986 if (delta_xy
[i
].file
== VGRF
) {
1987 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1988 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1990 delta_xy
[i
].file
= BAD_FILE
;
1999 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
, bool contiguous
,
2000 int *push_constant_loc
, int *pull_constant_loc
,
2001 unsigned *num_push_constants
,
2002 unsigned *num_pull_constants
,
2003 const unsigned max_push_components
,
2004 const unsigned max_chunk_size
,
2005 struct brw_stage_prog_data
*stage_prog_data
)
2007 /* This is the first live uniform in the chunk */
2008 if (*chunk_start
< 0)
2009 *chunk_start
= uniform
;
2011 /* If this element does not need to be contiguous with the next, we
2012 * split at this point and everything between chunk_start and u forms a
2016 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
2018 /* Decide whether we should push or pull this parameter. In the
2019 * Vulkan driver, push constants are explicitly exposed via the API
2020 * so we push everything. In GL, we only push small arrays.
2022 if (stage_prog_data
->pull_param
== NULL
||
2023 (*num_push_constants
+ chunk_size
<= max_push_components
&&
2024 chunk_size
<= max_chunk_size
)) {
2025 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
2026 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
2027 push_constant_loc
[j
] = (*num_push_constants
)++;
2029 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
2030 pull_constant_loc
[j
] = (*num_pull_constants
)++;
2038 * Assign UNIFORM file registers to either push constants or pull constants.
2040 * We allow a fragment shader to have more than the specified minimum
2041 * maximum number of fragment shader uniform components (64). If
2042 * there are too many of these, they'd fill up all of register space.
2043 * So, this will push some of them out to the pull constant buffer and
2044 * update the program to load them.
2047 fs_visitor::assign_constant_locations()
2049 /* Only the first compile gets to decide on locations. */
2050 if (dispatch_width
!= min_dispatch_width
)
2053 bool is_live
[uniforms
];
2054 memset(is_live
, 0, sizeof(is_live
));
2055 bool is_live_64bit
[uniforms
];
2056 memset(is_live_64bit
, 0, sizeof(is_live_64bit
));
2058 /* For each uniform slot, a value of true indicates that the given slot and
2059 * the next slot must remain contiguous. This is used to keep us from
2060 * splitting arrays apart.
2062 bool contiguous
[uniforms
];
2063 memset(contiguous
, 0, sizeof(contiguous
));
2065 int thread_local_id_index
=
2066 (stage
== MESA_SHADER_COMPUTE
) ?
2067 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
: -1;
2069 /* First, we walk through the instructions and do two things:
2071 * 1) Figure out which uniforms are live.
2073 * 2) Mark any indirectly used ranges of registers as contiguous.
2075 * Note that we don't move constant-indexed accesses to arrays. No
2076 * testing has been done of the performance impact of this choice.
2078 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2079 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2080 if (inst
->src
[i
].file
!= UNIFORM
)
2083 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2085 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2086 assert(inst
->src
[2].ud
% 4 == 0);
2087 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
2088 assert(last
< uniforms
);
2090 for (unsigned j
= constant_nr
; j
< last
; j
++) {
2092 contiguous
[j
] = true;
2093 if (type_sz(inst
->src
[i
].type
) == 8) {
2094 is_live_64bit
[j
] = true;
2097 is_live
[last
] = true;
2099 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
2100 int regs_read
= inst
->components_read(i
) *
2101 type_sz(inst
->src
[i
].type
) / 4;
2102 for (int j
= 0; j
< regs_read
; j
++) {
2103 is_live
[constant_nr
+ j
] = true;
2104 if (type_sz(inst
->src
[i
].type
) == 8) {
2105 is_live_64bit
[constant_nr
+ j
] = true;
2113 if (thread_local_id_index
>= 0 && !is_live
[thread_local_id_index
])
2114 thread_local_id_index
= -1;
2116 /* Only allow 16 registers (128 uniform components) as push constants.
2118 * Just demote the end of the list. We could probably do better
2119 * here, demoting things that are rarely used in the program first.
2121 * If changing this value, note the limitation about total_regs in
2124 unsigned int max_push_components
= 16 * 8;
2125 if (thread_local_id_index
>= 0)
2126 max_push_components
--; /* Save a slot for the thread ID */
2128 /* We push small arrays, but no bigger than 16 floats. This is big enough
2129 * for a vec4 but hopefully not large enough to push out other stuff. We
2130 * should probably use a better heuristic at some point.
2132 const unsigned int max_chunk_size
= 16;
2134 unsigned int num_push_constants
= 0;
2135 unsigned int num_pull_constants
= 0;
2137 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2138 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2140 /* Default to -1 meaning no location */
2141 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2142 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2144 int chunk_start
= -1;
2146 /* First push 64-bit uniforms to ensure they are properly aligned */
2147 for (unsigned u
= 0; u
< uniforms
; u
++) {
2148 if (!is_live
[u
] || !is_live_64bit
[u
])
2151 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2152 push_constant_loc
, pull_constant_loc
,
2153 &num_push_constants
, &num_pull_constants
,
2154 max_push_components
, max_chunk_size
,
2159 /* Then push the rest of uniforms */
2160 for (unsigned u
= 0; u
< uniforms
; u
++) {
2161 if (!is_live
[u
] || is_live_64bit
[u
])
2164 /* Skip thread_local_id_index to put it in the last push register. */
2165 if (thread_local_id_index
== (int)u
)
2168 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2169 push_constant_loc
, pull_constant_loc
,
2170 &num_push_constants
, &num_pull_constants
,
2171 max_push_components
, max_chunk_size
,
2175 /* Add the CS local thread ID uniform at the end of the push constants */
2176 if (thread_local_id_index
>= 0)
2177 push_constant_loc
[thread_local_id_index
] = num_push_constants
++;
2179 /* As the uniforms are going to be reordered, take the data from a temporary
2180 * copy of the original param[].
2182 gl_constant_value
**param
= ralloc_array(NULL
, gl_constant_value
*,
2183 stage_prog_data
->nr_params
);
2184 memcpy(param
, stage_prog_data
->param
,
2185 sizeof(gl_constant_value
*) * stage_prog_data
->nr_params
);
2186 stage_prog_data
->nr_params
= num_push_constants
;
2187 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2189 /* Up until now, the param[] array has been indexed by reg + reg_offset
2190 * of UNIFORM registers. Move pull constants into pull_param[] and
2191 * condense param[] to only contain the uniforms we chose to push.
2193 * NOTE: Because we are condensing the params[] array, we know that
2194 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2195 * having to make a copy.
2197 int new_thread_local_id_index
= -1;
2198 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2199 const gl_constant_value
*value
= param
[i
];
2201 if (pull_constant_loc
[i
] != -1) {
2202 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2203 } else if (push_constant_loc
[i
] != -1) {
2204 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2205 if (thread_local_id_index
== (int)i
)
2206 new_thread_local_id_index
= push_constant_loc
[i
];
2211 if (stage
== MESA_SHADER_COMPUTE
)
2212 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
=
2213 new_thread_local_id_index
;
2217 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2218 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2221 fs_visitor::lower_constant_loads()
2223 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2225 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2226 /* Set up the annotation tracking for new generated instructions. */
2227 const fs_builder
ibld(this, block
, inst
);
2229 for (int i
= 0; i
< inst
->sources
; i
++) {
2230 if (inst
->src
[i
].file
!= UNIFORM
)
2233 /* We'll handle this case later */
2234 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2237 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2238 if (location
>= uniforms
)
2239 continue; /* Out of bounds access */
2241 int pull_index
= pull_constant_loc
[location
];
2243 if (pull_index
== -1)
2246 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2249 if (type_sz(inst
->src
[i
].type
) <= 4)
2250 dst
= vgrf(glsl_type::float_type
);
2252 dst
= vgrf(glsl_type::double_type
);
2254 assert(inst
->src
[i
].stride
== 0);
2256 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2257 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2258 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2259 dst
, brw_imm_ud(index
), offset
);
2261 /* Rewrite the instruction to use the temporary VGRF. */
2262 inst
->src
[i
].file
= VGRF
;
2263 inst
->src
[i
].nr
= dst
.nr
;
2264 inst
->src
[i
].reg_offset
= 0;
2265 inst
->src
[i
].set_smear((pull_index
& 3) * 4 /
2266 type_sz(inst
->src
[i
].type
));
2268 brw_mark_surface_used(prog_data
, index
);
2271 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2272 inst
->src
[0].file
== UNIFORM
) {
2274 unsigned location
= inst
->src
[0].nr
+ inst
->src
[0].reg_offset
;
2275 if (location
>= uniforms
)
2276 continue; /* Out of bounds access */
2278 int pull_index
= pull_constant_loc
[location
];
2280 if (pull_index
== -1)
2283 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2287 inst
->remove(block
);
2289 brw_mark_surface_used(prog_data
, index
);
2292 invalidate_live_intervals();
2296 fs_visitor::opt_algebraic()
2298 bool progress
= false;
2300 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2301 switch (inst
->opcode
) {
2302 case BRW_OPCODE_MOV
:
2303 if (inst
->src
[0].file
!= IMM
)
2306 if (inst
->saturate
) {
2307 if (inst
->dst
.type
!= inst
->src
[0].type
)
2308 assert(!"unimplemented: saturate mixed types");
2310 if (brw_saturate_immediate(inst
->dst
.type
,
2311 &inst
->src
[0].as_brw_reg())) {
2312 inst
->saturate
= false;
2318 case BRW_OPCODE_MUL
:
2319 if (inst
->src
[1].file
!= IMM
)
2323 if (inst
->src
[1].is_one()) {
2324 inst
->opcode
= BRW_OPCODE_MOV
;
2325 inst
->src
[1] = reg_undef
;
2331 if (inst
->src
[1].is_negative_one()) {
2332 inst
->opcode
= BRW_OPCODE_MOV
;
2333 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2334 inst
->src
[1] = reg_undef
;
2340 if (inst
->src
[1].is_zero()) {
2341 inst
->opcode
= BRW_OPCODE_MOV
;
2342 inst
->src
[0] = inst
->src
[1];
2343 inst
->src
[1] = reg_undef
;
2348 if (inst
->src
[0].file
== IMM
) {
2349 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2350 inst
->opcode
= BRW_OPCODE_MOV
;
2351 inst
->src
[0].f
*= inst
->src
[1].f
;
2352 inst
->src
[1] = reg_undef
;
2357 case BRW_OPCODE_ADD
:
2358 if (inst
->src
[1].file
!= IMM
)
2362 if (inst
->src
[1].is_zero()) {
2363 inst
->opcode
= BRW_OPCODE_MOV
;
2364 inst
->src
[1] = reg_undef
;
2369 if (inst
->src
[0].file
== IMM
) {
2370 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2371 inst
->opcode
= BRW_OPCODE_MOV
;
2372 inst
->src
[0].f
+= inst
->src
[1].f
;
2373 inst
->src
[1] = reg_undef
;
2379 if (inst
->src
[0].equals(inst
->src
[1])) {
2380 inst
->opcode
= BRW_OPCODE_MOV
;
2381 inst
->src
[1] = reg_undef
;
2386 case BRW_OPCODE_LRP
:
2387 if (inst
->src
[1].equals(inst
->src
[2])) {
2388 inst
->opcode
= BRW_OPCODE_MOV
;
2389 inst
->src
[0] = inst
->src
[1];
2390 inst
->src
[1] = reg_undef
;
2391 inst
->src
[2] = reg_undef
;
2396 case BRW_OPCODE_CMP
:
2397 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2399 inst
->src
[0].negate
&&
2400 inst
->src
[1].is_zero()) {
2401 inst
->src
[0].abs
= false;
2402 inst
->src
[0].negate
= false;
2403 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2408 case BRW_OPCODE_SEL
:
2409 if (inst
->src
[0].equals(inst
->src
[1])) {
2410 inst
->opcode
= BRW_OPCODE_MOV
;
2411 inst
->src
[1] = reg_undef
;
2412 inst
->predicate
= BRW_PREDICATE_NONE
;
2413 inst
->predicate_inverse
= false;
2415 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2416 switch (inst
->conditional_mod
) {
2417 case BRW_CONDITIONAL_LE
:
2418 case BRW_CONDITIONAL_L
:
2419 switch (inst
->src
[1].type
) {
2420 case BRW_REGISTER_TYPE_F
:
2421 if (inst
->src
[1].f
>= 1.0f
) {
2422 inst
->opcode
= BRW_OPCODE_MOV
;
2423 inst
->src
[1] = reg_undef
;
2424 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2432 case BRW_CONDITIONAL_GE
:
2433 case BRW_CONDITIONAL_G
:
2434 switch (inst
->src
[1].type
) {
2435 case BRW_REGISTER_TYPE_F
:
2436 if (inst
->src
[1].f
<= 0.0f
) {
2437 inst
->opcode
= BRW_OPCODE_MOV
;
2438 inst
->src
[1] = reg_undef
;
2439 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2451 case BRW_OPCODE_MAD
:
2452 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2453 inst
->opcode
= BRW_OPCODE_MOV
;
2454 inst
->src
[1] = reg_undef
;
2455 inst
->src
[2] = reg_undef
;
2457 } else if (inst
->src
[0].is_zero()) {
2458 inst
->opcode
= BRW_OPCODE_MUL
;
2459 inst
->src
[0] = inst
->src
[2];
2460 inst
->src
[2] = reg_undef
;
2462 } else if (inst
->src
[1].is_one()) {
2463 inst
->opcode
= BRW_OPCODE_ADD
;
2464 inst
->src
[1] = inst
->src
[2];
2465 inst
->src
[2] = reg_undef
;
2467 } else if (inst
->src
[2].is_one()) {
2468 inst
->opcode
= BRW_OPCODE_ADD
;
2469 inst
->src
[2] = reg_undef
;
2471 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2472 inst
->opcode
= BRW_OPCODE_ADD
;
2473 inst
->src
[1].f
*= inst
->src
[2].f
;
2474 inst
->src
[2] = reg_undef
;
2478 case SHADER_OPCODE_BROADCAST
:
2479 if (is_uniform(inst
->src
[0])) {
2480 inst
->opcode
= BRW_OPCODE_MOV
;
2482 inst
->force_writemask_all
= true;
2484 } else if (inst
->src
[1].file
== IMM
) {
2485 inst
->opcode
= BRW_OPCODE_MOV
;
2486 inst
->src
[0] = component(inst
->src
[0],
2489 inst
->force_writemask_all
= true;
2498 /* Swap if src[0] is immediate. */
2499 if (progress
&& inst
->is_commutative()) {
2500 if (inst
->src
[0].file
== IMM
) {
2501 fs_reg tmp
= inst
->src
[1];
2502 inst
->src
[1] = inst
->src
[0];
2511 * Optimize sample messages that have constant zero values for the trailing
2512 * texture coordinates. We can just reduce the message length for these
2513 * instructions instead of reserving a register for it. Trailing parameters
2514 * that aren't sent default to zero anyway. This will cause the dead code
2515 * eliminator to remove the MOV instruction that would otherwise be emitted to
2516 * set up the zero value.
2519 fs_visitor::opt_zero_samples()
2521 /* Gen4 infers the texturing opcode based on the message length so we can't
2524 if (devinfo
->gen
< 5)
2527 bool progress
= false;
2529 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2530 if (!inst
->is_tex())
2533 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2535 if (load_payload
->is_head_sentinel() ||
2536 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2539 /* We don't want to remove the message header or the first parameter.
2540 * Removing the first parameter is not allowed, see the Haswell PRM
2541 * volume 7, page 149:
2543 * "Parameter 0 is required except for the sampleinfo message, which
2544 * has no parameter 0"
2546 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2547 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2548 (inst
->exec_size
/ 8) +
2549 inst
->header_size
- 1].is_zero()) {
2550 inst
->mlen
-= inst
->exec_size
/ 8;
2556 invalidate_live_intervals();
2562 * Optimize sample messages which are followed by the final RT write.
2564 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2565 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2566 * final texturing results copied to the framebuffer write payload and modify
2567 * them to write to the framebuffer directly.
2570 fs_visitor::opt_sampler_eot()
2572 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2574 if (stage
!= MESA_SHADER_FRAGMENT
)
2577 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2580 /* FINISHME: It should be possible to implement this optimization when there
2581 * are multiple drawbuffers.
2583 if (key
->nr_color_regions
!= 1)
2586 /* Requires emitting a bunch of saturating MOV instructions during logical
2587 * send lowering to clamp the color payload, which the sampler unit isn't
2588 * going to do for us.
2590 if (key
->clamp_fragment_color
)
2593 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2594 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2595 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2596 assert(fb_write
->eot
);
2597 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2599 /* There wasn't one; nothing to do. */
2600 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2603 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2605 /* 3D Sampler » Messages » Message Format
2607 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2608 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2610 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2611 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2612 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2613 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2614 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2615 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2616 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2617 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2620 /* XXX - This shouldn't be necessary. */
2621 if (tex_inst
->prev
->is_head_sentinel())
2624 /* Check that the FB write sources are fully initialized by the single
2625 * texturing instruction.
2627 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2628 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2629 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2630 fb_write
->regs_read(i
) != tex_inst
->regs_written
)
2632 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2633 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2638 assert(!tex_inst
->eot
); /* We can't get here twice */
2639 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2641 const fs_builder
ibld(this, block
, tex_inst
);
2643 tex_inst
->offset
|= fb_write
->target
<< 24;
2644 tex_inst
->eot
= true;
2645 tex_inst
->dst
= ibld
.null_reg_ud();
2646 tex_inst
->regs_written
= 0;
2647 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2649 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2650 * flag and submit a header together with the sampler message as required
2653 invalidate_live_intervals();
2658 fs_visitor::opt_register_renaming()
2660 bool progress
= false;
2663 int remap
[alloc
.count
];
2664 memset(remap
, -1, sizeof(int) * alloc
.count
);
2666 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2667 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2669 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2670 inst
->opcode
== BRW_OPCODE_WHILE
) {
2674 /* Rewrite instruction sources. */
2675 for (int i
= 0; i
< inst
->sources
; i
++) {
2676 if (inst
->src
[i
].file
== VGRF
&&
2677 remap
[inst
->src
[i
].nr
] != -1 &&
2678 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2679 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2684 const int dst
= inst
->dst
.nr
;
2687 inst
->dst
.file
== VGRF
&&
2688 alloc
.sizes
[inst
->dst
.nr
] == inst
->regs_written
&&
2689 !inst
->is_partial_write()) {
2690 if (remap
[dst
] == -1) {
2693 remap
[dst
] = alloc
.allocate(inst
->regs_written
);
2694 inst
->dst
.nr
= remap
[dst
];
2697 } else if (inst
->dst
.file
== VGRF
&&
2699 remap
[dst
] != dst
) {
2700 inst
->dst
.nr
= remap
[dst
];
2706 invalidate_live_intervals();
2708 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2709 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2710 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2719 * Remove redundant or useless discard jumps.
2721 * For example, we can eliminate jumps in the following sequence:
2723 * discard-jump (redundant with the next jump)
2724 * discard-jump (useless; jumps to the next instruction)
2728 fs_visitor::opt_redundant_discard_jumps()
2730 bool progress
= false;
2732 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2734 fs_inst
*placeholder_halt
= NULL
;
2735 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2736 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2737 placeholder_halt
= inst
;
2742 if (!placeholder_halt
)
2745 /* Delete any HALTs immediately before the placeholder halt. */
2746 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2747 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2748 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2749 prev
->remove(last_bblock
);
2754 invalidate_live_intervals();
2760 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2761 * from \p r which overlaps the region starting at \p r and spanning \p n GRF
2764 static inline unsigned
2765 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned n
)
2767 const int rel_offset
= (reg_offset(s
) - reg_offset(r
)) / REG_SIZE
;
2768 assert(reg_space(r
) == reg_space(s
) &&
2769 rel_offset
>= 0 && rel_offset
< int(8 * sizeof(unsigned)));
2770 return ((1 << n
) - 1) << rel_offset
;
2774 fs_visitor::compute_to_mrf()
2776 bool progress
= false;
2779 /* No MRFs on Gen >= 7. */
2780 if (devinfo
->gen
>= 7)
2783 calculate_live_intervals();
2785 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2789 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2790 inst
->is_partial_write() ||
2791 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2792 inst
->dst
.type
!= inst
->src
[0].type
||
2793 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2794 !inst
->src
[0].is_contiguous() ||
2795 inst
->src
[0].subreg_offset
)
2798 /* Can't compute-to-MRF this GRF if someone else was going to
2801 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2804 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2805 * things that computed the value of all GRFs of the source region. The
2806 * regs_left bitset keeps track of the registers we haven't yet found a
2807 * generating instruction for.
2809 unsigned regs_left
= (1 << inst
->regs_read(0)) - 1;
2811 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2812 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2813 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2814 /* Found the last thing to write our reg we want to turn
2815 * into a compute-to-MRF.
2818 /* If this one instruction didn't populate all the
2819 * channels, bail. We might be able to rewrite everything
2820 * that writes that reg, but it would require smarter
2823 if (scan_inst
->is_partial_write())
2826 /* Handling things not fully contained in the source of the copy
2827 * would need us to understand coalescing out more than one MOV at
2830 if (scan_inst
->dst
.reg_offset
< inst
->src
[0].reg_offset
||
2831 scan_inst
->dst
.reg_offset
+ scan_inst
->regs_written
>
2832 inst
->src
[0].reg_offset
+ inst
->regs_read(0))
2835 /* SEND instructions can't have MRF as a destination. */
2836 if (scan_inst
->mlen
)
2839 if (devinfo
->gen
== 6) {
2840 /* gen6 math instructions must have the destination be
2841 * GRF, so no compute-to-MRF for them.
2843 if (scan_inst
->is_math()) {
2848 /* Clear the bits for any registers this instruction overwrites. */
2849 regs_left
&= ~mask_relative_to(
2850 inst
->src
[0], scan_inst
->dst
, scan_inst
->regs_written
);
2855 /* We don't handle control flow here. Most computation of
2856 * values that end up in MRFs are shortly before the MRF
2859 if (block
->start() == scan_inst
)
2862 /* You can't read from an MRF, so if someone else reads our
2863 * MRF's source GRF that we wanted to rewrite, that stops us.
2865 bool interfered
= false;
2866 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2867 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->regs_read(i
) * REG_SIZE
,
2868 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2875 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2876 inst
->dst
, inst
->regs_written
* REG_SIZE
)) {
2877 /* If somebody else writes our MRF here, we can't
2878 * compute-to-MRF before that.
2883 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2884 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2885 inst
->dst
, inst
->regs_written
* REG_SIZE
)) {
2886 /* Found a SEND instruction, which means that there are
2887 * live values in MRFs from base_mrf to base_mrf +
2888 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2898 /* Found all generating instructions of our MRF's source value, so it
2899 * should be safe to rewrite them to point to the MRF directly.
2901 regs_left
= (1 << inst
->regs_read(0)) - 1;
2903 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2904 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2905 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2906 /* Clear the bits for any registers this instruction overwrites. */
2907 regs_left
&= ~mask_relative_to(
2908 inst
->src
[0], scan_inst
->dst
, scan_inst
->regs_written
);
2910 const unsigned rel_offset
= (reg_offset(scan_inst
->dst
) -
2911 reg_offset(inst
->src
[0])) / REG_SIZE
;
2913 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2914 /* Apply the same address transformation done by the hardware
2915 * for COMPR4 MRF writes.
2917 assert(rel_offset
< 2);
2918 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
* 4;
2920 /* Clear the COMPR4 bit if the generating instruction is not
2923 if (scan_inst
->regs_written
< 2)
2924 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2927 /* Calculate the MRF number the result of this instruction is
2928 * ultimately written to.
2930 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
;
2933 scan_inst
->dst
.file
= MRF
;
2934 scan_inst
->dst
.reg_offset
= 0;
2935 scan_inst
->saturate
|= inst
->saturate
;
2942 inst
->remove(block
);
2947 invalidate_live_intervals();
2953 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2954 * flow. We could probably do better here with some form of divergence
2958 fs_visitor::eliminate_find_live_channel()
2960 bool progress
= false;
2963 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2964 switch (inst
->opcode
) {
2970 case BRW_OPCODE_ENDIF
:
2971 case BRW_OPCODE_WHILE
:
2975 case FS_OPCODE_DISCARD_JUMP
:
2976 /* This can potentially make control flow non-uniform until the end
2981 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2983 inst
->opcode
= BRW_OPCODE_MOV
;
2984 inst
->src
[0] = brw_imm_ud(0u);
2986 inst
->force_writemask_all
= true;
3000 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
3001 * instructions to FS_OPCODE_REP_FB_WRITE.
3004 fs_visitor::emit_repclear_shader()
3006 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3008 int color_mrf
= base_mrf
+ 2;
3012 mov
= bld
.exec_all().group(4, 0)
3013 .MOV(brw_message_reg(color_mrf
),
3014 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
3016 struct brw_reg reg
=
3017 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
3018 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
3019 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
3021 mov
= bld
.exec_all().group(4, 0)
3022 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
3026 if (key
->nr_color_regions
== 1) {
3027 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3028 write
->saturate
= key
->clamp_fragment_color
;
3029 write
->base_mrf
= color_mrf
;
3031 write
->header_size
= 0;
3034 assume(key
->nr_color_regions
> 0);
3035 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3036 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3037 write
->saturate
= key
->clamp_fragment_color
;
3038 write
->base_mrf
= base_mrf
;
3040 write
->header_size
= 2;
3048 assign_constant_locations();
3049 assign_curb_setup();
3051 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3053 assert(mov
->src
[0].file
== FIXED_GRF
);
3054 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3059 * Walks through basic blocks, looking for repeated MRF writes and
3060 * removing the later ones.
3063 fs_visitor::remove_duplicate_mrf_writes()
3065 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3066 bool progress
= false;
3068 /* Need to update the MRF tracking for compressed instructions. */
3069 if (dispatch_width
>= 16)
3072 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3074 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3075 if (inst
->is_control_flow()) {
3076 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3079 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3080 inst
->dst
.file
== MRF
) {
3081 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3082 if (prev_inst
&& inst
->equals(prev_inst
)) {
3083 inst
->remove(block
);
3089 /* Clear out the last-write records for MRFs that were overwritten. */
3090 if (inst
->dst
.file
== MRF
) {
3091 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3094 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3095 /* Found a SEND instruction, which will include two or fewer
3096 * implied MRF writes. We could do better here.
3098 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3099 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3103 /* Clear out any MRF move records whose sources got overwritten. */
3104 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3105 if (last_mrf_move
[i
] &&
3106 regions_overlap(inst
->dst
, inst
->regs_written
* REG_SIZE
,
3107 last_mrf_move
[i
]->src
[0],
3108 last_mrf_move
[i
]->regs_read(0) * REG_SIZE
)) {
3109 last_mrf_move
[i
] = NULL
;
3113 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3114 inst
->dst
.file
== MRF
&&
3115 inst
->src
[0].file
!= ARF
&&
3116 !inst
->is_partial_write()) {
3117 last_mrf_move
[inst
->dst
.nr
] = inst
;
3122 invalidate_live_intervals();
3128 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3130 /* Clear the flag for registers that actually got read (as expected). */
3131 for (int i
= 0; i
< inst
->sources
; i
++) {
3133 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3134 grf
= inst
->src
[i
].nr
;
3139 if (grf
>= first_grf
&&
3140 grf
< first_grf
+ grf_len
) {
3141 deps
[grf
- first_grf
] = false;
3142 if (inst
->exec_size
== 16)
3143 deps
[grf
- first_grf
+ 1] = false;
3149 * Implements this workaround for the original 965:
3151 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3152 * check for post destination dependencies on this instruction, software
3153 * must ensure that there is no destination hazard for the case of ‘write
3154 * followed by a posted write’ shown in the following example.
3157 * 2. send r3.xy <rest of send instruction>
3160 * Due to no post-destination dependency check on the ‘send’, the above
3161 * code sequence could have two instructions (1 and 2) in flight at the
3162 * same time that both consider ‘r3’ as the target of their final writes.
3165 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3168 int write_len
= inst
->regs_written
;
3169 int first_write_grf
= inst
->dst
.nr
;
3170 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3171 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3173 memset(needs_dep
, false, sizeof(needs_dep
));
3174 memset(needs_dep
, true, write_len
);
3176 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3178 /* Walk backwards looking for writes to registers we're writing which
3179 * aren't read since being written. If we hit the start of the program,
3180 * we assume that there are no outstanding dependencies on entry to the
3183 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3184 /* If we hit control flow, assume that there *are* outstanding
3185 * dependencies, and force their cleanup before our instruction.
3187 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3188 for (int i
= 0; i
< write_len
; i
++) {
3190 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3191 first_write_grf
+ i
);
3196 /* We insert our reads as late as possible on the assumption that any
3197 * instruction but a MOV that might have left us an outstanding
3198 * dependency has more latency than a MOV.
3200 if (scan_inst
->dst
.file
== VGRF
) {
3201 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
3202 int reg
= scan_inst
->dst
.nr
+ i
;
3204 if (reg
>= first_write_grf
&&
3205 reg
< first_write_grf
+ write_len
&&
3206 needs_dep
[reg
- first_write_grf
]) {
3207 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3208 needs_dep
[reg
- first_write_grf
] = false;
3209 if (scan_inst
->exec_size
== 16)
3210 needs_dep
[reg
- first_write_grf
+ 1] = false;
3215 /* Clear the flag for registers that actually got read (as expected). */
3216 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3218 /* Continue the loop only if we haven't resolved all the dependencies */
3220 for (i
= 0; i
< write_len
; i
++) {
3230 * Implements this workaround for the original 965:
3232 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3233 * used as a destination register until after it has been sourced by an
3234 * instruction with a different destination register.
3237 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3239 int write_len
= inst
->regs_written
;
3240 int first_write_grf
= inst
->dst
.nr
;
3241 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3242 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3244 memset(needs_dep
, false, sizeof(needs_dep
));
3245 memset(needs_dep
, true, write_len
);
3246 /* Walk forwards looking for writes to registers we're writing which aren't
3247 * read before being written.
3249 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3250 /* If we hit control flow, force resolve all remaining dependencies. */
3251 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3252 for (int i
= 0; i
< write_len
; i
++) {
3254 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3255 first_write_grf
+ i
);
3260 /* Clear the flag for registers that actually got read (as expected). */
3261 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3263 /* We insert our reads as late as possible since they're reading the
3264 * result of a SEND, which has massive latency.
3266 if (scan_inst
->dst
.file
== VGRF
&&
3267 scan_inst
->dst
.nr
>= first_write_grf
&&
3268 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3269 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3270 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3272 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3275 /* Continue the loop only if we haven't resolved all the dependencies */
3277 for (i
= 0; i
< write_len
; i
++) {
3287 fs_visitor::insert_gen4_send_dependency_workarounds()
3289 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3292 bool progress
= false;
3294 /* Note that we're done with register allocation, so GRF fs_regs always
3295 * have a .reg_offset of 0.
3298 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3299 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3300 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3301 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3307 invalidate_live_intervals();
3311 * Turns the generic expression-style uniform pull constant load instruction
3312 * into a hardware-specific series of instructions for loading a pull
3315 * The expression style allows the CSE pass before this to optimize out
3316 * repeated loads from the same offset, and gives the pre-register-allocation
3317 * scheduling full flexibility, while the conversion to native instructions
3318 * allows the post-register-allocation scheduler the best information
3321 * Note that execution masking for setting up pull constant loads is special:
3322 * the channels that need to be written are unrelated to the current execution
3323 * mask, since a later instruction will use one of the result channels as a
3324 * source operand for all 8 or 16 of its channels.
3327 fs_visitor::lower_uniform_pull_constant_loads()
3329 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3330 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3333 if (devinfo
->gen
>= 7) {
3334 /* The offset arg is a vec4-aligned immediate byte offset. */
3335 fs_reg const_offset_reg
= inst
->src
[1];
3336 assert(const_offset_reg
.file
== IMM
&&
3337 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3338 assert(const_offset_reg
.ud
% 16 == 0);
3340 fs_reg payload
, offset
;
3341 if (devinfo
->gen
>= 9) {
3342 /* We have to use a message header on Skylake to get SIMD4x2
3343 * mode. Reserve space for the register.
3345 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3346 offset
.reg_offset
++;
3349 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3353 /* This is actually going to be a MOV, but since only the first dword
3354 * is accessed, we have a special opcode to do just that one. Note
3355 * that this needs to be an operation that will be considered a def
3356 * by live variable analysis, or register allocation will explode.
3358 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3359 8, offset
, const_offset_reg
);
3360 setup
->force_writemask_all
= true;
3362 setup
->ir
= inst
->ir
;
3363 setup
->annotation
= inst
->annotation
;
3364 inst
->insert_before(block
, setup
);
3366 /* Similarly, this will only populate the first 4 channels of the
3367 * result register (since we only use smear values from 0-3), but we
3368 * don't tell the optimizer.
3370 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3371 inst
->src
[1] = payload
;
3373 invalidate_live_intervals();
3375 /* Before register allocation, we didn't tell the scheduler about the
3376 * MRF we use. We know it's safe to use this MRF because nothing
3377 * else does except for register spill/unspill, which generates and
3378 * uses its MRF within a single IR instruction.
3380 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3387 fs_visitor::lower_load_payload()
3389 bool progress
= false;
3391 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3392 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3395 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3396 assert(inst
->saturate
== false);
3397 fs_reg dst
= inst
->dst
;
3399 /* Get rid of COMPR4. We'll add it back in if we need it */
3400 if (dst
.file
== MRF
)
3401 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3403 const fs_builder
ibld(this, block
, inst
);
3404 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3406 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3407 if (inst
->src
[i
].file
!= BAD_FILE
) {
3408 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3409 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3410 hbld
.MOV(mov_dst
, mov_src
);
3412 dst
= offset(dst
, hbld
, 1);
3415 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3416 inst
->exec_size
> 8) {
3417 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3418 * a straightforward copy. Instead, the result of the
3419 * LOAD_PAYLOAD is treated as interleaved and the first four
3420 * non-header sources are unpacked as:
3431 * This is used for gen <= 5 fb writes.
3433 assert(inst
->exec_size
== 16);
3434 assert(inst
->header_size
+ 4 <= inst
->sources
);
3435 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3436 if (inst
->src
[i
].file
!= BAD_FILE
) {
3437 if (devinfo
->has_compr4
) {
3438 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3439 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3440 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3442 /* Platform doesn't have COMPR4. We have to fake it */
3443 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3444 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3446 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3453 /* The loop above only ever incremented us through the first set
3454 * of 4 registers. However, thanks to the magic of COMPR4, we
3455 * actually wrote to the first 8 registers, so we need to take
3456 * that into account now.
3460 /* The COMPR4 code took care of the first 4 sources. We'll let
3461 * the regular path handle any remaining sources. Yes, we are
3462 * modifying the instruction but we're about to delete it so
3463 * this really doesn't hurt anything.
3465 inst
->header_size
+= 4;
3468 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3469 if (inst
->src
[i
].file
!= BAD_FILE
)
3470 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3471 dst
= offset(dst
, ibld
, 1);
3474 inst
->remove(block
);
3479 invalidate_live_intervals();
3485 fs_visitor::lower_integer_multiplication()
3487 bool progress
= false;
3489 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3490 const fs_builder
ibld(this, block
, inst
);
3492 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3493 if (inst
->dst
.is_accumulator() ||
3494 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3495 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3498 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3499 * operation directly, but CHV/BXT cannot.
3501 if (devinfo
->gen
>= 8 &&
3502 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3505 if (inst
->src
[1].file
== IMM
&&
3506 inst
->src
[1].ud
< (1 << 16)) {
3507 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3508 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3511 * If multiplying by an immediate value that fits in 16-bits, do a
3512 * single MUL instruction with that value in the proper location.
3514 if (devinfo
->gen
< 7) {
3515 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3517 ibld
.MOV(imm
, inst
->src
[1]);
3518 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3520 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3521 ibld
.MUL(inst
->dst
, inst
->src
[0],
3522 ud
? brw_imm_uw(inst
->src
[1].ud
)
3523 : brw_imm_w(inst
->src
[1].d
));
3526 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3527 * do 32-bit integer multiplication in one instruction, but instead
3528 * must do a sequence (which actually calculates a 64-bit result):
3530 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3531 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3532 * mov(8) g2<1>D acc0<8,8,1>D
3534 * But on Gen > 6, the ability to use second accumulator register
3535 * (acc1) for non-float data types was removed, preventing a simple
3536 * implementation in SIMD16. A 16-channel result can be calculated by
3537 * executing the three instructions twice in SIMD8, once with quarter
3538 * control of 1Q for the first eight channels and again with 2Q for
3539 * the second eight channels.
3541 * Which accumulator register is implicitly accessed (by AccWrEnable
3542 * for instance) is determined by the quarter control. Unfortunately
3543 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3544 * implicit accumulator access by an instruction with 2Q will access
3545 * acc1 regardless of whether the data type is usable in acc1.
3547 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3548 * integer data types.
3550 * Since we only want the low 32-bits of the result, we can do two
3551 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3552 * adjust the high result and add them (like the mach is doing):
3554 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3555 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3556 * shl(8) g9<1>D g8<8,8,1>D 16D
3557 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3559 * We avoid the shl instruction by realizing that we only want to add
3560 * the low 16-bits of the "high" result to the high 16-bits of the
3561 * "low" result and using proper regioning on the add:
3563 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3564 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3565 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3567 * Since it does not use the (single) accumulator register, we can
3568 * schedule multi-component multiplications much better.
3571 fs_reg orig_dst
= inst
->dst
;
3572 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3573 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3576 fs_reg low
= inst
->dst
;
3577 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3580 if (devinfo
->gen
>= 7) {
3581 fs_reg src1_0_w
= inst
->src
[1];
3582 fs_reg src1_1_w
= inst
->src
[1];
3584 if (inst
->src
[1].file
== IMM
) {
3585 src1_0_w
.ud
&= 0xffff;
3588 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3589 if (src1_0_w
.stride
!= 0) {
3590 assert(src1_0_w
.stride
== 1);
3591 src1_0_w
.stride
= 2;
3594 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3595 if (src1_1_w
.stride
!= 0) {
3596 assert(src1_1_w
.stride
== 1);
3597 src1_1_w
.stride
= 2;
3599 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3601 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3602 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3604 fs_reg src0_0_w
= inst
->src
[0];
3605 fs_reg src0_1_w
= inst
->src
[0];
3607 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3608 if (src0_0_w
.stride
!= 0) {
3609 assert(src0_0_w
.stride
== 1);
3610 src0_0_w
.stride
= 2;
3613 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3614 if (src0_1_w
.stride
!= 0) {
3615 assert(src0_1_w
.stride
== 1);
3616 src0_1_w
.stride
= 2;
3618 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3620 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3621 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3624 fs_reg dst
= inst
->dst
;
3625 dst
.type
= BRW_REGISTER_TYPE_UW
;
3626 dst
.subreg_offset
= 2;
3629 high
.type
= BRW_REGISTER_TYPE_UW
;
3632 low
.type
= BRW_REGISTER_TYPE_UW
;
3633 low
.subreg_offset
= 2;
3636 ibld
.ADD(dst
, low
, high
);
3638 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3639 set_condmod(inst
->conditional_mod
,
3640 ibld
.MOV(orig_dst
, inst
->dst
));
3644 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3645 /* Should have been lowered to 8-wide. */
3646 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3647 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3649 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3650 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3652 if (devinfo
->gen
>= 8) {
3653 /* Until Gen8, integer multiplies read 32-bits from one source,
3654 * and 16-bits from the other, and relying on the MACH instruction
3655 * to generate the high bits of the result.
3657 * On Gen8, the multiply instruction does a full 32x32-bit
3658 * multiply, but in order to do a 64-bit multiply we can simulate
3659 * the previous behavior and then use a MACH instruction.
3661 * FINISHME: Don't use source modifiers on src1.
3663 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3664 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3665 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3666 mul
->src
[1].stride
*= 2;
3668 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3670 /* Among other things the quarter control bits influence which
3671 * accumulator register is used by the hardware for instructions
3672 * that access the accumulator implicitly (e.g. MACH). A
3673 * second-half instruction would normally map to acc1, which
3674 * doesn't exist on Gen7 and up (the hardware does emulate it for
3675 * floating-point instructions *only* by taking advantage of the
3676 * extra precision of acc0 not normally used for floating point
3679 * HSW and up are careful enough not to try to access an
3680 * accumulator register that doesn't exist, but on earlier Gen7
3681 * hardware we need to make sure that the quarter control bits are
3682 * zero to avoid non-deterministic behaviour and emit an extra MOV
3683 * to get the result masked correctly according to the current
3687 mach
->force_writemask_all
= true;
3688 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3689 ibld
.MOV(inst
->dst
, mach
->dst
);
3695 inst
->remove(block
);
3700 invalidate_live_intervals();
3706 fs_visitor::lower_minmax()
3708 assert(devinfo
->gen
< 6);
3710 bool progress
= false;
3712 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3713 const fs_builder
ibld(this, block
, inst
);
3715 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3716 inst
->predicate
== BRW_PREDICATE_NONE
) {
3717 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3718 * the original SEL.L/GE instruction
3720 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3721 inst
->conditional_mod
);
3722 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3723 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3730 invalidate_live_intervals();
3736 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3737 fs_reg
*dst
, fs_reg color
, unsigned components
)
3739 if (key
->clamp_fragment_color
) {
3740 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3741 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3743 for (unsigned i
= 0; i
< components
; i
++)
3745 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3750 for (unsigned i
= 0; i
< components
; i
++)
3751 dst
[i
] = offset(color
, bld
, i
);
3755 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3756 const brw_wm_prog_data
*prog_data
,
3757 const brw_wm_prog_key
*key
,
3758 const fs_visitor::thread_payload
&payload
)
3760 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3761 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3762 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3763 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3764 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3765 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3766 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3767 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3768 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3769 const unsigned components
=
3770 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3772 /* We can potentially have a message length of up to 15, so we have to set
3773 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3776 int header_size
= 2, payload_header_size
;
3777 unsigned length
= 0;
3779 /* From the Sandy Bridge PRM, volume 4, page 198:
3781 * "Dispatched Pixel Enables. One bit per pixel indicating
3782 * which pixels were originally enabled when the thread was
3783 * dispatched. This field is only required for the end-of-
3784 * thread message and on all dual-source messages."
3786 if (devinfo
->gen
>= 6 &&
3787 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3788 color1
.file
== BAD_FILE
&&
3789 key
->nr_color_regions
== 1) {
3793 if (header_size
!= 0) {
3794 assert(header_size
== 2);
3795 /* Allocate 2 registers for a header */
3799 if (payload
.aa_dest_stencil_reg
) {
3800 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3801 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3802 .MOV(sources
[length
],
3803 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3807 if (sample_mask
.file
!= BAD_FILE
) {
3808 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3809 BRW_REGISTER_TYPE_UD
);
3811 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3812 * relevant. Since it's unsigned single words one vgrf is always
3813 * 16-wide, but only the lower or higher 8 channels will be used by the
3814 * hardware when doing a SIMD8 write depending on whether we have
3815 * selected the subspans for the first or second half respectively.
3817 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3818 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3819 sample_mask
.stride
*= 2;
3821 bld
.exec_all().annotate("FB write oMask")
3822 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3828 payload_header_size
= length
;
3830 if (src0_alpha
.file
!= BAD_FILE
) {
3831 /* FIXME: This is being passed at the wrong location in the payload and
3832 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3833 * It's supposed to be immediately before oMask but there seems to be no
3834 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3835 * requires header sources to form a contiguous segment at the beginning
3836 * of the message and src0_alpha has per-channel semantics.
3838 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3842 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3845 if (color1
.file
!= BAD_FILE
) {
3846 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3850 if (src_depth
.file
!= BAD_FILE
) {
3851 sources
[length
] = src_depth
;
3855 if (dst_depth
.file
!= BAD_FILE
) {
3856 sources
[length
] = dst_depth
;
3860 if (src_stencil
.file
!= BAD_FILE
) {
3861 assert(devinfo
->gen
>= 9);
3862 assert(bld
.dispatch_width() != 16);
3864 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3865 * available on gen9+. As such it's impossible to have both enabled at the
3866 * same time and therefore length cannot overrun the array.
3868 assert(length
< 15);
3870 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3871 bld
.exec_all().annotate("FB write OS")
3872 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3873 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3878 if (devinfo
->gen
>= 7) {
3879 /* Send from the GRF */
3880 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3881 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3882 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3883 load
->dst
= payload
;
3885 inst
->src
[0] = payload
;
3886 inst
->resize_sources(1);
3888 /* Send from the MRF */
3889 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3890 sources
, length
, payload_header_size
);
3892 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3893 * will do this for us if we just give it a COMPR4 destination.
3895 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3896 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3898 inst
->resize_sources(0);
3902 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3903 inst
->mlen
= load
->regs_written
;
3904 inst
->header_size
= header_size
;
3908 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3909 const fs_reg
&coordinate
,
3910 const fs_reg
&shadow_c
,
3911 const fs_reg
&lod
, const fs_reg
&lod2
,
3912 const fs_reg
&surface
,
3913 const fs_reg
&sampler
,
3914 unsigned coord_components
,
3915 unsigned grad_components
)
3917 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3918 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3919 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3920 fs_reg msg_end
= msg_begin
;
3923 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3925 for (unsigned i
= 0; i
< coord_components
; i
++)
3926 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3927 offset(coordinate
, bld
, i
));
3929 msg_end
= offset(msg_end
, bld
, coord_components
);
3931 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3932 * require all three components to be present and zero if they are unused.
3934 if (coord_components
> 0 &&
3935 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3936 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3937 for (unsigned i
= coord_components
; i
< 3; i
++)
3938 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3940 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3943 if (op
== SHADER_OPCODE_TXD
) {
3944 /* TXD unsupported in SIMD16 mode. */
3945 assert(bld
.dispatch_width() == 8);
3947 /* the slots for u and v are always present, but r is optional */
3948 if (coord_components
< 2)
3949 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3952 * dPdx = dudx, dvdx, drdx
3953 * dPdy = dudy, dvdy, drdy
3955 * 1-arg: Does not exist.
3957 * 2-arg: dudx dvdx dudy dvdy
3958 * dPdx.x dPdx.y dPdy.x dPdy.y
3961 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3962 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3963 * m5 m6 m7 m8 m9 m10
3965 for (unsigned i
= 0; i
< grad_components
; i
++)
3966 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3968 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3970 for (unsigned i
= 0; i
< grad_components
; i
++)
3971 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3973 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3977 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3978 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3980 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3981 bld
.dispatch_width() == 16);
3983 const brw_reg_type type
=
3984 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3985 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3986 bld
.MOV(retype(msg_end
, type
), lod
);
3987 msg_end
= offset(msg_end
, bld
, 1);
3990 if (shadow_c
.file
!= BAD_FILE
) {
3991 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3992 /* There's no plain shadow compare message, so we use shadow
3993 * compare with a bias of 0.0.
3995 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3996 msg_end
= offset(msg_end
, bld
, 1);
3999 bld
.MOV(msg_end
, shadow_c
);
4000 msg_end
= offset(msg_end
, bld
, 1);
4004 inst
->src
[0] = reg_undef
;
4005 inst
->src
[1] = surface
;
4006 inst
->src
[2] = sampler
;
4007 inst
->resize_sources(3);
4008 inst
->base_mrf
= msg_begin
.nr
;
4009 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
4010 inst
->header_size
= 1;
4014 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4015 const fs_reg
&coordinate
,
4016 const fs_reg
&shadow_c
,
4017 const fs_reg
&lod
, const fs_reg
&lod2
,
4018 const fs_reg
&sample_index
,
4019 const fs_reg
&surface
,
4020 const fs_reg
&sampler
,
4021 const fs_reg
&offset_value
,
4022 unsigned coord_components
,
4023 unsigned grad_components
)
4025 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
4026 fs_reg msg_coords
= message
;
4027 unsigned header_size
= 0;
4029 if (offset_value
.file
!= BAD_FILE
) {
4030 /* The offsets set up by the visitor are in the m1 header, so we can't
4037 for (unsigned i
= 0; i
< coord_components
; i
++)
4038 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
4039 offset(coordinate
, bld
, i
));
4041 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
4042 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
4044 if (shadow_c
.file
!= BAD_FILE
) {
4045 fs_reg msg_shadow
= msg_lod
;
4046 bld
.MOV(msg_shadow
, shadow_c
);
4047 msg_lod
= offset(msg_shadow
, bld
, 1);
4052 case SHADER_OPCODE_TXL
:
4054 bld
.MOV(msg_lod
, lod
);
4055 msg_end
= offset(msg_lod
, bld
, 1);
4057 case SHADER_OPCODE_TXD
:
4060 * dPdx = dudx, dvdx, drdx
4061 * dPdy = dudy, dvdy, drdy
4063 * Load up these values:
4064 * - dudx dudy dvdx dvdy drdx drdy
4065 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4068 for (unsigned i
= 0; i
< grad_components
; i
++) {
4069 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4070 msg_end
= offset(msg_end
, bld
, 1);
4072 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4073 msg_end
= offset(msg_end
, bld
, 1);
4076 case SHADER_OPCODE_TXS
:
4077 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4078 bld
.MOV(msg_lod
, lod
);
4079 msg_end
= offset(msg_lod
, bld
, 1);
4081 case SHADER_OPCODE_TXF
:
4082 msg_lod
= offset(msg_coords
, bld
, 3);
4083 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4084 msg_end
= offset(msg_lod
, bld
, 1);
4086 case SHADER_OPCODE_TXF_CMS
:
4087 msg_lod
= offset(msg_coords
, bld
, 3);
4089 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4091 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4092 msg_end
= offset(msg_lod
, bld
, 2);
4099 inst
->src
[0] = reg_undef
;
4100 inst
->src
[1] = surface
;
4101 inst
->src
[2] = sampler
;
4102 inst
->resize_sources(3);
4103 inst
->base_mrf
= message
.nr
;
4104 inst
->mlen
= msg_end
.nr
- message
.nr
;
4105 inst
->header_size
= header_size
;
4107 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4108 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4112 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
4114 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4117 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4121 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4122 const fs_reg
&coordinate
,
4123 const fs_reg
&shadow_c
,
4124 fs_reg lod
, const fs_reg
&lod2
,
4125 const fs_reg
&sample_index
,
4127 const fs_reg
&surface
,
4128 const fs_reg
&sampler
,
4129 const fs_reg
&offset_value
,
4130 unsigned coord_components
,
4131 unsigned grad_components
)
4133 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4134 int reg_width
= bld
.dispatch_width() / 8;
4135 unsigned header_size
= 0, length
= 0;
4136 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4137 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4138 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4140 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4141 offset_value
.file
!= BAD_FILE
|| inst
->eot
||
4142 op
== SHADER_OPCODE_SAMPLEINFO
||
4143 is_high_sampler(devinfo
, sampler
)) {
4144 /* For general texture offsets (no txf workaround), we need a header to
4145 * put them in. Note that we're only reserving space for it in the
4146 * message payload as it will be initialized implicitly by the
4149 * TG4 needs to place its channel select in the header, for interaction
4150 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4151 * larger sampler numbers we need to offset the Sampler State Pointer in
4155 sources
[0] = fs_reg();
4158 /* If we're requesting fewer than four channels worth of response,
4159 * and we have an explicit header, we need to set up the sampler
4160 * writemask. It's reversed from normal: 1 means "don't write".
4162 if (!inst
->eot
&& inst
->regs_written
!= 4 * reg_width
) {
4163 assert((inst
->regs_written
% reg_width
) == 0);
4164 unsigned mask
= ~((1 << (inst
->regs_written
/ reg_width
)) - 1) & 0xf;
4165 inst
->offset
|= mask
<< 12;
4169 if (shadow_c
.file
!= BAD_FILE
) {
4170 bld
.MOV(sources
[length
], shadow_c
);
4174 bool coordinate_done
= false;
4176 /* The sampler can only meaningfully compute LOD for fragment shader
4177 * messages. For all other stages, we change the opcode to TXL and
4178 * hardcode the LOD to 0.
4180 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
4181 op
== SHADER_OPCODE_TEX
) {
4182 op
= SHADER_OPCODE_TXL
;
4183 lod
= brw_imm_f(0.0f
);
4186 /* Set up the LOD info */
4189 case SHADER_OPCODE_TXL
:
4190 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4191 op
= SHADER_OPCODE_TXL_LZ
;
4194 bld
.MOV(sources
[length
], lod
);
4197 case SHADER_OPCODE_TXD
:
4198 /* TXD should have been lowered in SIMD16 mode. */
4199 assert(bld
.dispatch_width() == 8);
4201 /* Load dPdx and the coordinate together:
4202 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4204 for (unsigned i
= 0; i
< coord_components
; i
++) {
4205 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4207 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4208 * only derivatives for (u, v, r).
4210 if (i
< grad_components
) {
4211 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4212 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4216 coordinate_done
= true;
4218 case SHADER_OPCODE_TXS
:
4219 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4222 case SHADER_OPCODE_TXF
:
4223 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4224 * On Gen9 they are u, v, lod, r
4226 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4228 if (devinfo
->gen
>= 9) {
4229 if (coord_components
>= 2) {
4230 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4231 offset(coordinate
, bld
, 1));
4233 sources
[length
] = brw_imm_d(0);
4238 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4239 op
= SHADER_OPCODE_TXF_LZ
;
4241 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4245 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4246 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4247 offset(coordinate
, bld
, i
));
4249 coordinate_done
= true;
4252 case SHADER_OPCODE_TXF_CMS
:
4253 case SHADER_OPCODE_TXF_CMS_W
:
4254 case SHADER_OPCODE_TXF_UMS
:
4255 case SHADER_OPCODE_TXF_MCS
:
4256 if (op
== SHADER_OPCODE_TXF_UMS
||
4257 op
== SHADER_OPCODE_TXF_CMS
||
4258 op
== SHADER_OPCODE_TXF_CMS_W
) {
4259 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4263 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4264 /* Data from the multisample control surface. */
4265 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4268 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4271 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4272 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4275 offset(mcs
, bld
, 1));
4280 /* There is no offsetting for this message; just copy in the integer
4281 * texture coordinates.
4283 for (unsigned i
= 0; i
< coord_components
; i
++)
4284 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4285 offset(coordinate
, bld
, i
));
4287 coordinate_done
= true;
4289 case SHADER_OPCODE_TG4_OFFSET
:
4290 /* gather4_po_c should have been lowered in SIMD16 mode. */
4291 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
4293 /* More crazy intermixing */
4294 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4295 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4297 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4298 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4299 offset(offset_value
, bld
, i
));
4301 if (coord_components
== 3) /* r if present */
4302 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4304 coordinate_done
= true;
4310 /* Set up the coordinate (except for cases where it was done above) */
4311 if (!coordinate_done
) {
4312 for (unsigned i
= 0; i
< coord_components
; i
++)
4313 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4318 mlen
= length
* reg_width
- header_size
;
4320 mlen
= length
* reg_width
;
4322 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4323 BRW_REGISTER_TYPE_F
);
4324 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4326 /* Generate the SEND. */
4328 inst
->src
[0] = src_payload
;
4329 inst
->src
[1] = surface
;
4330 inst
->src
[2] = sampler
;
4331 inst
->resize_sources(3);
4333 inst
->header_size
= header_size
;
4335 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4336 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4340 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4342 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4343 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4344 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4345 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4346 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4347 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4348 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4349 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4350 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4351 const fs_reg
&offset_value
= inst
->src
[TEX_LOGICAL_SRC_OFFSET_VALUE
];
4352 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4353 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4354 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4355 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4357 if (devinfo
->gen
>= 7) {
4358 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4359 shadow_c
, lod
, lod2
, sample_index
,
4360 mcs
, surface
, sampler
, offset_value
,
4361 coord_components
, grad_components
);
4362 } else if (devinfo
->gen
>= 5) {
4363 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4364 shadow_c
, lod
, lod2
, sample_index
,
4365 surface
, sampler
, offset_value
,
4366 coord_components
, grad_components
);
4368 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4369 shadow_c
, lod
, lod2
,
4371 coord_components
, grad_components
);
4376 * Initialize the header present in some typed and untyped surface
4380 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4382 fs_builder ubld
= bld
.exec_all().group(8, 0);
4383 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4384 ubld
.MOV(dst
, brw_imm_d(0));
4385 ubld
.MOV(component(dst
, 7), sample_mask
);
4390 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4391 const fs_reg
&sample_mask
)
4393 /* Get the logical send arguments. */
4394 const fs_reg
&addr
= inst
->src
[0];
4395 const fs_reg
&src
= inst
->src
[1];
4396 const fs_reg
&surface
= inst
->src
[2];
4397 const UNUSED fs_reg
&dims
= inst
->src
[3];
4398 const fs_reg
&arg
= inst
->src
[4];
4400 /* Calculate the total number of components of the payload. */
4401 const unsigned addr_sz
= inst
->components_read(0);
4402 const unsigned src_sz
= inst
->components_read(1);
4403 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4404 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4406 /* Allocate space for the payload. */
4407 fs_reg
*const components
= new fs_reg
[sz
];
4408 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4411 /* Construct the payload. */
4413 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4415 for (unsigned i
= 0; i
< addr_sz
; i
++)
4416 components
[n
++] = offset(addr
, bld
, i
);
4418 for (unsigned i
= 0; i
< src_sz
; i
++)
4419 components
[n
++] = offset(src
, bld
, i
);
4421 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4423 /* Update the original instruction. */
4425 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4426 inst
->header_size
= header_sz
;
4428 inst
->src
[0] = payload
;
4429 inst
->src
[1] = surface
;
4431 inst
->resize_sources(3);
4433 delete[] components
;
4437 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4439 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4441 if (devinfo
->gen
>= 7) {
4442 /* We are switching the instruction from an ALU-like instruction to a
4443 * send-from-grf instruction. Since sends can't handle strides or
4444 * source modifiers, we have to make a copy of the offset source.
4446 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4447 bld
.MOV(tmp
, inst
->src
[1]);
4450 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4453 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4454 BRW_REGISTER_TYPE_UD
);
4456 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4458 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4459 inst
->resize_sources(1);
4460 inst
->base_mrf
= payload
.nr
;
4461 inst
->header_size
= 1;
4462 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4467 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4469 assert(bld
.shader
->devinfo
->gen
< 6);
4472 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4474 if (inst
->sources
> 1) {
4475 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4476 * "Message Payload":
4478 * "Operand0[7]. For the INT DIV functions, this operand is the
4481 * "Operand1[7]. For the INT DIV functions, this operand is the
4484 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4485 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4486 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4488 inst
->resize_sources(1);
4489 inst
->src
[0] = src0
;
4491 assert(inst
->exec_size
== 8);
4492 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4497 fs_visitor::lower_logical_sends()
4499 bool progress
= false;
4501 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4502 const fs_builder
ibld(this, block
, inst
);
4504 switch (inst
->opcode
) {
4505 case FS_OPCODE_FB_WRITE_LOGICAL
:
4506 assert(stage
== MESA_SHADER_FRAGMENT
);
4507 lower_fb_write_logical_send(ibld
, inst
,
4508 (const brw_wm_prog_data
*)prog_data
,
4509 (const brw_wm_prog_key
*)key
,
4513 case SHADER_OPCODE_TEX_LOGICAL
:
4514 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4517 case SHADER_OPCODE_TXD_LOGICAL
:
4518 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4521 case SHADER_OPCODE_TXF_LOGICAL
:
4522 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4525 case SHADER_OPCODE_TXL_LOGICAL
:
4526 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4529 case SHADER_OPCODE_TXS_LOGICAL
:
4530 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4533 case FS_OPCODE_TXB_LOGICAL
:
4534 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4537 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4538 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4541 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4542 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4545 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4546 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4549 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4550 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4553 case SHADER_OPCODE_LOD_LOGICAL
:
4554 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4557 case SHADER_OPCODE_TG4_LOGICAL
:
4558 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4561 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4562 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4565 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4566 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4569 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4570 lower_surface_logical_send(ibld
, inst
,
4571 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4575 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4576 lower_surface_logical_send(ibld
, inst
,
4577 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4578 ibld
.sample_mask_reg());
4581 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4582 lower_surface_logical_send(ibld
, inst
,
4583 SHADER_OPCODE_UNTYPED_ATOMIC
,
4584 ibld
.sample_mask_reg());
4587 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4588 lower_surface_logical_send(ibld
, inst
,
4589 SHADER_OPCODE_TYPED_SURFACE_READ
,
4593 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4594 lower_surface_logical_send(ibld
, inst
,
4595 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4596 ibld
.sample_mask_reg());
4599 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4600 lower_surface_logical_send(ibld
, inst
,
4601 SHADER_OPCODE_TYPED_ATOMIC
,
4602 ibld
.sample_mask_reg());
4605 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4606 lower_varying_pull_constant_logical_send(ibld
, inst
);
4609 case SHADER_OPCODE_RCP
:
4610 case SHADER_OPCODE_RSQ
:
4611 case SHADER_OPCODE_SQRT
:
4612 case SHADER_OPCODE_EXP2
:
4613 case SHADER_OPCODE_LOG2
:
4614 case SHADER_OPCODE_SIN
:
4615 case SHADER_OPCODE_COS
:
4616 case SHADER_OPCODE_POW
:
4617 case SHADER_OPCODE_INT_QUOTIENT
:
4618 case SHADER_OPCODE_INT_REMAINDER
:
4619 /* The math opcodes are overloaded for the send-like and
4620 * expression-like instructions which seems kind of icky. Gen6+ has
4621 * a native (but rather quirky) MATH instruction so we don't need to
4622 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4623 * logical instructions (which we can easily recognize because they
4624 * have mlen = 0) into send-like virtual instructions.
4626 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4627 lower_math_logical_send(ibld
, inst
);
4642 invalidate_live_intervals();
4648 * Get the closest allowed SIMD width for instruction \p inst accounting for
4649 * some common regioning and execution control restrictions that apply to FPU
4650 * instructions. These restrictions don't necessarily have any relevance to
4651 * instructions not executed by the FPU pipeline like extended math, control
4652 * flow or send message instructions.
4654 * For virtual opcodes it's really up to the instruction -- In some cases
4655 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4656 * instructions) it may simplify virtual instruction lowering if we can
4657 * enforce FPU-like regioning restrictions already on the virtual instruction,
4658 * in other cases (e.g. virtual send-like instructions) this may be
4659 * excessively restrictive.
4662 get_fpu_lowered_simd_width(const struct brw_device_info
*devinfo
,
4663 const fs_inst
*inst
)
4665 /* Maximum execution size representable in the instruction controls. */
4666 unsigned max_width
= MIN2(32, inst
->exec_size
);
4668 /* According to the PRMs:
4669 * "A. In Direct Addressing mode, a source cannot span more than 2
4670 * adjacent GRF registers.
4671 * B. A destination cannot span more than 2 adjacent GRF registers."
4673 * Look for the source or destination with the largest register region
4674 * which is the one that is going to limit the overall execution size of
4675 * the instruction due to this rule.
4677 unsigned reg_count
= inst
->regs_written
;
4679 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4680 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4682 /* Calculate the maximum execution size of the instruction based on the
4683 * factor by which it goes over the hardware limit of 2 GRFs.
4686 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4688 /* According to the IVB PRMs:
4689 * "When destination spans two registers, the source MUST span two
4690 * registers. The exception to the above rule:
4692 * - When source is scalar, the source registers are not incremented.
4693 * - When source is packed integer Word and destination is packed
4694 * integer DWord, the source register is not incremented but the
4695 * source sub register is incremented."
4697 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4698 * restrictions. The code below intentionally doesn't check whether the
4699 * destination type is integer because empirically the hardware doesn't
4700 * seem to care what the actual type is as long as it's dword-aligned.
4702 if (devinfo
->gen
< 8) {
4703 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4704 if (inst
->regs_written
== 2 &&
4705 inst
->regs_read(i
) != 0 && inst
->regs_read(i
) != 2 &&
4706 !is_uniform(inst
->src
[i
]) &&
4707 !(type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4708 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1))
4709 max_width
= MIN2(max_width
, inst
->exec_size
/
4710 inst
->regs_written
);
4714 /* From the IVB PRMs:
4715 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4716 * are applied for both halves of the SIMD32 instruction. If different
4717 * execution mask channels are required, split the instruction into two
4718 * SIMD16 instructions."
4720 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4721 * 32-wide control flow support in hardware and will behave similarly.
4723 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4724 max_width
= MIN2(max_width
, 16);
4726 /* From the IVB PRMs (applies to HSW too):
4727 * "Instructions with condition modifiers must not use SIMD32."
4729 * From the BDW PRMs (applies to later hardware too):
4730 * "Ternary instruction with condition modifiers must not use SIMD32."
4732 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4733 max_width
= MIN2(max_width
, 16);
4735 /* From the IVB PRMs (applies to other devices that don't have the
4736 * brw_device_info::supports_simd16_3src flag set):
4737 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4738 * SIMD8 is not allowed for DF operations."
4740 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4741 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4743 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
4744 * the 8-bit quarter of the execution mask signals specified in the
4745 * instruction control fields) for the second compressed half of any
4746 * single-precision instruction (for double-precision instructions
4747 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
4748 * the EU will apply the wrong execution controls for the second
4749 * sequential GRF write if the number of channels per GRF is not exactly
4750 * eight in single-precision mode (or four in double-float mode).
4752 * In this situation we calculate the maximum size of the split
4753 * instructions so they only ever write to a single register.
4755 if (devinfo
->gen
< 8 && inst
->regs_written
> 1 &&
4756 !inst
->force_writemask_all
) {
4757 const unsigned channels_per_grf
= inst
->exec_size
/ inst
->regs_written
;
4758 unsigned exec_type_size
= 0;
4759 for (int i
= 0; i
< inst
->sources
; i
++) {
4760 if (inst
->src
[i
].file
!= BAD_FILE
)
4761 exec_type_size
= MAX2(exec_type_size
, type_sz(inst
->src
[i
].type
));
4763 assert(exec_type_size
);
4765 /* The hardware shifts exactly 8 channels per compressed half of the
4766 * instruction in single-precision mode and exactly 4 in double-precision.
4768 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
4769 max_width
= MIN2(max_width
, channels_per_grf
);
4772 /* Only power-of-two execution sizes are representable in the instruction
4775 return 1 << _mesa_logbase2(max_width
);
4779 * Get the closest native SIMD width supported by the hardware for instruction
4780 * \p inst. The instruction will be left untouched by
4781 * fs_visitor::lower_simd_width() if the returned value is equal to the
4782 * original execution size.
4785 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4786 const fs_inst
*inst
)
4788 switch (inst
->opcode
) {
4789 case BRW_OPCODE_MOV
:
4790 case BRW_OPCODE_SEL
:
4791 case BRW_OPCODE_NOT
:
4792 case BRW_OPCODE_AND
:
4794 case BRW_OPCODE_XOR
:
4795 case BRW_OPCODE_SHR
:
4796 case BRW_OPCODE_SHL
:
4797 case BRW_OPCODE_ASR
:
4798 case BRW_OPCODE_CMPN
:
4799 case BRW_OPCODE_CSEL
:
4800 case BRW_OPCODE_F32TO16
:
4801 case BRW_OPCODE_F16TO32
:
4802 case BRW_OPCODE_BFREV
:
4803 case BRW_OPCODE_BFE
:
4804 case BRW_OPCODE_ADD
:
4805 case BRW_OPCODE_MUL
:
4806 case BRW_OPCODE_AVG
:
4807 case BRW_OPCODE_FRC
:
4808 case BRW_OPCODE_RNDU
:
4809 case BRW_OPCODE_RNDD
:
4810 case BRW_OPCODE_RNDE
:
4811 case BRW_OPCODE_RNDZ
:
4812 case BRW_OPCODE_LZD
:
4813 case BRW_OPCODE_FBH
:
4814 case BRW_OPCODE_FBL
:
4815 case BRW_OPCODE_CBIT
:
4816 case BRW_OPCODE_SAD2
:
4817 case BRW_OPCODE_MAD
:
4818 case BRW_OPCODE_LRP
:
4819 case FS_OPCODE_PACK
:
4820 return get_fpu_lowered_simd_width(devinfo
, inst
);
4822 case BRW_OPCODE_CMP
: {
4823 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4824 * when the destination is a GRF the dependency-clear bit on the flag
4825 * register is cleared early.
4827 * Suggested workarounds are to disable coissuing CMP instructions
4828 * or to split CMP(16) instructions into two CMP(8) instructions.
4830 * We choose to split into CMP(8) instructions since disabling
4831 * coissuing would affect CMP instructions not otherwise affected by
4834 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4835 !inst
->dst
.is_null() ? 8 : ~0);
4836 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4838 case BRW_OPCODE_BFI1
:
4839 case BRW_OPCODE_BFI2
:
4840 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4842 * "Force BFI instructions to be executed always in SIMD8."
4844 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4845 get_fpu_lowered_simd_width(devinfo
, inst
));
4848 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4849 return inst
->exec_size
;
4851 case SHADER_OPCODE_RCP
:
4852 case SHADER_OPCODE_RSQ
:
4853 case SHADER_OPCODE_SQRT
:
4854 case SHADER_OPCODE_EXP2
:
4855 case SHADER_OPCODE_LOG2
:
4856 case SHADER_OPCODE_SIN
:
4857 case SHADER_OPCODE_COS
:
4858 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4861 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4862 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4863 MIN2(8, inst
->exec_size
));
4865 case SHADER_OPCODE_POW
:
4866 /* SIMD16 is only allowed on Gen7+. */
4867 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4868 MIN2(8, inst
->exec_size
));
4870 case SHADER_OPCODE_INT_QUOTIENT
:
4871 case SHADER_OPCODE_INT_REMAINDER
:
4872 /* Integer division is limited to SIMD8 on all generations. */
4873 return MIN2(8, inst
->exec_size
);
4875 case FS_OPCODE_LINTERP
:
4876 case FS_OPCODE_GET_BUFFER_SIZE
:
4877 case FS_OPCODE_DDX_COARSE
:
4878 case FS_OPCODE_DDX_FINE
:
4879 case FS_OPCODE_DDY_COARSE
:
4880 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4881 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4882 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4883 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4884 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4885 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
4886 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4887 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4888 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4889 return MIN2(16, inst
->exec_size
);
4891 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4892 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4893 * message used to implement varying pull constant loads, so expand it
4894 * to SIMD16. An alternative with longer message payload length but
4895 * shorter return payload would be to use the SIMD8 sampler message that
4896 * takes (header, u, v, r) as parameters instead of (header, u).
4898 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4900 case FS_OPCODE_DDY_FINE
:
4901 /* The implementation of this virtual opcode may require emitting
4902 * compressed Align16 instructions, which are severely limited on some
4905 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4906 * Region Restrictions):
4908 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4909 * and SIMD8 is not allowed for DF operations."
4911 * In this context, "DW operations" means "operations acting on 32-bit
4912 * values", so it includes operations on floats.
4914 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4915 * (Instruction Compression -> Rules and Restrictions):
4917 * "A compressed instruction must be in Align1 access mode. Align16
4918 * mode instructions cannot be compressed."
4920 * Similar text exists in the g45 PRM.
4922 * Empirically, compressed align16 instructions using odd register
4923 * numbers don't appear to work on Sandybridge either.
4925 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4926 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4927 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
4929 case SHADER_OPCODE_MULH
:
4930 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4931 * is 8-wide on Gen7+.
4933 return (devinfo
->gen
>= 7 ? 8 :
4934 get_fpu_lowered_simd_width(devinfo
, inst
));
4936 case FS_OPCODE_FB_WRITE_LOGICAL
:
4937 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4940 assert(devinfo
->gen
!= 6 ||
4941 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4942 inst
->exec_size
== 8);
4943 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4944 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4945 8 : MIN2(16, inst
->exec_size
));
4947 case SHADER_OPCODE_TEX_LOGICAL
:
4948 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4949 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4950 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4951 case SHADER_OPCODE_LOD_LOGICAL
:
4952 case SHADER_OPCODE_TG4_LOGICAL
:
4953 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4954 return MIN2(16, inst
->exec_size
);
4956 case SHADER_OPCODE_TXD_LOGICAL
:
4957 /* TXD is unsupported in SIMD16 mode. */
4960 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4961 /* gather4_po_c is unsupported in SIMD16 mode. */
4962 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4963 return (shadow_c
.file
!= BAD_FILE
? 8 : MIN2(16, inst
->exec_size
));
4965 case SHADER_OPCODE_TXL_LOGICAL
:
4966 case FS_OPCODE_TXB_LOGICAL
: {
4967 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4968 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4969 * mode because the message exceeds the maximum length of 11.
4971 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4972 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4974 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4977 return MIN2(16, inst
->exec_size
);
4979 case SHADER_OPCODE_TXF_LOGICAL
:
4980 case SHADER_OPCODE_TXS_LOGICAL
:
4981 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4982 * messages. Use SIMD16 instead.
4984 if (devinfo
->gen
== 4)
4987 return MIN2(16, inst
->exec_size
);
4989 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4990 /* This opcode can take up to 6 arguments which means that in some
4991 * circumstances it can end up with a message that is too long in SIMD16
4994 const unsigned coord_components
=
4995 inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4996 /* First three arguments are the sample index and the two arguments for
4999 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
5002 return MIN2(16, inst
->exec_size
);
5005 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5006 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5007 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5010 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5011 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5012 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5013 return MIN2(16, inst
->exec_size
);
5015 case SHADER_OPCODE_URB_READ_SIMD8
:
5016 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
5017 case SHADER_OPCODE_URB_WRITE_SIMD8
:
5018 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
5019 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
5020 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
5021 return MIN2(8, inst
->exec_size
);
5023 case SHADER_OPCODE_MOV_INDIRECT
:
5024 /* Prior to Broadwell, we only have 8 address subregisters */
5025 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
5026 2 * REG_SIZE
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
5029 case SHADER_OPCODE_LOAD_PAYLOAD
: {
5030 const unsigned reg_count
=
5031 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
5033 if (reg_count
> 2) {
5034 /* Only LOAD_PAYLOAD instructions with per-channel destination region
5035 * can be easily lowered (which excludes headers and heterogeneous
5038 assert(!inst
->header_size
);
5039 for (unsigned i
= 0; i
< inst
->sources
; i
++)
5040 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
5041 inst
->src
[i
].file
== BAD_FILE
);
5043 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
5045 return inst
->exec_size
;
5049 return inst
->exec_size
;
5054 * Return true if splitting out the group of channels of instruction \p inst
5055 * given by lbld.group() requires allocating a temporary for the i-th source
5056 * of the lowered instruction.
5059 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
5061 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
5062 (inst
->components_read(i
) == 1 &&
5063 lbld
.dispatch_width() <= inst
->exec_size
));
5067 * Extract the data that would be consumed by the channel group given by
5068 * lbld.group() from the i-th source region of instruction \p inst and return
5069 * it as result in packed form. If any copy instructions are required they
5070 * will be emitted before the given \p inst in \p block.
5073 emit_unzip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
,
5076 /* Specified channel group from the source region. */
5077 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
5079 if (needs_src_copy(lbld
, inst
, i
)) {
5080 /* Builder of the right width to perform the copy avoiding uninitialized
5081 * data if the lowered execution size is greater than the original
5082 * execution size of the instruction.
5084 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5085 inst
->exec_size
), 0);
5086 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
5088 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
5089 cbld
.at(block
, inst
)
5090 .MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
5094 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
5095 /* The source is invariant for all dispatch_width-wide groups of the
5098 return inst
->src
[i
];
5101 /* We can just point the lowered instruction at the right channel group
5102 * from the original region.
5109 * Return true if splitting out the group of channels of instruction \p inst
5110 * given by lbld.group() requires allocating a temporary for the destination
5111 * of the lowered instruction and copying the data back to the original
5112 * destination region.
5115 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5117 /* If the instruction writes more than one component we'll have to shuffle
5118 * the results of multiple lowered instructions in order to make sure that
5119 * they end up arranged correctly in the original destination region.
5121 if (inst
->regs_written
* REG_SIZE
>
5122 inst
->dst
.component_size(inst
->exec_size
))
5125 /* If the lowered execution size is larger than the original the result of
5126 * the instruction won't fit in the original destination, so we'll have to
5127 * allocate a temporary in any case.
5129 if (lbld
.dispatch_width() > inst
->exec_size
)
5132 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5133 /* If we already made a copy of the source for other reasons there won't
5134 * be any overlap with the destination.
5136 if (needs_src_copy(lbld
, inst
, i
))
5139 /* In order to keep the logic simple we emit a copy whenever the
5140 * destination region doesn't exactly match an overlapping source, which
5141 * may point at the source and destination not being aligned group by
5142 * group which could cause one of the lowered instructions to overwrite
5143 * the data read from the same source by other lowered instructions.
5145 if (regions_overlap(inst
->dst
, inst
->regs_written
* REG_SIZE
,
5146 inst
->src
[i
], inst
->regs_read(i
) * REG_SIZE
) &&
5147 !inst
->dst
.equals(inst
->src
[i
]))
5155 * Insert data from a packed temporary into the channel group given by
5156 * lbld.group() of the destination region of instruction \p inst and return
5157 * the temporary as result. If any copy instructions are required they will
5158 * be emitted around the given \p inst in \p block.
5161 emit_zip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
)
5163 /* Builder of the right width to perform the copy avoiding uninitialized
5164 * data if the lowered execution size is greater than the original
5165 * execution size of the instruction.
5167 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5168 inst
->exec_size
), 0);
5170 /* Specified channel group from the destination region. */
5171 const fs_reg dst
= horiz_offset(inst
->dst
, lbld
.group());
5172 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
5173 inst
->dst
.component_size(inst
->exec_size
);
5175 if (needs_dst_copy(lbld
, inst
)) {
5176 const fs_reg tmp
= lbld
.vgrf(inst
->dst
.type
, dst_size
);
5178 if (inst
->predicate
) {
5179 /* Handle predication by copying the original contents of
5180 * the destination into the temporary before emitting the
5181 * lowered instruction.
5183 for (unsigned k
= 0; k
< dst_size
; ++k
)
5184 cbld
.at(block
, inst
)
5185 .MOV(offset(tmp
, lbld
, k
), offset(dst
, inst
->exec_size
, k
));
5188 for (unsigned k
= 0; k
< dst_size
; ++k
)
5189 cbld
.at(block
, inst
->next
)
5190 .MOV(offset(dst
, inst
->exec_size
, k
), offset(tmp
, lbld
, k
));
5195 /* No need to allocate a temporary for the lowered instruction, just
5196 * take the right group of channels from the original region.
5203 fs_visitor::lower_simd_width()
5205 bool progress
= false;
5207 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5208 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5210 if (lower_width
!= inst
->exec_size
) {
5211 /* Builder matching the original instruction. We may also need to
5212 * emit an instruction of width larger than the original, set the
5213 * execution size of the builder to the highest of both for now so
5214 * we're sure that both cases can be handled.
5216 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5217 const fs_builder ibld
= bld
.at(block
, inst
)
5218 .exec_all(inst
->force_writemask_all
)
5219 .group(max_width
, inst
->group
/ max_width
);
5221 /* Split the copies in chunks of the execution width of either the
5222 * original or the lowered instruction, whichever is lower.
5224 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5225 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
5226 inst
->dst
.component_size(inst
->exec_size
);
5228 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5230 for (unsigned i
= 0; i
< n
; i
++) {
5231 /* Emit a copy of the original instruction with the lowered width.
5232 * If the EOT flag was set throw it away except for the last
5233 * instruction to avoid killing the thread prematurely.
5235 fs_inst split_inst
= *inst
;
5236 split_inst
.exec_size
= lower_width
;
5237 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
5239 /* Select the correct channel enables for the i-th group, then
5240 * transform the sources and destination and emit the lowered
5243 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5245 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5246 split_inst
.src
[j
] = emit_unzip(lbld
, block
, inst
, j
);
5248 split_inst
.dst
= emit_zip(lbld
, block
, inst
);
5249 split_inst
.regs_written
= DIV_ROUND_UP(
5250 split_inst
.dst
.component_size(lower_width
) * dst_size
,
5253 lbld
.emit(split_inst
);
5256 inst
->remove(block
);
5262 invalidate_live_intervals();
5268 fs_visitor::dump_instructions()
5270 dump_instructions(NULL
);
5274 fs_visitor::dump_instructions(const char *name
)
5276 FILE *file
= stderr
;
5277 if (name
&& geteuid() != 0) {
5278 file
= fopen(name
, "w");
5284 calculate_register_pressure();
5285 int ip
= 0, max_pressure
= 0;
5286 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5287 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5288 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5289 dump_instruction(inst
, file
);
5292 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5295 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5296 fprintf(file
, "%4d: ", ip
++);
5297 dump_instruction(inst
, file
);
5301 if (file
!= stderr
) {
5307 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5309 dump_instruction(be_inst
, stderr
);
5313 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5315 fs_inst
*inst
= (fs_inst
*)be_inst
;
5317 if (inst
->predicate
) {
5318 fprintf(file
, "(%cf0.%d) ",
5319 inst
->predicate_inverse
? '-' : '+',
5323 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5325 fprintf(file
, ".sat");
5326 if (inst
->conditional_mod
) {
5327 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5328 if (!inst
->predicate
&&
5329 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5330 inst
->opcode
!= BRW_OPCODE_IF
&&
5331 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5332 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5335 fprintf(file
, "(%d) ", inst
->exec_size
);
5338 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5342 fprintf(file
, "(EOT) ");
5345 switch (inst
->dst
.file
) {
5347 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5348 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
5349 inst
->dst
.subreg_offset
)
5350 fprintf(file
, "+%d.%d",
5351 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
5354 fprintf(file
, "g%d", inst
->dst
.nr
);
5357 fprintf(file
, "m%d", inst
->dst
.nr
);
5360 fprintf(file
, "(null)");
5363 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
5366 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
5369 switch (inst
->dst
.nr
) {
5371 fprintf(file
, "null");
5373 case BRW_ARF_ADDRESS
:
5374 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5376 case BRW_ARF_ACCUMULATOR
:
5377 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5380 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5383 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5386 if (inst
->dst
.subnr
)
5387 fprintf(file
, "+%d", inst
->dst
.subnr
);
5390 unreachable("not reached");
5392 if (inst
->dst
.stride
!= 1)
5393 fprintf(file
, "<%u>", inst
->dst
.stride
);
5394 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
5396 for (int i
= 0; i
< inst
->sources
; i
++) {
5397 if (inst
->src
[i
].negate
)
5399 if (inst
->src
[i
].abs
)
5401 switch (inst
->src
[i
].file
) {
5403 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5404 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
5405 inst
->src
[i
].subreg_offset
)
5406 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
5407 inst
->src
[i
].subreg_offset
);
5410 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5413 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5416 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
5419 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
5420 if (inst
->src
[i
].subreg_offset
) {
5421 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
5422 inst
->src
[i
].subreg_offset
);
5426 fprintf(file
, "(null)");
5429 switch (inst
->src
[i
].type
) {
5430 case BRW_REGISTER_TYPE_F
:
5431 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5433 case BRW_REGISTER_TYPE_DF
:
5434 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5436 case BRW_REGISTER_TYPE_W
:
5437 case BRW_REGISTER_TYPE_D
:
5438 fprintf(file
, "%dd", inst
->src
[i
].d
);
5440 case BRW_REGISTER_TYPE_UW
:
5441 case BRW_REGISTER_TYPE_UD
:
5442 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5444 case BRW_REGISTER_TYPE_VF
:
5445 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5446 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5447 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5448 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5449 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5452 fprintf(file
, "???");
5457 switch (inst
->src
[i
].nr
) {
5459 fprintf(file
, "null");
5461 case BRW_ARF_ADDRESS
:
5462 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5464 case BRW_ARF_ACCUMULATOR
:
5465 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5468 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5471 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5474 if (inst
->src
[i
].subnr
)
5475 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
5478 if (inst
->src
[i
].abs
)
5481 if (inst
->src
[i
].file
!= IMM
) {
5483 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5484 unsigned hstride
= inst
->src
[i
].hstride
;
5485 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5487 stride
= inst
->src
[i
].stride
;
5490 fprintf(file
, "<%u>", stride
);
5492 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
5495 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5496 fprintf(file
, ", ");
5501 if (inst
->force_writemask_all
)
5502 fprintf(file
, "NoMask ");
5504 if (inst
->exec_size
!= dispatch_width
)
5505 fprintf(file
, "group%d ", inst
->group
);
5507 fprintf(file
, "\n");
5511 * Possibly returns an instruction that set up @param reg.
5513 * Sometimes we want to take the result of some expression/variable
5514 * dereference tree and rewrite the instruction generating the result
5515 * of the tree. When processing the tree, we know that the
5516 * instructions generated are all writing temporaries that are dead
5517 * outside of this tree. So, if we have some instructions that write
5518 * a temporary, we're free to point that temp write somewhere else.
5520 * Note that this doesn't guarantee that the instruction generated
5521 * only reg -- it might be the size=4 destination of a texture instruction.
5524 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5529 end
->is_partial_write() ||
5530 !reg
.equals(end
->dst
)) {
5538 fs_visitor::setup_fs_payload_gen6()
5540 assert(stage
== MESA_SHADER_FRAGMENT
);
5541 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5543 unsigned barycentric_interp_modes
=
5544 (stage
== MESA_SHADER_FRAGMENT
) ?
5545 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
5547 assert(devinfo
->gen
>= 6);
5549 /* R0-1: masks, pixel X/Y coordinates. */
5550 payload
.num_regs
= 2;
5551 /* R2: only for 32-pixel dispatch.*/
5553 /* R3-26: barycentric interpolation coordinates. These appear in the
5554 * same order that they appear in the brw_barycentric_mode
5555 * enum. Each set of coordinates occupies 2 registers if dispatch width
5556 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5557 * appear if they were enabled using the "Barycentric Interpolation
5558 * Mode" bits in WM_STATE.
5560 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5561 if (barycentric_interp_modes
& (1 << i
)) {
5562 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5563 payload
.num_regs
+= 2;
5564 if (dispatch_width
== 16) {
5565 payload
.num_regs
+= 2;
5570 /* R27: interpolated depth if uses source depth */
5571 prog_data
->uses_src_depth
=
5572 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5573 if (prog_data
->uses_src_depth
) {
5574 payload
.source_depth_reg
= payload
.num_regs
;
5576 if (dispatch_width
== 16) {
5577 /* R28: interpolated depth if not SIMD8. */
5582 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5583 prog_data
->uses_src_w
=
5584 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5585 if (prog_data
->uses_src_w
) {
5586 payload
.source_w_reg
= payload
.num_regs
;
5588 if (dispatch_width
== 16) {
5589 /* R30: interpolated W if not SIMD8. */
5594 /* R31: MSAA position offsets. */
5595 if (prog_data
->persample_dispatch
&&
5596 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5597 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5599 * "MSDISPMODE_PERSAMPLE is required in order to select
5602 * So we can only really get sample positions if we are doing real
5603 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5604 * persample dispatch, we hard-code it to 0.5.
5606 prog_data
->uses_pos_offset
= true;
5607 payload
.sample_pos_reg
= payload
.num_regs
;
5611 /* R32: MSAA input coverage mask */
5612 prog_data
->uses_sample_mask
=
5613 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5614 if (prog_data
->uses_sample_mask
) {
5615 assert(devinfo
->gen
>= 7);
5616 payload
.sample_mask_in_reg
= payload
.num_regs
;
5618 if (dispatch_width
== 16) {
5619 /* R33: input coverage mask if not SIMD8. */
5624 /* R34-: bary for 32-pixel. */
5625 /* R58-59: interp W for 32-pixel. */
5627 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5628 source_depth_to_render_target
= true;
5633 fs_visitor::setup_vs_payload()
5635 /* R0: thread header, R1: urb handles */
5636 payload
.num_regs
= 2;
5640 fs_visitor::setup_gs_payload()
5642 assert(stage
== MESA_SHADER_GEOMETRY
);
5644 struct brw_gs_prog_data
*gs_prog_data
=
5645 (struct brw_gs_prog_data
*) prog_data
;
5646 struct brw_vue_prog_data
*vue_prog_data
=
5647 (struct brw_vue_prog_data
*) prog_data
;
5649 /* R0: thread header, R1: output URB handles */
5650 payload
.num_regs
= 2;
5652 if (gs_prog_data
->include_primitive_id
) {
5653 /* R2: Primitive ID 0..7 */
5657 /* Use a maximum of 24 registers for push-model inputs. */
5658 const unsigned max_push_components
= 24;
5660 /* If pushing our inputs would take too many registers, reduce the URB read
5661 * length (which is in HWords, or 8 registers), and resort to pulling.
5663 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5664 * have to multiply by VerticesIn to obtain the total storage requirement.
5666 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5667 max_push_components
) {
5668 gs_prog_data
->base
.include_vue_handles
= true;
5670 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5671 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5673 vue_prog_data
->urb_read_length
=
5674 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5679 fs_visitor::setup_cs_payload()
5681 assert(devinfo
->gen
>= 7);
5682 payload
.num_regs
= 1;
5686 fs_visitor::calculate_register_pressure()
5688 invalidate_live_intervals();
5689 calculate_live_intervals();
5691 unsigned num_instructions
= 0;
5692 foreach_block(block
, cfg
)
5693 num_instructions
+= block
->instructions
.length();
5695 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5697 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5698 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5699 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5704 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5706 * The needs_unlit_centroid_workaround ends up producing one of these per
5707 * channel of centroid input, so it's good to clean them up.
5709 * An assumption here is that nothing ever modifies the dispatched pixels
5710 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5711 * dictates that anyway.
5714 fs_visitor::opt_drop_redundant_mov_to_flags()
5716 bool flag_mov_found
[2] = {false};
5717 bool progress
= false;
5719 /* Instructions removed by this pass can only be added if this were true */
5720 if (!devinfo
->needs_unlit_centroid_workaround
)
5723 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5724 if (inst
->is_control_flow()) {
5725 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5726 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5727 if (!flag_mov_found
[inst
->flag_subreg
]) {
5728 flag_mov_found
[inst
->flag_subreg
] = true;
5730 inst
->remove(block
);
5733 } else if (inst
->flags_written()) {
5734 flag_mov_found
[inst
->flag_subreg
] = false;
5742 fs_visitor::optimize()
5744 /* Start by validating the shader we currently have. */
5747 /* bld is the common builder object pointing at the end of the program we
5748 * used to translate it into i965 IR. For the optimization and lowering
5749 * passes coming next, any code added after the end of the program without
5750 * having explicitly called fs_builder::at() clearly points at a mistake.
5751 * Ideally optimization passes wouldn't be part of the visitor so they
5752 * wouldn't have access to bld at all, but they do, so just in case some
5753 * pass forgets to ask for a location explicitly set it to NULL here to
5754 * make it trip. The dispatch width is initialized to a bogus value to
5755 * make sure that optimizations set the execution controls explicitly to
5756 * match the code they are manipulating instead of relying on the defaults.
5758 bld
= fs_builder(this, 64);
5760 assign_constant_locations();
5761 lower_constant_loads();
5765 split_virtual_grfs();
5768 #define OPT(pass, args...) ({ \
5770 bool this_progress = pass(args); \
5772 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5773 char filename[64]; \
5774 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5775 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5777 backend_shader::dump_instructions(filename); \
5782 progress = progress || this_progress; \
5786 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5788 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5789 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5791 backend_shader::dump_instructions(filename
);
5794 bool progress
= false;
5798 OPT(opt_drop_redundant_mov_to_flags
);
5805 OPT(remove_duplicate_mrf_writes
);
5809 OPT(opt_copy_propagate
);
5810 OPT(opt_predicated_break
, this);
5811 OPT(opt_cmod_propagation
);
5812 OPT(dead_code_eliminate
);
5813 OPT(opt_peephole_sel
);
5814 OPT(dead_control_flow_eliminate
, this);
5815 OPT(opt_register_renaming
);
5816 OPT(opt_saturate_propagation
);
5817 OPT(register_coalesce
);
5818 OPT(compute_to_mrf
);
5819 OPT(eliminate_find_live_channel
);
5821 OPT(compact_virtual_grfs
);
5827 if (OPT(lower_pack
)) {
5828 OPT(register_coalesce
);
5829 OPT(dead_code_eliminate
);
5832 if (OPT(lower_d2x
)) {
5833 OPT(opt_copy_propagate
);
5834 OPT(dead_code_eliminate
);
5837 OPT(lower_simd_width
);
5839 /* After SIMD lowering just in case we had to unroll the EOT send. */
5840 OPT(opt_sampler_eot
);
5842 OPT(lower_logical_sends
);
5845 OPT(opt_copy_propagate
);
5846 /* Only run after logical send lowering because it's easier to implement
5847 * in terms of physical sends.
5849 if (OPT(opt_zero_samples
))
5850 OPT(opt_copy_propagate
);
5851 /* Run after logical send lowering to give it a chance to CSE the
5852 * LOAD_PAYLOAD instructions created to construct the payloads of
5853 * e.g. texturing messages in cases where it wasn't possible to CSE the
5854 * whole logical instruction.
5857 OPT(register_coalesce
);
5858 OPT(compute_to_mrf
);
5859 OPT(dead_code_eliminate
);
5860 OPT(remove_duplicate_mrf_writes
);
5861 OPT(opt_peephole_sel
);
5864 OPT(opt_redundant_discard_jumps
);
5866 if (OPT(lower_load_payload
)) {
5867 split_virtual_grfs();
5868 OPT(register_coalesce
);
5869 OPT(compute_to_mrf
);
5870 OPT(dead_code_eliminate
);
5873 OPT(opt_combine_constants
);
5874 OPT(lower_integer_multiplication
);
5876 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5877 OPT(opt_cmod_propagation
);
5879 OPT(opt_copy_propagate
);
5880 OPT(dead_code_eliminate
);
5883 lower_uniform_pull_constant_loads();
5889 * Three source instruction must have a GRF/MRF destination register.
5890 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5893 fs_visitor::fixup_3src_null_dest()
5895 bool progress
= false;
5897 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5898 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5899 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5906 invalidate_live_intervals();
5910 fs_visitor::allocate_registers(bool allow_spilling
)
5912 bool allocated_without_spills
;
5914 static const enum instruction_scheduler_mode pre_modes
[] = {
5916 SCHEDULE_PRE_NON_LIFO
,
5920 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
5922 /* Try each scheduling heuristic to see if it can successfully register
5923 * allocate without spilling. They should be ordered by decreasing
5924 * performance but increasing likelihood of allocating.
5926 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5927 schedule_instructions(pre_modes
[i
]);
5930 assign_regs_trivial();
5931 allocated_without_spills
= true;
5933 allocated_without_spills
= assign_regs(false, spill_all
);
5935 if (allocated_without_spills
)
5939 if (!allocated_without_spills
) {
5940 /* We assume that any spilling is worse than just dropping back to
5941 * SIMD8. There's probably actually some intermediate point where
5942 * SIMD16 with a couple of spills is still better.
5944 if (dispatch_width
> min_dispatch_width
) {
5945 fail("Failure to register allocate. Reduce number of "
5946 "live scalar values to avoid this.");
5948 compiler
->shader_perf_log(log_data
,
5949 "%s shader triggered register spilling. "
5950 "Try reducing the number of live scalar "
5951 "values to improve performance.\n",
5955 /* Since we're out of heuristics, just go spill registers until we
5956 * get an allocation.
5958 while (!assign_regs(true, spill_all
)) {
5964 assert(last_scratch
== 0 || allow_spilling
);
5966 /* This must come after all optimization and register allocation, since
5967 * it inserts dead code that happens to have side effects, and it does
5968 * so based on the actual physical registers in use.
5970 insert_gen4_send_dependency_workarounds();
5975 schedule_instructions(SCHEDULE_POST
);
5977 if (last_scratch
> 0) {
5978 unsigned max_scratch_size
= 2 * 1024 * 1024;
5980 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5982 if (stage
== MESA_SHADER_COMPUTE
) {
5983 if (devinfo
->is_haswell
) {
5984 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5985 * field documentation, Haswell supports a minimum of 2kB of
5986 * scratch space for compute shaders, unlike every other stage
5989 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
5990 } else if (devinfo
->gen
<= 7) {
5991 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5992 * field documentation, platforms prior to Haswell measure scratch
5993 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
5995 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
5996 max_scratch_size
= 12 * 1024;
6000 /* We currently only support up to 2MB of scratch space. If we
6001 * need to support more eventually, the documentation suggests
6002 * that we could allocate a larger buffer, and partition it out
6003 * ourselves. We'd just have to undo the hardware's address
6004 * calculation by subtracting (FFTID * Per Thread Scratch Space)
6005 * and then add FFTID * (Larger Per Thread Scratch Space).
6007 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
6008 * Thread Group Tracking > Local Memory/Scratch Space.
6010 assert(prog_data
->total_scratch
< max_scratch_size
);
6015 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
6017 assert(stage
== MESA_SHADER_VERTEX
);
6021 if (shader_time_index
>= 0)
6022 emit_shader_time_begin();
6029 compute_clip_distance(clip_planes
);
6033 if (shader_time_index
>= 0)
6034 emit_shader_time_end();
6040 assign_curb_setup();
6041 assign_vs_urb_setup();
6043 fixup_3src_null_dest();
6044 allocate_registers(true);
6050 fs_visitor::run_tcs_single_patch()
6052 assert(stage
== MESA_SHADER_TESS_CTRL
);
6054 struct brw_tcs_prog_data
*tcs_prog_data
=
6055 (struct brw_tcs_prog_data
*) prog_data
;
6057 /* r1-r4 contain the ICP handles. */
6058 payload
.num_regs
= 5;
6060 if (shader_time_index
>= 0)
6061 emit_shader_time_begin();
6063 /* Initialize gl_InvocationID */
6064 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
6065 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6066 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
6067 bld
.MOV(channels_ud
, channels_uw
);
6069 if (tcs_prog_data
->instances
== 1) {
6070 invocation_id
= channels_ud
;
6072 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6074 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
6075 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6076 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6077 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
6078 brw_imm_ud(INTEL_MASK(23, 17)));
6079 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
6081 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
6084 /* Fix the disptach mask */
6085 if (nir
->info
.tcs
.vertices_out
% 8) {
6086 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
6087 brw_imm_ud(nir
->info
.tcs
.vertices_out
), BRW_CONDITIONAL_L
);
6088 bld
.IF(BRW_PREDICATE_NORMAL
);
6093 if (nir
->info
.tcs
.vertices_out
% 8) {
6094 bld
.emit(BRW_OPCODE_ENDIF
);
6097 /* Emit EOT write; set TR DS Cache bit */
6099 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6100 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6101 fs_reg(brw_imm_ud(0)),
6103 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6104 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6106 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6107 bld
.null_reg_ud(), payload
);
6111 if (shader_time_index
>= 0)
6112 emit_shader_time_end();
6121 assign_curb_setup();
6122 assign_tcs_single_patch_urb_setup();
6124 fixup_3src_null_dest();
6125 allocate_registers(true);
6131 fs_visitor::run_tes()
6133 assert(stage
== MESA_SHADER_TESS_EVAL
);
6135 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6136 payload
.num_regs
= 5;
6138 if (shader_time_index
>= 0)
6139 emit_shader_time_begin();
6148 if (shader_time_index
>= 0)
6149 emit_shader_time_end();
6155 assign_curb_setup();
6156 assign_tes_urb_setup();
6158 fixup_3src_null_dest();
6159 allocate_registers(true);
6165 fs_visitor::run_gs()
6167 assert(stage
== MESA_SHADER_GEOMETRY
);
6171 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6173 if (gs_compile
->control_data_header_size_bits
> 0) {
6174 /* Create a VGRF to store accumulated control data bits. */
6175 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6177 /* If we're outputting more than 32 control data bits, then EmitVertex()
6178 * will set control_data_bits to 0 after emitting the first vertex.
6179 * Otherwise, we need to initialize it to 0 here.
6181 if (gs_compile
->control_data_header_size_bits
<= 32) {
6182 const fs_builder abld
= bld
.annotate("initialize control data bits");
6183 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6187 if (shader_time_index
>= 0)
6188 emit_shader_time_begin();
6192 emit_gs_thread_end();
6194 if (shader_time_index
>= 0)
6195 emit_shader_time_end();
6204 assign_curb_setup();
6205 assign_gs_urb_setup();
6207 fixup_3src_null_dest();
6208 allocate_registers(true);
6214 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6216 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
6217 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6219 assert(stage
== MESA_SHADER_FRAGMENT
);
6221 if (devinfo
->gen
>= 6)
6222 setup_fs_payload_gen6();
6224 setup_fs_payload_gen4();
6228 } else if (do_rep_send
) {
6229 assert(dispatch_width
== 16);
6230 emit_repclear_shader();
6232 if (shader_time_index
>= 0)
6233 emit_shader_time_begin();
6235 calculate_urb_setup();
6236 if (nir
->info
.inputs_read
> 0) {
6237 if (devinfo
->gen
< 6)
6238 emit_interpolation_setup_gen4();
6240 emit_interpolation_setup_gen6();
6243 /* We handle discards by keeping track of the still-live pixels in f0.1.
6244 * Initialize it with the dispatched pixels.
6246 if (wm_prog_data
->uses_kill
) {
6247 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6248 discard_init
->flag_subreg
= 1;
6251 /* Generate FS IR for main(). (the visitor only descends into
6252 * functions called "main").
6259 if (wm_prog_data
->uses_kill
)
6260 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6262 if (wm_key
->alpha_test_func
)
6267 if (shader_time_index
>= 0)
6268 emit_shader_time_end();
6274 assign_curb_setup();
6277 fixup_3src_null_dest();
6278 allocate_registers(allow_spilling
);
6288 fs_visitor::run_cs()
6290 assert(stage
== MESA_SHADER_COMPUTE
);
6294 if (shader_time_index
>= 0)
6295 emit_shader_time_begin();
6297 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6298 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6299 const fs_builder abld
= bld
.exec_all().group(1, 0);
6300 abld
.MOV(retype(suboffset(brw_sr0_reg(), 1), BRW_REGISTER_TYPE_UW
),
6301 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6309 emit_cs_terminate();
6311 if (shader_time_index
>= 0)
6312 emit_shader_time_end();
6318 assign_curb_setup();
6320 fixup_3src_null_dest();
6321 allocate_registers(true);
6330 * Return a bitfield where bit n is set if barycentric interpolation mode n
6331 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6334 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
6335 const nir_shader
*shader
)
6337 unsigned barycentric_interp_modes
= 0;
6339 nir_foreach_variable(var
, &shader
->inputs
) {
6340 /* Ignore WPOS; it doesn't require interpolation. */
6341 if (var
->data
.location
== VARYING_SLOT_POS
)
6344 /* Flat inputs don't need barycentric modes. */
6345 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6348 /* Determine the set (or sets) of barycentric coordinates needed to
6349 * interpolate this variable. Note that when
6350 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
6351 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
6352 * for lit pixels, so we need both sets of barycentric coordinates.
6354 enum brw_barycentric_mode bary_mode
=
6355 barycentric_mode((glsl_interp_mode
) var
->data
.interpolation
,
6356 var
->data
.centroid
, var
->data
.sample
);
6358 barycentric_interp_modes
|= 1 << bary_mode
;
6360 if (var
->data
.centroid
&& devinfo
->needs_unlit_centroid_workaround
)
6361 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary_mode
);
6364 return barycentric_interp_modes
;
6368 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6369 const nir_shader
*shader
)
6371 prog_data
->flat_inputs
= 0;
6373 nir_foreach_variable(var
, &shader
->inputs
) {
6374 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6376 if (input_index
< 0)
6380 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6381 prog_data
->flat_inputs
|= (1 << input_index
);
6386 computed_depth_mode(const nir_shader
*shader
)
6388 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6389 switch (shader
->info
.fs
.depth_layout
) {
6390 case FRAG_DEPTH_LAYOUT_NONE
:
6391 case FRAG_DEPTH_LAYOUT_ANY
:
6392 return BRW_PSCDEPTH_ON
;
6393 case FRAG_DEPTH_LAYOUT_GREATER
:
6394 return BRW_PSCDEPTH_ON_GE
;
6395 case FRAG_DEPTH_LAYOUT_LESS
:
6396 return BRW_PSCDEPTH_ON_LE
;
6397 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6398 return BRW_PSCDEPTH_OFF
;
6401 return BRW_PSCDEPTH_OFF
;
6405 * Apply default interpolation settings to FS inputs which don't specify any.
6408 brw_nir_set_default_interpolation(const struct brw_device_info
*devinfo
,
6409 struct nir_shader
*nir
,
6410 bool api_flat_shade
,
6411 bool per_sample_interpolation
)
6413 assert(nir
->stage
== MESA_SHADER_FRAGMENT
);
6415 nir_foreach_variable(var
, &nir
->inputs
) {
6416 /* Apply default interpolation mode.
6418 * Everything defaults to smooth except for the legacy GL color
6419 * built-in variables, which might be flat depending on API state.
6421 if (var
->data
.interpolation
== INTERP_MODE_NONE
) {
6422 const bool flat
= api_flat_shade
&&
6423 (var
->data
.location
== VARYING_SLOT_COL0
||
6424 var
->data
.location
== VARYING_SLOT_COL1
);
6426 var
->data
.interpolation
= flat
? INTERP_MODE_FLAT
6427 : INTERP_MODE_SMOOTH
;
6430 /* Apply 'sample' if necessary for API state. */
6431 if (per_sample_interpolation
&&
6432 var
->data
.interpolation
!= INTERP_MODE_FLAT
) {
6433 var
->data
.centroid
= false;
6434 var
->data
.sample
= true;
6437 /* On Ironlake and below, there is only one interpolation mode.
6438 * Centroid interpolation doesn't mean anything on this hardware --
6439 * there is no multisampling.
6441 if (devinfo
->gen
< 6) {
6442 var
->data
.centroid
= false;
6443 var
->data
.sample
= false;
6449 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6451 const struct brw_wm_prog_key
*key
,
6452 struct brw_wm_prog_data
*prog_data
,
6453 const nir_shader
*src_shader
,
6454 struct gl_program
*prog
,
6455 int shader_time_index8
, int shader_time_index16
,
6456 bool allow_spilling
,
6458 unsigned *final_assembly_size
,
6461 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6462 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6464 brw_nir_set_default_interpolation(compiler
->devinfo
, shader
,
6465 key
->flat_shade
, key
->persample_interp
);
6466 brw_nir_lower_fs_inputs(shader
);
6467 brw_nir_lower_fs_outputs(shader
);
6468 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6470 /* key->alpha_test_func means simulating alpha testing via discards,
6471 * so the shader definitely kills pixels.
6473 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
6474 prog_data
->uses_omask
= key
->multisample_fbo
&&
6475 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6476 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6477 prog_data
->computed_stencil
=
6478 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6480 prog_data
->persample_dispatch
=
6481 key
->multisample_fbo
&&
6482 (key
->persample_interp
||
6483 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6484 SYSTEM_BIT_SAMPLE_POS
)) ||
6485 shader
->info
.fs
.uses_sample_qualifier
);
6487 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
6489 prog_data
->barycentric_interp_modes
=
6490 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
6492 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6493 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6494 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6496 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6497 &prog_data
->base
, prog
, shader
, 8,
6498 shader_time_index8
);
6499 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6501 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6504 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6506 simd8_grf_start
= v8
.payload
.num_regs
;
6507 simd8_grf_used
= v8
.grf_used
;
6510 if (v8
.max_dispatch_width
>= 16 &&
6511 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6512 /* Try a SIMD16 compile */
6513 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6514 &prog_data
->base
, prog
, shader
, 16,
6515 shader_time_index16
);
6516 v16
.import_uniforms(&v8
);
6517 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6518 compiler
->shader_perf_log(log_data
,
6519 "SIMD16 shader failed to compile: %s",
6522 simd16_cfg
= v16
.cfg
;
6523 simd16_grf_start
= v16
.payload
.num_regs
;
6524 simd16_grf_used
= v16
.grf_used
;
6528 /* When the caller requests a repclear shader, they want SIMD16-only */
6532 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6533 * at the top to select the shader. We've never implemented that.
6534 * Instead, we just give them exactly one shader and we pick the widest one
6537 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6540 if (prog_data
->persample_dispatch
) {
6541 /* Starting with SandyBridge (where we first get MSAA), the different
6542 * pixel dispatch combinations are grouped into classifications A
6543 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6544 * generations, the only configurations supporting persample dispatch
6545 * are are this in which only one dispatch width is enabled.
6547 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6548 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6550 if (compiler
->devinfo
->gen
== 6 &&
6551 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6553 } else if (simd16_cfg
) {
6558 /* We have to compute the flat inputs after the visitor is finished running
6559 * because it relies on prog_data->urb_setup which is computed in
6560 * fs_visitor::calculate_urb_setup().
6562 brw_compute_flat_inputs(prog_data
, shader
);
6564 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6565 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6566 MESA_SHADER_FRAGMENT
);
6568 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6569 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6570 shader
->info
.label
? shader
->info
.label
:
6572 shader
->info
.name
));
6576 prog_data
->dispatch_8
= true;
6577 g
.generate_code(simd8_cfg
, 8);
6578 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6579 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6582 prog_data
->dispatch_16
= true;
6583 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6584 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6585 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6587 } else if (simd16_cfg
) {
6588 prog_data
->dispatch_16
= true;
6589 g
.generate_code(simd16_cfg
, 16);
6590 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6591 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6594 return g
.get_assembly(final_assembly_size
);
6598 fs_visitor::emit_cs_work_group_id_setup()
6600 assert(stage
== MESA_SHADER_COMPUTE
);
6602 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6604 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6605 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6606 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6608 bld
.MOV(*reg
, r0_1
);
6609 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6610 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6616 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
6618 block
->dwords
= dwords
;
6619 block
->regs
= DIV_ROUND_UP(dwords
, 8);
6620 block
->size
= block
->regs
* 32;
6624 cs_fill_push_const_info(const struct brw_device_info
*devinfo
,
6625 struct brw_cs_prog_data
*cs_prog_data
)
6627 const struct brw_stage_prog_data
*prog_data
=
6628 (struct brw_stage_prog_data
*) cs_prog_data
;
6629 bool fill_thread_id
=
6630 cs_prog_data
->thread_local_id_index
>= 0 &&
6631 cs_prog_data
->thread_local_id_index
< (int)prog_data
->nr_params
;
6632 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
6634 /* The thread ID should be stored in the last param dword */
6635 assert(prog_data
->nr_params
> 0 || !fill_thread_id
);
6636 assert(!fill_thread_id
||
6637 cs_prog_data
->thread_local_id_index
==
6638 (int)prog_data
->nr_params
- 1);
6640 unsigned cross_thread_dwords
, per_thread_dwords
;
6641 if (!cross_thread_supported
) {
6642 cross_thread_dwords
= 0u;
6643 per_thread_dwords
= prog_data
->nr_params
;
6644 } else if (fill_thread_id
) {
6645 /* Fill all but the last register with cross-thread payload */
6646 cross_thread_dwords
= 8 * (cs_prog_data
->thread_local_id_index
/ 8);
6647 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
6648 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
6650 /* Fill all data using cross-thread payload */
6651 cross_thread_dwords
= prog_data
->nr_params
;
6652 per_thread_dwords
= 0u;
6655 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
6656 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
6658 unsigned total_dwords
=
6659 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
6660 cs_prog_data
->push
.cross_thread
.size
) / 4;
6661 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
6663 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
6664 cs_prog_data
->push
.per_thread
.size
== 0);
6665 assert(cs_prog_data
->push
.cross_thread
.dwords
+
6666 cs_prog_data
->push
.per_thread
.dwords
==
6667 prog_data
->nr_params
);
6671 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
6673 cs_prog_data
->simd_size
= size
;
6674 unsigned group_size
= cs_prog_data
->local_size
[0] *
6675 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
6676 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
6680 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6682 const struct brw_cs_prog_key
*key
,
6683 struct brw_cs_prog_data
*prog_data
,
6684 const nir_shader
*src_shader
,
6685 int shader_time_index
,
6686 unsigned *final_assembly_size
,
6689 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6690 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6692 brw_nir_lower_cs_shared(shader
);
6693 prog_data
->base
.total_shared
+= shader
->num_shared
;
6695 /* Now that we cloned the nir_shader, we can update num_uniforms based on
6696 * the thread_local_id_index.
6698 assert(prog_data
->thread_local_id_index
>= 0);
6699 shader
->num_uniforms
=
6700 MAX2(shader
->num_uniforms
,
6701 (unsigned)4 * (prog_data
->thread_local_id_index
+ 1));
6703 brw_nir_lower_intrinsics(shader
, &prog_data
->base
);
6704 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6706 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
6707 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
6708 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
6709 unsigned local_workgroup_size
=
6710 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
6711 shader
->info
.cs
.local_size
[2];
6713 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
6714 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
6717 const char *fail_msg
= NULL
;
6719 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6721 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6722 NULL
, /* Never used in core profile */
6723 shader
, 8, shader_time_index
);
6724 if (simd_required
<= 8) {
6726 fail_msg
= v8
.fail_msg
;
6729 cs_set_simd_size(prog_data
, 8);
6730 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6731 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
6735 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6736 NULL
, /* Never used in core profile */
6737 shader
, 16, shader_time_index
);
6738 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6739 !fail_msg
&& v8
.max_dispatch_width
>= 16 &&
6740 simd_required
<= 16) {
6741 /* Try a SIMD16 compile */
6742 if (simd_required
<= 8)
6743 v16
.import_uniforms(&v8
);
6744 if (!v16
.run_cs()) {
6745 compiler
->shader_perf_log(log_data
,
6746 "SIMD16 shader failed to compile: %s",
6750 "Couldn't generate SIMD16 program and not "
6751 "enough threads for SIMD8";
6755 cs_set_simd_size(prog_data
, 16);
6756 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6757 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
6761 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6762 NULL
, /* Never used in core profile */
6763 shader
, 32, shader_time_index
);
6764 if (!fail_msg
&& v8
.max_dispatch_width
>= 32 &&
6765 (simd_required
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
6766 /* Try a SIMD32 compile */
6767 if (simd_required
<= 8)
6768 v32
.import_uniforms(&v8
);
6769 else if (simd_required
<= 16)
6770 v32
.import_uniforms(&v16
);
6772 if (!v32
.run_cs()) {
6773 compiler
->shader_perf_log(log_data
,
6774 "SIMD32 shader failed to compile: %s",
6778 "Couldn't generate SIMD32 program and not "
6779 "enough threads for SIMD16";
6783 cs_set_simd_size(prog_data
, 32);
6784 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6788 if (unlikely(cfg
== NULL
)) {
6791 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6796 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6797 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6798 MESA_SHADER_COMPUTE
);
6799 if (INTEL_DEBUG
& DEBUG_CS
) {
6800 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6801 shader
->info
.label
? shader
->info
.label
:
6804 g
.enable_debug(name
);
6807 g
.generate_code(cfg
, prog_data
->simd_size
);
6809 return g
.get_assembly(final_assembly_size
);