2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "compiler/glsl_types.h"
42 #include "compiler/nir/nir_builder.h"
43 #include "program/prog_parameter.h"
47 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
51 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
52 const fs_reg
*src
, unsigned sources
)
54 memset(this, 0, sizeof(*this));
56 this->src
= new fs_reg
[MAX2(sources
, 3)];
57 for (unsigned i
= 0; i
< sources
; i
++)
58 this->src
[i
] = src
[i
];
60 this->opcode
= opcode
;
62 this->sources
= sources
;
63 this->exec_size
= exec_size
;
66 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
68 assert(this->exec_size
!= 0);
70 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
72 /* This will be the case for almost all instructions. */
79 this->size_written
= dst
.component_size(exec_size
);
82 this->size_written
= 0;
86 unreachable("Invalid destination register file");
89 this->writes_accumulator
= false;
94 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
99 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
104 init(opcode
, exec_size
, dst
, NULL
, 0);
107 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg src
[1] = { src0
};
111 init(opcode
, exec_size
, dst
, src
, 1);
114 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
115 const fs_reg
&src0
, const fs_reg
&src1
)
117 const fs_reg src
[2] = { src0
, src1
};
118 init(opcode
, exec_size
, dst
, src
, 2);
121 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
122 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
124 const fs_reg src
[3] = { src0
, src1
, src2
};
125 init(opcode
, exec_size
, dst
, src
, 3);
128 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
129 const fs_reg src
[], unsigned sources
)
131 init(opcode
, exec_width
, dst
, src
, sources
);
134 fs_inst::fs_inst(const fs_inst
&that
)
136 memcpy(this, &that
, sizeof(that
));
138 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
140 for (unsigned i
= 0; i
< that
.sources
; i
++)
141 this->src
[i
] = that
.src
[i
];
150 fs_inst::resize_sources(uint8_t num_sources
)
152 if (this->sources
!= num_sources
) {
153 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
155 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
156 src
[i
] = this->src
[i
];
160 this->sources
= num_sources
;
165 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
167 const fs_reg
&surf_index
,
168 const fs_reg
&varying_offset
,
169 uint32_t const_offset
)
171 /* We have our constant surface use a pitch of 4 bytes, so our index can
172 * be any component of a vector, and then we load 4 contiguous
173 * components starting from that.
175 * We break down the const_offset to a portion added to the variable
176 * offset and a portion done using reg_offset, which means that if you
177 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
178 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
179 * CSE can later notice that those loads are all the same and eliminate
180 * the redundant ones.
182 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
183 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
185 /* The pull load message will load a vec4 (16 bytes). If we are loading
186 * a double this means we are only loading 2 elements worth of data.
187 * We also want to use a 32-bit data type for the dst of the load operation
188 * so other parts of the driver don't get confused about the size of the
191 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
192 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
193 vec4_result
, surf_index
, vec4_offset
);
194 inst
->size_written
= 4 * bld
.dispatch_width() / 8 * REG_SIZE
;
196 if (type_sz(dst
.type
) == 8) {
197 shuffle_32bit_load_result_to_64bit_data(
198 bld
, retype(vec4_result
, dst
.type
), vec4_result
, 2);
201 vec4_result
.type
= dst
.type
;
202 bld
.MOV(dst
, offset(vec4_result
, bld
,
203 (const_offset
& 0xf) / type_sz(vec4_result
.type
)));
207 * A helper for MOV generation for fixing up broken hardware SEND dependency
211 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
213 /* The caller always wants uncompressed to emit the minimal extra
214 * dependencies, and to avoid having to deal with aligning its regs to 2.
216 const fs_builder ubld
= bld
.annotate("send dependency resolve")
219 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
223 fs_inst::equals(fs_inst
*inst
) const
225 return (opcode
== inst
->opcode
&&
226 dst
.equals(inst
->dst
) &&
227 src
[0].equals(inst
->src
[0]) &&
228 src
[1].equals(inst
->src
[1]) &&
229 src
[2].equals(inst
->src
[2]) &&
230 saturate
== inst
->saturate
&&
231 predicate
== inst
->predicate
&&
232 conditional_mod
== inst
->conditional_mod
&&
233 mlen
== inst
->mlen
&&
234 base_mrf
== inst
->base_mrf
&&
235 target
== inst
->target
&&
237 header_size
== inst
->header_size
&&
238 shadow_compare
== inst
->shadow_compare
&&
239 exec_size
== inst
->exec_size
&&
240 offset
== inst
->offset
);
244 fs_inst::overwrites_reg(const fs_reg
®
) const
246 return reg
.in_range(dst
, DIV_ROUND_UP(size_written
, REG_SIZE
));
250 fs_inst::is_send_from_grf() const
253 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
254 case SHADER_OPCODE_SHADER_TIME_ADD
:
255 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
256 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
257 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
258 case SHADER_OPCODE_UNTYPED_ATOMIC
:
259 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
260 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
261 case SHADER_OPCODE_TYPED_ATOMIC
:
262 case SHADER_OPCODE_TYPED_SURFACE_READ
:
263 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
264 case SHADER_OPCODE_URB_WRITE_SIMD8
:
265 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
266 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
267 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
268 case SHADER_OPCODE_URB_READ_SIMD8
:
269 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
271 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
272 return src
[1].file
== VGRF
;
273 case FS_OPCODE_FB_WRITE
:
274 case FS_OPCODE_FB_READ
:
275 return src
[0].file
== VGRF
;
278 return src
[0].file
== VGRF
;
285 * Returns true if this instruction's sources and destinations cannot
286 * safely be the same register.
288 * In most cases, a register can be written over safely by the same
289 * instruction that is its last use. For a single instruction, the
290 * sources are dereferenced before writing of the destination starts
293 * However, there are a few cases where this can be problematic:
295 * - Virtual opcodes that translate to multiple instructions in the
296 * code generator: if src == dst and one instruction writes the
297 * destination before a later instruction reads the source, then
298 * src will have been clobbered.
300 * - SIMD16 compressed instructions with certain regioning (see below).
302 * The register allocator uses this information to set up conflicts between
303 * GRF sources and the destination.
306 fs_inst::has_source_and_destination_hazard() const
309 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
310 /* Multiple partial writes to the destination */
313 /* The SIMD16 compressed instruction
315 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
317 * is actually decoded in hardware as:
319 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
320 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
322 * Which is safe. However, if we have uniform accesses
323 * happening, we get into trouble:
325 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
326 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
328 * Now our destination for the first instruction overwrote the
329 * second instruction's src0, and we get garbage for those 8
330 * pixels. There's a similar issue for the pre-gen6
331 * pixel_x/pixel_y, which are registers of 16-bit values and thus
332 * would get stomped by the first decode as well.
334 if (exec_size
== 16) {
335 for (int i
= 0; i
< sources
; i
++) {
336 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
337 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
338 src
[i
].type
== BRW_REGISTER_TYPE_W
||
339 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
340 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
350 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
352 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
355 fs_reg reg
= this->src
[0];
356 if (reg
.file
!= VGRF
|| reg
.offset
/ REG_SIZE
!= 0 || reg
.stride
== 0)
359 if (grf_alloc
.sizes
[reg
.nr
] * REG_SIZE
!= this->size_written
)
362 for (int i
= 0; i
< this->sources
; i
++) {
363 reg
.type
= this->src
[i
].type
;
364 if (!this->src
[i
].equals(reg
))
367 if (i
< this->header_size
) {
368 reg
.offset
+= REG_SIZE
;
370 reg
= horiz_offset(reg
, this->exec_size
);
378 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
)
380 if (devinfo
->gen
== 6 && is_math())
383 if (is_send_from_grf())
386 if (!backend_instruction::can_do_source_mods())
393 fs_inst::can_change_types() const
395 return dst
.type
== src
[0].type
&&
396 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
397 (opcode
== BRW_OPCODE_MOV
||
398 (opcode
== BRW_OPCODE_SEL
&&
399 dst
.type
== src
[1].type
&&
400 predicate
!= BRW_PREDICATE_NONE
&&
401 !src
[1].abs
&& !src
[1].negate
));
405 fs_inst::has_side_effects() const
407 return this->eot
|| backend_instruction::has_side_effects();
413 memset(this, 0, sizeof(*this));
417 /** Generic unset register constructor. */
421 this->file
= BAD_FILE
;
424 fs_reg::fs_reg(struct ::brw_reg reg
) :
429 if (this->file
== IMM
&&
430 (this->type
!= BRW_REGISTER_TYPE_V
&&
431 this->type
!= BRW_REGISTER_TYPE_UV
&&
432 this->type
!= BRW_REGISTER_TYPE_VF
)) {
438 fs_reg::equals(const fs_reg
&r
) const
440 return (this->backend_reg::equals(r
) &&
445 fs_reg::set_smear(unsigned subreg
)
447 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
448 offset
= ROUND_DOWN_TO(offset
, REG_SIZE
) + subreg
* type_sz(type
);
454 fs_reg::is_contiguous() const
460 fs_reg::component_size(unsigned width
) const
462 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
465 return MAX2(width
* stride
, 1) * type_sz(type
);
469 type_size_scalar(const struct glsl_type
*type
)
471 unsigned int size
, i
;
473 switch (type
->base_type
) {
476 case GLSL_TYPE_FLOAT
:
478 return type
->components();
479 case GLSL_TYPE_DOUBLE
:
480 return type
->components() * 2;
481 case GLSL_TYPE_ARRAY
:
482 return type_size_scalar(type
->fields
.array
) * type
->length
;
483 case GLSL_TYPE_STRUCT
:
485 for (i
= 0; i
< type
->length
; i
++) {
486 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
489 case GLSL_TYPE_SAMPLER
:
490 /* Samplers take up no register space, since they're baked in at
494 case GLSL_TYPE_ATOMIC_UINT
:
496 case GLSL_TYPE_SUBROUTINE
:
498 case GLSL_TYPE_IMAGE
:
499 return BRW_IMAGE_PARAM_SIZE
;
501 case GLSL_TYPE_ERROR
:
502 case GLSL_TYPE_INTERFACE
:
503 case GLSL_TYPE_FUNCTION
:
504 unreachable("not reached");
511 * Returns the number of scalar components needed to store type, assuming
512 * that vectors are padded out to vec4.
514 * This has the packing rules of type_size_vec4(), but counts components
515 * similar to type_size_scalar().
518 type_size_vec4_times_4(const struct glsl_type
*type
)
520 return 4 * type_size_vec4(type
);
523 /* Attribute arrays are loaded as one vec4 per element (or matrix column),
524 * except for double-precision types, which are loaded as one dvec4.
527 type_size_vs_input(const struct glsl_type
*type
)
529 if (type
->is_double()) {
530 return type_size_dvec4(type
);
532 return type_size_vec4(type
);
537 * Create a MOV to read the timestamp register.
539 * The caller is responsible for emitting the MOV. The return value is
540 * the destination of the MOV, with extra parameters set.
543 fs_visitor::get_timestamp(const fs_builder
&bld
)
545 assert(devinfo
->gen
>= 7);
547 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
550 BRW_REGISTER_TYPE_UD
));
552 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
554 /* We want to read the 3 fields we care about even if it's not enabled in
557 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
563 fs_visitor::emit_shader_time_begin()
565 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
567 /* We want only the low 32 bits of the timestamp. Since it's running
568 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
569 * which is plenty of time for our purposes. It is identical across the
570 * EUs, but since it's tracking GPU core speed it will increment at a
571 * varying rate as render P-states change.
573 shader_start_time
.set_smear(0);
577 fs_visitor::emit_shader_time_end()
579 /* Insert our code just before the final SEND with EOT. */
580 exec_node
*end
= this->instructions
.get_tail();
581 assert(end
&& ((fs_inst
*) end
)->eot
);
582 const fs_builder ibld
= bld
.annotate("shader time end")
583 .exec_all().at(NULL
, end
);
585 fs_reg shader_end_time
= get_timestamp(ibld
);
587 /* We only use the low 32 bits of the timestamp - see
588 * emit_shader_time_begin()).
590 * We could also check if render P-states have changed (or anything
591 * else that might disrupt timing) by setting smear to 2 and checking if
592 * that field is != 0.
594 shader_end_time
.set_smear(0);
596 /* Check that there weren't any timestamp reset events (assuming these
597 * were the only two timestamp reads that happened).
599 fs_reg reset
= shader_end_time
;
601 set_condmod(BRW_CONDITIONAL_Z
,
602 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
603 ibld
.IF(BRW_PREDICATE_NORMAL
);
605 fs_reg start
= shader_start_time
;
607 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
610 const fs_builder cbld
= ibld
.group(1, 0);
611 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
613 /* If there were no instructions between the two timestamp gets, the diff
614 * is 2 cycles. Remove that overhead, so I can forget about that when
615 * trying to determine the time taken for single instructions.
617 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
618 SHADER_TIME_ADD(cbld
, 0, diff
);
619 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
620 ibld
.emit(BRW_OPCODE_ELSE
);
621 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
622 ibld
.emit(BRW_OPCODE_ENDIF
);
626 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
627 int shader_time_subindex
,
630 int index
= shader_time_index
* 3 + shader_time_subindex
;
631 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
634 if (dispatch_width
== 8)
635 payload
= vgrf(glsl_type::uvec2_type
);
637 payload
= vgrf(glsl_type::uint_type
);
639 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
643 fs_visitor::vfail(const char *format
, va_list va
)
652 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
653 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
655 this->fail_msg
= msg
;
658 fprintf(stderr
, "%s", msg
);
663 fs_visitor::fail(const char *format
, ...)
667 va_start(va
, format
);
673 * Mark this program as impossible to compile with dispatch width greater
676 * During the SIMD8 compile (which happens first), we can detect and flag
677 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
678 * SIMD16+ compile altogether.
680 * During a compile of dispatch width greater than n (if one happens anyway),
681 * this just calls fail().
684 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
686 if (dispatch_width
> n
) {
689 max_dispatch_width
= n
;
690 compiler
->shader_perf_log(log_data
,
691 "Shader dispatch width limited to SIMD%d: %s",
697 * Returns true if the instruction has a flag that means it won't
698 * update an entire destination register.
700 * For example, dead code elimination and live variable analysis want to know
701 * when a write to a variable screens off any preceding values that were in
705 fs_inst::is_partial_write() const
707 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
708 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
709 !this->dst
.is_contiguous() ||
710 this->dst
.offset
% REG_SIZE
!= 0);
714 fs_inst::components_read(unsigned i
) const
716 /* Return zero if the source is not present. */
717 if (src
[i
].file
== BAD_FILE
)
721 case FS_OPCODE_LINTERP
:
727 case FS_OPCODE_PIXEL_X
:
728 case FS_OPCODE_PIXEL_Y
:
732 case FS_OPCODE_FB_WRITE_LOGICAL
:
733 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
734 /* First/second FB write color. */
736 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
740 case SHADER_OPCODE_TEX_LOGICAL
:
741 case SHADER_OPCODE_TXD_LOGICAL
:
742 case SHADER_OPCODE_TXF_LOGICAL
:
743 case SHADER_OPCODE_TXL_LOGICAL
:
744 case SHADER_OPCODE_TXS_LOGICAL
:
745 case FS_OPCODE_TXB_LOGICAL
:
746 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
747 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
748 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
749 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
750 case SHADER_OPCODE_LOD_LOGICAL
:
751 case SHADER_OPCODE_TG4_LOGICAL
:
752 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
753 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
754 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
755 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
756 /* Texture coordinates. */
757 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
758 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
759 /* Texture derivatives. */
760 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
761 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
762 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
763 /* Texture offset. */
764 else if (i
== TEX_LOGICAL_SRC_OFFSET_VALUE
)
767 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
772 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
773 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
774 assert(src
[3].file
== IMM
);
775 /* Surface coordinates. */
778 /* Surface operation source (ignored for reads). */
784 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
785 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
786 assert(src
[3].file
== IMM
&&
788 /* Surface coordinates. */
791 /* Surface operation source. */
797 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
798 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
799 assert(src
[3].file
== IMM
&&
801 const unsigned op
= src
[4].ud
;
802 /* Surface coordinates. */
805 /* Surface operation source. */
806 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
808 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
809 op
== BRW_AOP_PREDEC
))
821 fs_inst::size_read(int arg
) const
824 case FS_OPCODE_FB_WRITE
:
825 case FS_OPCODE_FB_READ
:
826 case SHADER_OPCODE_URB_WRITE_SIMD8
:
827 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
828 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
829 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
830 case SHADER_OPCODE_URB_READ_SIMD8
:
831 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
832 case SHADER_OPCODE_UNTYPED_ATOMIC
:
833 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
834 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
835 case SHADER_OPCODE_TYPED_ATOMIC
:
836 case SHADER_OPCODE_TYPED_SURFACE_READ
:
837 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
838 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
840 return mlen
* REG_SIZE
;
843 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
844 /* The payload is actually stored in src1 */
846 return mlen
* REG_SIZE
;
849 case FS_OPCODE_LINTERP
:
854 case SHADER_OPCODE_LOAD_PAYLOAD
:
855 if (arg
< this->header_size
)
859 case CS_OPCODE_CS_TERMINATE
:
860 case SHADER_OPCODE_BARRIER
:
863 case SHADER_OPCODE_MOV_INDIRECT
:
865 assert(src
[2].file
== IMM
);
866 unsigned region_length
= src
[2].ud
;
868 if (src
[0].file
== UNIFORM
) {
869 assert(region_length
% 4 == 0);
870 return region_length
;
871 } else if (src
[0].file
== FIXED_GRF
) {
872 /* If the start of the region is not register aligned, then
873 * there's some portion of the register that's technically
874 * unread at the beginning.
876 * However, the register allocator works in terms of whole
877 * registers, and does not use subnr. It assumes that the
878 * read starts at the beginning of the register, and extends
879 * regs_read() whole registers beyond that.
881 * To compensate, we extend the region length to include this
882 * unread portion at the beginning.
885 region_length
+= src
[0].subnr
;
887 return region_length
;
889 assert(!"Invalid register file");
895 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
896 return mlen
* REG_SIZE
;
900 switch (src
[arg
].file
) {
903 return components_read(arg
) * type_sz(src
[arg
].type
);
909 return components_read(arg
) * src
[arg
].component_size(exec_size
);
911 unreachable("MRF registers are not allowed as sources");
917 /* Return the subset of flag registers that an instruction could
918 * potentially read or write based on the execution controls and flag
919 * subregister number of the instruction.
922 flag_mask(const fs_inst
*inst
)
924 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
925 const unsigned end
= start
+ inst
->exec_size
;
926 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
931 fs_inst::flags_read(const gen_device_info
*devinfo
) const
933 /* XXX - This doesn't consider explicit uses of the flag register as source
936 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
937 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
938 /* The vertical predication modes combine corresponding bits from
939 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
941 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
942 return flag_mask(this) << shift
| flag_mask(this);
943 } else if (predicate
) {
944 return flag_mask(this);
951 fs_inst::flags_written() const
953 /* XXX - This doesn't consider explicit uses of the flag register as
954 * destination region.
956 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
957 opcode
!= BRW_OPCODE_IF
&&
958 opcode
!= BRW_OPCODE_WHILE
)) ||
959 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
960 return flag_mask(this);
967 * Returns how many MRFs an FS opcode will write over.
969 * Note that this is not the 0 or 1 implied writes in an actual gen
970 * instruction -- the FS opcodes often generate MOVs in addition.
973 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
978 if (inst
->base_mrf
== -1)
981 switch (inst
->opcode
) {
982 case SHADER_OPCODE_RCP
:
983 case SHADER_OPCODE_RSQ
:
984 case SHADER_OPCODE_SQRT
:
985 case SHADER_OPCODE_EXP2
:
986 case SHADER_OPCODE_LOG2
:
987 case SHADER_OPCODE_SIN
:
988 case SHADER_OPCODE_COS
:
989 return 1 * dispatch_width
/ 8;
990 case SHADER_OPCODE_POW
:
991 case SHADER_OPCODE_INT_QUOTIENT
:
992 case SHADER_OPCODE_INT_REMAINDER
:
993 return 2 * dispatch_width
/ 8;
994 case SHADER_OPCODE_TEX
:
996 case SHADER_OPCODE_TXD
:
997 case SHADER_OPCODE_TXF
:
998 case SHADER_OPCODE_TXF_CMS
:
999 case SHADER_OPCODE_TXF_MCS
:
1000 case SHADER_OPCODE_TG4
:
1001 case SHADER_OPCODE_TG4_OFFSET
:
1002 case SHADER_OPCODE_TXL
:
1003 case SHADER_OPCODE_TXS
:
1004 case SHADER_OPCODE_LOD
:
1005 case SHADER_OPCODE_SAMPLEINFO
:
1007 case FS_OPCODE_FB_WRITE
:
1009 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1010 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1012 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1014 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1017 unreachable("not reached");
1022 fs_visitor::vgrf(const glsl_type
*const type
)
1024 int reg_width
= dispatch_width
/ 8;
1025 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
1026 brw_type_for_base_type(type
));
1029 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1034 this->type
= BRW_REGISTER_TYPE_F
;
1035 this->stride
= (file
== UNIFORM
? 0 : 1);
1038 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1044 this->stride
= (file
== UNIFORM
? 0 : 1);
1047 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1048 * This brings in those uniform definitions
1051 fs_visitor::import_uniforms(fs_visitor
*v
)
1053 this->push_constant_loc
= v
->push_constant_loc
;
1054 this->pull_constant_loc
= v
->pull_constant_loc
;
1055 this->uniforms
= v
->uniforms
;
1059 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1061 assert(stage
== MESA_SHADER_FRAGMENT
);
1063 /* gl_FragCoord.x */
1064 bld
.MOV(wpos
, this->pixel_x
);
1065 wpos
= offset(wpos
, bld
, 1);
1067 /* gl_FragCoord.y */
1068 bld
.MOV(wpos
, this->pixel_y
);
1069 wpos
= offset(wpos
, bld
, 1);
1071 /* gl_FragCoord.z */
1072 if (devinfo
->gen
>= 6) {
1073 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1075 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1076 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1077 interp_reg(VARYING_SLOT_POS
, 2));
1079 wpos
= offset(wpos
, bld
, 1);
1081 /* gl_FragCoord.w: Already set up in emit_interpolation */
1082 bld
.MOV(wpos
, this->wpos_w
);
1085 enum brw_barycentric_mode
1086 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1088 /* Barycentric modes don't make sense for flat inputs. */
1089 assert(mode
!= INTERP_MODE_FLAT
);
1093 case nir_intrinsic_load_barycentric_pixel
:
1094 case nir_intrinsic_load_barycentric_at_offset
:
1095 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1097 case nir_intrinsic_load_barycentric_centroid
:
1098 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1100 case nir_intrinsic_load_barycentric_sample
:
1101 case nir_intrinsic_load_barycentric_at_sample
:
1102 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1105 unreachable("invalid intrinsic");
1108 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1111 return (enum brw_barycentric_mode
) bary
;
1115 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1117 static enum brw_barycentric_mode
1118 centroid_to_pixel(enum brw_barycentric_mode bary
)
1120 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1121 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1122 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1126 fs_visitor::emit_frontfacing_interpolation()
1128 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1130 if (devinfo
->gen
>= 6) {
1131 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1132 * a boolean result from this (~0/true or 0/false).
1134 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1135 * this task in only one instruction:
1136 * - a negation source modifier will flip the bit; and
1137 * - a W -> D type conversion will sign extend the bit into the high
1138 * word of the destination.
1140 * An ASR 15 fills the low word of the destination.
1142 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1145 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1147 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1148 * a boolean result from this (1/true or 0/false).
1150 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1151 * the negation source modifier to flip it. Unfortunately the SHR
1152 * instruction only operates on UD (or D with an abs source modifier)
1153 * sources without negation.
1155 * Instead, use ASR (which will give ~0/true or 0/false).
1157 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1160 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1167 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1169 assert(stage
== MESA_SHADER_FRAGMENT
);
1170 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1171 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1173 if (wm_prog_data
->persample_dispatch
) {
1174 /* Convert int_sample_pos to floating point */
1175 bld
.MOV(dst
, int_sample_pos
);
1176 /* Scale to the range [0, 1] */
1177 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1180 /* From ARB_sample_shading specification:
1181 * "When rendering to a non-multisample buffer, or if multisample
1182 * rasterization is disabled, gl_SamplePosition will always be
1185 bld
.MOV(dst
, brw_imm_f(0.5f
));
1190 fs_visitor::emit_samplepos_setup()
1192 assert(devinfo
->gen
>= 6);
1194 const fs_builder abld
= bld
.annotate("compute sample position");
1195 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1197 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1198 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1200 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1201 * mode will be enabled.
1203 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1204 * R31.1:0 Position Offset X/Y for Slot[3:0]
1205 * R31.3:2 Position Offset X/Y for Slot[7:4]
1208 * The X, Y sample positions come in as bytes in thread payload. So, read
1209 * the positions using vstride=16, width=8, hstride=2.
1211 struct brw_reg sample_pos_reg
=
1212 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1213 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1215 if (dispatch_width
== 8) {
1216 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1218 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1219 abld
.half(1).MOV(half(int_sample_x
, 1),
1220 fs_reg(suboffset(sample_pos_reg
, 16)));
1222 /* Compute gl_SamplePosition.x */
1223 compute_sample_position(pos
, int_sample_x
);
1224 pos
= offset(pos
, abld
, 1);
1225 if (dispatch_width
== 8) {
1226 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1228 abld
.half(0).MOV(half(int_sample_y
, 0),
1229 fs_reg(suboffset(sample_pos_reg
, 1)));
1230 abld
.half(1).MOV(half(int_sample_y
, 1),
1231 fs_reg(suboffset(sample_pos_reg
, 17)));
1233 /* Compute gl_SamplePosition.y */
1234 compute_sample_position(pos
, int_sample_y
);
1239 fs_visitor::emit_sampleid_setup()
1241 assert(stage
== MESA_SHADER_FRAGMENT
);
1242 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1243 assert(devinfo
->gen
>= 6);
1245 const fs_builder abld
= bld
.annotate("compute sample id");
1246 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1248 if (!key
->multisample_fbo
) {
1249 /* As per GL_ARB_sample_shading specification:
1250 * "When rendering to a non-multisample buffer, or if multisample
1251 * rasterization is disabled, gl_SampleID will always be zero."
1253 abld
.MOV(*reg
, brw_imm_d(0));
1254 } else if (devinfo
->gen
>= 8) {
1255 /* Sample ID comes in as 4-bit numbers in g1.0:
1257 * 15:12 Slot 3 SampleID (only used in SIMD16)
1258 * 11:8 Slot 2 SampleID (only used in SIMD16)
1259 * 7:4 Slot 1 SampleID
1260 * 3:0 Slot 0 SampleID
1262 * Each slot corresponds to four channels, so we want to replicate each
1263 * half-byte value to 4 channels in a row:
1265 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1266 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1268 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1269 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1271 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1272 * channels to read the first byte (7:0), and the second group of 8
1273 * channels to read the second byte (15:8). Then, we shift right by
1274 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1275 * values into place. Finally, we AND with 0xf to keep the low nibble.
1277 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1278 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1280 * TODO: These payload bits exist on Gen7 too, but they appear to always
1281 * be zero, so this code fails to work. We should find out why.
1283 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1285 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1286 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1287 brw_imm_v(0x44440000));
1288 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1290 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1292 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1294 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1295 * 8x multisampling, subspan 0 will represent sample N (where N
1296 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1297 * 7. We can find the value of N by looking at R0.0 bits 7:6
1298 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1299 * (since samples are always delivered in pairs). That is, we
1300 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1301 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1302 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1303 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1304 * populating a temporary variable with the sequence (0, 1, 2, 3),
1305 * and then reading from it using vstride=1, width=4, hstride=0.
1306 * These computations hold good for 4x multisampling as well.
1308 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1309 * the first four slots are sample 0 of subspan 0; the next four
1310 * are sample 1 of subspan 0; the third group is sample 0 of
1311 * subspan 1, and finally sample 1 of subspan 1.
1314 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1315 * accomodate 16x MSAA.
1317 abld
.exec_all().group(1, 0)
1318 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1320 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1322 /* This works for both SIMD8 and SIMD16 */
1323 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1325 /* This special instruction takes care of setting vstride=1,
1326 * width=4, hstride=0 of t2 during an ADD instruction.
1328 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1335 fs_visitor::emit_samplemaskin_setup()
1337 assert(stage
== MESA_SHADER_FRAGMENT
);
1338 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1339 assert(devinfo
->gen
>= 6);
1341 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1343 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1344 BRW_REGISTER_TYPE_D
));
1346 if (wm_prog_data
->persample_dispatch
) {
1347 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1348 * and a mask representing which sample is being processed by the
1349 * current shader invocation.
1351 * From the OES_sample_variables specification:
1352 * "When per-sample shading is active due to the use of a fragment input
1353 * qualified by "sample" or due to the use of the gl_SampleID or
1354 * gl_SamplePosition variables, only the bit for the current sample is
1355 * set in gl_SampleMaskIn."
1357 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1359 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1360 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1362 fs_reg one
= vgrf(glsl_type::int_type
);
1363 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1364 abld
.MOV(one
, brw_imm_d(1));
1365 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1366 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1368 /* In per-pixel mode, the coverage mask is sufficient. */
1369 *reg
= coverage_mask
;
1375 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1377 if (!src
.abs
&& !src
.negate
)
1380 fs_reg temp
= bld
.vgrf(src
.type
);
1387 fs_visitor::emit_discard_jump()
1389 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1391 /* For performance, after a discard, jump to the end of the
1392 * shader if all relevant channels have been discarded.
1394 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1395 discard_jump
->flag_subreg
= 1;
1397 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1398 discard_jump
->predicate_inverse
= true;
1402 fs_visitor::emit_gs_thread_end()
1404 assert(stage
== MESA_SHADER_GEOMETRY
);
1406 struct brw_gs_prog_data
*gs_prog_data
=
1407 (struct brw_gs_prog_data
*) prog_data
;
1409 if (gs_compile
->control_data_header_size_bits
> 0) {
1410 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1413 const fs_builder abld
= bld
.annotate("thread end");
1416 if (gs_prog_data
->static_vertex_count
!= -1) {
1417 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1418 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1419 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1420 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1421 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1424 /* Delete now dead instructions. */
1425 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1431 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1435 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1436 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1437 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1440 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1441 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1442 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1443 sources
[1] = this->final_gs_vertex_count
;
1444 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1445 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1453 fs_visitor::assign_curb_setup()
1455 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1457 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1458 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1459 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1460 if (inst
->src
[i
].file
== UNIFORM
) {
1461 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1463 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1464 constant_nr
= push_constant_loc
[uniform_nr
];
1466 /* Section 5.11 of the OpenGL 4.1 spec says:
1467 * "Out-of-bounds reads return undefined values, which include
1468 * values from other variables of the active program or zero."
1469 * Just return the first push constant.
1474 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1477 brw_reg
.abs
= inst
->src
[i
].abs
;
1478 brw_reg
.negate
= inst
->src
[i
].negate
;
1480 assert(inst
->src
[i
].stride
== 0);
1481 inst
->src
[i
] = byte_offset(
1482 retype(brw_reg
, inst
->src
[i
].type
),
1483 inst
->src
[i
].offset
% 4);
1488 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1489 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1493 fs_visitor::calculate_urb_setup()
1495 assert(stage
== MESA_SHADER_FRAGMENT
);
1496 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1497 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1499 memset(prog_data
->urb_setup
, -1,
1500 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1503 /* Figure out where each of the incoming setup attributes lands. */
1504 if (devinfo
->gen
>= 6) {
1505 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1506 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1507 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1508 * first 16 varying inputs, so we can put them wherever we want.
1509 * Just put them in order.
1511 * This is useful because it means that (a) inputs not used by the
1512 * fragment shader won't take up valuable register space, and (b) we
1513 * won't have to recompile the fragment shader if it gets paired with
1514 * a different vertex (or geometry) shader.
1516 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1517 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1518 BITFIELD64_BIT(i
)) {
1519 prog_data
->urb_setup
[i
] = urb_next
++;
1523 bool include_vue_header
=
1524 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1526 /* We have enough input varyings that the SF/SBE pipeline stage can't
1527 * arbitrarily rearrange them to suit our whim; we have to put them
1528 * in an order that matches the output of the previous pipeline stage
1529 * (geometry or vertex shader).
1531 struct brw_vue_map prev_stage_vue_map
;
1532 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1533 key
->input_slots_valid
,
1534 nir
->info
.separate_shader
);
1536 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1538 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1539 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1541 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1542 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1543 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1544 BITFIELD64_BIT(varying
))) {
1545 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1548 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1551 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1552 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1553 /* Point size is packed into the header, not as a general attribute */
1554 if (i
== VARYING_SLOT_PSIZ
)
1557 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1558 /* The back color slot is skipped when the front color is
1559 * also written to. In addition, some slots can be
1560 * written in the vertex shader and not read in the
1561 * fragment shader. So the register number must always be
1562 * incremented, mapped or not.
1564 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1565 prog_data
->urb_setup
[i
] = urb_next
;
1571 * It's a FS only attribute, and we did interpolation for this attribute
1572 * in SF thread. So, count it here, too.
1574 * See compile_sf_prog() for more info.
1576 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1577 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1580 prog_data
->num_varying_inputs
= urb_next
;
1584 fs_visitor::assign_urb_setup()
1586 assert(stage
== MESA_SHADER_FRAGMENT
);
1587 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1589 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1591 /* Offset all the urb_setup[] index by the actual position of the
1592 * setup regs, now that the location of the constants has been chosen.
1594 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1595 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1596 assert(inst
->src
[1].file
== FIXED_GRF
);
1597 inst
->src
[1].nr
+= urb_start
;
1600 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1601 assert(inst
->src
[0].file
== FIXED_GRF
);
1602 inst
->src
[0].nr
+= urb_start
;
1606 /* Each attribute is 4 setup channels, each of which is half a reg. */
1607 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1611 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1613 for (int i
= 0; i
< inst
->sources
; i
++) {
1614 if (inst
->src
[i
].file
== ATTR
) {
1615 int grf
= payload
.num_regs
+
1616 prog_data
->curb_read_length
+
1618 inst
->src
[i
].offset
/ REG_SIZE
;
1620 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1622 * VertStride must be used to cross GRF register boundaries. This
1623 * rule implies that elements within a 'Width' cannot cross GRF
1626 * So, for registers that are large enough, we have to split the exec
1627 * size in two and trust the compression state to sort it out.
1629 unsigned total_size
= inst
->exec_size
*
1630 inst
->src
[i
].stride
*
1631 type_sz(inst
->src
[i
].type
);
1633 assert(total_size
<= 2 * REG_SIZE
);
1634 const unsigned exec_size
=
1635 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1637 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1638 struct brw_reg reg
=
1639 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1640 inst
->src
[i
].offset
% REG_SIZE
),
1641 exec_size
* inst
->src
[i
].stride
,
1642 width
, inst
->src
[i
].stride
);
1643 reg
.abs
= inst
->src
[i
].abs
;
1644 reg
.negate
= inst
->src
[i
].negate
;
1652 fs_visitor::assign_vs_urb_setup()
1654 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1656 assert(stage
== MESA_SHADER_VERTEX
);
1658 /* Each attribute is 4 regs. */
1659 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1661 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1663 /* Rewrite all ATTR file references to the hw grf that they land in. */
1664 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1665 convert_attr_sources_to_hw_regs(inst
);
1670 fs_visitor::assign_tcs_single_patch_urb_setup()
1672 assert(stage
== MESA_SHADER_TESS_CTRL
);
1674 /* Rewrite all ATTR file references to HW_REGs. */
1675 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1676 convert_attr_sources_to_hw_regs(inst
);
1681 fs_visitor::assign_tes_urb_setup()
1683 assert(stage
== MESA_SHADER_TESS_EVAL
);
1685 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1687 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1689 /* Rewrite all ATTR file references to HW_REGs. */
1690 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1691 convert_attr_sources_to_hw_regs(inst
);
1696 fs_visitor::assign_gs_urb_setup()
1698 assert(stage
== MESA_SHADER_GEOMETRY
);
1700 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1702 first_non_payload_grf
+=
1703 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1705 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1706 /* Rewrite all ATTR file references to GRFs. */
1707 convert_attr_sources_to_hw_regs(inst
);
1713 * Split large virtual GRFs into separate components if we can.
1715 * This is mostly duplicated with what brw_fs_vector_splitting does,
1716 * but that's really conservative because it's afraid of doing
1717 * splitting that doesn't result in real progress after the rest of
1718 * the optimization phases, which would cause infinite looping in
1719 * optimization. We can do it once here, safely. This also has the
1720 * opportunity to split interpolated values, or maybe even uniforms,
1721 * which we don't have at the IR level.
1723 * We want to split, because virtual GRFs are what we register
1724 * allocate and spill (due to contiguousness requirements for some
1725 * instructions), and they're what we naturally generate in the
1726 * codegen process, but most virtual GRFs don't actually need to be
1727 * contiguous sets of GRFs. If we split, we'll end up with reduced
1728 * live intervals and better dead code elimination and coalescing.
1731 fs_visitor::split_virtual_grfs()
1733 int num_vars
= this->alloc
.count
;
1735 /* Count the total number of registers */
1737 int vgrf_to_reg
[num_vars
];
1738 for (int i
= 0; i
< num_vars
; i
++) {
1739 vgrf_to_reg
[i
] = reg_count
;
1740 reg_count
+= alloc
.sizes
[i
];
1743 /* An array of "split points". For each register slot, this indicates
1744 * if this slot can be separated from the previous slot. Every time an
1745 * instruction uses multiple elements of a register (as a source or
1746 * destination), we mark the used slots as inseparable. Then we go
1747 * through and split the registers into the smallest pieces we can.
1749 bool split_points
[reg_count
];
1750 memset(split_points
, 0, sizeof(split_points
));
1752 /* Mark all used registers as fully splittable */
1753 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1754 if (inst
->dst
.file
== VGRF
) {
1755 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1756 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1757 split_points
[reg
+ j
] = true;
1760 for (int i
= 0; i
< inst
->sources
; i
++) {
1761 if (inst
->src
[i
].file
== VGRF
) {
1762 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1763 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1764 split_points
[reg
+ j
] = true;
1769 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1770 if (inst
->dst
.file
== VGRF
) {
1771 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1772 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1773 split_points
[reg
+ j
] = false;
1775 for (int i
= 0; i
< inst
->sources
; i
++) {
1776 if (inst
->src
[i
].file
== VGRF
) {
1777 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1778 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1779 split_points
[reg
+ j
] = false;
1784 int new_virtual_grf
[reg_count
];
1785 int new_reg_offset
[reg_count
];
1788 for (int i
= 0; i
< num_vars
; i
++) {
1789 /* The first one should always be 0 as a quick sanity check. */
1790 assert(split_points
[reg
] == false);
1793 new_reg_offset
[reg
] = 0;
1798 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1799 /* If this is a split point, reset the offset to 0 and allocate a
1800 * new virtual GRF for the previous offset many registers
1802 if (split_points
[reg
]) {
1803 assert(offset
<= MAX_VGRF_SIZE
);
1804 int grf
= alloc
.allocate(offset
);
1805 for (int k
= reg
- offset
; k
< reg
; k
++)
1806 new_virtual_grf
[k
] = grf
;
1809 new_reg_offset
[reg
] = offset
;
1814 /* The last one gets the original register number */
1815 assert(offset
<= MAX_VGRF_SIZE
);
1816 alloc
.sizes
[i
] = offset
;
1817 for (int k
= reg
- offset
; k
< reg
; k
++)
1818 new_virtual_grf
[k
] = i
;
1820 assert(reg
== reg_count
);
1822 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1823 if (inst
->dst
.file
== VGRF
) {
1824 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1825 inst
->dst
.nr
= new_virtual_grf
[reg
];
1826 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
1827 inst
->dst
.offset
% REG_SIZE
;
1828 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1830 for (int i
= 0; i
< inst
->sources
; i
++) {
1831 if (inst
->src
[i
].file
== VGRF
) {
1832 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1833 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1834 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
1835 inst
->src
[i
].offset
% REG_SIZE
;
1836 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1840 invalidate_live_intervals();
1844 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1846 * During code generation, we create tons of temporary variables, many of
1847 * which get immediately killed and are never used again. Yet, in later
1848 * optimization and analysis passes, such as compute_live_intervals, we need
1849 * to loop over all the virtual GRFs. Compacting them can save a lot of
1853 fs_visitor::compact_virtual_grfs()
1855 bool progress
= false;
1856 int remap_table
[this->alloc
.count
];
1857 memset(remap_table
, -1, sizeof(remap_table
));
1859 /* Mark which virtual GRFs are used. */
1860 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1861 if (inst
->dst
.file
== VGRF
)
1862 remap_table
[inst
->dst
.nr
] = 0;
1864 for (int i
= 0; i
< inst
->sources
; i
++) {
1865 if (inst
->src
[i
].file
== VGRF
)
1866 remap_table
[inst
->src
[i
].nr
] = 0;
1870 /* Compact the GRF arrays. */
1872 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1873 if (remap_table
[i
] == -1) {
1874 /* We just found an unused register. This means that we are
1875 * actually going to compact something.
1879 remap_table
[i
] = new_index
;
1880 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1881 invalidate_live_intervals();
1886 this->alloc
.count
= new_index
;
1888 /* Patch all the instructions to use the newly renumbered registers */
1889 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1890 if (inst
->dst
.file
== VGRF
)
1891 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1893 for (int i
= 0; i
< inst
->sources
; i
++) {
1894 if (inst
->src
[i
].file
== VGRF
)
1895 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1899 /* Patch all the references to delta_xy, since they're used in register
1900 * allocation. If they're unused, switch them to BAD_FILE so we don't
1901 * think some random VGRF is delta_xy.
1903 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1904 if (delta_xy
[i
].file
== VGRF
) {
1905 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1906 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1908 delta_xy
[i
].file
= BAD_FILE
;
1917 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
, bool contiguous
,
1918 int *push_constant_loc
, int *pull_constant_loc
,
1919 unsigned *num_push_constants
,
1920 unsigned *num_pull_constants
,
1921 const unsigned max_push_components
,
1922 const unsigned max_chunk_size
,
1923 struct brw_stage_prog_data
*stage_prog_data
)
1925 /* This is the first live uniform in the chunk */
1926 if (*chunk_start
< 0)
1927 *chunk_start
= uniform
;
1929 /* If this element does not need to be contiguous with the next, we
1930 * split at this point and everything between chunk_start and u forms a
1934 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
1936 /* Decide whether we should push or pull this parameter. In the
1937 * Vulkan driver, push constants are explicitly exposed via the API
1938 * so we push everything. In GL, we only push small arrays.
1940 if (stage_prog_data
->pull_param
== NULL
||
1941 (*num_push_constants
+ chunk_size
<= max_push_components
&&
1942 chunk_size
<= max_chunk_size
)) {
1943 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
1944 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1945 push_constant_loc
[j
] = (*num_push_constants
)++;
1947 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1948 pull_constant_loc
[j
] = (*num_pull_constants
)++;
1956 * Assign UNIFORM file registers to either push constants or pull constants.
1958 * We allow a fragment shader to have more than the specified minimum
1959 * maximum number of fragment shader uniform components (64). If
1960 * there are too many of these, they'd fill up all of register space.
1961 * So, this will push some of them out to the pull constant buffer and
1962 * update the program to load them.
1965 fs_visitor::assign_constant_locations()
1967 /* Only the first compile gets to decide on locations. */
1968 if (dispatch_width
!= min_dispatch_width
)
1971 bool is_live
[uniforms
];
1972 memset(is_live
, 0, sizeof(is_live
));
1973 bool is_live_64bit
[uniforms
];
1974 memset(is_live_64bit
, 0, sizeof(is_live_64bit
));
1976 /* For each uniform slot, a value of true indicates that the given slot and
1977 * the next slot must remain contiguous. This is used to keep us from
1978 * splitting arrays apart.
1980 bool contiguous
[uniforms
];
1981 memset(contiguous
, 0, sizeof(contiguous
));
1983 int thread_local_id_index
=
1984 (stage
== MESA_SHADER_COMPUTE
) ?
1985 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
: -1;
1987 /* First, we walk through the instructions and do two things:
1989 * 1) Figure out which uniforms are live.
1991 * 2) Mark any indirectly used ranges of registers as contiguous.
1993 * Note that we don't move constant-indexed accesses to arrays. No
1994 * testing has been done of the performance impact of this choice.
1996 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1997 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1998 if (inst
->src
[i
].file
!= UNIFORM
)
2001 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
2003 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2004 assert(inst
->src
[2].ud
% 4 == 0);
2005 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
2006 assert(last
< uniforms
);
2008 for (unsigned j
= constant_nr
; j
< last
; j
++) {
2010 contiguous
[j
] = true;
2011 if (type_sz(inst
->src
[i
].type
) == 8) {
2012 is_live_64bit
[j
] = true;
2015 is_live
[last
] = true;
2017 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
2018 int regs_read
= inst
->components_read(i
) *
2019 type_sz(inst
->src
[i
].type
) / 4;
2020 for (int j
= 0; j
< regs_read
; j
++) {
2021 is_live
[constant_nr
+ j
] = true;
2022 if (type_sz(inst
->src
[i
].type
) == 8) {
2023 is_live_64bit
[constant_nr
+ j
] = true;
2031 if (thread_local_id_index
>= 0 && !is_live
[thread_local_id_index
])
2032 thread_local_id_index
= -1;
2034 /* Only allow 16 registers (128 uniform components) as push constants.
2036 * Just demote the end of the list. We could probably do better
2037 * here, demoting things that are rarely used in the program first.
2039 * If changing this value, note the limitation about total_regs in
2042 unsigned int max_push_components
= 16 * 8;
2043 if (thread_local_id_index
>= 0)
2044 max_push_components
--; /* Save a slot for the thread ID */
2046 /* We push small arrays, but no bigger than 16 floats. This is big enough
2047 * for a vec4 but hopefully not large enough to push out other stuff. We
2048 * should probably use a better heuristic at some point.
2050 const unsigned int max_chunk_size
= 16;
2052 unsigned int num_push_constants
= 0;
2053 unsigned int num_pull_constants
= 0;
2055 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2056 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2058 /* Default to -1 meaning no location */
2059 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2060 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2062 int chunk_start
= -1;
2064 /* First push 64-bit uniforms to ensure they are properly aligned */
2065 for (unsigned u
= 0; u
< uniforms
; u
++) {
2066 if (!is_live
[u
] || !is_live_64bit
[u
])
2069 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2070 push_constant_loc
, pull_constant_loc
,
2071 &num_push_constants
, &num_pull_constants
,
2072 max_push_components
, max_chunk_size
,
2077 /* Then push the rest of uniforms */
2078 for (unsigned u
= 0; u
< uniforms
; u
++) {
2079 if (!is_live
[u
] || is_live_64bit
[u
])
2082 /* Skip thread_local_id_index to put it in the last push register. */
2083 if (thread_local_id_index
== (int)u
)
2086 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2087 push_constant_loc
, pull_constant_loc
,
2088 &num_push_constants
, &num_pull_constants
,
2089 max_push_components
, max_chunk_size
,
2093 /* Add the CS local thread ID uniform at the end of the push constants */
2094 if (thread_local_id_index
>= 0)
2095 push_constant_loc
[thread_local_id_index
] = num_push_constants
++;
2097 /* As the uniforms are going to be reordered, take the data from a temporary
2098 * copy of the original param[].
2100 gl_constant_value
**param
= ralloc_array(NULL
, gl_constant_value
*,
2101 stage_prog_data
->nr_params
);
2102 memcpy(param
, stage_prog_data
->param
,
2103 sizeof(gl_constant_value
*) * stage_prog_data
->nr_params
);
2104 stage_prog_data
->nr_params
= num_push_constants
;
2105 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2107 /* Up until now, the param[] array has been indexed by reg + reg_offset
2108 * of UNIFORM registers. Move pull constants into pull_param[] and
2109 * condense param[] to only contain the uniforms we chose to push.
2111 * NOTE: Because we are condensing the params[] array, we know that
2112 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2113 * having to make a copy.
2115 int new_thread_local_id_index
= -1;
2116 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2117 const gl_constant_value
*value
= param
[i
];
2119 if (pull_constant_loc
[i
] != -1) {
2120 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2121 } else if (push_constant_loc
[i
] != -1) {
2122 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2123 if (thread_local_id_index
== (int)i
)
2124 new_thread_local_id_index
= push_constant_loc
[i
];
2129 if (stage
== MESA_SHADER_COMPUTE
)
2130 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
=
2131 new_thread_local_id_index
;
2135 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2136 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2139 fs_visitor::lower_constant_loads()
2141 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2143 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2144 /* Set up the annotation tracking for new generated instructions. */
2145 const fs_builder
ibld(this, block
, inst
);
2147 for (int i
= 0; i
< inst
->sources
; i
++) {
2148 if (inst
->src
[i
].file
!= UNIFORM
)
2151 /* We'll handle this case later */
2152 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2155 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
2156 if (location
>= uniforms
)
2157 continue; /* Out of bounds access */
2159 int pull_index
= pull_constant_loc
[location
];
2161 if (pull_index
== -1)
2164 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2167 if (type_sz(inst
->src
[i
].type
) <= 4)
2168 dst
= vgrf(glsl_type::float_type
);
2170 dst
= vgrf(glsl_type::double_type
);
2172 assert(inst
->src
[i
].stride
== 0);
2174 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2175 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2176 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2177 dst
, brw_imm_ud(index
), offset
);
2179 /* Rewrite the instruction to use the temporary VGRF. */
2180 inst
->src
[i
].file
= VGRF
;
2181 inst
->src
[i
].nr
= dst
.nr
;
2182 inst
->src
[i
].offset
%= 4;
2183 inst
->src
[i
].set_smear((pull_index
& 3) * 4 /
2184 type_sz(inst
->src
[i
].type
));
2186 brw_mark_surface_used(prog_data
, index
);
2189 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2190 inst
->src
[0].file
== UNIFORM
) {
2192 unsigned location
= inst
->src
[0].nr
+ inst
->src
[0].offset
/ 4;
2193 if (location
>= uniforms
)
2194 continue; /* Out of bounds access */
2196 int pull_index
= pull_constant_loc
[location
];
2198 if (pull_index
== -1)
2201 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2205 inst
->remove(block
);
2207 brw_mark_surface_used(prog_data
, index
);
2210 invalidate_live_intervals();
2214 fs_visitor::opt_algebraic()
2216 bool progress
= false;
2218 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2219 switch (inst
->opcode
) {
2220 case BRW_OPCODE_MOV
:
2221 if (inst
->src
[0].file
!= IMM
)
2224 if (inst
->saturate
) {
2225 if (inst
->dst
.type
!= inst
->src
[0].type
)
2226 assert(!"unimplemented: saturate mixed types");
2228 if (brw_saturate_immediate(inst
->dst
.type
,
2229 &inst
->src
[0].as_brw_reg())) {
2230 inst
->saturate
= false;
2236 case BRW_OPCODE_MUL
:
2237 if (inst
->src
[1].file
!= IMM
)
2241 if (inst
->src
[1].is_one()) {
2242 inst
->opcode
= BRW_OPCODE_MOV
;
2243 inst
->src
[1] = reg_undef
;
2249 if (inst
->src
[1].is_negative_one()) {
2250 inst
->opcode
= BRW_OPCODE_MOV
;
2251 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2252 inst
->src
[1] = reg_undef
;
2258 if (inst
->src
[1].is_zero()) {
2259 inst
->opcode
= BRW_OPCODE_MOV
;
2260 inst
->src
[0] = inst
->src
[1];
2261 inst
->src
[1] = reg_undef
;
2266 if (inst
->src
[0].file
== IMM
) {
2267 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2268 inst
->opcode
= BRW_OPCODE_MOV
;
2269 inst
->src
[0].f
*= inst
->src
[1].f
;
2270 inst
->src
[1] = reg_undef
;
2275 case BRW_OPCODE_ADD
:
2276 if (inst
->src
[1].file
!= IMM
)
2280 if (inst
->src
[1].is_zero()) {
2281 inst
->opcode
= BRW_OPCODE_MOV
;
2282 inst
->src
[1] = reg_undef
;
2287 if (inst
->src
[0].file
== IMM
) {
2288 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2289 inst
->opcode
= BRW_OPCODE_MOV
;
2290 inst
->src
[0].f
+= inst
->src
[1].f
;
2291 inst
->src
[1] = reg_undef
;
2297 if (inst
->src
[0].equals(inst
->src
[1])) {
2298 inst
->opcode
= BRW_OPCODE_MOV
;
2299 inst
->src
[1] = reg_undef
;
2304 case BRW_OPCODE_LRP
:
2305 if (inst
->src
[1].equals(inst
->src
[2])) {
2306 inst
->opcode
= BRW_OPCODE_MOV
;
2307 inst
->src
[0] = inst
->src
[1];
2308 inst
->src
[1] = reg_undef
;
2309 inst
->src
[2] = reg_undef
;
2314 case BRW_OPCODE_CMP
:
2315 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2317 inst
->src
[0].negate
&&
2318 inst
->src
[1].is_zero()) {
2319 inst
->src
[0].abs
= false;
2320 inst
->src
[0].negate
= false;
2321 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2326 case BRW_OPCODE_SEL
:
2327 if (inst
->src
[0].equals(inst
->src
[1])) {
2328 inst
->opcode
= BRW_OPCODE_MOV
;
2329 inst
->src
[1] = reg_undef
;
2330 inst
->predicate
= BRW_PREDICATE_NONE
;
2331 inst
->predicate_inverse
= false;
2333 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2334 switch (inst
->conditional_mod
) {
2335 case BRW_CONDITIONAL_LE
:
2336 case BRW_CONDITIONAL_L
:
2337 switch (inst
->src
[1].type
) {
2338 case BRW_REGISTER_TYPE_F
:
2339 if (inst
->src
[1].f
>= 1.0f
) {
2340 inst
->opcode
= BRW_OPCODE_MOV
;
2341 inst
->src
[1] = reg_undef
;
2342 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2350 case BRW_CONDITIONAL_GE
:
2351 case BRW_CONDITIONAL_G
:
2352 switch (inst
->src
[1].type
) {
2353 case BRW_REGISTER_TYPE_F
:
2354 if (inst
->src
[1].f
<= 0.0f
) {
2355 inst
->opcode
= BRW_OPCODE_MOV
;
2356 inst
->src
[1] = reg_undef
;
2357 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2369 case BRW_OPCODE_MAD
:
2370 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2371 inst
->opcode
= BRW_OPCODE_MOV
;
2372 inst
->src
[1] = reg_undef
;
2373 inst
->src
[2] = reg_undef
;
2375 } else if (inst
->src
[0].is_zero()) {
2376 inst
->opcode
= BRW_OPCODE_MUL
;
2377 inst
->src
[0] = inst
->src
[2];
2378 inst
->src
[2] = reg_undef
;
2380 } else if (inst
->src
[1].is_one()) {
2381 inst
->opcode
= BRW_OPCODE_ADD
;
2382 inst
->src
[1] = inst
->src
[2];
2383 inst
->src
[2] = reg_undef
;
2385 } else if (inst
->src
[2].is_one()) {
2386 inst
->opcode
= BRW_OPCODE_ADD
;
2387 inst
->src
[2] = reg_undef
;
2389 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2390 inst
->opcode
= BRW_OPCODE_ADD
;
2391 inst
->src
[1].f
*= inst
->src
[2].f
;
2392 inst
->src
[2] = reg_undef
;
2396 case SHADER_OPCODE_BROADCAST
:
2397 if (is_uniform(inst
->src
[0])) {
2398 inst
->opcode
= BRW_OPCODE_MOV
;
2400 inst
->force_writemask_all
= true;
2402 } else if (inst
->src
[1].file
== IMM
) {
2403 inst
->opcode
= BRW_OPCODE_MOV
;
2404 inst
->src
[0] = component(inst
->src
[0],
2407 inst
->force_writemask_all
= true;
2416 /* Swap if src[0] is immediate. */
2417 if (progress
&& inst
->is_commutative()) {
2418 if (inst
->src
[0].file
== IMM
) {
2419 fs_reg tmp
= inst
->src
[1];
2420 inst
->src
[1] = inst
->src
[0];
2429 * Optimize sample messages that have constant zero values for the trailing
2430 * texture coordinates. We can just reduce the message length for these
2431 * instructions instead of reserving a register for it. Trailing parameters
2432 * that aren't sent default to zero anyway. This will cause the dead code
2433 * eliminator to remove the MOV instruction that would otherwise be emitted to
2434 * set up the zero value.
2437 fs_visitor::opt_zero_samples()
2439 /* Gen4 infers the texturing opcode based on the message length so we can't
2442 if (devinfo
->gen
< 5)
2445 bool progress
= false;
2447 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2448 if (!inst
->is_tex())
2451 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2453 if (load_payload
->is_head_sentinel() ||
2454 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2457 /* We don't want to remove the message header or the first parameter.
2458 * Removing the first parameter is not allowed, see the Haswell PRM
2459 * volume 7, page 149:
2461 * "Parameter 0 is required except for the sampleinfo message, which
2462 * has no parameter 0"
2464 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2465 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2466 (inst
->exec_size
/ 8) +
2467 inst
->header_size
- 1].is_zero()) {
2468 inst
->mlen
-= inst
->exec_size
/ 8;
2474 invalidate_live_intervals();
2480 * Optimize sample messages which are followed by the final RT write.
2482 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2483 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2484 * final texturing results copied to the framebuffer write payload and modify
2485 * them to write to the framebuffer directly.
2488 fs_visitor::opt_sampler_eot()
2490 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2492 if (stage
!= MESA_SHADER_FRAGMENT
)
2495 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2498 /* FINISHME: It should be possible to implement this optimization when there
2499 * are multiple drawbuffers.
2501 if (key
->nr_color_regions
!= 1)
2504 /* Requires emitting a bunch of saturating MOV instructions during logical
2505 * send lowering to clamp the color payload, which the sampler unit isn't
2506 * going to do for us.
2508 if (key
->clamp_fragment_color
)
2511 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2512 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2513 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2514 assert(fb_write
->eot
);
2515 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2517 /* There wasn't one; nothing to do. */
2518 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2521 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2523 /* 3D Sampler » Messages » Message Format
2525 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2526 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2528 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2529 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2530 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2531 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2532 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2533 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2534 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2535 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2538 /* XXX - This shouldn't be necessary. */
2539 if (tex_inst
->prev
->is_head_sentinel())
2542 /* Check that the FB write sources are fully initialized by the single
2543 * texturing instruction.
2545 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2546 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2547 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2548 fb_write
->size_read(i
) != tex_inst
->size_written
)
2550 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2551 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2556 assert(!tex_inst
->eot
); /* We can't get here twice */
2557 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2559 const fs_builder
ibld(this, block
, tex_inst
);
2561 tex_inst
->offset
|= fb_write
->target
<< 24;
2562 tex_inst
->eot
= true;
2563 tex_inst
->dst
= ibld
.null_reg_ud();
2564 tex_inst
->size_written
= 0;
2565 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2567 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2568 * flag and submit a header together with the sampler message as required
2571 invalidate_live_intervals();
2576 fs_visitor::opt_register_renaming()
2578 bool progress
= false;
2581 int remap
[alloc
.count
];
2582 memset(remap
, -1, sizeof(int) * alloc
.count
);
2584 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2585 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2587 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2588 inst
->opcode
== BRW_OPCODE_WHILE
) {
2592 /* Rewrite instruction sources. */
2593 for (int i
= 0; i
< inst
->sources
; i
++) {
2594 if (inst
->src
[i
].file
== VGRF
&&
2595 remap
[inst
->src
[i
].nr
] != -1 &&
2596 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2597 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2602 const int dst
= inst
->dst
.nr
;
2605 inst
->dst
.file
== VGRF
&&
2606 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
2607 !inst
->is_partial_write()) {
2608 if (remap
[dst
] == -1) {
2611 remap
[dst
] = alloc
.allocate(regs_written(inst
));
2612 inst
->dst
.nr
= remap
[dst
];
2615 } else if (inst
->dst
.file
== VGRF
&&
2617 remap
[dst
] != dst
) {
2618 inst
->dst
.nr
= remap
[dst
];
2624 invalidate_live_intervals();
2626 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2627 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2628 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2637 * Remove redundant or useless discard jumps.
2639 * For example, we can eliminate jumps in the following sequence:
2641 * discard-jump (redundant with the next jump)
2642 * discard-jump (useless; jumps to the next instruction)
2646 fs_visitor::opt_redundant_discard_jumps()
2648 bool progress
= false;
2650 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2652 fs_inst
*placeholder_halt
= NULL
;
2653 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2654 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2655 placeholder_halt
= inst
;
2660 if (!placeholder_halt
)
2663 /* Delete any HALTs immediately before the placeholder halt. */
2664 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2665 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2666 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2667 prev
->remove(last_bblock
);
2672 invalidate_live_intervals();
2678 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2679 * from \p r which overlaps the region starting at \p r and spanning \p n GRF
2682 static inline unsigned
2683 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned n
)
2685 const int rel_offset
= (reg_offset(s
) - reg_offset(r
)) / REG_SIZE
;
2686 assert(reg_space(r
) == reg_space(s
) &&
2687 rel_offset
>= 0 && rel_offset
< int(8 * sizeof(unsigned)));
2688 return ((1 << n
) - 1) << rel_offset
;
2692 fs_visitor::compute_to_mrf()
2694 bool progress
= false;
2697 /* No MRFs on Gen >= 7. */
2698 if (devinfo
->gen
>= 7)
2701 calculate_live_intervals();
2703 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2707 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2708 inst
->is_partial_write() ||
2709 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2710 inst
->dst
.type
!= inst
->src
[0].type
||
2711 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2712 !inst
->src
[0].is_contiguous() ||
2713 inst
->src
[0].offset
% REG_SIZE
!= 0)
2716 /* Can't compute-to-MRF this GRF if someone else was going to
2719 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2722 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2723 * things that computed the value of all GRFs of the source region. The
2724 * regs_left bitset keeps track of the registers we haven't yet found a
2725 * generating instruction for.
2727 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
2729 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2730 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2731 inst
->src
[0], inst
->size_read(0))) {
2732 /* Found the last thing to write our reg we want to turn
2733 * into a compute-to-MRF.
2736 /* If this one instruction didn't populate all the
2737 * channels, bail. We might be able to rewrite everything
2738 * that writes that reg, but it would require smarter
2741 if (scan_inst
->is_partial_write())
2744 /* Handling things not fully contained in the source of the copy
2745 * would need us to understand coalescing out more than one MOV at
2748 if (scan_inst
->dst
.offset
/ REG_SIZE
< inst
->src
[0].offset
/ REG_SIZE
||
2749 scan_inst
->dst
.offset
/ REG_SIZE
+ DIV_ROUND_UP(scan_inst
->size_written
, REG_SIZE
) >
2750 inst
->src
[0].offset
/ REG_SIZE
+ DIV_ROUND_UP(inst
->size_read(0), REG_SIZE
))
2753 /* SEND instructions can't have MRF as a destination. */
2754 if (scan_inst
->mlen
)
2757 if (devinfo
->gen
== 6) {
2758 /* gen6 math instructions must have the destination be
2759 * GRF, so no compute-to-MRF for them.
2761 if (scan_inst
->is_math()) {
2766 /* Clear the bits for any registers this instruction overwrites. */
2767 regs_left
&= ~mask_relative_to(
2768 inst
->src
[0], scan_inst
->dst
, DIV_ROUND_UP(scan_inst
->size_written
,
2774 /* We don't handle control flow here. Most computation of
2775 * values that end up in MRFs are shortly before the MRF
2778 if (block
->start() == scan_inst
)
2781 /* You can't read from an MRF, so if someone else reads our
2782 * MRF's source GRF that we wanted to rewrite, that stops us.
2784 bool interfered
= false;
2785 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2786 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
2787 inst
->src
[0], inst
->size_read(0))) {
2794 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2795 inst
->dst
, inst
->size_written
)) {
2796 /* If somebody else writes our MRF here, we can't
2797 * compute-to-MRF before that.
2802 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2803 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2804 inst
->dst
, inst
->size_written
)) {
2805 /* Found a SEND instruction, which means that there are
2806 * live values in MRFs from base_mrf to base_mrf +
2807 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2817 /* Found all generating instructions of our MRF's source value, so it
2818 * should be safe to rewrite them to point to the MRF directly.
2820 regs_left
= (1 << regs_read(inst
, 0)) - 1;
2822 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2823 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2824 inst
->src
[0], inst
->size_read(0))) {
2825 /* Clear the bits for any registers this instruction overwrites. */
2826 regs_left
&= ~mask_relative_to(
2827 inst
->src
[0], scan_inst
->dst
, DIV_ROUND_UP(scan_inst
->size_written
,
2830 const unsigned rel_offset
= (reg_offset(scan_inst
->dst
) -
2831 reg_offset(inst
->src
[0])) / REG_SIZE
;
2833 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2834 /* Apply the same address transformation done by the hardware
2835 * for COMPR4 MRF writes.
2837 assert(rel_offset
< 2);
2838 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
* 4;
2840 /* Clear the COMPR4 bit if the generating instruction is not
2843 if (scan_inst
->size_written
< 2 * REG_SIZE
)
2844 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2847 /* Calculate the MRF number the result of this instruction is
2848 * ultimately written to.
2850 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
;
2853 scan_inst
->dst
.file
= MRF
;
2854 scan_inst
->dst
.offset
%= REG_SIZE
;
2855 scan_inst
->saturate
|= inst
->saturate
;
2862 inst
->remove(block
);
2867 invalidate_live_intervals();
2873 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2874 * flow. We could probably do better here with some form of divergence
2878 fs_visitor::eliminate_find_live_channel()
2880 bool progress
= false;
2883 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2884 switch (inst
->opcode
) {
2890 case BRW_OPCODE_ENDIF
:
2891 case BRW_OPCODE_WHILE
:
2895 case FS_OPCODE_DISCARD_JUMP
:
2896 /* This can potentially make control flow non-uniform until the end
2901 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2903 inst
->opcode
= BRW_OPCODE_MOV
;
2904 inst
->src
[0] = brw_imm_ud(0u);
2906 inst
->force_writemask_all
= true;
2920 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2921 * instructions to FS_OPCODE_REP_FB_WRITE.
2924 fs_visitor::emit_repclear_shader()
2926 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2928 int color_mrf
= base_mrf
+ 2;
2932 mov
= bld
.exec_all().group(4, 0)
2933 .MOV(brw_message_reg(color_mrf
),
2934 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2936 struct brw_reg reg
=
2937 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2938 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
2939 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2941 mov
= bld
.exec_all().group(4, 0)
2942 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2946 if (key
->nr_color_regions
== 1) {
2947 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2948 write
->saturate
= key
->clamp_fragment_color
;
2949 write
->base_mrf
= color_mrf
;
2951 write
->header_size
= 0;
2954 assume(key
->nr_color_regions
> 0);
2955 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2956 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2957 write
->saturate
= key
->clamp_fragment_color
;
2958 write
->base_mrf
= base_mrf
;
2960 write
->header_size
= 2;
2968 assign_constant_locations();
2969 assign_curb_setup();
2971 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2973 assert(mov
->src
[0].file
== FIXED_GRF
);
2974 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2979 * Walks through basic blocks, looking for repeated MRF writes and
2980 * removing the later ones.
2983 fs_visitor::remove_duplicate_mrf_writes()
2985 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2986 bool progress
= false;
2988 /* Need to update the MRF tracking for compressed instructions. */
2989 if (dispatch_width
>= 16)
2992 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2994 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2995 if (inst
->is_control_flow()) {
2996 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2999 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3000 inst
->dst
.file
== MRF
) {
3001 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3002 if (prev_inst
&& inst
->equals(prev_inst
)) {
3003 inst
->remove(block
);
3009 /* Clear out the last-write records for MRFs that were overwritten. */
3010 if (inst
->dst
.file
== MRF
) {
3011 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3014 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3015 /* Found a SEND instruction, which will include two or fewer
3016 * implied MRF writes. We could do better here.
3018 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3019 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3023 /* Clear out any MRF move records whose sources got overwritten. */
3024 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3025 if (last_mrf_move
[i
] &&
3026 regions_overlap(inst
->dst
, inst
->size_written
,
3027 last_mrf_move
[i
]->src
[0],
3028 last_mrf_move
[i
]->size_read(0))) {
3029 last_mrf_move
[i
] = NULL
;
3033 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3034 inst
->dst
.file
== MRF
&&
3035 inst
->src
[0].file
!= ARF
&&
3036 !inst
->is_partial_write()) {
3037 last_mrf_move
[inst
->dst
.nr
] = inst
;
3042 invalidate_live_intervals();
3048 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3050 /* Clear the flag for registers that actually got read (as expected). */
3051 for (int i
= 0; i
< inst
->sources
; i
++) {
3053 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3054 grf
= inst
->src
[i
].nr
;
3059 if (grf
>= first_grf
&&
3060 grf
< first_grf
+ grf_len
) {
3061 deps
[grf
- first_grf
] = false;
3062 if (inst
->exec_size
== 16)
3063 deps
[grf
- first_grf
+ 1] = false;
3069 * Implements this workaround for the original 965:
3071 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3072 * check for post destination dependencies on this instruction, software
3073 * must ensure that there is no destination hazard for the case of ‘write
3074 * followed by a posted write’ shown in the following example.
3077 * 2. send r3.xy <rest of send instruction>
3080 * Due to no post-destination dependency check on the ‘send’, the above
3081 * code sequence could have two instructions (1 and 2) in flight at the
3082 * same time that both consider ‘r3’ as the target of their final writes.
3085 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3088 int write_len
= regs_written(inst
);
3089 int first_write_grf
= inst
->dst
.nr
;
3090 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3091 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3093 memset(needs_dep
, false, sizeof(needs_dep
));
3094 memset(needs_dep
, true, write_len
);
3096 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3098 /* Walk backwards looking for writes to registers we're writing which
3099 * aren't read since being written. If we hit the start of the program,
3100 * we assume that there are no outstanding dependencies on entry to the
3103 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3104 /* If we hit control flow, assume that there *are* outstanding
3105 * dependencies, and force their cleanup before our instruction.
3107 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3108 for (int i
= 0; i
< write_len
; i
++) {
3110 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3111 first_write_grf
+ i
);
3116 /* We insert our reads as late as possible on the assumption that any
3117 * instruction but a MOV that might have left us an outstanding
3118 * dependency has more latency than a MOV.
3120 if (scan_inst
->dst
.file
== VGRF
) {
3121 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3122 int reg
= scan_inst
->dst
.nr
+ i
;
3124 if (reg
>= first_write_grf
&&
3125 reg
< first_write_grf
+ write_len
&&
3126 needs_dep
[reg
- first_write_grf
]) {
3127 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3128 needs_dep
[reg
- first_write_grf
] = false;
3129 if (scan_inst
->exec_size
== 16)
3130 needs_dep
[reg
- first_write_grf
+ 1] = false;
3135 /* Clear the flag for registers that actually got read (as expected). */
3136 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3138 /* Continue the loop only if we haven't resolved all the dependencies */
3140 for (i
= 0; i
< write_len
; i
++) {
3150 * Implements this workaround for the original 965:
3152 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3153 * used as a destination register until after it has been sourced by an
3154 * instruction with a different destination register.
3157 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3159 int write_len
= regs_written(inst
);
3160 int first_write_grf
= inst
->dst
.nr
;
3161 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3162 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3164 memset(needs_dep
, false, sizeof(needs_dep
));
3165 memset(needs_dep
, true, write_len
);
3166 /* Walk forwards looking for writes to registers we're writing which aren't
3167 * read before being written.
3169 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3170 /* If we hit control flow, force resolve all remaining dependencies. */
3171 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3172 for (int i
= 0; i
< write_len
; i
++) {
3174 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3175 first_write_grf
+ i
);
3180 /* Clear the flag for registers that actually got read (as expected). */
3181 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3183 /* We insert our reads as late as possible since they're reading the
3184 * result of a SEND, which has massive latency.
3186 if (scan_inst
->dst
.file
== VGRF
&&
3187 scan_inst
->dst
.nr
>= first_write_grf
&&
3188 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3189 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3190 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3192 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3195 /* Continue the loop only if we haven't resolved all the dependencies */
3197 for (i
= 0; i
< write_len
; i
++) {
3207 fs_visitor::insert_gen4_send_dependency_workarounds()
3209 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3212 bool progress
= false;
3214 /* Note that we're done with register allocation, so GRF fs_regs always
3215 * have a .reg_offset of 0.
3218 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3219 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3220 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3221 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3227 invalidate_live_intervals();
3231 * Turns the generic expression-style uniform pull constant load instruction
3232 * into a hardware-specific series of instructions for loading a pull
3235 * The expression style allows the CSE pass before this to optimize out
3236 * repeated loads from the same offset, and gives the pre-register-allocation
3237 * scheduling full flexibility, while the conversion to native instructions
3238 * allows the post-register-allocation scheduler the best information
3241 * Note that execution masking for setting up pull constant loads is special:
3242 * the channels that need to be written are unrelated to the current execution
3243 * mask, since a later instruction will use one of the result channels as a
3244 * source operand for all 8 or 16 of its channels.
3247 fs_visitor::lower_uniform_pull_constant_loads()
3249 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3250 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3253 if (devinfo
->gen
>= 7) {
3254 /* The offset arg is a vec4-aligned immediate byte offset. */
3255 fs_reg const_offset_reg
= inst
->src
[1];
3256 assert(const_offset_reg
.file
== IMM
&&
3257 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3258 assert(const_offset_reg
.ud
% 16 == 0);
3260 fs_reg payload
, offset
;
3261 if (devinfo
->gen
>= 9) {
3262 /* We have to use a message header on Skylake to get SIMD4x2
3263 * mode. Reserve space for the register.
3265 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3266 offset
.offset
+= REG_SIZE
;
3269 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3273 /* This is actually going to be a MOV, but since only the first dword
3274 * is accessed, we have a special opcode to do just that one. Note
3275 * that this needs to be an operation that will be considered a def
3276 * by live variable analysis, or register allocation will explode.
3278 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3279 8, offset
, const_offset_reg
);
3280 setup
->force_writemask_all
= true;
3282 setup
->ir
= inst
->ir
;
3283 setup
->annotation
= inst
->annotation
;
3284 inst
->insert_before(block
, setup
);
3286 /* Similarly, this will only populate the first 4 channels of the
3287 * result register (since we only use smear values from 0-3), but we
3288 * don't tell the optimizer.
3290 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3291 inst
->src
[1] = payload
;
3293 invalidate_live_intervals();
3295 /* Before register allocation, we didn't tell the scheduler about the
3296 * MRF we use. We know it's safe to use this MRF because nothing
3297 * else does except for register spill/unspill, which generates and
3298 * uses its MRF within a single IR instruction.
3300 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3307 fs_visitor::lower_load_payload()
3309 bool progress
= false;
3311 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3312 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3315 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3316 assert(inst
->saturate
== false);
3317 fs_reg dst
= inst
->dst
;
3319 /* Get rid of COMPR4. We'll add it back in if we need it */
3320 if (dst
.file
== MRF
)
3321 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3323 const fs_builder
ibld(this, block
, inst
);
3324 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3326 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3327 if (inst
->src
[i
].file
!= BAD_FILE
) {
3328 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3329 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3330 hbld
.MOV(mov_dst
, mov_src
);
3332 dst
= offset(dst
, hbld
, 1);
3335 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3336 inst
->exec_size
> 8) {
3337 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3338 * a straightforward copy. Instead, the result of the
3339 * LOAD_PAYLOAD is treated as interleaved and the first four
3340 * non-header sources are unpacked as:
3351 * This is used for gen <= 5 fb writes.
3353 assert(inst
->exec_size
== 16);
3354 assert(inst
->header_size
+ 4 <= inst
->sources
);
3355 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3356 if (inst
->src
[i
].file
!= BAD_FILE
) {
3357 if (devinfo
->has_compr4
) {
3358 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3359 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3360 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3362 /* Platform doesn't have COMPR4. We have to fake it */
3363 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3364 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3366 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3373 /* The loop above only ever incremented us through the first set
3374 * of 4 registers. However, thanks to the magic of COMPR4, we
3375 * actually wrote to the first 8 registers, so we need to take
3376 * that into account now.
3380 /* The COMPR4 code took care of the first 4 sources. We'll let
3381 * the regular path handle any remaining sources. Yes, we are
3382 * modifying the instruction but we're about to delete it so
3383 * this really doesn't hurt anything.
3385 inst
->header_size
+= 4;
3388 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3389 if (inst
->src
[i
].file
!= BAD_FILE
)
3390 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3391 dst
= offset(dst
, ibld
, 1);
3394 inst
->remove(block
);
3399 invalidate_live_intervals();
3405 fs_visitor::lower_integer_multiplication()
3407 bool progress
= false;
3409 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3410 const fs_builder
ibld(this, block
, inst
);
3412 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3413 if (inst
->dst
.is_accumulator() ||
3414 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3415 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3418 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3419 * operation directly, but CHV/BXT cannot.
3421 if (devinfo
->gen
>= 8 &&
3422 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3425 if (inst
->src
[1].file
== IMM
&&
3426 inst
->src
[1].ud
< (1 << 16)) {
3427 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3428 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3431 * If multiplying by an immediate value that fits in 16-bits, do a
3432 * single MUL instruction with that value in the proper location.
3434 if (devinfo
->gen
< 7) {
3435 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3437 ibld
.MOV(imm
, inst
->src
[1]);
3438 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3440 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3441 ibld
.MUL(inst
->dst
, inst
->src
[0],
3442 ud
? brw_imm_uw(inst
->src
[1].ud
)
3443 : brw_imm_w(inst
->src
[1].d
));
3446 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3447 * do 32-bit integer multiplication in one instruction, but instead
3448 * must do a sequence (which actually calculates a 64-bit result):
3450 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3451 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3452 * mov(8) g2<1>D acc0<8,8,1>D
3454 * But on Gen > 6, the ability to use second accumulator register
3455 * (acc1) for non-float data types was removed, preventing a simple
3456 * implementation in SIMD16. A 16-channel result can be calculated by
3457 * executing the three instructions twice in SIMD8, once with quarter
3458 * control of 1Q for the first eight channels and again with 2Q for
3459 * the second eight channels.
3461 * Which accumulator register is implicitly accessed (by AccWrEnable
3462 * for instance) is determined by the quarter control. Unfortunately
3463 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3464 * implicit accumulator access by an instruction with 2Q will access
3465 * acc1 regardless of whether the data type is usable in acc1.
3467 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3468 * integer data types.
3470 * Since we only want the low 32-bits of the result, we can do two
3471 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3472 * adjust the high result and add them (like the mach is doing):
3474 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3475 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3476 * shl(8) g9<1>D g8<8,8,1>D 16D
3477 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3479 * We avoid the shl instruction by realizing that we only want to add
3480 * the low 16-bits of the "high" result to the high 16-bits of the
3481 * "low" result and using proper regioning on the add:
3483 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3484 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3485 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3487 * Since it does not use the (single) accumulator register, we can
3488 * schedule multi-component multiplications much better.
3491 fs_reg orig_dst
= inst
->dst
;
3492 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3493 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3496 fs_reg low
= inst
->dst
;
3497 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3500 if (devinfo
->gen
>= 7) {
3501 fs_reg src1_0_w
= inst
->src
[1];
3502 fs_reg src1_1_w
= inst
->src
[1];
3504 if (inst
->src
[1].file
== IMM
) {
3505 src1_0_w
.ud
&= 0xffff;
3508 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3509 if (src1_0_w
.stride
!= 0) {
3510 assert(src1_0_w
.stride
== 1);
3511 src1_0_w
.stride
= 2;
3514 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3515 if (src1_1_w
.stride
!= 0) {
3516 assert(src1_1_w
.stride
== 1);
3517 src1_1_w
.stride
= 2;
3519 src1_1_w
.offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3521 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3522 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3524 fs_reg src0_0_w
= inst
->src
[0];
3525 fs_reg src0_1_w
= inst
->src
[0];
3527 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3528 if (src0_0_w
.stride
!= 0) {
3529 assert(src0_0_w
.stride
== 1);
3530 src0_0_w
.stride
= 2;
3533 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3534 if (src0_1_w
.stride
!= 0) {
3535 assert(src0_1_w
.stride
== 1);
3536 src0_1_w
.stride
= 2;
3538 src0_1_w
.offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3540 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3541 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3544 fs_reg dst
= inst
->dst
;
3545 dst
.type
= BRW_REGISTER_TYPE_UW
;
3546 dst
.offset
= ROUND_DOWN_TO(dst
.offset
, REG_SIZE
) + 2;
3549 high
.type
= BRW_REGISTER_TYPE_UW
;
3552 low
.type
= BRW_REGISTER_TYPE_UW
;
3553 low
.offset
= ROUND_DOWN_TO(low
.offset
, REG_SIZE
) + 2;
3556 ibld
.ADD(dst
, low
, high
);
3558 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3559 set_condmod(inst
->conditional_mod
,
3560 ibld
.MOV(orig_dst
, inst
->dst
));
3564 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3565 /* Should have been lowered to 8-wide. */
3566 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3567 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3569 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3570 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3572 if (devinfo
->gen
>= 8) {
3573 /* Until Gen8, integer multiplies read 32-bits from one source,
3574 * and 16-bits from the other, and relying on the MACH instruction
3575 * to generate the high bits of the result.
3577 * On Gen8, the multiply instruction does a full 32x32-bit
3578 * multiply, but in order to do a 64-bit multiply we can simulate
3579 * the previous behavior and then use a MACH instruction.
3581 * FINISHME: Don't use source modifiers on src1.
3583 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3584 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3585 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3586 mul
->src
[1].stride
*= 2;
3588 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3590 /* Among other things the quarter control bits influence which
3591 * accumulator register is used by the hardware for instructions
3592 * that access the accumulator implicitly (e.g. MACH). A
3593 * second-half instruction would normally map to acc1, which
3594 * doesn't exist on Gen7 and up (the hardware does emulate it for
3595 * floating-point instructions *only* by taking advantage of the
3596 * extra precision of acc0 not normally used for floating point
3599 * HSW and up are careful enough not to try to access an
3600 * accumulator register that doesn't exist, but on earlier Gen7
3601 * hardware we need to make sure that the quarter control bits are
3602 * zero to avoid non-deterministic behaviour and emit an extra MOV
3603 * to get the result masked correctly according to the current
3607 mach
->force_writemask_all
= true;
3608 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3609 ibld
.MOV(inst
->dst
, mach
->dst
);
3615 inst
->remove(block
);
3620 invalidate_live_intervals();
3626 fs_visitor::lower_minmax()
3628 assert(devinfo
->gen
< 6);
3630 bool progress
= false;
3632 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3633 const fs_builder
ibld(this, block
, inst
);
3635 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3636 inst
->predicate
== BRW_PREDICATE_NONE
) {
3637 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3638 * the original SEL.L/GE instruction
3640 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3641 inst
->conditional_mod
);
3642 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3643 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3650 invalidate_live_intervals();
3656 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3657 fs_reg
*dst
, fs_reg color
, unsigned components
)
3659 if (key
->clamp_fragment_color
) {
3660 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3661 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3663 for (unsigned i
= 0; i
< components
; i
++)
3665 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3670 for (unsigned i
= 0; i
< components
; i
++)
3671 dst
[i
] = offset(color
, bld
, i
);
3675 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3676 const brw_wm_prog_data
*prog_data
,
3677 const brw_wm_prog_key
*key
,
3678 const fs_visitor::thread_payload
&payload
)
3680 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3681 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3682 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3683 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3684 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3685 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3686 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3687 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3688 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3689 const unsigned components
=
3690 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3692 /* We can potentially have a message length of up to 15, so we have to set
3693 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3696 int header_size
= 2, payload_header_size
;
3697 unsigned length
= 0;
3699 /* From the Sandy Bridge PRM, volume 4, page 198:
3701 * "Dispatched Pixel Enables. One bit per pixel indicating
3702 * which pixels were originally enabled when the thread was
3703 * dispatched. This field is only required for the end-of-
3704 * thread message and on all dual-source messages."
3706 if (devinfo
->gen
>= 6 &&
3707 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3708 color1
.file
== BAD_FILE
&&
3709 key
->nr_color_regions
== 1) {
3713 if (header_size
!= 0) {
3714 assert(header_size
== 2);
3715 /* Allocate 2 registers for a header */
3719 if (payload
.aa_dest_stencil_reg
) {
3720 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3721 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3722 .MOV(sources
[length
],
3723 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3727 if (sample_mask
.file
!= BAD_FILE
) {
3728 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3729 BRW_REGISTER_TYPE_UD
);
3731 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3732 * relevant. Since it's unsigned single words one vgrf is always
3733 * 16-wide, but only the lower or higher 8 channels will be used by the
3734 * hardware when doing a SIMD8 write depending on whether we have
3735 * selected the subspans for the first or second half respectively.
3737 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3738 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3739 sample_mask
.stride
*= 2;
3741 bld
.exec_all().annotate("FB write oMask")
3742 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3748 payload_header_size
= length
;
3750 if (src0_alpha
.file
!= BAD_FILE
) {
3751 /* FIXME: This is being passed at the wrong location in the payload and
3752 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3753 * It's supposed to be immediately before oMask but there seems to be no
3754 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3755 * requires header sources to form a contiguous segment at the beginning
3756 * of the message and src0_alpha has per-channel semantics.
3758 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3762 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3765 if (color1
.file
!= BAD_FILE
) {
3766 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3770 if (src_depth
.file
!= BAD_FILE
) {
3771 sources
[length
] = src_depth
;
3775 if (dst_depth
.file
!= BAD_FILE
) {
3776 sources
[length
] = dst_depth
;
3780 if (src_stencil
.file
!= BAD_FILE
) {
3781 assert(devinfo
->gen
>= 9);
3782 assert(bld
.dispatch_width() != 16);
3784 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3785 * available on gen9+. As such it's impossible to have both enabled at the
3786 * same time and therefore length cannot overrun the array.
3788 assert(length
< 15);
3790 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3791 bld
.exec_all().annotate("FB write OS")
3792 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3793 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3798 if (devinfo
->gen
>= 7) {
3799 /* Send from the GRF */
3800 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3801 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3802 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
3803 load
->dst
= payload
;
3805 inst
->src
[0] = payload
;
3806 inst
->resize_sources(1);
3808 /* Send from the MRF */
3809 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3810 sources
, length
, payload_header_size
);
3812 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3813 * will do this for us if we just give it a COMPR4 destination.
3815 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3816 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3818 inst
->resize_sources(0);
3822 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3823 inst
->mlen
= regs_written(load
);
3824 inst
->header_size
= header_size
;
3828 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
3830 const fs_builder
&ubld
= bld
.exec_all();
3831 const unsigned length
= 2;
3832 const fs_reg header
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
, length
);
3835 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3837 inst
->resize_sources(1);
3838 inst
->src
[0] = header
;
3839 inst
->opcode
= FS_OPCODE_FB_READ
;
3840 inst
->mlen
= length
;
3841 inst
->header_size
= length
;
3845 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3846 const fs_reg
&coordinate
,
3847 const fs_reg
&shadow_c
,
3848 const fs_reg
&lod
, const fs_reg
&lod2
,
3849 const fs_reg
&surface
,
3850 const fs_reg
&sampler
,
3851 unsigned coord_components
,
3852 unsigned grad_components
)
3854 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3855 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3856 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3857 fs_reg msg_end
= msg_begin
;
3860 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3862 for (unsigned i
= 0; i
< coord_components
; i
++)
3863 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3864 offset(coordinate
, bld
, i
));
3866 msg_end
= offset(msg_end
, bld
, coord_components
);
3868 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3869 * require all three components to be present and zero if they are unused.
3871 if (coord_components
> 0 &&
3872 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3873 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3874 for (unsigned i
= coord_components
; i
< 3; i
++)
3875 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3877 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3880 if (op
== SHADER_OPCODE_TXD
) {
3881 /* TXD unsupported in SIMD16 mode. */
3882 assert(bld
.dispatch_width() == 8);
3884 /* the slots for u and v are always present, but r is optional */
3885 if (coord_components
< 2)
3886 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3889 * dPdx = dudx, dvdx, drdx
3890 * dPdy = dudy, dvdy, drdy
3892 * 1-arg: Does not exist.
3894 * 2-arg: dudx dvdx dudy dvdy
3895 * dPdx.x dPdx.y dPdy.x dPdy.y
3898 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3899 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3900 * m5 m6 m7 m8 m9 m10
3902 for (unsigned i
= 0; i
< grad_components
; i
++)
3903 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3905 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3907 for (unsigned i
= 0; i
< grad_components
; i
++)
3908 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3910 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3914 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3915 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3917 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3918 bld
.dispatch_width() == 16);
3920 const brw_reg_type type
=
3921 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3922 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3923 bld
.MOV(retype(msg_end
, type
), lod
);
3924 msg_end
= offset(msg_end
, bld
, 1);
3927 if (shadow_c
.file
!= BAD_FILE
) {
3928 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3929 /* There's no plain shadow compare message, so we use shadow
3930 * compare with a bias of 0.0.
3932 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3933 msg_end
= offset(msg_end
, bld
, 1);
3936 bld
.MOV(msg_end
, shadow_c
);
3937 msg_end
= offset(msg_end
, bld
, 1);
3941 inst
->src
[0] = reg_undef
;
3942 inst
->src
[1] = surface
;
3943 inst
->src
[2] = sampler
;
3944 inst
->resize_sources(3);
3945 inst
->base_mrf
= msg_begin
.nr
;
3946 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3947 inst
->header_size
= 1;
3951 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3952 const fs_reg
&coordinate
,
3953 const fs_reg
&shadow_c
,
3954 const fs_reg
&lod
, const fs_reg
&lod2
,
3955 const fs_reg
&sample_index
,
3956 const fs_reg
&surface
,
3957 const fs_reg
&sampler
,
3958 const fs_reg
&offset_value
,
3959 unsigned coord_components
,
3960 unsigned grad_components
)
3962 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3963 fs_reg msg_coords
= message
;
3964 unsigned header_size
= 0;
3966 if (offset_value
.file
!= BAD_FILE
) {
3967 /* The offsets set up by the visitor are in the m1 header, so we can't
3974 for (unsigned i
= 0; i
< coord_components
; i
++)
3975 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
3976 offset(coordinate
, bld
, i
));
3978 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3979 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3981 if (shadow_c
.file
!= BAD_FILE
) {
3982 fs_reg msg_shadow
= msg_lod
;
3983 bld
.MOV(msg_shadow
, shadow_c
);
3984 msg_lod
= offset(msg_shadow
, bld
, 1);
3989 case SHADER_OPCODE_TXL
:
3991 bld
.MOV(msg_lod
, lod
);
3992 msg_end
= offset(msg_lod
, bld
, 1);
3994 case SHADER_OPCODE_TXD
:
3997 * dPdx = dudx, dvdx, drdx
3998 * dPdy = dudy, dvdy, drdy
4000 * Load up these values:
4001 * - dudx dudy dvdx dvdy drdx drdy
4002 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4005 for (unsigned i
= 0; i
< grad_components
; i
++) {
4006 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4007 msg_end
= offset(msg_end
, bld
, 1);
4009 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4010 msg_end
= offset(msg_end
, bld
, 1);
4013 case SHADER_OPCODE_TXS
:
4014 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4015 bld
.MOV(msg_lod
, lod
);
4016 msg_end
= offset(msg_lod
, bld
, 1);
4018 case SHADER_OPCODE_TXF
:
4019 msg_lod
= offset(msg_coords
, bld
, 3);
4020 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4021 msg_end
= offset(msg_lod
, bld
, 1);
4023 case SHADER_OPCODE_TXF_CMS
:
4024 msg_lod
= offset(msg_coords
, bld
, 3);
4026 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4028 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4029 msg_end
= offset(msg_lod
, bld
, 2);
4036 inst
->src
[0] = reg_undef
;
4037 inst
->src
[1] = surface
;
4038 inst
->src
[2] = sampler
;
4039 inst
->resize_sources(3);
4040 inst
->base_mrf
= message
.nr
;
4041 inst
->mlen
= msg_end
.nr
- message
.nr
;
4042 inst
->header_size
= header_size
;
4044 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4045 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4049 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4051 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4054 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4058 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4059 const fs_reg
&coordinate
,
4060 const fs_reg
&shadow_c
,
4061 fs_reg lod
, const fs_reg
&lod2
,
4062 const fs_reg
&sample_index
,
4064 const fs_reg
&surface
,
4065 const fs_reg
&sampler
,
4066 const fs_reg
&offset_value
,
4067 unsigned coord_components
,
4068 unsigned grad_components
)
4070 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4071 unsigned reg_width
= bld
.dispatch_width() / 8;
4072 unsigned header_size
= 0, length
= 0;
4073 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4074 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4075 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4077 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4078 offset_value
.file
!= BAD_FILE
|| inst
->eot
||
4079 op
== SHADER_OPCODE_SAMPLEINFO
||
4080 is_high_sampler(devinfo
, sampler
)) {
4081 /* For general texture offsets (no txf workaround), we need a header to
4082 * put them in. Note that we're only reserving space for it in the
4083 * message payload as it will be initialized implicitly by the
4086 * TG4 needs to place its channel select in the header, for interaction
4087 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4088 * larger sampler numbers we need to offset the Sampler State Pointer in
4092 sources
[0] = fs_reg();
4095 /* If we're requesting fewer than four channels worth of response,
4096 * and we have an explicit header, we need to set up the sampler
4097 * writemask. It's reversed from normal: 1 means "don't write".
4099 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4100 assert(regs_written(inst
) % reg_width
== 0);
4101 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4102 inst
->offset
|= mask
<< 12;
4106 if (shadow_c
.file
!= BAD_FILE
) {
4107 bld
.MOV(sources
[length
], shadow_c
);
4111 bool coordinate_done
= false;
4113 /* Set up the LOD info */
4116 case SHADER_OPCODE_TXL
:
4117 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4118 op
= SHADER_OPCODE_TXL_LZ
;
4121 bld
.MOV(sources
[length
], lod
);
4124 case SHADER_OPCODE_TXD
:
4125 /* TXD should have been lowered in SIMD16 mode. */
4126 assert(bld
.dispatch_width() == 8);
4128 /* Load dPdx and the coordinate together:
4129 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4131 for (unsigned i
= 0; i
< coord_components
; i
++) {
4132 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4134 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4135 * only derivatives for (u, v, r).
4137 if (i
< grad_components
) {
4138 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4139 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4143 coordinate_done
= true;
4145 case SHADER_OPCODE_TXS
:
4146 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4149 case SHADER_OPCODE_TXF
:
4150 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4151 * On Gen9 they are u, v, lod, r
4153 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4155 if (devinfo
->gen
>= 9) {
4156 if (coord_components
>= 2) {
4157 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4158 offset(coordinate
, bld
, 1));
4160 sources
[length
] = brw_imm_d(0);
4165 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4166 op
= SHADER_OPCODE_TXF_LZ
;
4168 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4172 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4173 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4174 offset(coordinate
, bld
, i
));
4176 coordinate_done
= true;
4179 case SHADER_OPCODE_TXF_CMS
:
4180 case SHADER_OPCODE_TXF_CMS_W
:
4181 case SHADER_OPCODE_TXF_UMS
:
4182 case SHADER_OPCODE_TXF_MCS
:
4183 if (op
== SHADER_OPCODE_TXF_UMS
||
4184 op
== SHADER_OPCODE_TXF_CMS
||
4185 op
== SHADER_OPCODE_TXF_CMS_W
) {
4186 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4190 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4191 /* Data from the multisample control surface. */
4192 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4195 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4198 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4199 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4202 offset(mcs
, bld
, 1));
4207 /* There is no offsetting for this message; just copy in the integer
4208 * texture coordinates.
4210 for (unsigned i
= 0; i
< coord_components
; i
++)
4211 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4212 offset(coordinate
, bld
, i
));
4214 coordinate_done
= true;
4216 case SHADER_OPCODE_TG4_OFFSET
:
4217 /* More crazy intermixing */
4218 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4219 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4221 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4222 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4223 offset(offset_value
, bld
, i
));
4225 if (coord_components
== 3) /* r if present */
4226 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4228 coordinate_done
= true;
4234 /* Set up the coordinate (except for cases where it was done above) */
4235 if (!coordinate_done
) {
4236 for (unsigned i
= 0; i
< coord_components
; i
++)
4237 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4242 mlen
= length
* reg_width
- header_size
;
4244 mlen
= length
* reg_width
;
4246 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4247 BRW_REGISTER_TYPE_F
);
4248 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4250 /* Generate the SEND. */
4252 inst
->src
[0] = src_payload
;
4253 inst
->src
[1] = surface
;
4254 inst
->src
[2] = sampler
;
4255 inst
->resize_sources(3);
4257 inst
->header_size
= header_size
;
4259 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4260 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4264 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4266 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4267 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4268 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4269 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4270 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4271 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4272 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4273 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4274 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4275 const fs_reg
&offset_value
= inst
->src
[TEX_LOGICAL_SRC_OFFSET_VALUE
];
4276 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4277 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4278 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4279 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4281 if (devinfo
->gen
>= 7) {
4282 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4283 shadow_c
, lod
, lod2
, sample_index
,
4284 mcs
, surface
, sampler
, offset_value
,
4285 coord_components
, grad_components
);
4286 } else if (devinfo
->gen
>= 5) {
4287 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4288 shadow_c
, lod
, lod2
, sample_index
,
4289 surface
, sampler
, offset_value
,
4290 coord_components
, grad_components
);
4292 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4293 shadow_c
, lod
, lod2
,
4295 coord_components
, grad_components
);
4300 * Initialize the header present in some typed and untyped surface
4304 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4306 fs_builder ubld
= bld
.exec_all().group(8, 0);
4307 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4308 ubld
.MOV(dst
, brw_imm_d(0));
4309 ubld
.MOV(component(dst
, 7), sample_mask
);
4314 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4315 const fs_reg
&sample_mask
)
4317 /* Get the logical send arguments. */
4318 const fs_reg
&addr
= inst
->src
[0];
4319 const fs_reg
&src
= inst
->src
[1];
4320 const fs_reg
&surface
= inst
->src
[2];
4321 const UNUSED fs_reg
&dims
= inst
->src
[3];
4322 const fs_reg
&arg
= inst
->src
[4];
4324 /* Calculate the total number of components of the payload. */
4325 const unsigned addr_sz
= inst
->components_read(0);
4326 const unsigned src_sz
= inst
->components_read(1);
4327 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4328 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4330 /* Allocate space for the payload. */
4331 fs_reg
*const components
= new fs_reg
[sz
];
4332 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4335 /* Construct the payload. */
4337 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4339 for (unsigned i
= 0; i
< addr_sz
; i
++)
4340 components
[n
++] = offset(addr
, bld
, i
);
4342 for (unsigned i
= 0; i
< src_sz
; i
++)
4343 components
[n
++] = offset(src
, bld
, i
);
4345 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4347 /* Update the original instruction. */
4349 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4350 inst
->header_size
= header_sz
;
4352 inst
->src
[0] = payload
;
4353 inst
->src
[1] = surface
;
4355 inst
->resize_sources(3);
4357 delete[] components
;
4361 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4363 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4365 if (devinfo
->gen
>= 7) {
4366 /* We are switching the instruction from an ALU-like instruction to a
4367 * send-from-grf instruction. Since sends can't handle strides or
4368 * source modifiers, we have to make a copy of the offset source.
4370 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4371 bld
.MOV(tmp
, inst
->src
[1]);
4374 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4377 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4378 BRW_REGISTER_TYPE_UD
);
4380 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4382 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4383 inst
->resize_sources(1);
4384 inst
->base_mrf
= payload
.nr
;
4385 inst
->header_size
= 1;
4386 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4391 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4393 assert(bld
.shader
->devinfo
->gen
< 6);
4396 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4398 if (inst
->sources
> 1) {
4399 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4400 * "Message Payload":
4402 * "Operand0[7]. For the INT DIV functions, this operand is the
4405 * "Operand1[7]. For the INT DIV functions, this operand is the
4408 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4409 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4410 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4412 inst
->resize_sources(1);
4413 inst
->src
[0] = src0
;
4415 assert(inst
->exec_size
== 8);
4416 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4421 fs_visitor::lower_logical_sends()
4423 bool progress
= false;
4425 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4426 const fs_builder
ibld(this, block
, inst
);
4428 switch (inst
->opcode
) {
4429 case FS_OPCODE_FB_WRITE_LOGICAL
:
4430 assert(stage
== MESA_SHADER_FRAGMENT
);
4431 lower_fb_write_logical_send(ibld
, inst
,
4432 (const brw_wm_prog_data
*)prog_data
,
4433 (const brw_wm_prog_key
*)key
,
4437 case FS_OPCODE_FB_READ_LOGICAL
:
4438 lower_fb_read_logical_send(ibld
, inst
);
4441 case SHADER_OPCODE_TEX_LOGICAL
:
4442 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4445 case SHADER_OPCODE_TXD_LOGICAL
:
4446 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4449 case SHADER_OPCODE_TXF_LOGICAL
:
4450 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4453 case SHADER_OPCODE_TXL_LOGICAL
:
4454 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4457 case SHADER_OPCODE_TXS_LOGICAL
:
4458 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4461 case FS_OPCODE_TXB_LOGICAL
:
4462 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4465 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4466 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4469 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4470 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4473 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4474 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4477 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4478 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4481 case SHADER_OPCODE_LOD_LOGICAL
:
4482 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4485 case SHADER_OPCODE_TG4_LOGICAL
:
4486 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4489 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4490 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4493 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4494 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4497 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4498 lower_surface_logical_send(ibld
, inst
,
4499 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4503 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4504 lower_surface_logical_send(ibld
, inst
,
4505 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4506 ibld
.sample_mask_reg());
4509 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4510 lower_surface_logical_send(ibld
, inst
,
4511 SHADER_OPCODE_UNTYPED_ATOMIC
,
4512 ibld
.sample_mask_reg());
4515 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4516 lower_surface_logical_send(ibld
, inst
,
4517 SHADER_OPCODE_TYPED_SURFACE_READ
,
4521 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4522 lower_surface_logical_send(ibld
, inst
,
4523 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4524 ibld
.sample_mask_reg());
4527 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4528 lower_surface_logical_send(ibld
, inst
,
4529 SHADER_OPCODE_TYPED_ATOMIC
,
4530 ibld
.sample_mask_reg());
4533 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4534 lower_varying_pull_constant_logical_send(ibld
, inst
);
4537 case SHADER_OPCODE_RCP
:
4538 case SHADER_OPCODE_RSQ
:
4539 case SHADER_OPCODE_SQRT
:
4540 case SHADER_OPCODE_EXP2
:
4541 case SHADER_OPCODE_LOG2
:
4542 case SHADER_OPCODE_SIN
:
4543 case SHADER_OPCODE_COS
:
4544 case SHADER_OPCODE_POW
:
4545 case SHADER_OPCODE_INT_QUOTIENT
:
4546 case SHADER_OPCODE_INT_REMAINDER
:
4547 /* The math opcodes are overloaded for the send-like and
4548 * expression-like instructions which seems kind of icky. Gen6+ has
4549 * a native (but rather quirky) MATH instruction so we don't need to
4550 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4551 * logical instructions (which we can easily recognize because they
4552 * have mlen = 0) into send-like virtual instructions.
4554 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4555 lower_math_logical_send(ibld
, inst
);
4570 invalidate_live_intervals();
4576 * Get the closest allowed SIMD width for instruction \p inst accounting for
4577 * some common regioning and execution control restrictions that apply to FPU
4578 * instructions. These restrictions don't necessarily have any relevance to
4579 * instructions not executed by the FPU pipeline like extended math, control
4580 * flow or send message instructions.
4582 * For virtual opcodes it's really up to the instruction -- In some cases
4583 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4584 * instructions) it may simplify virtual instruction lowering if we can
4585 * enforce FPU-like regioning restrictions already on the virtual instruction,
4586 * in other cases (e.g. virtual send-like instructions) this may be
4587 * excessively restrictive.
4590 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
4591 const fs_inst
*inst
)
4593 /* Maximum execution size representable in the instruction controls. */
4594 unsigned max_width
= MIN2(32, inst
->exec_size
);
4596 /* According to the PRMs:
4597 * "A. In Direct Addressing mode, a source cannot span more than 2
4598 * adjacent GRF registers.
4599 * B. A destination cannot span more than 2 adjacent GRF registers."
4601 * Look for the source or destination with the largest register region
4602 * which is the one that is going to limit the overall execution size of
4603 * the instruction due to this rule.
4605 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4607 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4608 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
4610 /* Calculate the maximum execution size of the instruction based on the
4611 * factor by which it goes over the hardware limit of 2 GRFs.
4614 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4616 /* According to the IVB PRMs:
4617 * "When destination spans two registers, the source MUST span two
4618 * registers. The exception to the above rule:
4620 * - When source is scalar, the source registers are not incremented.
4621 * - When source is packed integer Word and destination is packed
4622 * integer DWord, the source register is not incremented but the
4623 * source sub register is incremented."
4625 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4626 * restrictions. The code below intentionally doesn't check whether the
4627 * destination type is integer because empirically the hardware doesn't
4628 * seem to care what the actual type is as long as it's dword-aligned.
4630 if (devinfo
->gen
< 8) {
4631 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4632 if (DIV_ROUND_UP(inst
->size_written
, REG_SIZE
) == 2 &&
4633 inst
->size_read(i
) != 0 && DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
) != 2 &&
4634 !is_uniform(inst
->src
[i
]) &&
4635 !(type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4636 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1)) {
4637 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4638 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4643 /* From the IVB PRMs:
4644 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4645 * are applied for both halves of the SIMD32 instruction. If different
4646 * execution mask channels are required, split the instruction into two
4647 * SIMD16 instructions."
4649 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4650 * 32-wide control flow support in hardware and will behave similarly.
4652 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4653 max_width
= MIN2(max_width
, 16);
4655 /* From the IVB PRMs (applies to HSW too):
4656 * "Instructions with condition modifiers must not use SIMD32."
4658 * From the BDW PRMs (applies to later hardware too):
4659 * "Ternary instruction with condition modifiers must not use SIMD32."
4661 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4662 max_width
= MIN2(max_width
, 16);
4664 /* From the IVB PRMs (applies to other devices that don't have the
4665 * gen_device_info::supports_simd16_3src flag set):
4666 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4667 * SIMD8 is not allowed for DF operations."
4669 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4670 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4672 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
4673 * the 8-bit quarter of the execution mask signals specified in the
4674 * instruction control fields) for the second compressed half of any
4675 * single-precision instruction (for double-precision instructions
4676 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
4677 * the EU will apply the wrong execution controls for the second
4678 * sequential GRF write if the number of channels per GRF is not exactly
4679 * eight in single-precision mode (or four in double-float mode).
4681 * In this situation we calculate the maximum size of the split
4682 * instructions so they only ever write to a single register.
4684 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
4685 !inst
->force_writemask_all
) {
4686 const unsigned channels_per_grf
= inst
->exec_size
/
4687 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4688 unsigned exec_type_size
= 0;
4689 for (int i
= 0; i
< inst
->sources
; i
++) {
4690 if (inst
->src
[i
].file
!= BAD_FILE
)
4691 exec_type_size
= MAX2(exec_type_size
, type_sz(inst
->src
[i
].type
));
4693 assert(exec_type_size
);
4695 /* The hardware shifts exactly 8 channels per compressed half of the
4696 * instruction in single-precision mode and exactly 4 in double-precision.
4698 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
4699 max_width
= MIN2(max_width
, channels_per_grf
);
4702 /* Only power-of-two execution sizes are representable in the instruction
4705 return 1 << _mesa_logbase2(max_width
);
4709 * Get the maximum allowed SIMD width for instruction \p inst accounting for
4710 * various payload size restrictions that apply to sampler message
4713 * This is only intended to provide a maximum theoretical bound for the
4714 * execution size of the message based on the number of argument components
4715 * alone, which in most cases will determine whether the SIMD8 or SIMD16
4716 * variant of the message can be used, though some messages may have
4717 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
4718 * the message length to determine the exact SIMD width and argument count,
4719 * which makes a number of sampler message combinations impossible to
4723 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
4724 const fs_inst
*inst
)
4726 /* Calculate the number of coordinate components that have to be present
4727 * assuming that additional arguments follow the texel coordinates in the
4728 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
4729 * need to pad to four or three components depending on the message,
4730 * pre-ILK we need to pad to at most three components.
4732 const unsigned req_coord_components
=
4733 (devinfo
->gen
>= 7 ||
4734 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
4735 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
4736 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
4739 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
4740 * variant of the TXL or TXF message.
4742 const bool implicit_lod
= devinfo
->gen
>= 9 &&
4743 (inst
->opcode
== SHADER_OPCODE_TXL
||
4744 inst
->opcode
== SHADER_OPCODE_TXF
) &&
4745 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
4747 /* Calculate the total number of argument components that need to be passed
4748 * to the sampler unit.
4750 const unsigned num_payload_components
=
4751 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
4752 req_coord_components
) +
4753 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
4754 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
4755 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
4756 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
4757 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
4758 inst
->components_read(TEX_LOGICAL_SRC_OFFSET_VALUE
) : 0) +
4759 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
4761 /* SIMD16 messages with more than five arguments exceed the maximum message
4762 * size supported by the sampler, regardless of whether a header is
4765 return MIN2(inst
->exec_size
,
4766 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
4770 * Get the closest native SIMD width supported by the hardware for instruction
4771 * \p inst. The instruction will be left untouched by
4772 * fs_visitor::lower_simd_width() if the returned value is equal to the
4773 * original execution size.
4776 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
4777 const fs_inst
*inst
)
4779 switch (inst
->opcode
) {
4780 case BRW_OPCODE_MOV
:
4781 case BRW_OPCODE_SEL
:
4782 case BRW_OPCODE_NOT
:
4783 case BRW_OPCODE_AND
:
4785 case BRW_OPCODE_XOR
:
4786 case BRW_OPCODE_SHR
:
4787 case BRW_OPCODE_SHL
:
4788 case BRW_OPCODE_ASR
:
4789 case BRW_OPCODE_CMPN
:
4790 case BRW_OPCODE_CSEL
:
4791 case BRW_OPCODE_F32TO16
:
4792 case BRW_OPCODE_F16TO32
:
4793 case BRW_OPCODE_BFREV
:
4794 case BRW_OPCODE_BFE
:
4795 case BRW_OPCODE_ADD
:
4796 case BRW_OPCODE_MUL
:
4797 case BRW_OPCODE_AVG
:
4798 case BRW_OPCODE_FRC
:
4799 case BRW_OPCODE_RNDU
:
4800 case BRW_OPCODE_RNDD
:
4801 case BRW_OPCODE_RNDE
:
4802 case BRW_OPCODE_RNDZ
:
4803 case BRW_OPCODE_LZD
:
4804 case BRW_OPCODE_FBH
:
4805 case BRW_OPCODE_FBL
:
4806 case BRW_OPCODE_CBIT
:
4807 case BRW_OPCODE_SAD2
:
4808 case BRW_OPCODE_MAD
:
4809 case BRW_OPCODE_LRP
:
4810 case FS_OPCODE_PACK
:
4811 return get_fpu_lowered_simd_width(devinfo
, inst
);
4813 case BRW_OPCODE_CMP
: {
4814 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4815 * when the destination is a GRF the dependency-clear bit on the flag
4816 * register is cleared early.
4818 * Suggested workarounds are to disable coissuing CMP instructions
4819 * or to split CMP(16) instructions into two CMP(8) instructions.
4821 * We choose to split into CMP(8) instructions since disabling
4822 * coissuing would affect CMP instructions not otherwise affected by
4825 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4826 !inst
->dst
.is_null() ? 8 : ~0);
4827 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4829 case BRW_OPCODE_BFI1
:
4830 case BRW_OPCODE_BFI2
:
4831 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4833 * "Force BFI instructions to be executed always in SIMD8."
4835 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4836 get_fpu_lowered_simd_width(devinfo
, inst
));
4839 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4840 return inst
->exec_size
;
4842 case SHADER_OPCODE_RCP
:
4843 case SHADER_OPCODE_RSQ
:
4844 case SHADER_OPCODE_SQRT
:
4845 case SHADER_OPCODE_EXP2
:
4846 case SHADER_OPCODE_LOG2
:
4847 case SHADER_OPCODE_SIN
:
4848 case SHADER_OPCODE_COS
:
4849 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4852 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4853 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4854 MIN2(8, inst
->exec_size
));
4856 case SHADER_OPCODE_POW
:
4857 /* SIMD16 is only allowed on Gen7+. */
4858 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4859 MIN2(8, inst
->exec_size
));
4861 case SHADER_OPCODE_INT_QUOTIENT
:
4862 case SHADER_OPCODE_INT_REMAINDER
:
4863 /* Integer division is limited to SIMD8 on all generations. */
4864 return MIN2(8, inst
->exec_size
);
4866 case FS_OPCODE_LINTERP
:
4867 case FS_OPCODE_GET_BUFFER_SIZE
:
4868 case FS_OPCODE_DDX_COARSE
:
4869 case FS_OPCODE_DDX_FINE
:
4870 case FS_OPCODE_DDY_COARSE
:
4871 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4872 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4873 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4874 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4875 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4876 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4877 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4878 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4879 return MIN2(16, inst
->exec_size
);
4881 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4882 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4883 * message used to implement varying pull constant loads, so expand it
4884 * to SIMD16. An alternative with longer message payload length but
4885 * shorter return payload would be to use the SIMD8 sampler message that
4886 * takes (header, u, v, r) as parameters instead of (header, u).
4888 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4890 case FS_OPCODE_DDY_FINE
:
4891 /* The implementation of this virtual opcode may require emitting
4892 * compressed Align16 instructions, which are severely limited on some
4895 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4896 * Region Restrictions):
4898 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4899 * and SIMD8 is not allowed for DF operations."
4901 * In this context, "DW operations" means "operations acting on 32-bit
4902 * values", so it includes operations on floats.
4904 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4905 * (Instruction Compression -> Rules and Restrictions):
4907 * "A compressed instruction must be in Align1 access mode. Align16
4908 * mode instructions cannot be compressed."
4910 * Similar text exists in the g45 PRM.
4912 * Empirically, compressed align16 instructions using odd register
4913 * numbers don't appear to work on Sandybridge either.
4915 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4916 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4917 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
4919 case SHADER_OPCODE_MULH
:
4920 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4921 * is 8-wide on Gen7+.
4923 return (devinfo
->gen
>= 7 ? 8 :
4924 get_fpu_lowered_simd_width(devinfo
, inst
));
4926 case FS_OPCODE_FB_WRITE_LOGICAL
:
4927 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4930 assert(devinfo
->gen
!= 6 ||
4931 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4932 inst
->exec_size
== 8);
4933 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4934 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4935 8 : MIN2(16, inst
->exec_size
));
4937 case FS_OPCODE_FB_READ_LOGICAL
:
4938 return MIN2(16, inst
->exec_size
);
4940 case SHADER_OPCODE_TEX_LOGICAL
:
4941 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4942 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4943 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4944 case SHADER_OPCODE_LOD_LOGICAL
:
4945 case SHADER_OPCODE_TG4_LOGICAL
:
4946 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4947 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4948 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4949 return get_sampler_lowered_simd_width(devinfo
, inst
);
4951 case SHADER_OPCODE_TXD_LOGICAL
:
4952 /* TXD is unsupported in SIMD16 mode. */
4955 case SHADER_OPCODE_TXL_LOGICAL
:
4956 case FS_OPCODE_TXB_LOGICAL
:
4957 /* Only one execution size is representable pre-ILK depending on whether
4958 * the shadow reference argument is present.
4960 if (devinfo
->gen
== 4)
4961 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
4963 return get_sampler_lowered_simd_width(devinfo
, inst
);
4965 case SHADER_OPCODE_TXF_LOGICAL
:
4966 case SHADER_OPCODE_TXS_LOGICAL
:
4967 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4968 * messages. Use SIMD16 instead.
4970 if (devinfo
->gen
== 4)
4973 return get_sampler_lowered_simd_width(devinfo
, inst
);
4975 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4976 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4977 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4980 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4981 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4982 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4983 return MIN2(16, inst
->exec_size
);
4985 case SHADER_OPCODE_URB_READ_SIMD8
:
4986 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
4987 case SHADER_OPCODE_URB_WRITE_SIMD8
:
4988 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
4989 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
4990 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
4991 return MIN2(8, inst
->exec_size
);
4993 case SHADER_OPCODE_MOV_INDIRECT
:
4994 /* Prior to Broadwell, we only have 8 address subregisters */
4995 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
4996 2 * REG_SIZE
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
4999 case SHADER_OPCODE_LOAD_PAYLOAD
: {
5000 const unsigned reg_count
=
5001 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
5003 if (reg_count
> 2) {
5004 /* Only LOAD_PAYLOAD instructions with per-channel destination region
5005 * can be easily lowered (which excludes headers and heterogeneous
5008 assert(!inst
->header_size
);
5009 for (unsigned i
= 0; i
< inst
->sources
; i
++)
5010 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
5011 inst
->src
[i
].file
== BAD_FILE
);
5013 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
5015 return inst
->exec_size
;
5019 return inst
->exec_size
;
5024 * Return true if splitting out the group of channels of instruction \p inst
5025 * given by lbld.group() requires allocating a temporary for the i-th source
5026 * of the lowered instruction.
5029 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
5031 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
5032 (inst
->components_read(i
) == 1 &&
5033 lbld
.dispatch_width() <= inst
->exec_size
));
5037 * Extract the data that would be consumed by the channel group given by
5038 * lbld.group() from the i-th source region of instruction \p inst and return
5039 * it as result in packed form. If any copy instructions are required they
5040 * will be emitted before the given \p inst in \p block.
5043 emit_unzip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
,
5046 /* Specified channel group from the source region. */
5047 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
5049 if (needs_src_copy(lbld
, inst
, i
)) {
5050 /* Builder of the right width to perform the copy avoiding uninitialized
5051 * data if the lowered execution size is greater than the original
5052 * execution size of the instruction.
5054 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5055 inst
->exec_size
), 0);
5056 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
5058 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
5059 cbld
.at(block
, inst
)
5060 .MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
5064 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
5065 /* The source is invariant for all dispatch_width-wide groups of the
5068 return inst
->src
[i
];
5071 /* We can just point the lowered instruction at the right channel group
5072 * from the original region.
5079 * Return true if splitting out the group of channels of instruction \p inst
5080 * given by lbld.group() requires allocating a temporary for the destination
5081 * of the lowered instruction and copying the data back to the original
5082 * destination region.
5085 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5087 /* If the instruction writes more than one component we'll have to shuffle
5088 * the results of multiple lowered instructions in order to make sure that
5089 * they end up arranged correctly in the original destination region.
5091 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
5094 /* If the lowered execution size is larger than the original the result of
5095 * the instruction won't fit in the original destination, so we'll have to
5096 * allocate a temporary in any case.
5098 if (lbld
.dispatch_width() > inst
->exec_size
)
5101 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5102 /* If we already made a copy of the source for other reasons there won't
5103 * be any overlap with the destination.
5105 if (needs_src_copy(lbld
, inst
, i
))
5108 /* In order to keep the logic simple we emit a copy whenever the
5109 * destination region doesn't exactly match an overlapping source, which
5110 * may point at the source and destination not being aligned group by
5111 * group which could cause one of the lowered instructions to overwrite
5112 * the data read from the same source by other lowered instructions.
5114 if (regions_overlap(inst
->dst
, inst
->size_written
,
5115 inst
->src
[i
], inst
->size_read(i
)) &&
5116 !inst
->dst
.equals(inst
->src
[i
]))
5124 * Insert data from a packed temporary into the channel group given by
5125 * lbld.group() of the destination region of instruction \p inst and return
5126 * the temporary as result. If any copy instructions are required they will
5127 * be emitted around the given \p inst in \p block.
5130 emit_zip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
)
5132 /* Builder of the right width to perform the copy avoiding uninitialized
5133 * data if the lowered execution size is greater than the original
5134 * execution size of the instruction.
5136 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5137 inst
->exec_size
), 0);
5139 /* Specified channel group from the destination region. */
5140 const fs_reg dst
= horiz_offset(inst
->dst
, lbld
.group());
5141 const unsigned dst_size
= inst
->size_written
/
5142 inst
->dst
.component_size(inst
->exec_size
);
5144 if (needs_dst_copy(lbld
, inst
)) {
5145 const fs_reg tmp
= lbld
.vgrf(inst
->dst
.type
, dst_size
);
5147 if (inst
->predicate
) {
5148 /* Handle predication by copying the original contents of
5149 * the destination into the temporary before emitting the
5150 * lowered instruction.
5152 for (unsigned k
= 0; k
< dst_size
; ++k
)
5153 cbld
.at(block
, inst
)
5154 .MOV(offset(tmp
, lbld
, k
), offset(dst
, inst
->exec_size
, k
));
5157 for (unsigned k
= 0; k
< dst_size
; ++k
)
5158 cbld
.at(block
, inst
->next
)
5159 .MOV(offset(dst
, inst
->exec_size
, k
), offset(tmp
, lbld
, k
));
5164 /* No need to allocate a temporary for the lowered instruction, just
5165 * take the right group of channels from the original region.
5172 fs_visitor::lower_simd_width()
5174 bool progress
= false;
5176 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5177 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5179 if (lower_width
!= inst
->exec_size
) {
5180 /* Builder matching the original instruction. We may also need to
5181 * emit an instruction of width larger than the original, set the
5182 * execution size of the builder to the highest of both for now so
5183 * we're sure that both cases can be handled.
5185 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5186 const fs_builder ibld
= bld
.at(block
, inst
)
5187 .exec_all(inst
->force_writemask_all
)
5188 .group(max_width
, inst
->group
/ max_width
);
5190 /* Split the copies in chunks of the execution width of either the
5191 * original or the lowered instruction, whichever is lower.
5193 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5194 const unsigned dst_size
= inst
->size_written
/
5195 inst
->dst
.component_size(inst
->exec_size
);
5197 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5199 for (unsigned i
= 0; i
< n
; i
++) {
5200 /* Emit a copy of the original instruction with the lowered width.
5201 * If the EOT flag was set throw it away except for the last
5202 * instruction to avoid killing the thread prematurely.
5204 fs_inst split_inst
= *inst
;
5205 split_inst
.exec_size
= lower_width
;
5206 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
5208 /* Select the correct channel enables for the i-th group, then
5209 * transform the sources and destination and emit the lowered
5212 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5214 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5215 split_inst
.src
[j
] = emit_unzip(lbld
, block
, inst
, j
);
5217 split_inst
.dst
= emit_zip(lbld
, block
, inst
);
5218 split_inst
.size_written
=
5219 split_inst
.dst
.component_size(lower_width
) * dst_size
;
5221 lbld
.emit(split_inst
);
5224 inst
->remove(block
);
5230 invalidate_live_intervals();
5236 fs_visitor::dump_instructions()
5238 dump_instructions(NULL
);
5242 fs_visitor::dump_instructions(const char *name
)
5244 FILE *file
= stderr
;
5245 if (name
&& geteuid() != 0) {
5246 file
= fopen(name
, "w");
5252 calculate_register_pressure();
5253 int ip
= 0, max_pressure
= 0;
5254 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5255 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5256 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5257 dump_instruction(inst
, file
);
5260 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5263 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5264 fprintf(file
, "%4d: ", ip
++);
5265 dump_instruction(inst
, file
);
5269 if (file
!= stderr
) {
5275 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5277 dump_instruction(be_inst
, stderr
);
5281 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5283 fs_inst
*inst
= (fs_inst
*)be_inst
;
5285 if (inst
->predicate
) {
5286 fprintf(file
, "(%cf0.%d) ",
5287 inst
->predicate_inverse
? '-' : '+',
5291 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5293 fprintf(file
, ".sat");
5294 if (inst
->conditional_mod
) {
5295 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5296 if (!inst
->predicate
&&
5297 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5298 inst
->opcode
!= BRW_OPCODE_IF
&&
5299 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5300 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5303 fprintf(file
, "(%d) ", inst
->exec_size
);
5306 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5310 fprintf(file
, "(EOT) ");
5313 switch (inst
->dst
.file
) {
5315 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5316 if (alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
||
5317 inst
->dst
.offset
% REG_SIZE
)
5318 fprintf(file
, "+%d.%d",
5319 inst
->dst
.offset
/ REG_SIZE
, inst
->dst
.offset
% REG_SIZE
);
5322 fprintf(file
, "g%d", inst
->dst
.nr
);
5325 fprintf(file
, "m%d", inst
->dst
.nr
);
5328 fprintf(file
, "(null)");
5331 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.offset
/ 4);
5334 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.offset
/ REG_SIZE
);
5337 switch (inst
->dst
.nr
) {
5339 fprintf(file
, "null");
5341 case BRW_ARF_ADDRESS
:
5342 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5344 case BRW_ARF_ACCUMULATOR
:
5345 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5348 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5351 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5354 if (inst
->dst
.subnr
)
5355 fprintf(file
, "+%d", inst
->dst
.subnr
);
5358 unreachable("not reached");
5360 if (inst
->dst
.stride
!= 1)
5361 fprintf(file
, "<%u>", inst
->dst
.stride
);
5362 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
5364 for (int i
= 0; i
< inst
->sources
; i
++) {
5365 if (inst
->src
[i
].negate
)
5367 if (inst
->src
[i
].abs
)
5369 switch (inst
->src
[i
].file
) {
5371 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5372 if (alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
) ||
5373 inst
->src
[i
].offset
% REG_SIZE
!= 0)
5374 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ REG_SIZE
,
5375 inst
->src
[i
].offset
% REG_SIZE
);
5378 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5381 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5384 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].offset
/ REG_SIZE
);
5387 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4);
5388 if (inst
->src
[i
].offset
% 4 != 0) {
5389 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ 4,
5390 inst
->src
[i
].offset
% 4);
5394 fprintf(file
, "(null)");
5397 switch (inst
->src
[i
].type
) {
5398 case BRW_REGISTER_TYPE_F
:
5399 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5401 case BRW_REGISTER_TYPE_DF
:
5402 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5404 case BRW_REGISTER_TYPE_W
:
5405 case BRW_REGISTER_TYPE_D
:
5406 fprintf(file
, "%dd", inst
->src
[i
].d
);
5408 case BRW_REGISTER_TYPE_UW
:
5409 case BRW_REGISTER_TYPE_UD
:
5410 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5412 case BRW_REGISTER_TYPE_VF
:
5413 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5414 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5415 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5416 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5417 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5420 fprintf(file
, "???");
5425 switch (inst
->src
[i
].nr
) {
5427 fprintf(file
, "null");
5429 case BRW_ARF_ADDRESS
:
5430 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5432 case BRW_ARF_ACCUMULATOR
:
5433 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5436 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5439 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5442 if (inst
->src
[i
].subnr
)
5443 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
5446 if (inst
->src
[i
].abs
)
5449 if (inst
->src
[i
].file
!= IMM
) {
5451 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5452 unsigned hstride
= inst
->src
[i
].hstride
;
5453 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5455 stride
= inst
->src
[i
].stride
;
5458 fprintf(file
, "<%u>", stride
);
5460 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
5463 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5464 fprintf(file
, ", ");
5469 if (inst
->force_writemask_all
)
5470 fprintf(file
, "NoMask ");
5472 if (inst
->exec_size
!= dispatch_width
)
5473 fprintf(file
, "group%d ", inst
->group
);
5475 fprintf(file
, "\n");
5479 * Possibly returns an instruction that set up @param reg.
5481 * Sometimes we want to take the result of some expression/variable
5482 * dereference tree and rewrite the instruction generating the result
5483 * of the tree. When processing the tree, we know that the
5484 * instructions generated are all writing temporaries that are dead
5485 * outside of this tree. So, if we have some instructions that write
5486 * a temporary, we're free to point that temp write somewhere else.
5488 * Note that this doesn't guarantee that the instruction generated
5489 * only reg -- it might be the size=4 destination of a texture instruction.
5492 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5497 end
->is_partial_write() ||
5498 !reg
.equals(end
->dst
)) {
5506 fs_visitor::setup_fs_payload_gen6()
5508 assert(stage
== MESA_SHADER_FRAGMENT
);
5509 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5511 unsigned barycentric_interp_modes
=
5512 (stage
== MESA_SHADER_FRAGMENT
) ?
5513 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
5515 assert(devinfo
->gen
>= 6);
5517 /* R0-1: masks, pixel X/Y coordinates. */
5518 payload
.num_regs
= 2;
5519 /* R2: only for 32-pixel dispatch.*/
5521 /* R3-26: barycentric interpolation coordinates. These appear in the
5522 * same order that they appear in the brw_barycentric_mode
5523 * enum. Each set of coordinates occupies 2 registers if dispatch width
5524 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5525 * appear if they were enabled using the "Barycentric Interpolation
5526 * Mode" bits in WM_STATE.
5528 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5529 if (barycentric_interp_modes
& (1 << i
)) {
5530 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5531 payload
.num_regs
+= 2;
5532 if (dispatch_width
== 16) {
5533 payload
.num_regs
+= 2;
5538 /* R27: interpolated depth if uses source depth */
5539 prog_data
->uses_src_depth
=
5540 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5541 if (prog_data
->uses_src_depth
) {
5542 payload
.source_depth_reg
= payload
.num_regs
;
5544 if (dispatch_width
== 16) {
5545 /* R28: interpolated depth if not SIMD8. */
5550 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5551 prog_data
->uses_src_w
=
5552 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5553 if (prog_data
->uses_src_w
) {
5554 payload
.source_w_reg
= payload
.num_regs
;
5556 if (dispatch_width
== 16) {
5557 /* R30: interpolated W if not SIMD8. */
5562 /* R31: MSAA position offsets. */
5563 if (prog_data
->persample_dispatch
&&
5564 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5565 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5567 * "MSDISPMODE_PERSAMPLE is required in order to select
5570 * So we can only really get sample positions if we are doing real
5571 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5572 * persample dispatch, we hard-code it to 0.5.
5574 prog_data
->uses_pos_offset
= true;
5575 payload
.sample_pos_reg
= payload
.num_regs
;
5579 /* R32: MSAA input coverage mask */
5580 prog_data
->uses_sample_mask
=
5581 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5582 if (prog_data
->uses_sample_mask
) {
5583 assert(devinfo
->gen
>= 7);
5584 payload
.sample_mask_in_reg
= payload
.num_regs
;
5586 if (dispatch_width
== 16) {
5587 /* R33: input coverage mask if not SIMD8. */
5592 /* R34-: bary for 32-pixel. */
5593 /* R58-59: interp W for 32-pixel. */
5595 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5596 source_depth_to_render_target
= true;
5601 fs_visitor::setup_vs_payload()
5603 /* R0: thread header, R1: urb handles */
5604 payload
.num_regs
= 2;
5608 fs_visitor::setup_gs_payload()
5610 assert(stage
== MESA_SHADER_GEOMETRY
);
5612 struct brw_gs_prog_data
*gs_prog_data
=
5613 (struct brw_gs_prog_data
*) prog_data
;
5614 struct brw_vue_prog_data
*vue_prog_data
=
5615 (struct brw_vue_prog_data
*) prog_data
;
5617 /* R0: thread header, R1: output URB handles */
5618 payload
.num_regs
= 2;
5620 if (gs_prog_data
->include_primitive_id
) {
5621 /* R2: Primitive ID 0..7 */
5625 /* Use a maximum of 24 registers for push-model inputs. */
5626 const unsigned max_push_components
= 24;
5628 /* If pushing our inputs would take too many registers, reduce the URB read
5629 * length (which is in HWords, or 8 registers), and resort to pulling.
5631 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5632 * have to multiply by VerticesIn to obtain the total storage requirement.
5634 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5635 max_push_components
|| gs_prog_data
->invocations
> 1) {
5636 gs_prog_data
->base
.include_vue_handles
= true;
5638 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5639 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5641 vue_prog_data
->urb_read_length
=
5642 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5647 fs_visitor::setup_cs_payload()
5649 assert(devinfo
->gen
>= 7);
5650 payload
.num_regs
= 1;
5654 fs_visitor::calculate_register_pressure()
5656 invalidate_live_intervals();
5657 calculate_live_intervals();
5659 unsigned num_instructions
= 0;
5660 foreach_block(block
, cfg
)
5661 num_instructions
+= block
->instructions
.length();
5663 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5665 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5666 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5667 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5672 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5674 * The needs_unlit_centroid_workaround ends up producing one of these per
5675 * channel of centroid input, so it's good to clean them up.
5677 * An assumption here is that nothing ever modifies the dispatched pixels
5678 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5679 * dictates that anyway.
5682 fs_visitor::opt_drop_redundant_mov_to_flags()
5684 bool flag_mov_found
[2] = {false};
5685 bool progress
= false;
5687 /* Instructions removed by this pass can only be added if this were true */
5688 if (!devinfo
->needs_unlit_centroid_workaround
)
5691 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5692 if (inst
->is_control_flow()) {
5693 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5694 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5695 if (!flag_mov_found
[inst
->flag_subreg
]) {
5696 flag_mov_found
[inst
->flag_subreg
] = true;
5698 inst
->remove(block
);
5701 } else if (inst
->flags_written()) {
5702 flag_mov_found
[inst
->flag_subreg
] = false;
5710 fs_visitor::optimize()
5712 /* Start by validating the shader we currently have. */
5715 /* bld is the common builder object pointing at the end of the program we
5716 * used to translate it into i965 IR. For the optimization and lowering
5717 * passes coming next, any code added after the end of the program without
5718 * having explicitly called fs_builder::at() clearly points at a mistake.
5719 * Ideally optimization passes wouldn't be part of the visitor so they
5720 * wouldn't have access to bld at all, but they do, so just in case some
5721 * pass forgets to ask for a location explicitly set it to NULL here to
5722 * make it trip. The dispatch width is initialized to a bogus value to
5723 * make sure that optimizations set the execution controls explicitly to
5724 * match the code they are manipulating instead of relying on the defaults.
5726 bld
= fs_builder(this, 64);
5728 assign_constant_locations();
5729 lower_constant_loads();
5733 split_virtual_grfs();
5736 #define OPT(pass, args...) ({ \
5738 bool this_progress = pass(args); \
5740 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5741 char filename[64]; \
5742 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5743 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5745 backend_shader::dump_instructions(filename); \
5750 progress = progress || this_progress; \
5754 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5756 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5757 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5759 backend_shader::dump_instructions(filename
);
5762 bool progress
= false;
5766 OPT(opt_drop_redundant_mov_to_flags
);
5773 OPT(remove_duplicate_mrf_writes
);
5777 OPT(opt_copy_propagate
);
5778 OPT(opt_predicated_break
, this);
5779 OPT(opt_cmod_propagation
);
5780 OPT(dead_code_eliminate
);
5781 OPT(opt_peephole_sel
);
5782 OPT(dead_control_flow_eliminate
, this);
5783 OPT(opt_register_renaming
);
5784 OPT(opt_saturate_propagation
);
5785 OPT(register_coalesce
);
5786 OPT(compute_to_mrf
);
5787 OPT(eliminate_find_live_channel
);
5789 OPT(compact_virtual_grfs
);
5795 if (OPT(lower_pack
)) {
5796 OPT(register_coalesce
);
5797 OPT(dead_code_eliminate
);
5800 if (OPT(lower_d2x
)) {
5801 OPT(opt_copy_propagate
);
5802 OPT(dead_code_eliminate
);
5805 OPT(lower_simd_width
);
5807 /* After SIMD lowering just in case we had to unroll the EOT send. */
5808 OPT(opt_sampler_eot
);
5810 OPT(lower_logical_sends
);
5813 OPT(opt_copy_propagate
);
5814 /* Only run after logical send lowering because it's easier to implement
5815 * in terms of physical sends.
5817 if (OPT(opt_zero_samples
))
5818 OPT(opt_copy_propagate
);
5819 /* Run after logical send lowering to give it a chance to CSE the
5820 * LOAD_PAYLOAD instructions created to construct the payloads of
5821 * e.g. texturing messages in cases where it wasn't possible to CSE the
5822 * whole logical instruction.
5825 OPT(register_coalesce
);
5826 OPT(compute_to_mrf
);
5827 OPT(dead_code_eliminate
);
5828 OPT(remove_duplicate_mrf_writes
);
5829 OPT(opt_peephole_sel
);
5832 OPT(opt_redundant_discard_jumps
);
5834 if (OPT(lower_load_payload
)) {
5835 split_virtual_grfs();
5836 OPT(register_coalesce
);
5837 OPT(compute_to_mrf
);
5838 OPT(dead_code_eliminate
);
5841 OPT(opt_combine_constants
);
5842 OPT(lower_integer_multiplication
);
5844 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5845 OPT(opt_cmod_propagation
);
5847 OPT(opt_copy_propagate
);
5848 OPT(dead_code_eliminate
);
5851 lower_uniform_pull_constant_loads();
5857 * Three source instruction must have a GRF/MRF destination register.
5858 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5861 fs_visitor::fixup_3src_null_dest()
5863 bool progress
= false;
5865 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5866 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5867 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5874 invalidate_live_intervals();
5878 fs_visitor::allocate_registers(bool allow_spilling
)
5880 bool allocated_without_spills
;
5882 static const enum instruction_scheduler_mode pre_modes
[] = {
5884 SCHEDULE_PRE_NON_LIFO
,
5888 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
5890 /* Try each scheduling heuristic to see if it can successfully register
5891 * allocate without spilling. They should be ordered by decreasing
5892 * performance but increasing likelihood of allocating.
5894 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5895 schedule_instructions(pre_modes
[i
]);
5898 assign_regs_trivial();
5899 allocated_without_spills
= true;
5901 allocated_without_spills
= assign_regs(false, spill_all
);
5903 if (allocated_without_spills
)
5907 if (!allocated_without_spills
) {
5908 if (!allow_spilling
)
5909 fail("Failure to register allocate and spilling is not allowed.");
5911 /* We assume that any spilling is worse than just dropping back to
5912 * SIMD8. There's probably actually some intermediate point where
5913 * SIMD16 with a couple of spills is still better.
5915 if (dispatch_width
> min_dispatch_width
) {
5916 fail("Failure to register allocate. Reduce number of "
5917 "live scalar values to avoid this.");
5919 compiler
->shader_perf_log(log_data
,
5920 "%s shader triggered register spilling. "
5921 "Try reducing the number of live scalar "
5922 "values to improve performance.\n",
5926 /* Since we're out of heuristics, just go spill registers until we
5927 * get an allocation.
5929 while (!assign_regs(true, spill_all
)) {
5935 /* This must come after all optimization and register allocation, since
5936 * it inserts dead code that happens to have side effects, and it does
5937 * so based on the actual physical registers in use.
5939 insert_gen4_send_dependency_workarounds();
5944 schedule_instructions(SCHEDULE_POST
);
5946 if (last_scratch
> 0) {
5947 unsigned max_scratch_size
= 2 * 1024 * 1024;
5949 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5951 if (stage
== MESA_SHADER_COMPUTE
) {
5952 if (devinfo
->is_haswell
) {
5953 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5954 * field documentation, Haswell supports a minimum of 2kB of
5955 * scratch space for compute shaders, unlike every other stage
5958 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
5959 } else if (devinfo
->gen
<= 7) {
5960 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5961 * field documentation, platforms prior to Haswell measure scratch
5962 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
5964 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
5965 max_scratch_size
= 12 * 1024;
5969 /* We currently only support up to 2MB of scratch space. If we
5970 * need to support more eventually, the documentation suggests
5971 * that we could allocate a larger buffer, and partition it out
5972 * ourselves. We'd just have to undo the hardware's address
5973 * calculation by subtracting (FFTID * Per Thread Scratch Space)
5974 * and then add FFTID * (Larger Per Thread Scratch Space).
5976 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
5977 * Thread Group Tracking > Local Memory/Scratch Space.
5979 assert(prog_data
->total_scratch
< max_scratch_size
);
5984 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5986 assert(stage
== MESA_SHADER_VERTEX
);
5990 if (shader_time_index
>= 0)
5991 emit_shader_time_begin();
5998 compute_clip_distance(clip_planes
);
6002 if (shader_time_index
>= 0)
6003 emit_shader_time_end();
6009 assign_curb_setup();
6010 assign_vs_urb_setup();
6012 fixup_3src_null_dest();
6013 allocate_registers(true);
6019 fs_visitor::run_tcs_single_patch()
6021 assert(stage
== MESA_SHADER_TESS_CTRL
);
6023 struct brw_tcs_prog_data
*tcs_prog_data
=
6024 (struct brw_tcs_prog_data
*) prog_data
;
6026 /* r1-r4 contain the ICP handles. */
6027 payload
.num_regs
= 5;
6029 if (shader_time_index
>= 0)
6030 emit_shader_time_begin();
6032 /* Initialize gl_InvocationID */
6033 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
6034 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6035 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
6036 bld
.MOV(channels_ud
, channels_uw
);
6038 if (tcs_prog_data
->instances
== 1) {
6039 invocation_id
= channels_ud
;
6041 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6043 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
6044 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6045 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6046 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
6047 brw_imm_ud(INTEL_MASK(23, 17)));
6048 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
6050 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
6053 /* Fix the disptach mask */
6054 if (nir
->info
.tcs
.vertices_out
% 8) {
6055 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
6056 brw_imm_ud(nir
->info
.tcs
.vertices_out
), BRW_CONDITIONAL_L
);
6057 bld
.IF(BRW_PREDICATE_NORMAL
);
6062 if (nir
->info
.tcs
.vertices_out
% 8) {
6063 bld
.emit(BRW_OPCODE_ENDIF
);
6066 /* Emit EOT write; set TR DS Cache bit */
6068 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6069 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6070 fs_reg(brw_imm_ud(0)),
6072 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6073 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6075 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6076 bld
.null_reg_ud(), payload
);
6080 if (shader_time_index
>= 0)
6081 emit_shader_time_end();
6090 assign_curb_setup();
6091 assign_tcs_single_patch_urb_setup();
6093 fixup_3src_null_dest();
6094 allocate_registers(true);
6100 fs_visitor::run_tes()
6102 assert(stage
== MESA_SHADER_TESS_EVAL
);
6104 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6105 payload
.num_regs
= 5;
6107 if (shader_time_index
>= 0)
6108 emit_shader_time_begin();
6117 if (shader_time_index
>= 0)
6118 emit_shader_time_end();
6124 assign_curb_setup();
6125 assign_tes_urb_setup();
6127 fixup_3src_null_dest();
6128 allocate_registers(true);
6134 fs_visitor::run_gs()
6136 assert(stage
== MESA_SHADER_GEOMETRY
);
6140 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6142 if (gs_compile
->control_data_header_size_bits
> 0) {
6143 /* Create a VGRF to store accumulated control data bits. */
6144 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6146 /* If we're outputting more than 32 control data bits, then EmitVertex()
6147 * will set control_data_bits to 0 after emitting the first vertex.
6148 * Otherwise, we need to initialize it to 0 here.
6150 if (gs_compile
->control_data_header_size_bits
<= 32) {
6151 const fs_builder abld
= bld
.annotate("initialize control data bits");
6152 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6156 if (shader_time_index
>= 0)
6157 emit_shader_time_begin();
6161 emit_gs_thread_end();
6163 if (shader_time_index
>= 0)
6164 emit_shader_time_end();
6173 assign_curb_setup();
6174 assign_gs_urb_setup();
6176 fixup_3src_null_dest();
6177 allocate_registers(true);
6183 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6185 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
6186 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6188 assert(stage
== MESA_SHADER_FRAGMENT
);
6190 if (devinfo
->gen
>= 6)
6191 setup_fs_payload_gen6();
6193 setup_fs_payload_gen4();
6197 } else if (do_rep_send
) {
6198 assert(dispatch_width
== 16);
6199 emit_repclear_shader();
6201 if (shader_time_index
>= 0)
6202 emit_shader_time_begin();
6204 calculate_urb_setup();
6205 if (nir
->info
.inputs_read
> 0 ||
6206 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
6207 if (devinfo
->gen
< 6)
6208 emit_interpolation_setup_gen4();
6210 emit_interpolation_setup_gen6();
6213 /* We handle discards by keeping track of the still-live pixels in f0.1.
6214 * Initialize it with the dispatched pixels.
6216 if (wm_prog_data
->uses_kill
) {
6217 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6218 discard_init
->flag_subreg
= 1;
6221 /* Generate FS IR for main(). (the visitor only descends into
6222 * functions called "main").
6229 if (wm_prog_data
->uses_kill
)
6230 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6232 if (wm_key
->alpha_test_func
)
6237 if (shader_time_index
>= 0)
6238 emit_shader_time_end();
6244 assign_curb_setup();
6247 fixup_3src_null_dest();
6248 allocate_registers(allow_spilling
);
6258 fs_visitor::run_cs()
6260 assert(stage
== MESA_SHADER_COMPUTE
);
6264 if (shader_time_index
>= 0)
6265 emit_shader_time_begin();
6267 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6268 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6269 const fs_builder abld
= bld
.exec_all().group(1, 0);
6270 abld
.MOV(retype(suboffset(brw_sr0_reg(), 1), BRW_REGISTER_TYPE_UW
),
6271 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6279 emit_cs_terminate();
6281 if (shader_time_index
>= 0)
6282 emit_shader_time_end();
6288 assign_curb_setup();
6290 fixup_3src_null_dest();
6291 allocate_registers(true);
6300 * Return a bitfield where bit n is set if barycentric interpolation mode n
6301 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6303 * We examine the load_barycentric intrinsics rather than looking at input
6304 * variables so that we catch interpolateAtCentroid() messages too, which
6305 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6308 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
6309 const nir_shader
*shader
)
6311 unsigned barycentric_interp_modes
= 0;
6313 nir_foreach_function(f
, shader
) {
6317 nir_foreach_block(block
, f
->impl
) {
6318 nir_foreach_instr(instr
, block
) {
6319 if (instr
->type
!= nir_instr_type_intrinsic
)
6322 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6323 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6326 /* Ignore WPOS; it doesn't require interpolation. */
6327 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6330 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6331 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
6332 nir_intrinsic_interp_mode(intrin
);
6333 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
6334 enum brw_barycentric_mode bary
=
6335 brw_barycentric_mode(interp
, bary_op
);
6337 barycentric_interp_modes
|= 1 << bary
;
6339 if (devinfo
->needs_unlit_centroid_workaround
&&
6340 bary_op
== nir_intrinsic_load_barycentric_centroid
)
6341 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
6346 return barycentric_interp_modes
;
6350 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6351 const nir_shader
*shader
)
6353 prog_data
->flat_inputs
= 0;
6355 nir_foreach_variable(var
, &shader
->inputs
) {
6356 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6358 if (input_index
< 0)
6362 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6363 prog_data
->flat_inputs
|= (1 << input_index
);
6368 computed_depth_mode(const nir_shader
*shader
)
6370 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6371 switch (shader
->info
.fs
.depth_layout
) {
6372 case FRAG_DEPTH_LAYOUT_NONE
:
6373 case FRAG_DEPTH_LAYOUT_ANY
:
6374 return BRW_PSCDEPTH_ON
;
6375 case FRAG_DEPTH_LAYOUT_GREATER
:
6376 return BRW_PSCDEPTH_ON_GE
;
6377 case FRAG_DEPTH_LAYOUT_LESS
:
6378 return BRW_PSCDEPTH_ON_LE
;
6379 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6380 return BRW_PSCDEPTH_OFF
;
6383 return BRW_PSCDEPTH_OFF
;
6387 * Move load_interpolated_input with simple (payload-based) barycentric modes
6388 * to the top of the program so we don't emit multiple PLNs for the same input.
6390 * This works around CSE not being able to handle non-dominating cases
6396 * interpolate the same exact input
6399 * This should be replaced by global value numbering someday.
6402 move_interpolation_to_top(nir_shader
*nir
)
6404 nir_foreach_function(f
, nir
) {
6408 nir_block
*top
= nir_start_block(f
->impl
);
6409 exec_node
*cursor_node
= NULL
;
6411 nir_foreach_block(block
, f
->impl
) {
6415 nir_foreach_instr_safe(instr
, block
) {
6416 if (instr
->type
!= nir_instr_type_intrinsic
)
6419 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6420 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6422 nir_intrinsic_instr
*bary_intrinsic
=
6423 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6424 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
6426 /* Leave interpolateAtSample/Offset() where they are. */
6427 if (op
== nir_intrinsic_load_barycentric_at_sample
||
6428 op
== nir_intrinsic_load_barycentric_at_offset
)
6431 nir_instr
*move
[3] = {
6432 &bary_intrinsic
->instr
,
6433 intrin
->src
[1].ssa
->parent_instr
,
6437 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
6438 if (move
[i
]->block
!= top
) {
6439 move
[i
]->block
= top
;
6440 exec_node_remove(&move
[i
]->node
);
6442 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
6444 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
6446 cursor_node
= &move
[i
]->node
;
6451 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6452 ((unsigned) nir_metadata_block_index
|
6453 (unsigned) nir_metadata_dominance
));
6458 * Apply default interpolation settings to FS inputs which don't specify any.
6461 brw_nir_set_default_interpolation(const struct gen_device_info
*devinfo
,
6462 struct nir_shader
*nir
,
6463 bool api_flat_shade
,
6464 bool per_sample_interpolation
)
6466 assert(nir
->stage
== MESA_SHADER_FRAGMENT
);
6468 nir_foreach_variable(var
, &nir
->inputs
) {
6469 /* Apply default interpolation mode.
6471 * Everything defaults to smooth except for the legacy GL color
6472 * built-in variables, which might be flat depending on API state.
6474 if (var
->data
.interpolation
== INTERP_MODE_NONE
) {
6475 const bool flat
= api_flat_shade
&&
6476 (var
->data
.location
== VARYING_SLOT_COL0
||
6477 var
->data
.location
== VARYING_SLOT_COL1
);
6479 var
->data
.interpolation
= flat
? INTERP_MODE_FLAT
6480 : INTERP_MODE_SMOOTH
;
6483 /* Apply 'sample' if necessary for API state. */
6484 if (per_sample_interpolation
&&
6485 var
->data
.interpolation
!= INTERP_MODE_FLAT
) {
6486 var
->data
.centroid
= false;
6487 var
->data
.sample
= true;
6490 /* On Ironlake and below, there is only one interpolation mode.
6491 * Centroid interpolation doesn't mean anything on this hardware --
6492 * there is no multisampling.
6494 if (devinfo
->gen
< 6) {
6495 var
->data
.centroid
= false;
6496 var
->data
.sample
= false;
6502 * Demote per-sample barycentric intrinsics to centroid.
6504 * Useful when rendering to a non-multisampled buffer.
6507 demote_sample_qualifiers(nir_shader
*nir
)
6509 nir_foreach_function(f
, nir
) {
6514 nir_builder_init(&b
, f
->impl
);
6516 nir_foreach_block(block
, f
->impl
) {
6517 nir_foreach_instr_safe(instr
, block
) {
6518 if (instr
->type
!= nir_instr_type_intrinsic
)
6521 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6522 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
6523 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
6526 b
.cursor
= nir_before_instr(instr
);
6527 nir_ssa_def
*centroid
=
6528 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
6529 nir_intrinsic_interp_mode(intrin
));
6530 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
6531 nir_src_for_ssa(centroid
));
6532 nir_instr_remove(instr
);
6536 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6537 ((unsigned) nir_metadata_block_index
|
6538 (unsigned) nir_metadata_dominance
));
6543 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6545 const struct brw_wm_prog_key
*key
,
6546 struct brw_wm_prog_data
*prog_data
,
6547 const nir_shader
*src_shader
,
6548 struct gl_program
*prog
,
6549 int shader_time_index8
, int shader_time_index16
,
6550 bool allow_spilling
,
6552 unsigned *final_assembly_size
,
6555 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6556 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6558 brw_nir_set_default_interpolation(compiler
->devinfo
, shader
,
6559 key
->flat_shade
, key
->persample_interp
);
6560 brw_nir_lower_fs_inputs(shader
);
6561 brw_nir_lower_fs_outputs(shader
);
6562 if (!key
->multisample_fbo
)
6563 NIR_PASS_V(shader
, demote_sample_qualifiers
);
6564 NIR_PASS_V(shader
, move_interpolation_to_top
);
6565 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6567 /* key->alpha_test_func means simulating alpha testing via discards,
6568 * so the shader definitely kills pixels.
6570 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
6571 prog_data
->uses_omask
= key
->multisample_fbo
&&
6572 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6573 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6574 prog_data
->computed_stencil
=
6575 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6577 prog_data
->persample_dispatch
=
6578 key
->multisample_fbo
&&
6579 (key
->persample_interp
||
6580 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6581 SYSTEM_BIT_SAMPLE_POS
)) ||
6582 shader
->info
.fs
.uses_sample_qualifier
||
6583 shader
->info
.outputs_read
);
6585 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
6587 prog_data
->barycentric_interp_modes
=
6588 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
6590 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6591 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6592 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6594 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6595 &prog_data
->base
, prog
, shader
, 8,
6596 shader_time_index8
);
6597 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6599 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6602 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6604 simd8_grf_start
= v8
.payload
.num_regs
;
6605 simd8_grf_used
= v8
.grf_used
;
6608 if (v8
.max_dispatch_width
>= 16 &&
6609 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6610 /* Try a SIMD16 compile */
6611 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6612 &prog_data
->base
, prog
, shader
, 16,
6613 shader_time_index16
);
6614 v16
.import_uniforms(&v8
);
6615 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6616 compiler
->shader_perf_log(log_data
,
6617 "SIMD16 shader failed to compile: %s",
6620 simd16_cfg
= v16
.cfg
;
6621 simd16_grf_start
= v16
.payload
.num_regs
;
6622 simd16_grf_used
= v16
.grf_used
;
6626 /* When the caller requests a repclear shader, they want SIMD16-only */
6630 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6631 * at the top to select the shader. We've never implemented that.
6632 * Instead, we just give them exactly one shader and we pick the widest one
6635 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6638 if (prog_data
->persample_dispatch
) {
6639 /* Starting with SandyBridge (where we first get MSAA), the different
6640 * pixel dispatch combinations are grouped into classifications A
6641 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6642 * generations, the only configurations supporting persample dispatch
6643 * are are this in which only one dispatch width is enabled.
6645 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6646 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6648 if (compiler
->devinfo
->gen
== 6 &&
6649 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6651 } else if (simd16_cfg
) {
6656 /* We have to compute the flat inputs after the visitor is finished running
6657 * because it relies on prog_data->urb_setup which is computed in
6658 * fs_visitor::calculate_urb_setup().
6660 brw_compute_flat_inputs(prog_data
, shader
);
6662 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6663 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6664 MESA_SHADER_FRAGMENT
);
6666 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6667 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6668 shader
->info
.label
? shader
->info
.label
:
6670 shader
->info
.name
));
6674 prog_data
->dispatch_8
= true;
6675 g
.generate_code(simd8_cfg
, 8);
6676 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6677 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6680 prog_data
->dispatch_16
= true;
6681 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6682 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6683 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6685 } else if (simd16_cfg
) {
6686 prog_data
->dispatch_16
= true;
6687 g
.generate_code(simd16_cfg
, 16);
6688 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6689 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6692 return g
.get_assembly(final_assembly_size
);
6696 fs_visitor::emit_cs_work_group_id_setup()
6698 assert(stage
== MESA_SHADER_COMPUTE
);
6700 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6702 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6703 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6704 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6706 bld
.MOV(*reg
, r0_1
);
6707 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6708 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6714 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
6716 block
->dwords
= dwords
;
6717 block
->regs
= DIV_ROUND_UP(dwords
, 8);
6718 block
->size
= block
->regs
* 32;
6722 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
6723 struct brw_cs_prog_data
*cs_prog_data
)
6725 const struct brw_stage_prog_data
*prog_data
=
6726 (struct brw_stage_prog_data
*) cs_prog_data
;
6727 bool fill_thread_id
=
6728 cs_prog_data
->thread_local_id_index
>= 0 &&
6729 cs_prog_data
->thread_local_id_index
< (int)prog_data
->nr_params
;
6730 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
6732 /* The thread ID should be stored in the last param dword */
6733 assert(prog_data
->nr_params
> 0 || !fill_thread_id
);
6734 assert(!fill_thread_id
||
6735 cs_prog_data
->thread_local_id_index
==
6736 (int)prog_data
->nr_params
- 1);
6738 unsigned cross_thread_dwords
, per_thread_dwords
;
6739 if (!cross_thread_supported
) {
6740 cross_thread_dwords
= 0u;
6741 per_thread_dwords
= prog_data
->nr_params
;
6742 } else if (fill_thread_id
) {
6743 /* Fill all but the last register with cross-thread payload */
6744 cross_thread_dwords
= 8 * (cs_prog_data
->thread_local_id_index
/ 8);
6745 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
6746 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
6748 /* Fill all data using cross-thread payload */
6749 cross_thread_dwords
= prog_data
->nr_params
;
6750 per_thread_dwords
= 0u;
6753 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
6754 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
6756 unsigned total_dwords
=
6757 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
6758 cs_prog_data
->push
.cross_thread
.size
) / 4;
6759 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
6761 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
6762 cs_prog_data
->push
.per_thread
.size
== 0);
6763 assert(cs_prog_data
->push
.cross_thread
.dwords
+
6764 cs_prog_data
->push
.per_thread
.dwords
==
6765 prog_data
->nr_params
);
6769 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
6771 cs_prog_data
->simd_size
= size
;
6772 unsigned group_size
= cs_prog_data
->local_size
[0] *
6773 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
6774 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
6778 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6780 const struct brw_cs_prog_key
*key
,
6781 struct brw_cs_prog_data
*prog_data
,
6782 const nir_shader
*src_shader
,
6783 int shader_time_index
,
6784 unsigned *final_assembly_size
,
6787 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6788 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6790 brw_nir_lower_cs_shared(shader
);
6791 prog_data
->base
.total_shared
+= shader
->num_shared
;
6793 /* Now that we cloned the nir_shader, we can update num_uniforms based on
6794 * the thread_local_id_index.
6796 assert(prog_data
->thread_local_id_index
>= 0);
6797 shader
->num_uniforms
=
6798 MAX2(shader
->num_uniforms
,
6799 (unsigned)4 * (prog_data
->thread_local_id_index
+ 1));
6801 brw_nir_lower_intrinsics(shader
, &prog_data
->base
);
6802 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6804 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
6805 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
6806 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
6807 unsigned local_workgroup_size
=
6808 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
6809 shader
->info
.cs
.local_size
[2];
6811 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
6812 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
6815 const char *fail_msg
= NULL
;
6817 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6819 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6820 NULL
, /* Never used in core profile */
6821 shader
, 8, shader_time_index
);
6822 if (simd_required
<= 8) {
6824 fail_msg
= v8
.fail_msg
;
6827 cs_set_simd_size(prog_data
, 8);
6828 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6829 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
6833 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6834 NULL
, /* Never used in core profile */
6835 shader
, 16, shader_time_index
);
6836 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6837 !fail_msg
&& v8
.max_dispatch_width
>= 16 &&
6838 simd_required
<= 16) {
6839 /* Try a SIMD16 compile */
6840 if (simd_required
<= 8)
6841 v16
.import_uniforms(&v8
);
6842 if (!v16
.run_cs()) {
6843 compiler
->shader_perf_log(log_data
,
6844 "SIMD16 shader failed to compile: %s",
6848 "Couldn't generate SIMD16 program and not "
6849 "enough threads for SIMD8";
6853 cs_set_simd_size(prog_data
, 16);
6854 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6855 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
6859 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6860 NULL
, /* Never used in core profile */
6861 shader
, 32, shader_time_index
);
6862 if (!fail_msg
&& v8
.max_dispatch_width
>= 32 &&
6863 (simd_required
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
6864 /* Try a SIMD32 compile */
6865 if (simd_required
<= 8)
6866 v32
.import_uniforms(&v8
);
6867 else if (simd_required
<= 16)
6868 v32
.import_uniforms(&v16
);
6870 if (!v32
.run_cs()) {
6871 compiler
->shader_perf_log(log_data
,
6872 "SIMD32 shader failed to compile: %s",
6876 "Couldn't generate SIMD32 program and not "
6877 "enough threads for SIMD16";
6881 cs_set_simd_size(prog_data
, 32);
6882 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6886 if (unlikely(cfg
== NULL
)) {
6889 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6894 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6895 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6896 MESA_SHADER_COMPUTE
);
6897 if (INTEL_DEBUG
& DEBUG_CS
) {
6898 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6899 shader
->info
.label
? shader
->info
.label
:
6902 g
.enable_debug(name
);
6905 g
.generate_code(cfg
, prog_data
->simd_size
);
6907 return g
.get_assembly(final_assembly_size
);