2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "main/hash_table.h"
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/fbobject.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/register_allocate.h"
42 #include "program/sampler.h"
43 #include "program/hash_table.h"
44 #include "brw_context.h"
49 #include "brw_dead_control_flow.h"
50 #include "main/uniforms.h"
51 #include "brw_fs_live_variables.h"
52 #include "glsl/glsl_types.h"
57 memset(this, 0, sizeof(*this));
58 this->opcode
= BRW_OPCODE_NOP
;
59 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
61 this->dst
= reg_undef
;
62 this->src
[0] = reg_undef
;
63 this->src
[1] = reg_undef
;
64 this->src
[2] = reg_undef
;
66 /* This will be the case for almost all instructions. */
67 this->regs_written
= 1;
75 fs_inst::fs_inst(enum opcode opcode
)
78 this->opcode
= opcode
;
81 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
)
84 this->opcode
= opcode
;
88 assert(dst
.reg_offset
>= 0);
91 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
)
94 this->opcode
= opcode
;
99 assert(dst
.reg_offset
>= 0);
100 if (src
[0].file
== GRF
)
101 assert(src
[0].reg_offset
>= 0);
104 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
107 this->opcode
= opcode
;
113 assert(dst
.reg_offset
>= 0);
114 if (src
[0].file
== GRF
)
115 assert(src
[0].reg_offset
>= 0);
116 if (src
[1].file
== GRF
)
117 assert(src
[1].reg_offset
>= 0);
120 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
,
121 fs_reg src0
, fs_reg src1
, fs_reg src2
)
124 this->opcode
= opcode
;
131 assert(dst
.reg_offset
>= 0);
132 if (src
[0].file
== GRF
)
133 assert(src
[0].reg_offset
>= 0);
134 if (src
[1].file
== GRF
)
135 assert(src
[1].reg_offset
>= 0);
136 if (src
[2].file
== GRF
)
137 assert(src
[2].reg_offset
>= 0);
142 fs_visitor::op(fs_reg dst, fs_reg src0) \
144 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0); \
149 fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1) \
151 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
156 fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2) \
158 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2);\
189 /** Gen4 predicated IF. */
191 fs_visitor::IF(uint32_t predicate
)
193 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
);
194 inst
->predicate
= predicate
;
198 /** Gen6 IF with embedded comparison. */
200 fs_visitor::IF(fs_reg src0
, fs_reg src1
, uint32_t condition
)
202 assert(brw
->gen
== 6);
203 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
,
204 reg_null_d
, src0
, src1
);
205 inst
->conditional_mod
= condition
;
210 * CMP: Sets the low bit of the destination channels with the result
211 * of the comparison, while the upper bits are undefined, and updates
212 * the flag register with the packed 16 bits of the result.
215 fs_visitor::CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
, uint32_t condition
)
219 /* Take the instruction:
221 * CMP null<d> src0<f> src1<f>
223 * Original gen4 does type conversion to the destination type before
224 * comparison, producing garbage results for floating point comparisons.
225 * gen5 does the comparison on the execution type (resolved source types),
226 * so dst type doesn't matter. gen6 does comparison and then uses the
227 * result as if it was the dst type with no conversion, which happens to
228 * mostly work out for float-interpreted-as-int since our comparisons are
232 dst
.type
= src0
.type
;
233 if (dst
.file
== HW_REG
)
234 dst
.fixed_hw_reg
.type
= dst
.type
;
237 resolve_ud_negate(&src0
);
238 resolve_ud_negate(&src1
);
240 inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_CMP
, dst
, src0
, src1
);
241 inst
->conditional_mod
= condition
;
247 fs_visitor::VARYING_PULL_CONSTANT_LOAD(fs_reg dst
, fs_reg surf_index
,
248 fs_reg varying_offset
,
249 uint32_t const_offset
)
251 exec_list instructions
;
254 /* We have our constant surface use a pitch of 4 bytes, so our index can
255 * be any component of a vector, and then we load 4 contiguous
256 * components starting from that.
258 * We break down the const_offset to a portion added to the variable
259 * offset and a portion done using reg_offset, which means that if you
260 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
261 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
262 * CSE can later notice that those loads are all the same and eliminate
263 * the redundant ones.
265 fs_reg vec4_offset
= fs_reg(this, glsl_type::int_type
);
266 instructions
.push_tail(ADD(vec4_offset
,
267 varying_offset
, const_offset
& ~3));
270 if (brw
->gen
== 4 && dispatch_width
== 8) {
271 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
272 * u, v, r) as parameters, or we can just use the SIMD16 message
273 * consisting of (header, u). We choose the second, at the cost of a
274 * longer return length.
281 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
283 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
284 fs_reg vec4_result
= fs_reg(GRF
, virtual_grf_alloc(4 * scale
), dst
.type
);
285 inst
= new(mem_ctx
) fs_inst(op
, vec4_result
, surf_index
, vec4_offset
);
286 inst
->regs_written
= 4 * scale
;
287 instructions
.push_tail(inst
);
291 inst
->header_present
= true;
295 inst
->mlen
= 1 + dispatch_width
/ 8;
298 vec4_result
.reg_offset
+= (const_offset
& 3) * scale
;
299 instructions
.push_tail(MOV(dst
, vec4_result
));
305 * A helper for MOV generation for fixing up broken hardware SEND dependency
309 fs_visitor::DEP_RESOLVE_MOV(int grf
)
311 fs_inst
*inst
= MOV(brw_null_reg(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
314 inst
->annotation
= "send dependency resolve";
316 /* The caller always wants uncompressed to emit the minimal extra
317 * dependencies, and to avoid having to deal with aligning its regs to 2.
319 inst
->force_uncompressed
= true;
325 fs_inst::equals(fs_inst
*inst
)
327 return (opcode
== inst
->opcode
&&
328 dst
.equals(inst
->dst
) &&
329 src
[0].equals(inst
->src
[0]) &&
330 src
[1].equals(inst
->src
[1]) &&
331 src
[2].equals(inst
->src
[2]) &&
332 saturate
== inst
->saturate
&&
333 predicate
== inst
->predicate
&&
334 conditional_mod
== inst
->conditional_mod
&&
335 mlen
== inst
->mlen
&&
336 base_mrf
== inst
->base_mrf
&&
337 sampler
== inst
->sampler
&&
338 target
== inst
->target
&&
340 header_present
== inst
->header_present
&&
341 shadow_compare
== inst
->shadow_compare
&&
342 offset
== inst
->offset
);
346 fs_inst::overwrites_reg(const fs_reg
®
)
348 return (reg
.file
== dst
.file
&&
349 reg
.reg
== dst
.reg
&&
350 reg
.reg_offset
>= dst
.reg_offset
&&
351 reg
.reg_offset
< dst
.reg_offset
+ regs_written
);
355 fs_inst::is_send_from_grf()
357 return (opcode
== FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
||
358 opcode
== SHADER_OPCODE_SHADER_TIME_ADD
||
359 (opcode
== FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
&&
360 src
[1].file
== GRF
) ||
361 (is_tex() && src
[0].file
== GRF
));
365 fs_visitor::can_do_source_mods(fs_inst
*inst
)
367 if (brw
->gen
== 6 && inst
->is_math())
370 if (inst
->is_send_from_grf())
373 if (!inst
->can_do_source_mods())
382 memset(this, 0, sizeof(*this));
386 /** Generic unset register constructor. */
390 this->file
= BAD_FILE
;
393 /** Immediate value constructor. */
394 fs_reg::fs_reg(float f
)
398 this->type
= BRW_REGISTER_TYPE_F
;
402 /** Immediate value constructor. */
403 fs_reg::fs_reg(int32_t i
)
407 this->type
= BRW_REGISTER_TYPE_D
;
411 /** Immediate value constructor. */
412 fs_reg::fs_reg(uint32_t u
)
416 this->type
= BRW_REGISTER_TYPE_UD
;
420 /** Fixed brw_reg. */
421 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
425 this->fixed_hw_reg
= fixed_hw_reg
;
426 this->type
= fixed_hw_reg
.type
;
430 fs_reg::equals(const fs_reg
&r
) const
432 return (file
== r
.file
&&
434 reg_offset
== r
.reg_offset
&&
436 negate
== r
.negate
&&
438 !reladdr
&& !r
.reladdr
&&
439 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
440 sizeof(fixed_hw_reg
)) == 0 &&
446 fs_reg::retype(uint32_t type
)
448 fs_reg result
= *this;
454 fs_reg::is_zero() const
459 return type
== BRW_REGISTER_TYPE_F
? imm
.f
== 0.0 : imm
.i
== 0;
463 fs_reg::is_one() const
468 return type
== BRW_REGISTER_TYPE_F
? imm
.f
== 1.0 : imm
.i
== 1;
472 fs_reg::is_null() const
474 return file
== HW_REG
&&
475 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
476 fixed_hw_reg
.nr
== BRW_ARF_NULL
;
480 fs_reg::is_valid_3src() const
482 return file
== GRF
|| file
== UNIFORM
;
486 fs_visitor::type_size(const struct glsl_type
*type
)
488 unsigned int size
, i
;
490 switch (type
->base_type
) {
493 case GLSL_TYPE_FLOAT
:
495 return type
->components();
496 case GLSL_TYPE_ARRAY
:
497 return type_size(type
->fields
.array
) * type
->length
;
498 case GLSL_TYPE_STRUCT
:
500 for (i
= 0; i
< type
->length
; i
++) {
501 size
+= type_size(type
->fields
.structure
[i
].type
);
504 case GLSL_TYPE_SAMPLER
:
505 /* Samplers take up no register space, since they're baked in at
509 case GLSL_TYPE_ATOMIC_UINT
:
512 case GLSL_TYPE_ERROR
:
513 case GLSL_TYPE_INTERFACE
:
514 assert(!"not reached");
522 fs_visitor::get_timestamp()
524 assert(brw
->gen
>= 7);
526 fs_reg ts
= fs_reg(retype(brw_vec1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
529 BRW_REGISTER_TYPE_UD
));
531 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
533 fs_inst
*mov
= emit(MOV(dst
, ts
));
534 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
535 * even if it's not enabled in the dispatch.
537 mov
->force_writemask_all
= true;
538 mov
->force_uncompressed
= true;
540 /* The caller wants the low 32 bits of the timestamp. Since it's running
541 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
542 * which is plenty of time for our purposes. It is identical across the
543 * EUs, but since it's tracking GPU core speed it will increment at a
544 * varying rate as render P-states change.
546 * The caller could also check if render P-states have changed (or anything
547 * else that might disrupt timing) by setting smear to 2 and checking if
548 * that field is != 0.
556 fs_visitor::emit_shader_time_begin()
558 current_annotation
= "shader time start";
559 shader_start_time
= get_timestamp();
563 fs_visitor::emit_shader_time_end()
565 current_annotation
= "shader time end";
567 enum shader_time_shader_type type
, written_type
, reset_type
;
568 if (dispatch_width
== 8) {
570 written_type
= ST_FS8_WRITTEN
;
571 reset_type
= ST_FS8_RESET
;
573 assert(dispatch_width
== 16);
575 written_type
= ST_FS16_WRITTEN
;
576 reset_type
= ST_FS16_RESET
;
579 fs_reg shader_end_time
= get_timestamp();
581 /* Check that there weren't any timestamp reset events (assuming these
582 * were the only two timestamp reads that happened).
584 fs_reg reset
= shader_end_time
;
586 fs_inst
*test
= emit(AND(reg_null_d
, reset
, fs_reg(1u)));
587 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
588 emit(IF(BRW_PREDICATE_NORMAL
));
590 push_force_uncompressed();
591 fs_reg start
= shader_start_time
;
593 fs_reg diff
= fs_reg(this, glsl_type::uint_type
);
594 emit(ADD(diff
, start
, shader_end_time
));
596 /* If there were no instructions between the two timestamp gets, the diff
597 * is 2 cycles. Remove that overhead, so I can forget about that when
598 * trying to determine the time taken for single instructions.
600 emit(ADD(diff
, diff
, fs_reg(-2u)));
602 emit_shader_time_write(type
, diff
);
603 emit_shader_time_write(written_type
, fs_reg(1u));
604 emit(BRW_OPCODE_ELSE
);
605 emit_shader_time_write(reset_type
, fs_reg(1u));
606 emit(BRW_OPCODE_ENDIF
);
608 pop_force_uncompressed();
612 fs_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
615 int shader_time_index
=
616 brw_get_shader_time_index(brw
, shader_prog
, &fp
->Base
, type
);
617 fs_reg offset
= fs_reg(shader_time_index
* SHADER_TIME_STRIDE
);
620 if (dispatch_width
== 8)
621 payload
= fs_reg(this, glsl_type::uvec2_type
);
623 payload
= fs_reg(this, glsl_type::uint_type
);
625 emit(fs_inst(SHADER_OPCODE_SHADER_TIME_ADD
,
626 fs_reg(), payload
, offset
, value
));
630 fs_visitor::fail(const char *format
, ...)
640 va_start(va
, format
);
641 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
643 msg
= ralloc_asprintf(mem_ctx
, "FS compile failed: %s\n", msg
);
645 this->fail_msg
= msg
;
647 if (INTEL_DEBUG
& DEBUG_WM
) {
648 fprintf(stderr
, "%s", msg
);
653 fs_visitor::emit(enum opcode opcode
)
655 return emit(fs_inst(opcode
));
659 fs_visitor::emit(enum opcode opcode
, fs_reg dst
)
661 return emit(fs_inst(opcode
, dst
));
665 fs_visitor::emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
)
667 return emit(fs_inst(opcode
, dst
, src0
));
671 fs_visitor::emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
673 return emit(fs_inst(opcode
, dst
, src0
, src1
));
677 fs_visitor::emit(enum opcode opcode
, fs_reg dst
,
678 fs_reg src0
, fs_reg src1
, fs_reg src2
)
680 return emit(fs_inst(opcode
, dst
, src0
, src1
, src2
));
684 fs_visitor::push_force_uncompressed()
686 force_uncompressed_stack
++;
690 fs_visitor::pop_force_uncompressed()
692 force_uncompressed_stack
--;
693 assert(force_uncompressed_stack
>= 0);
697 * Returns true if the instruction has a flag that means it won't
698 * update an entire destination register.
700 * For example, dead code elimination and live variable analysis want to know
701 * when a write to a variable screens off any preceding values that were in
705 fs_inst::is_partial_write()
707 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
708 this->force_uncompressed
||
709 this->force_sechalf
);
713 fs_inst::regs_read(fs_visitor
*v
, int arg
)
715 if (is_tex() && arg
== 0 && src
[0].file
== GRF
) {
716 if (v
->dispatch_width
== 16)
717 return (mlen
+ 1) / 2;
725 fs_inst::reads_flag()
731 fs_inst::writes_flag()
733 return (conditional_mod
&& opcode
!= BRW_OPCODE_SEL
) ||
734 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
738 * Returns how many MRFs an FS opcode will write over.
740 * Note that this is not the 0 or 1 implied writes in an actual gen
741 * instruction -- the FS opcodes often generate MOVs in addition.
744 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
749 if (inst
->base_mrf
== -1)
752 switch (inst
->opcode
) {
753 case SHADER_OPCODE_RCP
:
754 case SHADER_OPCODE_RSQ
:
755 case SHADER_OPCODE_SQRT
:
756 case SHADER_OPCODE_EXP2
:
757 case SHADER_OPCODE_LOG2
:
758 case SHADER_OPCODE_SIN
:
759 case SHADER_OPCODE_COS
:
760 return 1 * dispatch_width
/ 8;
761 case SHADER_OPCODE_POW
:
762 case SHADER_OPCODE_INT_QUOTIENT
:
763 case SHADER_OPCODE_INT_REMAINDER
:
764 return 2 * dispatch_width
/ 8;
765 case SHADER_OPCODE_TEX
:
767 case SHADER_OPCODE_TXD
:
768 case SHADER_OPCODE_TXF
:
769 case SHADER_OPCODE_TXF_MS
:
770 case SHADER_OPCODE_TXF_MCS
:
771 case SHADER_OPCODE_TG4
:
772 case SHADER_OPCODE_TG4_OFFSET
:
773 case SHADER_OPCODE_TXL
:
774 case SHADER_OPCODE_TXS
:
775 case SHADER_OPCODE_LOD
:
777 case FS_OPCODE_FB_WRITE
:
779 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
780 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
782 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
784 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
786 case SHADER_OPCODE_UNTYPED_ATOMIC
:
787 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
790 assert(!"not reached");
796 fs_visitor::virtual_grf_alloc(int size
)
798 if (virtual_grf_array_size
<= virtual_grf_count
) {
799 if (virtual_grf_array_size
== 0)
800 virtual_grf_array_size
= 16;
802 virtual_grf_array_size
*= 2;
803 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
804 virtual_grf_array_size
);
806 virtual_grf_sizes
[virtual_grf_count
] = size
;
807 return virtual_grf_count
++;
810 /** Fixed HW reg constructor. */
811 fs_reg::fs_reg(enum register_file file
, int reg
)
816 this->type
= BRW_REGISTER_TYPE_F
;
819 /** Fixed HW reg constructor. */
820 fs_reg::fs_reg(enum register_file file
, int reg
, uint32_t type
)
828 /** Automatic reg constructor. */
829 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
834 this->reg
= v
->virtual_grf_alloc(v
->type_size(type
));
835 this->reg_offset
= 0;
836 this->type
= brw_type_for_base_type(type
);
840 fs_visitor::variable_storage(ir_variable
*var
)
842 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
846 import_uniforms_callback(const void *key
,
850 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
851 const fs_reg
*reg
= (const fs_reg
*)data
;
853 if (reg
->file
!= UNIFORM
)
856 hash_table_insert(dst_ht
, data
, key
);
859 /* For 16-wide, we need to follow from the uniform setup of 8-wide dispatch.
860 * This brings in those uniform definitions
863 fs_visitor::import_uniforms(fs_visitor
*v
)
865 hash_table_call_foreach(v
->variable_ht
,
866 import_uniforms_callback
,
868 this->params_remap
= v
->params_remap
;
869 this->nr_params_remap
= v
->nr_params_remap
;
872 /* Our support for uniforms is piggy-backed on the struct
873 * gl_fragment_program, because that's where the values actually
874 * get stored, rather than in some global gl_shader_program uniform
878 fs_visitor::setup_uniform_values(ir_variable
*ir
)
880 int namelen
= strlen(ir
->name
);
882 /* The data for our (non-builtin) uniforms is stored in a series of
883 * gl_uniform_driver_storage structs for each subcomponent that
884 * glGetUniformLocation() could name. We know it's been set up in the same
885 * order we'd walk the type, so walk the list of storage and find anything
886 * with our name, or the prefix of a component that starts with our name.
888 unsigned params_before
= c
->prog_data
.nr_params
;
889 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
890 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
892 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
893 (storage
->name
[namelen
] != 0 &&
894 storage
->name
[namelen
] != '.' &&
895 storage
->name
[namelen
] != '[')) {
899 unsigned slots
= storage
->type
->component_slots();
900 if (storage
->array_elements
)
901 slots
*= storage
->array_elements
;
903 for (unsigned i
= 0; i
< slots
; i
++) {
904 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
905 &storage
->storage
[i
].f
;
909 /* Make sure we actually initialized the right amount of stuff here. */
910 assert(params_before
+ ir
->type
->component_slots() ==
911 c
->prog_data
.nr_params
);
916 /* Our support for builtin uniforms is even scarier than non-builtin.
917 * It sits on top of the PROG_STATE_VAR parameters that are
918 * automatically updated from GL context state.
921 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
923 const ir_state_slot
*const slots
= ir
->state_slots
;
924 assert(ir
->state_slots
!= NULL
);
926 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
927 /* This state reference has already been setup by ir_to_mesa, but we'll
928 * get the same index back here.
930 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
931 (gl_state_index
*)slots
[i
].tokens
);
933 /* Add each of the unique swizzles of the element as a parameter.
934 * This'll end up matching the expected layout of the
935 * array/matrix/structure we're trying to fill in.
938 for (unsigned int j
= 0; j
< 4; j
++) {
939 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
940 if (swiz
== last_swiz
)
944 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
945 &fp
->Base
.Parameters
->ParameterValues
[index
][swiz
].f
;
951 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
953 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
955 bool flip
= !ir
->data
.origin_upper_left
^ c
->key
.render_to_fbo
;
958 if (ir
->data
.pixel_center_integer
) {
959 emit(MOV(wpos
, this->pixel_x
));
961 emit(ADD(wpos
, this->pixel_x
, fs_reg(0.5f
)));
966 if (!flip
&& ir
->data
.pixel_center_integer
) {
967 emit(MOV(wpos
, this->pixel_y
));
969 fs_reg pixel_y
= this->pixel_y
;
970 float offset
= (ir
->data
.pixel_center_integer
? 0.0 : 0.5);
973 pixel_y
.negate
= true;
974 offset
+= c
->key
.drawable_height
- 1.0;
977 emit(ADD(wpos
, pixel_y
, fs_reg(offset
)));
983 emit(MOV(wpos
, fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
985 emit(FS_OPCODE_LINTERP
, wpos
,
986 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
987 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
988 interp_reg(VARYING_SLOT_POS
, 2));
992 /* gl_FragCoord.w: Already set up in emit_interpolation */
993 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
999 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1000 glsl_interp_qualifier interpolation_mode
,
1003 brw_wm_barycentric_interp_mode barycoord_mode
;
1004 if (brw
->gen
>= 6) {
1006 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1007 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1009 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1011 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1012 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1014 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1017 /* On Ironlake and below, there is only one interpolation mode.
1018 * Centroid interpolation doesn't mean anything on this hardware --
1019 * there is no multisampling.
1021 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1023 return emit(FS_OPCODE_LINTERP
, attr
,
1024 this->delta_x
[barycoord_mode
],
1025 this->delta_y
[barycoord_mode
], interp
);
1029 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
1031 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1032 reg
->type
= brw_type_for_base_type(ir
->type
->get_scalar_type());
1035 unsigned int array_elements
;
1036 const glsl_type
*type
;
1038 if (ir
->type
->is_array()) {
1039 array_elements
= ir
->type
->length
;
1040 if (array_elements
== 0) {
1041 fail("dereferenced array '%s' has length 0\n", ir
->name
);
1043 type
= ir
->type
->fields
.array
;
1049 glsl_interp_qualifier interpolation_mode
=
1050 ir
->determine_interpolation_mode(c
->key
.flat_shade
);
1052 int location
= ir
->data
.location
;
1053 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1054 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1055 if (c
->prog_data
.urb_setup
[location
] == -1) {
1056 /* If there's no incoming setup data for this slot, don't
1057 * emit interpolation for it.
1059 attr
.reg_offset
+= type
->vector_elements
;
1064 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1065 /* Constant interpolation (flat shading) case. The SF has
1066 * handed us defined values in only the constant offset
1067 * field of the setup reg.
1069 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1070 struct brw_reg interp
= interp_reg(location
, k
);
1071 interp
= suboffset(interp
, 3);
1072 interp
.type
= reg
->type
;
1073 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1077 /* Smooth/noperspective interpolation case. */
1078 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1079 /* FINISHME: At some point we probably want to push
1080 * this farther by giving similar treatment to the
1081 * other potentially constant components of the
1082 * attribute, as well as making brw_vs_constval.c
1083 * handle varyings other than gl_TexCoord.
1085 struct brw_reg interp
= interp_reg(location
, k
);
1086 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1088 if (brw
->needs_unlit_centroid_workaround
&& ir
->data
.centroid
) {
1089 /* Get the pixel/sample mask into f0 so that we know
1090 * which pixels are lit. Then, for each channel that is
1091 * unlit, replace the centroid data with non-centroid
1094 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1095 fs_inst
*inst
= emit_linterp(attr
, fs_reg(interp
),
1096 interpolation_mode
, false);
1097 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1098 inst
->predicate_inverse
= true;
1100 if (brw
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1101 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
1115 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
1117 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1119 /* The frontfacing comes in as a bit in the thread payload. */
1120 if (brw
->gen
>= 6) {
1121 emit(BRW_OPCODE_ASR
, *reg
,
1122 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1124 emit(BRW_OPCODE_NOT
, *reg
, *reg
);
1125 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1));
1127 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
1128 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
1131 emit(CMP(*reg
, fs_reg(r1_6ud
), fs_reg(1u << 31), BRW_CONDITIONAL_L
));
1132 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u));
1139 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1141 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1143 if (c
->key
.compute_pos_offset
) {
1144 /* Convert int_sample_pos to floating point */
1145 emit(MOV(dst
, int_sample_pos
));
1146 /* Scale to the range [0, 1] */
1147 emit(MUL(dst
, dst
, fs_reg(1 / 16.0f
)));
1150 /* From ARB_sample_shading specification:
1151 * "When rendering to a non-multisample buffer, or if multisample
1152 * rasterization is disabled, gl_SamplePosition will always be
1155 emit(MOV(dst
, fs_reg(0.5f
)));
1160 fs_visitor::emit_samplepos_setup(ir_variable
*ir
)
1162 assert(brw
->gen
>= 6);
1163 assert(ir
->type
== glsl_type::vec2_type
);
1165 this->current_annotation
= "compute sample position";
1166 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1168 fs_reg int_sample_x
= fs_reg(this, glsl_type::int_type
);
1169 fs_reg int_sample_y
= fs_reg(this, glsl_type::int_type
);
1171 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1172 * mode will be enabled.
1174 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1175 * R31.1:0 Position Offset X/Y for Slot[3:0]
1176 * R31.3:2 Position Offset X/Y for Slot[7:4]
1179 * The X, Y sample positions come in as bytes in thread payload. So, read
1180 * the positions using vstride=16, width=8, hstride=2.
1182 struct brw_reg sample_pos_reg
=
1183 stride(retype(brw_vec1_grf(c
->sample_pos_reg
, 0),
1184 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1186 emit(MOV(int_sample_x
, fs_reg(sample_pos_reg
)));
1187 if (dispatch_width
== 16) {
1188 int_sample_x
.sechalf
= true;
1189 fs_inst
*inst
= emit(MOV(int_sample_x
,
1190 fs_reg(suboffset(sample_pos_reg
, 16))));
1191 inst
->force_sechalf
= true;
1192 int_sample_x
.sechalf
= false;
1194 /* Compute gl_SamplePosition.x */
1195 compute_sample_position(pos
, int_sample_x
);
1197 emit(MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1))));
1198 if (dispatch_width
== 16) {
1199 int_sample_y
.sechalf
= true;
1200 fs_inst
*inst
= emit(MOV(int_sample_y
,
1201 fs_reg(suboffset(sample_pos_reg
, 17))));
1202 inst
->force_sechalf
= true;
1203 int_sample_y
.sechalf
= false;
1205 /* Compute gl_SamplePosition.y */
1206 compute_sample_position(pos
, int_sample_y
);
1211 fs_visitor::emit_sampleid_setup(ir_variable
*ir
)
1213 assert(brw
->gen
>= 6);
1215 this->current_annotation
= "compute sample id";
1216 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1218 if (c
->key
.compute_sample_id
) {
1219 fs_reg t1
= fs_reg(this, glsl_type::int_type
);
1220 fs_reg t2
= fs_reg(this, glsl_type::int_type
);
1221 t2
.type
= BRW_REGISTER_TYPE_UW
;
1223 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1224 * 8x multisampling, subspan 0 will represent sample N (where N
1225 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1226 * 7. We can find the value of N by looking at R0.0 bits 7:6
1227 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1228 * (since samples are always delivered in pairs). That is, we
1229 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1230 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1231 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1232 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1233 * populating a temporary variable with the sequence (0, 1, 2, 3),
1234 * and then reading from it using vstride=1, width=4, hstride=0.
1235 * These computations hold good for 4x multisampling as well.
1237 emit(BRW_OPCODE_AND
, t1
,
1238 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1239 fs_reg(brw_imm_d(0xc0)));
1240 emit(BRW_OPCODE_SHR
, t1
, t1
, fs_reg(5));
1241 /* This works for both SIMD8 and SIMD16 */
1242 emit(MOV(t2
, brw_imm_v(0x3210)));
1243 /* This special instruction takes care of setting vstride=1,
1244 * width=4, hstride=0 of t2 during an ADD instruction.
1246 emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1248 /* As per GL_ARB_sample_shading specification:
1249 * "When rendering to a non-multisample buffer, or if multisample
1250 * rasterization is disabled, gl_SampleID will always be zero."
1252 emit(BRW_OPCODE_MOV
, *reg
, fs_reg(0));
1259 fs_visitor::fix_math_operand(fs_reg src
)
1261 /* Can't do hstride == 0 args on gen6 math, so expand it out. We
1262 * might be able to do better by doing execsize = 1 math and then
1263 * expanding that result out, but we would need to be careful with
1266 * The hardware ignores source modifiers (negate and abs) on math
1267 * instructions, so we also move to a temp to set those up.
1269 if (brw
->gen
== 6 && src
.file
!= UNIFORM
&& src
.file
!= IMM
&&
1270 !src
.abs
&& !src
.negate
)
1273 /* Gen7 relaxes most of the above restrictions, but still can't use IMM
1276 if (brw
->gen
>= 7 && src
.file
!= IMM
)
1279 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
1280 expanded
.type
= src
.type
;
1281 emit(BRW_OPCODE_MOV
, expanded
, src
);
1286 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src
)
1289 case SHADER_OPCODE_RCP
:
1290 case SHADER_OPCODE_RSQ
:
1291 case SHADER_OPCODE_SQRT
:
1292 case SHADER_OPCODE_EXP2
:
1293 case SHADER_OPCODE_LOG2
:
1294 case SHADER_OPCODE_SIN
:
1295 case SHADER_OPCODE_COS
:
1298 assert(!"not reached: bad math opcode");
1302 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
1303 * might be able to do better by doing execsize = 1 math and then
1304 * expanding that result out, but we would need to be careful with
1307 * Gen 6 hardware ignores source modifiers (negate and abs) on math
1308 * instructions, so we also move to a temp to set those up.
1311 src
= fix_math_operand(src
);
1313 fs_inst
*inst
= emit(opcode
, dst
, src
);
1317 inst
->mlen
= dispatch_width
/ 8;
1324 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
1330 case SHADER_OPCODE_INT_QUOTIENT
:
1331 case SHADER_OPCODE_INT_REMAINDER
:
1332 if (brw
->gen
>= 7 && dispatch_width
== 16)
1333 fail("16-wide INTDIV unsupported\n");
1335 case SHADER_OPCODE_POW
:
1338 assert(!"not reached: unsupported binary math opcode.");
1342 if (brw
->gen
>= 6) {
1343 src0
= fix_math_operand(src0
);
1344 src1
= fix_math_operand(src1
);
1346 inst
= emit(opcode
, dst
, src0
, src1
);
1348 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
1349 * "Message Payload":
1351 * "Operand0[7]. For the INT DIV functions, this operand is the
1354 * "Operand1[7]. For the INT DIV functions, this operand is the
1357 bool is_int_div
= opcode
!= SHADER_OPCODE_POW
;
1358 fs_reg
&op0
= is_int_div
? src1
: src0
;
1359 fs_reg
&op1
= is_int_div
? src0
: src1
;
1361 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1, op1
.type
), op1
);
1362 inst
= emit(opcode
, dst
, op0
, reg_null_f
);
1364 inst
->base_mrf
= base_mrf
;
1365 inst
->mlen
= 2 * dispatch_width
/ 8;
1371 fs_visitor::assign_curb_setup()
1373 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
1374 if (dispatch_width
== 8) {
1375 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
1377 c
->prog_data
.first_curbe_grf_16
= c
->nr_payload_regs
;
1380 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1381 foreach_list(node
, &this->instructions
) {
1382 fs_inst
*inst
= (fs_inst
*)node
;
1384 for (unsigned int i
= 0; i
< 3; i
++) {
1385 if (inst
->src
[i
].file
== UNIFORM
) {
1386 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1387 struct brw_reg brw_reg
= brw_vec1_grf(c
->nr_payload_regs
+
1391 inst
->src
[i
].file
= HW_REG
;
1392 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
1399 fs_visitor::calculate_urb_setup()
1401 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1402 c
->prog_data
.urb_setup
[i
] = -1;
1406 /* Figure out where each of the incoming setup attributes lands. */
1407 if (brw
->gen
>= 6) {
1408 if (_mesa_bitcount_64(fp
->Base
.InputsRead
&
1409 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1410 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1411 * first 16 varying inputs, so we can put them wherever we want.
1412 * Just put them in order.
1414 * This is useful because it means that (a) inputs not used by the
1415 * fragment shader won't take up valuable register space, and (b) we
1416 * won't have to recompile the fragment shader if it gets paired with
1417 * a different vertex (or geometry) shader.
1419 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1420 if (fp
->Base
.InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1421 BITFIELD64_BIT(i
)) {
1422 c
->prog_data
.urb_setup
[i
] = urb_next
++;
1426 /* We have enough input varyings that the SF/SBE pipeline stage can't
1427 * arbitrarily rearrange them to suit our whim; we have to put them
1428 * in an order that matches the output of the previous pipeline stage
1429 * (geometry or vertex shader).
1431 struct brw_vue_map prev_stage_vue_map
;
1432 brw_compute_vue_map(brw
, &prev_stage_vue_map
,
1433 c
->key
.input_slots_valid
);
1434 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1435 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1436 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1438 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1439 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1442 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1443 (fp
->Base
.InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1444 BITFIELD64_BIT(varying
))) {
1445 c
->prog_data
.urb_setup
[varying
] = slot
- first_slot
;
1448 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1451 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1452 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1453 /* Point size is packed into the header, not as a general attribute */
1454 if (i
== VARYING_SLOT_PSIZ
)
1457 if (c
->key
.input_slots_valid
& BITFIELD64_BIT(i
)) {
1458 /* The back color slot is skipped when the front color is
1459 * also written to. In addition, some slots can be
1460 * written in the vertex shader and not read in the
1461 * fragment shader. So the register number must always be
1462 * incremented, mapped or not.
1464 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1465 c
->prog_data
.urb_setup
[i
] = urb_next
;
1471 * It's a FS only attribute, and we did interpolation for this attribute
1472 * in SF thread. So, count it here, too.
1474 * See compile_sf_prog() for more info.
1476 if (fp
->Base
.InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1477 c
->prog_data
.urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1480 c
->prog_data
.num_varying_inputs
= urb_next
;
1484 fs_visitor::assign_urb_setup()
1486 int urb_start
= c
->nr_payload_regs
+ c
->prog_data
.curb_read_length
;
1488 /* Offset all the urb_setup[] index by the actual position of the
1489 * setup regs, now that the location of the constants has been chosen.
1491 foreach_list(node
, &this->instructions
) {
1492 fs_inst
*inst
= (fs_inst
*)node
;
1494 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1495 assert(inst
->src
[2].file
== HW_REG
);
1496 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
1499 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1500 assert(inst
->src
[0].file
== HW_REG
);
1501 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1505 /* Each attribute is 4 setup channels, each of which is half a reg. */
1506 this->first_non_payload_grf
=
1507 urb_start
+ c
->prog_data
.num_varying_inputs
* 2;
1511 * Split large virtual GRFs into separate components if we can.
1513 * This is mostly duplicated with what brw_fs_vector_splitting does,
1514 * but that's really conservative because it's afraid of doing
1515 * splitting that doesn't result in real progress after the rest of
1516 * the optimization phases, which would cause infinite looping in
1517 * optimization. We can do it once here, safely. This also has the
1518 * opportunity to split interpolated values, or maybe even uniforms,
1519 * which we don't have at the IR level.
1521 * We want to split, because virtual GRFs are what we register
1522 * allocate and spill (due to contiguousness requirements for some
1523 * instructions), and they're what we naturally generate in the
1524 * codegen process, but most virtual GRFs don't actually need to be
1525 * contiguous sets of GRFs. If we split, we'll end up with reduced
1526 * live intervals and better dead code elimination and coalescing.
1529 fs_visitor::split_virtual_grfs()
1531 int num_vars
= this->virtual_grf_count
;
1532 bool split_grf
[num_vars
];
1533 int new_virtual_grf
[num_vars
];
1535 /* Try to split anything > 0 sized. */
1536 for (int i
= 0; i
< num_vars
; i
++) {
1537 if (this->virtual_grf_sizes
[i
] != 1)
1538 split_grf
[i
] = true;
1540 split_grf
[i
] = false;
1544 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
) {
1545 /* PLN opcodes rely on the delta_xy being contiguous. We only have to
1546 * check this for BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because prior to
1547 * Gen6, that was the only supported interpolation mode, and since Gen6,
1548 * delta_x and delta_y are in fixed hardware registers.
1550 split_grf
[this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
] =
1554 foreach_list(node
, &this->instructions
) {
1555 fs_inst
*inst
= (fs_inst
*)node
;
1557 /* If there's a SEND message that requires contiguous destination
1558 * registers, no splitting is allowed.
1560 if (inst
->regs_written
> 1) {
1561 split_grf
[inst
->dst
.reg
] = false;
1564 /* If we're sending from a GRF, don't split it, on the assumption that
1565 * the send is reading the whole thing.
1567 if (inst
->is_send_from_grf()) {
1568 for (int i
= 0; i
< 3; i
++) {
1569 if (inst
->src
[i
].file
== GRF
) {
1570 split_grf
[inst
->src
[i
].reg
] = false;
1576 /* Allocate new space for split regs. Note that the virtual
1577 * numbers will be contiguous.
1579 for (int i
= 0; i
< num_vars
; i
++) {
1581 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1582 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1583 int reg
= virtual_grf_alloc(1);
1584 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1587 this->virtual_grf_sizes
[i
] = 1;
1591 foreach_list(node
, &this->instructions
) {
1592 fs_inst
*inst
= (fs_inst
*)node
;
1594 if (inst
->dst
.file
== GRF
&&
1595 split_grf
[inst
->dst
.reg
] &&
1596 inst
->dst
.reg_offset
!= 0) {
1597 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1598 inst
->dst
.reg_offset
- 1);
1599 inst
->dst
.reg_offset
= 0;
1601 for (int i
= 0; i
< 3; i
++) {
1602 if (inst
->src
[i
].file
== GRF
&&
1603 split_grf
[inst
->src
[i
].reg
] &&
1604 inst
->src
[i
].reg_offset
!= 0) {
1605 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1606 inst
->src
[i
].reg_offset
- 1);
1607 inst
->src
[i
].reg_offset
= 0;
1611 invalidate_live_intervals();
1615 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1617 * During code generation, we create tons of temporary variables, many of
1618 * which get immediately killed and are never used again. Yet, in later
1619 * optimization and analysis passes, such as compute_live_intervals, we need
1620 * to loop over all the virtual GRFs. Compacting them can save a lot of
1624 fs_visitor::compact_virtual_grfs()
1626 /* Mark which virtual GRFs are used, and count how many. */
1627 int remap_table
[this->virtual_grf_count
];
1628 memset(remap_table
, -1, sizeof(remap_table
));
1630 foreach_list(node
, &this->instructions
) {
1631 const fs_inst
*inst
= (const fs_inst
*) node
;
1633 if (inst
->dst
.file
== GRF
)
1634 remap_table
[inst
->dst
.reg
] = 0;
1636 for (int i
= 0; i
< 3; i
++) {
1637 if (inst
->src
[i
].file
== GRF
)
1638 remap_table
[inst
->src
[i
].reg
] = 0;
1642 /* In addition to registers used in instructions, fs_visitor keeps
1643 * direct references to certain special values which must be patched:
1645 fs_reg
*special
[] = {
1646 &frag_depth
, &pixel_x
, &pixel_y
, &pixel_w
, &wpos_w
, &dual_src_output
,
1647 &outputs
[0], &outputs
[1], &outputs
[2], &outputs
[3],
1648 &outputs
[4], &outputs
[5], &outputs
[6], &outputs
[7],
1649 &delta_x
[0], &delta_x
[1], &delta_x
[2],
1650 &delta_x
[3], &delta_x
[4], &delta_x
[5],
1651 &delta_y
[0], &delta_y
[1], &delta_y
[2],
1652 &delta_y
[3], &delta_y
[4], &delta_y
[5],
1654 STATIC_ASSERT(BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
== 6);
1655 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
== 8);
1657 /* Treat all special values as used, to be conservative */
1658 for (unsigned i
= 0; i
< ARRAY_SIZE(special
); i
++) {
1659 if (special
[i
]->file
== GRF
)
1660 remap_table
[special
[i
]->reg
] = 0;
1663 /* Compact the GRF arrays. */
1665 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
1666 if (remap_table
[i
] != -1) {
1667 remap_table
[i
] = new_index
;
1668 virtual_grf_sizes
[new_index
] = virtual_grf_sizes
[i
];
1669 invalidate_live_intervals();
1674 this->virtual_grf_count
= new_index
;
1676 /* Patch all the instructions to use the newly renumbered registers */
1677 foreach_list(node
, &this->instructions
) {
1678 fs_inst
*inst
= (fs_inst
*) node
;
1680 if (inst
->dst
.file
== GRF
)
1681 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1683 for (int i
= 0; i
< 3; i
++) {
1684 if (inst
->src
[i
].file
== GRF
)
1685 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1689 /* Patch all the references to special values */
1690 for (unsigned i
= 0; i
< ARRAY_SIZE(special
); i
++) {
1691 if (special
[i
]->file
== GRF
&& remap_table
[special
[i
]->reg
] != -1)
1692 special
[i
]->reg
= remap_table
[special
[i
]->reg
];
1697 fs_visitor::remove_dead_constants()
1699 if (dispatch_width
== 8) {
1700 this->params_remap
= ralloc_array(mem_ctx
, int, c
->prog_data
.nr_params
);
1701 this->nr_params_remap
= c
->prog_data
.nr_params
;
1703 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++)
1704 this->params_remap
[i
] = -1;
1706 /* Find which params are still in use. */
1707 foreach_list(node
, &this->instructions
) {
1708 fs_inst
*inst
= (fs_inst
*)node
;
1710 for (int i
= 0; i
< 3; i
++) {
1711 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1713 if (inst
->src
[i
].file
!= UNIFORM
)
1716 /* Section 5.11 of the OpenGL 4.3 spec says:
1718 * "Out-of-bounds reads return undefined values, which include
1719 * values from other variables of the active program or zero."
1721 if (constant_nr
< 0 || constant_nr
>= (int)c
->prog_data
.nr_params
) {
1725 /* For now, set this to non-negative. We'll give it the
1726 * actual new number in a moment, in order to keep the
1727 * register numbers nicely ordered.
1729 this->params_remap
[constant_nr
] = 0;
1733 /* Figure out what the new numbers for the params will be. At some
1734 * point when we're doing uniform array access, we're going to want
1735 * to keep the distinction between .reg and .reg_offset, but for
1736 * now we don't care.
1738 unsigned int new_nr_params
= 0;
1739 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1740 if (this->params_remap
[i
] != -1) {
1741 this->params_remap
[i
] = new_nr_params
++;
1745 /* Update the list of params to be uploaded to match our new numbering. */
1746 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1747 int remapped
= this->params_remap
[i
];
1752 c
->prog_data
.param
[remapped
] = c
->prog_data
.param
[i
];
1755 c
->prog_data
.nr_params
= new_nr_params
;
1757 /* This should have been generated in the 8-wide pass already. */
1758 assert(this->params_remap
);
1761 /* Now do the renumbering of the shader to remove unused params. */
1762 foreach_list(node
, &this->instructions
) {
1763 fs_inst
*inst
= (fs_inst
*)node
;
1765 for (int i
= 0; i
< 3; i
++) {
1766 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1768 if (inst
->src
[i
].file
!= UNIFORM
)
1771 /* as above alias to 0 */
1772 if (constant_nr
< 0 || constant_nr
>= (int)this->nr_params_remap
) {
1775 assert(this->params_remap
[constant_nr
] != -1);
1776 inst
->src
[i
].reg
= this->params_remap
[constant_nr
];
1777 inst
->src
[i
].reg_offset
= 0;
1785 * Implements array access of uniforms by inserting a
1786 * PULL_CONSTANT_LOAD instruction.
1788 * Unlike temporary GRF array access (where we don't support it due to
1789 * the difficulty of doing relative addressing on instruction
1790 * destinations), we could potentially do array access of uniforms
1791 * that were loaded in GRF space as push constants. In real-world
1792 * usage we've seen, though, the arrays being used are always larger
1793 * than we could load as push constants, so just always move all
1794 * uniform array access out to a pull constant buffer.
1797 fs_visitor::move_uniform_array_access_to_pull_constants()
1799 int pull_constant_loc
[c
->prog_data
.nr_params
];
1801 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1802 pull_constant_loc
[i
] = -1;
1805 /* Walk through and find array access of uniforms. Put a copy of that
1806 * uniform in the pull constant buffer.
1808 * Note that we don't move constant-indexed accesses to arrays. No
1809 * testing has been done of the performance impact of this choice.
1811 foreach_list_safe(node
, &this->instructions
) {
1812 fs_inst
*inst
= (fs_inst
*)node
;
1814 for (int i
= 0 ; i
< 3; i
++) {
1815 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
1818 int uniform
= inst
->src
[i
].reg
;
1820 /* If this array isn't already present in the pull constant buffer,
1823 if (pull_constant_loc
[uniform
] == -1) {
1824 const float **values
= &c
->prog_data
.param
[uniform
];
1826 pull_constant_loc
[uniform
] = c
->prog_data
.nr_pull_params
;
1828 assert(param_size
[uniform
]);
1830 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
1831 c
->prog_data
.pull_param
[c
->prog_data
.nr_pull_params
++] =
1836 /* Set up the annotation tracking for new generated instructions. */
1838 current_annotation
= inst
->annotation
;
1840 fs_reg surf_index
= fs_reg(c
->prog_data
.base
.binding_table
.pull_constants_start
);
1841 fs_reg temp
= fs_reg(this, glsl_type::float_type
);
1842 exec_list list
= VARYING_PULL_CONSTANT_LOAD(temp
,
1844 *inst
->src
[i
].reladdr
,
1845 pull_constant_loc
[uniform
] +
1846 inst
->src
[i
].reg_offset
);
1847 inst
->insert_before(&list
);
1849 inst
->src
[i
].file
= temp
.file
;
1850 inst
->src
[i
].reg
= temp
.reg
;
1851 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
1852 inst
->src
[i
].reladdr
= NULL
;
1858 * Choose accesses from the UNIFORM file to demote to using the pull
1861 * We allow a fragment shader to have more than the specified minimum
1862 * maximum number of fragment shader uniform components (64). If
1863 * there are too many of these, they'd fill up all of register space.
1864 * So, this will push some of them out to the pull constant buffer and
1865 * update the program to load them.
1868 fs_visitor::setup_pull_constants()
1870 /* Only allow 16 registers (128 uniform components) as push constants. */
1871 unsigned int max_uniform_components
= 16 * 8;
1872 if (c
->prog_data
.nr_params
<= max_uniform_components
)
1875 if (dispatch_width
== 16) {
1876 fail("Pull constants not supported in 16-wide\n");
1880 /* Just demote the end of the list. We could probably do better
1881 * here, demoting things that are rarely used in the program first.
1883 unsigned int pull_uniform_base
= max_uniform_components
;
1885 int pull_constant_loc
[c
->prog_data
.nr_params
];
1886 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1887 if (i
< pull_uniform_base
) {
1888 pull_constant_loc
[i
] = -1;
1890 pull_constant_loc
[i
] = -1;
1891 /* If our constant is already being uploaded for reladdr purposes,
1894 for (unsigned int j
= 0; j
< c
->prog_data
.nr_pull_params
; j
++) {
1895 if (c
->prog_data
.pull_param
[j
] == c
->prog_data
.param
[i
]) {
1896 pull_constant_loc
[i
] = j
;
1900 if (pull_constant_loc
[i
] == -1) {
1901 int pull_index
= c
->prog_data
.nr_pull_params
++;
1902 c
->prog_data
.pull_param
[pull_index
] = c
->prog_data
.param
[i
];
1903 pull_constant_loc
[i
] = pull_index
;;
1907 c
->prog_data
.nr_params
= pull_uniform_base
;
1909 foreach_list(node
, &this->instructions
) {
1910 fs_inst
*inst
= (fs_inst
*)node
;
1912 for (int i
= 0; i
< 3; i
++) {
1913 if (inst
->src
[i
].file
!= UNIFORM
)
1916 int pull_index
= pull_constant_loc
[inst
->src
[i
].reg
+
1917 inst
->src
[i
].reg_offset
];
1918 if (pull_index
== -1)
1921 assert(!inst
->src
[i
].reladdr
);
1923 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
1924 fs_reg index
= fs_reg(c
->prog_data
.base
.binding_table
.pull_constants_start
);
1925 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
1927 new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
1928 dst
, index
, offset
);
1929 pull
->ir
= inst
->ir
;
1930 pull
->annotation
= inst
->annotation
;
1932 inst
->insert_before(pull
);
1934 inst
->src
[i
].file
= GRF
;
1935 inst
->src
[i
].reg
= dst
.reg
;
1936 inst
->src
[i
].reg_offset
= 0;
1937 inst
->src
[i
].smear
= pull_index
& 3;
1943 fs_visitor::opt_algebraic()
1945 bool progress
= false;
1947 foreach_list(node
, &this->instructions
) {
1948 fs_inst
*inst
= (fs_inst
*)node
;
1950 switch (inst
->opcode
) {
1951 case BRW_OPCODE_MUL
:
1952 if (inst
->src
[1].file
!= IMM
)
1956 if (inst
->src
[1].is_one()) {
1957 inst
->opcode
= BRW_OPCODE_MOV
;
1958 inst
->src
[1] = reg_undef
;
1964 if (inst
->src
[1].is_zero()) {
1965 inst
->opcode
= BRW_OPCODE_MOV
;
1966 inst
->src
[0] = inst
->src
[1];
1967 inst
->src
[1] = reg_undef
;
1973 case BRW_OPCODE_ADD
:
1974 if (inst
->src
[1].file
!= IMM
)
1978 if (inst
->src
[1].is_zero()) {
1979 inst
->opcode
= BRW_OPCODE_MOV
;
1980 inst
->src
[1] = reg_undef
;
1986 if (inst
->src
[0].equals(inst
->src
[1])) {
1987 inst
->opcode
= BRW_OPCODE_MOV
;
1988 inst
->src
[1] = reg_undef
;
1993 case BRW_OPCODE_SEL
:
1994 if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
1995 switch (inst
->conditional_mod
) {
1996 case BRW_CONDITIONAL_LE
:
1997 case BRW_CONDITIONAL_L
:
1998 switch (inst
->src
[1].type
) {
1999 case BRW_REGISTER_TYPE_F
:
2000 if (inst
->src
[1].imm
.f
>= 1.0f
) {
2001 inst
->opcode
= BRW_OPCODE_MOV
;
2002 inst
->src
[1] = reg_undef
;
2010 case BRW_CONDITIONAL_GE
:
2011 case BRW_CONDITIONAL_G
:
2012 switch (inst
->src
[1].type
) {
2013 case BRW_REGISTER_TYPE_F
:
2014 if (inst
->src
[1].imm
.f
<= 0.0f
) {
2015 inst
->opcode
= BRW_OPCODE_MOV
;
2016 inst
->src
[1] = reg_undef
;
2017 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2038 * Removes any instructions writing a VGRF where that VGRF is not used by any
2039 * later instruction.
2042 fs_visitor::dead_code_eliminate()
2044 bool progress
= false;
2047 calculate_live_intervals();
2049 foreach_list_safe(node
, &this->instructions
) {
2050 fs_inst
*inst
= (fs_inst
*)node
;
2052 if (inst
->dst
.file
== GRF
&& !inst
->has_side_effects()) {
2055 for (int i
= 0; i
< inst
->regs_written
; i
++) {
2056 int var
= live_intervals
->var_from_vgrf
[inst
->dst
.reg
];
2057 assert(live_intervals
->end
[var
+ inst
->dst
.reg_offset
+ i
] >= pc
);
2058 if (live_intervals
->end
[var
+ inst
->dst
.reg_offset
+ i
] != pc
) {
2065 /* Don't dead code eliminate instructions that write to the
2066 * accumulator as a side-effect. Instead just set the destination
2067 * to the null register to free it.
2069 switch (inst
->opcode
) {
2070 case BRW_OPCODE_ADDC
:
2071 case BRW_OPCODE_SUBB
:
2072 case BRW_OPCODE_MACH
:
2073 inst
->dst
= fs_reg(retype(brw_null_reg(), inst
->dst
.type
));
2087 invalidate_live_intervals();
2092 struct dead_code_hash_key
2099 dead_code_hash_compare(const void *a
, const void *b
)
2101 return memcmp(a
, b
, sizeof(struct dead_code_hash_key
)) == 0;
2105 clear_dead_code_hash(struct hash_table
*ht
)
2107 struct hash_entry
*entry
;
2109 hash_table_foreach(ht
, entry
) {
2110 _mesa_hash_table_remove(ht
, entry
);
2115 insert_dead_code_hash(struct hash_table
*ht
,
2116 int vgrf
, int reg_offset
, fs_inst
*inst
)
2118 /* We don't bother freeing keys, because they'll be GCed with the ht. */
2119 struct dead_code_hash_key
*key
= ralloc(ht
, struct dead_code_hash_key
);
2122 key
->reg_offset
= reg_offset
;
2124 _mesa_hash_table_insert(ht
, _mesa_hash_data(key
, sizeof(*key
)), key
, inst
);
2127 static struct hash_entry
*
2128 get_dead_code_hash_entry(struct hash_table
*ht
, int vgrf
, int reg_offset
)
2130 struct dead_code_hash_key key
;
2133 key
.reg_offset
= reg_offset
;
2135 return _mesa_hash_table_search(ht
, _mesa_hash_data(&key
, sizeof(key
)), &key
);
2139 remove_dead_code_hash(struct hash_table
*ht
,
2140 int vgrf
, int reg_offset
)
2142 struct hash_entry
*entry
= get_dead_code_hash_entry(ht
, vgrf
, reg_offset
);
2146 _mesa_hash_table_remove(ht
, entry
);
2150 * Walks basic blocks, removing any regs that are written but not read before
2153 * The dead_code_eliminate() function implements a global dead code
2154 * elimination, but it only handles the removing the last write to a register
2155 * if it's never read. This one can handle intermediate writes, but only
2156 * within a basic block.
2159 fs_visitor::dead_code_eliminate_local()
2161 struct hash_table
*ht
;
2162 bool progress
= false;
2164 ht
= _mesa_hash_table_create(mem_ctx
, dead_code_hash_compare
);
2166 foreach_list_safe(node
, &this->instructions
) {
2167 fs_inst
*inst
= (fs_inst
*)node
;
2169 /* At a basic block, empty the HT since we don't understand dataflow
2172 if (inst
->is_control_flow()) {
2173 clear_dead_code_hash(ht
);
2177 /* Clear the HT of any instructions that got read. */
2178 for (int i
= 0; i
< 3; i
++) {
2179 fs_reg src
= inst
->src
[i
];
2180 if (src
.file
!= GRF
)
2184 if (inst
->is_send_from_grf())
2185 read
= virtual_grf_sizes
[src
.reg
] - src
.reg_offset
;
2187 for (int reg_offset
= src
.reg_offset
;
2188 reg_offset
< src
.reg_offset
+ read
;
2190 remove_dead_code_hash(ht
, src
.reg
, reg_offset
);
2194 /* Add any update of a GRF to the HT, removing a previous write if it
2197 if (inst
->dst
.file
== GRF
) {
2198 if (inst
->regs_written
> 1) {
2199 /* We don't know how to trim channels from an instruction's
2200 * writes, so we can't incrementally remove unread channels from
2201 * it. Just remove whatever it overwrites from the table
2203 for (int i
= 0; i
< inst
->regs_written
; i
++) {
2204 remove_dead_code_hash(ht
,
2206 inst
->dst
.reg_offset
+ i
);
2209 struct hash_entry
*entry
=
2210 get_dead_code_hash_entry(ht
, inst
->dst
.reg
,
2211 inst
->dst
.reg_offset
);
2214 if (inst
->is_partial_write()) {
2215 /* For a partial write, we can't remove any previous dead code
2216 * candidate, since we're just modifying their result.
2219 /* We're completely updating a channel, and there was a
2220 * previous write to the channel that wasn't read. Kill it!
2222 fs_inst
*inst
= (fs_inst
*)entry
->data
;
2227 _mesa_hash_table_remove(ht
, entry
);
2230 if (!inst
->has_side_effects())
2231 insert_dead_code_hash(ht
, inst
->dst
.reg
, inst
->dst
.reg_offset
,
2237 _mesa_hash_table_destroy(ht
, NULL
);
2240 invalidate_live_intervals();
2246 * Implements register coalescing: Checks if the two registers involved in a
2247 * raw move don't interfere, in which case they can both be stored in the same
2248 * place and the MOV removed.
2251 fs_visitor::register_coalesce()
2253 bool progress
= false;
2255 calculate_live_intervals();
2257 foreach_list_safe(node
, &this->instructions
) {
2258 fs_inst
*inst
= (fs_inst
*)node
;
2260 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2261 inst
->is_partial_write() ||
2263 inst
->src
[0].file
!= GRF
||
2264 inst
->src
[0].negate
||
2266 inst
->src
[0].smear
!= -1 ||
2267 inst
->dst
.file
!= GRF
||
2268 inst
->dst
.type
!= inst
->src
[0].type
||
2269 virtual_grf_sizes
[inst
->src
[0].reg
] != 1) {
2273 int var_from
= live_intervals
->var_from_reg(&inst
->src
[0]);
2274 int var_to
= live_intervals
->var_from_reg(&inst
->dst
);
2276 if (live_intervals
->vars_interfere(var_from
, var_to
) &&
2277 !inst
->dst
.equals(inst
->src
[0]))
2280 int reg_from
= inst
->src
[0].reg
;
2281 assert(inst
->src
[0].reg_offset
== 0);
2282 int reg_to
= inst
->dst
.reg
;
2283 int reg_to_offset
= inst
->dst
.reg_offset
;
2285 foreach_list(node
, &this->instructions
) {
2286 fs_inst
*scan_inst
= (fs_inst
*)node
;
2288 if (scan_inst
->dst
.file
== GRF
&&
2289 scan_inst
->dst
.reg
== reg_from
) {
2290 scan_inst
->dst
.reg
= reg_to
;
2291 scan_inst
->dst
.reg_offset
= reg_to_offset
;
2293 for (int i
= 0; i
< 3; i
++) {
2294 if (scan_inst
->src
[i
].file
== GRF
&&
2295 scan_inst
->src
[i
].reg
== reg_from
) {
2296 scan_inst
->src
[i
].reg
= reg_to
;
2297 scan_inst
->src
[i
].reg_offset
= reg_to_offset
;
2308 invalidate_live_intervals();
2314 fs_visitor::compute_to_mrf()
2316 bool progress
= false;
2319 calculate_live_intervals();
2321 foreach_list_safe(node
, &this->instructions
) {
2322 fs_inst
*inst
= (fs_inst
*)node
;
2327 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2328 inst
->is_partial_write() ||
2329 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2330 inst
->dst
.type
!= inst
->src
[0].type
||
2331 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
2334 /* Work out which hardware MRF registers are written by this
2337 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2339 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2340 mrf_high
= mrf_low
+ 4;
2341 } else if (dispatch_width
== 16 &&
2342 (!inst
->force_uncompressed
&& !inst
->force_sechalf
)) {
2343 mrf_high
= mrf_low
+ 1;
2348 /* Can't compute-to-MRF this GRF if someone else was going to
2351 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2354 /* Found a move of a GRF to a MRF. Let's see if we can go
2355 * rewrite the thing that made this GRF to write into the MRF.
2358 for (scan_inst
= (fs_inst
*)inst
->prev
;
2359 scan_inst
->prev
!= NULL
;
2360 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2361 if (scan_inst
->dst
.file
== GRF
&&
2362 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2363 /* Found the last thing to write our reg we want to turn
2364 * into a compute-to-MRF.
2367 /* If this one instruction didn't populate all the
2368 * channels, bail. We might be able to rewrite everything
2369 * that writes that reg, but it would require smarter
2370 * tracking to delay the rewriting until complete success.
2372 if (scan_inst
->is_partial_write())
2375 /* Things returning more than one register would need us to
2376 * understand coalescing out more than one MOV at a time.
2378 if (scan_inst
->regs_written
> 1)
2381 /* SEND instructions can't have MRF as a destination. */
2382 if (scan_inst
->mlen
)
2385 if (brw
->gen
== 6) {
2386 /* gen6 math instructions must have the destination be
2387 * GRF, so no compute-to-MRF for them.
2389 if (scan_inst
->is_math()) {
2394 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2395 /* Found the creator of our MRF's source value. */
2396 scan_inst
->dst
.file
= MRF
;
2397 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2398 scan_inst
->saturate
|= inst
->saturate
;
2405 /* We don't handle control flow here. Most computation of
2406 * values that end up in MRFs are shortly before the MRF
2409 if (scan_inst
->is_control_flow() && scan_inst
->opcode
!= BRW_OPCODE_IF
)
2412 /* You can't read from an MRF, so if someone else reads our
2413 * MRF's source GRF that we wanted to rewrite, that stops us.
2415 bool interfered
= false;
2416 for (int i
= 0; i
< 3; i
++) {
2417 if (scan_inst
->src
[i
].file
== GRF
&&
2418 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2419 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2426 if (scan_inst
->dst
.file
== MRF
) {
2427 /* If somebody else writes our MRF here, we can't
2428 * compute-to-MRF before that.
2430 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2433 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2434 scan_mrf_high
= scan_mrf_low
+ 4;
2435 } else if (dispatch_width
== 16 &&
2436 (!scan_inst
->force_uncompressed
&&
2437 !scan_inst
->force_sechalf
)) {
2438 scan_mrf_high
= scan_mrf_low
+ 1;
2440 scan_mrf_high
= scan_mrf_low
;
2443 if (mrf_low
== scan_mrf_low
||
2444 mrf_low
== scan_mrf_high
||
2445 mrf_high
== scan_mrf_low
||
2446 mrf_high
== scan_mrf_high
) {
2451 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2452 /* Found a SEND instruction, which means that there are
2453 * live values in MRFs from base_mrf to base_mrf +
2454 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2457 if (mrf_low
>= scan_inst
->base_mrf
&&
2458 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2461 if (mrf_high
>= scan_inst
->base_mrf
&&
2462 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2470 invalidate_live_intervals();
2476 * Walks through basic blocks, looking for repeated MRF writes and
2477 * removing the later ones.
2480 fs_visitor::remove_duplicate_mrf_writes()
2482 fs_inst
*last_mrf_move
[16];
2483 bool progress
= false;
2485 /* Need to update the MRF tracking for compressed instructions. */
2486 if (dispatch_width
== 16)
2489 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2491 foreach_list_safe(node
, &this->instructions
) {
2492 fs_inst
*inst
= (fs_inst
*)node
;
2494 if (inst
->is_control_flow()) {
2495 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2498 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2499 inst
->dst
.file
== MRF
) {
2500 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2501 if (prev_inst
&& inst
->equals(prev_inst
)) {
2508 /* Clear out the last-write records for MRFs that were overwritten. */
2509 if (inst
->dst
.file
== MRF
) {
2510 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2513 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2514 /* Found a SEND instruction, which will include two or fewer
2515 * implied MRF writes. We could do better here.
2517 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2518 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2522 /* Clear out any MRF move records whose sources got overwritten. */
2523 if (inst
->dst
.file
== GRF
) {
2524 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
2525 if (last_mrf_move
[i
] &&
2526 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2527 last_mrf_move
[i
] = NULL
;
2532 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2533 inst
->dst
.file
== MRF
&&
2534 inst
->src
[0].file
== GRF
&&
2535 !inst
->is_partial_write()) {
2536 last_mrf_move
[inst
->dst
.reg
] = inst
;
2541 invalidate_live_intervals();
2547 clear_deps_for_inst_src(fs_inst
*inst
, int dispatch_width
, bool *deps
,
2548 int first_grf
, int grf_len
)
2550 bool inst_16wide
= (dispatch_width
> 8 &&
2551 !inst
->force_uncompressed
&&
2552 !inst
->force_sechalf
);
2554 /* Clear the flag for registers that actually got read (as expected). */
2555 for (int i
= 0; i
< 3; i
++) {
2557 if (inst
->src
[i
].file
== GRF
) {
2558 grf
= inst
->src
[i
].reg
;
2559 } else if (inst
->src
[i
].file
== HW_REG
&&
2560 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2561 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2566 if (grf
>= first_grf
&&
2567 grf
< first_grf
+ grf_len
) {
2568 deps
[grf
- first_grf
] = false;
2570 deps
[grf
- first_grf
+ 1] = false;
2576 * Implements this workaround for the original 965:
2578 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2579 * check for post destination dependencies on this instruction, software
2580 * must ensure that there is no destination hazard for the case of ‘write
2581 * followed by a posted write’ shown in the following example.
2584 * 2. send r3.xy <rest of send instruction>
2587 * Due to no post-destination dependency check on the ‘send’, the above
2588 * code sequence could have two instructions (1 and 2) in flight at the
2589 * same time that both consider ‘r3’ as the target of their final writes.
2592 fs_visitor::insert_gen4_pre_send_dependency_workarounds(fs_inst
*inst
)
2594 int reg_size
= dispatch_width
/ 8;
2595 int write_len
= inst
->regs_written
* reg_size
;
2596 int first_write_grf
= inst
->dst
.reg
;
2597 bool needs_dep
[BRW_MAX_MRF
];
2598 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2600 memset(needs_dep
, false, sizeof(needs_dep
));
2601 memset(needs_dep
, true, write_len
);
2603 clear_deps_for_inst_src(inst
, dispatch_width
,
2604 needs_dep
, first_write_grf
, write_len
);
2606 /* Walk backwards looking for writes to registers we're writing which
2607 * aren't read since being written. If we hit the start of the program,
2608 * we assume that there are no outstanding dependencies on entry to the
2611 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->prev
;
2613 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2615 /* If we hit control flow, assume that there *are* outstanding
2616 * dependencies, and force their cleanup before our instruction.
2618 if (scan_inst
->is_control_flow()) {
2619 for (int i
= 0; i
< write_len
; i
++) {
2621 inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2627 bool scan_inst_16wide
= (dispatch_width
> 8 &&
2628 !scan_inst
->force_uncompressed
&&
2629 !scan_inst
->force_sechalf
);
2631 /* We insert our reads as late as possible on the assumption that any
2632 * instruction but a MOV that might have left us an outstanding
2633 * dependency has more latency than a MOV.
2635 if (scan_inst
->dst
.file
== GRF
) {
2636 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2637 int reg
= scan_inst
->dst
.reg
+ i
* reg_size
;
2639 if (reg
>= first_write_grf
&&
2640 reg
< first_write_grf
+ write_len
&&
2641 needs_dep
[reg
- first_write_grf
]) {
2642 inst
->insert_before(DEP_RESOLVE_MOV(reg
));
2643 needs_dep
[reg
- first_write_grf
] = false;
2644 if (scan_inst_16wide
)
2645 needs_dep
[reg
- first_write_grf
+ 1] = false;
2650 /* Clear the flag for registers that actually got read (as expected). */
2651 clear_deps_for_inst_src(scan_inst
, dispatch_width
,
2652 needs_dep
, first_write_grf
, write_len
);
2654 /* Continue the loop only if we haven't resolved all the dependencies */
2656 for (i
= 0; i
< write_len
; i
++) {
2666 * Implements this workaround for the original 965:
2668 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2669 * used as a destination register until after it has been sourced by an
2670 * instruction with a different destination register.
2673 fs_visitor::insert_gen4_post_send_dependency_workarounds(fs_inst
*inst
)
2675 int write_len
= inst
->regs_written
* dispatch_width
/ 8;
2676 int first_write_grf
= inst
->dst
.reg
;
2677 bool needs_dep
[BRW_MAX_MRF
];
2678 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2680 memset(needs_dep
, false, sizeof(needs_dep
));
2681 memset(needs_dep
, true, write_len
);
2682 /* Walk forwards looking for writes to registers we're writing which aren't
2683 * read before being written.
2685 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->next
;
2686 !scan_inst
->is_tail_sentinel();
2687 scan_inst
= (fs_inst
*)scan_inst
->next
) {
2688 /* If we hit control flow, force resolve all remaining dependencies. */
2689 if (scan_inst
->is_control_flow()) {
2690 for (int i
= 0; i
< write_len
; i
++) {
2692 scan_inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2697 /* Clear the flag for registers that actually got read (as expected). */
2698 clear_deps_for_inst_src(scan_inst
, dispatch_width
,
2699 needs_dep
, first_write_grf
, write_len
);
2701 /* We insert our reads as late as possible since they're reading the
2702 * result of a SEND, which has massive latency.
2704 if (scan_inst
->dst
.file
== GRF
&&
2705 scan_inst
->dst
.reg
>= first_write_grf
&&
2706 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
2707 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
2708 scan_inst
->insert_before(DEP_RESOLVE_MOV(scan_inst
->dst
.reg
));
2709 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
2712 /* Continue the loop only if we haven't resolved all the dependencies */
2714 for (i
= 0; i
< write_len
; i
++) {
2722 /* If we hit the end of the program, resolve all remaining dependencies out
2725 fs_inst
*last_inst
= (fs_inst
*)this->instructions
.get_tail();
2726 assert(last_inst
->eot
);
2727 for (int i
= 0; i
< write_len
; i
++) {
2729 last_inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2734 fs_visitor::insert_gen4_send_dependency_workarounds()
2736 if (brw
->gen
!= 4 || brw
->is_g4x
)
2739 /* Note that we're done with register allocation, so GRF fs_regs always
2740 * have a .reg_offset of 0.
2743 foreach_list_safe(node
, &this->instructions
) {
2744 fs_inst
*inst
= (fs_inst
*)node
;
2746 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
2747 insert_gen4_pre_send_dependency_workarounds(inst
);
2748 insert_gen4_post_send_dependency_workarounds(inst
);
2754 * Turns the generic expression-style uniform pull constant load instruction
2755 * into a hardware-specific series of instructions for loading a pull
2758 * The expression style allows the CSE pass before this to optimize out
2759 * repeated loads from the same offset, and gives the pre-register-allocation
2760 * scheduling full flexibility, while the conversion to native instructions
2761 * allows the post-register-allocation scheduler the best information
2764 * Note that execution masking for setting up pull constant loads is special:
2765 * the channels that need to be written are unrelated to the current execution
2766 * mask, since a later instruction will use one of the result channels as a
2767 * source operand for all 8 or 16 of its channels.
2770 fs_visitor::lower_uniform_pull_constant_loads()
2772 foreach_list(node
, &this->instructions
) {
2773 fs_inst
*inst
= (fs_inst
*)node
;
2775 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
2778 if (brw
->gen
>= 7) {
2779 /* The offset arg before was a vec4-aligned byte offset. We need to
2780 * turn it into a dword offset.
2782 fs_reg const_offset_reg
= inst
->src
[1];
2783 assert(const_offset_reg
.file
== IMM
&&
2784 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
2785 const_offset_reg
.imm
.u
/= 4;
2786 fs_reg payload
= fs_reg(this, glsl_type::uint_type
);
2788 /* This is actually going to be a MOV, but since only the first dword
2789 * is accessed, we have a special opcode to do just that one. Note
2790 * that this needs to be an operation that will be considered a def
2791 * by live variable analysis, or register allocation will explode.
2793 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
2794 payload
, const_offset_reg
);
2795 setup
->force_writemask_all
= true;
2797 setup
->ir
= inst
->ir
;
2798 setup
->annotation
= inst
->annotation
;
2799 inst
->insert_before(setup
);
2801 /* Similarly, this will only populate the first 4 channels of the
2802 * result register (since we only use smear values from 0-3), but we
2803 * don't tell the optimizer.
2805 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
2806 inst
->src
[1] = payload
;
2808 invalidate_live_intervals();
2810 /* Before register allocation, we didn't tell the scheduler about the
2811 * MRF we use. We know it's safe to use this MRF because nothing
2812 * else does except for register spill/unspill, which generates and
2813 * uses its MRF within a single IR instruction.
2815 inst
->base_mrf
= 14;
2822 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
2824 fs_inst
*inst
= (fs_inst
*)be_inst
;
2826 if (inst
->predicate
) {
2827 printf("(%cf0.%d) ",
2828 inst
->predicate_inverse
? '-' : '+',
2832 printf("%s", brw_instruction_name(inst
->opcode
));
2835 if (inst
->conditional_mod
) {
2836 printf("%s", conditional_modifier
[inst
->conditional_mod
]);
2837 if (!inst
->predicate
&&
2838 (brw
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
2839 inst
->opcode
!= BRW_OPCODE_IF
&&
2840 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
2841 printf(".f0.%d", inst
->flag_subreg
);
2847 switch (inst
->dst
.file
) {
2849 printf("vgrf%d", inst
->dst
.reg
);
2850 if (inst
->dst
.reg_offset
)
2851 printf("+%d", inst
->dst
.reg_offset
);
2854 printf("m%d", inst
->dst
.reg
);
2860 printf("***u%d***", inst
->dst
.reg
);
2863 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
2864 switch (inst
->dst
.fixed_hw_reg
.nr
) {
2868 case BRW_ARF_ADDRESS
:
2869 printf("a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
2871 case BRW_ARF_ACCUMULATOR
:
2872 printf("acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
2875 printf("f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
2876 inst
->dst
.fixed_hw_reg
.subnr
);
2879 printf("arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
2880 inst
->dst
.fixed_hw_reg
.subnr
);
2884 printf("hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
2886 if (inst
->dst
.fixed_hw_reg
.subnr
)
2887 printf("+%d", inst
->dst
.fixed_hw_reg
.subnr
);
2893 printf(":%s, ", reg_encoding
[inst
->dst
.type
]);
2895 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
2896 if (inst
->src
[i
].negate
)
2898 if (inst
->src
[i
].abs
)
2900 switch (inst
->src
[i
].file
) {
2902 printf("vgrf%d", inst
->src
[i
].reg
);
2903 if (inst
->src
[i
].reg_offset
)
2904 printf("+%d", inst
->src
[i
].reg_offset
);
2907 printf("***m%d***", inst
->src
[i
].reg
);
2910 printf("u%d", inst
->src
[i
].reg
);
2911 if (inst
->src
[i
].reg_offset
)
2912 printf(".%d", inst
->src
[i
].reg_offset
);
2918 switch (inst
->src
[i
].type
) {
2919 case BRW_REGISTER_TYPE_F
:
2920 printf("%ff", inst
->src
[i
].imm
.f
);
2922 case BRW_REGISTER_TYPE_D
:
2923 printf("%dd", inst
->src
[i
].imm
.i
);
2925 case BRW_REGISTER_TYPE_UD
:
2926 printf("%uu", inst
->src
[i
].imm
.u
);
2934 if (inst
->src
[i
].fixed_hw_reg
.negate
)
2936 if (inst
->src
[i
].fixed_hw_reg
.abs
)
2938 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
2939 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
2943 case BRW_ARF_ADDRESS
:
2944 printf("a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
2946 case BRW_ARF_ACCUMULATOR
:
2947 printf("acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
2950 printf("f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
2951 inst
->src
[i
].fixed_hw_reg
.subnr
);
2954 printf("arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
2955 inst
->src
[i
].fixed_hw_reg
.subnr
);
2959 printf("hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
2961 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
2962 printf("+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
2963 if (inst
->src
[i
].fixed_hw_reg
.abs
)
2970 if (inst
->src
[i
].abs
)
2973 if (inst
->src
[i
].file
!= IMM
) {
2974 printf(":%s", reg_encoding
[inst
->src
[i
].type
]);
2977 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
2983 if (inst
->force_uncompressed
)
2986 if (inst
->force_sechalf
)
2993 * Possibly returns an instruction that set up @param reg.
2995 * Sometimes we want to take the result of some expression/variable
2996 * dereference tree and rewrite the instruction generating the result
2997 * of the tree. When processing the tree, we know that the
2998 * instructions generated are all writing temporaries that are dead
2999 * outside of this tree. So, if we have some instructions that write
3000 * a temporary, we're free to point that temp write somewhere else.
3002 * Note that this doesn't guarantee that the instruction generated
3003 * only reg -- it might be the size=4 destination of a texture instruction.
3006 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
3011 end
->is_partial_write() ||
3013 !reg
.equals(end
->dst
)) {
3021 fs_visitor::setup_payload_gen6()
3024 (fp
->Base
.InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
3025 unsigned barycentric_interp_modes
= c
->prog_data
.barycentric_interp_modes
;
3027 assert(brw
->gen
>= 6);
3029 /* R0-1: masks, pixel X/Y coordinates. */
3030 c
->nr_payload_regs
= 2;
3031 /* R2: only for 32-pixel dispatch.*/
3033 /* R3-26: barycentric interpolation coordinates. These appear in the
3034 * same order that they appear in the brw_wm_barycentric_interp_mode
3035 * enum. Each set of coordinates occupies 2 registers if dispatch width
3036 * == 8 and 4 registers if dispatch width == 16. Coordinates only
3037 * appear if they were enabled using the "Barycentric Interpolation
3038 * Mode" bits in WM_STATE.
3040 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
3041 if (barycentric_interp_modes
& (1 << i
)) {
3042 c
->barycentric_coord_reg
[i
] = c
->nr_payload_regs
;
3043 c
->nr_payload_regs
+= 2;
3044 if (dispatch_width
== 16) {
3045 c
->nr_payload_regs
+= 2;
3050 /* R27: interpolated depth if uses source depth */
3052 c
->source_depth_reg
= c
->nr_payload_regs
;
3053 c
->nr_payload_regs
++;
3054 if (dispatch_width
== 16) {
3055 /* R28: interpolated depth if not 8-wide. */
3056 c
->nr_payload_regs
++;
3059 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
3061 c
->source_w_reg
= c
->nr_payload_regs
;
3062 c
->nr_payload_regs
++;
3063 if (dispatch_width
== 16) {
3064 /* R30: interpolated W if not 8-wide. */
3065 c
->nr_payload_regs
++;
3069 c
->prog_data
.uses_pos_offset
= c
->key
.compute_pos_offset
;
3070 /* R31: MSAA position offsets. */
3071 if (c
->prog_data
.uses_pos_offset
) {
3072 c
->sample_pos_reg
= c
->nr_payload_regs
;
3073 c
->nr_payload_regs
++;
3076 /* R32-: bary for 32-pixel. */
3077 /* R58-59: interp W for 32-pixel. */
3079 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3080 c
->source_depth_to_render_target
= true;
3085 fs_visitor::assign_binding_table_offsets()
3087 uint32_t next_binding_table_offset
= 0;
3089 /* If there are no color regions, we still perform an FB write to a null
3090 * renderbuffer, which we place at surface index 0.
3092 c
->prog_data
.binding_table
.render_target_start
= next_binding_table_offset
;
3093 next_binding_table_offset
+= MAX2(c
->key
.nr_color_regions
, 1);
3095 assign_common_binding_table_offsets(next_binding_table_offset
);
3101 sanity_param_count
= fp
->Base
.Parameters
->NumParameters
;
3102 uint32_t orig_nr_params
= c
->prog_data
.nr_params
;
3103 bool allocated_without_spills
;
3105 assign_binding_table_offsets();
3108 setup_payload_gen6();
3110 setup_payload_gen4();
3115 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3116 emit_shader_time_begin();
3118 calculate_urb_setup();
3119 if (fp
->Base
.InputsRead
> 0) {
3121 emit_interpolation_setup_gen4();
3123 emit_interpolation_setup_gen6();
3126 /* We handle discards by keeping track of the still-live pixels in f0.1.
3127 * Initialize it with the dispatched pixels.
3129 if (fp
->UsesKill
|| c
->key
.alpha_test_func
) {
3130 fs_inst
*discard_init
= emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
3131 discard_init
->flag_subreg
= 1;
3134 /* Generate FS IR for main(). (the visitor only descends into
3135 * functions called "main").
3138 foreach_list(node
, &*shader
->ir
) {
3139 ir_instruction
*ir
= (ir_instruction
*)node
;
3141 this->result
= reg_undef
;
3145 emit_fragment_program_code();
3151 emit(FS_OPCODE_PLACEHOLDER_HALT
);
3153 if (c
->key
.alpha_test_func
)
3158 split_virtual_grfs();
3160 move_uniform_array_access_to_pull_constants();
3161 remove_dead_constants();
3162 setup_pull_constants();
3168 compact_virtual_grfs();
3170 progress
= remove_duplicate_mrf_writes() || progress
;
3172 progress
= opt_algebraic() || progress
;
3173 progress
= opt_cse() || progress
;
3174 progress
= opt_copy_propagate() || progress
;
3175 progress
= opt_peephole_sel() || progress
;
3176 progress
= opt_peephole_predicated_break() || progress
;
3177 progress
= dead_code_eliminate() || progress
;
3178 progress
= dead_code_eliminate_local() || progress
;
3179 progress
= dead_control_flow_eliminate(this) || progress
;
3180 progress
= register_coalesce() || progress
;
3181 progress
= compute_to_mrf() || progress
;
3184 lower_uniform_pull_constant_loads();
3186 assign_curb_setup();
3189 static enum instruction_scheduler_mode pre_modes
[] = {
3191 SCHEDULE_PRE_NON_LIFO
,
3195 /* Try each scheduling heuristic to see if it can successfully register
3196 * allocate without spilling. They should be ordered by decreasing
3197 * performance but increasing likelihood of allocating.
3199 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
3200 schedule_instructions(pre_modes
[i
]);
3203 assign_regs_trivial();
3204 allocated_without_spills
= true;
3206 allocated_without_spills
= assign_regs(false);
3208 if (allocated_without_spills
)
3212 if (!allocated_without_spills
) {
3213 /* We assume that any spilling is worse than just dropping back to
3214 * SIMD8. There's probably actually some intermediate point where
3215 * SIMD16 with a couple of spills is still better.
3217 if (dispatch_width
== 16) {
3218 fail("Failure to register allocate. Reduce number of "
3219 "live scalar values to avoid this.");
3222 /* Since we're out of heuristics, just go spill registers until we
3223 * get an allocation.
3225 while (!assign_regs(true)) {
3231 assert(force_uncompressed_stack
== 0);
3233 /* This must come after all optimization and register allocation, since
3234 * it inserts dead code that happens to have side effects, and it does
3235 * so based on the actual physical registers in use.
3237 insert_gen4_send_dependency_workarounds();
3242 if (!allocated_without_spills
)
3243 schedule_instructions(SCHEDULE_POST
);
3245 if (dispatch_width
== 8) {
3246 c
->prog_data
.reg_blocks
= brw_register_blocks(grf_used
);
3248 c
->prog_data
.reg_blocks_16
= brw_register_blocks(grf_used
);
3250 /* Make sure we didn't try to sneak in an extra uniform */
3251 assert(orig_nr_params
== c
->prog_data
.nr_params
);
3252 (void) orig_nr_params
;
3255 /* If any state parameters were appended, then ParameterValues could have
3256 * been realloced, in which case the driver uniform storage set up by
3257 * _mesa_associate_uniform_storage() would point to freed memory. Make
3258 * sure that didn't happen.
3260 assert(sanity_param_count
== fp
->Base
.Parameters
->NumParameters
);
3266 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
,
3267 struct gl_fragment_program
*fp
,
3268 struct gl_shader_program
*prog
,
3269 unsigned *final_assembly_size
)
3271 bool start_busy
= false;
3272 float start_time
= 0;
3274 if (unlikely(brw
->perf_debug
)) {
3275 start_busy
= (brw
->batch
.last_bo
&&
3276 drm_intel_bo_busy(brw
->batch
.last_bo
));
3277 start_time
= get_time();
3280 struct brw_shader
*shader
= NULL
;
3282 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3284 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3286 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3287 _mesa_print_ir(shader
->ir
, NULL
);
3290 printf("ARB_fragment_program %d ir for native fragment shader\n",
3292 _mesa_print_program(&fp
->Base
);
3296 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3298 fs_visitor
v(brw
, c
, prog
, fp
, 8);
3301 prog
->LinkStatus
= false;
3302 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
3305 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
3311 exec_list
*simd16_instructions
= NULL
;
3312 fs_visitor
v2(brw
, c
, prog
, fp
, 16);
3313 if (brw
->gen
>= 5 && likely(!(INTEL_DEBUG
& DEBUG_NO16
))) {
3314 if (c
->prog_data
.nr_pull_params
== 0) {
3315 /* Try a 16-wide compile */
3316 v2
.import_uniforms(&v
);
3318 perf_debug("16-wide shader failed to compile, falling back to "
3319 "8-wide at a 10-20%% performance cost: %s", v2
.fail_msg
);
3321 simd16_instructions
= &v2
.instructions
;
3324 perf_debug("Skipping 16-wide due to pull parameters.\n");
3328 fs_generator
g(brw
, c
, prog
, fp
, v
.dual_src_output
.file
!= BAD_FILE
);
3329 const unsigned *generated
= g
.generate_assembly(&v
.instructions
,
3330 simd16_instructions
,
3331 final_assembly_size
);
3333 if (unlikely(brw
->perf_debug
) && shader
) {
3334 if (shader
->compiled_once
)
3335 brw_wm_debug_recompile(brw
, prog
, &c
->key
);
3336 shader
->compiled_once
= true;
3338 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
3339 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
3340 (get_time() - start_time
) * 1000);
3348 brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
3350 struct brw_context
*brw
= brw_context(ctx
);
3351 struct brw_wm_prog_key key
;
3353 if (!prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
])
3356 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)
3357 prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
]->Program
;
3358 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
3359 bool program_uses_dfdy
= fp
->UsesDFdy
;
3361 memset(&key
, 0, sizeof(key
));
3365 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
3367 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
3368 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
3370 /* Just assume depth testing. */
3371 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
3372 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
3375 if (brw
->gen
< 6 || _mesa_bitcount_64(fp
->Base
.InputsRead
&
3376 BRW_FS_VARYING_INPUT_MASK
) > 16)
3377 key
.input_slots_valid
= fp
->Base
.InputsRead
| VARYING_BIT_POS
;
3379 key
.clamp_fragment_color
= ctx
->API
== API_OPENGL_COMPAT
;
3381 unsigned sampler_count
= _mesa_fls(fp
->Base
.SamplersUsed
);
3382 for (unsigned i
= 0; i
< sampler_count
; i
++) {
3383 if (fp
->Base
.ShadowSamplers
& (1 << i
)) {
3384 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
3385 key
.tex
.swizzles
[i
] =
3386 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
3388 /* Color sampler: assume no swizzling. */
3389 key
.tex
.swizzles
[i
] = SWIZZLE_XYZW
;
3393 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
) {
3394 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
3397 if ((fp
->Base
.InputsRead
& VARYING_BIT_POS
) || program_uses_dfdy
) {
3398 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
3401 key
.nr_color_regions
= 1;
3403 /* GL_FRAGMENT_SHADER_DERIVATIVE_HINT is almost always GL_DONT_CARE. The
3404 * quality of the derivatives is likely to be determined by the driconf
3407 key
.high_quality_derivatives
= brw
->disable_derivative_optimization
;
3409 key
.program_string_id
= bfp
->id
;
3411 uint32_t old_prog_offset
= brw
->wm
.base
.prog_offset
;
3412 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
3414 bool success
= do_wm_prog(brw
, prog
, bfp
, &key
);
3416 brw
->wm
.base
.prog_offset
= old_prog_offset
;
3417 brw
->wm
.prog_data
= old_prog_data
;