2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "../glsl/glsl_types.h"
47 #include "../glsl/ir_optimization.h"
48 #include "../glsl/ir_print_visitor.h"
51 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
52 GRF
= BRW_GENERAL_REGISTER_FILE
,
53 MRF
= BRW_MESSAGE_REGISTER_FILE
,
54 IMM
= BRW_IMMEDIATE_VALUE
,
55 FIXED_HW_REG
, /* a struct brw_reg */
56 UNIFORM
, /* prog_data->params[hw_reg] */
61 FS_OPCODE_FB_WRITE
= 256,
79 static int using_new_fs
= -1;
80 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
83 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
85 struct brw_shader
*shader
;
87 shader
= talloc_zero(NULL
, struct brw_shader
);
89 shader
->base
.Type
= type
;
90 shader
->base
.Name
= name
;
91 _mesa_init_shader(ctx
, &shader
->base
);
97 struct gl_shader_program
*
98 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
100 struct brw_shader_program
*prog
;
101 prog
= talloc_zero(NULL
, struct brw_shader_program
);
103 prog
->base
.Name
= name
;
104 _mesa_init_shader_program(ctx
, &prog
->base
);
110 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
112 if (!_mesa_ir_compile_shader(ctx
, shader
))
119 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
121 if (using_new_fs
== -1)
122 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
124 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
125 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
127 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
128 void *mem_ctx
= talloc_new(NULL
);
132 talloc_free(shader
->ir
);
133 shader
->ir
= new(shader
) exec_list
;
134 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
136 do_mat_op_to_vec(shader
->ir
);
137 do_mod_to_fract(shader
->ir
);
138 do_div_to_mul_rcp(shader
->ir
);
139 do_sub_to_add_neg(shader
->ir
);
140 do_explog_to_explog2(shader
->ir
);
141 do_lower_texture_projection(shader
->ir
);
146 brw_do_channel_expressions(shader
->ir
);
147 brw_do_vector_splitting(shader
->ir
);
149 progress
= do_lower_jumps(shader
->ir
, true, true,
150 true, /* main return */
151 false, /* continue */
155 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
157 progress
= lower_noise(shader
->ir
) || progress
;
159 lower_variable_index_to_cond_assign(shader
->ir
,
161 GL_TRUE
, /* output */
163 GL_TRUE
/* uniform */
167 validate_ir_tree(shader
->ir
);
169 reparent_ir(shader
->ir
, shader
->ir
);
170 talloc_free(mem_ctx
);
174 if (!_mesa_ir_link_shader(ctx
, prog
))
181 type_size(const struct glsl_type
*type
)
183 unsigned int size
, i
;
185 switch (type
->base_type
) {
188 case GLSL_TYPE_FLOAT
:
190 return type
->components();
191 case GLSL_TYPE_ARRAY
:
192 return type_size(type
->fields
.array
) * type
->length
;
193 case GLSL_TYPE_STRUCT
:
195 for (i
= 0; i
< type
->length
; i
++) {
196 size
+= type_size(type
->fields
.structure
[i
].type
);
199 case GLSL_TYPE_SAMPLER
:
200 /* Samplers take up no register space, since they're baked in at
205 assert(!"not reached");
212 /* Callers of this talloc-based new need not call delete. It's
213 * easier to just talloc_free 'ctx' (or any of its ancestors). */
214 static void* operator new(size_t size
, void *ctx
)
218 node
= talloc_size(ctx
, size
);
219 assert(node
!= NULL
);
227 this->reg_offset
= 0;
233 /** Generic unset register constructor. */
237 this->file
= BAD_FILE
;
240 /** Immediate value constructor. */
245 this->type
= BRW_REGISTER_TYPE_F
;
249 /** Immediate value constructor. */
254 this->type
= BRW_REGISTER_TYPE_D
;
258 /** Immediate value constructor. */
263 this->type
= BRW_REGISTER_TYPE_UD
;
267 /** Fixed brw_reg Immediate value constructor. */
268 fs_reg(struct brw_reg fixed_hw_reg
)
271 this->file
= FIXED_HW_REG
;
272 this->fixed_hw_reg
= fixed_hw_reg
;
273 this->type
= fixed_hw_reg
.type
;
276 fs_reg(enum register_file file
, int hw_reg
);
277 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
279 /** Register file: ARF, GRF, MRF, IMM. */
280 enum register_file file
;
281 /** virtual register number. 0 = fixed hw reg */
283 /** Offset within the virtual register. */
285 /** HW register number. Generally unset until register allocation. */
287 /** Register type. BRW_REGISTER_TYPE_* */
291 struct brw_reg fixed_hw_reg
;
293 /** Value for file == BRW_IMMMEDIATE_FILE */
301 static const fs_reg reg_undef
;
302 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
304 class fs_inst
: public exec_node
{
306 /* Callers of this talloc-based new need not call delete. It's
307 * easier to just talloc_free 'ctx' (or any of its ancestors). */
308 static void* operator new(size_t size
, void *ctx
)
312 node
= talloc_zero_size(ctx
, size
);
313 assert(node
!= NULL
);
320 this->opcode
= BRW_OPCODE_NOP
;
321 this->saturate
= false;
322 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
323 this->predicated
= false;
327 this->header_present
= false;
328 this->shadow_compare
= false;
339 this->opcode
= opcode
;
342 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
)
345 this->opcode
= opcode
;
350 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
353 this->opcode
= opcode
;
359 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg src2
)
362 this->opcode
= opcode
;
369 int opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
374 int conditional_mod
; /**< BRW_CONDITIONAL_* */
376 int mlen
; /**< SEND message length */
378 int target
; /**< MRT target. */
384 * Annotation for the generated IR. One of the two can be set.
387 const char *annotation
;
391 class fs_visitor
: public ir_visitor
395 fs_visitor(struct brw_wm_compile
*c
, struct brw_shader
*shader
)
400 this->fp
= brw
->fragment_program
;
401 this->intel
= &brw
->intel
;
402 this->ctx
= &intel
->ctx
;
403 this->mem_ctx
= talloc_new(NULL
);
404 this->shader
= shader
;
406 this->variable_ht
= hash_table_ctor(0,
407 hash_table_pointer_hash
,
408 hash_table_pointer_compare
);
410 this->frag_color
= NULL
;
411 this->frag_data
= NULL
;
412 this->frag_depth
= NULL
;
413 this->first_non_payload_grf
= 0;
415 this->current_annotation
= NULL
;
416 this->annotation_string
= NULL
;
417 this->annotation_ir
= NULL
;
418 this->base_ir
= NULL
;
420 this->virtual_grf_sizes
= NULL
;
421 this->virtual_grf_next
= 1;
422 this->virtual_grf_array_size
= 0;
423 this->virtual_grf_def
= NULL
;
424 this->virtual_grf_use
= NULL
;
426 this->kill_emitted
= false;
431 talloc_free(this->mem_ctx
);
432 hash_table_dtor(this->variable_ht
);
435 fs_reg
*variable_storage(ir_variable
*var
);
436 int virtual_grf_alloc(int size
);
438 void visit(ir_variable
*ir
);
439 void visit(ir_assignment
*ir
);
440 void visit(ir_dereference_variable
*ir
);
441 void visit(ir_dereference_record
*ir
);
442 void visit(ir_dereference_array
*ir
);
443 void visit(ir_expression
*ir
);
444 void visit(ir_texture
*ir
);
445 void visit(ir_if
*ir
);
446 void visit(ir_constant
*ir
);
447 void visit(ir_swizzle
*ir
);
448 void visit(ir_return
*ir
);
449 void visit(ir_loop
*ir
);
450 void visit(ir_loop_jump
*ir
);
451 void visit(ir_discard
*ir
);
452 void visit(ir_call
*ir
);
453 void visit(ir_function
*ir
);
454 void visit(ir_function_signature
*ir
);
456 fs_inst
*emit(fs_inst inst
);
457 void assign_curb_setup();
458 void calculate_urb_setup();
459 void assign_urb_setup();
461 void assign_regs_trivial();
462 void calculate_live_intervals();
463 bool propagate_constants();
464 bool dead_code_eliminate();
465 bool virtual_grf_interferes(int a
, int b
);
466 void generate_code();
467 void generate_fb_write(fs_inst
*inst
);
468 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
469 struct brw_reg
*src
);
470 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
471 void generate_math(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg
*src
);
472 void generate_discard(fs_inst
*inst
, struct brw_reg temp
);
473 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
474 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
476 void emit_dummy_fs();
477 void emit_fragcoord_interpolation(ir_variable
*ir
);
478 void emit_general_interpolation(ir_variable
*ir
);
479 void emit_interpolation_setup_gen4();
480 void emit_interpolation_setup_gen6();
481 fs_inst
*emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
);
482 fs_inst
*emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
);
483 void emit_fb_writes();
484 void emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
485 const glsl_type
*type
, bool predicated
);
487 struct brw_reg
interp_reg(int location
, int channel
);
488 int setup_uniform_values(int loc
, const glsl_type
*type
);
489 void setup_builtin_uniform_values(ir_variable
*ir
);
491 struct brw_context
*brw
;
492 const struct gl_fragment_program
*fp
;
493 struct intel_context
*intel
;
495 struct brw_wm_compile
*c
;
496 struct brw_compile
*p
;
497 struct brw_shader
*shader
;
499 exec_list instructions
;
501 int *virtual_grf_sizes
;
502 int virtual_grf_next
;
503 int virtual_grf_array_size
;
504 int *virtual_grf_def
;
505 int *virtual_grf_use
;
507 struct hash_table
*variable_ht
;
508 ir_variable
*frag_color
, *frag_data
, *frag_depth
;
509 int first_non_payload_grf
;
510 int urb_setup
[FRAG_ATTRIB_MAX
];
513 /** @{ debug annotation info */
514 const char *current_annotation
;
515 ir_instruction
*base_ir
;
516 const char **annotation_string
;
517 ir_instruction
**annotation_ir
;
522 /* Result of last visit() method. */
537 fs_visitor::virtual_grf_alloc(int size
)
539 if (virtual_grf_array_size
<= virtual_grf_next
) {
540 if (virtual_grf_array_size
== 0)
541 virtual_grf_array_size
= 16;
543 virtual_grf_array_size
*= 2;
544 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
545 int, virtual_grf_array_size
);
547 /* This slot is always unused. */
548 virtual_grf_sizes
[0] = 0;
550 virtual_grf_sizes
[virtual_grf_next
] = size
;
551 return virtual_grf_next
++;
554 /** Fixed HW reg constructor. */
555 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
559 this->hw_reg
= hw_reg
;
560 this->type
= BRW_REGISTER_TYPE_F
;
564 brw_type_for_base_type(const struct glsl_type
*type
)
566 switch (type
->base_type
) {
567 case GLSL_TYPE_FLOAT
:
568 return BRW_REGISTER_TYPE_F
;
571 return BRW_REGISTER_TYPE_D
;
573 return BRW_REGISTER_TYPE_UD
;
574 case GLSL_TYPE_ARRAY
:
575 case GLSL_TYPE_STRUCT
:
576 /* These should be overridden with the type of the member when
577 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
578 * way to trip up if we don't.
580 return BRW_REGISTER_TYPE_UD
;
582 assert(!"not reached");
583 return BRW_REGISTER_TYPE_F
;
587 /** Automatic reg constructor. */
588 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
593 this->reg
= v
->virtual_grf_alloc(type_size(type
));
594 this->reg_offset
= 0;
595 this->type
= brw_type_for_base_type(type
);
599 fs_visitor::variable_storage(ir_variable
*var
)
601 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
604 /* Our support for uniforms is piggy-backed on the struct
605 * gl_fragment_program, because that's where the values actually
606 * get stored, rather than in some global gl_shader_program uniform
610 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
612 unsigned int offset
= 0;
615 if (type
->is_matrix()) {
616 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
617 type
->vector_elements
,
620 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
621 offset
+= setup_uniform_values(loc
+ offset
, column
);
627 switch (type
->base_type
) {
628 case GLSL_TYPE_FLOAT
:
632 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
633 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
634 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
638 case GLSL_TYPE_STRUCT
:
639 for (unsigned int i
= 0; i
< type
->length
; i
++) {
640 offset
+= setup_uniform_values(loc
+ offset
,
641 type
->fields
.structure
[i
].type
);
645 case GLSL_TYPE_ARRAY
:
646 for (unsigned int i
= 0; i
< type
->length
; i
++) {
647 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
651 case GLSL_TYPE_SAMPLER
:
652 /* The sampler takes up a slot, but we don't use any values from it. */
656 assert(!"not reached");
662 /* Our support for builtin uniforms is even scarier than non-builtin.
663 * It sits on top of the PROG_STATE_VAR parameters that are
664 * automatically updated from GL context state.
667 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
669 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
671 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
672 statevar
= &_mesa_builtin_uniform_desc
[i
];
673 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
677 if (!statevar
->name
) {
679 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
684 if (ir
->type
->is_array()) {
685 array_count
= ir
->type
->length
;
690 for (int a
= 0; a
< array_count
; a
++) {
691 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
692 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
693 int tokens
[STATE_LENGTH
];
695 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
696 if (ir
->type
->is_array()) {
700 /* This state reference has already been setup by ir_to_mesa,
701 * but we'll get the same index back here.
703 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
704 (gl_state_index
*)tokens
);
705 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
707 /* Add each of the unique swizzles of the element as a
708 * parameter. This'll end up matching the expected layout of
709 * the array/matrix/structure we're trying to fill in.
712 for (unsigned int i
= 0; i
< 4; i
++) {
713 int swiz
= GET_SWZ(element
->swizzle
, i
);
714 if (swiz
== last_swiz
)
718 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
725 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
727 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
729 fs_reg neg_y
= this->pixel_y
;
733 if (ir
->pixel_center_integer
) {
734 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
736 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
741 if (ir
->origin_upper_left
&& ir
->pixel_center_integer
) {
742 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
744 fs_reg pixel_y
= this->pixel_y
;
745 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
747 if (!ir
->origin_upper_left
) {
748 pixel_y
.negate
= true;
749 offset
+= c
->key
.drawable_height
- 1.0;
752 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
757 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
758 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
761 /* gl_FragCoord.w: Already set up in emit_interpolation */
762 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
764 hash_table_insert(this->variable_ht
, reg
, ir
);
769 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
771 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
772 /* Interpolation is always in floating point regs. */
773 reg
->type
= BRW_REGISTER_TYPE_F
;
776 unsigned int array_elements
;
777 const glsl_type
*type
;
779 if (ir
->type
->is_array()) {
780 array_elements
= ir
->type
->length
;
781 if (array_elements
== 0) {
784 type
= ir
->type
->fields
.array
;
790 int location
= ir
->location
;
791 for (unsigned int i
= 0; i
< array_elements
; i
++) {
792 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
793 if (urb_setup
[location
] == -1) {
794 /* If there's no incoming setup data for this slot, don't
795 * emit interpolation for it.
797 attr
.reg_offset
+= type
->vector_elements
;
802 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
803 struct brw_reg interp
= interp_reg(location
, c
);
804 emit(fs_inst(FS_OPCODE_LINTERP
,
811 attr
.reg_offset
-= type
->vector_elements
;
813 if (intel
->gen
< 6) {
814 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
815 emit(fs_inst(BRW_OPCODE_MUL
,
826 hash_table_insert(this->variable_ht
, reg
, ir
);
830 fs_visitor::visit(ir_variable
*ir
)
834 if (variable_storage(ir
))
837 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
838 this->frag_color
= ir
;
839 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
840 this->frag_data
= ir
;
841 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
842 this->frag_depth
= ir
;
845 if (ir
->mode
== ir_var_in
) {
846 if (!strcmp(ir
->name
, "gl_FragCoord")) {
847 emit_fragcoord_interpolation(ir
);
849 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
850 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
851 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
852 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
855 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
859 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
860 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
862 emit_general_interpolation(ir
);
867 if (ir
->mode
== ir_var_uniform
) {
868 int param_index
= c
->prog_data
.nr_params
;
870 if (!strncmp(ir
->name
, "gl_", 3)) {
871 setup_builtin_uniform_values(ir
);
873 setup_uniform_values(ir
->location
, ir
->type
);
876 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
880 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
882 hash_table_insert(this->variable_ht
, reg
, ir
);
886 fs_visitor::visit(ir_dereference_variable
*ir
)
888 fs_reg
*reg
= variable_storage(ir
->var
);
893 fs_visitor::visit(ir_dereference_record
*ir
)
895 const glsl_type
*struct_type
= ir
->record
->type
;
897 ir
->record
->accept(this);
899 unsigned int offset
= 0;
900 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
901 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
903 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
905 this->result
.reg_offset
+= offset
;
906 this->result
.type
= brw_type_for_base_type(ir
->type
);
910 fs_visitor::visit(ir_dereference_array
*ir
)
915 ir
->array
->accept(this);
916 index
= ir
->array_index
->as_constant();
918 element_size
= type_size(ir
->type
);
919 this->result
.type
= brw_type_for_base_type(ir
->type
);
922 assert(this->result
.file
== UNIFORM
||
923 (this->result
.file
== GRF
&&
924 this->result
.reg
!= 0));
925 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
927 assert(!"FINISHME: non-constant array element");
932 fs_visitor::visit(ir_expression
*ir
)
934 unsigned int operand
;
939 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
940 ir
->operands
[operand
]->accept(this);
941 if (this->result
.file
== BAD_FILE
) {
943 printf("Failed to get tree for expression operand:\n");
944 ir
->operands
[operand
]->accept(&v
);
947 op
[operand
] = this->result
;
949 /* Matrix expression operands should have been broken down to vector
950 * operations already.
952 assert(!ir
->operands
[operand
]->type
->is_matrix());
953 /* And then those vector operands should have been broken down to scalar.
955 assert(!ir
->operands
[operand
]->type
->is_vector());
958 /* Storage for our result. If our result goes into an assignment, it will
959 * just get copy-propagated out, so no worries.
961 this->result
= fs_reg(this, ir
->type
);
963 switch (ir
->operation
) {
964 case ir_unop_logic_not
:
965 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
968 op
[0].negate
= !op
[0].negate
;
969 this->result
= op
[0];
973 this->result
= op
[0];
976 temp
= fs_reg(this, ir
->type
);
978 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
980 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
981 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
982 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
983 inst
->predicated
= true;
985 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
986 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
987 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
988 inst
->predicated
= true;
992 emit(fs_inst(FS_OPCODE_RCP
, this->result
, op
[0]));
996 emit(fs_inst(FS_OPCODE_EXP2
, this->result
, op
[0]));
999 emit(fs_inst(FS_OPCODE_LOG2
, this->result
, op
[0]));
1003 assert(!"not reached: should be handled by ir_explog_to_explog2");
1006 emit(fs_inst(FS_OPCODE_SIN
, this->result
, op
[0]));
1009 emit(fs_inst(FS_OPCODE_COS
, this->result
, op
[0]));
1013 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
1016 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
1020 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
1023 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1027 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
1030 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1033 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1037 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1038 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1039 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1041 case ir_binop_greater
:
1042 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1043 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1044 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1046 case ir_binop_lequal
:
1047 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1048 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1049 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1051 case ir_binop_gequal
:
1052 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1053 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1054 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1056 case ir_binop_equal
:
1057 case ir_binop_all_equal
: /* same as nequal for scalars */
1058 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1059 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1060 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1062 case ir_binop_nequal
:
1063 case ir_binop_any_nequal
: /* same as nequal for scalars */
1064 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1065 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1066 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1069 case ir_binop_logic_xor
:
1070 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
1073 case ir_binop_logic_or
:
1074 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
1077 case ir_binop_logic_and
:
1078 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
1082 case ir_binop_cross
:
1084 assert(!"not reached: should be handled by brw_fs_channel_expressions");
1088 assert(!"not reached: should be handled by lower_noise");
1092 emit(fs_inst(FS_OPCODE_SQRT
, this->result
, op
[0]));
1096 emit(fs_inst(FS_OPCODE_RSQ
, this->result
, op
[0]));
1102 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1105 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1109 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
1110 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1113 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1116 op
[0].negate
= ~op
[0].negate
;
1117 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1118 this->result
.negate
= true;
1121 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1124 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
1128 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1129 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1131 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1132 inst
->predicated
= true;
1135 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1136 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1138 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1139 inst
->predicated
= true;
1143 inst
= emit(fs_inst(FS_OPCODE_POW
, this->result
, op
[0], op
[1]));
1146 case ir_unop_bit_not
:
1148 case ir_binop_lshift
:
1149 case ir_binop_rshift
:
1150 case ir_binop_bit_and
:
1151 case ir_binop_bit_xor
:
1152 case ir_binop_bit_or
:
1153 assert(!"GLSL 1.30 features unsupported");
1159 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1160 const glsl_type
*type
, bool predicated
)
1162 switch (type
->base_type
) {
1163 case GLSL_TYPE_FLOAT
:
1164 case GLSL_TYPE_UINT
:
1166 case GLSL_TYPE_BOOL
:
1167 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1168 l
.type
= brw_type_for_base_type(type
);
1169 r
.type
= brw_type_for_base_type(type
);
1171 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1172 inst
->predicated
= predicated
;
1178 case GLSL_TYPE_ARRAY
:
1179 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1180 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1183 case GLSL_TYPE_STRUCT
:
1184 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1185 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1190 case GLSL_TYPE_SAMPLER
:
1194 assert(!"not reached");
1200 fs_visitor::visit(ir_assignment
*ir
)
1205 /* FINISHME: arrays on the lhs */
1206 ir
->lhs
->accept(this);
1209 ir
->rhs
->accept(this);
1212 assert(l
.file
!= BAD_FILE
);
1213 assert(r
.file
!= BAD_FILE
);
1215 if (ir
->condition
) {
1216 /* Get the condition bool into the predicate. */
1217 ir
->condition
->accept(this);
1218 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, this->result
, fs_reg(0)));
1219 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1222 if (ir
->lhs
->type
->is_scalar() ||
1223 ir
->lhs
->type
->is_vector()) {
1224 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1225 if (ir
->write_mask
& (1 << i
)) {
1226 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1228 inst
->predicated
= true;
1234 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1239 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1243 bool simd16
= false;
1246 if (ir
->shadow_comparitor
) {
1247 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1248 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1250 coordinate
.reg_offset
++;
1252 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1255 if (ir
->op
== ir_tex
) {
1256 /* There's no plain shadow compare message, so we use shadow
1257 * compare with a bias of 0.0.
1259 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1262 } else if (ir
->op
== ir_txb
) {
1263 ir
->lod_info
.bias
->accept(this);
1264 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1268 assert(ir
->op
== ir_txl
);
1269 ir
->lod_info
.lod
->accept(this);
1270 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1275 ir
->shadow_comparitor
->accept(this);
1276 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1278 } else if (ir
->op
== ir_tex
) {
1279 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1280 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1282 coordinate
.reg_offset
++;
1284 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1287 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1288 * instructions. We'll need to do SIMD16 here.
1290 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1292 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
* 2;) {
1293 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1295 coordinate
.reg_offset
++;
1298 /* The unused upper half. */
1302 /* lod/bias appears after u/v/r. */
1305 if (ir
->op
== ir_txb
) {
1306 ir
->lod_info
.bias
->accept(this);
1307 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1311 ir
->lod_info
.lod
->accept(this);
1312 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1317 /* The unused upper half. */
1320 /* Now, since we're doing simd16, the return is 2 interleaved
1321 * vec4s where the odd-indexed ones are junk. We'll need to move
1322 * this weirdness around to the expected layout.
1326 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1328 dst
.type
= BRW_REGISTER_TYPE_F
;
1331 fs_inst
*inst
= NULL
;
1334 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
1337 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
1340 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
1344 assert(!"GLSL 1.30 features unsupported");
1350 for (int i
= 0; i
< 4; i
++) {
1351 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1352 orig_dst
.reg_offset
++;
1353 dst
.reg_offset
+= 2;
1361 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1363 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1364 * optional parameters like shadow comparitor or LOD bias. If
1365 * optional parameters aren't present, those base slots are
1366 * optional and don't need to be included in the message.
1368 * We don't fill in the unnecessary slots regardless, which may
1369 * look surprising in the disassembly.
1374 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1375 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1376 coordinate
.reg_offset
++;
1379 if (ir
->shadow_comparitor
) {
1380 mlen
= MAX2(mlen
, 4);
1382 ir
->shadow_comparitor
->accept(this);
1383 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1387 fs_inst
*inst
= NULL
;
1390 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
1393 ir
->lod_info
.bias
->accept(this);
1394 mlen
= MAX2(mlen
, 4);
1395 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1398 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
1401 ir
->lod_info
.lod
->accept(this);
1402 mlen
= MAX2(mlen
, 4);
1403 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1406 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
1410 assert(!"GLSL 1.30 features unsupported");
1419 fs_visitor::visit(ir_texture
*ir
)
1421 fs_inst
*inst
= NULL
;
1423 ir
->coordinate
->accept(this);
1424 fs_reg coordinate
= this->result
;
1426 /* Should be lowered by do_lower_texture_projection */
1427 assert(!ir
->projector
);
1429 /* Writemasking doesn't eliminate channels on SIMD8 texture
1430 * samples, so don't worry about them.
1432 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1434 if (intel
->gen
< 5) {
1435 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1437 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1441 _mesa_get_sampler_uniform_value(ir
->sampler
,
1442 ctx
->Shader
.CurrentProgram
,
1443 &brw
->fragment_program
->Base
);
1444 inst
->sampler
= c
->fp
->program
.Base
.SamplerUnits
[inst
->sampler
];
1448 if (ir
->shadow_comparitor
)
1449 inst
->shadow_compare
= true;
1451 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1452 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1454 for (int i
= 0; i
< 4; i
++) {
1455 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1456 fs_reg l
= swizzle_dst
;
1459 if (swiz
== SWIZZLE_ZERO
) {
1460 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1461 } else if (swiz
== SWIZZLE_ONE
) {
1462 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1465 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1466 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1469 this->result
= swizzle_dst
;
1474 fs_visitor::visit(ir_swizzle
*ir
)
1476 ir
->val
->accept(this);
1477 fs_reg val
= this->result
;
1479 if (ir
->type
->vector_elements
== 1) {
1480 this->result
.reg_offset
+= ir
->mask
.x
;
1484 fs_reg result
= fs_reg(this, ir
->type
);
1485 this->result
= result
;
1487 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1488 fs_reg channel
= val
;
1506 channel
.reg_offset
+= swiz
;
1507 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1508 result
.reg_offset
++;
1513 fs_visitor::visit(ir_discard
*ir
)
1515 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1517 assert(ir
->condition
== NULL
); /* FINISHME */
1519 emit(fs_inst(FS_OPCODE_DISCARD
, temp
, temp
));
1520 kill_emitted
= true;
1524 fs_visitor::visit(ir_constant
*ir
)
1526 fs_reg
reg(this, ir
->type
);
1529 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1530 switch (ir
->type
->base_type
) {
1531 case GLSL_TYPE_FLOAT
:
1532 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1534 case GLSL_TYPE_UINT
:
1535 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1538 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1540 case GLSL_TYPE_BOOL
:
1541 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1544 assert(!"Non-float/uint/int/bool constant");
1551 fs_visitor::visit(ir_if
*ir
)
1555 /* Don't point the annotation at the if statement, because then it plus
1556 * the then and else blocks get printed.
1558 this->base_ir
= ir
->condition
;
1560 /* Generate the condition into the condition code. */
1561 ir
->condition
->accept(this);
1562 inst
= emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(brw_null_reg()), this->result
));
1563 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1565 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1566 inst
->predicated
= true;
1568 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1569 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1575 if (!ir
->else_instructions
.is_empty()) {
1576 emit(fs_inst(BRW_OPCODE_ELSE
));
1578 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1579 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1586 emit(fs_inst(BRW_OPCODE_ENDIF
));
1590 fs_visitor::visit(ir_loop
*ir
)
1592 fs_reg counter
= reg_undef
;
1595 this->base_ir
= ir
->counter
;
1596 ir
->counter
->accept(this);
1597 counter
= *(variable_storage(ir
->counter
));
1600 this->base_ir
= ir
->from
;
1601 ir
->from
->accept(this);
1603 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1607 emit(fs_inst(BRW_OPCODE_DO
));
1610 this->base_ir
= ir
->to
;
1611 ir
->to
->accept(this);
1613 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
,
1614 counter
, this->result
));
1616 case ir_binop_equal
:
1617 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1619 case ir_binop_nequal
:
1620 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1622 case ir_binop_gequal
:
1623 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1625 case ir_binop_lequal
:
1626 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1628 case ir_binop_greater
:
1629 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1632 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1635 assert(!"not reached: unknown loop condition");
1640 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1641 inst
->predicated
= true;
1644 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1645 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1651 if (ir
->increment
) {
1652 this->base_ir
= ir
->increment
;
1653 ir
->increment
->accept(this);
1654 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1657 emit(fs_inst(BRW_OPCODE_WHILE
));
1661 fs_visitor::visit(ir_loop_jump
*ir
)
1664 case ir_loop_jump::jump_break
:
1665 emit(fs_inst(BRW_OPCODE_BREAK
));
1667 case ir_loop_jump::jump_continue
:
1668 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1674 fs_visitor::visit(ir_call
*ir
)
1676 assert(!"FINISHME");
1680 fs_visitor::visit(ir_return
*ir
)
1682 assert(!"FINISHME");
1686 fs_visitor::visit(ir_function
*ir
)
1688 /* Ignore function bodies other than main() -- we shouldn't see calls to
1689 * them since they should all be inlined before we get to ir_to_mesa.
1691 if (strcmp(ir
->name
, "main") == 0) {
1692 const ir_function_signature
*sig
;
1695 sig
= ir
->matching_signature(&empty
);
1699 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1700 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1709 fs_visitor::visit(ir_function_signature
*ir
)
1711 assert(!"not reached");
1716 fs_visitor::emit(fs_inst inst
)
1718 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1721 list_inst
->annotation
= this->current_annotation
;
1722 list_inst
->ir
= this->base_ir
;
1724 this->instructions
.push_tail(list_inst
);
1729 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1731 fs_visitor::emit_dummy_fs()
1733 /* Everyone's favorite color. */
1734 emit(fs_inst(BRW_OPCODE_MOV
,
1737 emit(fs_inst(BRW_OPCODE_MOV
,
1740 emit(fs_inst(BRW_OPCODE_MOV
,
1743 emit(fs_inst(BRW_OPCODE_MOV
,
1748 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1753 /* The register location here is relative to the start of the URB
1754 * data. It will get adjusted to be a real location before
1755 * generate_code() time.
1758 fs_visitor::interp_reg(int location
, int channel
)
1760 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1761 int stride
= (channel
& 1) * 4;
1763 assert(urb_setup
[location
] != -1);
1765 return brw_vec1_grf(regnr
, stride
);
1768 /** Emits the interpolation for the varying inputs. */
1770 fs_visitor::emit_interpolation_setup_gen4()
1772 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1774 this->current_annotation
= "compute pixel centers";
1775 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1776 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1777 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1778 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1779 emit(fs_inst(BRW_OPCODE_ADD
,
1781 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1782 fs_reg(brw_imm_v(0x10101010))));
1783 emit(fs_inst(BRW_OPCODE_ADD
,
1785 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1786 fs_reg(brw_imm_v(0x11001100))));
1788 this->current_annotation
= "compute pixel deltas from v0";
1790 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1791 this->delta_y
= this->delta_x
;
1792 this->delta_y
.reg_offset
++;
1794 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1795 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1797 emit(fs_inst(BRW_OPCODE_ADD
,
1800 fs_reg(negate(brw_vec1_grf(1, 0)))));
1801 emit(fs_inst(BRW_OPCODE_ADD
,
1804 fs_reg(negate(brw_vec1_grf(1, 1)))));
1806 this->current_annotation
= "compute pos.w and 1/pos.w";
1807 /* Compute wpos.w. It's always in our setup, since it's needed to
1808 * interpolate the other attributes.
1810 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1811 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1812 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1813 /* Compute the pixel 1/W value from wpos.w. */
1814 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1815 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
));
1816 this->current_annotation
= NULL
;
1819 /** Emits the interpolation for the varying inputs. */
1821 fs_visitor::emit_interpolation_setup_gen6()
1823 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1825 /* If the pixel centers end up used, the setup is the same as for gen4. */
1826 this->current_annotation
= "compute pixel centers";
1827 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1828 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1829 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1830 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1831 emit(fs_inst(BRW_OPCODE_ADD
,
1833 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1834 fs_reg(brw_imm_v(0x10101010))));
1835 emit(fs_inst(BRW_OPCODE_ADD
,
1837 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1838 fs_reg(brw_imm_v(0x11001100))));
1840 this->current_annotation
= "compute 1/pos.w";
1841 this->wpos_w
= fs_reg(brw_vec8_grf(c
->key
.source_w_reg
, 0));
1842 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1843 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
));
1845 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1846 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1848 this->current_annotation
= NULL
;
1852 fs_visitor::emit_fb_writes()
1854 this->current_annotation
= "FB write header";
1855 GLboolean header_present
= GL_TRUE
;
1858 if (intel
->gen
>= 6 &&
1859 !this->kill_emitted
&&
1860 c
->key
.nr_color_regions
== 1) {
1861 header_present
= false;
1864 if (header_present
) {
1869 if (c
->key
.aa_dest_stencil_reg
) {
1870 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1871 fs_reg(brw_vec8_grf(c
->key
.aa_dest_stencil_reg
, 0))));
1874 /* Reserve space for color. It'll be filled in per MRT below. */
1878 if (c
->key
.source_depth_to_render_target
) {
1879 if (c
->key
.computes_depth
) {
1880 /* Hand over gl_FragDepth. */
1881 assert(this->frag_depth
);
1882 fs_reg depth
= *(variable_storage(this->frag_depth
));
1884 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
1886 /* Pass through the payload depth. */
1887 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1888 fs_reg(brw_vec8_grf(c
->key
.source_depth_reg
, 0))));
1892 if (c
->key
.dest_depth_reg
) {
1893 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1894 fs_reg(brw_vec8_grf(c
->key
.dest_depth_reg
, 0))));
1897 fs_reg color
= reg_undef
;
1898 if (this->frag_color
)
1899 color
= *(variable_storage(this->frag_color
));
1900 else if (this->frag_data
)
1901 color
= *(variable_storage(this->frag_data
));
1903 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1904 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1905 "FB write target %d",
1907 if (this->frag_color
|| this->frag_data
) {
1908 for (int i
= 0; i
< 4; i
++) {
1909 emit(fs_inst(BRW_OPCODE_MOV
,
1910 fs_reg(MRF
, color_mrf
+ i
),
1916 if (this->frag_color
)
1917 color
.reg_offset
-= 4;
1919 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1920 reg_undef
, reg_undef
));
1921 inst
->target
= target
;
1923 if (target
== c
->key
.nr_color_regions
- 1)
1925 inst
->header_present
= header_present
;
1928 if (c
->key
.nr_color_regions
== 0) {
1929 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1930 reg_undef
, reg_undef
));
1933 inst
->header_present
= header_present
;
1936 this->current_annotation
= NULL
;
1940 fs_visitor::generate_fb_write(fs_inst
*inst
)
1942 GLboolean eot
= inst
->eot
;
1943 struct brw_reg implied_header
;
1945 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1948 brw_push_insn_state(p
);
1949 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1950 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1952 if (inst
->header_present
) {
1953 if (intel
->gen
>= 6) {
1956 brw_vec8_grf(0, 0));
1957 implied_header
= brw_null_reg();
1959 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1964 brw_vec8_grf(1, 0));
1966 implied_header
= brw_null_reg();
1969 brw_pop_insn_state(p
);
1972 8, /* dispatch_width */
1973 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
1983 fs_visitor::generate_linterp(fs_inst
*inst
,
1984 struct brw_reg dst
, struct brw_reg
*src
)
1986 struct brw_reg delta_x
= src
[0];
1987 struct brw_reg delta_y
= src
[1];
1988 struct brw_reg interp
= src
[2];
1991 delta_y
.nr
== delta_x
.nr
+ 1 &&
1992 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
1993 brw_PLN(p
, dst
, interp
, delta_x
);
1995 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
1996 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2001 fs_visitor::generate_math(fs_inst
*inst
,
2002 struct brw_reg dst
, struct brw_reg
*src
)
2006 switch (inst
->opcode
) {
2008 op
= BRW_MATH_FUNCTION_INV
;
2011 op
= BRW_MATH_FUNCTION_RSQ
;
2013 case FS_OPCODE_SQRT
:
2014 op
= BRW_MATH_FUNCTION_SQRT
;
2016 case FS_OPCODE_EXP2
:
2017 op
= BRW_MATH_FUNCTION_EXP
;
2019 case FS_OPCODE_LOG2
:
2020 op
= BRW_MATH_FUNCTION_LOG
;
2023 op
= BRW_MATH_FUNCTION_POW
;
2026 op
= BRW_MATH_FUNCTION_SIN
;
2029 op
= BRW_MATH_FUNCTION_COS
;
2032 assert(!"not reached: unknown math function");
2037 if (inst
->opcode
== FS_OPCODE_POW
) {
2038 brw_MOV(p
, brw_message_reg(3), src
[1]);
2043 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2044 BRW_MATH_SATURATE_NONE
,
2046 BRW_MATH_DATA_VECTOR
,
2047 BRW_MATH_PRECISION_FULL
);
2051 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2055 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2057 if (intel
->gen
== 5) {
2058 switch (inst
->opcode
) {
2060 if (inst
->shadow_compare
) {
2061 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2063 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2067 if (inst
->shadow_compare
) {
2068 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2070 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2075 switch (inst
->opcode
) {
2077 /* Note that G45 and older determines shadow compare and dispatch width
2078 * from message length for most messages.
2080 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2081 if (inst
->shadow_compare
) {
2082 assert(inst
->mlen
== 5);
2084 assert(inst
->mlen
<= 6);
2088 if (inst
->shadow_compare
) {
2089 assert(inst
->mlen
== 5);
2090 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2092 assert(inst
->mlen
== 8);
2093 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2094 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2099 assert(msg_type
!= -1);
2101 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2110 retype(dst
, BRW_REGISTER_TYPE_UW
),
2112 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2113 SURF_INDEX_TEXTURE(inst
->sampler
),
2125 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2128 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2130 * and we're trying to produce:
2133 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2134 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2135 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2136 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2137 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2138 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2139 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2140 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2142 * and add another set of two more subspans if in 16-pixel dispatch mode.
2144 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2145 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2146 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2147 * between each other. We could probably do it like ddx and swizzle the right
2148 * order later, but bail for now and just produce
2149 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2152 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2154 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2155 BRW_REGISTER_TYPE_F
,
2156 BRW_VERTICAL_STRIDE_2
,
2158 BRW_HORIZONTAL_STRIDE_0
,
2159 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2160 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2161 BRW_REGISTER_TYPE_F
,
2162 BRW_VERTICAL_STRIDE_2
,
2164 BRW_HORIZONTAL_STRIDE_0
,
2165 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2166 brw_ADD(p
, dst
, src0
, negate(src1
));
2170 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2172 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2173 BRW_REGISTER_TYPE_F
,
2174 BRW_VERTICAL_STRIDE_4
,
2176 BRW_HORIZONTAL_STRIDE_0
,
2177 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2178 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2179 BRW_REGISTER_TYPE_F
,
2180 BRW_VERTICAL_STRIDE_4
,
2182 BRW_HORIZONTAL_STRIDE_0
,
2183 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2184 brw_ADD(p
, dst
, src0
, negate(src1
));
2188 fs_visitor::generate_discard(fs_inst
*inst
, struct brw_reg temp
)
2190 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2191 temp
= brw_uw1_reg(temp
.file
, temp
.nr
, 0);
2193 brw_push_insn_state(p
);
2194 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2195 brw_NOT(p
, temp
, brw_mask_reg(1)); /* IMASK */
2196 brw_AND(p
, g0
, temp
, g0
);
2197 brw_pop_insn_state(p
);
2201 fs_visitor::assign_curb_setup()
2203 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
2204 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2206 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2207 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2208 fs_inst
*inst
= (fs_inst
*)iter
.get();
2210 for (unsigned int i
= 0; i
< 3; i
++) {
2211 if (inst
->src
[i
].file
== UNIFORM
) {
2212 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2213 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2217 inst
->src
[i
].file
= FIXED_HW_REG
;
2218 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
2225 fs_visitor::calculate_urb_setup()
2227 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2232 /* Figure out where each of the incoming setup attributes lands. */
2233 if (intel
->gen
>= 6) {
2234 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2235 if (i
== FRAG_ATTRIB_WPOS
||
2236 (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
))) {
2237 urb_setup
[i
] = urb_next
++;
2241 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2242 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2243 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2246 if (i
>= VERT_RESULT_VAR0
)
2247 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2248 else if (i
<= VERT_RESULT_TEX7
)
2254 urb_setup
[fp_index
] = urb_next
++;
2259 /* Each attribute is 4 setup channels, each of which is half a reg. */
2260 c
->prog_data
.urb_read_length
= urb_next
* 2;
2264 fs_visitor::assign_urb_setup()
2266 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2268 /* Offset all the urb_setup[] index by the actual position of the
2269 * setup regs, now that the location of the constants has been chosen.
2271 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2272 fs_inst
*inst
= (fs_inst
*)iter
.get();
2274 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2277 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2279 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2282 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2286 assign_reg(int *reg_hw_locations
, fs_reg
*reg
)
2288 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
2289 reg
->hw_reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
;
2295 fs_visitor::assign_regs_trivial()
2298 int hw_reg_mapping
[this->virtual_grf_next
];
2301 hw_reg_mapping
[0] = 0;
2302 hw_reg_mapping
[1] = this->first_non_payload_grf
;
2303 for (i
= 2; i
< this->virtual_grf_next
; i
++) {
2304 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
2305 this->virtual_grf_sizes
[i
- 1]);
2307 last_grf
= hw_reg_mapping
[i
- 1] + this->virtual_grf_sizes
[i
- 1];
2309 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2310 fs_inst
*inst
= (fs_inst
*)iter
.get();
2312 assign_reg(hw_reg_mapping
, &inst
->dst
);
2313 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2314 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2317 this->grf_used
= last_grf
+ 1;
2321 fs_visitor::assign_regs()
2324 int hw_reg_mapping
[this->virtual_grf_next
+ 1];
2325 int base_reg_count
= BRW_MAX_GRF
- this->first_non_payload_grf
;
2326 int class_sizes
[base_reg_count
];
2327 int class_count
= 0;
2328 int aligned_pair_class
= -1;
2330 /* Set up the register classes.
2332 * The base registers store a scalar value. For texture samples,
2333 * we get virtual GRFs composed of 4 contiguous hw register. For
2334 * structures and arrays, we store them as contiguous larger things
2335 * than that, though we should be able to do better most of the
2338 class_sizes
[class_count
++] = 1;
2339 if (brw
->has_pln
&& intel
->gen
< 6) {
2340 /* Always set up the (unaligned) pairs for gen5, so we can find
2341 * them for making the aligned pair class.
2343 class_sizes
[class_count
++] = 2;
2345 for (int r
= 1; r
< this->virtual_grf_next
; r
++) {
2348 for (i
= 0; i
< class_count
; i
++) {
2349 if (class_sizes
[i
] == this->virtual_grf_sizes
[r
])
2352 if (i
== class_count
) {
2353 if (this->virtual_grf_sizes
[r
] >= base_reg_count
) {
2354 fprintf(stderr
, "Object too large to register allocate.\n");
2358 class_sizes
[class_count
++] = this->virtual_grf_sizes
[r
];
2362 int ra_reg_count
= 0;
2363 int class_base_reg
[class_count
];
2364 int class_reg_count
[class_count
];
2365 int classes
[class_count
+ 1];
2367 for (int i
= 0; i
< class_count
; i
++) {
2368 class_base_reg
[i
] = ra_reg_count
;
2369 class_reg_count
[i
] = base_reg_count
- (class_sizes
[i
] - 1);
2370 ra_reg_count
+= class_reg_count
[i
];
2373 struct ra_regs
*regs
= ra_alloc_reg_set(ra_reg_count
);
2374 for (int i
= 0; i
< class_count
; i
++) {
2375 classes
[i
] = ra_alloc_reg_class(regs
);
2377 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2378 ra_class_add_reg(regs
, classes
[i
], class_base_reg
[i
] + i_r
);
2381 /* Add conflicts between our contiguous registers aliasing
2382 * base regs and other register classes' contiguous registers
2383 * that alias base regs, or the base regs themselves for classes[0].
2385 for (int c
= 0; c
<= i
; c
++) {
2386 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2387 for (int c_r
= MAX2(0, i_r
- (class_sizes
[c
] - 1));
2388 c_r
< MIN2(class_reg_count
[c
], i_r
+ class_sizes
[i
]);
2392 printf("%d/%d conflicts %d/%d\n",
2393 class_sizes
[i
], this->first_non_payload_grf
+ i_r
,
2394 class_sizes
[c
], this->first_non_payload_grf
+ c_r
);
2397 ra_add_reg_conflict(regs
,
2398 class_base_reg
[i
] + i_r
,
2399 class_base_reg
[c
] + c_r
);
2405 /* Add a special class for aligned pairs, which we'll put delta_x/y
2406 * in on gen5 so that we can do PLN.
2408 if (brw
->has_pln
&& intel
->gen
< 6) {
2409 int reg_count
= (base_reg_count
- 1) / 2;
2410 int unaligned_pair_class
= 1;
2411 assert(class_sizes
[unaligned_pair_class
] == 2);
2413 aligned_pair_class
= class_count
;
2414 classes
[aligned_pair_class
] = ra_alloc_reg_class(regs
);
2415 class_base_reg
[aligned_pair_class
] = 0;
2416 class_reg_count
[aligned_pair_class
] = 0;
2417 int start
= (this->first_non_payload_grf
& 1) ? 1 : 0;
2419 for (int i
= 0; i
< reg_count
; i
++) {
2420 ra_class_add_reg(regs
, classes
[aligned_pair_class
],
2421 class_base_reg
[unaligned_pair_class
] + i
* 2 + start
);
2426 ra_set_finalize(regs
);
2428 struct ra_graph
*g
= ra_alloc_interference_graph(regs
,
2429 this->virtual_grf_next
);
2430 /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
2433 ra_set_node_class(g
, 0, classes
[0]);
2435 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2436 for (int c
= 0; c
< class_count
; c
++) {
2437 if (class_sizes
[c
] == this->virtual_grf_sizes
[i
]) {
2438 if (aligned_pair_class
>= 0 &&
2439 this->delta_x
.reg
== i
) {
2440 ra_set_node_class(g
, i
, classes
[aligned_pair_class
]);
2442 ra_set_node_class(g
, i
, classes
[c
]);
2448 for (int j
= 1; j
< i
; j
++) {
2449 if (virtual_grf_interferes(i
, j
)) {
2450 ra_add_node_interference(g
, i
, j
);
2455 /* FINISHME: Handle spilling */
2456 if (!ra_allocate_no_spills(g
)) {
2457 fprintf(stderr
, "Failed to allocate registers.\n");
2462 /* Get the chosen virtual registers for each node, and map virtual
2463 * regs in the register classes back down to real hardware reg
2466 hw_reg_mapping
[0] = 0; /* unused */
2467 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2468 int reg
= ra_get_node_reg(g
, i
);
2471 for (int c
= 0; c
< class_count
; c
++) {
2472 if (reg
>= class_base_reg
[c
] &&
2473 reg
< class_base_reg
[c
] + class_reg_count
[c
]) {
2474 hw_reg
= reg
- class_base_reg
[c
];
2479 assert(hw_reg
!= -1);
2480 hw_reg_mapping
[i
] = this->first_non_payload_grf
+ hw_reg
;
2481 last_grf
= MAX2(last_grf
,
2482 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
] - 1);
2485 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2486 fs_inst
*inst
= (fs_inst
*)iter
.get();
2488 assign_reg(hw_reg_mapping
, &inst
->dst
);
2489 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2490 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2493 this->grf_used
= last_grf
+ 1;
2500 fs_visitor::calculate_live_intervals()
2502 int num_vars
= this->virtual_grf_next
;
2503 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2504 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2508 for (int i
= 0; i
< num_vars
; i
++) {
2514 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2515 fs_inst
*inst
= (fs_inst
*)iter
.get();
2517 if (inst
->opcode
== BRW_OPCODE_DO
) {
2518 if (loop_depth
++ == 0)
2520 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2523 if (loop_depth
== 0) {
2526 * Patches up any vars marked for use within the loop as
2527 * live until the end. This is conservative, as there
2528 * will often be variables defined and used inside the
2529 * loop but dead at the end of the loop body.
2531 for (int i
= 0; i
< num_vars
; i
++) {
2532 if (use
[i
] == loop_start
) {
2543 for (unsigned int i
= 0; i
< 3; i
++) {
2544 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2545 use
[inst
->src
[i
].reg
] = MAX2(use
[inst
->src
[i
].reg
], eip
);
2548 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2549 def
[inst
->dst
.reg
] = MIN2(def
[inst
->dst
.reg
], eip
);
2556 talloc_free(this->virtual_grf_def
);
2557 talloc_free(this->virtual_grf_use
);
2558 this->virtual_grf_def
= def
;
2559 this->virtual_grf_use
= use
;
2563 * Attempts to move immediate constants into the immediate
2564 * constant slot of following instructions.
2566 * Immediate constants are a bit tricky -- they have to be in the last
2567 * operand slot, you can't do abs/negate on them,
2571 fs_visitor::propagate_constants()
2573 bool progress
= false;
2575 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2576 fs_inst
*inst
= (fs_inst
*)iter
.get();
2578 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2580 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2581 inst
->dst
.type
!= inst
->src
[0].type
)
2584 /* Don't bother with cases where we should have had the
2585 * operation on the constant folded in GLSL already.
2590 /* Found a move of a constant to a GRF. Find anything else using the GRF
2591 * before it's written, and replace it with the constant if we can.
2593 exec_list_iterator scan_iter
= iter
;
2595 for (; scan_iter
.has_next(); scan_iter
.next()) {
2596 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2598 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2599 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2600 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2601 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2605 for (int i
= 2; i
>= 0; i
--) {
2606 if (scan_inst
->src
[i
].file
!= GRF
||
2607 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2608 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2611 /* Don't bother with cases where we should have had the
2612 * operation on the constant folded in GLSL already.
2614 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2617 switch (scan_inst
->opcode
) {
2618 case BRW_OPCODE_MOV
:
2619 scan_inst
->src
[i
] = inst
->src
[0];
2623 case BRW_OPCODE_MUL
:
2624 case BRW_OPCODE_ADD
:
2626 scan_inst
->src
[i
] = inst
->src
[0];
2628 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2629 /* Fit this constant in by commuting the operands */
2630 scan_inst
->src
[0] = scan_inst
->src
[1];
2631 scan_inst
->src
[1] = inst
->src
[0];
2634 case BRW_OPCODE_CMP
:
2636 scan_inst
->src
[i
] = inst
->src
[0];
2642 if (scan_inst
->dst
.file
== GRF
&&
2643 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2644 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2645 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2654 * Must be called after calculate_live_intervales() to remove unused
2655 * writes to registers -- register allocation will fail otherwise
2656 * because something deffed but not used won't be considered to
2657 * interfere with other regs.
2660 fs_visitor::dead_code_eliminate()
2662 bool progress
= false;
2663 int num_vars
= this->virtual_grf_next
;
2664 bool dead
[num_vars
];
2666 for (int i
= 0; i
< num_vars
; i
++) {
2667 /* This would be ">=", but FS_OPCODE_DISCARD has a src == dst where
2668 * it writes dst then reads it as src.
2670 dead
[i
] = this->virtual_grf_def
[i
] > this->virtual_grf_use
[i
];
2673 /* Mark off its interval so it won't interfere with anything. */
2674 this->virtual_grf_def
[i
] = -1;
2675 this->virtual_grf_use
[i
] = -1;
2679 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2680 fs_inst
*inst
= (fs_inst
*)iter
.get();
2682 if (inst
->dst
.file
== GRF
&& dead
[inst
->dst
.reg
]) {
2692 fs_visitor::virtual_grf_interferes(int a
, int b
)
2694 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
2695 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
2697 /* For dead code, just check if the def interferes with the other range. */
2698 if (this->virtual_grf_use
[a
] == -1) {
2699 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
2700 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
2702 if (this->virtual_grf_use
[b
] == -1) {
2703 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
2704 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
2707 return start
<= end
;
2710 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
2712 struct brw_reg brw_reg
;
2714 switch (reg
->file
) {
2718 brw_reg
= brw_vec8_reg(reg
->file
,
2720 brw_reg
= retype(brw_reg
, reg
->type
);
2723 switch (reg
->type
) {
2724 case BRW_REGISTER_TYPE_F
:
2725 brw_reg
= brw_imm_f(reg
->imm
.f
);
2727 case BRW_REGISTER_TYPE_D
:
2728 brw_reg
= brw_imm_d(reg
->imm
.i
);
2730 case BRW_REGISTER_TYPE_UD
:
2731 brw_reg
= brw_imm_ud(reg
->imm
.u
);
2734 assert(!"not reached");
2739 brw_reg
= reg
->fixed_hw_reg
;
2742 /* Probably unused. */
2743 brw_reg
= brw_null_reg();
2746 assert(!"not reached");
2747 brw_reg
= brw_null_reg();
2751 brw_reg
= brw_abs(brw_reg
);
2753 brw_reg
= negate(brw_reg
);
2759 fs_visitor::generate_code()
2761 unsigned int annotation_len
= 0;
2762 int last_native_inst
= 0;
2763 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
2764 int if_stack_depth
= 0, loop_stack_depth
= 0;
2765 int if_depth_in_loop
[16];
2767 if_depth_in_loop
[loop_stack_depth
] = 0;
2769 memset(&if_stack
, 0, sizeof(if_stack
));
2770 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2771 fs_inst
*inst
= (fs_inst
*)iter
.get();
2772 struct brw_reg src
[3], dst
;
2774 for (unsigned int i
= 0; i
< 3; i
++) {
2775 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
2777 dst
= brw_reg_from_fs_reg(&inst
->dst
);
2779 brw_set_conditionalmod(p
, inst
->conditional_mod
);
2780 brw_set_predicate_control(p
, inst
->predicated
);
2782 switch (inst
->opcode
) {
2783 case BRW_OPCODE_MOV
:
2784 brw_MOV(p
, dst
, src
[0]);
2786 case BRW_OPCODE_ADD
:
2787 brw_ADD(p
, dst
, src
[0], src
[1]);
2789 case BRW_OPCODE_MUL
:
2790 brw_MUL(p
, dst
, src
[0], src
[1]);
2793 case BRW_OPCODE_FRC
:
2794 brw_FRC(p
, dst
, src
[0]);
2796 case BRW_OPCODE_RNDD
:
2797 brw_RNDD(p
, dst
, src
[0]);
2799 case BRW_OPCODE_RNDZ
:
2800 brw_RNDZ(p
, dst
, src
[0]);
2803 case BRW_OPCODE_AND
:
2804 brw_AND(p
, dst
, src
[0], src
[1]);
2807 brw_OR(p
, dst
, src
[0], src
[1]);
2809 case BRW_OPCODE_XOR
:
2810 brw_XOR(p
, dst
, src
[0], src
[1]);
2813 case BRW_OPCODE_CMP
:
2814 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
2816 case BRW_OPCODE_SEL
:
2817 brw_SEL(p
, dst
, src
[0], src
[1]);
2821 assert(if_stack_depth
< 16);
2822 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
2823 if_depth_in_loop
[loop_stack_depth
]++;
2826 case BRW_OPCODE_ELSE
:
2827 if_stack
[if_stack_depth
- 1] =
2828 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
2830 case BRW_OPCODE_ENDIF
:
2832 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
2833 if_depth_in_loop
[loop_stack_depth
]--;
2837 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
2838 if_depth_in_loop
[loop_stack_depth
] = 0;
2841 case BRW_OPCODE_BREAK
:
2842 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
2843 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2845 case BRW_OPCODE_CONTINUE
:
2846 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
2847 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2850 case BRW_OPCODE_WHILE
: {
2851 struct brw_instruction
*inst0
, *inst1
;
2854 if (intel
->gen
>= 5)
2857 assert(loop_stack_depth
> 0);
2859 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
2860 /* patch all the BREAK/CONT instructions from last BGNLOOP */
2861 while (inst0
> loop_stack
[loop_stack_depth
]) {
2863 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
2864 inst0
->bits3
.if_else
.jump_count
== 0) {
2865 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
2867 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
2868 inst0
->bits3
.if_else
.jump_count
== 0) {
2869 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
2877 case FS_OPCODE_SQRT
:
2878 case FS_OPCODE_EXP2
:
2879 case FS_OPCODE_LOG2
:
2883 generate_math(inst
, dst
, src
);
2885 case FS_OPCODE_LINTERP
:
2886 generate_linterp(inst
, dst
, src
);
2891 generate_tex(inst
, dst
, src
[0]);
2893 case FS_OPCODE_DISCARD
:
2894 generate_discard(inst
, dst
/* src0 == dst */);
2897 generate_ddx(inst
, dst
, src
[0]);
2900 generate_ddy(inst
, dst
, src
[0]);
2902 case FS_OPCODE_FB_WRITE
:
2903 generate_fb_write(inst
);
2906 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
2907 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
2908 brw_opcodes
[inst
->opcode
].name
);
2910 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
2915 if (annotation_len
< p
->nr_insn
) {
2916 annotation_len
*= 2;
2917 if (annotation_len
< 16)
2918 annotation_len
= 16;
2920 this->annotation_string
= talloc_realloc(this->mem_ctx
,
2924 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
2930 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
2931 this->annotation_string
[i
] = inst
->annotation
;
2932 this->annotation_ir
[i
] = inst
->ir
;
2934 last_native_inst
= p
->nr_insn
;
2939 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
2941 struct brw_compile
*p
= &c
->func
;
2942 struct intel_context
*intel
= &brw
->intel
;
2943 GLcontext
*ctx
= &intel
->ctx
;
2944 struct brw_shader
*shader
= NULL
;
2945 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
2953 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
2954 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
2955 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
2962 /* We always use 8-wide mode, at least for now. For one, flow
2963 * control only works in 8-wide. Also, when we're fragment shader
2964 * bound, we're almost always under register pressure as well, so
2965 * 8-wide would save us from the performance cliff of spilling
2968 c
->dispatch_width
= 8;
2970 if (INTEL_DEBUG
& DEBUG_WM
) {
2971 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
2972 _mesa_print_ir(shader
->ir
, NULL
);
2976 /* Now the main event: Visit the shader IR and generate our FS IR for it.
2978 fs_visitor
v(c
, shader
);
2983 v
.calculate_urb_setup();
2985 v
.emit_interpolation_setup_gen4();
2987 v
.emit_interpolation_setup_gen6();
2989 /* Generate FS IR for main(). (the visitor only descends into
2990 * functions called "main").
2992 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
2993 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
2999 v
.assign_curb_setup();
3000 v
.assign_urb_setup();
3006 v
.calculate_live_intervals();
3007 progress
= v
.propagate_constants() || progress
;
3008 progress
= v
.dead_code_eliminate() || progress
;
3012 v
.assign_regs_trivial();
3020 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3025 if (INTEL_DEBUG
& DEBUG_WM
) {
3026 const char *last_annotation_string
= NULL
;
3027 ir_instruction
*last_annotation_ir
= NULL
;
3029 printf("Native code for fragment shader %d:\n", prog
->Name
);
3030 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3031 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
3032 last_annotation_ir
= v
.annotation_ir
[i
];
3033 if (last_annotation_ir
) {
3035 last_annotation_ir
->print();
3039 if (last_annotation_string
!= v
.annotation_string
[i
]) {
3040 last_annotation_string
= v
.annotation_string
[i
];
3041 if (last_annotation_string
)
3042 printf(" %s\n", last_annotation_string
);
3044 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3049 c
->prog_data
.total_grf
= v
.grf_used
;
3050 c
->prog_data
.total_scratch
= 0;