2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "main/hash_table.h"
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/fbobject.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/register_allocate.h"
42 #include "program/sampler.h"
43 #include "program/hash_table.h"
44 #include "brw_context.h"
49 #include "brw_dead_control_flow.h"
50 #include "main/uniforms.h"
51 #include "brw_fs_live_variables.h"
52 #include "glsl/glsl_types.h"
57 memset(this, 0, sizeof(*this));
58 this->opcode
= BRW_OPCODE_NOP
;
59 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
61 this->dst
= reg_undef
;
62 this->src
[0] = reg_undef
;
63 this->src
[1] = reg_undef
;
64 this->src
[2] = reg_undef
;
66 /* This will be the case for almost all instructions. */
67 this->regs_written
= 1;
75 fs_inst::fs_inst(enum opcode opcode
)
78 this->opcode
= opcode
;
81 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
)
84 this->opcode
= opcode
;
88 assert(dst
.reg_offset
>= 0);
91 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
)
94 this->opcode
= opcode
;
99 assert(dst
.reg_offset
>= 0);
100 if (src
[0].file
== GRF
)
101 assert(src
[0].reg_offset
>= 0);
104 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
107 this->opcode
= opcode
;
113 assert(dst
.reg_offset
>= 0);
114 if (src
[0].file
== GRF
)
115 assert(src
[0].reg_offset
>= 0);
116 if (src
[1].file
== GRF
)
117 assert(src
[1].reg_offset
>= 0);
120 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
,
121 fs_reg src0
, fs_reg src1
, fs_reg src2
)
124 this->opcode
= opcode
;
131 assert(dst
.reg_offset
>= 0);
132 if (src
[0].file
== GRF
)
133 assert(src
[0].reg_offset
>= 0);
134 if (src
[1].file
== GRF
)
135 assert(src
[1].reg_offset
>= 0);
136 if (src
[2].file
== GRF
)
137 assert(src
[2].reg_offset
>= 0);
142 fs_visitor::op(fs_reg dst, fs_reg src0) \
144 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0); \
149 fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1) \
151 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
156 fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2) \
158 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2);\
189 /** Gen4 predicated IF. */
191 fs_visitor::IF(uint32_t predicate
)
193 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
);
194 inst
->predicate
= predicate
;
198 /** Gen6 IF with embedded comparison. */
200 fs_visitor::IF(fs_reg src0
, fs_reg src1
, uint32_t condition
)
202 assert(brw
->gen
== 6);
203 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
,
204 reg_null_d
, src0
, src1
);
205 inst
->conditional_mod
= condition
;
210 * CMP: Sets the low bit of the destination channels with the result
211 * of the comparison, while the upper bits are undefined, and updates
212 * the flag register with the packed 16 bits of the result.
215 fs_visitor::CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
, uint32_t condition
)
219 /* Take the instruction:
221 * CMP null<d> src0<f> src1<f>
223 * Original gen4 does type conversion to the destination type before
224 * comparison, producing garbage results for floating point comparisons.
225 * gen5 does the comparison on the execution type (resolved source types),
226 * so dst type doesn't matter. gen6 does comparison and then uses the
227 * result as if it was the dst type with no conversion, which happens to
228 * mostly work out for float-interpreted-as-int since our comparisons are
232 dst
.type
= src0
.type
;
233 if (dst
.file
== HW_REG
)
234 dst
.fixed_hw_reg
.type
= dst
.type
;
237 resolve_ud_negate(&src0
);
238 resolve_ud_negate(&src1
);
240 inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_CMP
, dst
, src0
, src1
);
241 inst
->conditional_mod
= condition
;
247 fs_visitor::VARYING_PULL_CONSTANT_LOAD(fs_reg dst
, fs_reg surf_index
,
248 fs_reg varying_offset
,
249 uint32_t const_offset
)
251 exec_list instructions
;
254 /* We have our constant surface use a pitch of 4 bytes, so our index can
255 * be any component of a vector, and then we load 4 contiguous
256 * components starting from that.
258 * We break down the const_offset to a portion added to the variable
259 * offset and a portion done using reg_offset, which means that if you
260 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
261 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
262 * CSE can later notice that those loads are all the same and eliminate
263 * the redundant ones.
265 fs_reg vec4_offset
= fs_reg(this, glsl_type::int_type
);
266 instructions
.push_tail(ADD(vec4_offset
,
267 varying_offset
, const_offset
& ~3));
270 if (brw
->gen
== 4 && dispatch_width
== 8) {
271 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
272 * u, v, r) as parameters, or we can just use the SIMD16 message
273 * consisting of (header, u). We choose the second, at the cost of a
274 * longer return length.
281 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
283 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
284 fs_reg vec4_result
= fs_reg(GRF
, virtual_grf_alloc(4 * scale
), dst
.type
);
285 inst
= new(mem_ctx
) fs_inst(op
, vec4_result
, surf_index
, vec4_offset
);
286 inst
->regs_written
= 4 * scale
;
287 instructions
.push_tail(inst
);
291 inst
->header_present
= true;
295 inst
->mlen
= 1 + dispatch_width
/ 8;
298 vec4_result
.reg_offset
+= (const_offset
& 3) * scale
;
299 instructions
.push_tail(MOV(dst
, vec4_result
));
305 * A helper for MOV generation for fixing up broken hardware SEND dependency
309 fs_visitor::DEP_RESOLVE_MOV(int grf
)
311 fs_inst
*inst
= MOV(brw_null_reg(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
314 inst
->annotation
= "send dependency resolve";
316 /* The caller always wants uncompressed to emit the minimal extra
317 * dependencies, and to avoid having to deal with aligning its regs to 2.
319 inst
->force_uncompressed
= true;
325 fs_inst::equals(fs_inst
*inst
)
327 return (opcode
== inst
->opcode
&&
328 dst
.equals(inst
->dst
) &&
329 src
[0].equals(inst
->src
[0]) &&
330 src
[1].equals(inst
->src
[1]) &&
331 src
[2].equals(inst
->src
[2]) &&
332 saturate
== inst
->saturate
&&
333 predicate
== inst
->predicate
&&
334 conditional_mod
== inst
->conditional_mod
&&
335 mlen
== inst
->mlen
&&
336 base_mrf
== inst
->base_mrf
&&
337 sampler
== inst
->sampler
&&
338 target
== inst
->target
&&
340 header_present
== inst
->header_present
&&
341 shadow_compare
== inst
->shadow_compare
&&
342 offset
== inst
->offset
);
346 fs_inst::overwrites_reg(const fs_reg
®
)
348 return (reg
.file
== dst
.file
&&
349 reg
.reg
== dst
.reg
&&
350 reg
.reg_offset
>= dst
.reg_offset
&&
351 reg
.reg_offset
< dst
.reg_offset
+ regs_written
);
355 fs_inst::is_send_from_grf()
357 return (opcode
== FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
||
358 opcode
== SHADER_OPCODE_SHADER_TIME_ADD
||
359 (opcode
== FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
&&
360 src
[1].file
== GRF
) ||
361 (is_tex() && src
[0].file
== GRF
));
365 fs_visitor::can_do_source_mods(fs_inst
*inst
)
367 if (brw
->gen
== 6 && inst
->is_math())
370 if (inst
->is_send_from_grf())
373 if (!inst
->can_do_source_mods())
382 memset(this, 0, sizeof(*this));
386 /** Generic unset register constructor. */
390 this->file
= BAD_FILE
;
393 /** Immediate value constructor. */
394 fs_reg::fs_reg(float f
)
398 this->type
= BRW_REGISTER_TYPE_F
;
402 /** Immediate value constructor. */
403 fs_reg::fs_reg(int32_t i
)
407 this->type
= BRW_REGISTER_TYPE_D
;
411 /** Immediate value constructor. */
412 fs_reg::fs_reg(uint32_t u
)
416 this->type
= BRW_REGISTER_TYPE_UD
;
420 /** Fixed brw_reg. */
421 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
425 this->fixed_hw_reg
= fixed_hw_reg
;
426 this->type
= fixed_hw_reg
.type
;
430 fs_reg::equals(const fs_reg
&r
) const
432 return (file
== r
.file
&&
434 reg_offset
== r
.reg_offset
&&
436 negate
== r
.negate
&&
438 !reladdr
&& !r
.reladdr
&&
439 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
440 sizeof(fixed_hw_reg
)) == 0 &&
446 fs_reg::retype(uint32_t type
)
448 fs_reg result
= *this;
454 fs_reg::is_zero() const
459 return type
== BRW_REGISTER_TYPE_F
? imm
.f
== 0.0 : imm
.i
== 0;
463 fs_reg::is_one() const
468 return type
== BRW_REGISTER_TYPE_F
? imm
.f
== 1.0 : imm
.i
== 1;
472 fs_reg::is_null() const
474 return file
== HW_REG
&&
475 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
476 fixed_hw_reg
.nr
== BRW_ARF_NULL
;
480 fs_reg::is_valid_3src() const
482 return file
== GRF
|| file
== UNIFORM
;
486 fs_visitor::type_size(const struct glsl_type
*type
)
488 unsigned int size
, i
;
490 switch (type
->base_type
) {
493 case GLSL_TYPE_FLOAT
:
495 return type
->components();
496 case GLSL_TYPE_ARRAY
:
497 return type_size(type
->fields
.array
) * type
->length
;
498 case GLSL_TYPE_STRUCT
:
500 for (i
= 0; i
< type
->length
; i
++) {
501 size
+= type_size(type
->fields
.structure
[i
].type
);
504 case GLSL_TYPE_SAMPLER
:
505 /* Samplers take up no register space, since they're baked in at
509 case GLSL_TYPE_ATOMIC_UINT
:
511 case GLSL_TYPE_IMAGE
:
513 case GLSL_TYPE_ERROR
:
514 case GLSL_TYPE_INTERFACE
:
515 assert(!"not reached");
523 fs_visitor::get_timestamp()
525 assert(brw
->gen
>= 7);
527 fs_reg ts
= fs_reg(retype(brw_vec1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
530 BRW_REGISTER_TYPE_UD
));
532 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
534 fs_inst
*mov
= emit(MOV(dst
, ts
));
535 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
536 * even if it's not enabled in the dispatch.
538 mov
->force_writemask_all
= true;
539 mov
->force_uncompressed
= true;
541 /* The caller wants the low 32 bits of the timestamp. Since it's running
542 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
543 * which is plenty of time for our purposes. It is identical across the
544 * EUs, but since it's tracking GPU core speed it will increment at a
545 * varying rate as render P-states change.
547 * The caller could also check if render P-states have changed (or anything
548 * else that might disrupt timing) by setting smear to 2 and checking if
549 * that field is != 0.
557 fs_visitor::emit_shader_time_begin()
559 current_annotation
= "shader time start";
560 shader_start_time
= get_timestamp();
564 fs_visitor::emit_shader_time_end()
566 current_annotation
= "shader time end";
568 enum shader_time_shader_type type
, written_type
, reset_type
;
569 if (dispatch_width
== 8) {
571 written_type
= ST_FS8_WRITTEN
;
572 reset_type
= ST_FS8_RESET
;
574 assert(dispatch_width
== 16);
576 written_type
= ST_FS16_WRITTEN
;
577 reset_type
= ST_FS16_RESET
;
580 fs_reg shader_end_time
= get_timestamp();
582 /* Check that there weren't any timestamp reset events (assuming these
583 * were the only two timestamp reads that happened).
585 fs_reg reset
= shader_end_time
;
587 fs_inst
*test
= emit(AND(reg_null_d
, reset
, fs_reg(1u)));
588 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
589 emit(IF(BRW_PREDICATE_NORMAL
));
591 push_force_uncompressed();
592 fs_reg start
= shader_start_time
;
594 fs_reg diff
= fs_reg(this, glsl_type::uint_type
);
595 emit(ADD(diff
, start
, shader_end_time
));
597 /* If there were no instructions between the two timestamp gets, the diff
598 * is 2 cycles. Remove that overhead, so I can forget about that when
599 * trying to determine the time taken for single instructions.
601 emit(ADD(diff
, diff
, fs_reg(-2u)));
603 emit_shader_time_write(type
, diff
);
604 emit_shader_time_write(written_type
, fs_reg(1u));
605 emit(BRW_OPCODE_ELSE
);
606 emit_shader_time_write(reset_type
, fs_reg(1u));
607 emit(BRW_OPCODE_ENDIF
);
609 pop_force_uncompressed();
613 fs_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
616 int shader_time_index
=
617 brw_get_shader_time_index(brw
, shader_prog
, &fp
->Base
, type
);
618 fs_reg offset
= fs_reg(shader_time_index
* SHADER_TIME_STRIDE
);
621 if (dispatch_width
== 8)
622 payload
= fs_reg(this, glsl_type::uvec2_type
);
624 payload
= fs_reg(this, glsl_type::uint_type
);
626 emit(fs_inst(SHADER_OPCODE_SHADER_TIME_ADD
,
627 fs_reg(), payload
, offset
, value
));
631 fs_visitor::fail(const char *format
, ...)
641 va_start(va
, format
);
642 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
644 msg
= ralloc_asprintf(mem_ctx
, "FS compile failed: %s\n", msg
);
646 this->fail_msg
= msg
;
648 if (INTEL_DEBUG
& DEBUG_WM
) {
649 fprintf(stderr
, "%s", msg
);
654 fs_visitor::emit(enum opcode opcode
)
656 return emit(fs_inst(opcode
));
660 fs_visitor::emit(enum opcode opcode
, fs_reg dst
)
662 return emit(fs_inst(opcode
, dst
));
666 fs_visitor::emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
)
668 return emit(fs_inst(opcode
, dst
, src0
));
672 fs_visitor::emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
674 return emit(fs_inst(opcode
, dst
, src0
, src1
));
678 fs_visitor::emit(enum opcode opcode
, fs_reg dst
,
679 fs_reg src0
, fs_reg src1
, fs_reg src2
)
681 return emit(fs_inst(opcode
, dst
, src0
, src1
, src2
));
685 fs_visitor::push_force_uncompressed()
687 force_uncompressed_stack
++;
691 fs_visitor::pop_force_uncompressed()
693 force_uncompressed_stack
--;
694 assert(force_uncompressed_stack
>= 0);
698 * Returns true if the instruction has a flag that means it won't
699 * update an entire destination register.
701 * For example, dead code elimination and live variable analysis want to know
702 * when a write to a variable screens off any preceding values that were in
706 fs_inst::is_partial_write()
708 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
709 this->force_uncompressed
||
710 this->force_sechalf
);
714 fs_inst::regs_read(fs_visitor
*v
, int arg
)
716 if (is_tex() && arg
== 0 && src
[0].file
== GRF
) {
717 if (v
->dispatch_width
== 16)
718 return (mlen
+ 1) / 2;
726 fs_inst::reads_flag()
732 fs_inst::writes_flag()
734 return (conditional_mod
&& opcode
!= BRW_OPCODE_SEL
) ||
735 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
739 * Returns how many MRFs an FS opcode will write over.
741 * Note that this is not the 0 or 1 implied writes in an actual gen
742 * instruction -- the FS opcodes often generate MOVs in addition.
745 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
750 if (inst
->base_mrf
== -1)
753 switch (inst
->opcode
) {
754 case SHADER_OPCODE_RCP
:
755 case SHADER_OPCODE_RSQ
:
756 case SHADER_OPCODE_SQRT
:
757 case SHADER_OPCODE_EXP2
:
758 case SHADER_OPCODE_LOG2
:
759 case SHADER_OPCODE_SIN
:
760 case SHADER_OPCODE_COS
:
761 return 1 * dispatch_width
/ 8;
762 case SHADER_OPCODE_POW
:
763 case SHADER_OPCODE_INT_QUOTIENT
:
764 case SHADER_OPCODE_INT_REMAINDER
:
765 return 2 * dispatch_width
/ 8;
766 case SHADER_OPCODE_TEX
:
768 case SHADER_OPCODE_TXD
:
769 case SHADER_OPCODE_TXF
:
770 case SHADER_OPCODE_TXF_CMS
:
771 case SHADER_OPCODE_TXF_MCS
:
772 case SHADER_OPCODE_TG4
:
773 case SHADER_OPCODE_TG4_OFFSET
:
774 case SHADER_OPCODE_TXL
:
775 case SHADER_OPCODE_TXS
:
776 case SHADER_OPCODE_LOD
:
778 case FS_OPCODE_FB_WRITE
:
780 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
781 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
783 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
785 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
787 case SHADER_OPCODE_UNTYPED_ATOMIC
:
788 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
791 assert(!"not reached");
797 fs_visitor::virtual_grf_alloc(int size
)
799 if (virtual_grf_array_size
<= virtual_grf_count
) {
800 if (virtual_grf_array_size
== 0)
801 virtual_grf_array_size
= 16;
803 virtual_grf_array_size
*= 2;
804 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
805 virtual_grf_array_size
);
807 virtual_grf_sizes
[virtual_grf_count
] = size
;
808 return virtual_grf_count
++;
811 /** Fixed HW reg constructor. */
812 fs_reg::fs_reg(enum register_file file
, int reg
)
817 this->type
= BRW_REGISTER_TYPE_F
;
820 /** Fixed HW reg constructor. */
821 fs_reg::fs_reg(enum register_file file
, int reg
, uint32_t type
)
829 /** Automatic reg constructor. */
830 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
835 this->reg
= v
->virtual_grf_alloc(v
->type_size(type
));
836 this->reg_offset
= 0;
837 this->type
= brw_type_for_base_type(type
);
841 fs_visitor::variable_storage(ir_variable
*var
)
843 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
847 import_uniforms_callback(const void *key
,
851 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
852 const fs_reg
*reg
= (const fs_reg
*)data
;
854 if (reg
->file
!= UNIFORM
)
857 hash_table_insert(dst_ht
, data
, key
);
860 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
861 * This brings in those uniform definitions
864 fs_visitor::import_uniforms(fs_visitor
*v
)
866 hash_table_call_foreach(v
->variable_ht
,
867 import_uniforms_callback
,
869 this->params_remap
= v
->params_remap
;
870 this->nr_params_remap
= v
->nr_params_remap
;
873 /* Our support for uniforms is piggy-backed on the struct
874 * gl_fragment_program, because that's where the values actually
875 * get stored, rather than in some global gl_shader_program uniform
879 fs_visitor::setup_uniform_values(ir_variable
*ir
)
881 int namelen
= strlen(ir
->name
);
883 /* The data for our (non-builtin) uniforms is stored in a series of
884 * gl_uniform_driver_storage structs for each subcomponent that
885 * glGetUniformLocation() could name. We know it's been set up in the same
886 * order we'd walk the type, so walk the list of storage and find anything
887 * with our name, or the prefix of a component that starts with our name.
889 unsigned params_before
= c
->prog_data
.nr_params
;
890 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
891 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
893 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
894 (storage
->name
[namelen
] != 0 &&
895 storage
->name
[namelen
] != '.' &&
896 storage
->name
[namelen
] != '[')) {
900 unsigned slots
= storage
->type
->component_slots();
901 if (storage
->array_elements
)
902 slots
*= storage
->array_elements
;
904 for (unsigned i
= 0; i
< slots
; i
++) {
905 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
906 &storage
->storage
[i
].f
;
910 /* Make sure we actually initialized the right amount of stuff here. */
911 assert(params_before
+ ir
->type
->component_slots() ==
912 c
->prog_data
.nr_params
);
917 /* Our support for builtin uniforms is even scarier than non-builtin.
918 * It sits on top of the PROG_STATE_VAR parameters that are
919 * automatically updated from GL context state.
922 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
924 const ir_state_slot
*const slots
= ir
->state_slots
;
925 assert(ir
->state_slots
!= NULL
);
927 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
928 /* This state reference has already been setup by ir_to_mesa, but we'll
929 * get the same index back here.
931 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
932 (gl_state_index
*)slots
[i
].tokens
);
934 /* Add each of the unique swizzles of the element as a parameter.
935 * This'll end up matching the expected layout of the
936 * array/matrix/structure we're trying to fill in.
939 for (unsigned int j
= 0; j
< 4; j
++) {
940 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
941 if (swiz
== last_swiz
)
945 c
->prog_data
.param
[c
->prog_data
.nr_params
++] =
946 &fp
->Base
.Parameters
->ParameterValues
[index
][swiz
].f
;
952 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
954 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
956 bool flip
= !ir
->data
.origin_upper_left
^ c
->key
.render_to_fbo
;
959 if (ir
->data
.pixel_center_integer
) {
960 emit(MOV(wpos
, this->pixel_x
));
962 emit(ADD(wpos
, this->pixel_x
, fs_reg(0.5f
)));
967 if (!flip
&& ir
->data
.pixel_center_integer
) {
968 emit(MOV(wpos
, this->pixel_y
));
970 fs_reg pixel_y
= this->pixel_y
;
971 float offset
= (ir
->data
.pixel_center_integer
? 0.0 : 0.5);
974 pixel_y
.negate
= true;
975 offset
+= c
->key
.drawable_height
- 1.0;
978 emit(ADD(wpos
, pixel_y
, fs_reg(offset
)));
984 emit(MOV(wpos
, fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
986 emit(FS_OPCODE_LINTERP
, wpos
,
987 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
988 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
989 interp_reg(VARYING_SLOT_POS
, 2));
993 /* gl_FragCoord.w: Already set up in emit_interpolation */
994 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
1000 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1001 glsl_interp_qualifier interpolation_mode
,
1002 bool is_centroid
, bool is_sample
)
1004 brw_wm_barycentric_interp_mode barycoord_mode
;
1005 if (brw
->gen
>= 6) {
1007 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1008 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1010 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1011 } else if (is_sample
) {
1012 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1013 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1015 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1017 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1018 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1020 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1023 /* On Ironlake and below, there is only one interpolation mode.
1024 * Centroid interpolation doesn't mean anything on this hardware --
1025 * there is no multisampling.
1027 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1029 return emit(FS_OPCODE_LINTERP
, attr
,
1030 this->delta_x
[barycoord_mode
],
1031 this->delta_y
[barycoord_mode
], interp
);
1035 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
1037 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1038 reg
->type
= brw_type_for_base_type(ir
->type
->get_scalar_type());
1041 unsigned int array_elements
;
1042 const glsl_type
*type
;
1044 if (ir
->type
->is_array()) {
1045 array_elements
= ir
->type
->length
;
1046 if (array_elements
== 0) {
1047 fail("dereferenced array '%s' has length 0\n", ir
->name
);
1049 type
= ir
->type
->fields
.array
;
1055 glsl_interp_qualifier interpolation_mode
=
1056 ir
->determine_interpolation_mode(c
->key
.flat_shade
);
1058 int location
= ir
->data
.location
;
1059 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1060 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1061 if (c
->prog_data
.urb_setup
[location
] == -1) {
1062 /* If there's no incoming setup data for this slot, don't
1063 * emit interpolation for it.
1065 attr
.reg_offset
+= type
->vector_elements
;
1070 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1071 /* Constant interpolation (flat shading) case. The SF has
1072 * handed us defined values in only the constant offset
1073 * field of the setup reg.
1075 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1076 struct brw_reg interp
= interp_reg(location
, k
);
1077 interp
= suboffset(interp
, 3);
1078 interp
.type
= reg
->type
;
1079 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1083 /* Smooth/noperspective interpolation case. */
1084 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1085 /* FINISHME: At some point we probably want to push
1086 * this farther by giving similar treatment to the
1087 * other potentially constant components of the
1088 * attribute, as well as making brw_vs_constval.c
1089 * handle varyings other than gl_TexCoord.
1091 struct brw_reg interp
= interp_reg(location
, k
);
1092 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1093 ir
->data
.centroid
&& !c
->key
.persample_shading
,
1094 ir
->data
.sample
|| c
->key
.persample_shading
);
1095 if (brw
->needs_unlit_centroid_workaround
&& ir
->data
.centroid
) {
1096 /* Get the pixel/sample mask into f0 so that we know
1097 * which pixels are lit. Then, for each channel that is
1098 * unlit, replace the centroid data with non-centroid
1101 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1102 fs_inst
*inst
= emit_linterp(attr
, fs_reg(interp
),
1105 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1106 inst
->predicate_inverse
= true;
1108 if (brw
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1109 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
1123 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
1125 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1127 /* The frontfacing comes in as a bit in the thread payload. */
1128 if (brw
->gen
>= 6) {
1129 emit(BRW_OPCODE_ASR
, *reg
,
1130 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1132 emit(BRW_OPCODE_NOT
, *reg
, *reg
);
1133 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1));
1135 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
1136 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
1139 emit(CMP(*reg
, fs_reg(r1_6ud
), fs_reg(1u << 31), BRW_CONDITIONAL_L
));
1140 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u));
1147 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1149 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1151 if (c
->key
.compute_pos_offset
) {
1152 /* Convert int_sample_pos to floating point */
1153 emit(MOV(dst
, int_sample_pos
));
1154 /* Scale to the range [0, 1] */
1155 emit(MUL(dst
, dst
, fs_reg(1 / 16.0f
)));
1158 /* From ARB_sample_shading specification:
1159 * "When rendering to a non-multisample buffer, or if multisample
1160 * rasterization is disabled, gl_SamplePosition will always be
1163 emit(MOV(dst
, fs_reg(0.5f
)));
1168 fs_visitor::emit_samplepos_setup(ir_variable
*ir
)
1170 assert(brw
->gen
>= 6);
1171 assert(ir
->type
== glsl_type::vec2_type
);
1173 this->current_annotation
= "compute sample position";
1174 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1176 fs_reg int_sample_x
= fs_reg(this, glsl_type::int_type
);
1177 fs_reg int_sample_y
= fs_reg(this, glsl_type::int_type
);
1179 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1180 * mode will be enabled.
1182 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1183 * R31.1:0 Position Offset X/Y for Slot[3:0]
1184 * R31.3:2 Position Offset X/Y for Slot[7:4]
1187 * The X, Y sample positions come in as bytes in thread payload. So, read
1188 * the positions using vstride=16, width=8, hstride=2.
1190 struct brw_reg sample_pos_reg
=
1191 stride(retype(brw_vec1_grf(c
->sample_pos_reg
, 0),
1192 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1194 emit(MOV(int_sample_x
, fs_reg(sample_pos_reg
)));
1195 if (dispatch_width
== 16) {
1196 int_sample_x
.sechalf
= true;
1197 fs_inst
*inst
= emit(MOV(int_sample_x
,
1198 fs_reg(suboffset(sample_pos_reg
, 16))));
1199 inst
->force_sechalf
= true;
1200 int_sample_x
.sechalf
= false;
1202 /* Compute gl_SamplePosition.x */
1203 compute_sample_position(pos
, int_sample_x
);
1205 emit(MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1))));
1206 if (dispatch_width
== 16) {
1207 int_sample_y
.sechalf
= true;
1208 fs_inst
*inst
= emit(MOV(int_sample_y
,
1209 fs_reg(suboffset(sample_pos_reg
, 17))));
1210 inst
->force_sechalf
= true;
1211 int_sample_y
.sechalf
= false;
1213 /* Compute gl_SamplePosition.y */
1214 compute_sample_position(pos
, int_sample_y
);
1219 fs_visitor::emit_sampleid_setup(ir_variable
*ir
)
1221 assert(brw
->gen
>= 6);
1223 this->current_annotation
= "compute sample id";
1224 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1226 if (c
->key
.compute_sample_id
) {
1227 fs_reg t1
= fs_reg(this, glsl_type::int_type
);
1228 fs_reg t2
= fs_reg(this, glsl_type::int_type
);
1229 t2
.type
= BRW_REGISTER_TYPE_UW
;
1231 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1232 * 8x multisampling, subspan 0 will represent sample N (where N
1233 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1234 * 7. We can find the value of N by looking at R0.0 bits 7:6
1235 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1236 * (since samples are always delivered in pairs). That is, we
1237 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1238 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1239 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1240 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1241 * populating a temporary variable with the sequence (0, 1, 2, 3),
1242 * and then reading from it using vstride=1, width=4, hstride=0.
1243 * These computations hold good for 4x multisampling as well.
1245 emit(BRW_OPCODE_AND
, t1
,
1246 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1247 fs_reg(brw_imm_d(0xc0)));
1248 emit(BRW_OPCODE_SHR
, t1
, t1
, fs_reg(5));
1249 /* This works for both SIMD8 and SIMD16 */
1250 emit(MOV(t2
, brw_imm_v(0x3210)));
1251 /* This special instruction takes care of setting vstride=1,
1252 * width=4, hstride=0 of t2 during an ADD instruction.
1254 emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1256 /* As per GL_ARB_sample_shading specification:
1257 * "When rendering to a non-multisample buffer, or if multisample
1258 * rasterization is disabled, gl_SampleID will always be zero."
1260 emit(BRW_OPCODE_MOV
, *reg
, fs_reg(0));
1267 fs_visitor::emit_samplemaskin_setup(ir_variable
*ir
)
1269 assert(brw
->gen
>= 7);
1270 this->current_annotation
= "compute gl_SampleMaskIn";
1271 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1272 emit(MOV(*reg
, fs_reg(retype(brw_vec8_grf(c
->sample_mask_reg
, 0), BRW_REGISTER_TYPE_D
))));
1277 fs_visitor::fix_math_operand(fs_reg src
)
1279 /* Can't do hstride == 0 args on gen6 math, so expand it out. We
1280 * might be able to do better by doing execsize = 1 math and then
1281 * expanding that result out, but we would need to be careful with
1284 * The hardware ignores source modifiers (negate and abs) on math
1285 * instructions, so we also move to a temp to set those up.
1287 if (brw
->gen
== 6 && src
.file
!= UNIFORM
&& src
.file
!= IMM
&&
1288 !src
.abs
&& !src
.negate
)
1291 /* Gen7 relaxes most of the above restrictions, but still can't use IMM
1294 if (brw
->gen
>= 7 && src
.file
!= IMM
)
1297 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
1298 expanded
.type
= src
.type
;
1299 emit(BRW_OPCODE_MOV
, expanded
, src
);
1304 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src
)
1307 case SHADER_OPCODE_RCP
:
1308 case SHADER_OPCODE_RSQ
:
1309 case SHADER_OPCODE_SQRT
:
1310 case SHADER_OPCODE_EXP2
:
1311 case SHADER_OPCODE_LOG2
:
1312 case SHADER_OPCODE_SIN
:
1313 case SHADER_OPCODE_COS
:
1316 assert(!"not reached: bad math opcode");
1320 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
1321 * might be able to do better by doing execsize = 1 math and then
1322 * expanding that result out, but we would need to be careful with
1325 * Gen 6 hardware ignores source modifiers (negate and abs) on math
1326 * instructions, so we also move to a temp to set those up.
1329 src
= fix_math_operand(src
);
1331 fs_inst
*inst
= emit(opcode
, dst
, src
);
1335 inst
->mlen
= dispatch_width
/ 8;
1342 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
1348 case SHADER_OPCODE_INT_QUOTIENT
:
1349 case SHADER_OPCODE_INT_REMAINDER
:
1350 if (brw
->gen
>= 7 && dispatch_width
== 16)
1351 fail("SIMD16 INTDIV unsupported\n");
1353 case SHADER_OPCODE_POW
:
1356 assert(!"not reached: unsupported binary math opcode.");
1360 if (brw
->gen
>= 6) {
1361 src0
= fix_math_operand(src0
);
1362 src1
= fix_math_operand(src1
);
1364 inst
= emit(opcode
, dst
, src0
, src1
);
1366 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
1367 * "Message Payload":
1369 * "Operand0[7]. For the INT DIV functions, this operand is the
1372 * "Operand1[7]. For the INT DIV functions, this operand is the
1375 bool is_int_div
= opcode
!= SHADER_OPCODE_POW
;
1376 fs_reg
&op0
= is_int_div
? src1
: src0
;
1377 fs_reg
&op1
= is_int_div
? src0
: src1
;
1379 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1, op1
.type
), op1
);
1380 inst
= emit(opcode
, dst
, op0
, reg_null_f
);
1382 inst
->base_mrf
= base_mrf
;
1383 inst
->mlen
= 2 * dispatch_width
/ 8;
1389 fs_visitor::assign_curb_setup()
1391 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
1392 if (dispatch_width
== 8) {
1393 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
1395 c
->prog_data
.first_curbe_grf_16
= c
->nr_payload_regs
;
1398 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1399 foreach_list(node
, &this->instructions
) {
1400 fs_inst
*inst
= (fs_inst
*)node
;
1402 for (unsigned int i
= 0; i
< 3; i
++) {
1403 if (inst
->src
[i
].file
== UNIFORM
) {
1404 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1405 struct brw_reg brw_reg
= brw_vec1_grf(c
->nr_payload_regs
+
1409 inst
->src
[i
].file
= HW_REG
;
1410 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
1417 fs_visitor::calculate_urb_setup()
1419 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1420 c
->prog_data
.urb_setup
[i
] = -1;
1424 /* Figure out where each of the incoming setup attributes lands. */
1425 if (brw
->gen
>= 6) {
1426 if (_mesa_bitcount_64(fp
->Base
.InputsRead
&
1427 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1428 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1429 * first 16 varying inputs, so we can put them wherever we want.
1430 * Just put them in order.
1432 * This is useful because it means that (a) inputs not used by the
1433 * fragment shader won't take up valuable register space, and (b) we
1434 * won't have to recompile the fragment shader if it gets paired with
1435 * a different vertex (or geometry) shader.
1437 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1438 if (fp
->Base
.InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1439 BITFIELD64_BIT(i
)) {
1440 c
->prog_data
.urb_setup
[i
] = urb_next
++;
1444 /* We have enough input varyings that the SF/SBE pipeline stage can't
1445 * arbitrarily rearrange them to suit our whim; we have to put them
1446 * in an order that matches the output of the previous pipeline stage
1447 * (geometry or vertex shader).
1449 struct brw_vue_map prev_stage_vue_map
;
1450 brw_compute_vue_map(brw
, &prev_stage_vue_map
,
1451 c
->key
.input_slots_valid
);
1452 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1453 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1454 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1456 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1457 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1460 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1461 (fp
->Base
.InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1462 BITFIELD64_BIT(varying
))) {
1463 c
->prog_data
.urb_setup
[varying
] = slot
- first_slot
;
1466 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1469 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1470 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1471 /* Point size is packed into the header, not as a general attribute */
1472 if (i
== VARYING_SLOT_PSIZ
)
1475 if (c
->key
.input_slots_valid
& BITFIELD64_BIT(i
)) {
1476 /* The back color slot is skipped when the front color is
1477 * also written to. In addition, some slots can be
1478 * written in the vertex shader and not read in the
1479 * fragment shader. So the register number must always be
1480 * incremented, mapped or not.
1482 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1483 c
->prog_data
.urb_setup
[i
] = urb_next
;
1489 * It's a FS only attribute, and we did interpolation for this attribute
1490 * in SF thread. So, count it here, too.
1492 * See compile_sf_prog() for more info.
1494 if (fp
->Base
.InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1495 c
->prog_data
.urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1498 c
->prog_data
.num_varying_inputs
= urb_next
;
1502 fs_visitor::assign_urb_setup()
1504 int urb_start
= c
->nr_payload_regs
+ c
->prog_data
.curb_read_length
;
1506 /* Offset all the urb_setup[] index by the actual position of the
1507 * setup regs, now that the location of the constants has been chosen.
1509 foreach_list(node
, &this->instructions
) {
1510 fs_inst
*inst
= (fs_inst
*)node
;
1512 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1513 assert(inst
->src
[2].file
== HW_REG
);
1514 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
1517 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1518 assert(inst
->src
[0].file
== HW_REG
);
1519 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1523 /* Each attribute is 4 setup channels, each of which is half a reg. */
1524 this->first_non_payload_grf
=
1525 urb_start
+ c
->prog_data
.num_varying_inputs
* 2;
1529 * Split large virtual GRFs into separate components if we can.
1531 * This is mostly duplicated with what brw_fs_vector_splitting does,
1532 * but that's really conservative because it's afraid of doing
1533 * splitting that doesn't result in real progress after the rest of
1534 * the optimization phases, which would cause infinite looping in
1535 * optimization. We can do it once here, safely. This also has the
1536 * opportunity to split interpolated values, or maybe even uniforms,
1537 * which we don't have at the IR level.
1539 * We want to split, because virtual GRFs are what we register
1540 * allocate and spill (due to contiguousness requirements for some
1541 * instructions), and they're what we naturally generate in the
1542 * codegen process, but most virtual GRFs don't actually need to be
1543 * contiguous sets of GRFs. If we split, we'll end up with reduced
1544 * live intervals and better dead code elimination and coalescing.
1547 fs_visitor::split_virtual_grfs()
1549 int num_vars
= this->virtual_grf_count
;
1550 bool split_grf
[num_vars
];
1551 int new_virtual_grf
[num_vars
];
1553 /* Try to split anything > 0 sized. */
1554 for (int i
= 0; i
< num_vars
; i
++) {
1555 if (this->virtual_grf_sizes
[i
] != 1)
1556 split_grf
[i
] = true;
1558 split_grf
[i
] = false;
1562 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
) {
1563 /* PLN opcodes rely on the delta_xy being contiguous. We only have to
1564 * check this for BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because prior to
1565 * Gen6, that was the only supported interpolation mode, and since Gen6,
1566 * delta_x and delta_y are in fixed hardware registers.
1568 split_grf
[this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
] =
1572 foreach_list(node
, &this->instructions
) {
1573 fs_inst
*inst
= (fs_inst
*)node
;
1575 /* If there's a SEND message that requires contiguous destination
1576 * registers, no splitting is allowed.
1578 if (inst
->regs_written
> 1) {
1579 split_grf
[inst
->dst
.reg
] = false;
1582 /* If we're sending from a GRF, don't split it, on the assumption that
1583 * the send is reading the whole thing.
1585 if (inst
->is_send_from_grf()) {
1586 for (int i
= 0; i
< 3; i
++) {
1587 if (inst
->src
[i
].file
== GRF
) {
1588 split_grf
[inst
->src
[i
].reg
] = false;
1594 /* Allocate new space for split regs. Note that the virtual
1595 * numbers will be contiguous.
1597 for (int i
= 0; i
< num_vars
; i
++) {
1599 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1600 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1601 int reg
= virtual_grf_alloc(1);
1602 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1605 this->virtual_grf_sizes
[i
] = 1;
1609 foreach_list(node
, &this->instructions
) {
1610 fs_inst
*inst
= (fs_inst
*)node
;
1612 if (inst
->dst
.file
== GRF
&&
1613 split_grf
[inst
->dst
.reg
] &&
1614 inst
->dst
.reg_offset
!= 0) {
1615 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1616 inst
->dst
.reg_offset
- 1);
1617 inst
->dst
.reg_offset
= 0;
1619 for (int i
= 0; i
< 3; i
++) {
1620 if (inst
->src
[i
].file
== GRF
&&
1621 split_grf
[inst
->src
[i
].reg
] &&
1622 inst
->src
[i
].reg_offset
!= 0) {
1623 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1624 inst
->src
[i
].reg_offset
- 1);
1625 inst
->src
[i
].reg_offset
= 0;
1629 invalidate_live_intervals();
1633 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1635 * During code generation, we create tons of temporary variables, many of
1636 * which get immediately killed and are never used again. Yet, in later
1637 * optimization and analysis passes, such as compute_live_intervals, we need
1638 * to loop over all the virtual GRFs. Compacting them can save a lot of
1642 fs_visitor::compact_virtual_grfs()
1644 /* Mark which virtual GRFs are used, and count how many. */
1645 int remap_table
[this->virtual_grf_count
];
1646 memset(remap_table
, -1, sizeof(remap_table
));
1648 foreach_list(node
, &this->instructions
) {
1649 const fs_inst
*inst
= (const fs_inst
*) node
;
1651 if (inst
->dst
.file
== GRF
)
1652 remap_table
[inst
->dst
.reg
] = 0;
1654 for (int i
= 0; i
< 3; i
++) {
1655 if (inst
->src
[i
].file
== GRF
)
1656 remap_table
[inst
->src
[i
].reg
] = 0;
1660 /* In addition to registers used in instructions, fs_visitor keeps
1661 * direct references to certain special values which must be patched:
1663 fs_reg
*special
[] = {
1664 &frag_depth
, &pixel_x
, &pixel_y
, &pixel_w
, &wpos_w
, &dual_src_output
,
1665 &outputs
[0], &outputs
[1], &outputs
[2], &outputs
[3],
1666 &outputs
[4], &outputs
[5], &outputs
[6], &outputs
[7],
1667 &delta_x
[0], &delta_x
[1], &delta_x
[2],
1668 &delta_x
[3], &delta_x
[4], &delta_x
[5],
1669 &delta_y
[0], &delta_y
[1], &delta_y
[2],
1670 &delta_y
[3], &delta_y
[4], &delta_y
[5],
1672 STATIC_ASSERT(BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
== 6);
1673 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
== 8);
1675 /* Treat all special values as used, to be conservative */
1676 for (unsigned i
= 0; i
< ARRAY_SIZE(special
); i
++) {
1677 if (special
[i
]->file
== GRF
)
1678 remap_table
[special
[i
]->reg
] = 0;
1681 /* Compact the GRF arrays. */
1683 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
1684 if (remap_table
[i
] != -1) {
1685 remap_table
[i
] = new_index
;
1686 virtual_grf_sizes
[new_index
] = virtual_grf_sizes
[i
];
1687 invalidate_live_intervals();
1692 this->virtual_grf_count
= new_index
;
1694 /* Patch all the instructions to use the newly renumbered registers */
1695 foreach_list(node
, &this->instructions
) {
1696 fs_inst
*inst
= (fs_inst
*) node
;
1698 if (inst
->dst
.file
== GRF
)
1699 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1701 for (int i
= 0; i
< 3; i
++) {
1702 if (inst
->src
[i
].file
== GRF
)
1703 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1707 /* Patch all the references to special values */
1708 for (unsigned i
= 0; i
< ARRAY_SIZE(special
); i
++) {
1709 if (special
[i
]->file
== GRF
&& remap_table
[special
[i
]->reg
] != -1)
1710 special
[i
]->reg
= remap_table
[special
[i
]->reg
];
1715 fs_visitor::remove_dead_constants()
1717 if (dispatch_width
== 8) {
1718 this->params_remap
= ralloc_array(mem_ctx
, int, c
->prog_data
.nr_params
);
1719 this->nr_params_remap
= c
->prog_data
.nr_params
;
1721 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++)
1722 this->params_remap
[i
] = -1;
1724 /* Find which params are still in use. */
1725 foreach_list(node
, &this->instructions
) {
1726 fs_inst
*inst
= (fs_inst
*)node
;
1728 for (int i
= 0; i
< 3; i
++) {
1729 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1731 if (inst
->src
[i
].file
!= UNIFORM
)
1734 /* Section 5.11 of the OpenGL 4.3 spec says:
1736 * "Out-of-bounds reads return undefined values, which include
1737 * values from other variables of the active program or zero."
1739 if (constant_nr
< 0 || constant_nr
>= (int)c
->prog_data
.nr_params
) {
1743 /* For now, set this to non-negative. We'll give it the
1744 * actual new number in a moment, in order to keep the
1745 * register numbers nicely ordered.
1747 this->params_remap
[constant_nr
] = 0;
1751 /* Figure out what the new numbers for the params will be. At some
1752 * point when we're doing uniform array access, we're going to want
1753 * to keep the distinction between .reg and .reg_offset, but for
1754 * now we don't care.
1756 unsigned int new_nr_params
= 0;
1757 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1758 if (this->params_remap
[i
] != -1) {
1759 this->params_remap
[i
] = new_nr_params
++;
1763 /* Update the list of params to be uploaded to match our new numbering. */
1764 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1765 int remapped
= this->params_remap
[i
];
1770 c
->prog_data
.param
[remapped
] = c
->prog_data
.param
[i
];
1773 c
->prog_data
.nr_params
= new_nr_params
;
1775 /* This should have been generated in the SIMD8 pass already. */
1776 assert(this->params_remap
);
1779 /* Now do the renumbering of the shader to remove unused params. */
1780 foreach_list(node
, &this->instructions
) {
1781 fs_inst
*inst
= (fs_inst
*)node
;
1783 for (int i
= 0; i
< 3; i
++) {
1784 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1786 if (inst
->src
[i
].file
!= UNIFORM
)
1789 /* as above alias to 0 */
1790 if (constant_nr
< 0 || constant_nr
>= (int)this->nr_params_remap
) {
1793 assert(this->params_remap
[constant_nr
] != -1);
1794 inst
->src
[i
].reg
= this->params_remap
[constant_nr
];
1795 inst
->src
[i
].reg_offset
= 0;
1803 * Implements array access of uniforms by inserting a
1804 * PULL_CONSTANT_LOAD instruction.
1806 * Unlike temporary GRF array access (where we don't support it due to
1807 * the difficulty of doing relative addressing on instruction
1808 * destinations), we could potentially do array access of uniforms
1809 * that were loaded in GRF space as push constants. In real-world
1810 * usage we've seen, though, the arrays being used are always larger
1811 * than we could load as push constants, so just always move all
1812 * uniform array access out to a pull constant buffer.
1815 fs_visitor::move_uniform_array_access_to_pull_constants()
1817 int pull_constant_loc
[c
->prog_data
.nr_params
];
1819 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1820 pull_constant_loc
[i
] = -1;
1823 /* Walk through and find array access of uniforms. Put a copy of that
1824 * uniform in the pull constant buffer.
1826 * Note that we don't move constant-indexed accesses to arrays. No
1827 * testing has been done of the performance impact of this choice.
1829 foreach_list_safe(node
, &this->instructions
) {
1830 fs_inst
*inst
= (fs_inst
*)node
;
1832 for (int i
= 0 ; i
< 3; i
++) {
1833 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
1836 int uniform
= inst
->src
[i
].reg
;
1838 /* If this array isn't already present in the pull constant buffer,
1841 if (pull_constant_loc
[uniform
] == -1) {
1842 const float **values
= &c
->prog_data
.param
[uniform
];
1844 pull_constant_loc
[uniform
] = c
->prog_data
.nr_pull_params
;
1846 assert(param_size
[uniform
]);
1848 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
1849 c
->prog_data
.pull_param
[c
->prog_data
.nr_pull_params
++] =
1854 /* Set up the annotation tracking for new generated instructions. */
1856 current_annotation
= inst
->annotation
;
1858 fs_reg surf_index
= fs_reg(c
->prog_data
.base
.binding_table
.pull_constants_start
);
1859 fs_reg temp
= fs_reg(this, glsl_type::float_type
);
1860 exec_list list
= VARYING_PULL_CONSTANT_LOAD(temp
,
1862 *inst
->src
[i
].reladdr
,
1863 pull_constant_loc
[uniform
] +
1864 inst
->src
[i
].reg_offset
);
1865 inst
->insert_before(&list
);
1867 inst
->src
[i
].file
= temp
.file
;
1868 inst
->src
[i
].reg
= temp
.reg
;
1869 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
1870 inst
->src
[i
].reladdr
= NULL
;
1876 * Choose accesses from the UNIFORM file to demote to using the pull
1879 * We allow a fragment shader to have more than the specified minimum
1880 * maximum number of fragment shader uniform components (64). If
1881 * there are too many of these, they'd fill up all of register space.
1882 * So, this will push some of them out to the pull constant buffer and
1883 * update the program to load them.
1886 fs_visitor::setup_pull_constants()
1888 /* Only allow 16 registers (128 uniform components) as push constants. */
1889 unsigned int max_uniform_components
= 16 * 8;
1890 if (c
->prog_data
.nr_params
<= max_uniform_components
)
1893 if (dispatch_width
== 16) {
1894 fail("Pull constants not supported in SIMD16\n");
1898 /* Just demote the end of the list. We could probably do better
1899 * here, demoting things that are rarely used in the program first.
1901 unsigned int pull_uniform_base
= max_uniform_components
;
1903 int pull_constant_loc
[c
->prog_data
.nr_params
];
1904 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1905 if (i
< pull_uniform_base
) {
1906 pull_constant_loc
[i
] = -1;
1908 pull_constant_loc
[i
] = -1;
1909 /* If our constant is already being uploaded for reladdr purposes,
1912 for (unsigned int j
= 0; j
< c
->prog_data
.nr_pull_params
; j
++) {
1913 if (c
->prog_data
.pull_param
[j
] == c
->prog_data
.param
[i
]) {
1914 pull_constant_loc
[i
] = j
;
1918 if (pull_constant_loc
[i
] == -1) {
1919 int pull_index
= c
->prog_data
.nr_pull_params
++;
1920 c
->prog_data
.pull_param
[pull_index
] = c
->prog_data
.param
[i
];
1921 pull_constant_loc
[i
] = pull_index
;;
1925 c
->prog_data
.nr_params
= pull_uniform_base
;
1927 foreach_list(node
, &this->instructions
) {
1928 fs_inst
*inst
= (fs_inst
*)node
;
1930 for (int i
= 0; i
< 3; i
++) {
1931 if (inst
->src
[i
].file
!= UNIFORM
)
1934 int pull_index
= pull_constant_loc
[inst
->src
[i
].reg
+
1935 inst
->src
[i
].reg_offset
];
1936 if (pull_index
== -1)
1939 assert(!inst
->src
[i
].reladdr
);
1941 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
1942 fs_reg index
= fs_reg(c
->prog_data
.base
.binding_table
.pull_constants_start
);
1943 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
1945 new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
1946 dst
, index
, offset
);
1947 pull
->ir
= inst
->ir
;
1948 pull
->annotation
= inst
->annotation
;
1950 inst
->insert_before(pull
);
1952 inst
->src
[i
].file
= GRF
;
1953 inst
->src
[i
].reg
= dst
.reg
;
1954 inst
->src
[i
].reg_offset
= 0;
1955 inst
->src
[i
].smear
= pull_index
& 3;
1961 fs_visitor::opt_algebraic()
1963 bool progress
= false;
1965 foreach_list(node
, &this->instructions
) {
1966 fs_inst
*inst
= (fs_inst
*)node
;
1968 switch (inst
->opcode
) {
1969 case BRW_OPCODE_MUL
:
1970 if (inst
->src
[1].file
!= IMM
)
1974 if (inst
->src
[1].is_one()) {
1975 inst
->opcode
= BRW_OPCODE_MOV
;
1976 inst
->src
[1] = reg_undef
;
1982 if (inst
->src
[1].is_zero()) {
1983 inst
->opcode
= BRW_OPCODE_MOV
;
1984 inst
->src
[0] = inst
->src
[1];
1985 inst
->src
[1] = reg_undef
;
1991 case BRW_OPCODE_ADD
:
1992 if (inst
->src
[1].file
!= IMM
)
1996 if (inst
->src
[1].is_zero()) {
1997 inst
->opcode
= BRW_OPCODE_MOV
;
1998 inst
->src
[1] = reg_undef
;
2004 if (inst
->src
[0].equals(inst
->src
[1])) {
2005 inst
->opcode
= BRW_OPCODE_MOV
;
2006 inst
->src
[1] = reg_undef
;
2011 case BRW_OPCODE_LRP
:
2012 if (inst
->src
[1].equals(inst
->src
[2])) {
2013 inst
->opcode
= BRW_OPCODE_MOV
;
2014 inst
->src
[0] = inst
->src
[1];
2015 inst
->src
[1] = reg_undef
;
2016 inst
->src
[2] = reg_undef
;
2021 case BRW_OPCODE_SEL
:
2022 if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2023 switch (inst
->conditional_mod
) {
2024 case BRW_CONDITIONAL_LE
:
2025 case BRW_CONDITIONAL_L
:
2026 switch (inst
->src
[1].type
) {
2027 case BRW_REGISTER_TYPE_F
:
2028 if (inst
->src
[1].imm
.f
>= 1.0f
) {
2029 inst
->opcode
= BRW_OPCODE_MOV
;
2030 inst
->src
[1] = reg_undef
;
2038 case BRW_CONDITIONAL_GE
:
2039 case BRW_CONDITIONAL_G
:
2040 switch (inst
->src
[1].type
) {
2041 case BRW_REGISTER_TYPE_F
:
2042 if (inst
->src
[1].imm
.f
<= 0.0f
) {
2043 inst
->opcode
= BRW_OPCODE_MOV
;
2044 inst
->src
[1] = reg_undef
;
2045 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2066 * Removes any instructions writing a VGRF where that VGRF is not used by any
2067 * later instruction.
2070 fs_visitor::dead_code_eliminate()
2072 bool progress
= false;
2075 calculate_live_intervals();
2077 foreach_list_safe(node
, &this->instructions
) {
2078 fs_inst
*inst
= (fs_inst
*)node
;
2080 if (inst
->dst
.file
== GRF
&& !inst
->has_side_effects()) {
2083 for (int i
= 0; i
< inst
->regs_written
; i
++) {
2084 int var
= live_intervals
->var_from_vgrf
[inst
->dst
.reg
];
2085 assert(live_intervals
->end
[var
+ inst
->dst
.reg_offset
+ i
] >= pc
);
2086 if (live_intervals
->end
[var
+ inst
->dst
.reg_offset
+ i
] != pc
) {
2093 /* Don't dead code eliminate instructions that write to the
2094 * accumulator as a side-effect. Instead just set the destination
2095 * to the null register to free it.
2097 switch (inst
->opcode
) {
2098 case BRW_OPCODE_ADDC
:
2099 case BRW_OPCODE_SUBB
:
2100 case BRW_OPCODE_MACH
:
2101 inst
->dst
= fs_reg(retype(brw_null_reg(), inst
->dst
.type
));
2115 invalidate_live_intervals();
2120 struct dead_code_hash_key
2127 dead_code_hash_compare(const void *a
, const void *b
)
2129 return memcmp(a
, b
, sizeof(struct dead_code_hash_key
)) == 0;
2133 clear_dead_code_hash(struct hash_table
*ht
)
2135 struct hash_entry
*entry
;
2137 hash_table_foreach(ht
, entry
) {
2138 _mesa_hash_table_remove(ht
, entry
);
2143 insert_dead_code_hash(struct hash_table
*ht
,
2144 int vgrf
, int reg_offset
, fs_inst
*inst
)
2146 /* We don't bother freeing keys, because they'll be GCed with the ht. */
2147 struct dead_code_hash_key
*key
= ralloc(ht
, struct dead_code_hash_key
);
2150 key
->reg_offset
= reg_offset
;
2152 _mesa_hash_table_insert(ht
, _mesa_hash_data(key
, sizeof(*key
)), key
, inst
);
2155 static struct hash_entry
*
2156 get_dead_code_hash_entry(struct hash_table
*ht
, int vgrf
, int reg_offset
)
2158 struct dead_code_hash_key key
;
2161 key
.reg_offset
= reg_offset
;
2163 return _mesa_hash_table_search(ht
, _mesa_hash_data(&key
, sizeof(key
)), &key
);
2167 remove_dead_code_hash(struct hash_table
*ht
,
2168 int vgrf
, int reg_offset
)
2170 struct hash_entry
*entry
= get_dead_code_hash_entry(ht
, vgrf
, reg_offset
);
2174 _mesa_hash_table_remove(ht
, entry
);
2178 * Walks basic blocks, removing any regs that are written but not read before
2181 * The dead_code_eliminate() function implements a global dead code
2182 * elimination, but it only handles the removing the last write to a register
2183 * if it's never read. This one can handle intermediate writes, but only
2184 * within a basic block.
2187 fs_visitor::dead_code_eliminate_local()
2189 struct hash_table
*ht
;
2190 bool progress
= false;
2192 ht
= _mesa_hash_table_create(mem_ctx
, dead_code_hash_compare
);
2198 foreach_list_safe(node
, &this->instructions
) {
2199 fs_inst
*inst
= (fs_inst
*)node
;
2201 /* At a basic block, empty the HT since we don't understand dataflow
2204 if (inst
->is_control_flow()) {
2205 clear_dead_code_hash(ht
);
2209 /* Clear the HT of any instructions that got read. */
2210 for (int i
= 0; i
< 3; i
++) {
2211 fs_reg src
= inst
->src
[i
];
2212 if (src
.file
!= GRF
)
2216 if (inst
->is_send_from_grf())
2217 read
= virtual_grf_sizes
[src
.reg
] - src
.reg_offset
;
2219 for (int reg_offset
= src
.reg_offset
;
2220 reg_offset
< src
.reg_offset
+ read
;
2222 remove_dead_code_hash(ht
, src
.reg
, reg_offset
);
2226 /* Add any update of a GRF to the HT, removing a previous write if it
2229 if (inst
->dst
.file
== GRF
) {
2230 if (inst
->regs_written
> 1) {
2231 /* We don't know how to trim channels from an instruction's
2232 * writes, so we can't incrementally remove unread channels from
2233 * it. Just remove whatever it overwrites from the table
2235 for (int i
= 0; i
< inst
->regs_written
; i
++) {
2236 remove_dead_code_hash(ht
,
2238 inst
->dst
.reg_offset
+ i
);
2241 struct hash_entry
*entry
=
2242 get_dead_code_hash_entry(ht
, inst
->dst
.reg
,
2243 inst
->dst
.reg_offset
);
2246 if (inst
->is_partial_write()) {
2247 /* For a partial write, we can't remove any previous dead code
2248 * candidate, since we're just modifying their result.
2251 /* We're completely updating a channel, and there was a
2252 * previous write to the channel that wasn't read. Kill it!
2254 fs_inst
*inst
= (fs_inst
*)entry
->data
;
2259 _mesa_hash_table_remove(ht
, entry
);
2262 if (!inst
->has_side_effects())
2263 insert_dead_code_hash(ht
, inst
->dst
.reg
, inst
->dst
.reg_offset
,
2269 _mesa_hash_table_destroy(ht
, NULL
);
2272 invalidate_live_intervals();
2278 * Implements register coalescing: Checks if the two registers involved in a
2279 * raw move don't interfere, in which case they can both be stored in the same
2280 * place and the MOV removed.
2282 * To do this, all uses of the source of the MOV in the shader are replaced
2283 * with the destination of the MOV. For example:
2285 * add vgrf3:F, vgrf1:F, vgrf2:F
2286 * mov vgrf4:F, vgrf3:F
2287 * mul vgrf5:F, vgrf5:F, vgrf4:F
2291 * add vgrf4:F, vgrf1:F, vgrf2:F
2292 * mul vgrf5:F, vgrf5:F, vgrf4:F
2295 fs_visitor::register_coalesce()
2297 bool progress
= false;
2299 calculate_live_intervals();
2302 int channels_remaining
= 0;
2303 int reg_from
= -1, reg_to
= -1;
2304 int reg_to_offset
[MAX_SAMPLER_MESSAGE_SIZE
];
2305 fs_inst
*mov
[MAX_SAMPLER_MESSAGE_SIZE
];
2307 foreach_list(node
, &this->instructions
) {
2308 fs_inst
*inst
= (fs_inst
*)node
;
2310 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2311 inst
->is_partial_write() ||
2313 inst
->src
[0].file
!= GRF
||
2314 inst
->src
[0].negate
||
2316 inst
->src
[0].smear
!= -1 ||
2317 inst
->dst
.file
!= GRF
||
2318 inst
->dst
.type
!= inst
->src
[0].type
) {
2322 if (virtual_grf_sizes
[inst
->src
[0].reg
] >
2323 virtual_grf_sizes
[inst
->dst
.reg
])
2326 int var_from
= live_intervals
->var_from_reg(&inst
->src
[0]);
2327 int var_to
= live_intervals
->var_from_reg(&inst
->dst
);
2329 if (live_intervals
->vars_interfere(var_from
, var_to
) &&
2330 !inst
->dst
.equals(inst
->src
[0])) {
2332 /* We know that the live ranges of A (var_from) and B (var_to)
2333 * interfere because of the ->vars_interfere() call above. If the end
2334 * of B's live range is after the end of A's range, then we know two
2336 * - the start of B's live range must be in A's live range (since we
2337 * already know the two ranges interfere, this is the only remaining
2339 * - the interference isn't of the form we're looking for (where B is
2340 * entirely inside A)
2342 if (live_intervals
->end
[var_to
] > live_intervals
->end
[var_from
])
2345 bool overwritten
= false;
2348 foreach_list(n
, &this->instructions
) {
2349 fs_inst
*scan_inst
= (fs_inst
*)n
;
2352 if (scan_inst
->is_control_flow()) {
2357 if (scan_ip
<= live_intervals
->start
[var_to
])
2360 if (scan_ip
> live_intervals
->end
[var_to
])
2363 if (scan_inst
->dst
.equals(inst
->dst
) ||
2364 scan_inst
->dst
.equals(inst
->src
[0])) {
2374 if (reg_from
!= inst
->src
[0].reg
) {
2375 reg_from
= inst
->src
[0].reg
;
2377 src_size
= virtual_grf_sizes
[inst
->src
[0].reg
];
2378 assert(src_size
<= MAX_SAMPLER_MESSAGE_SIZE
);
2380 channels_remaining
= src_size
;
2381 memset(mov
, 0, sizeof(mov
));
2383 reg_to
= inst
->dst
.reg
;
2386 if (reg_to
!= inst
->dst
.reg
)
2389 const int offset
= inst
->src
[0].reg_offset
;
2390 reg_to_offset
[offset
] = inst
->dst
.reg_offset
;
2392 channels_remaining
--;
2394 if (channels_remaining
)
2397 bool removed
= false;
2398 for (int i
= 0; i
< src_size
; i
++) {
2402 mov
[i
]->opcode
= BRW_OPCODE_NOP
;
2403 mov
[i
]->conditional_mod
= BRW_CONDITIONAL_NONE
;
2404 mov
[i
]->dst
= reg_undef
;
2405 mov
[i
]->src
[0] = reg_undef
;
2406 mov
[i
]->src
[1] = reg_undef
;
2407 mov
[i
]->src
[2] = reg_undef
;
2411 foreach_list(node
, &this->instructions
) {
2412 fs_inst
*scan_inst
= (fs_inst
*)node
;
2414 for (int i
= 0; i
< src_size
; i
++) {
2416 if (scan_inst
->dst
.file
== GRF
&&
2417 scan_inst
->dst
.reg
== reg_from
&&
2418 scan_inst
->dst
.reg_offset
== i
) {
2419 scan_inst
->dst
.reg
= reg_to
;
2420 scan_inst
->dst
.reg_offset
= reg_to_offset
[i
];
2422 for (int j
= 0; j
< 3; j
++) {
2423 if (scan_inst
->src
[j
].file
== GRF
&&
2424 scan_inst
->src
[j
].reg
== reg_from
&&
2425 scan_inst
->src
[j
].reg_offset
== i
) {
2426 scan_inst
->src
[j
].reg
= reg_to
;
2427 scan_inst
->src
[j
].reg_offset
= reg_to_offset
[i
];
2435 live_intervals
->start
[var_to
] = MIN2(live_intervals
->start
[var_to
],
2436 live_intervals
->start
[var_from
]);
2437 live_intervals
->end
[var_to
] = MAX2(live_intervals
->end
[var_to
],
2438 live_intervals
->end
[var_from
]);
2443 foreach_list_safe(node
, &this->instructions
) {
2444 fs_inst
*inst
= (fs_inst
*)node
;
2446 if (inst
->opcode
== BRW_OPCODE_NOP
) {
2453 invalidate_live_intervals();
2459 fs_visitor::compute_to_mrf()
2461 bool progress
= false;
2464 calculate_live_intervals();
2466 foreach_list_safe(node
, &this->instructions
) {
2467 fs_inst
*inst
= (fs_inst
*)node
;
2472 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2473 inst
->is_partial_write() ||
2474 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2475 inst
->dst
.type
!= inst
->src
[0].type
||
2476 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
2479 /* Work out which hardware MRF registers are written by this
2482 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2484 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2485 mrf_high
= mrf_low
+ 4;
2486 } else if (dispatch_width
== 16 &&
2487 (!inst
->force_uncompressed
&& !inst
->force_sechalf
)) {
2488 mrf_high
= mrf_low
+ 1;
2493 /* Can't compute-to-MRF this GRF if someone else was going to
2496 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2499 /* Found a move of a GRF to a MRF. Let's see if we can go
2500 * rewrite the thing that made this GRF to write into the MRF.
2503 for (scan_inst
= (fs_inst
*)inst
->prev
;
2504 scan_inst
->prev
!= NULL
;
2505 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2506 if (scan_inst
->dst
.file
== GRF
&&
2507 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2508 /* Found the last thing to write our reg we want to turn
2509 * into a compute-to-MRF.
2512 /* If this one instruction didn't populate all the
2513 * channels, bail. We might be able to rewrite everything
2514 * that writes that reg, but it would require smarter
2515 * tracking to delay the rewriting until complete success.
2517 if (scan_inst
->is_partial_write())
2520 /* Things returning more than one register would need us to
2521 * understand coalescing out more than one MOV at a time.
2523 if (scan_inst
->regs_written
> 1)
2526 /* SEND instructions can't have MRF as a destination. */
2527 if (scan_inst
->mlen
)
2530 if (brw
->gen
== 6) {
2531 /* gen6 math instructions must have the destination be
2532 * GRF, so no compute-to-MRF for them.
2534 if (scan_inst
->is_math()) {
2539 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2540 /* Found the creator of our MRF's source value. */
2541 scan_inst
->dst
.file
= MRF
;
2542 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2543 scan_inst
->saturate
|= inst
->saturate
;
2550 /* We don't handle control flow here. Most computation of
2551 * values that end up in MRFs are shortly before the MRF
2554 if (scan_inst
->is_control_flow() && scan_inst
->opcode
!= BRW_OPCODE_IF
)
2557 /* You can't read from an MRF, so if someone else reads our
2558 * MRF's source GRF that we wanted to rewrite, that stops us.
2560 bool interfered
= false;
2561 for (int i
= 0; i
< 3; i
++) {
2562 if (scan_inst
->src
[i
].file
== GRF
&&
2563 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2564 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2571 if (scan_inst
->dst
.file
== MRF
) {
2572 /* If somebody else writes our MRF here, we can't
2573 * compute-to-MRF before that.
2575 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2578 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2579 scan_mrf_high
= scan_mrf_low
+ 4;
2580 } else if (dispatch_width
== 16 &&
2581 (!scan_inst
->force_uncompressed
&&
2582 !scan_inst
->force_sechalf
)) {
2583 scan_mrf_high
= scan_mrf_low
+ 1;
2585 scan_mrf_high
= scan_mrf_low
;
2588 if (mrf_low
== scan_mrf_low
||
2589 mrf_low
== scan_mrf_high
||
2590 mrf_high
== scan_mrf_low
||
2591 mrf_high
== scan_mrf_high
) {
2596 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2597 /* Found a SEND instruction, which means that there are
2598 * live values in MRFs from base_mrf to base_mrf +
2599 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2602 if (mrf_low
>= scan_inst
->base_mrf
&&
2603 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2606 if (mrf_high
>= scan_inst
->base_mrf
&&
2607 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2615 invalidate_live_intervals();
2621 * Walks through basic blocks, looking for repeated MRF writes and
2622 * removing the later ones.
2625 fs_visitor::remove_duplicate_mrf_writes()
2627 fs_inst
*last_mrf_move
[16];
2628 bool progress
= false;
2630 /* Need to update the MRF tracking for compressed instructions. */
2631 if (dispatch_width
== 16)
2634 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2636 foreach_list_safe(node
, &this->instructions
) {
2637 fs_inst
*inst
= (fs_inst
*)node
;
2639 if (inst
->is_control_flow()) {
2640 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2643 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2644 inst
->dst
.file
== MRF
) {
2645 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2646 if (prev_inst
&& inst
->equals(prev_inst
)) {
2653 /* Clear out the last-write records for MRFs that were overwritten. */
2654 if (inst
->dst
.file
== MRF
) {
2655 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2658 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2659 /* Found a SEND instruction, which will include two or fewer
2660 * implied MRF writes. We could do better here.
2662 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2663 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2667 /* Clear out any MRF move records whose sources got overwritten. */
2668 if (inst
->dst
.file
== GRF
) {
2669 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
2670 if (last_mrf_move
[i
] &&
2671 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2672 last_mrf_move
[i
] = NULL
;
2677 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2678 inst
->dst
.file
== MRF
&&
2679 inst
->src
[0].file
== GRF
&&
2680 !inst
->is_partial_write()) {
2681 last_mrf_move
[inst
->dst
.reg
] = inst
;
2686 invalidate_live_intervals();
2692 clear_deps_for_inst_src(fs_inst
*inst
, int dispatch_width
, bool *deps
,
2693 int first_grf
, int grf_len
)
2695 bool inst_simd16
= (dispatch_width
> 8 &&
2696 !inst
->force_uncompressed
&&
2697 !inst
->force_sechalf
);
2699 /* Clear the flag for registers that actually got read (as expected). */
2700 for (int i
= 0; i
< 3; i
++) {
2702 if (inst
->src
[i
].file
== GRF
) {
2703 grf
= inst
->src
[i
].reg
;
2704 } else if (inst
->src
[i
].file
== HW_REG
&&
2705 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2706 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2711 if (grf
>= first_grf
&&
2712 grf
< first_grf
+ grf_len
) {
2713 deps
[grf
- first_grf
] = false;
2715 deps
[grf
- first_grf
+ 1] = false;
2721 * Implements this workaround for the original 965:
2723 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2724 * check for post destination dependencies on this instruction, software
2725 * must ensure that there is no destination hazard for the case of ‘write
2726 * followed by a posted write’ shown in the following example.
2729 * 2. send r3.xy <rest of send instruction>
2732 * Due to no post-destination dependency check on the ‘send’, the above
2733 * code sequence could have two instructions (1 and 2) in flight at the
2734 * same time that both consider ‘r3’ as the target of their final writes.
2737 fs_visitor::insert_gen4_pre_send_dependency_workarounds(fs_inst
*inst
)
2739 int reg_size
= dispatch_width
/ 8;
2740 int write_len
= inst
->regs_written
* reg_size
;
2741 int first_write_grf
= inst
->dst
.reg
;
2742 bool needs_dep
[BRW_MAX_MRF
];
2743 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2745 memset(needs_dep
, false, sizeof(needs_dep
));
2746 memset(needs_dep
, true, write_len
);
2748 clear_deps_for_inst_src(inst
, dispatch_width
,
2749 needs_dep
, first_write_grf
, write_len
);
2751 /* Walk backwards looking for writes to registers we're writing which
2752 * aren't read since being written. If we hit the start of the program,
2753 * we assume that there are no outstanding dependencies on entry to the
2756 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->prev
;
2758 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2760 /* If we hit control flow, assume that there *are* outstanding
2761 * dependencies, and force their cleanup before our instruction.
2763 if (scan_inst
->is_control_flow()) {
2764 for (int i
= 0; i
< write_len
; i
++) {
2766 inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2772 bool scan_inst_simd16
= (dispatch_width
> 8 &&
2773 !scan_inst
->force_uncompressed
&&
2774 !scan_inst
->force_sechalf
);
2776 /* We insert our reads as late as possible on the assumption that any
2777 * instruction but a MOV that might have left us an outstanding
2778 * dependency has more latency than a MOV.
2780 if (scan_inst
->dst
.file
== GRF
) {
2781 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2782 int reg
= scan_inst
->dst
.reg
+ i
* reg_size
;
2784 if (reg
>= first_write_grf
&&
2785 reg
< first_write_grf
+ write_len
&&
2786 needs_dep
[reg
- first_write_grf
]) {
2787 inst
->insert_before(DEP_RESOLVE_MOV(reg
));
2788 needs_dep
[reg
- first_write_grf
] = false;
2789 if (scan_inst_simd16
)
2790 needs_dep
[reg
- first_write_grf
+ 1] = false;
2795 /* Clear the flag for registers that actually got read (as expected). */
2796 clear_deps_for_inst_src(scan_inst
, dispatch_width
,
2797 needs_dep
, first_write_grf
, write_len
);
2799 /* Continue the loop only if we haven't resolved all the dependencies */
2801 for (i
= 0; i
< write_len
; i
++) {
2811 * Implements this workaround for the original 965:
2813 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2814 * used as a destination register until after it has been sourced by an
2815 * instruction with a different destination register.
2818 fs_visitor::insert_gen4_post_send_dependency_workarounds(fs_inst
*inst
)
2820 int write_len
= inst
->regs_written
* dispatch_width
/ 8;
2821 int first_write_grf
= inst
->dst
.reg
;
2822 bool needs_dep
[BRW_MAX_MRF
];
2823 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2825 memset(needs_dep
, false, sizeof(needs_dep
));
2826 memset(needs_dep
, true, write_len
);
2827 /* Walk forwards looking for writes to registers we're writing which aren't
2828 * read before being written.
2830 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->next
;
2831 !scan_inst
->is_tail_sentinel();
2832 scan_inst
= (fs_inst
*)scan_inst
->next
) {
2833 /* If we hit control flow, force resolve all remaining dependencies. */
2834 if (scan_inst
->is_control_flow()) {
2835 for (int i
= 0; i
< write_len
; i
++) {
2837 scan_inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2842 /* Clear the flag for registers that actually got read (as expected). */
2843 clear_deps_for_inst_src(scan_inst
, dispatch_width
,
2844 needs_dep
, first_write_grf
, write_len
);
2846 /* We insert our reads as late as possible since they're reading the
2847 * result of a SEND, which has massive latency.
2849 if (scan_inst
->dst
.file
== GRF
&&
2850 scan_inst
->dst
.reg
>= first_write_grf
&&
2851 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
2852 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
2853 scan_inst
->insert_before(DEP_RESOLVE_MOV(scan_inst
->dst
.reg
));
2854 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
2857 /* Continue the loop only if we haven't resolved all the dependencies */
2859 for (i
= 0; i
< write_len
; i
++) {
2867 /* If we hit the end of the program, resolve all remaining dependencies out
2870 fs_inst
*last_inst
= (fs_inst
*)this->instructions
.get_tail();
2871 assert(last_inst
->eot
);
2872 for (int i
= 0; i
< write_len
; i
++) {
2874 last_inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2879 fs_visitor::insert_gen4_send_dependency_workarounds()
2881 if (brw
->gen
!= 4 || brw
->is_g4x
)
2884 /* Note that we're done with register allocation, so GRF fs_regs always
2885 * have a .reg_offset of 0.
2888 foreach_list_safe(node
, &this->instructions
) {
2889 fs_inst
*inst
= (fs_inst
*)node
;
2891 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
2892 insert_gen4_pre_send_dependency_workarounds(inst
);
2893 insert_gen4_post_send_dependency_workarounds(inst
);
2899 * Turns the generic expression-style uniform pull constant load instruction
2900 * into a hardware-specific series of instructions for loading a pull
2903 * The expression style allows the CSE pass before this to optimize out
2904 * repeated loads from the same offset, and gives the pre-register-allocation
2905 * scheduling full flexibility, while the conversion to native instructions
2906 * allows the post-register-allocation scheduler the best information
2909 * Note that execution masking for setting up pull constant loads is special:
2910 * the channels that need to be written are unrelated to the current execution
2911 * mask, since a later instruction will use one of the result channels as a
2912 * source operand for all 8 or 16 of its channels.
2915 fs_visitor::lower_uniform_pull_constant_loads()
2917 foreach_list(node
, &this->instructions
) {
2918 fs_inst
*inst
= (fs_inst
*)node
;
2920 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
2923 if (brw
->gen
>= 7) {
2924 /* The offset arg before was a vec4-aligned byte offset. We need to
2925 * turn it into a dword offset.
2927 fs_reg const_offset_reg
= inst
->src
[1];
2928 assert(const_offset_reg
.file
== IMM
&&
2929 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
2930 const_offset_reg
.imm
.u
/= 4;
2931 fs_reg payload
= fs_reg(this, glsl_type::uint_type
);
2933 /* This is actually going to be a MOV, but since only the first dword
2934 * is accessed, we have a special opcode to do just that one. Note
2935 * that this needs to be an operation that will be considered a def
2936 * by live variable analysis, or register allocation will explode.
2938 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
2939 payload
, const_offset_reg
);
2940 setup
->force_writemask_all
= true;
2942 setup
->ir
= inst
->ir
;
2943 setup
->annotation
= inst
->annotation
;
2944 inst
->insert_before(setup
);
2946 /* Similarly, this will only populate the first 4 channels of the
2947 * result register (since we only use smear values from 0-3), but we
2948 * don't tell the optimizer.
2950 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
2951 inst
->src
[1] = payload
;
2953 invalidate_live_intervals();
2955 /* Before register allocation, we didn't tell the scheduler about the
2956 * MRF we use. We know it's safe to use this MRF because nothing
2957 * else does except for register spill/unspill, which generates and
2958 * uses its MRF within a single IR instruction.
2960 inst
->base_mrf
= 14;
2967 fs_visitor::dump_instructions()
2969 calculate_register_pressure();
2971 int ip
= 0, max_pressure
= 0;
2972 foreach_list(node
, &this->instructions
) {
2973 backend_instruction
*inst
= (backend_instruction
*)node
;
2974 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
2975 printf("{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
2976 dump_instruction(inst
);
2979 printf("Maximum %3d registers live at once.\n", max_pressure
);
2983 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
2985 fs_inst
*inst
= (fs_inst
*)be_inst
;
2987 if (inst
->predicate
) {
2988 printf("(%cf0.%d) ",
2989 inst
->predicate_inverse
? '-' : '+',
2993 printf("%s", brw_instruction_name(inst
->opcode
));
2996 if (inst
->conditional_mod
) {
2997 printf("%s", conditional_modifier
[inst
->conditional_mod
]);
2998 if (!inst
->predicate
&&
2999 (brw
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
3000 inst
->opcode
!= BRW_OPCODE_IF
&&
3001 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
3002 printf(".f0.%d", inst
->flag_subreg
);
3008 switch (inst
->dst
.file
) {
3010 printf("vgrf%d", inst
->dst
.reg
);
3011 if (virtual_grf_sizes
[inst
->dst
.reg
] != 1)
3012 printf("+%d", inst
->dst
.reg_offset
);
3015 printf("m%d", inst
->dst
.reg
);
3021 printf("***u%d***", inst
->dst
.reg
);
3024 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3025 switch (inst
->dst
.fixed_hw_reg
.nr
) {
3029 case BRW_ARF_ADDRESS
:
3030 printf("a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
3032 case BRW_ARF_ACCUMULATOR
:
3033 printf("acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
3036 printf("f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3037 inst
->dst
.fixed_hw_reg
.subnr
);
3040 printf("arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3041 inst
->dst
.fixed_hw_reg
.subnr
);
3045 printf("hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
3047 if (inst
->dst
.fixed_hw_reg
.subnr
)
3048 printf("+%d", inst
->dst
.fixed_hw_reg
.subnr
);
3054 printf(":%s, ", reg_encoding
[inst
->dst
.type
]);
3056 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
3057 if (inst
->src
[i
].negate
)
3059 if (inst
->src
[i
].abs
)
3061 switch (inst
->src
[i
].file
) {
3063 printf("vgrf%d", inst
->src
[i
].reg
);
3064 if (virtual_grf_sizes
[inst
->src
[i
].reg
] != 1)
3065 printf("+%d", inst
->src
[i
].reg_offset
);
3068 printf("***m%d***", inst
->src
[i
].reg
);
3071 printf("u%d", inst
->src
[i
].reg
);
3072 if (virtual_grf_sizes
[inst
->src
[i
].reg
] != 1)
3073 printf(".%d", inst
->src
[i
].reg_offset
);
3079 switch (inst
->src
[i
].type
) {
3080 case BRW_REGISTER_TYPE_F
:
3081 printf("%ff", inst
->src
[i
].imm
.f
);
3083 case BRW_REGISTER_TYPE_D
:
3084 printf("%dd", inst
->src
[i
].imm
.i
);
3086 case BRW_REGISTER_TYPE_UD
:
3087 printf("%uu", inst
->src
[i
].imm
.u
);
3095 if (inst
->src
[i
].fixed_hw_reg
.negate
)
3097 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3099 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3100 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
3104 case BRW_ARF_ADDRESS
:
3105 printf("a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3107 case BRW_ARF_ACCUMULATOR
:
3108 printf("acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3111 printf("f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3112 inst
->src
[i
].fixed_hw_reg
.subnr
);
3115 printf("arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3116 inst
->src
[i
].fixed_hw_reg
.subnr
);
3120 printf("hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
3122 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
3123 printf("+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3124 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3131 if (inst
->src
[i
].abs
)
3134 if (inst
->src
[i
].file
!= IMM
) {
3135 printf(":%s", brw_reg_type_letters(inst
->src
[i
].type
));
3138 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
3144 if (inst
->force_uncompressed
)
3147 if (inst
->force_sechalf
)
3154 * Possibly returns an instruction that set up @param reg.
3156 * Sometimes we want to take the result of some expression/variable
3157 * dereference tree and rewrite the instruction generating the result
3158 * of the tree. When processing the tree, we know that the
3159 * instructions generated are all writing temporaries that are dead
3160 * outside of this tree. So, if we have some instructions that write
3161 * a temporary, we're free to point that temp write somewhere else.
3163 * Note that this doesn't guarantee that the instruction generated
3164 * only reg -- it might be the size=4 destination of a texture instruction.
3167 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
3172 end
->is_partial_write() ||
3174 !reg
.equals(end
->dst
)) {
3182 fs_visitor::setup_payload_gen6()
3185 (fp
->Base
.InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
3186 unsigned barycentric_interp_modes
= c
->prog_data
.barycentric_interp_modes
;
3188 assert(brw
->gen
>= 6);
3190 /* R0-1: masks, pixel X/Y coordinates. */
3191 c
->nr_payload_regs
= 2;
3192 /* R2: only for 32-pixel dispatch.*/
3194 /* R3-26: barycentric interpolation coordinates. These appear in the
3195 * same order that they appear in the brw_wm_barycentric_interp_mode
3196 * enum. Each set of coordinates occupies 2 registers if dispatch width
3197 * == 8 and 4 registers if dispatch width == 16. Coordinates only
3198 * appear if they were enabled using the "Barycentric Interpolation
3199 * Mode" bits in WM_STATE.
3201 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
3202 if (barycentric_interp_modes
& (1 << i
)) {
3203 c
->barycentric_coord_reg
[i
] = c
->nr_payload_regs
;
3204 c
->nr_payload_regs
+= 2;
3205 if (dispatch_width
== 16) {
3206 c
->nr_payload_regs
+= 2;
3211 /* R27: interpolated depth if uses source depth */
3213 c
->source_depth_reg
= c
->nr_payload_regs
;
3214 c
->nr_payload_regs
++;
3215 if (dispatch_width
== 16) {
3216 /* R28: interpolated depth if not SIMD8. */
3217 c
->nr_payload_regs
++;
3220 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
3222 c
->source_w_reg
= c
->nr_payload_regs
;
3223 c
->nr_payload_regs
++;
3224 if (dispatch_width
== 16) {
3225 /* R30: interpolated W if not SIMD8. */
3226 c
->nr_payload_regs
++;
3230 c
->prog_data
.uses_pos_offset
= c
->key
.compute_pos_offset
;
3231 /* R31: MSAA position offsets. */
3232 if (c
->prog_data
.uses_pos_offset
) {
3233 c
->sample_pos_reg
= c
->nr_payload_regs
;
3234 c
->nr_payload_regs
++;
3237 /* R32: MSAA input coverage mask */
3238 if (fp
->Base
.SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
3239 assert(brw
->gen
>= 7);
3240 c
->sample_mask_reg
= c
->nr_payload_regs
;
3241 c
->nr_payload_regs
++;
3242 if (dispatch_width
== 16) {
3243 /* R33: input coverage mask if not SIMD8. */
3244 c
->nr_payload_regs
++;
3248 /* R34-: bary for 32-pixel. */
3249 /* R58-59: interp W for 32-pixel. */
3251 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3252 c
->source_depth_to_render_target
= true;
3257 fs_visitor::assign_binding_table_offsets()
3259 uint32_t next_binding_table_offset
= 0;
3261 /* If there are no color regions, we still perform an FB write to a null
3262 * renderbuffer, which we place at surface index 0.
3264 c
->prog_data
.binding_table
.render_target_start
= next_binding_table_offset
;
3265 next_binding_table_offset
+= MAX2(c
->key
.nr_color_regions
, 1);
3267 assign_common_binding_table_offsets(next_binding_table_offset
);
3271 fs_visitor::calculate_register_pressure()
3273 calculate_live_intervals();
3275 int num_instructions
= 0;
3276 foreach_list(node
, &this->instructions
) {
3280 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
3282 for (int reg
= 0; reg
< virtual_grf_count
; reg
++) {
3283 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
3284 regs_live_at_ip
[ip
] += virtual_grf_sizes
[reg
];
3291 sanity_param_count
= fp
->Base
.Parameters
->NumParameters
;
3292 uint32_t orig_nr_params
= c
->prog_data
.nr_params
;
3293 bool allocated_without_spills
;
3295 assign_binding_table_offsets();
3298 setup_payload_gen6();
3300 setup_payload_gen4();
3305 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3306 emit_shader_time_begin();
3308 calculate_urb_setup();
3309 if (fp
->Base
.InputsRead
> 0) {
3311 emit_interpolation_setup_gen4();
3313 emit_interpolation_setup_gen6();
3316 /* We handle discards by keeping track of the still-live pixels in f0.1.
3317 * Initialize it with the dispatched pixels.
3319 if (fp
->UsesKill
|| c
->key
.alpha_test_func
) {
3320 fs_inst
*discard_init
= emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
3321 discard_init
->flag_subreg
= 1;
3324 /* Generate FS IR for main(). (the visitor only descends into
3325 * functions called "main").
3328 foreach_list(node
, &*shader
->base
.ir
) {
3329 ir_instruction
*ir
= (ir_instruction
*)node
;
3331 this->result
= reg_undef
;
3335 emit_fragment_program_code();
3341 emit(FS_OPCODE_PLACEHOLDER_HALT
);
3343 if (c
->key
.alpha_test_func
)
3348 split_virtual_grfs();
3350 move_uniform_array_access_to_pull_constants();
3351 remove_dead_constants();
3352 setup_pull_constants();
3358 compact_virtual_grfs();
3360 progress
= remove_duplicate_mrf_writes() || progress
;
3362 progress
= opt_algebraic() || progress
;
3363 progress
= opt_cse() || progress
;
3364 progress
= opt_copy_propagate() || progress
;
3365 progress
= opt_peephole_predicated_break() || progress
;
3366 progress
= dead_code_eliminate() || progress
;
3367 progress
= dead_code_eliminate_local() || progress
;
3368 progress
= opt_peephole_sel() || progress
;
3369 progress
= dead_control_flow_eliminate(this) || progress
;
3370 progress
= opt_saturate_propagation() || progress
;
3371 progress
= register_coalesce() || progress
;
3372 progress
= compute_to_mrf() || progress
;
3375 lower_uniform_pull_constant_loads();
3377 assign_curb_setup();
3380 static enum instruction_scheduler_mode pre_modes
[] = {
3382 SCHEDULE_PRE_NON_LIFO
,
3386 /* Try each scheduling heuristic to see if it can successfully register
3387 * allocate without spilling. They should be ordered by decreasing
3388 * performance but increasing likelihood of allocating.
3390 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
3391 schedule_instructions(pre_modes
[i
]);
3394 assign_regs_trivial();
3395 allocated_without_spills
= true;
3397 allocated_without_spills
= assign_regs(false);
3399 if (allocated_without_spills
)
3403 if (!allocated_without_spills
) {
3404 /* We assume that any spilling is worse than just dropping back to
3405 * SIMD8. There's probably actually some intermediate point where
3406 * SIMD16 with a couple of spills is still better.
3408 if (dispatch_width
== 16) {
3409 fail("Failure to register allocate. Reduce number of "
3410 "live scalar values to avoid this.");
3413 /* Since we're out of heuristics, just go spill registers until we
3414 * get an allocation.
3416 while (!assign_regs(true)) {
3422 assert(force_uncompressed_stack
== 0);
3424 /* This must come after all optimization and register allocation, since
3425 * it inserts dead code that happens to have side effects, and it does
3426 * so based on the actual physical registers in use.
3428 insert_gen4_send_dependency_workarounds();
3433 if (!allocated_without_spills
)
3434 schedule_instructions(SCHEDULE_POST
);
3436 if (dispatch_width
== 8) {
3437 c
->prog_data
.reg_blocks
= brw_register_blocks(grf_used
);
3439 c
->prog_data
.reg_blocks_16
= brw_register_blocks(grf_used
);
3441 /* Make sure we didn't try to sneak in an extra uniform */
3442 assert(orig_nr_params
== c
->prog_data
.nr_params
);
3443 (void) orig_nr_params
;
3446 /* If any state parameters were appended, then ParameterValues could have
3447 * been realloced, in which case the driver uniform storage set up by
3448 * _mesa_associate_uniform_storage() would point to freed memory. Make
3449 * sure that didn't happen.
3451 assert(sanity_param_count
== fp
->Base
.Parameters
->NumParameters
);
3457 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
,
3458 struct gl_fragment_program
*fp
,
3459 struct gl_shader_program
*prog
,
3460 unsigned *final_assembly_size
)
3462 bool start_busy
= false;
3463 float start_time
= 0;
3465 if (unlikely(brw
->perf_debug
)) {
3466 start_busy
= (brw
->batch
.last_bo
&&
3467 drm_intel_bo_busy(brw
->batch
.last_bo
));
3468 start_time
= get_time();
3471 struct brw_shader
*shader
= NULL
;
3473 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3475 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3477 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3478 _mesa_print_ir(shader
->base
.ir
, NULL
);
3481 printf("ARB_fragment_program %d ir for native fragment shader\n",
3483 _mesa_print_program(&fp
->Base
);
3487 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3489 fs_visitor
v(brw
, c
, prog
, fp
, 8);
3492 prog
->LinkStatus
= false;
3493 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
3496 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
3502 exec_list
*simd16_instructions
= NULL
;
3503 fs_visitor
v2(brw
, c
, prog
, fp
, 16);
3504 if (brw
->gen
>= 5 && likely(!(INTEL_DEBUG
& DEBUG_NO16
))) {
3505 if (c
->prog_data
.nr_pull_params
== 0) {
3506 /* Try a SIMD16 compile */
3507 v2
.import_uniforms(&v
);
3509 perf_debug("SIMD16 shader failed to compile, falling back to "
3510 "SIMD8 at a 10-20%% performance cost: %s", v2
.fail_msg
);
3512 simd16_instructions
= &v2
.instructions
;
3515 perf_debug("Skipping SIMD16 due to pull parameters.\n");
3519 const unsigned *assembly
= NULL
;
3520 if (brw
->gen
>= 8) {
3521 gen8_fs_generator
g(brw
, c
, prog
, fp
, v
.dual_src_output
.file
!= BAD_FILE
);
3522 assembly
= g
.generate_assembly(&v
.instructions
, simd16_instructions
,
3523 final_assembly_size
);
3525 fs_generator
g(brw
, c
, prog
, fp
, v
.dual_src_output
.file
!= BAD_FILE
);
3526 assembly
= g
.generate_assembly(&v
.instructions
, simd16_instructions
,
3527 final_assembly_size
);
3530 if (unlikely(brw
->perf_debug
) && shader
) {
3531 if (shader
->compiled_once
)
3532 brw_wm_debug_recompile(brw
, prog
, &c
->key
);
3533 shader
->compiled_once
= true;
3535 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
3536 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
3537 (get_time() - start_time
) * 1000);
3545 brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
3547 struct brw_context
*brw
= brw_context(ctx
);
3548 struct brw_wm_prog_key key
;
3550 if (!prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
])
3553 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)
3554 prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
]->Program
;
3555 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
3556 bool program_uses_dfdy
= fp
->UsesDFdy
;
3558 memset(&key
, 0, sizeof(key
));
3562 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
3564 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
3565 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
3567 /* Just assume depth testing. */
3568 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
3569 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
3572 if (brw
->gen
< 6 || _mesa_bitcount_64(fp
->Base
.InputsRead
&
3573 BRW_FS_VARYING_INPUT_MASK
) > 16)
3574 key
.input_slots_valid
= fp
->Base
.InputsRead
| VARYING_BIT_POS
;
3576 key
.clamp_fragment_color
= ctx
->API
== API_OPENGL_COMPAT
;
3578 unsigned sampler_count
= _mesa_fls(fp
->Base
.SamplersUsed
);
3579 for (unsigned i
= 0; i
< sampler_count
; i
++) {
3580 if (fp
->Base
.ShadowSamplers
& (1 << i
)) {
3581 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
3582 key
.tex
.swizzles
[i
] =
3583 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
3585 /* Color sampler: assume no swizzling. */
3586 key
.tex
.swizzles
[i
] = SWIZZLE_XYZW
;
3590 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
) {
3591 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
3594 key
.nr_color_regions
= _mesa_bitcount_64(fp
->Base
.OutputsWritten
&
3595 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
3596 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
)));
3598 if ((fp
->Base
.InputsRead
& VARYING_BIT_POS
) || program_uses_dfdy
) {
3599 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
) ||
3600 key
.nr_color_regions
> 1;
3603 /* GL_FRAGMENT_SHADER_DERIVATIVE_HINT is almost always GL_DONT_CARE. The
3604 * quality of the derivatives is likely to be determined by the driconf
3607 key
.high_quality_derivatives
= brw
->disable_derivative_optimization
;
3609 key
.program_string_id
= bfp
->id
;
3611 uint32_t old_prog_offset
= brw
->wm
.base
.prog_offset
;
3612 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
3614 bool success
= do_wm_prog(brw
, prog
, bfp
, &key
);
3616 brw
->wm
.base
.prog_offset
= old_prog_offset
;
3617 brw
->wm
.prog_data
= old_prog_data
;