2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "brw_dead_control_flow.h"
47 #include "main/uniforms.h"
48 #include "brw_fs_live_variables.h"
49 #include "glsl/glsl_types.h"
50 #include "program/sampler.h"
53 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
54 const fs_reg
*src
, unsigned sources
)
56 memset(this, 0, sizeof(*this));
58 this->src
= new fs_reg
[MAX2(sources
, 3)];
59 for (unsigned i
= 0; i
< sources
; i
++)
60 this->src
[i
] = src
[i
];
62 this->opcode
= opcode
;
64 this->sources
= sources
;
65 this->exec_size
= exec_size
;
67 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
69 /* If exec_size == 0, try to guess it from the registers. Since all
70 * manner of things may use hardware registers, we first try to guess
71 * based on GRF registers. If this fails, we will go ahead and take the
72 * width from the destination register.
74 if (this->exec_size
== 0) {
75 if (dst
.file
== GRF
) {
76 this->exec_size
= dst
.width
;
78 for (unsigned i
= 0; i
< sources
; ++i
) {
79 if (src
[i
].file
!= GRF
&& src
[i
].file
!= ATTR
)
82 if (this->exec_size
<= 1)
83 this->exec_size
= src
[i
].width
;
84 assert(src
[i
].width
== 1 || src
[i
].width
== this->exec_size
);
88 if (this->exec_size
== 0 && dst
.file
!= BAD_FILE
)
89 this->exec_size
= dst
.width
;
91 assert(this->exec_size
!= 0);
93 for (unsigned i
= 0; i
< sources
; ++i
) {
94 switch (this->src
[i
].file
) {
96 this->src
[i
].effective_width
= 8;
101 assert(this->src
[i
].width
> 0);
102 if (this->src
[i
].width
== 1) {
103 this->src
[i
].effective_width
= this->exec_size
;
105 this->src
[i
].effective_width
= this->src
[i
].width
;
110 this->src
[i
].effective_width
= this->exec_size
;
113 unreachable("Invalid source register file");
116 this->dst
.effective_width
= this->exec_size
;
118 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
120 /* This will be the case for almost all instructions. */
127 DIV_ROUND_UP(MAX2(dst
.width
* dst
.stride
, 1) * type_sz(dst
.type
), 32);
130 this->regs_written
= 0;
134 unreachable("Invalid destination register file");
136 unreachable("Invalid register file");
139 this->writes_accumulator
= false;
144 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
147 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
149 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
152 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
)
154 init(opcode
, 0, dst
, NULL
, 0);
157 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
160 const fs_reg src
[1] = { src0
};
161 init(opcode
, exec_size
, dst
, src
, 1);
164 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
)
166 const fs_reg src
[1] = { src0
};
167 init(opcode
, 0, dst
, src
, 1);
170 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
171 const fs_reg
&src0
, const fs_reg
&src1
)
173 const fs_reg src
[2] = { src0
, src1
};
174 init(opcode
, exec_size
, dst
, src
, 2);
177 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
180 const fs_reg src
[2] = { src0
, src1
};
181 init(opcode
, 0, dst
, src
, 2);
184 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
185 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
187 const fs_reg src
[3] = { src0
, src1
, src2
};
188 init(opcode
, exec_size
, dst
, src
, 3);
191 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
192 const fs_reg
&src1
, const fs_reg
&src2
)
194 const fs_reg src
[3] = { src0
, src1
, src2
};
195 init(opcode
, 0, dst
, src
, 3);
198 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
,
199 const fs_reg src
[], unsigned sources
)
201 init(opcode
, 0, dst
, src
, sources
);
204 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
205 const fs_reg src
[], unsigned sources
)
207 init(opcode
, exec_width
, dst
, src
, sources
);
210 fs_inst::fs_inst(const fs_inst
&that
)
212 memcpy(this, &that
, sizeof(that
));
214 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
216 for (unsigned i
= 0; i
< that
.sources
; i
++)
217 this->src
[i
] = that
.src
[i
];
226 fs_inst::resize_sources(uint8_t num_sources
)
228 if (this->sources
!= num_sources
) {
229 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
231 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
232 src
[i
] = this->src
[i
];
236 this->sources
= num_sources
;
242 fs_visitor::op(const fs_reg &dst, const fs_reg &src0) \
244 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0); \
249 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
250 const fs_reg &src1) \
252 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
255 #define ALU2_ACC(op) \
257 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
258 const fs_reg &src1) \
260 fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1);\
261 inst->writes_accumulator = true; \
267 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
268 const fs_reg &src1, const fs_reg &src2) \
270 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2);\
302 /** Gen4 predicated IF. */
304 fs_visitor::IF(enum brw_predicate predicate
)
306 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
, dispatch_width
);
307 inst
->predicate
= predicate
;
311 /** Gen6 IF with embedded comparison. */
313 fs_visitor::IF(const fs_reg
&src0
, const fs_reg
&src1
,
314 enum brw_conditional_mod condition
)
316 assert(brw
->gen
== 6);
317 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
, dispatch_width
,
318 reg_null_d
, src0
, src1
);
319 inst
->conditional_mod
= condition
;
324 * CMP: Sets the low bit of the destination channels with the result
325 * of the comparison, while the upper bits are undefined, and updates
326 * the flag register with the packed 16 bits of the result.
329 fs_visitor::CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
,
330 enum brw_conditional_mod condition
)
334 /* Take the instruction:
336 * CMP null<d> src0<f> src1<f>
338 * Original gen4 does type conversion to the destination type before
339 * comparison, producing garbage results for floating point comparisons.
341 * The destination type doesn't matter on newer generations, so we set the
342 * type to match src0 so we can compact the instruction.
344 dst
.type
= src0
.type
;
345 if (dst
.file
== HW_REG
)
346 dst
.fixed_hw_reg
.type
= dst
.type
;
348 resolve_ud_negate(&src0
);
349 resolve_ud_negate(&src1
);
351 inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_CMP
, dst
, src0
, src1
);
352 inst
->conditional_mod
= condition
;
358 fs_visitor::LOAD_PAYLOAD(const fs_reg
&dst
, fs_reg
*src
, int sources
)
360 uint8_t exec_size
= dst
.width
;
361 for (int i
= 0; i
< sources
; ++i
) {
362 assert(src
[i
].width
% dst
.width
== 0);
363 if (src
[i
].width
> exec_size
)
364 exec_size
= src
[i
].width
;
367 fs_inst
*inst
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
, exec_size
,
369 inst
->regs_written
= 0;
370 for (int i
= 0; i
< sources
; ++i
) {
371 /* The LOAD_PAYLOAD instruction only really makes sense if we are
372 * dealing with whole registers. If this ever changes, we can deal
375 int size
= inst
->src
[i
].effective_width
* type_sz(src
[i
].type
);
376 assert(size
% 32 == 0);
377 inst
->regs_written
+= (size
+ 31) / 32;
384 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_reg
&dst
,
385 const fs_reg
&surf_index
,
386 const fs_reg
&varying_offset
,
387 uint32_t const_offset
)
389 exec_list instructions
;
392 /* We have our constant surface use a pitch of 4 bytes, so our index can
393 * be any component of a vector, and then we load 4 contiguous
394 * components starting from that.
396 * We break down the const_offset to a portion added to the variable
397 * offset and a portion done using reg_offset, which means that if you
398 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
399 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
400 * CSE can later notice that those loads are all the same and eliminate
401 * the redundant ones.
403 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
404 instructions
.push_tail(ADD(vec4_offset
,
405 varying_offset
, fs_reg(const_offset
& ~3)));
408 if (brw
->gen
== 4 && dst
.width
== 8) {
409 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
410 * u, v, r) as parameters, or we can just use the SIMD16 message
411 * consisting of (header, u). We choose the second, at the cost of a
412 * longer return length.
419 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
421 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
423 assert(dst
.width
% 8 == 0);
424 int regs_written
= 4 * (dst
.width
/ 8) * scale
;
425 fs_reg vec4_result
= fs_reg(GRF
, alloc
.allocate(regs_written
),
426 dst
.type
, dst
.width
);
427 inst
= new(mem_ctx
) fs_inst(op
, vec4_result
, surf_index
, vec4_offset
);
428 inst
->regs_written
= regs_written
;
429 instructions
.push_tail(inst
);
433 inst
->header_present
= true;
437 inst
->mlen
= 1 + dispatch_width
/ 8;
440 fs_reg result
= offset(vec4_result
, (const_offset
& 3) * scale
);
441 instructions
.push_tail(MOV(dst
, result
));
447 * A helper for MOV generation for fixing up broken hardware SEND dependency
451 fs_visitor::DEP_RESOLVE_MOV(int grf
)
453 fs_inst
*inst
= MOV(brw_null_reg(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
456 inst
->annotation
= "send dependency resolve";
458 /* The caller always wants uncompressed to emit the minimal extra
459 * dependencies, and to avoid having to deal with aligning its regs to 2.
467 fs_inst::equals(fs_inst
*inst
) const
469 return (opcode
== inst
->opcode
&&
470 dst
.equals(inst
->dst
) &&
471 src
[0].equals(inst
->src
[0]) &&
472 src
[1].equals(inst
->src
[1]) &&
473 src
[2].equals(inst
->src
[2]) &&
474 saturate
== inst
->saturate
&&
475 predicate
== inst
->predicate
&&
476 conditional_mod
== inst
->conditional_mod
&&
477 mlen
== inst
->mlen
&&
478 base_mrf
== inst
->base_mrf
&&
479 target
== inst
->target
&&
481 header_present
== inst
->header_present
&&
482 shadow_compare
== inst
->shadow_compare
&&
483 exec_size
== inst
->exec_size
&&
484 offset
== inst
->offset
);
488 fs_inst::overwrites_reg(const fs_reg
®
) const
490 return (reg
.file
== dst
.file
&&
491 reg
.reg
== dst
.reg
&&
492 reg
.reg_offset
>= dst
.reg_offset
&&
493 reg
.reg_offset
< dst
.reg_offset
+ regs_written
);
497 fs_inst::is_send_from_grf() const
500 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
501 case SHADER_OPCODE_SHADER_TIME_ADD
:
502 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
503 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
504 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
505 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
506 case SHADER_OPCODE_UNTYPED_ATOMIC
:
507 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
508 case SHADER_OPCODE_URB_WRITE_SIMD8
:
510 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
511 return src
[1].file
== GRF
;
512 case FS_OPCODE_FB_WRITE
:
513 return src
[0].file
== GRF
;
516 return src
[0].file
== GRF
;
523 fs_inst::can_do_source_mods(struct brw_context
*brw
)
525 if (brw
->gen
== 6 && is_math())
528 if (is_send_from_grf())
531 if (!backend_instruction::can_do_source_mods())
540 memset(this, 0, sizeof(*this));
544 /** Generic unset register constructor. */
548 this->file
= BAD_FILE
;
551 /** Immediate value constructor. */
552 fs_reg::fs_reg(float f
)
556 this->type
= BRW_REGISTER_TYPE_F
;
557 this->fixed_hw_reg
.dw1
.f
= f
;
561 /** Immediate value constructor. */
562 fs_reg::fs_reg(int32_t i
)
566 this->type
= BRW_REGISTER_TYPE_D
;
567 this->fixed_hw_reg
.dw1
.d
= i
;
571 /** Immediate value constructor. */
572 fs_reg::fs_reg(uint32_t u
)
576 this->type
= BRW_REGISTER_TYPE_UD
;
577 this->fixed_hw_reg
.dw1
.ud
= u
;
581 /** Vector float immediate value constructor. */
582 fs_reg::fs_reg(uint8_t vf
[4])
586 this->type
= BRW_REGISTER_TYPE_VF
;
587 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
590 /** Vector float immediate value constructor. */
591 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
595 this->type
= BRW_REGISTER_TYPE_VF
;
596 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
602 /** Fixed brw_reg. */
603 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
607 this->fixed_hw_reg
= fixed_hw_reg
;
608 this->type
= fixed_hw_reg
.type
;
609 this->width
= 1 << fixed_hw_reg
.width
;
613 fs_reg::equals(const fs_reg
&r
) const
615 return (file
== r
.file
&&
617 reg_offset
== r
.reg_offset
&&
618 subreg_offset
== r
.subreg_offset
&&
620 negate
== r
.negate
&&
622 !reladdr
&& !r
.reladdr
&&
623 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
, sizeof(fixed_hw_reg
)) == 0 &&
629 fs_reg::set_smear(unsigned subreg
)
631 assert(file
!= HW_REG
&& file
!= IMM
);
632 subreg_offset
= subreg
* type_sz(type
);
638 fs_reg::is_contiguous() const
644 fs_visitor::type_size(const struct glsl_type
*type
)
646 unsigned int size
, i
;
648 switch (type
->base_type
) {
651 case GLSL_TYPE_FLOAT
:
653 return type
->components();
654 case GLSL_TYPE_ARRAY
:
655 return type_size(type
->fields
.array
) * type
->length
;
656 case GLSL_TYPE_STRUCT
:
658 for (i
= 0; i
< type
->length
; i
++) {
659 size
+= type_size(type
->fields
.structure
[i
].type
);
662 case GLSL_TYPE_SAMPLER
:
663 /* Samplers take up no register space, since they're baked in at
667 case GLSL_TYPE_ATOMIC_UINT
:
669 case GLSL_TYPE_IMAGE
:
671 case GLSL_TYPE_ERROR
:
672 case GLSL_TYPE_INTERFACE
:
673 case GLSL_TYPE_DOUBLE
:
674 unreachable("not reached");
681 * Create a MOV to read the timestamp register.
683 * The caller is responsible for emitting the MOV. The return value is
684 * the destination of the MOV, with extra parameters set.
687 fs_visitor::get_timestamp(fs_inst
**out_mov
)
689 assert(brw
->gen
>= 7);
691 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
694 BRW_REGISTER_TYPE_UD
));
696 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
, 4);
698 fs_inst
*mov
= MOV(dst
, ts
);
699 /* We want to read the 3 fields we care about even if it's not enabled in
702 mov
->force_writemask_all
= true;
704 /* The caller wants the low 32 bits of the timestamp. Since it's running
705 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
706 * which is plenty of time for our purposes. It is identical across the
707 * EUs, but since it's tracking GPU core speed it will increment at a
708 * varying rate as render P-states change.
710 * The caller could also check if render P-states have changed (or anything
711 * else that might disrupt timing) by setting smear to 2 and checking if
712 * that field is != 0.
721 fs_visitor::emit_shader_time_begin()
723 current_annotation
= "shader time start";
725 shader_start_time
= get_timestamp(&mov
);
730 fs_visitor::emit_shader_time_end()
732 current_annotation
= "shader time end";
734 enum shader_time_shader_type type
, written_type
, reset_type
;
736 case MESA_SHADER_VERTEX
:
738 written_type
= ST_VS_WRITTEN
;
739 reset_type
= ST_VS_RESET
;
741 case MESA_SHADER_GEOMETRY
:
743 written_type
= ST_GS_WRITTEN
;
744 reset_type
= ST_GS_RESET
;
746 case MESA_SHADER_FRAGMENT
:
747 if (dispatch_width
== 8) {
749 written_type
= ST_FS8_WRITTEN
;
750 reset_type
= ST_FS8_RESET
;
752 assert(dispatch_width
== 16);
754 written_type
= ST_FS16_WRITTEN
;
755 reset_type
= ST_FS16_RESET
;
759 unreachable("fs_visitor::emit_shader_time_end missing code");
762 /* Insert our code just before the final SEND with EOT. */
763 exec_node
*end
= this->instructions
.get_tail();
764 assert(end
&& ((fs_inst
*) end
)->eot
);
767 fs_reg shader_end_time
= get_timestamp(&tm_read
);
768 end
->insert_before(tm_read
);
770 /* Check that there weren't any timestamp reset events (assuming these
771 * were the only two timestamp reads that happened).
773 fs_reg reset
= shader_end_time
;
775 fs_inst
*test
= AND(reg_null_d
, reset
, fs_reg(1u));
776 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
777 test
->force_writemask_all
= true;
778 end
->insert_before(test
);
779 end
->insert_before(IF(BRW_PREDICATE_NORMAL
));
781 fs_reg start
= shader_start_time
;
783 fs_reg diff
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
, 1);
785 fs_inst
*add
= ADD(diff
, start
, shader_end_time
);
786 add
->force_writemask_all
= true;
787 end
->insert_before(add
);
789 /* If there were no instructions between the two timestamp gets, the diff
790 * is 2 cycles. Remove that overhead, so I can forget about that when
791 * trying to determine the time taken for single instructions.
793 add
= ADD(diff
, diff
, fs_reg(-2u));
794 add
->force_writemask_all
= true;
795 end
->insert_before(add
);
797 end
->insert_before(SHADER_TIME_ADD(type
, diff
));
798 end
->insert_before(SHADER_TIME_ADD(written_type
, fs_reg(1u)));
799 end
->insert_before(new(mem_ctx
) fs_inst(BRW_OPCODE_ELSE
, dispatch_width
));
800 end
->insert_before(SHADER_TIME_ADD(reset_type
, fs_reg(1u)));
801 end
->insert_before(new(mem_ctx
) fs_inst(BRW_OPCODE_ENDIF
, dispatch_width
));
805 fs_visitor::SHADER_TIME_ADD(enum shader_time_shader_type type
, fs_reg value
)
807 int shader_time_index
=
808 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
809 fs_reg offset
= fs_reg(shader_time_index
* SHADER_TIME_STRIDE
);
812 if (dispatch_width
== 8)
813 payload
= vgrf(glsl_type::uvec2_type
);
815 payload
= vgrf(glsl_type::uint_type
);
817 return new(mem_ctx
) fs_inst(SHADER_OPCODE_SHADER_TIME_ADD
,
818 fs_reg(), payload
, offset
, value
);
822 fs_visitor::vfail(const char *format
, va_list va
)
831 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
832 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
834 this->fail_msg
= msg
;
837 fprintf(stderr
, "%s", msg
);
842 fs_visitor::fail(const char *format
, ...)
846 va_start(va
, format
);
852 * Mark this program as impossible to compile in SIMD16 mode.
854 * During the SIMD8 compile (which happens first), we can detect and flag
855 * things that are unsupported in SIMD16 mode, so the compiler can skip
856 * the SIMD16 compile altogether.
858 * During a SIMD16 compile (if one happens anyway), this just calls fail().
861 fs_visitor::no16(const char *format
, ...)
865 va_start(va
, format
);
867 if (dispatch_width
== 16) {
870 simd16_unsupported
= true;
872 if (brw
->perf_debug
) {
874 ralloc_vasprintf_append(&no16_msg
, format
, va
);
876 no16_msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
884 fs_visitor::emit(enum opcode opcode
)
886 return emit(new(mem_ctx
) fs_inst(opcode
, dispatch_width
));
890 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
)
892 return emit(new(mem_ctx
) fs_inst(opcode
, dst
));
896 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
)
898 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
));
902 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
905 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
, src1
));
909 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
910 const fs_reg
&src1
, const fs_reg
&src2
)
912 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
, src1
, src2
));
916 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
,
917 fs_reg src
[], int sources
)
919 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src
, sources
));
923 * Returns true if the instruction has a flag that means it won't
924 * update an entire destination register.
926 * For example, dead code elimination and live variable analysis want to know
927 * when a write to a variable screens off any preceding values that were in
931 fs_inst::is_partial_write() const
933 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
934 (this->dst
.width
* type_sz(this->dst
.type
)) < 32 ||
935 !this->dst
.is_contiguous());
939 fs_inst::regs_read(int arg
) const
941 if (is_tex() && arg
== 0 && src
[0].file
== GRF
) {
943 } else if (opcode
== FS_OPCODE_FB_WRITE
&& arg
== 0) {
945 } else if (opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
&& arg
== 0) {
947 } else if (opcode
== SHADER_OPCODE_UNTYPED_ATOMIC
&& arg
== 0) {
949 } else if (opcode
== SHADER_OPCODE_UNTYPED_SURFACE_READ
&& arg
== 0) {
951 } else if (opcode
== FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
&& arg
== 0) {
955 switch (src
[arg
].file
) {
962 if (src
[arg
].stride
== 0) {
965 int size
= src
[arg
].width
* src
[arg
].stride
* type_sz(src
[arg
].type
);
966 return (size
+ 31) / 32;
969 unreachable("MRF registers are not allowed as sources");
971 unreachable("Invalid register file");
976 fs_inst::reads_flag() const
982 fs_inst::writes_flag() const
984 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
985 opcode
!= BRW_OPCODE_IF
&&
986 opcode
!= BRW_OPCODE_WHILE
)) ||
987 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
991 * Returns how many MRFs an FS opcode will write over.
993 * Note that this is not the 0 or 1 implied writes in an actual gen
994 * instruction -- the FS opcodes often generate MOVs in addition.
997 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
1002 if (inst
->base_mrf
== -1)
1005 switch (inst
->opcode
) {
1006 case SHADER_OPCODE_RCP
:
1007 case SHADER_OPCODE_RSQ
:
1008 case SHADER_OPCODE_SQRT
:
1009 case SHADER_OPCODE_EXP2
:
1010 case SHADER_OPCODE_LOG2
:
1011 case SHADER_OPCODE_SIN
:
1012 case SHADER_OPCODE_COS
:
1013 return 1 * dispatch_width
/ 8;
1014 case SHADER_OPCODE_POW
:
1015 case SHADER_OPCODE_INT_QUOTIENT
:
1016 case SHADER_OPCODE_INT_REMAINDER
:
1017 return 2 * dispatch_width
/ 8;
1018 case SHADER_OPCODE_TEX
:
1020 case SHADER_OPCODE_TXD
:
1021 case SHADER_OPCODE_TXF
:
1022 case SHADER_OPCODE_TXF_CMS
:
1023 case SHADER_OPCODE_TXF_MCS
:
1024 case SHADER_OPCODE_TG4
:
1025 case SHADER_OPCODE_TG4_OFFSET
:
1026 case SHADER_OPCODE_TXL
:
1027 case SHADER_OPCODE_TXS
:
1028 case SHADER_OPCODE_LOD
:
1030 case FS_OPCODE_FB_WRITE
:
1032 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1033 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1035 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
1037 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1039 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1040 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1041 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1042 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
1043 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
1044 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
1045 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
1048 unreachable("not reached");
1053 fs_visitor::vgrf(const glsl_type
*const type
)
1055 int reg_width
= dispatch_width
/ 8;
1056 return fs_reg(GRF
, alloc
.allocate(type_size(type
) * reg_width
),
1057 brw_type_for_base_type(type
), dispatch_width
);
1061 fs_visitor::vgrf(int num_components
)
1063 int reg_width
= dispatch_width
/ 8;
1064 return fs_reg(GRF
, alloc
.allocate(num_components
* reg_width
),
1065 BRW_REGISTER_TYPE_F
, dispatch_width
);
1068 /** Fixed HW reg constructor. */
1069 fs_reg::fs_reg(enum register_file file
, int reg
)
1074 this->type
= BRW_REGISTER_TYPE_F
;
1085 /** Fixed HW reg constructor. */
1086 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
)
1102 /** Fixed HW reg constructor. */
1103 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
,
1110 this->width
= width
;
1114 fs_visitor::variable_storage(ir_variable
*var
)
1116 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
1120 import_uniforms_callback(const void *key
,
1124 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
1125 const fs_reg
*reg
= (const fs_reg
*)data
;
1127 if (reg
->file
!= UNIFORM
)
1130 hash_table_insert(dst_ht
, data
, key
);
1133 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1134 * This brings in those uniform definitions
1137 fs_visitor::import_uniforms(fs_visitor
*v
)
1139 hash_table_call_foreach(v
->variable_ht
,
1140 import_uniforms_callback
,
1142 this->push_constant_loc
= v
->push_constant_loc
;
1143 this->pull_constant_loc
= v
->pull_constant_loc
;
1144 this->uniforms
= v
->uniforms
;
1145 this->param_size
= v
->param_size
;
1148 /* Our support for uniforms is piggy-backed on the struct
1149 * gl_fragment_program, because that's where the values actually
1150 * get stored, rather than in some global gl_shader_program uniform
1154 fs_visitor::setup_uniform_values(ir_variable
*ir
)
1156 int namelen
= strlen(ir
->name
);
1158 /* The data for our (non-builtin) uniforms is stored in a series of
1159 * gl_uniform_driver_storage structs for each subcomponent that
1160 * glGetUniformLocation() could name. We know it's been set up in the same
1161 * order we'd walk the type, so walk the list of storage and find anything
1162 * with our name, or the prefix of a component that starts with our name.
1164 unsigned params_before
= uniforms
;
1165 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
1166 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
1168 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
1169 (storage
->name
[namelen
] != 0 &&
1170 storage
->name
[namelen
] != '.' &&
1171 storage
->name
[namelen
] != '[')) {
1175 unsigned slots
= storage
->type
->component_slots();
1176 if (storage
->array_elements
)
1177 slots
*= storage
->array_elements
;
1179 for (unsigned i
= 0; i
< slots
; i
++) {
1180 stage_prog_data
->param
[uniforms
++] = &storage
->storage
[i
];
1184 /* Make sure we actually initialized the right amount of stuff here. */
1185 assert(params_before
+ ir
->type
->component_slots() == uniforms
);
1186 (void)params_before
;
1190 /* Our support for builtin uniforms is even scarier than non-builtin.
1191 * It sits on top of the PROG_STATE_VAR parameters that are
1192 * automatically updated from GL context state.
1195 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
1197 const ir_state_slot
*const slots
= ir
->get_state_slots();
1198 assert(slots
!= NULL
);
1200 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1201 /* This state reference has already been setup by ir_to_mesa, but we'll
1202 * get the same index back here.
1204 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1205 (gl_state_index
*)slots
[i
].tokens
);
1207 /* Add each of the unique swizzles of the element as a parameter.
1208 * This'll end up matching the expected layout of the
1209 * array/matrix/structure we're trying to fill in.
1212 for (unsigned int j
= 0; j
< 4; j
++) {
1213 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
1214 if (swiz
== last_swiz
)
1218 stage_prog_data
->param
[uniforms
++] =
1219 &prog
->Parameters
->ParameterValues
[index
][swiz
];
1225 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
1226 bool origin_upper_left
)
1228 assert(stage
== MESA_SHADER_FRAGMENT
);
1229 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1230 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1232 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
1234 /* gl_FragCoord.x */
1235 if (pixel_center_integer
) {
1236 emit(MOV(wpos
, this->pixel_x
));
1238 emit(ADD(wpos
, this->pixel_x
, fs_reg(0.5f
)));
1240 wpos
= offset(wpos
, 1);
1242 /* gl_FragCoord.y */
1243 if (!flip
&& pixel_center_integer
) {
1244 emit(MOV(wpos
, this->pixel_y
));
1246 fs_reg pixel_y
= this->pixel_y
;
1247 float offset
= (pixel_center_integer
? 0.0 : 0.5);
1250 pixel_y
.negate
= true;
1251 offset
+= key
->drawable_height
- 1.0;
1254 emit(ADD(wpos
, pixel_y
, fs_reg(offset
)));
1256 wpos
= offset(wpos
, 1);
1258 /* gl_FragCoord.z */
1259 if (brw
->gen
>= 6) {
1260 emit(MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0))));
1262 emit(FS_OPCODE_LINTERP
, wpos
,
1263 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1264 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1265 interp_reg(VARYING_SLOT_POS
, 2));
1267 wpos
= offset(wpos
, 1);
1269 /* gl_FragCoord.w: Already set up in emit_interpolation */
1270 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
1276 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1277 glsl_interp_qualifier interpolation_mode
,
1278 bool is_centroid
, bool is_sample
)
1280 brw_wm_barycentric_interp_mode barycoord_mode
;
1281 if (brw
->gen
>= 6) {
1283 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1284 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1286 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1287 } else if (is_sample
) {
1288 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1289 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1291 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1293 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1294 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1296 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1299 /* On Ironlake and below, there is only one interpolation mode.
1300 * Centroid interpolation doesn't mean anything on this hardware --
1301 * there is no multisampling.
1303 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1305 return emit(FS_OPCODE_LINTERP
, attr
,
1306 this->delta_x
[barycoord_mode
],
1307 this->delta_y
[barycoord_mode
], interp
);
1311 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1312 const glsl_type
*type
,
1313 glsl_interp_qualifier interpolation_mode
,
1314 int location
, bool mod_centroid
,
1317 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1319 assert(stage
== MESA_SHADER_FRAGMENT
);
1320 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1321 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1323 unsigned int array_elements
;
1325 if (type
->is_array()) {
1326 array_elements
= type
->length
;
1327 if (array_elements
== 0) {
1328 fail("dereferenced array '%s' has length 0\n", name
);
1330 type
= type
->fields
.array
;
1335 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1337 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1338 if (key
->flat_shade
&& is_gl_Color
) {
1339 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1341 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1345 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1346 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1347 if (prog_data
->urb_setup
[location
] == -1) {
1348 /* If there's no incoming setup data for this slot, don't
1349 * emit interpolation for it.
1351 attr
= offset(attr
, type
->vector_elements
);
1356 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1357 /* Constant interpolation (flat shading) case. The SF has
1358 * handed us defined values in only the constant offset
1359 * field of the setup reg.
1361 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1362 struct brw_reg interp
= interp_reg(location
, k
);
1363 interp
= suboffset(interp
, 3);
1364 interp
.type
= attr
.type
;
1365 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1366 attr
= offset(attr
, 1);
1369 /* Smooth/noperspective interpolation case. */
1370 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1371 struct brw_reg interp
= interp_reg(location
, k
);
1372 if (brw
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1373 /* Get the pixel/sample mask into f0 so that we know
1374 * which pixels are lit. Then, for each channel that is
1375 * unlit, replace the centroid data with non-centroid
1378 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1381 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1383 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1384 inst
->predicate_inverse
= true;
1386 inst
->no_dd_clear
= true;
1388 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1389 mod_centroid
&& !key
->persample_shading
,
1390 mod_sample
|| key
->persample_shading
);
1391 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1392 inst
->predicate_inverse
= false;
1394 inst
->no_dd_check
= true;
1397 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1398 mod_centroid
&& !key
->persample_shading
,
1399 mod_sample
|| key
->persample_shading
);
1401 if (brw
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1402 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
1404 attr
= offset(attr
, 1);
1414 fs_visitor::emit_frontfacing_interpolation()
1416 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1418 if (brw
->gen
>= 6) {
1419 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1420 * a boolean result from this (~0/true or 0/false).
1422 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1423 * this task in only one instruction:
1424 * - a negation source modifier will flip the bit; and
1425 * - a W -> D type conversion will sign extend the bit into the high
1426 * word of the destination.
1428 * An ASR 15 fills the low word of the destination.
1430 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1433 emit(ASR(*reg
, g0
, fs_reg(15)));
1435 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1436 * a boolean result from this (1/true or 0/false).
1438 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1439 * the negation source modifier to flip it. Unfortunately the SHR
1440 * instruction only operates on UD (or D with an abs source modifier)
1441 * sources without negation.
1443 * Instead, use ASR (which will give ~0/true or 0/false).
1445 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1448 emit(ASR(*reg
, g1_6
, fs_reg(31)));
1455 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1457 assert(stage
== MESA_SHADER_FRAGMENT
);
1458 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1459 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1461 if (key
->compute_pos_offset
) {
1462 /* Convert int_sample_pos to floating point */
1463 emit(MOV(dst
, int_sample_pos
));
1464 /* Scale to the range [0, 1] */
1465 emit(MUL(dst
, dst
, fs_reg(1 / 16.0f
)));
1468 /* From ARB_sample_shading specification:
1469 * "When rendering to a non-multisample buffer, or if multisample
1470 * rasterization is disabled, gl_SamplePosition will always be
1473 emit(MOV(dst
, fs_reg(0.5f
)));
1478 fs_visitor::emit_samplepos_setup()
1480 assert(brw
->gen
>= 6);
1482 this->current_annotation
= "compute sample position";
1483 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1485 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1486 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1488 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1489 * mode will be enabled.
1491 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1492 * R31.1:0 Position Offset X/Y for Slot[3:0]
1493 * R31.3:2 Position Offset X/Y for Slot[7:4]
1496 * The X, Y sample positions come in as bytes in thread payload. So, read
1497 * the positions using vstride=16, width=8, hstride=2.
1499 struct brw_reg sample_pos_reg
=
1500 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1501 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1503 if (dispatch_width
== 8) {
1504 emit(MOV(int_sample_x
, fs_reg(sample_pos_reg
)));
1506 emit(MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
)));
1507 emit(MOV(half(int_sample_x
, 1), fs_reg(suboffset(sample_pos_reg
, 16))))
1508 ->force_sechalf
= true;
1510 /* Compute gl_SamplePosition.x */
1511 compute_sample_position(pos
, int_sample_x
);
1512 pos
= offset(pos
, 1);
1513 if (dispatch_width
== 8) {
1514 emit(MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1))));
1516 emit(MOV(half(int_sample_y
, 0),
1517 fs_reg(suboffset(sample_pos_reg
, 1))));
1518 emit(MOV(half(int_sample_y
, 1), fs_reg(suboffset(sample_pos_reg
, 17))))
1519 ->force_sechalf
= true;
1521 /* Compute gl_SamplePosition.y */
1522 compute_sample_position(pos
, int_sample_y
);
1527 fs_visitor::emit_sampleid_setup()
1529 assert(stage
== MESA_SHADER_FRAGMENT
);
1530 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1531 assert(brw
->gen
>= 6);
1533 this->current_annotation
= "compute sample id";
1534 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1536 if (key
->compute_sample_id
) {
1537 fs_reg t1
= vgrf(glsl_type::int_type
);
1538 fs_reg t2
= vgrf(glsl_type::int_type
);
1539 t2
.type
= BRW_REGISTER_TYPE_UW
;
1541 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1542 * 8x multisampling, subspan 0 will represent sample N (where N
1543 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1544 * 7. We can find the value of N by looking at R0.0 bits 7:6
1545 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1546 * (since samples are always delivered in pairs). That is, we
1547 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1548 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1549 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1550 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1551 * populating a temporary variable with the sequence (0, 1, 2, 3),
1552 * and then reading from it using vstride=1, width=4, hstride=0.
1553 * These computations hold good for 4x multisampling as well.
1555 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1556 * the first four slots are sample 0 of subspan 0; the next four
1557 * are sample 1 of subspan 0; the third group is sample 0 of
1558 * subspan 1, and finally sample 1 of subspan 1.
1561 inst
= emit(BRW_OPCODE_AND
, t1
,
1562 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1564 inst
->force_writemask_all
= true;
1565 inst
= emit(BRW_OPCODE_SHR
, t1
, t1
, fs_reg(5));
1566 inst
->force_writemask_all
= true;
1567 /* This works for both SIMD8 and SIMD16 */
1568 inst
= emit(MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210)));
1569 inst
->force_writemask_all
= true;
1570 /* This special instruction takes care of setting vstride=1,
1571 * width=4, hstride=0 of t2 during an ADD instruction.
1573 emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1575 /* As per GL_ARB_sample_shading specification:
1576 * "When rendering to a non-multisample buffer, or if multisample
1577 * rasterization is disabled, gl_SampleID will always be zero."
1579 emit(BRW_OPCODE_MOV
, *reg
, fs_reg(0));
1586 fs_visitor::resolve_source_modifiers(fs_reg
*src
)
1588 if (!src
->abs
&& !src
->negate
)
1591 fs_reg temp
= retype(vgrf(1), src
->type
);
1592 emit(MOV(temp
, *src
));
1597 fs_visitor::fix_math_operand(fs_reg src
)
1599 /* Can't do hstride == 0 args on gen6 math, so expand it out. We
1600 * might be able to do better by doing execsize = 1 math and then
1601 * expanding that result out, but we would need to be careful with
1604 * The hardware ignores source modifiers (negate and abs) on math
1605 * instructions, so we also move to a temp to set those up.
1607 if (brw
->gen
== 6 && src
.file
!= UNIFORM
&& src
.file
!= IMM
&&
1608 !src
.abs
&& !src
.negate
)
1611 /* Gen7 relaxes most of the above restrictions, but still can't use IMM
1614 if (brw
->gen
>= 7 && src
.file
!= IMM
)
1617 fs_reg expanded
= vgrf(glsl_type::float_type
);
1618 expanded
.type
= src
.type
;
1619 emit(BRW_OPCODE_MOV
, expanded
, src
);
1624 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src
)
1627 case SHADER_OPCODE_RCP
:
1628 case SHADER_OPCODE_RSQ
:
1629 case SHADER_OPCODE_SQRT
:
1630 case SHADER_OPCODE_EXP2
:
1631 case SHADER_OPCODE_LOG2
:
1632 case SHADER_OPCODE_SIN
:
1633 case SHADER_OPCODE_COS
:
1636 unreachable("not reached: bad math opcode");
1639 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
1640 * might be able to do better by doing execsize = 1 math and then
1641 * expanding that result out, but we would need to be careful with
1644 * Gen 6 hardware ignores source modifiers (negate and abs) on math
1645 * instructions, so we also move to a temp to set those up.
1647 if (brw
->gen
== 6 || brw
->gen
== 7)
1648 src
= fix_math_operand(src
);
1650 fs_inst
*inst
= emit(opcode
, dst
, src
);
1654 inst
->mlen
= dispatch_width
/ 8;
1661 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
1666 if (brw
->gen
>= 8) {
1667 inst
= emit(opcode
, dst
, src0
, src1
);
1668 } else if (brw
->gen
>= 6) {
1669 src0
= fix_math_operand(src0
);
1670 src1
= fix_math_operand(src1
);
1672 inst
= emit(opcode
, dst
, src0
, src1
);
1674 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
1675 * "Message Payload":
1677 * "Operand0[7]. For the INT DIV functions, this operand is the
1680 * "Operand1[7]. For the INT DIV functions, this operand is the
1683 bool is_int_div
= opcode
!= SHADER_OPCODE_POW
;
1684 fs_reg
&op0
= is_int_div
? src1
: src0
;
1685 fs_reg
&op1
= is_int_div
? src0
: src1
;
1687 emit(MOV(fs_reg(MRF
, base_mrf
+ 1, op1
.type
, dispatch_width
), op1
));
1688 inst
= emit(opcode
, dst
, op0
, reg_null_f
);
1690 inst
->base_mrf
= base_mrf
;
1691 inst
->mlen
= 2 * dispatch_width
/ 8;
1697 fs_visitor::emit_discard_jump()
1699 /* For performance, after a discard, jump to the end of the
1700 * shader if all relevant channels have been discarded.
1702 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1703 discard_jump
->flag_subreg
= 1;
1705 discard_jump
->predicate
= (dispatch_width
== 8)
1706 ? BRW_PREDICATE_ALIGN1_ANY8H
1707 : BRW_PREDICATE_ALIGN1_ANY16H
;
1708 discard_jump
->predicate_inverse
= true;
1712 fs_visitor::assign_curb_setup()
1714 if (dispatch_width
== 8) {
1715 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1717 assert(stage
== MESA_SHADER_FRAGMENT
);
1718 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1719 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1722 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1724 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1725 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1726 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1727 if (inst
->src
[i
].file
== UNIFORM
) {
1728 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1730 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1731 constant_nr
= push_constant_loc
[uniform_nr
];
1733 /* Section 5.11 of the OpenGL 4.1 spec says:
1734 * "Out-of-bounds reads return undefined values, which include
1735 * values from other variables of the active program or zero."
1736 * Just return the first push constant.
1741 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1745 inst
->src
[i
].file
= HW_REG
;
1746 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1747 retype(brw_reg
, inst
->src
[i
].type
),
1748 inst
->src
[i
].subreg_offset
);
1755 fs_visitor::calculate_urb_setup()
1757 assert(stage
== MESA_SHADER_FRAGMENT
);
1758 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1759 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1761 memset(prog_data
->urb_setup
, -1,
1762 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1765 /* Figure out where each of the incoming setup attributes lands. */
1766 if (brw
->gen
>= 6) {
1767 if (_mesa_bitcount_64(prog
->InputsRead
&
1768 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1769 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1770 * first 16 varying inputs, so we can put them wherever we want.
1771 * Just put them in order.
1773 * This is useful because it means that (a) inputs not used by the
1774 * fragment shader won't take up valuable register space, and (b) we
1775 * won't have to recompile the fragment shader if it gets paired with
1776 * a different vertex (or geometry) shader.
1778 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1779 if (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1780 BITFIELD64_BIT(i
)) {
1781 prog_data
->urb_setup
[i
] = urb_next
++;
1785 /* We have enough input varyings that the SF/SBE pipeline stage can't
1786 * arbitrarily rearrange them to suit our whim; we have to put them
1787 * in an order that matches the output of the previous pipeline stage
1788 * (geometry or vertex shader).
1790 struct brw_vue_map prev_stage_vue_map
;
1791 brw_compute_vue_map(brw
, &prev_stage_vue_map
,
1792 key
->input_slots_valid
);
1793 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1794 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1795 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1797 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1798 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1801 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1802 (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1803 BITFIELD64_BIT(varying
))) {
1804 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1807 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1810 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1811 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1812 /* Point size is packed into the header, not as a general attribute */
1813 if (i
== VARYING_SLOT_PSIZ
)
1816 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1817 /* The back color slot is skipped when the front color is
1818 * also written to. In addition, some slots can be
1819 * written in the vertex shader and not read in the
1820 * fragment shader. So the register number must always be
1821 * incremented, mapped or not.
1823 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1824 prog_data
->urb_setup
[i
] = urb_next
;
1830 * It's a FS only attribute, and we did interpolation for this attribute
1831 * in SF thread. So, count it here, too.
1833 * See compile_sf_prog() for more info.
1835 if (prog
->InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1836 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1839 prog_data
->num_varying_inputs
= urb_next
;
1843 fs_visitor::assign_urb_setup()
1845 assert(stage
== MESA_SHADER_FRAGMENT
);
1846 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1848 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1850 /* Offset all the urb_setup[] index by the actual position of the
1851 * setup regs, now that the location of the constants has been chosen.
1853 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1854 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1855 assert(inst
->src
[2].file
== HW_REG
);
1856 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
1859 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1860 assert(inst
->src
[0].file
== HW_REG
);
1861 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1865 /* Each attribute is 4 setup channels, each of which is half a reg. */
1866 this->first_non_payload_grf
=
1867 urb_start
+ prog_data
->num_varying_inputs
* 2;
1871 fs_visitor::assign_vs_urb_setup()
1873 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1874 int grf
, count
, slot
, channel
, attr
;
1876 assert(stage
== MESA_SHADER_VERTEX
);
1877 count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1878 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1881 /* Each attribute is 4 regs. */
1882 this->first_non_payload_grf
=
1883 payload
.num_regs
+ prog_data
->curb_read_length
+ count
* 4;
1885 unsigned vue_entries
=
1886 MAX2(count
, vs_prog_data
->base
.vue_map
.num_slots
);
1888 vs_prog_data
->base
.urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1889 vs_prog_data
->base
.urb_read_length
= (count
+ 1) / 2;
1891 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1893 /* Rewrite all ATTR file references to the hw grf that they land in. */
1894 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1895 for (int i
= 0; i
< inst
->sources
; i
++) {
1896 if (inst
->src
[i
].file
== ATTR
) {
1898 if (inst
->src
[i
].reg
== VERT_ATTRIB_MAX
) {
1901 /* Attributes come in in a contiguous block, ordered by their
1902 * gl_vert_attrib value. That means we can compute the slot
1903 * number for an attribute by masking out the enabled
1904 * attributes before it and counting the bits.
1906 attr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
/ 4;
1907 slot
= _mesa_bitcount_64(vs_prog_data
->inputs_read
&
1908 BITFIELD64_MASK(attr
));
1911 channel
= inst
->src
[i
].reg_offset
& 3;
1913 grf
= payload
.num_regs
+
1914 prog_data
->curb_read_length
+
1917 inst
->src
[i
].file
= HW_REG
;
1918 inst
->src
[i
].fixed_hw_reg
=
1919 retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
);
1926 * Split large virtual GRFs into separate components if we can.
1928 * This is mostly duplicated with what brw_fs_vector_splitting does,
1929 * but that's really conservative because it's afraid of doing
1930 * splitting that doesn't result in real progress after the rest of
1931 * the optimization phases, which would cause infinite looping in
1932 * optimization. We can do it once here, safely. This also has the
1933 * opportunity to split interpolated values, or maybe even uniforms,
1934 * which we don't have at the IR level.
1936 * We want to split, because virtual GRFs are what we register
1937 * allocate and spill (due to contiguousness requirements for some
1938 * instructions), and they're what we naturally generate in the
1939 * codegen process, but most virtual GRFs don't actually need to be
1940 * contiguous sets of GRFs. If we split, we'll end up with reduced
1941 * live intervals and better dead code elimination and coalescing.
1944 fs_visitor::split_virtual_grfs()
1946 int num_vars
= this->alloc
.count
;
1948 /* Count the total number of registers */
1950 int vgrf_to_reg
[num_vars
];
1951 for (int i
= 0; i
< num_vars
; i
++) {
1952 vgrf_to_reg
[i
] = reg_count
;
1953 reg_count
+= alloc
.sizes
[i
];
1956 /* An array of "split points". For each register slot, this indicates
1957 * if this slot can be separated from the previous slot. Every time an
1958 * instruction uses multiple elements of a register (as a source or
1959 * destination), we mark the used slots as inseparable. Then we go
1960 * through and split the registers into the smallest pieces we can.
1962 bool split_points
[reg_count
];
1963 memset(split_points
, 0, sizeof(split_points
));
1965 /* Mark all used registers as fully splittable */
1966 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1967 if (inst
->dst
.file
== GRF
) {
1968 int reg
= vgrf_to_reg
[inst
->dst
.reg
];
1969 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.reg
]; j
++)
1970 split_points
[reg
+ j
] = true;
1973 for (int i
= 0; i
< inst
->sources
; i
++) {
1974 if (inst
->src
[i
].file
== GRF
) {
1975 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
];
1976 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].reg
]; j
++)
1977 split_points
[reg
+ j
] = true;
1983 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
) {
1984 /* PLN opcodes rely on the delta_xy being contiguous. We only have to
1985 * check this for BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because prior to
1986 * Gen6, that was the only supported interpolation mode, and since Gen6,
1987 * delta_x and delta_y are in fixed hardware registers.
1989 int vgrf
= this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
;
1990 split_points
[vgrf_to_reg
[vgrf
] + 1] = false;
1993 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1994 if (inst
->dst
.file
== GRF
) {
1995 int reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1996 for (int j
= 1; j
< inst
->regs_written
; j
++)
1997 split_points
[reg
+ j
] = false;
1999 for (int i
= 0; i
< inst
->sources
; i
++) {
2000 if (inst
->src
[i
].file
== GRF
) {
2001 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
2002 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
2003 split_points
[reg
+ j
] = false;
2008 int new_virtual_grf
[reg_count
];
2009 int new_reg_offset
[reg_count
];
2012 for (int i
= 0; i
< num_vars
; i
++) {
2013 /* The first one should always be 0 as a quick sanity check. */
2014 assert(split_points
[reg
] == false);
2017 new_reg_offset
[reg
] = 0;
2022 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
2023 /* If this is a split point, reset the offset to 0 and allocate a
2024 * new virtual GRF for the previous offset many registers
2026 if (split_points
[reg
]) {
2027 assert(offset
<= MAX_VGRF_SIZE
);
2028 int grf
= alloc
.allocate(offset
);
2029 for (int k
= reg
- offset
; k
< reg
; k
++)
2030 new_virtual_grf
[k
] = grf
;
2033 new_reg_offset
[reg
] = offset
;
2038 /* The last one gets the original register number */
2039 assert(offset
<= MAX_VGRF_SIZE
);
2040 alloc
.sizes
[i
] = offset
;
2041 for (int k
= reg
- offset
; k
< reg
; k
++)
2042 new_virtual_grf
[k
] = i
;
2044 assert(reg
== reg_count
);
2046 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2047 if (inst
->dst
.file
== GRF
) {
2048 reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
2049 inst
->dst
.reg
= new_virtual_grf
[reg
];
2050 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
2051 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2053 for (int i
= 0; i
< inst
->sources
; i
++) {
2054 if (inst
->src
[i
].file
== GRF
) {
2055 reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
2056 inst
->src
[i
].reg
= new_virtual_grf
[reg
];
2057 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
2058 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2062 invalidate_live_intervals();
2066 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
2068 * During code generation, we create tons of temporary variables, many of
2069 * which get immediately killed and are never used again. Yet, in later
2070 * optimization and analysis passes, such as compute_live_intervals, we need
2071 * to loop over all the virtual GRFs. Compacting them can save a lot of
2075 fs_visitor::compact_virtual_grfs()
2077 bool progress
= false;
2078 int remap_table
[this->alloc
.count
];
2079 memset(remap_table
, -1, sizeof(remap_table
));
2081 /* Mark which virtual GRFs are used. */
2082 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
2083 if (inst
->dst
.file
== GRF
)
2084 remap_table
[inst
->dst
.reg
] = 0;
2086 for (int i
= 0; i
< inst
->sources
; i
++) {
2087 if (inst
->src
[i
].file
== GRF
)
2088 remap_table
[inst
->src
[i
].reg
] = 0;
2092 /* Compact the GRF arrays. */
2094 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
2095 if (remap_table
[i
] == -1) {
2096 /* We just found an unused register. This means that we are
2097 * actually going to compact something.
2101 remap_table
[i
] = new_index
;
2102 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
2103 invalidate_live_intervals();
2108 this->alloc
.count
= new_index
;
2110 /* Patch all the instructions to use the newly renumbered registers */
2111 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2112 if (inst
->dst
.file
== GRF
)
2113 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
2115 for (int i
= 0; i
< inst
->sources
; i
++) {
2116 if (inst
->src
[i
].file
== GRF
)
2117 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
2121 /* Patch all the references to delta_x/delta_y, since they're used in
2122 * register allocation. If they're unused, switch them to BAD_FILE so
2123 * we don't think some random VGRF is delta_x/delta_y.
2125 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_x
); i
++) {
2126 if (delta_x
[i
].file
== GRF
) {
2127 if (remap_table
[delta_x
[i
].reg
] != -1) {
2128 delta_x
[i
].reg
= remap_table
[delta_x
[i
].reg
];
2130 delta_x
[i
].file
= BAD_FILE
;
2134 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_y
); i
++) {
2135 if (delta_y
[i
].file
== GRF
) {
2136 if (remap_table
[delta_y
[i
].reg
] != -1) {
2137 delta_y
[i
].reg
= remap_table
[delta_y
[i
].reg
];
2139 delta_y
[i
].file
= BAD_FILE
;
2148 * Implements array access of uniforms by inserting a
2149 * PULL_CONSTANT_LOAD instruction.
2151 * Unlike temporary GRF array access (where we don't support it due to
2152 * the difficulty of doing relative addressing on instruction
2153 * destinations), we could potentially do array access of uniforms
2154 * that were loaded in GRF space as push constants. In real-world
2155 * usage we've seen, though, the arrays being used are always larger
2156 * than we could load as push constants, so just always move all
2157 * uniform array access out to a pull constant buffer.
2160 fs_visitor::move_uniform_array_access_to_pull_constants()
2162 if (dispatch_width
!= 8)
2165 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2166 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
2168 /* Walk through and find array access of uniforms. Put a copy of that
2169 * uniform in the pull constant buffer.
2171 * Note that we don't move constant-indexed accesses to arrays. No
2172 * testing has been done of the performance impact of this choice.
2174 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2175 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2176 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
2179 int uniform
= inst
->src
[i
].reg
;
2181 /* If this array isn't already present in the pull constant buffer,
2184 if (pull_constant_loc
[uniform
] == -1) {
2185 const gl_constant_value
**values
= &stage_prog_data
->param
[uniform
];
2187 assert(param_size
[uniform
]);
2189 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
2190 pull_constant_loc
[uniform
+ j
] = stage_prog_data
->nr_pull_params
;
2192 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
2201 * Assign UNIFORM file registers to either push constants or pull constants.
2203 * We allow a fragment shader to have more than the specified minimum
2204 * maximum number of fragment shader uniform components (64). If
2205 * there are too many of these, they'd fill up all of register space.
2206 * So, this will push some of them out to the pull constant buffer and
2207 * update the program to load them.
2210 fs_visitor::assign_constant_locations()
2212 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
2213 if (dispatch_width
!= 8)
2216 /* Find which UNIFORM registers are still in use. */
2217 bool is_live
[uniforms
];
2218 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2222 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2223 for (int i
= 0; i
< inst
->sources
; i
++) {
2224 if (inst
->src
[i
].file
!= UNIFORM
)
2227 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
2228 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
2229 is_live
[constant_nr
] = true;
2233 /* Only allow 16 registers (128 uniform components) as push constants.
2235 * Just demote the end of the list. We could probably do better
2236 * here, demoting things that are rarely used in the program first.
2238 * If changing this value, note the limitation about total_regs in
2241 unsigned int max_push_components
= 16 * 8;
2242 unsigned int num_push_constants
= 0;
2244 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2246 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2247 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
2248 /* This UNIFORM register is either dead, or has already been demoted
2249 * to a pull const. Mark it as no longer living in the param[] array.
2251 push_constant_loc
[i
] = -1;
2255 if (num_push_constants
< max_push_components
) {
2256 /* Retain as a push constant. Record the location in the params[]
2259 push_constant_loc
[i
] = num_push_constants
++;
2261 /* Demote to a pull constant. */
2262 push_constant_loc
[i
] = -1;
2264 int pull_index
= stage_prog_data
->nr_pull_params
++;
2265 stage_prog_data
->pull_param
[pull_index
] = stage_prog_data
->param
[i
];
2266 pull_constant_loc
[i
] = pull_index
;
2270 stage_prog_data
->nr_params
= num_push_constants
;
2272 /* Up until now, the param[] array has been indexed by reg + reg_offset
2273 * of UNIFORM registers. Condense it to only contain the uniforms we
2274 * chose to upload as push constants.
2276 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2277 int remapped
= push_constant_loc
[i
];
2282 assert(remapped
<= (int)i
);
2283 stage_prog_data
->param
[remapped
] = stage_prog_data
->param
[i
];
2288 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2289 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2292 fs_visitor::demote_pull_constants()
2294 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2295 for (int i
= 0; i
< inst
->sources
; i
++) {
2296 if (inst
->src
[i
].file
!= UNIFORM
)
2300 unsigned location
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
2301 if (location
>= uniforms
) /* Out of bounds access */
2304 pull_index
= pull_constant_loc
[location
];
2306 if (pull_index
== -1)
2309 /* Set up the annotation tracking for new generated instructions. */
2311 current_annotation
= inst
->annotation
;
2313 fs_reg
surf_index(stage_prog_data
->binding_table
.pull_constants_start
);
2314 fs_reg dst
= vgrf(glsl_type::float_type
);
2316 /* Generate a pull load into dst. */
2317 if (inst
->src
[i
].reladdr
) {
2318 exec_list list
= VARYING_PULL_CONSTANT_LOAD(dst
,
2320 *inst
->src
[i
].reladdr
,
2322 inst
->insert_before(block
, &list
);
2323 inst
->src
[i
].reladdr
= NULL
;
2325 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
2327 new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, 8,
2328 dst
, surf_index
, offset
);
2329 inst
->insert_before(block
, pull
);
2330 inst
->src
[i
].set_smear(pull_index
& 3);
2333 /* Rewrite the instruction to use the temporary VGRF. */
2334 inst
->src
[i
].file
= GRF
;
2335 inst
->src
[i
].reg
= dst
.reg
;
2336 inst
->src
[i
].reg_offset
= 0;
2337 inst
->src
[i
].width
= dispatch_width
;
2340 invalidate_live_intervals();
2344 fs_visitor::opt_algebraic()
2346 bool progress
= false;
2348 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2349 switch (inst
->opcode
) {
2350 case BRW_OPCODE_MOV
:
2351 if (inst
->src
[0].file
!= IMM
)
2354 if (inst
->saturate
) {
2355 if (inst
->dst
.type
!= inst
->src
[0].type
)
2356 assert(!"unimplemented: saturate mixed types");
2358 if (brw_saturate_immediate(inst
->dst
.type
,
2359 &inst
->src
[0].fixed_hw_reg
)) {
2360 inst
->saturate
= false;
2366 case BRW_OPCODE_MUL
:
2367 if (inst
->src
[1].file
!= IMM
)
2371 if (inst
->src
[1].is_one()) {
2372 inst
->opcode
= BRW_OPCODE_MOV
;
2373 inst
->src
[1] = reg_undef
;
2379 if (inst
->src
[1].is_negative_one()) {
2380 inst
->opcode
= BRW_OPCODE_MOV
;
2381 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2382 inst
->src
[1] = reg_undef
;
2388 if (inst
->src
[1].is_zero()) {
2389 inst
->opcode
= BRW_OPCODE_MOV
;
2390 inst
->src
[0] = inst
->src
[1];
2391 inst
->src
[1] = reg_undef
;
2396 if (inst
->src
[0].file
== IMM
) {
2397 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2398 inst
->opcode
= BRW_OPCODE_MOV
;
2399 inst
->src
[0].fixed_hw_reg
.dw1
.f
*= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2400 inst
->src
[1] = reg_undef
;
2405 case BRW_OPCODE_ADD
:
2406 if (inst
->src
[1].file
!= IMM
)
2410 if (inst
->src
[1].is_zero()) {
2411 inst
->opcode
= BRW_OPCODE_MOV
;
2412 inst
->src
[1] = reg_undef
;
2417 if (inst
->src
[0].file
== IMM
) {
2418 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2419 inst
->opcode
= BRW_OPCODE_MOV
;
2420 inst
->src
[0].fixed_hw_reg
.dw1
.f
+= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2421 inst
->src
[1] = reg_undef
;
2427 if (inst
->src
[0].equals(inst
->src
[1])) {
2428 inst
->opcode
= BRW_OPCODE_MOV
;
2429 inst
->src
[1] = reg_undef
;
2434 case BRW_OPCODE_LRP
:
2435 if (inst
->src
[1].equals(inst
->src
[2])) {
2436 inst
->opcode
= BRW_OPCODE_MOV
;
2437 inst
->src
[0] = inst
->src
[1];
2438 inst
->src
[1] = reg_undef
;
2439 inst
->src
[2] = reg_undef
;
2444 case BRW_OPCODE_CMP
:
2445 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2447 inst
->src
[0].negate
&&
2448 inst
->src
[1].is_zero()) {
2449 inst
->src
[0].abs
= false;
2450 inst
->src
[0].negate
= false;
2451 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2456 case BRW_OPCODE_SEL
:
2457 if (inst
->src
[0].equals(inst
->src
[1])) {
2458 inst
->opcode
= BRW_OPCODE_MOV
;
2459 inst
->src
[1] = reg_undef
;
2460 inst
->predicate
= BRW_PREDICATE_NONE
;
2461 inst
->predicate_inverse
= false;
2463 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2464 switch (inst
->conditional_mod
) {
2465 case BRW_CONDITIONAL_LE
:
2466 case BRW_CONDITIONAL_L
:
2467 switch (inst
->src
[1].type
) {
2468 case BRW_REGISTER_TYPE_F
:
2469 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
>= 1.0f
) {
2470 inst
->opcode
= BRW_OPCODE_MOV
;
2471 inst
->src
[1] = reg_undef
;
2472 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2480 case BRW_CONDITIONAL_GE
:
2481 case BRW_CONDITIONAL_G
:
2482 switch (inst
->src
[1].type
) {
2483 case BRW_REGISTER_TYPE_F
:
2484 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
<= 0.0f
) {
2485 inst
->opcode
= BRW_OPCODE_MOV
;
2486 inst
->src
[1] = reg_undef
;
2487 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2499 case BRW_OPCODE_MAD
:
2500 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2501 inst
->opcode
= BRW_OPCODE_MOV
;
2502 inst
->src
[1] = reg_undef
;
2503 inst
->src
[2] = reg_undef
;
2505 } else if (inst
->src
[0].is_zero()) {
2506 inst
->opcode
= BRW_OPCODE_MUL
;
2507 inst
->src
[0] = inst
->src
[2];
2508 inst
->src
[2] = reg_undef
;
2510 } else if (inst
->src
[1].is_one()) {
2511 inst
->opcode
= BRW_OPCODE_ADD
;
2512 inst
->src
[1] = inst
->src
[2];
2513 inst
->src
[2] = reg_undef
;
2515 } else if (inst
->src
[2].is_one()) {
2516 inst
->opcode
= BRW_OPCODE_ADD
;
2517 inst
->src
[2] = reg_undef
;
2519 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2520 inst
->opcode
= BRW_OPCODE_ADD
;
2521 inst
->src
[1].fixed_hw_reg
.dw1
.f
*= inst
->src
[2].fixed_hw_reg
.dw1
.f
;
2522 inst
->src
[2] = reg_undef
;
2526 case SHADER_OPCODE_RCP
: {
2527 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2528 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2529 if (inst
->src
[0].equals(prev
->dst
)) {
2530 inst
->opcode
= SHADER_OPCODE_RSQ
;
2531 inst
->src
[0] = prev
->src
[0];
2541 /* Swap if src[0] is immediate. */
2542 if (progress
&& inst
->is_commutative()) {
2543 if (inst
->src
[0].file
== IMM
) {
2544 fs_reg tmp
= inst
->src
[1];
2545 inst
->src
[1] = inst
->src
[0];
2554 fs_visitor::opt_register_renaming()
2556 bool progress
= false;
2559 int remap
[alloc
.count
];
2560 memset(remap
, -1, sizeof(int) * alloc
.count
);
2562 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2563 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2565 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2566 inst
->opcode
== BRW_OPCODE_WHILE
) {
2570 /* Rewrite instruction sources. */
2571 for (int i
= 0; i
< inst
->sources
; i
++) {
2572 if (inst
->src
[i
].file
== GRF
&&
2573 remap
[inst
->src
[i
].reg
] != -1 &&
2574 remap
[inst
->src
[i
].reg
] != inst
->src
[i
].reg
) {
2575 inst
->src
[i
].reg
= remap
[inst
->src
[i
].reg
];
2580 const int dst
= inst
->dst
.reg
;
2583 inst
->dst
.file
== GRF
&&
2584 alloc
.sizes
[inst
->dst
.reg
] == inst
->dst
.width
/ 8 &&
2585 !inst
->is_partial_write()) {
2586 if (remap
[dst
] == -1) {
2589 remap
[dst
] = alloc
.allocate(inst
->dst
.width
/ 8);
2590 inst
->dst
.reg
= remap
[dst
];
2593 } else if (inst
->dst
.file
== GRF
&&
2595 remap
[dst
] != dst
) {
2596 inst
->dst
.reg
= remap
[dst
];
2602 invalidate_live_intervals();
2604 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_x
); i
++) {
2605 if (delta_x
[i
].file
== GRF
&& remap
[delta_x
[i
].reg
] != -1) {
2606 delta_x
[i
].reg
= remap
[delta_x
[i
].reg
];
2609 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_y
); i
++) {
2610 if (delta_y
[i
].file
== GRF
&& remap
[delta_y
[i
].reg
] != -1) {
2611 delta_y
[i
].reg
= remap
[delta_y
[i
].reg
];
2620 * Remove redundant or useless discard jumps.
2622 * For example, we can eliminate jumps in the following sequence:
2624 * discard-jump (redundant with the next jump)
2625 * discard-jump (useless; jumps to the next instruction)
2629 fs_visitor::opt_redundant_discard_jumps()
2631 bool progress
= false;
2633 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2635 fs_inst
*placeholder_halt
= NULL
;
2636 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2637 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2638 placeholder_halt
= inst
;
2643 if (!placeholder_halt
)
2646 /* Delete any HALTs immediately before the placeholder halt. */
2647 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2648 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2649 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2650 prev
->remove(last_bblock
);
2655 invalidate_live_intervals();
2661 fs_visitor::compute_to_mrf()
2663 bool progress
= false;
2666 /* No MRFs on Gen >= 7. */
2670 calculate_live_intervals();
2672 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2676 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2677 inst
->is_partial_write() ||
2678 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2679 inst
->dst
.type
!= inst
->src
[0].type
||
2680 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2681 !inst
->src
[0].is_contiguous() ||
2682 inst
->src
[0].subreg_offset
)
2685 /* Work out which hardware MRF registers are written by this
2688 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2690 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2691 mrf_high
= mrf_low
+ 4;
2692 } else if (inst
->exec_size
== 16) {
2693 mrf_high
= mrf_low
+ 1;
2698 /* Can't compute-to-MRF this GRF if someone else was going to
2701 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2704 /* Found a move of a GRF to a MRF. Let's see if we can go
2705 * rewrite the thing that made this GRF to write into the MRF.
2707 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2708 if (scan_inst
->dst
.file
== GRF
&&
2709 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2710 /* Found the last thing to write our reg we want to turn
2711 * into a compute-to-MRF.
2714 /* If this one instruction didn't populate all the
2715 * channels, bail. We might be able to rewrite everything
2716 * that writes that reg, but it would require smarter
2717 * tracking to delay the rewriting until complete success.
2719 if (scan_inst
->is_partial_write())
2722 /* Things returning more than one register would need us to
2723 * understand coalescing out more than one MOV at a time.
2725 if (scan_inst
->regs_written
> scan_inst
->dst
.width
/ 8)
2728 /* SEND instructions can't have MRF as a destination. */
2729 if (scan_inst
->mlen
)
2732 if (brw
->gen
== 6) {
2733 /* gen6 math instructions must have the destination be
2734 * GRF, so no compute-to-MRF for them.
2736 if (scan_inst
->is_math()) {
2741 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2742 /* Found the creator of our MRF's source value. */
2743 scan_inst
->dst
.file
= MRF
;
2744 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2745 scan_inst
->saturate
|= inst
->saturate
;
2746 inst
->remove(block
);
2752 /* We don't handle control flow here. Most computation of
2753 * values that end up in MRFs are shortly before the MRF
2756 if (block
->start() == scan_inst
)
2759 /* You can't read from an MRF, so if someone else reads our
2760 * MRF's source GRF that we wanted to rewrite, that stops us.
2762 bool interfered
= false;
2763 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2764 if (scan_inst
->src
[i
].file
== GRF
&&
2765 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2766 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2773 if (scan_inst
->dst
.file
== MRF
) {
2774 /* If somebody else writes our MRF here, we can't
2775 * compute-to-MRF before that.
2777 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2780 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2781 scan_mrf_high
= scan_mrf_low
+ 4;
2782 } else if (scan_inst
->exec_size
== 16) {
2783 scan_mrf_high
= scan_mrf_low
+ 1;
2785 scan_mrf_high
= scan_mrf_low
;
2788 if (mrf_low
== scan_mrf_low
||
2789 mrf_low
== scan_mrf_high
||
2790 mrf_high
== scan_mrf_low
||
2791 mrf_high
== scan_mrf_high
) {
2796 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2797 /* Found a SEND instruction, which means that there are
2798 * live values in MRFs from base_mrf to base_mrf +
2799 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2802 if (mrf_low
>= scan_inst
->base_mrf
&&
2803 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2806 if (mrf_high
>= scan_inst
->base_mrf
&&
2807 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2815 invalidate_live_intervals();
2821 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2822 * instructions to FS_OPCODE_REP_FB_WRITE.
2825 fs_visitor::emit_repclear_shader()
2827 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2829 int color_mrf
= base_mrf
+ 2;
2831 fs_inst
*mov
= emit(MOV(vec4(brw_message_reg(color_mrf
)),
2832 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
)));
2833 mov
->force_writemask_all
= true;
2836 if (key
->nr_color_regions
== 1) {
2837 write
= emit(FS_OPCODE_REP_FB_WRITE
);
2838 write
->saturate
= key
->clamp_fragment_color
;
2839 write
->base_mrf
= color_mrf
;
2841 write
->header_present
= false;
2844 assume(key
->nr_color_regions
> 0);
2845 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2846 write
= emit(FS_OPCODE_REP_FB_WRITE
);
2847 write
->saturate
= key
->clamp_fragment_color
;
2848 write
->base_mrf
= base_mrf
;
2850 write
->header_present
= true;
2858 assign_constant_locations();
2859 assign_curb_setup();
2861 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2862 assert(mov
->src
[0].file
== HW_REG
);
2863 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].fixed_hw_reg
.nr
, 0);
2867 * Walks through basic blocks, looking for repeated MRF writes and
2868 * removing the later ones.
2871 fs_visitor::remove_duplicate_mrf_writes()
2873 fs_inst
*last_mrf_move
[16];
2874 bool progress
= false;
2876 /* Need to update the MRF tracking for compressed instructions. */
2877 if (dispatch_width
== 16)
2880 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2882 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2883 if (inst
->is_control_flow()) {
2884 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2887 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2888 inst
->dst
.file
== MRF
) {
2889 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2890 if (prev_inst
&& inst
->equals(prev_inst
)) {
2891 inst
->remove(block
);
2897 /* Clear out the last-write records for MRFs that were overwritten. */
2898 if (inst
->dst
.file
== MRF
) {
2899 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2902 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2903 /* Found a SEND instruction, which will include two or fewer
2904 * implied MRF writes. We could do better here.
2906 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2907 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2911 /* Clear out any MRF move records whose sources got overwritten. */
2912 if (inst
->dst
.file
== GRF
) {
2913 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2914 if (last_mrf_move
[i
] &&
2915 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2916 last_mrf_move
[i
] = NULL
;
2921 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2922 inst
->dst
.file
== MRF
&&
2923 inst
->src
[0].file
== GRF
&&
2924 !inst
->is_partial_write()) {
2925 last_mrf_move
[inst
->dst
.reg
] = inst
;
2930 invalidate_live_intervals();
2936 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2938 /* Clear the flag for registers that actually got read (as expected). */
2939 for (int i
= 0; i
< inst
->sources
; i
++) {
2941 if (inst
->src
[i
].file
== GRF
) {
2942 grf
= inst
->src
[i
].reg
;
2943 } else if (inst
->src
[i
].file
== HW_REG
&&
2944 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2945 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2950 if (grf
>= first_grf
&&
2951 grf
< first_grf
+ grf_len
) {
2952 deps
[grf
- first_grf
] = false;
2953 if (inst
->exec_size
== 16)
2954 deps
[grf
- first_grf
+ 1] = false;
2960 * Implements this workaround for the original 965:
2962 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2963 * check for post destination dependencies on this instruction, software
2964 * must ensure that there is no destination hazard for the case of ‘write
2965 * followed by a posted write’ shown in the following example.
2968 * 2. send r3.xy <rest of send instruction>
2971 * Due to no post-destination dependency check on the ‘send’, the above
2972 * code sequence could have two instructions (1 and 2) in flight at the
2973 * same time that both consider ‘r3’ as the target of their final writes.
2976 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2979 int write_len
= inst
->regs_written
;
2980 int first_write_grf
= inst
->dst
.reg
;
2981 bool needs_dep
[BRW_MAX_MRF
];
2982 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2984 memset(needs_dep
, false, sizeof(needs_dep
));
2985 memset(needs_dep
, true, write_len
);
2987 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2989 /* Walk backwards looking for writes to registers we're writing which
2990 * aren't read since being written. If we hit the start of the program,
2991 * we assume that there are no outstanding dependencies on entry to the
2994 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2995 /* If we hit control flow, assume that there *are* outstanding
2996 * dependencies, and force their cleanup before our instruction.
2998 if (block
->start() == scan_inst
) {
2999 for (int i
= 0; i
< write_len
; i
++) {
3001 inst
->insert_before(block
, DEP_RESOLVE_MOV(first_write_grf
+ i
));
3007 /* We insert our reads as late as possible on the assumption that any
3008 * instruction but a MOV that might have left us an outstanding
3009 * dependency has more latency than a MOV.
3011 if (scan_inst
->dst
.file
== GRF
) {
3012 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
3013 int reg
= scan_inst
->dst
.reg
+ i
;
3015 if (reg
>= first_write_grf
&&
3016 reg
< first_write_grf
+ write_len
&&
3017 needs_dep
[reg
- first_write_grf
]) {
3018 inst
->insert_before(block
, DEP_RESOLVE_MOV(reg
));
3019 needs_dep
[reg
- first_write_grf
] = false;
3020 if (scan_inst
->exec_size
== 16)
3021 needs_dep
[reg
- first_write_grf
+ 1] = false;
3026 /* Clear the flag for registers that actually got read (as expected). */
3027 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3029 /* Continue the loop only if we haven't resolved all the dependencies */
3031 for (i
= 0; i
< write_len
; i
++) {
3041 * Implements this workaround for the original 965:
3043 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3044 * used as a destination register until after it has been sourced by an
3045 * instruction with a different destination register.
3048 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3050 int write_len
= inst
->regs_written
;
3051 int first_write_grf
= inst
->dst
.reg
;
3052 bool needs_dep
[BRW_MAX_MRF
];
3053 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3055 memset(needs_dep
, false, sizeof(needs_dep
));
3056 memset(needs_dep
, true, write_len
);
3057 /* Walk forwards looking for writes to registers we're writing which aren't
3058 * read before being written.
3060 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
, block
) {
3061 /* If we hit control flow, force resolve all remaining dependencies. */
3062 if (block
->end() == scan_inst
) {
3063 for (int i
= 0; i
< write_len
; i
++) {
3065 scan_inst
->insert_before(block
,
3066 DEP_RESOLVE_MOV(first_write_grf
+ i
));
3071 /* Clear the flag for registers that actually got read (as expected). */
3072 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3074 /* We insert our reads as late as possible since they're reading the
3075 * result of a SEND, which has massive latency.
3077 if (scan_inst
->dst
.file
== GRF
&&
3078 scan_inst
->dst
.reg
>= first_write_grf
&&
3079 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
3080 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
3081 scan_inst
->insert_before(block
, DEP_RESOLVE_MOV(scan_inst
->dst
.reg
));
3082 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
3085 /* Continue the loop only if we haven't resolved all the dependencies */
3087 for (i
= 0; i
< write_len
; i
++) {
3097 fs_visitor::insert_gen4_send_dependency_workarounds()
3099 if (brw
->gen
!= 4 || brw
->is_g4x
)
3102 bool progress
= false;
3104 /* Note that we're done with register allocation, so GRF fs_regs always
3105 * have a .reg_offset of 0.
3108 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3109 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
3110 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3111 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3117 invalidate_live_intervals();
3121 * Turns the generic expression-style uniform pull constant load instruction
3122 * into a hardware-specific series of instructions for loading a pull
3125 * The expression style allows the CSE pass before this to optimize out
3126 * repeated loads from the same offset, and gives the pre-register-allocation
3127 * scheduling full flexibility, while the conversion to native instructions
3128 * allows the post-register-allocation scheduler the best information
3131 * Note that execution masking for setting up pull constant loads is special:
3132 * the channels that need to be written are unrelated to the current execution
3133 * mask, since a later instruction will use one of the result channels as a
3134 * source operand for all 8 or 16 of its channels.
3137 fs_visitor::lower_uniform_pull_constant_loads()
3139 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3140 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3143 if (brw
->gen
>= 7) {
3144 /* The offset arg before was a vec4-aligned byte offset. We need to
3145 * turn it into a dword offset.
3147 fs_reg const_offset_reg
= inst
->src
[1];
3148 assert(const_offset_reg
.file
== IMM
&&
3149 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3150 const_offset_reg
.fixed_hw_reg
.dw1
.ud
/= 4;
3151 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1));
3153 /* We have to use a message header on Skylake to get SIMD4x2 mode.
3154 * Reserve space for the register.
3156 if (brw
->gen
>= 9) {
3157 payload
.reg_offset
++;
3158 alloc
.sizes
[payload
.reg
] = 2;
3161 /* This is actually going to be a MOV, but since only the first dword
3162 * is accessed, we have a special opcode to do just that one. Note
3163 * that this needs to be an operation that will be considered a def
3164 * by live variable analysis, or register allocation will explode.
3166 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3167 8, payload
, const_offset_reg
);
3168 setup
->force_writemask_all
= true;
3170 setup
->ir
= inst
->ir
;
3171 setup
->annotation
= inst
->annotation
;
3172 inst
->insert_before(block
, setup
);
3174 /* Similarly, this will only populate the first 4 channels of the
3175 * result register (since we only use smear values from 0-3), but we
3176 * don't tell the optimizer.
3178 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3179 inst
->src
[1] = payload
;
3181 invalidate_live_intervals();
3183 /* Before register allocation, we didn't tell the scheduler about the
3184 * MRF we use. We know it's safe to use this MRF because nothing
3185 * else does except for register spill/unspill, which generates and
3186 * uses its MRF within a single IR instruction.
3188 inst
->base_mrf
= 14;
3195 fs_visitor::lower_load_payload()
3197 bool progress
= false;
3199 int vgrf_to_reg
[alloc
.count
];
3201 for (unsigned i
= 0; i
< alloc
.count
; ++i
) {
3202 vgrf_to_reg
[i
] = reg_count
;
3203 reg_count
+= alloc
.sizes
[i
];
3207 bool written
:1; /* Whether this register has ever been written */
3208 bool force_writemask_all
:1;
3209 bool force_sechalf
:1;
3210 } metadata
[reg_count
];
3211 memset(metadata
, 0, sizeof(metadata
));
3213 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3214 if (inst
->dst
.file
== GRF
) {
3215 const int dst_reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
3216 bool force_sechalf
= inst
->force_sechalf
&&
3217 !inst
->force_writemask_all
;
3218 bool toggle_sechalf
= inst
->dst
.width
== 16 &&
3219 type_sz(inst
->dst
.type
) == 4 &&
3220 !inst
->force_writemask_all
;
3221 for (int i
= 0; i
< inst
->regs_written
; ++i
) {
3222 metadata
[dst_reg
+ i
].written
= true;
3223 metadata
[dst_reg
+ i
].force_sechalf
= force_sechalf
;
3224 metadata
[dst_reg
+ i
].force_writemask_all
= inst
->force_writemask_all
;
3225 force_sechalf
= (toggle_sechalf
!= force_sechalf
);
3229 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
3230 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== GRF
);
3231 fs_reg dst
= inst
->dst
;
3233 for (int i
= 0; i
< inst
->sources
; i
++) {
3234 dst
.width
= inst
->src
[i
].effective_width
;
3235 dst
.type
= inst
->src
[i
].type
;
3237 if (inst
->src
[i
].file
== BAD_FILE
) {
3238 /* Do nothing but otherwise increment as normal */
3239 } else if (dst
.file
== MRF
&&
3242 i
+ 4 < inst
->sources
&&
3243 inst
->src
[i
+ 4].equals(horiz_offset(inst
->src
[i
], 8))) {
3244 fs_reg compr4_dst
= dst
;
3245 compr4_dst
.reg
+= BRW_MRF_COMPR4
;
3246 compr4_dst
.width
= 16;
3247 fs_reg compr4_src
= inst
->src
[i
];
3248 compr4_src
.width
= 16;
3249 fs_inst
*mov
= MOV(compr4_dst
, compr4_src
);
3250 mov
->force_writemask_all
= true;
3251 inst
->insert_before(block
, mov
);
3252 /* Mark i+4 as BAD_FILE so we don't emit a MOV for it */
3253 inst
->src
[i
+ 4].file
= BAD_FILE
;
3255 fs_inst
*mov
= MOV(dst
, inst
->src
[i
]);
3256 if (inst
->src
[i
].file
== GRF
) {
3257 int src_reg
= vgrf_to_reg
[inst
->src
[i
].reg
] +
3258 inst
->src
[i
].reg_offset
;
3259 mov
->force_sechalf
= metadata
[src_reg
].force_sechalf
;
3260 mov
->force_writemask_all
= metadata
[src_reg
].force_writemask_all
;
3262 /* We don't have any useful metadata for immediates or
3263 * uniforms. Assume that any of the channels of the
3264 * destination may be used.
3266 assert(inst
->src
[i
].file
== IMM
||
3267 inst
->src
[i
].file
== UNIFORM
);
3268 mov
->force_writemask_all
= true;
3271 if (dst
.file
== GRF
) {
3272 const int dst_reg
= vgrf_to_reg
[dst
.reg
] + dst
.reg_offset
;
3273 const bool force_writemask
= mov
->force_writemask_all
;
3274 metadata
[dst_reg
].force_writemask_all
= force_writemask
;
3275 metadata
[dst_reg
].force_sechalf
= mov
->force_sechalf
;
3276 if (dst
.width
* type_sz(dst
.type
) > 32) {
3277 assert(!mov
->force_sechalf
);
3278 metadata
[dst_reg
+ 1].force_writemask_all
= force_writemask
;
3279 metadata
[dst_reg
+ 1].force_sechalf
= !force_writemask
;
3283 inst
->insert_before(block
, mov
);
3286 dst
= offset(dst
, 1);
3289 inst
->remove(block
);
3295 invalidate_live_intervals();
3301 fs_visitor::dump_instructions()
3303 dump_instructions(NULL
);
3307 fs_visitor::dump_instructions(const char *name
)
3309 FILE *file
= stderr
;
3310 if (name
&& geteuid() != 0) {
3311 file
= fopen(name
, "w");
3317 calculate_register_pressure();
3318 int ip
= 0, max_pressure
= 0;
3319 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
3320 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
3321 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
3322 dump_instruction(inst
, file
);
3325 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
3328 foreach_in_list(backend_instruction
, inst
, &instructions
) {
3329 fprintf(file
, "%4d: ", ip
++);
3330 dump_instruction(inst
, file
);
3334 if (file
!= stderr
) {
3340 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
3342 dump_instruction(be_inst
, stderr
);
3346 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
3348 fs_inst
*inst
= (fs_inst
*)be_inst
;
3350 if (inst
->predicate
) {
3351 fprintf(file
, "(%cf0.%d) ",
3352 inst
->predicate_inverse
? '-' : '+',
3356 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
3358 fprintf(file
, ".sat");
3359 if (inst
->conditional_mod
) {
3360 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
3361 if (!inst
->predicate
&&
3362 (brw
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
3363 inst
->opcode
!= BRW_OPCODE_IF
&&
3364 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
3365 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
3368 fprintf(file
, "(%d) ", inst
->exec_size
);
3371 switch (inst
->dst
.file
) {
3373 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
3374 if (inst
->dst
.width
!= dispatch_width
)
3375 fprintf(file
, "@%d", inst
->dst
.width
);
3376 if (alloc
.sizes
[inst
->dst
.reg
] != inst
->dst
.width
/ 8 ||
3377 inst
->dst
.subreg_offset
)
3378 fprintf(file
, "+%d.%d",
3379 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
3382 fprintf(file
, "m%d", inst
->dst
.reg
);
3385 fprintf(file
, "(null)");
3388 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
3391 fprintf(file
, "***attr%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
3394 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3395 switch (inst
->dst
.fixed_hw_reg
.nr
) {
3397 fprintf(file
, "null");
3399 case BRW_ARF_ADDRESS
:
3400 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
3402 case BRW_ARF_ACCUMULATOR
:
3403 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
3406 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3407 inst
->dst
.fixed_hw_reg
.subnr
);
3410 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3411 inst
->dst
.fixed_hw_reg
.subnr
);
3415 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
3417 if (inst
->dst
.fixed_hw_reg
.subnr
)
3418 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
3421 fprintf(file
, "???");
3424 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
3426 for (int i
= 0; i
< inst
->sources
; i
++) {
3427 if (inst
->src
[i
].negate
)
3429 if (inst
->src
[i
].abs
)
3431 switch (inst
->src
[i
].file
) {
3433 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
3434 if (inst
->src
[i
].width
!= dispatch_width
)
3435 fprintf(file
, "@%d", inst
->src
[i
].width
);
3436 if (alloc
.sizes
[inst
->src
[i
].reg
] != inst
->src
[i
].width
/ 8 ||
3437 inst
->src
[i
].subreg_offset
)
3438 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
3439 inst
->src
[i
].subreg_offset
);
3442 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
3445 fprintf(file
, "attr%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
3448 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
3449 if (inst
->src
[i
].reladdr
) {
3450 fprintf(file
, "+reladdr");
3451 } else if (inst
->src
[i
].subreg_offset
) {
3452 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
3453 inst
->src
[i
].subreg_offset
);
3457 fprintf(file
, "(null)");
3460 switch (inst
->src
[i
].type
) {
3461 case BRW_REGISTER_TYPE_F
:
3462 fprintf(file
, "%ff", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
3464 case BRW_REGISTER_TYPE_W
:
3465 case BRW_REGISTER_TYPE_D
:
3466 fprintf(file
, "%dd", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
3468 case BRW_REGISTER_TYPE_UW
:
3469 case BRW_REGISTER_TYPE_UD
:
3470 fprintf(file
, "%uu", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
3472 case BRW_REGISTER_TYPE_VF
:
3473 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
3474 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
3475 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
3476 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
3477 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
3480 fprintf(file
, "???");
3485 if (inst
->src
[i
].fixed_hw_reg
.negate
)
3487 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3489 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3490 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
3492 fprintf(file
, "null");
3494 case BRW_ARF_ADDRESS
:
3495 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3497 case BRW_ARF_ACCUMULATOR
:
3498 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3501 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3502 inst
->src
[i
].fixed_hw_reg
.subnr
);
3505 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3506 inst
->src
[i
].fixed_hw_reg
.subnr
);
3510 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
3512 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
3513 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3514 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3518 fprintf(file
, "???");
3521 if (inst
->src
[i
].abs
)
3524 if (inst
->src
[i
].file
!= IMM
) {
3525 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
3528 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
3529 fprintf(file
, ", ");
3534 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
3535 if (inst
->force_sechalf
)
3536 fprintf(file
, "2ndhalf ");
3538 fprintf(file
, "1sthalf ");
3541 fprintf(file
, "\n");
3545 * Possibly returns an instruction that set up @param reg.
3547 * Sometimes we want to take the result of some expression/variable
3548 * dereference tree and rewrite the instruction generating the result
3549 * of the tree. When processing the tree, we know that the
3550 * instructions generated are all writing temporaries that are dead
3551 * outside of this tree. So, if we have some instructions that write
3552 * a temporary, we're free to point that temp write somewhere else.
3554 * Note that this doesn't guarantee that the instruction generated
3555 * only reg -- it might be the size=4 destination of a texture instruction.
3558 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
3563 end
->is_partial_write() ||
3565 !reg
.equals(end
->dst
)) {
3573 fs_visitor::setup_payload_gen6()
3576 (prog
->InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
3577 unsigned barycentric_interp_modes
=
3578 (stage
== MESA_SHADER_FRAGMENT
) ?
3579 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
3581 assert(brw
->gen
>= 6);
3583 /* R0-1: masks, pixel X/Y coordinates. */
3584 payload
.num_regs
= 2;
3585 /* R2: only for 32-pixel dispatch.*/
3587 /* R3-26: barycentric interpolation coordinates. These appear in the
3588 * same order that they appear in the brw_wm_barycentric_interp_mode
3589 * enum. Each set of coordinates occupies 2 registers if dispatch width
3590 * == 8 and 4 registers if dispatch width == 16. Coordinates only
3591 * appear if they were enabled using the "Barycentric Interpolation
3592 * Mode" bits in WM_STATE.
3594 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
3595 if (barycentric_interp_modes
& (1 << i
)) {
3596 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
3597 payload
.num_regs
+= 2;
3598 if (dispatch_width
== 16) {
3599 payload
.num_regs
+= 2;
3604 /* R27: interpolated depth if uses source depth */
3606 payload
.source_depth_reg
= payload
.num_regs
;
3608 if (dispatch_width
== 16) {
3609 /* R28: interpolated depth if not SIMD8. */
3613 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
3615 payload
.source_w_reg
= payload
.num_regs
;
3617 if (dispatch_width
== 16) {
3618 /* R30: interpolated W if not SIMD8. */
3623 if (stage
== MESA_SHADER_FRAGMENT
) {
3624 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3625 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3626 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
3627 /* R31: MSAA position offsets. */
3628 if (prog_data
->uses_pos_offset
) {
3629 payload
.sample_pos_reg
= payload
.num_regs
;
3634 /* R32: MSAA input coverage mask */
3635 if (prog
->SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
3636 assert(brw
->gen
>= 7);
3637 payload
.sample_mask_in_reg
= payload
.num_regs
;
3639 if (dispatch_width
== 16) {
3640 /* R33: input coverage mask if not SIMD8. */
3645 /* R34-: bary for 32-pixel. */
3646 /* R58-59: interp W for 32-pixel. */
3648 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3649 source_depth_to_render_target
= true;
3654 fs_visitor::setup_vs_payload()
3656 /* R0: thread header, R1: urb handles */
3657 payload
.num_regs
= 2;
3661 fs_visitor::assign_binding_table_offsets()
3663 assert(stage
== MESA_SHADER_FRAGMENT
);
3664 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3665 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3666 uint32_t next_binding_table_offset
= 0;
3668 /* If there are no color regions, we still perform an FB write to a null
3669 * renderbuffer, which we place at surface index 0.
3671 prog_data
->binding_table
.render_target_start
= next_binding_table_offset
;
3672 next_binding_table_offset
+= MAX2(key
->nr_color_regions
, 1);
3674 assign_common_binding_table_offsets(next_binding_table_offset
);
3678 fs_visitor::calculate_register_pressure()
3680 invalidate_live_intervals();
3681 calculate_live_intervals();
3683 unsigned num_instructions
= 0;
3684 foreach_block(block
, cfg
)
3685 num_instructions
+= block
->instructions
.length();
3687 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
3689 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
3690 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
3691 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
3696 fs_visitor::optimize()
3698 const char *stage_name
= stage
== MESA_SHADER_VERTEX
? "vs" : "fs";
3700 split_virtual_grfs();
3702 move_uniform_array_access_to_pull_constants();
3703 assign_constant_locations();
3704 demote_pull_constants();
3706 #define OPT(pass, args...) ({ \
3708 bool this_progress = pass(args); \
3710 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
3711 char filename[64]; \
3712 snprintf(filename, 64, "%s%d-%04d-%02d-%02d-" #pass, \
3713 stage_name, dispatch_width, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
3715 backend_visitor::dump_instructions(filename); \
3718 progress = progress || this_progress; \
3722 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
3724 snprintf(filename
, 64, "%s%d-%04d-00-start",
3725 stage_name
, dispatch_width
, shader_prog
? shader_prog
->Name
: 0);
3727 backend_visitor::dump_instructions(filename
);
3738 OPT(remove_duplicate_mrf_writes
);
3742 OPT(opt_copy_propagate
);
3743 OPT(opt_peephole_predicated_break
);
3744 OPT(opt_cmod_propagation
);
3745 OPT(dead_code_eliminate
);
3746 OPT(opt_peephole_sel
);
3747 OPT(dead_control_flow_eliminate
, this);
3748 OPT(opt_register_renaming
);
3749 OPT(opt_redundant_discard_jumps
);
3750 OPT(opt_saturate_propagation
);
3751 OPT(register_coalesce
);
3752 OPT(compute_to_mrf
);
3754 OPT(compact_virtual_grfs
);
3759 if (OPT(lower_load_payload
)) {
3760 split_virtual_grfs();
3761 OPT(register_coalesce
);
3762 OPT(compute_to_mrf
);
3763 OPT(dead_code_eliminate
);
3766 OPT(opt_combine_constants
);
3768 lower_uniform_pull_constant_loads();
3772 * Three source instruction must have a GRF/MRF destination register.
3773 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
3776 fs_visitor::fixup_3src_null_dest()
3778 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3779 if (inst
->is_3src() && inst
->dst
.is_null()) {
3780 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
3787 fs_visitor::allocate_registers()
3789 bool allocated_without_spills
;
3791 static const enum instruction_scheduler_mode pre_modes
[] = {
3793 SCHEDULE_PRE_NON_LIFO
,
3797 /* Try each scheduling heuristic to see if it can successfully register
3798 * allocate without spilling. They should be ordered by decreasing
3799 * performance but increasing likelihood of allocating.
3801 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
3802 schedule_instructions(pre_modes
[i
]);
3805 assign_regs_trivial();
3806 allocated_without_spills
= true;
3808 allocated_without_spills
= assign_regs(false);
3810 if (allocated_without_spills
)
3814 if (!allocated_without_spills
) {
3815 const char *stage_name
= stage
== MESA_SHADER_VERTEX
?
3816 "Vertex" : "Fragment";
3818 /* We assume that any spilling is worse than just dropping back to
3819 * SIMD8. There's probably actually some intermediate point where
3820 * SIMD16 with a couple of spills is still better.
3822 if (dispatch_width
== 16) {
3823 fail("Failure to register allocate. Reduce number of "
3824 "live scalar values to avoid this.");
3826 perf_debug("%s shader triggered register spilling. "
3827 "Try reducing the number of live scalar values to "
3828 "improve performance.\n", stage_name
);
3831 /* Since we're out of heuristics, just go spill registers until we
3832 * get an allocation.
3834 while (!assign_regs(true)) {
3840 /* This must come after all optimization and register allocation, since
3841 * it inserts dead code that happens to have side effects, and it does
3842 * so based on the actual physical registers in use.
3844 insert_gen4_send_dependency_workarounds();
3849 if (!allocated_without_spills
)
3850 schedule_instructions(SCHEDULE_POST
);
3852 if (last_scratch
> 0)
3853 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
3857 env_var_as_boolean(const char *var_name
, bool default_value
)
3859 const char *str
= getenv(var_name
);
3861 return default_value
;
3863 if (strcmp(str
, "1") == 0 ||
3864 strcasecmp(str
, "true") == 0 ||
3865 strcasecmp(str
, "yes") == 0) {
3867 } else if (strcmp(str
, "0") == 0 ||
3868 strcasecmp(str
, "false") == 0 ||
3869 strcasecmp(str
, "no") == 0) {
3872 return default_value
;
3877 fs_visitor::run_vs()
3879 assert(stage
== MESA_SHADER_VERTEX
);
3881 assign_common_binding_table_offsets(0);
3884 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3885 emit_shader_time_begin();
3887 if (env_var_as_boolean("INTEL_USE_NIR", false)) {
3890 foreach_in_list(ir_instruction
, ir
, shader
->base
.ir
) {
3892 this->result
= reg_undef
;
3907 assign_curb_setup();
3908 assign_vs_urb_setup();
3910 fixup_3src_null_dest();
3911 allocate_registers();
3917 fs_visitor::run_fs()
3919 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3920 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
3922 assert(stage
== MESA_SHADER_FRAGMENT
);
3924 sanity_param_count
= prog
->Parameters
->NumParameters
;
3926 assign_binding_table_offsets();
3929 setup_payload_gen6();
3931 setup_payload_gen4();
3935 } else if (brw
->use_rep_send
&& dispatch_width
== 16) {
3936 emit_repclear_shader();
3938 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3939 emit_shader_time_begin();
3941 calculate_urb_setup();
3942 if (prog
->InputsRead
> 0) {
3944 emit_interpolation_setup_gen4();
3946 emit_interpolation_setup_gen6();
3949 /* We handle discards by keeping track of the still-live pixels in f0.1.
3950 * Initialize it with the dispatched pixels.
3952 if (wm_prog_data
->uses_kill
) {
3953 fs_inst
*discard_init
= emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
3954 discard_init
->flag_subreg
= 1;
3957 /* Generate FS IR for main(). (the visitor only descends into
3958 * functions called "main").
3961 if (env_var_as_boolean("INTEL_USE_NIR", false)) {
3964 foreach_in_list(ir_instruction
, ir
, shader
->base
.ir
) {
3966 this->result
= reg_undef
;
3971 emit_fragment_program_code();
3977 emit(FS_OPCODE_PLACEHOLDER_HALT
);
3979 if (wm_key
->alpha_test_func
)
3984 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3985 emit_shader_time_end();
3991 assign_curb_setup();
3994 fixup_3src_null_dest();
3995 allocate_registers();
4001 if (dispatch_width
== 8)
4002 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
4004 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
4006 /* If any state parameters were appended, then ParameterValues could have
4007 * been realloced, in which case the driver uniform storage set up by
4008 * _mesa_associate_uniform_storage() would point to freed memory. Make
4009 * sure that didn't happen.
4011 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
4017 brw_wm_fs_emit(struct brw_context
*brw
,
4019 const struct brw_wm_prog_key
*key
,
4020 struct brw_wm_prog_data
*prog_data
,
4021 struct gl_fragment_program
*fp
,
4022 struct gl_shader_program
*prog
,
4023 unsigned *final_assembly_size
)
4025 bool start_busy
= false;
4026 double start_time
= 0;
4028 if (unlikely(brw
->perf_debug
)) {
4029 start_busy
= (brw
->batch
.last_bo
&&
4030 drm_intel_bo_busy(brw
->batch
.last_bo
));
4031 start_time
= get_time();
4034 struct brw_shader
*shader
= NULL
;
4036 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
4038 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
4039 brw_dump_ir("fragment", prog
, &shader
->base
, &fp
->Base
);
4041 /* Now the main event: Visit the shader IR and generate our FS IR for it.
4043 fs_visitor
v(brw
, mem_ctx
, key
, prog_data
, prog
, fp
, 8);
4046 prog
->LinkStatus
= false;
4047 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
4050 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
4056 cfg_t
*simd16_cfg
= NULL
;
4057 fs_visitor
v2(brw
, mem_ctx
, key
, prog_data
, prog
, fp
, 16);
4058 if (brw
->gen
>= 5 && likely(!(INTEL_DEBUG
& DEBUG_NO16
) ||
4059 brw
->use_rep_send
)) {
4060 if (!v
.simd16_unsupported
) {
4061 /* Try a SIMD16 compile */
4062 v2
.import_uniforms(&v
);
4064 perf_debug("SIMD16 shader failed to compile, falling back to "
4065 "SIMD8 at a 10-20%% performance cost: %s", v2
.fail_msg
);
4067 simd16_cfg
= v2
.cfg
;
4070 perf_debug("SIMD16 shader unsupported, falling back to "
4071 "SIMD8 at a 10-20%% performance cost: %s", v
.no16_msg
);
4076 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || brw
->no_simd8
;
4077 if (no_simd8
&& simd16_cfg
) {
4079 prog_data
->no_8
= true;
4082 prog_data
->no_8
= false;
4085 fs_generator
g(brw
, mem_ctx
, (void *) key
, &prog_data
->base
,
4086 &fp
->Base
, v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
4088 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
4091 name
= ralloc_asprintf(mem_ctx
, "%s fragment shader %d",
4092 prog
->Label
? prog
->Label
: "unnamed",
4095 name
= ralloc_asprintf(mem_ctx
, "fragment program %d", fp
->Base
.Id
);
4097 g
.enable_debug(name
);
4101 g
.generate_code(simd8_cfg
, 8);
4103 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
4105 if (unlikely(brw
->perf_debug
) && shader
) {
4106 if (shader
->compiled_once
)
4107 brw_wm_debug_recompile(brw
, prog
, key
);
4108 shader
->compiled_once
= true;
4110 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
4111 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
4112 (get_time() - start_time
) * 1000);
4116 return g
.get_assembly(final_assembly_size
);
4120 brw_fs_precompile(struct gl_context
*ctx
,
4121 struct gl_shader_program
*shader_prog
,
4122 struct gl_program
*prog
)
4124 struct brw_context
*brw
= brw_context(ctx
);
4125 struct brw_wm_prog_key key
;
4127 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*) prog
;
4128 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
4129 bool program_uses_dfdy
= fp
->UsesDFdy
;
4131 memset(&key
, 0, sizeof(key
));
4135 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
4137 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
4138 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
4140 /* Just assume depth testing. */
4141 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
4142 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
4145 if (brw
->gen
< 6 || _mesa_bitcount_64(fp
->Base
.InputsRead
&
4146 BRW_FS_VARYING_INPUT_MASK
) > 16)
4147 key
.input_slots_valid
= fp
->Base
.InputsRead
| VARYING_BIT_POS
;
4149 const bool has_shader_channel_select
= brw
->is_haswell
|| brw
->gen
>= 8;
4150 unsigned sampler_count
= _mesa_fls(fp
->Base
.SamplersUsed
);
4151 for (unsigned i
= 0; i
< sampler_count
; i
++) {
4152 if (!has_shader_channel_select
&& (fp
->Base
.ShadowSamplers
& (1 << i
))) {
4153 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
4154 key
.tex
.swizzles
[i
] =
4155 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
4157 /* Color sampler: assume no swizzling. */
4158 key
.tex
.swizzles
[i
] = SWIZZLE_XYZW
;
4162 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
) {
4163 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
4166 key
.nr_color_regions
= _mesa_bitcount_64(fp
->Base
.OutputsWritten
&
4167 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
4168 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
)));
4170 if ((fp
->Base
.InputsRead
& VARYING_BIT_POS
) || program_uses_dfdy
) {
4171 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
) ||
4172 key
.nr_color_regions
> 1;
4175 key
.program_string_id
= bfp
->id
;
4177 uint32_t old_prog_offset
= brw
->wm
.base
.prog_offset
;
4178 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
4180 bool success
= do_wm_prog(brw
, shader_prog
, bfp
, &key
);
4182 brw
->wm
.base
.prog_offset
= old_prog_offset
;
4183 brw
->wm
.prog_data
= old_prog_data
;