projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
i965: Split the gen4 and gen5 sampler handling apart.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 extern "C" {
29
30 #include <sys/types.h>
31
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
42 #include "brw_eu.h"
43 #include "brw_wm.h"
44 #include "talloc.h"
45 }
46 #include "../glsl/glsl_types.h"
47 #include "../glsl/ir_optimization.h"
48 #include "../glsl/ir_print_visitor.h"
49
50 enum register_file {
51 ARF = BRW_ARCHITECTURE_REGISTER_FILE,
52 GRF = BRW_GENERAL_REGISTER_FILE,
53 MRF = BRW_MESSAGE_REGISTER_FILE,
54 IMM = BRW_IMMEDIATE_VALUE,
55 FIXED_HW_REG, /* a struct brw_reg */
56 UNIFORM, /* prog_data->params[hw_reg] */
57 BAD_FILE
58 };
59
60 enum fs_opcodes {
61 FS_OPCODE_FB_WRITE = 256,
62 FS_OPCODE_RCP,
63 FS_OPCODE_RSQ,
64 FS_OPCODE_SQRT,
65 FS_OPCODE_EXP2,
66 FS_OPCODE_LOG2,
67 FS_OPCODE_POW,
68 FS_OPCODE_SIN,
69 FS_OPCODE_COS,
70 FS_OPCODE_DDX,
71 FS_OPCODE_DDY,
72 FS_OPCODE_LINTERP,
73 FS_OPCODE_TEX,
74 FS_OPCODE_TXB,
75 FS_OPCODE_TXL,
76 FS_OPCODE_DISCARD,
77 };
78
79 static int using_new_fs = -1;
80 static struct brw_reg brw_reg_from_fs_reg(class fs_reg *reg);
81
82 struct gl_shader *
83 brw_new_shader(GLcontext *ctx, GLuint name, GLuint type)
84 {
85 struct brw_shader *shader;
86
87 shader = talloc_zero(NULL, struct brw_shader);
88 if (shader) {
89 shader->base.Type = type;
90 shader->base.Name = name;
91 _mesa_init_shader(ctx, &shader->base);
92 }
93
94 return &shader->base;
95 }
96
97 struct gl_shader_program *
98 brw_new_shader_program(GLcontext *ctx, GLuint name)
99 {
100 struct brw_shader_program *prog;
101 prog = talloc_zero(NULL, struct brw_shader_program);
102 if (prog) {
103 prog->base.Name = name;
104 _mesa_init_shader_program(ctx, &prog->base);
105 }
106 return &prog->base;
107 }
108
109 GLboolean
110 brw_compile_shader(GLcontext *ctx, struct gl_shader *shader)
111 {
112 if (!_mesa_ir_compile_shader(ctx, shader))
113 return GL_FALSE;
114
115 return GL_TRUE;
116 }
117
118 GLboolean
119 brw_link_shader(GLcontext *ctx, struct gl_shader_program *prog)
120 {
121 if (using_new_fs == -1)
122 using_new_fs = getenv("INTEL_NEW_FS") != NULL;
123
124 for (unsigned i = 0; i < prog->_NumLinkedShaders; i++) {
125 struct brw_shader *shader = (struct brw_shader *)prog->_LinkedShaders[i];
126
127 if (using_new_fs && shader->base.Type == GL_FRAGMENT_SHADER) {
128 void *mem_ctx = talloc_new(NULL);
129 bool progress;
130
131 if (shader->ir)
132 talloc_free(shader->ir);
133 shader->ir = new(shader) exec_list;
134 clone_ir_list(mem_ctx, shader->ir, shader->base.ir);
135
136 do_mat_op_to_vec(shader->ir);
137 do_mod_to_fract(shader->ir);
138 do_div_to_mul_rcp(shader->ir);
139 do_sub_to_add_neg(shader->ir);
140 do_explog_to_explog2(shader->ir);
141 do_lower_texture_projection(shader->ir);
142
143 do {
144 progress = false;
145
146 brw_do_channel_expressions(shader->ir);
147 brw_do_vector_splitting(shader->ir);
148
149 progress = do_lower_jumps(shader->ir, true, true,
150 true, /* main return */
151 false, /* continue */
152 false /* loops */
153 ) || progress;
154
155 progress = do_common_optimization(shader->ir, true, 32) || progress;
156
157 progress = lower_noise(shader->ir) || progress;
158 progress =
159 lower_variable_index_to_cond_assign(shader->ir,
160 GL_TRUE, /* input */
161 GL_TRUE, /* output */
162 GL_TRUE, /* temp */
163 GL_TRUE /* uniform */
164 ) || progress;
165 } while (progress);
166
167 validate_ir_tree(shader->ir);
168
169 reparent_ir(shader->ir, shader->ir);
170 talloc_free(mem_ctx);
171 }
172 }
173
174 if (!_mesa_ir_link_shader(ctx, prog))
175 return GL_FALSE;
176
177 return GL_TRUE;
178 }
179
180 static int
181 type_size(const struct glsl_type *type)
182 {
183 unsigned int size, i;
184
185 switch (type->base_type) {
186 case GLSL_TYPE_UINT:
187 case GLSL_TYPE_INT:
188 case GLSL_TYPE_FLOAT:
189 case GLSL_TYPE_BOOL:
190 return type->components();
191 case GLSL_TYPE_ARRAY:
192 return type_size(type->fields.array) * type->length;
193 case GLSL_TYPE_STRUCT:
194 size = 0;
195 for (i = 0; i < type->length; i++) {
196 size += type_size(type->fields.structure[i].type);
197 }
198 return size;
199 case GLSL_TYPE_SAMPLER:
200 /* Samplers take up no register space, since they're baked in at
201 * link time.
202 */
203 return 0;
204 default:
205 assert(!"not reached");
206 return 0;
207 }
208 }
209
210 class fs_reg {
211 public:
212 /* Callers of this talloc-based new need not call delete. It's
213 * easier to just talloc_free 'ctx' (or any of its ancestors). */
214 static void* operator new(size_t size, void *ctx)
215 {
216 void *node;
217
218 node = talloc_size(ctx, size);
219 assert(node != NULL);
220
221 return node;
222 }
223
224 void init()
225 {
226 this->reg = 0;
227 this->reg_offset = 0;
228 this->negate = 0;
229 this->abs = 0;
230 this->hw_reg = -1;
231 }
232
233 /** Generic unset register constructor. */
234 fs_reg()
235 {
236 init();
237 this->file = BAD_FILE;
238 }
239
240 /** Immediate value constructor. */
241 fs_reg(float f)
242 {
243 init();
244 this->file = IMM;
245 this->type = BRW_REGISTER_TYPE_F;
246 this->imm.f = f;
247 }
248
249 /** Immediate value constructor. */
250 fs_reg(int32_t i)
251 {
252 init();
253 this->file = IMM;
254 this->type = BRW_REGISTER_TYPE_D;
255 this->imm.i = i;
256 }
257
258 /** Immediate value constructor. */
259 fs_reg(uint32_t u)
260 {
261 init();
262 this->file = IMM;
263 this->type = BRW_REGISTER_TYPE_UD;
264 this->imm.u = u;
265 }
266
267 /** Fixed brw_reg Immediate value constructor. */
268 fs_reg(struct brw_reg fixed_hw_reg)
269 {
270 init();
271 this->file = FIXED_HW_REG;
272 this->fixed_hw_reg = fixed_hw_reg;
273 this->type = fixed_hw_reg.type;
274 }
275
276 fs_reg(enum register_file file, int hw_reg);
277 fs_reg(class fs_visitor *v, const struct glsl_type *type);
278
279 /** Register file: ARF, GRF, MRF, IMM. */
280 enum register_file file;
281 /** virtual register number. 0 = fixed hw reg */
282 int reg;
283 /** Offset within the virtual register. */
284 int reg_offset;
285 /** HW register number. Generally unset until register allocation. */
286 int hw_reg;
287 /** Register type. BRW_REGISTER_TYPE_* */
288 int type;
289 bool negate;
290 bool abs;
291 struct brw_reg fixed_hw_reg;
292
293 /** Value for file == BRW_IMMMEDIATE_FILE */
294 union {
295 int32_t i;
296 uint32_t u;
297 float f;
298 } imm;
299 };
300
301 static const fs_reg reg_undef;
302 static const fs_reg reg_null(ARF, BRW_ARF_NULL);
303
304 class fs_inst : public exec_node {
305 public:
306 /* Callers of this talloc-based new need not call delete. It's
307 * easier to just talloc_free 'ctx' (or any of its ancestors). */
308 static void* operator new(size_t size, void *ctx)
309 {
310 void *node;
311
312 node = talloc_zero_size(ctx, size);
313 assert(node != NULL);
314
315 return node;
316 }
317
318 void init()
319 {
320 this->opcode = BRW_OPCODE_NOP;
321 this->saturate = false;
322 this->conditional_mod = BRW_CONDITIONAL_NONE;
323 this->predicated = false;
324 this->sampler = 0;
325 this->target = 0;
326 this->eot = false;
327 this->shadow_compare = false;
328 }
329
330 fs_inst()
331 {
332 init();
333 }
334
335 fs_inst(int opcode)
336 {
337 init();
338 this->opcode = opcode;
339 }
340
341 fs_inst(int opcode, fs_reg dst, fs_reg src0)
342 {
343 init();
344 this->opcode = opcode;
345 this->dst = dst;
346 this->src[0] = src0;
347 }
348
349 fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1)
350 {
351 init();
352 this->opcode = opcode;
353 this->dst = dst;
354 this->src[0] = src0;
355 this->src[1] = src1;
356 }
357
358 fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2)
359 {
360 init();
361 this->opcode = opcode;
362 this->dst = dst;
363 this->src[0] = src0;
364 this->src[1] = src1;
365 this->src[2] = src2;
366 }
367
368 int opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
369 fs_reg dst;
370 fs_reg src[3];
371 bool saturate;
372 bool predicated;
373 int conditional_mod; /**< BRW_CONDITIONAL_* */
374
375 int mlen; /**< SEND message length */
376 int sampler;
377 int target; /**< MRT target. */
378 bool eot;
379 bool shadow_compare;
380
381 /** @{
382 * Annotation for the generated IR. One of the two can be set.
383 */
384 ir_instruction *ir;
385 const char *annotation;
386 /** @} */
387 };
388
389 class fs_visitor : public ir_visitor
390 {
391 public:
392
393 fs_visitor(struct brw_wm_compile *c, struct brw_shader *shader)
394 {
395 this->c = c;
396 this->p = &c->func;
397 this->brw = p->brw;
398 this->fp = brw->fragment_program;
399 this->intel = &brw->intel;
400 this->ctx = &intel->ctx;
401 this->mem_ctx = talloc_new(NULL);
402 this->shader = shader;
403 this->fail = false;
404 this->variable_ht = hash_table_ctor(0,
405 hash_table_pointer_hash,
406 hash_table_pointer_compare);
407
408 this->frag_color = NULL;
409 this->frag_data = NULL;
410 this->frag_depth = NULL;
411 this->first_non_payload_grf = 0;
412
413 this->current_annotation = NULL;
414 this->annotation_string = NULL;
415 this->annotation_ir = NULL;
416 this->base_ir = NULL;
417
418 this->virtual_grf_sizes = NULL;
419 this->virtual_grf_next = 1;
420 this->virtual_grf_array_size = 0;
421 this->virtual_grf_def = NULL;
422 this->virtual_grf_use = NULL;
423 }
424 ~fs_visitor()
425 {
426 talloc_free(this->mem_ctx);
427 hash_table_dtor(this->variable_ht);
428 }
429
430 fs_reg *variable_storage(ir_variable *var);
431 int virtual_grf_alloc(int size);
432
433 void visit(ir_variable *ir);
434 void visit(ir_assignment *ir);
435 void visit(ir_dereference_variable *ir);
436 void visit(ir_dereference_record *ir);
437 void visit(ir_dereference_array *ir);
438 void visit(ir_expression *ir);
439 void visit(ir_texture *ir);
440 void visit(ir_if *ir);
441 void visit(ir_constant *ir);
442 void visit(ir_swizzle *ir);
443 void visit(ir_return *ir);
444 void visit(ir_loop *ir);
445 void visit(ir_loop_jump *ir);
446 void visit(ir_discard *ir);
447 void visit(ir_call *ir);
448 void visit(ir_function *ir);
449 void visit(ir_function_signature *ir);
450
451 fs_inst *emit(fs_inst inst);
452 void assign_curb_setup();
453 void assign_urb_setup();
454 void assign_regs();
455 void assign_regs_trivial();
456 void calculate_live_intervals();
457 bool virtual_grf_interferes(int a, int b);
458 void generate_code();
459 void generate_fb_write(fs_inst *inst);
460 void generate_linterp(fs_inst *inst, struct brw_reg dst,
461 struct brw_reg *src);
462 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
463 void generate_math(fs_inst *inst, struct brw_reg dst, struct brw_reg *src);
464 void generate_discard(fs_inst *inst, struct brw_reg temp);
465 void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
466 void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
467
468 void emit_dummy_fs();
469 void emit_fragcoord_interpolation(ir_variable *ir);
470 void emit_general_interpolation(ir_variable *ir);
471 void emit_interpolation_setup();
472 fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, int base_mrf);
473 fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, int base_mrf);
474 void emit_fb_writes();
475 void emit_assignment_writes(fs_reg &l, fs_reg &r,
476 const glsl_type *type, bool predicated);
477
478 struct brw_reg interp_reg(int location, int channel);
479 int setup_uniform_values(int loc, const glsl_type *type);
480 void setup_builtin_uniform_values(ir_variable *ir);
481
482 struct brw_context *brw;
483 const struct gl_fragment_program *fp;
484 struct intel_context *intel;
485 GLcontext *ctx;
486 struct brw_wm_compile *c;
487 struct brw_compile *p;
488 struct brw_shader *shader;
489 void *mem_ctx;
490 exec_list instructions;
491
492 int *virtual_grf_sizes;
493 int virtual_grf_next;
494 int virtual_grf_array_size;
495 int *virtual_grf_def;
496 int *virtual_grf_use;
497
498 struct hash_table *variable_ht;
499 ir_variable *frag_color, *frag_data, *frag_depth;
500 int first_non_payload_grf;
501
502 /** @{ debug annotation info */
503 const char *current_annotation;
504 ir_instruction *base_ir;
505 const char **annotation_string;
506 ir_instruction **annotation_ir;
507 /** @} */
508
509 bool fail;
510
511 /* Result of last visit() method. */
512 fs_reg result;
513
514 fs_reg pixel_x;
515 fs_reg pixel_y;
516 fs_reg wpos_w;
517 fs_reg pixel_w;
518 fs_reg delta_x;
519 fs_reg delta_y;
520
521 int grf_used;
522
523 };
524
525 int
526 fs_visitor::virtual_grf_alloc(int size)
527 {
528 if (virtual_grf_array_size <= virtual_grf_next) {
529 if (virtual_grf_array_size == 0)
530 virtual_grf_array_size = 16;
531 else
532 virtual_grf_array_size *= 2;
533 virtual_grf_sizes = talloc_realloc(mem_ctx, virtual_grf_sizes,
534 int, virtual_grf_array_size);
535
536 /* This slot is always unused. */
537 virtual_grf_sizes[0] = 0;
538 }
539 virtual_grf_sizes[virtual_grf_next] = size;
540 return virtual_grf_next++;
541 }
542
543 /** Fixed HW reg constructor. */
544 fs_reg::fs_reg(enum register_file file, int hw_reg)
545 {
546 init();
547 this->file = file;
548 this->hw_reg = hw_reg;
549 this->type = BRW_REGISTER_TYPE_F;
550 }
551
552 int
553 brw_type_for_base_type(const struct glsl_type *type)
554 {
555 switch (type->base_type) {
556 case GLSL_TYPE_FLOAT:
557 return BRW_REGISTER_TYPE_F;
558 case GLSL_TYPE_INT:
559 case GLSL_TYPE_BOOL:
560 return BRW_REGISTER_TYPE_D;
561 case GLSL_TYPE_UINT:
562 return BRW_REGISTER_TYPE_UD;
563 case GLSL_TYPE_ARRAY:
564 case GLSL_TYPE_STRUCT:
565 /* These should be overridden with the type of the member when
566 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
567 * way to trip up if we don't.
568 */
569 return BRW_REGISTER_TYPE_UD;
570 default:
571 assert(!"not reached");
572 return BRW_REGISTER_TYPE_F;
573 }
574 }
575
576 /** Automatic reg constructor. */
577 fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type)
578 {
579 init();
580
581 this->file = GRF;
582 this->reg = v->virtual_grf_alloc(type_size(type));
583 this->reg_offset = 0;
584 this->type = brw_type_for_base_type(type);
585 }
586
587 fs_reg *
588 fs_visitor::variable_storage(ir_variable *var)
589 {
590 return (fs_reg *)hash_table_find(this->variable_ht, var);
591 }
592
593 /* Our support for uniforms is piggy-backed on the struct
594 * gl_fragment_program, because that's where the values actually
595 * get stored, rather than in some global gl_shader_program uniform
596 * store.
597 */
598 int
599 fs_visitor::setup_uniform_values(int loc, const glsl_type *type)
600 {
601 unsigned int offset = 0;
602 float *vec_values;
603
604 if (type->is_matrix()) {
605 const glsl_type *column = glsl_type::get_instance(GLSL_TYPE_FLOAT,
606 type->vector_elements,
607 1);
608
609 for (unsigned int i = 0; i < type->matrix_columns; i++) {
610 offset += setup_uniform_values(loc + offset, column);
611 }
612
613 return offset;
614 }
615
616 switch (type->base_type) {
617 case GLSL_TYPE_FLOAT:
618 case GLSL_TYPE_UINT:
619 case GLSL_TYPE_INT:
620 case GLSL_TYPE_BOOL:
621 vec_values = fp->Base.Parameters->ParameterValues[loc];
622 for (unsigned int i = 0; i < type->vector_elements; i++) {
623 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[i];
624 }
625 return 1;
626
627 case GLSL_TYPE_STRUCT:
628 for (unsigned int i = 0; i < type->length; i++) {
629 offset += setup_uniform_values(loc + offset,
630 type->fields.structure[i].type);
631 }
632 return offset;
633
634 case GLSL_TYPE_ARRAY:
635 for (unsigned int i = 0; i < type->length; i++) {
636 offset += setup_uniform_values(loc + offset, type->fields.array);
637 }
638 return offset;
639
640 case GLSL_TYPE_SAMPLER:
641 /* The sampler takes up a slot, but we don't use any values from it. */
642 return 1;
643
644 default:
645 assert(!"not reached");
646 return 0;
647 }
648 }
649
650
651 /* Our support for builtin uniforms is even scarier than non-builtin.
652 * It sits on top of the PROG_STATE_VAR parameters that are
653 * automatically updated from GL context state.
654 */
655 void
656 fs_visitor::setup_builtin_uniform_values(ir_variable *ir)
657 {
658 const struct gl_builtin_uniform_desc *statevar = NULL;
659
660 for (unsigned int i = 0; _mesa_builtin_uniform_desc[i].name; i++) {
661 statevar = &_mesa_builtin_uniform_desc[i];
662 if (strcmp(ir->name, _mesa_builtin_uniform_desc[i].name) == 0)
663 break;
664 }
665
666 if (!statevar->name) {
667 this->fail = true;
668 printf("Failed to find builtin uniform `%s'\n", ir->name);
669 return;
670 }
671
672 int array_count;
673 if (ir->type->is_array()) {
674 array_count = ir->type->length;
675 } else {
676 array_count = 1;
677 }
678
679 for (int a = 0; a < array_count; a++) {
680 for (unsigned int i = 0; i < statevar->num_elements; i++) {
681 struct gl_builtin_uniform_element *element = &statevar->elements[i];
682 int tokens[STATE_LENGTH];
683
684 memcpy(tokens, element->tokens, sizeof(element->tokens));
685 if (ir->type->is_array()) {
686 tokens[1] = a;
687 }
688
689 /* This state reference has already been setup by ir_to_mesa,
690 * but we'll get the same index back here.
691 */
692 int index = _mesa_add_state_reference(this->fp->Base.Parameters,
693 (gl_state_index *)tokens);
694 float *vec_values = this->fp->Base.Parameters->ParameterValues[index];
695
696 /* Add each of the unique swizzles of the element as a
697 * parameter. This'll end up matching the expected layout of
698 * the array/matrix/structure we're trying to fill in.
699 */
700 int last_swiz = -1;
701 for (unsigned int i = 0; i < 4; i++) {
702 int swiz = GET_SWZ(element->swizzle, i);
703 if (swiz == last_swiz)
704 break;
705 last_swiz = swiz;
706
707 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[swiz];
708 }
709 }
710 }
711 }
712
713 void
714 fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
715 {
716 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
717 fs_reg wpos = *reg;
718 fs_reg neg_y = this->pixel_y;
719 neg_y.negate = true;
720
721 /* gl_FragCoord.x */
722 if (ir->pixel_center_integer) {
723 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_x));
724 } else {
725 emit(fs_inst(BRW_OPCODE_ADD, wpos, this->pixel_x, fs_reg(0.5f)));
726 }
727 wpos.reg_offset++;
728
729 /* gl_FragCoord.y */
730 if (ir->origin_upper_left && ir->pixel_center_integer) {
731 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_y));
732 } else {
733 fs_reg pixel_y = this->pixel_y;
734 float offset = (ir->pixel_center_integer ? 0.0 : 0.5);
735
736 if (!ir->origin_upper_left) {
737 pixel_y.negate = true;
738 offset += c->key.drawable_height - 1.0;
739 }
740
741 emit(fs_inst(BRW_OPCODE_ADD, wpos, pixel_y, fs_reg(offset)));
742 }
743 wpos.reg_offset++;
744
745 /* gl_FragCoord.z */
746 emit(fs_inst(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y,
747 interp_reg(FRAG_ATTRIB_WPOS, 2)));
748 wpos.reg_offset++;
749
750 /* gl_FragCoord.w: Already set up in emit_interpolation */
751 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->wpos_w));
752
753 hash_table_insert(this->variable_ht, reg, ir);
754 }
755
756
757 void
758 fs_visitor::emit_general_interpolation(ir_variable *ir)
759 {
760 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
761 /* Interpolation is always in floating point regs. */
762 reg->type = BRW_REGISTER_TYPE_F;
763 fs_reg attr = *reg;
764
765 unsigned int array_elements;
766 const glsl_type *type;
767
768 if (ir->type->is_array()) {
769 array_elements = ir->type->length;
770 if (array_elements == 0) {
771 this->fail = true;
772 }
773 type = ir->type->fields.array;
774 } else {
775 array_elements = 1;
776 type = ir->type;
777 }
778
779 int location = ir->location;
780 for (unsigned int i = 0; i < array_elements; i++) {
781 for (unsigned int j = 0; j < type->matrix_columns; j++) {
782 if (!(fp->Base.InputsRead & BITFIELD64_BIT(location))) {
783 /* If there's no incoming setup data for this slot, don't
784 * emit interpolation for it (since it's not used, and
785 * we'd fall over later trying to find the setup data.
786 */
787 attr.reg_offset += type->vector_elements;
788 continue;
789 }
790
791 for (unsigned int c = 0; c < type->vector_elements; c++) {
792 struct brw_reg interp = interp_reg(location, c);
793 emit(fs_inst(FS_OPCODE_LINTERP,
794 attr,
795 this->delta_x,
796 this->delta_y,
797 fs_reg(interp)));
798 attr.reg_offset++;
799 }
800 attr.reg_offset -= type->vector_elements;
801
802 for (unsigned int c = 0; c < type->vector_elements; c++) {
803 emit(fs_inst(BRW_OPCODE_MUL,
804 attr,
805 attr,
806 this->pixel_w));
807 attr.reg_offset++;
808 }
809 location++;
810 }
811 }
812
813 hash_table_insert(this->variable_ht, reg, ir);
814 }
815
816 void
817 fs_visitor::visit(ir_variable *ir)
818 {
819 fs_reg *reg = NULL;
820
821 if (variable_storage(ir))
822 return;
823
824 if (strcmp(ir->name, "gl_FragColor") == 0) {
825 this->frag_color = ir;
826 } else if (strcmp(ir->name, "gl_FragData") == 0) {
827 this->frag_data = ir;
828 } else if (strcmp(ir->name, "gl_FragDepth") == 0) {
829 this->frag_depth = ir;
830 }
831
832 if (ir->mode == ir_var_in) {
833 if (!strcmp(ir->name, "gl_FragCoord")) {
834 emit_fragcoord_interpolation(ir);
835 return;
836 } else if (!strcmp(ir->name, "gl_FrontFacing")) {
837 reg = new(this->mem_ctx) fs_reg(this, ir->type);
838 struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD);
839 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
840 * us front face
841 */
842 fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP,
843 *reg,
844 fs_reg(r1_6ud),
845 fs_reg(1u << 31)));
846 inst->conditional_mod = BRW_CONDITIONAL_L;
847 emit(fs_inst(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u)));
848 } else {
849 emit_general_interpolation(ir);
850 return;
851 }
852 }
853
854 if (ir->mode == ir_var_uniform) {
855 int param_index = c->prog_data.nr_params;
856
857 if (!strncmp(ir->name, "gl_", 3)) {
858 setup_builtin_uniform_values(ir);
859 } else {
860 setup_uniform_values(ir->location, ir->type);
861 }
862
863 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index);
864 }
865
866 if (!reg)
867 reg = new(this->mem_ctx) fs_reg(this, ir->type);
868
869 hash_table_insert(this->variable_ht, reg, ir);
870 }
871
872 void
873 fs_visitor::visit(ir_dereference_variable *ir)
874 {
875 fs_reg *reg = variable_storage(ir->var);
876 this->result = *reg;
877 }
878
879 void
880 fs_visitor::visit(ir_dereference_record *ir)
881 {
882 const glsl_type *struct_type = ir->record->type;
883
884 ir->record->accept(this);
885
886 unsigned int offset = 0;
887 for (unsigned int i = 0; i < struct_type->length; i++) {
888 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0)
889 break;
890 offset += type_size(struct_type->fields.structure[i].type);
891 }
892 this->result.reg_offset += offset;
893 this->result.type = brw_type_for_base_type(ir->type);
894 }
895
896 void
897 fs_visitor::visit(ir_dereference_array *ir)
898 {
899 ir_constant *index;
900 int element_size;
901
902 ir->array->accept(this);
903 index = ir->array_index->as_constant();
904
905 element_size = type_size(ir->type);
906 this->result.type = brw_type_for_base_type(ir->type);
907
908 if (index) {
909 assert(this->result.file == UNIFORM ||
910 (this->result.file == GRF &&
911 this->result.reg != 0));
912 this->result.reg_offset += index->value.i[0] * element_size;
913 } else {
914 assert(!"FINISHME: non-constant array element");
915 }
916 }
917
918 void
919 fs_visitor::visit(ir_expression *ir)
920 {
921 unsigned int operand;
922 fs_reg op[2], temp;
923 fs_reg result;
924 fs_inst *inst;
925
926 for (operand = 0; operand < ir->get_num_operands(); operand++) {
927 ir->operands[operand]->accept(this);
928 if (this->result.file == BAD_FILE) {
929 ir_print_visitor v;
930 printf("Failed to get tree for expression operand:\n");
931 ir->operands[operand]->accept(&v);
932 this->fail = true;
933 }
934 op[operand] = this->result;
935
936 /* Matrix expression operands should have been broken down to vector
937 * operations already.
938 */
939 assert(!ir->operands[operand]->type->is_matrix());
940 /* And then those vector operands should have been broken down to scalar.
941 */
942 assert(!ir->operands[operand]->type->is_vector());
943 }
944
945 /* Storage for our result. If our result goes into an assignment, it will
946 * just get copy-propagated out, so no worries.
947 */
948 this->result = fs_reg(this, ir->type);
949
950 switch (ir->operation) {
951 case ir_unop_logic_not:
952 emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], fs_reg(-1)));
953 break;
954 case ir_unop_neg:
955 op[0].negate = !op[0].negate;
956 this->result = op[0];
957 break;
958 case ir_unop_abs:
959 op[0].abs = true;
960 this->result = op[0];
961 break;
962 case ir_unop_sign:
963 temp = fs_reg(this, ir->type);
964
965 emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)));
966
967 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, op[0], fs_reg(0.0f)));
968 inst->conditional_mod = BRW_CONDITIONAL_G;
969 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)));
970 inst->predicated = true;
971
972 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, op[0], fs_reg(0.0f)));
973 inst->conditional_mod = BRW_CONDITIONAL_L;
974 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)));
975 inst->predicated = true;
976
977 break;
978 case ir_unop_rcp:
979 emit(fs_inst(FS_OPCODE_RCP, this->result, op[0]));
980 break;
981
982 case ir_unop_exp2:
983 emit(fs_inst(FS_OPCODE_EXP2, this->result, op[0]));
984 break;
985 case ir_unop_log2:
986 emit(fs_inst(FS_OPCODE_LOG2, this->result, op[0]));
987 break;
988 case ir_unop_exp:
989 case ir_unop_log:
990 assert(!"not reached: should be handled by ir_explog_to_explog2");
991 break;
992 case ir_unop_sin:
993 emit(fs_inst(FS_OPCODE_SIN, this->result, op[0]));
994 break;
995 case ir_unop_cos:
996 emit(fs_inst(FS_OPCODE_COS, this->result, op[0]));
997 break;
998
999 case ir_unop_dFdx:
1000 emit(fs_inst(FS_OPCODE_DDX, this->result, op[0]));
1001 break;
1002 case ir_unop_dFdy:
1003 emit(fs_inst(FS_OPCODE_DDY, this->result, op[0]));
1004 break;
1005
1006 case ir_binop_add:
1007 emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], op[1]));
1008 break;
1009 case ir_binop_sub:
1010 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1011 break;
1012
1013 case ir_binop_mul:
1014 emit(fs_inst(BRW_OPCODE_MUL, this->result, op[0], op[1]));
1015 break;
1016 case ir_binop_div:
1017 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1018 break;
1019 case ir_binop_mod:
1020 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1021 break;
1022
1023 case ir_binop_less:
1024 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1025 inst->conditional_mod = BRW_CONDITIONAL_L;
1026 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
1027 break;
1028 case ir_binop_greater:
1029 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1030 inst->conditional_mod = BRW_CONDITIONAL_G;
1031 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
1032 break;
1033 case ir_binop_lequal:
1034 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1035 inst->conditional_mod = BRW_CONDITIONAL_LE;
1036 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
1037 break;
1038 case ir_binop_gequal:
1039 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1040 inst->conditional_mod = BRW_CONDITIONAL_GE;
1041 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
1042 break;
1043 case ir_binop_equal:
1044 case ir_binop_all_equal: /* same as nequal for scalars */
1045 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1046 inst->conditional_mod = BRW_CONDITIONAL_Z;
1047 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
1048 break;
1049 case ir_binop_nequal:
1050 case ir_binop_any_nequal: /* same as nequal for scalars */
1051 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1052 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1053 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
1054 break;
1055
1056 case ir_binop_logic_xor:
1057 emit(fs_inst(BRW_OPCODE_XOR, this->result, op[0], op[1]));
1058 break;
1059
1060 case ir_binop_logic_or:
1061 emit(fs_inst(BRW_OPCODE_OR, this->result, op[0], op[1]));
1062 break;
1063
1064 case ir_binop_logic_and:
1065 emit(fs_inst(BRW_OPCODE_AND, this->result, op[0], op[1]));
1066 break;
1067
1068 case ir_binop_dot:
1069 case ir_binop_cross:
1070 case ir_unop_any:
1071 assert(!"not reached: should be handled by brw_fs_channel_expressions");
1072 break;
1073
1074 case ir_unop_noise:
1075 assert(!"not reached: should be handled by lower_noise");
1076 break;
1077
1078 case ir_unop_sqrt:
1079 emit(fs_inst(FS_OPCODE_SQRT, this->result, op[0]));
1080 break;
1081
1082 case ir_unop_rsq:
1083 emit(fs_inst(FS_OPCODE_RSQ, this->result, op[0]));
1084 break;
1085
1086 case ir_unop_i2f:
1087 case ir_unop_b2f:
1088 case ir_unop_b2i:
1089 emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0]));
1090 break;
1091 case ir_unop_f2i:
1092 emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0]));
1093 break;
1094 case ir_unop_f2b:
1095 case ir_unop_i2b:
1096 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], fs_reg(0.0f)));
1097 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1098
1099 case ir_unop_trunc:
1100 emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
1101 break;
1102 case ir_unop_ceil:
1103 op[0].negate = ~op[0].negate;
1104 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
1105 this->result.negate = true;
1106 break;
1107 case ir_unop_floor:
1108 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
1109 break;
1110 case ir_unop_fract:
1111 inst = emit(fs_inst(BRW_OPCODE_FRC, this->result, op[0]));
1112 break;
1113
1114 case ir_binop_min:
1115 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1116 inst->conditional_mod = BRW_CONDITIONAL_L;
1117
1118 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1]));
1119 inst->predicated = true;
1120 break;
1121 case ir_binop_max:
1122 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1123 inst->conditional_mod = BRW_CONDITIONAL_G;
1124
1125 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1]));
1126 inst->predicated = true;
1127 break;
1128
1129 case ir_binop_pow:
1130 inst = emit(fs_inst(FS_OPCODE_POW, this->result, op[0], op[1]));
1131 break;
1132
1133 case ir_unop_bit_not:
1134 case ir_unop_u2f:
1135 case ir_binop_lshift:
1136 case ir_binop_rshift:
1137 case ir_binop_bit_and:
1138 case ir_binop_bit_xor:
1139 case ir_binop_bit_or:
1140 assert(!"GLSL 1.30 features unsupported");
1141 break;
1142 }
1143 }
1144
1145 void
1146 fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r,
1147 const glsl_type *type, bool predicated)
1148 {
1149 switch (type->base_type) {
1150 case GLSL_TYPE_FLOAT:
1151 case GLSL_TYPE_UINT:
1152 case GLSL_TYPE_INT:
1153 case GLSL_TYPE_BOOL:
1154 for (unsigned int i = 0; i < type->components(); i++) {
1155 l.type = brw_type_for_base_type(type);
1156 r.type = brw_type_for_base_type(type);
1157
1158 fs_inst *inst = emit(fs_inst(BRW_OPCODE_MOV, l, r));
1159 inst->predicated = predicated;
1160
1161 l.reg_offset++;
1162 r.reg_offset++;
1163 }
1164 break;
1165 case GLSL_TYPE_ARRAY:
1166 for (unsigned int i = 0; i < type->length; i++) {
1167 emit_assignment_writes(l, r, type->fields.array, predicated);
1168 }
1169
1170 case GLSL_TYPE_STRUCT:
1171 for (unsigned int i = 0; i < type->length; i++) {
1172 emit_assignment_writes(l, r, type->fields.structure[i].type,
1173 predicated);
1174 }
1175 break;
1176
1177 case GLSL_TYPE_SAMPLER:
1178 break;
1179
1180 default:
1181 assert(!"not reached");
1182 break;
1183 }
1184 }
1185
1186 void
1187 fs_visitor::visit(ir_assignment *ir)
1188 {
1189 struct fs_reg l, r;
1190 fs_inst *inst;
1191
1192 /* FINISHME: arrays on the lhs */
1193 ir->lhs->accept(this);
1194 l = this->result;
1195
1196 ir->rhs->accept(this);
1197 r = this->result;
1198
1199 assert(l.file != BAD_FILE);
1200 assert(r.file != BAD_FILE);
1201
1202 if (ir->condition) {
1203 /* Get the condition bool into the predicate. */
1204 ir->condition->accept(this);
1205 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, this->result, fs_reg(0)));
1206 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1207 }
1208
1209 if (ir->lhs->type->is_scalar() ||
1210 ir->lhs->type->is_vector()) {
1211 for (int i = 0; i < ir->lhs->type->vector_elements; i++) {
1212 if (ir->write_mask & (1 << i)) {
1213 inst = emit(fs_inst(BRW_OPCODE_MOV, l, r));
1214 if (ir->condition)
1215 inst->predicated = true;
1216 r.reg_offset++;
1217 }
1218 l.reg_offset++;
1219 }
1220 } else {
1221 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL);
1222 }
1223 }
1224
1225 fs_inst *
1226 fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, int base_mrf)
1227 {
1228 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1229 int mlen = 3;
1230
1231 if (ir->shadow_comparitor) {
1232 if (ir->op == ir_tex) {
1233 /* There's no plain shadow compare message, so we use shadow
1234 * compare with a bias of 0.0.
1235 */
1236 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1237 fs_reg(0.0f)));
1238 mlen++;
1239 } else if (ir->op == ir_txb) {
1240 ir->lod_info.bias->accept(this);
1241 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1242 this->result));
1243 mlen++;
1244 } else {
1245 assert(ir->op == ir_txl);
1246 ir->lod_info.lod->accept(this);
1247 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1248 this->result));
1249 mlen++;
1250 }
1251
1252 ir->shadow_comparitor->accept(this);
1253 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1254 mlen++;
1255 } else {
1256 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare sampler
1257 * instructions. We'll need to do SIMD16 here.
1258 */
1259 abort();
1260 }
1261
1262 fs_inst *inst = NULL;
1263 switch (ir->op) {
1264 case ir_tex:
1265 inst = emit(fs_inst(FS_OPCODE_TEX, dst, fs_reg(MRF, base_mrf)));
1266 break;
1267 case ir_txb:
1268 inst = emit(fs_inst(FS_OPCODE_TXB, dst, fs_reg(MRF, base_mrf)));
1269 break;
1270 case ir_txl:
1271 inst = emit(fs_inst(FS_OPCODE_TXL, dst, fs_reg(MRF, base_mrf)));
1272 break;
1273 case ir_txd:
1274 case ir_txf:
1275 assert(!"GLSL 1.30 features unsupported");
1276 break;
1277 }
1278 inst->mlen = mlen;
1279
1280 return inst;
1281 }
1282
1283 fs_inst *
1284 fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, int base_mrf)
1285 {
1286 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1287 * optional parameters like shadow comparitor or LOD bias. If
1288 * optional parameters aren't present, those base slots are
1289 * optional and don't need to be included in the message.
1290 *
1291 * We don't fill in the unnecessary slots regardless, which may
1292 * look surprising in the disassembly.
1293 */
1294 int mlen = ir->coordinate->type->vector_elements;
1295
1296 if (ir->shadow_comparitor) {
1297 mlen = MAX2(mlen, 4);
1298
1299 ir->shadow_comparitor->accept(this);
1300 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1301 mlen++;
1302 }
1303
1304 fs_inst *inst = NULL;
1305 switch (ir->op) {
1306 case ir_tex:
1307 inst = emit(fs_inst(FS_OPCODE_TEX, dst, fs_reg(MRF, base_mrf)));
1308 break;
1309 case ir_txb:
1310 ir->lod_info.bias->accept(this);
1311 mlen = MAX2(mlen, 4);
1312 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1313 mlen++;
1314
1315 inst = emit(fs_inst(FS_OPCODE_TXB, dst, fs_reg(MRF, base_mrf)));
1316 break;
1317 case ir_txl:
1318 ir->lod_info.lod->accept(this);
1319 mlen = MAX2(mlen, 4);
1320 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1321 mlen++;
1322
1323 inst = emit(fs_inst(FS_OPCODE_TXL, dst, fs_reg(MRF, base_mrf)));
1324 break;
1325 case ir_txd:
1326 case ir_txf:
1327 assert(!"GLSL 1.30 features unsupported");
1328 break;
1329 }
1330 inst->mlen = mlen;
1331
1332 return inst;
1333 }
1334
1335 void
1336 fs_visitor::visit(ir_texture *ir)
1337 {
1338 int base_mrf = 2;
1339 fs_inst *inst = NULL;
1340 unsigned int mlen = 0;
1341
1342 ir->coordinate->accept(this);
1343 fs_reg coordinate = this->result;
1344
1345 /* Should be lowered by do_lower_texture_projection */
1346 assert(!ir->projector);
1347
1348 for (mlen = 0; mlen < ir->coordinate->type->vector_elements; mlen++) {
1349 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate));
1350 coordinate.reg_offset++;
1351 }
1352
1353 /* Writemasking doesn't eliminate channels on SIMD8 texture
1354 * samples, so don't worry about them.
1355 */
1356 fs_reg dst = fs_reg(this, glsl_type::vec4_type);
1357
1358 if (intel->gen < 5) {
1359 inst = emit_texture_gen4(ir, dst, base_mrf);
1360 } else {
1361 inst = emit_texture_gen5(ir, dst, base_mrf);
1362 }
1363
1364 inst->sampler =
1365 _mesa_get_sampler_uniform_value(ir->sampler,
1366 ctx->Shader.CurrentProgram,
1367 &brw->fragment_program->Base);
1368 inst->sampler = c->fp->program.Base.SamplerUnits[inst->sampler];
1369
1370 this->result = dst;
1371
1372 if (ir->shadow_comparitor)
1373 inst->shadow_compare = true;
1374 }
1375
1376 void
1377 fs_visitor::visit(ir_swizzle *ir)
1378 {
1379 ir->val->accept(this);
1380 fs_reg val = this->result;
1381
1382 fs_reg result = fs_reg(this, ir->type);
1383 this->result = result;
1384
1385 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1386 fs_reg channel = val;
1387 int swiz = 0;
1388
1389 switch (i) {
1390 case 0:
1391 swiz = ir->mask.x;
1392 break;
1393 case 1:
1394 swiz = ir->mask.y;
1395 break;
1396 case 2:
1397 swiz = ir->mask.z;
1398 break;
1399 case 3:
1400 swiz = ir->mask.w;
1401 break;
1402 }
1403
1404 channel.reg_offset += swiz;
1405 emit(fs_inst(BRW_OPCODE_MOV, result, channel));
1406 result.reg_offset++;
1407 }
1408 }
1409
1410 void
1411 fs_visitor::visit(ir_discard *ir)
1412 {
1413 fs_reg temp = fs_reg(this, glsl_type::uint_type);
1414
1415 assert(ir->condition == NULL); /* FINISHME */
1416
1417 emit(fs_inst(FS_OPCODE_DISCARD, temp, temp));
1418 }
1419
1420 void
1421 fs_visitor::visit(ir_constant *ir)
1422 {
1423 fs_reg reg(this, ir->type);
1424 this->result = reg;
1425
1426 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1427 switch (ir->type->base_type) {
1428 case GLSL_TYPE_FLOAT:
1429 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.f[i])));
1430 break;
1431 case GLSL_TYPE_UINT:
1432 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.u[i])));
1433 break;
1434 case GLSL_TYPE_INT:
1435 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.i[i])));
1436 break;
1437 case GLSL_TYPE_BOOL:
1438 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg((int)ir->value.b[i])));
1439 break;
1440 default:
1441 assert(!"Non-float/uint/int/bool constant");
1442 }
1443 reg.reg_offset++;
1444 }
1445 }
1446
1447 void
1448 fs_visitor::visit(ir_if *ir)
1449 {
1450 fs_inst *inst;
1451
1452 /* Don't point the annotation at the if statement, because then it plus
1453 * the then and else blocks get printed.
1454 */
1455 this->base_ir = ir->condition;
1456
1457 /* Generate the condition into the condition code. */
1458 ir->condition->accept(this);
1459 inst = emit(fs_inst(BRW_OPCODE_MOV, fs_reg(brw_null_reg()), this->result));
1460 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1461
1462 inst = emit(fs_inst(BRW_OPCODE_IF));
1463 inst->predicated = true;
1464
1465 foreach_iter(exec_list_iterator, iter, ir->then_instructions) {
1466 ir_instruction *ir = (ir_instruction *)iter.get();
1467 this->base_ir = ir;
1468
1469 ir->accept(this);
1470 }
1471
1472 if (!ir->else_instructions.is_empty()) {
1473 emit(fs_inst(BRW_OPCODE_ELSE));
1474
1475 foreach_iter(exec_list_iterator, iter, ir->else_instructions) {
1476 ir_instruction *ir = (ir_instruction *)iter.get();
1477 this->base_ir = ir;
1478
1479 ir->accept(this);
1480 }
1481 }
1482
1483 emit(fs_inst(BRW_OPCODE_ENDIF));
1484 }
1485
1486 void
1487 fs_visitor::visit(ir_loop *ir)
1488 {
1489 fs_reg counter = reg_undef;
1490
1491 if (ir->counter) {
1492 this->base_ir = ir->counter;
1493 ir->counter->accept(this);
1494 counter = *(variable_storage(ir->counter));
1495
1496 if (ir->from) {
1497 this->base_ir = ir->from;
1498 ir->from->accept(this);
1499
1500 emit(fs_inst(BRW_OPCODE_MOV, counter, this->result));
1501 }
1502 }
1503
1504 emit(fs_inst(BRW_OPCODE_DO));
1505
1506 if (ir->to) {
1507 this->base_ir = ir->to;
1508 ir->to->accept(this);
1509
1510 fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null,
1511 counter, this->result));
1512 switch (ir->cmp) {
1513 case ir_binop_equal:
1514 inst->conditional_mod = BRW_CONDITIONAL_Z;
1515 break;
1516 case ir_binop_nequal:
1517 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1518 break;
1519 case ir_binop_gequal:
1520 inst->conditional_mod = BRW_CONDITIONAL_GE;
1521 break;
1522 case ir_binop_lequal:
1523 inst->conditional_mod = BRW_CONDITIONAL_LE;
1524 break;
1525 case ir_binop_greater:
1526 inst->conditional_mod = BRW_CONDITIONAL_G;
1527 break;
1528 case ir_binop_less:
1529 inst->conditional_mod = BRW_CONDITIONAL_L;
1530 break;
1531 default:
1532 assert(!"not reached: unknown loop condition");
1533 this->fail = true;
1534 break;
1535 }
1536
1537 inst = emit(fs_inst(BRW_OPCODE_BREAK));
1538 inst->predicated = true;
1539 }
1540
1541 foreach_iter(exec_list_iterator, iter, ir->body_instructions) {
1542 ir_instruction *ir = (ir_instruction *)iter.get();
1543
1544 this->base_ir = ir;
1545 ir->accept(this);
1546 }
1547
1548 if (ir->increment) {
1549 this->base_ir = ir->increment;
1550 ir->increment->accept(this);
1551 emit(fs_inst(BRW_OPCODE_ADD, counter, counter, this->result));
1552 }
1553
1554 emit(fs_inst(BRW_OPCODE_WHILE));
1555 }
1556
1557 void
1558 fs_visitor::visit(ir_loop_jump *ir)
1559 {
1560 switch (ir->mode) {
1561 case ir_loop_jump::jump_break:
1562 emit(fs_inst(BRW_OPCODE_BREAK));
1563 break;
1564 case ir_loop_jump::jump_continue:
1565 emit(fs_inst(BRW_OPCODE_CONTINUE));
1566 break;
1567 }
1568 }
1569
1570 void
1571 fs_visitor::visit(ir_call *ir)
1572 {
1573 assert(!"FINISHME");
1574 }
1575
1576 void
1577 fs_visitor::visit(ir_return *ir)
1578 {
1579 assert(!"FINISHME");
1580 }
1581
1582 void
1583 fs_visitor::visit(ir_function *ir)
1584 {
1585 /* Ignore function bodies other than main() -- we shouldn't see calls to
1586 * them since they should all be inlined before we get to ir_to_mesa.
1587 */
1588 if (strcmp(ir->name, "main") == 0) {
1589 const ir_function_signature *sig;
1590 exec_list empty;
1591
1592 sig = ir->matching_signature(&empty);
1593
1594 assert(sig);
1595
1596 foreach_iter(exec_list_iterator, iter, sig->body) {
1597 ir_instruction *ir = (ir_instruction *)iter.get();
1598 this->base_ir = ir;
1599
1600 ir->accept(this);
1601 }
1602 }
1603 }
1604
1605 void
1606 fs_visitor::visit(ir_function_signature *ir)
1607 {
1608 assert(!"not reached");
1609 (void)ir;
1610 }
1611
1612 fs_inst *
1613 fs_visitor::emit(fs_inst inst)
1614 {
1615 fs_inst *list_inst = new(mem_ctx) fs_inst;
1616 *list_inst = inst;
1617
1618 list_inst->annotation = this->current_annotation;
1619 list_inst->ir = this->base_ir;
1620
1621 this->instructions.push_tail(list_inst);
1622
1623 return list_inst;
1624 }
1625
1626 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1627 void
1628 fs_visitor::emit_dummy_fs()
1629 {
1630 /* Everyone's favorite color. */
1631 emit(fs_inst(BRW_OPCODE_MOV,
1632 fs_reg(MRF, 2),
1633 fs_reg(1.0f)));
1634 emit(fs_inst(BRW_OPCODE_MOV,
1635 fs_reg(MRF, 3),
1636 fs_reg(0.0f)));
1637 emit(fs_inst(BRW_OPCODE_MOV,
1638 fs_reg(MRF, 4),
1639 fs_reg(1.0f)));
1640 emit(fs_inst(BRW_OPCODE_MOV,
1641 fs_reg(MRF, 5),
1642 fs_reg(0.0f)));
1643
1644 fs_inst *write;
1645 write = emit(fs_inst(FS_OPCODE_FB_WRITE,
1646 fs_reg(0),
1647 fs_reg(0)));
1648 }
1649
1650 /* The register location here is relative to the start of the URB
1651 * data. It will get adjusted to be a real location before
1652 * generate_code() time.
1653 */
1654 struct brw_reg
1655 fs_visitor::interp_reg(int location, int channel)
1656 {
1657 int regnr = location * 2 + channel / 2;
1658 int stride = (channel & 1) * 4;
1659
1660 return brw_vec1_grf(regnr, stride);
1661 }
1662
1663 /** Emits the interpolation for the varying inputs. */
1664 void
1665 fs_visitor::emit_interpolation_setup()
1666 {
1667 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
1668
1669 this->current_annotation = "compute pixel centers";
1670 this->pixel_x = fs_reg(this, glsl_type::uint_type);
1671 this->pixel_y = fs_reg(this, glsl_type::uint_type);
1672 this->pixel_x.type = BRW_REGISTER_TYPE_UW;
1673 this->pixel_y.type = BRW_REGISTER_TYPE_UW;
1674 emit(fs_inst(BRW_OPCODE_ADD,
1675 this->pixel_x,
1676 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
1677 fs_reg(brw_imm_v(0x10101010))));
1678 emit(fs_inst(BRW_OPCODE_ADD,
1679 this->pixel_y,
1680 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
1681 fs_reg(brw_imm_v(0x11001100))));
1682
1683 this->current_annotation = "compute pixel deltas from v0";
1684 this->delta_x = fs_reg(this, glsl_type::float_type);
1685 this->delta_y = fs_reg(this, glsl_type::float_type);
1686 emit(fs_inst(BRW_OPCODE_ADD,
1687 this->delta_x,
1688 this->pixel_x,
1689 fs_reg(negate(brw_vec1_grf(1, 0)))));
1690 emit(fs_inst(BRW_OPCODE_ADD,
1691 this->delta_y,
1692 this->pixel_y,
1693 fs_reg(negate(brw_vec1_grf(1, 1)))));
1694
1695 this->current_annotation = "compute pos.w and 1/pos.w";
1696 /* Compute wpos.w. It's always in our setup, since it's needed to
1697 * interpolate the other attributes.
1698 */
1699 this->wpos_w = fs_reg(this, glsl_type::float_type);
1700 emit(fs_inst(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y,
1701 interp_reg(FRAG_ATTRIB_WPOS, 3)));
1702 /* Compute the pixel 1/W value from wpos.w. */
1703 this->pixel_w = fs_reg(this, glsl_type::float_type);
1704 emit(fs_inst(FS_OPCODE_RCP, this->pixel_w, wpos_w));
1705 this->current_annotation = NULL;
1706 }
1707
1708 void
1709 fs_visitor::emit_fb_writes()
1710 {
1711 this->current_annotation = "FB write header";
1712 int nr = 0;
1713
1714 /* m0, m1 header */
1715 nr += 2;
1716
1717 if (c->key.aa_dest_stencil_reg) {
1718 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
1719 fs_reg(brw_vec8_grf(c->key.aa_dest_stencil_reg, 0))));
1720 }
1721
1722 /* Reserve space for color. It'll be filled in per MRT below. */
1723 int color_mrf = nr;
1724 nr += 4;
1725
1726 if (c->key.source_depth_to_render_target) {
1727 if (c->key.computes_depth) {
1728 /* Hand over gl_FragDepth. */
1729 assert(this->frag_depth);
1730 fs_reg depth = *(variable_storage(this->frag_depth));
1731
1732 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++), depth));
1733 } else {
1734 /* Pass through the payload depth. */
1735 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
1736 fs_reg(brw_vec8_grf(c->key.source_depth_reg, 0))));
1737 }
1738 }
1739
1740 if (c->key.dest_depth_reg) {
1741 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
1742 fs_reg(brw_vec8_grf(c->key.dest_depth_reg, 0))));
1743 }
1744
1745 fs_reg color = reg_undef;
1746 if (this->frag_color)
1747 color = *(variable_storage(this->frag_color));
1748 else if (this->frag_data)
1749 color = *(variable_storage(this->frag_data));
1750
1751 for (int target = 0; target < c->key.nr_color_regions; target++) {
1752 this->current_annotation = talloc_asprintf(this->mem_ctx,
1753 "FB write target %d",
1754 target);
1755 if (this->frag_color || this->frag_data) {
1756 for (int i = 0; i < 4; i++) {
1757 emit(fs_inst(BRW_OPCODE_MOV,
1758 fs_reg(MRF, color_mrf + i),
1759 color));
1760 color.reg_offset++;
1761 }
1762 }
1763
1764 if (this->frag_color)
1765 color.reg_offset -= 4;
1766
1767 fs_inst *inst = emit(fs_inst(FS_OPCODE_FB_WRITE,
1768 reg_undef, reg_undef));
1769 inst->target = target;
1770 inst->mlen = nr;
1771 if (target == c->key.nr_color_regions - 1)
1772 inst->eot = true;
1773 }
1774
1775 if (c->key.nr_color_regions == 0) {
1776 fs_inst *inst = emit(fs_inst(FS_OPCODE_FB_WRITE,
1777 reg_undef, reg_undef));
1778 inst->mlen = nr;
1779 inst->eot = true;
1780 }
1781
1782 this->current_annotation = NULL;
1783 }
1784
1785 void
1786 fs_visitor::generate_fb_write(fs_inst *inst)
1787 {
1788 GLboolean eot = inst->eot;
1789
1790 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1791 * move, here's g1.
1792 */
1793 brw_push_insn_state(p);
1794 brw_set_mask_control(p, BRW_MASK_DISABLE);
1795 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1796 brw_MOV(p,
1797 brw_message_reg(1),
1798 brw_vec8_grf(1, 0));
1799 brw_pop_insn_state(p);
1800
1801 brw_fb_WRITE(p,
1802 8, /* dispatch_width */
1803 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW),
1804 0, /* base MRF */
1805 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
1806 inst->target,
1807 inst->mlen,
1808 0,
1809 eot);
1810 }
1811
1812 void
1813 fs_visitor::generate_linterp(fs_inst *inst,
1814 struct brw_reg dst, struct brw_reg *src)
1815 {
1816 struct brw_reg delta_x = src[0];
1817 struct brw_reg delta_y = src[1];
1818 struct brw_reg interp = src[2];
1819
1820 if (brw->has_pln &&
1821 delta_y.nr == delta_x.nr + 1 &&
1822 (intel->gen >= 6 || (delta_x.nr & 1) == 0)) {
1823 brw_PLN(p, dst, interp, delta_x);
1824 } else {
1825 brw_LINE(p, brw_null_reg(), interp, delta_x);
1826 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
1827 }
1828 }
1829
1830 void
1831 fs_visitor::generate_math(fs_inst *inst,
1832 struct brw_reg dst, struct brw_reg *src)
1833 {
1834 int op;
1835
1836 switch (inst->opcode) {
1837 case FS_OPCODE_RCP:
1838 op = BRW_MATH_FUNCTION_INV;
1839 break;
1840 case FS_OPCODE_RSQ:
1841 op = BRW_MATH_FUNCTION_RSQ;
1842 break;
1843 case FS_OPCODE_SQRT:
1844 op = BRW_MATH_FUNCTION_SQRT;
1845 break;
1846 case FS_OPCODE_EXP2:
1847 op = BRW_MATH_FUNCTION_EXP;
1848 break;
1849 case FS_OPCODE_LOG2:
1850 op = BRW_MATH_FUNCTION_LOG;
1851 break;
1852 case FS_OPCODE_POW:
1853 op = BRW_MATH_FUNCTION_POW;
1854 break;
1855 case FS_OPCODE_SIN:
1856 op = BRW_MATH_FUNCTION_SIN;
1857 break;
1858 case FS_OPCODE_COS:
1859 op = BRW_MATH_FUNCTION_COS;
1860 break;
1861 default:
1862 assert(!"not reached: unknown math function");
1863 op = 0;
1864 break;
1865 }
1866
1867 if (inst->opcode == FS_OPCODE_POW) {
1868 brw_MOV(p, brw_message_reg(3), src[1]);
1869 }
1870
1871 brw_math(p, dst,
1872 op,
1873 inst->saturate ? BRW_MATH_SATURATE_SATURATE :
1874 BRW_MATH_SATURATE_NONE,
1875 2, src[0],
1876 BRW_MATH_DATA_VECTOR,
1877 BRW_MATH_PRECISION_FULL);
1878 }
1879
1880 void
1881 fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
1882 {
1883 int msg_type = -1;
1884 int rlen = 4;
1885
1886 if (intel->gen == 5) {
1887 switch (inst->opcode) {
1888 case FS_OPCODE_TEX:
1889 if (inst->shadow_compare) {
1890 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5;
1891 } else {
1892 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_GEN5;
1893 }
1894 break;
1895 case FS_OPCODE_TXB:
1896 if (inst->shadow_compare) {
1897 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5;
1898 } else {
1899 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5;
1900 }
1901 break;
1902 }
1903 } else {
1904 switch (inst->opcode) {
1905 case FS_OPCODE_TEX:
1906 /* Note that G45 and older determines shadow compare and dispatch width
1907 * from message length for most messages.
1908 */
1909 if (inst->shadow_compare) {
1910 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
1911 } else {
1912 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
1913 }
1914 case FS_OPCODE_TXB:
1915 if (inst->shadow_compare) {
1916 assert(!"FINISHME: shadow compare with bias.");
1917 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
1918 } else {
1919 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
1920 rlen = 8;
1921 }
1922 break;
1923 }
1924 }
1925 assert(msg_type != -1);
1926
1927 /* g0 header. */
1928 src.nr--;
1929
1930 brw_SAMPLE(p,
1931 retype(dst, BRW_REGISTER_TYPE_UW),
1932 src.nr,
1933 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
1934 SURF_INDEX_TEXTURE(inst->sampler),
1935 inst->sampler,
1936 WRITEMASK_XYZW,
1937 msg_type,
1938 rlen,
1939 inst->mlen + 1,
1940 0,
1941 1,
1942 BRW_SAMPLER_SIMD_MODE_SIMD8);
1943 }
1944
1945
1946 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1947 * looking like:
1948 *
1949 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1950 *
1951 * and we're trying to produce:
1952 *
1953 * DDX DDY
1954 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1955 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1956 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1957 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1958 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1959 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1960 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1961 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1962 *
1963 * and add another set of two more subspans if in 16-pixel dispatch mode.
1964 *
1965 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1966 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1967 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
1968 * between each other. We could probably do it like ddx and swizzle the right
1969 * order later, but bail for now and just produce
1970 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
1971 */
1972 void
1973 fs_visitor::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
1974 {
1975 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
1976 BRW_REGISTER_TYPE_F,
1977 BRW_VERTICAL_STRIDE_2,
1978 BRW_WIDTH_2,
1979 BRW_HORIZONTAL_STRIDE_0,
1980 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1981 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1982 BRW_REGISTER_TYPE_F,
1983 BRW_VERTICAL_STRIDE_2,
1984 BRW_WIDTH_2,
1985 BRW_HORIZONTAL_STRIDE_0,
1986 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1987 brw_ADD(p, dst, src0, negate(src1));
1988 }
1989
1990 void
1991 fs_visitor::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
1992 {
1993 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1994 BRW_REGISTER_TYPE_F,
1995 BRW_VERTICAL_STRIDE_4,
1996 BRW_WIDTH_4,
1997 BRW_HORIZONTAL_STRIDE_0,
1998 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1999 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
2000 BRW_REGISTER_TYPE_F,
2001 BRW_VERTICAL_STRIDE_4,
2002 BRW_WIDTH_4,
2003 BRW_HORIZONTAL_STRIDE_0,
2004 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
2005 brw_ADD(p, dst, src0, negate(src1));
2006 }
2007
2008 void
2009 fs_visitor::generate_discard(fs_inst *inst, struct brw_reg temp)
2010 {
2011 struct brw_reg g0 = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
2012 temp = brw_uw1_reg(temp.file, temp.nr, 0);
2013
2014 brw_push_insn_state(p);
2015 brw_set_mask_control(p, BRW_MASK_DISABLE);
2016 brw_NOT(p, temp, brw_mask_reg(1)); /* IMASK */
2017 brw_AND(p, g0, temp, g0);
2018 brw_pop_insn_state(p);
2019 }
2020
2021 void
2022 fs_visitor::assign_curb_setup()
2023 {
2024 c->prog_data.first_curbe_grf = c->key.nr_payload_regs;
2025 c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8;
2026
2027 if (intel->gen == 5 && (c->prog_data.first_curbe_grf +
2028 c->prog_data.curb_read_length) & 1) {
2029 /* Align the start of the interpolation coefficients so that we can use
2030 * the PLN instruction.
2031 */
2032 c->prog_data.first_curbe_grf++;
2033 }
2034
2035 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2036 foreach_iter(exec_list_iterator, iter, this->instructions) {
2037 fs_inst *inst = (fs_inst *)iter.get();
2038
2039 for (unsigned int i = 0; i < 3; i++) {
2040 if (inst->src[i].file == UNIFORM) {
2041 int constant_nr = inst->src[i].hw_reg + inst->src[i].reg_offset;
2042 struct brw_reg brw_reg = brw_vec1_grf(c->prog_data.first_curbe_grf +
2043 constant_nr / 8,
2044 constant_nr % 8);
2045
2046 inst->src[i].file = FIXED_HW_REG;
2047 inst->src[i].fixed_hw_reg = brw_reg;
2048 }
2049 }
2050 }
2051 }
2052
2053 void
2054 fs_visitor::assign_urb_setup()
2055 {
2056 int urb_start = c->prog_data.first_curbe_grf + c->prog_data.curb_read_length;
2057 int interp_reg_nr[FRAG_ATTRIB_MAX];
2058
2059 c->prog_data.urb_read_length = 0;
2060
2061 /* Figure out where each of the incoming setup attributes lands. */
2062 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
2063 interp_reg_nr[i] = -1;
2064
2065 if (i != FRAG_ATTRIB_WPOS &&
2066 !(brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(i)))
2067 continue;
2068
2069 /* Each attribute is 4 setup channels, each of which is half a reg. */
2070 interp_reg_nr[i] = urb_start + c->prog_data.urb_read_length;
2071 c->prog_data.urb_read_length += 2;
2072 }
2073
2074 /* Map the register numbers for FS_OPCODE_LINTERP so that it uses
2075 * the correct setup input.
2076 */
2077 foreach_iter(exec_list_iterator, iter, this->instructions) {
2078 fs_inst *inst = (fs_inst *)iter.get();
2079
2080 if (inst->opcode != FS_OPCODE_LINTERP)
2081 continue;
2082
2083 assert(inst->src[2].file == FIXED_HW_REG);
2084
2085 int location = inst->src[2].fixed_hw_reg.nr / 2;
2086 assert(interp_reg_nr[location] != -1);
2087 inst->src[2].fixed_hw_reg.nr = (interp_reg_nr[location] +
2088 (inst->src[2].fixed_hw_reg.nr & 1));
2089 }
2090
2091 this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length;
2092 }
2093
2094 static void
2095 assign_reg(int *reg_hw_locations, fs_reg *reg)
2096 {
2097 if (reg->file == GRF && reg->reg != 0) {
2098 reg->hw_reg = reg_hw_locations[reg->reg] + reg->reg_offset;
2099 reg->reg = 0;
2100 }
2101 }
2102
2103 void
2104 fs_visitor::assign_regs_trivial()
2105 {
2106 int last_grf = 0;
2107 int hw_reg_mapping[this->virtual_grf_next];
2108 int i;
2109
2110 hw_reg_mapping[0] = 0;
2111 hw_reg_mapping[1] = this->first_non_payload_grf;
2112 for (i = 2; i < this->virtual_grf_next; i++) {
2113 hw_reg_mapping[i] = (hw_reg_mapping[i - 1] +
2114 this->virtual_grf_sizes[i - 1]);
2115 }
2116 last_grf = hw_reg_mapping[i - 1] + this->virtual_grf_sizes[i - 1];
2117
2118 foreach_iter(exec_list_iterator, iter, this->instructions) {
2119 fs_inst *inst = (fs_inst *)iter.get();
2120
2121 assign_reg(hw_reg_mapping, &inst->dst);
2122 assign_reg(hw_reg_mapping, &inst->src[0]);
2123 assign_reg(hw_reg_mapping, &inst->src[1]);
2124 }
2125
2126 this->grf_used = last_grf + 1;
2127 }
2128
2129 void
2130 fs_visitor::assign_regs()
2131 {
2132 int last_grf = 0;
2133 int hw_reg_mapping[this->virtual_grf_next + 1];
2134 int base_reg_count = BRW_MAX_GRF - this->first_non_payload_grf;
2135 int class_sizes[base_reg_count];
2136 int class_count = 0;
2137
2138 calculate_live_intervals();
2139
2140 /* Set up the register classes.
2141 *
2142 * The base registers store a scalar value. For texture samples,
2143 * we get virtual GRFs composed of 4 contiguous hw register. For
2144 * structures and arrays, we store them as contiguous larger things
2145 * than that, though we should be able to do better most of the
2146 * time.
2147 */
2148 class_sizes[class_count++] = 1;
2149 for (int r = 1; r < this->virtual_grf_next; r++) {
2150 int i;
2151
2152 for (i = 0; i < class_count; i++) {
2153 if (class_sizes[i] == this->virtual_grf_sizes[r])
2154 break;
2155 }
2156 if (i == class_count) {
2157 class_sizes[class_count++] = this->virtual_grf_sizes[r];
2158 }
2159 }
2160
2161 int ra_reg_count = 0;
2162 int class_base_reg[class_count];
2163 int class_reg_count[class_count];
2164 int classes[class_count];
2165
2166 for (int i = 0; i < class_count; i++) {
2167 class_base_reg[i] = ra_reg_count;
2168 class_reg_count[i] = base_reg_count - (class_sizes[i] - 1);
2169 ra_reg_count += class_reg_count[i];
2170 }
2171
2172 struct ra_regs *regs = ra_alloc_reg_set(ra_reg_count);
2173 for (int i = 0; i < class_count; i++) {
2174 classes[i] = ra_alloc_reg_class(regs);
2175
2176 for (int i_r = 0; i_r < class_reg_count[i]; i_r++) {
2177 ra_class_add_reg(regs, classes[i], class_base_reg[i] + i_r);
2178 }
2179
2180 /* Add conflicts between our contiguous registers aliasing
2181 * base regs and other register classes' contiguous registers
2182 * that alias base regs, or the base regs themselves for classes[0].
2183 */
2184 for (int c = 0; c <= i; c++) {
2185 for (int i_r = 0; i_r < class_reg_count[i] - 1; i_r++) {
2186 for (int c_r = MAX2(0, i_r - (class_sizes[c] - 1));
2187 c_r <= MIN2(class_reg_count[c] - 1, i_r + class_sizes[i] - 1);
2188 c_r++) {
2189
2190 if (0) {
2191 printf("%d/%d conflicts %d/%d\n",
2192 class_sizes[i], i_r,
2193 class_sizes[c], c_r);
2194 }
2195
2196 ra_add_reg_conflict(regs,
2197 class_base_reg[i] + i_r,
2198 class_base_reg[c] + c_r);
2199 }
2200 }
2201 }
2202 }
2203
2204 ra_set_finalize(regs);
2205
2206 struct ra_graph *g = ra_alloc_interference_graph(regs,
2207 this->virtual_grf_next);
2208 /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
2209 * with nodes.
2210 */
2211 ra_set_node_class(g, 0, classes[0]);
2212
2213 for (int i = 1; i < this->virtual_grf_next; i++) {
2214 for (int c = 0; c < class_count; c++) {
2215 if (class_sizes[c] == this->virtual_grf_sizes[i]) {
2216 ra_set_node_class(g, i, classes[c]);
2217 break;
2218 }
2219 }
2220
2221 for (int j = 1; j < i; j++) {
2222 if (virtual_grf_interferes(i, j)) {
2223 ra_add_node_interference(g, i, j);
2224 }
2225 }
2226 }
2227
2228 /* FINISHME: Handle spilling */
2229 if (!ra_allocate_no_spills(g)) {
2230 fprintf(stderr, "Failed to allocate registers.\n");
2231 this->fail = true;
2232 return;
2233 }
2234
2235 /* Get the chosen virtual registers for each node, and map virtual
2236 * regs in the register classes back down to real hardware reg
2237 * numbers.
2238 */
2239 hw_reg_mapping[0] = 0; /* unused */
2240 for (int i = 1; i < this->virtual_grf_next; i++) {
2241 int reg = ra_get_node_reg(g, i);
2242 int hw_reg = -1;
2243
2244 for (int c = 0; c < class_count; c++) {
2245 if (reg >= class_base_reg[c] &&
2246 reg < class_base_reg[c] + class_reg_count[c] - 1) {
2247 hw_reg = reg - class_base_reg[c];
2248 break;
2249 }
2250 }
2251
2252 assert(hw_reg != -1);
2253 hw_reg_mapping[i] = this->first_non_payload_grf + hw_reg;
2254 last_grf = MAX2(last_grf,
2255 hw_reg_mapping[i] + this->virtual_grf_sizes[i] - 1);
2256 }
2257
2258 foreach_iter(exec_list_iterator, iter, this->instructions) {
2259 fs_inst *inst = (fs_inst *)iter.get();
2260
2261 assign_reg(hw_reg_mapping, &inst->dst);
2262 assign_reg(hw_reg_mapping, &inst->src[0]);
2263 assign_reg(hw_reg_mapping, &inst->src[1]);
2264 }
2265
2266 this->grf_used = last_grf + 1;
2267
2268 talloc_free(g);
2269 talloc_free(regs);
2270 }
2271
2272 void
2273 fs_visitor::calculate_live_intervals()
2274 {
2275 int num_vars = this->virtual_grf_next;
2276 int *def = talloc_array(mem_ctx, int, num_vars);
2277 int *use = talloc_array(mem_ctx, int, num_vars);
2278 int loop_depth = 0;
2279 int loop_start = 0;
2280
2281 for (int i = 0; i < num_vars; i++) {
2282 def[i] = 1 << 30;
2283 use[i] = 0;
2284 }
2285
2286 int ip = 0;
2287 foreach_iter(exec_list_iterator, iter, this->instructions) {
2288 fs_inst *inst = (fs_inst *)iter.get();
2289
2290 if (inst->opcode == BRW_OPCODE_DO) {
2291 if (loop_depth++ == 0)
2292 loop_start = ip;
2293 } else if (inst->opcode == BRW_OPCODE_WHILE) {
2294 loop_depth--;
2295
2296 if (loop_depth == 0) {
2297 /* FINISHME:
2298 *
2299 * Patches up any vars marked for use within the loop as
2300 * live until the end. This is conservative, as there
2301 * will often be variables defined and used inside the
2302 * loop but dead at the end of the loop body.
2303 */
2304 for (int i = 0; i < num_vars; i++) {
2305 if (use[i] == loop_start) {
2306 use[i] = ip;
2307 }
2308 }
2309 }
2310 } else {
2311 int eip = ip;
2312
2313 if (loop_depth)
2314 eip = loop_start;
2315
2316 for (unsigned int i = 0; i < 3; i++) {
2317 if (inst->src[i].file == GRF && inst->src[i].reg != 0) {
2318 def[inst->src[i].reg] = MIN2(def[inst->src[i].reg], eip);
2319 use[inst->src[i].reg] = MAX2(use[inst->src[i].reg], eip);
2320 }
2321 }
2322 if (inst->dst.file == GRF && inst->dst.reg != 0) {
2323 def[inst->dst.reg] = MIN2(def[inst->dst.reg], eip);
2324 use[inst->dst.reg] = MAX2(use[inst->dst.reg], eip);
2325 }
2326 }
2327
2328 ip++;
2329 }
2330
2331 this->virtual_grf_def = def;
2332 this->virtual_grf_use = use;
2333 }
2334
2335 bool
2336 fs_visitor::virtual_grf_interferes(int a, int b)
2337 {
2338 int start = MAX2(this->virtual_grf_def[a], this->virtual_grf_def[b]);
2339 int end = MIN2(this->virtual_grf_use[a], this->virtual_grf_use[b]);
2340
2341 return start <= end;
2342 }
2343
2344 static struct brw_reg brw_reg_from_fs_reg(fs_reg *reg)
2345 {
2346 struct brw_reg brw_reg;
2347
2348 switch (reg->file) {
2349 case GRF:
2350 case ARF:
2351 case MRF:
2352 brw_reg = brw_vec8_reg(reg->file,
2353 reg->hw_reg, 0);
2354 brw_reg = retype(brw_reg, reg->type);
2355 break;
2356 case IMM:
2357 switch (reg->type) {
2358 case BRW_REGISTER_TYPE_F:
2359 brw_reg = brw_imm_f(reg->imm.f);
2360 break;
2361 case BRW_REGISTER_TYPE_D:
2362 brw_reg = brw_imm_d(reg->imm.i);
2363 break;
2364 case BRW_REGISTER_TYPE_UD:
2365 brw_reg = brw_imm_ud(reg->imm.u);
2366 break;
2367 default:
2368 assert(!"not reached");
2369 break;
2370 }
2371 break;
2372 case FIXED_HW_REG:
2373 brw_reg = reg->fixed_hw_reg;
2374 break;
2375 case BAD_FILE:
2376 /* Probably unused. */
2377 brw_reg = brw_null_reg();
2378 break;
2379 case UNIFORM:
2380 assert(!"not reached");
2381 brw_reg = brw_null_reg();
2382 break;
2383 }
2384 if (reg->abs)
2385 brw_reg = brw_abs(brw_reg);
2386 if (reg->negate)
2387 brw_reg = negate(brw_reg);
2388
2389 return brw_reg;
2390 }
2391
2392 void
2393 fs_visitor::generate_code()
2394 {
2395 unsigned int annotation_len = 0;
2396 int last_native_inst = 0;
2397 struct brw_instruction *if_stack[16], *loop_stack[16];
2398 int if_stack_depth = 0, loop_stack_depth = 0;
2399 int if_depth_in_loop[16];
2400
2401 if_depth_in_loop[loop_stack_depth] = 0;
2402
2403 memset(&if_stack, 0, sizeof(if_stack));
2404 foreach_iter(exec_list_iterator, iter, this->instructions) {
2405 fs_inst *inst = (fs_inst *)iter.get();
2406 struct brw_reg src[3], dst;
2407
2408 for (unsigned int i = 0; i < 3; i++) {
2409 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
2410 }
2411 dst = brw_reg_from_fs_reg(&inst->dst);
2412
2413 brw_set_conditionalmod(p, inst->conditional_mod);
2414 brw_set_predicate_control(p, inst->predicated);
2415
2416 switch (inst->opcode) {
2417 case BRW_OPCODE_MOV:
2418 brw_MOV(p, dst, src[0]);
2419 break;
2420 case BRW_OPCODE_ADD:
2421 brw_ADD(p, dst, src[0], src[1]);
2422 break;
2423 case BRW_OPCODE_MUL:
2424 brw_MUL(p, dst, src[0], src[1]);
2425 break;
2426
2427 case BRW_OPCODE_FRC:
2428 brw_FRC(p, dst, src[0]);
2429 break;
2430 case BRW_OPCODE_RNDD:
2431 brw_RNDD(p, dst, src[0]);
2432 break;
2433 case BRW_OPCODE_RNDZ:
2434 brw_RNDZ(p, dst, src[0]);
2435 break;
2436
2437 case BRW_OPCODE_AND:
2438 brw_AND(p, dst, src[0], src[1]);
2439 break;
2440 case BRW_OPCODE_OR:
2441 brw_OR(p, dst, src[0], src[1]);
2442 break;
2443 case BRW_OPCODE_XOR:
2444 brw_XOR(p, dst, src[0], src[1]);
2445 break;
2446
2447 case BRW_OPCODE_CMP:
2448 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
2449 break;
2450 case BRW_OPCODE_SEL:
2451 brw_SEL(p, dst, src[0], src[1]);
2452 break;
2453
2454 case BRW_OPCODE_IF:
2455 assert(if_stack_depth < 16);
2456 if_stack[if_stack_depth] = brw_IF(p, BRW_EXECUTE_8);
2457 if_depth_in_loop[loop_stack_depth]++;
2458 if_stack_depth++;
2459 break;
2460 case BRW_OPCODE_ELSE:
2461 if_stack[if_stack_depth - 1] =
2462 brw_ELSE(p, if_stack[if_stack_depth - 1]);
2463 break;
2464 case BRW_OPCODE_ENDIF:
2465 if_stack_depth--;
2466 brw_ENDIF(p , if_stack[if_stack_depth]);
2467 if_depth_in_loop[loop_stack_depth]--;
2468 break;
2469
2470 case BRW_OPCODE_DO:
2471 loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
2472 if_depth_in_loop[loop_stack_depth] = 0;
2473 break;
2474
2475 case BRW_OPCODE_BREAK:
2476 brw_BREAK(p, if_depth_in_loop[loop_stack_depth]);
2477 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
2478 break;
2479 case BRW_OPCODE_CONTINUE:
2480 brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
2481 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
2482 break;
2483
2484 case BRW_OPCODE_WHILE: {
2485 struct brw_instruction *inst0, *inst1;
2486 GLuint br = 1;
2487
2488 if (intel->gen == 5)
2489 br = 2;
2490
2491 assert(loop_stack_depth > 0);
2492 loop_stack_depth--;
2493 inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
2494 /* patch all the BREAK/CONT instructions from last BGNLOOP */
2495 while (inst0 > loop_stack[loop_stack_depth]) {
2496 inst0--;
2497 if (inst0->header.opcode == BRW_OPCODE_BREAK &&
2498 inst0->bits3.if_else.jump_count == 0) {
2499 inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
2500 }
2501 else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
2502 inst0->bits3.if_else.jump_count == 0) {
2503 inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
2504 }
2505 }
2506 }
2507 break;
2508
2509 case FS_OPCODE_RCP:
2510 case FS_OPCODE_RSQ:
2511 case FS_OPCODE_SQRT:
2512 case FS_OPCODE_EXP2:
2513 case FS_OPCODE_LOG2:
2514 case FS_OPCODE_POW:
2515 case FS_OPCODE_SIN:
2516 case FS_OPCODE_COS:
2517 generate_math(inst, dst, src);
2518 break;
2519 case FS_OPCODE_LINTERP:
2520 generate_linterp(inst, dst, src);
2521 break;
2522 case FS_OPCODE_TEX:
2523 case FS_OPCODE_TXB:
2524 case FS_OPCODE_TXL:
2525 generate_tex(inst, dst, src[0]);
2526 break;
2527 case FS_OPCODE_DISCARD:
2528 generate_discard(inst, dst /* src0 == dst */);
2529 break;
2530 case FS_OPCODE_DDX:
2531 generate_ddx(inst, dst, src[0]);
2532 break;
2533 case FS_OPCODE_DDY:
2534 generate_ddy(inst, dst, src[0]);
2535 break;
2536 case FS_OPCODE_FB_WRITE:
2537 generate_fb_write(inst);
2538 break;
2539 default:
2540 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
2541 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
2542 brw_opcodes[inst->opcode].name);
2543 } else {
2544 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
2545 }
2546 this->fail = true;
2547 }
2548
2549 if (annotation_len < p->nr_insn) {
2550 annotation_len *= 2;
2551 if (annotation_len < 16)
2552 annotation_len = 16;
2553
2554 this->annotation_string = talloc_realloc(this->mem_ctx,
2555 annotation_string,
2556 const char *,
2557 annotation_len);
2558 this->annotation_ir = talloc_realloc(this->mem_ctx,
2559 annotation_ir,
2560 ir_instruction *,
2561 annotation_len);
2562 }
2563
2564 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
2565 this->annotation_string[i] = inst->annotation;
2566 this->annotation_ir[i] = inst->ir;
2567 }
2568 last_native_inst = p->nr_insn;
2569 }
2570 }
2571
2572 GLboolean
2573 brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c)
2574 {
2575 struct brw_compile *p = &c->func;
2576 struct intel_context *intel = &brw->intel;
2577 GLcontext *ctx = &intel->ctx;
2578 struct brw_shader *shader = NULL;
2579 struct gl_shader_program *prog = ctx->Shader.CurrentProgram;
2580
2581 if (!prog)
2582 return GL_FALSE;
2583
2584 if (!using_new_fs)
2585 return GL_FALSE;
2586
2587 for (unsigned int i = 0; i < prog->_NumLinkedShaders; i++) {
2588 if (prog->_LinkedShaders[i]->Type == GL_FRAGMENT_SHADER) {
2589 shader = (struct brw_shader *)prog->_LinkedShaders[i];
2590 break;
2591 }
2592 }
2593 if (!shader)
2594 return GL_FALSE;
2595
2596 /* We always use 8-wide mode, at least for now. For one, flow
2597 * control only works in 8-wide. Also, when we're fragment shader
2598 * bound, we're almost always under register pressure as well, so
2599 * 8-wide would save us from the performance cliff of spilling
2600 * regs.
2601 */
2602 c->dispatch_width = 8;
2603
2604 if (INTEL_DEBUG & DEBUG_WM) {
2605 printf("GLSL IR for native fragment shader %d:\n", prog->Name);
2606 _mesa_print_ir(shader->ir, NULL);
2607 printf("\n");
2608 }
2609
2610 /* Now the main event: Visit the shader IR and generate our FS IR for it.
2611 */
2612 fs_visitor v(c, shader);
2613
2614 if (0) {
2615 v.emit_dummy_fs();
2616 } else {
2617 v.emit_interpolation_setup();
2618
2619 /* Generate FS IR for main(). (the visitor only descends into
2620 * functions called "main").
2621 */
2622 foreach_iter(exec_list_iterator, iter, *shader->ir) {
2623 ir_instruction *ir = (ir_instruction *)iter.get();
2624 v.base_ir = ir;
2625 ir->accept(&v);
2626 }
2627
2628 v.emit_fb_writes();
2629 v.assign_curb_setup();
2630 v.assign_urb_setup();
2631 if (0)
2632 v.assign_regs_trivial();
2633 else
2634 v.assign_regs();
2635 }
2636
2637 v.generate_code();
2638
2639 assert(!v.fail); /* FINISHME: Cleanly fail, tested at link time, etc. */
2640
2641 if (v.fail)
2642 return GL_FALSE;
2643
2644 if (INTEL_DEBUG & DEBUG_WM) {
2645 const char *last_annotation_string = NULL;
2646 ir_instruction *last_annotation_ir = NULL;
2647
2648 printf("Native code for fragment shader %d:\n", prog->Name);
2649 for (unsigned int i = 0; i < p->nr_insn; i++) {
2650 if (last_annotation_ir != v.annotation_ir[i]) {
2651 last_annotation_ir = v.annotation_ir[i];
2652 if (last_annotation_ir) {
2653 printf(" ");
2654 last_annotation_ir->print();
2655 printf("\n");
2656 }
2657 }
2658 if (last_annotation_string != v.annotation_string[i]) {
2659 last_annotation_string = v.annotation_string[i];
2660 if (last_annotation_string)
2661 printf(" %s\n", last_annotation_string);
2662 }
2663 brw_disasm(stdout, &p->store[i], intel->gen);
2664 }
2665 printf("\n");
2666 }
2667
2668 c->prog_data.total_grf = v.grf_used;
2669 c->prog_data.total_scratch = 0;
2670
2671 return GL_TRUE;
2672 }