2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "util/hash_table.h"
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/fbobject.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/register_allocate.h"
42 #include "program/sampler.h"
43 #include "program/hash_table.h"
44 #include "brw_context.h"
49 #include "brw_dead_control_flow.h"
50 #include "main/uniforms.h"
51 #include "brw_fs_live_variables.h"
52 #include "glsl/glsl_types.h"
55 fs_inst::init(enum opcode opcode
, const fs_reg
&dst
, fs_reg
*src
, int sources
)
57 memset(this, 0, sizeof(*this));
59 this->opcode
= opcode
;
62 this->sources
= sources
;
64 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
66 /* This will be the case for almost all instructions. */
67 this->regs_written
= 1;
69 this->writes_accumulator
= false;
72 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
)
74 fs_reg
*src
= ralloc_array(this, fs_reg
, 3);
75 init(opcode
, dst
, src
, 0);
78 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
)
80 fs_reg
*src
= ralloc_array(this, fs_reg
, 3);
82 init(opcode
, dst
, src
, 1);
85 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
88 fs_reg
*src
= ralloc_array(this, fs_reg
, 3);
91 init(opcode
, dst
, src
, 2);
94 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
95 const fs_reg
&src1
, const fs_reg
&src2
)
97 fs_reg
*src
= ralloc_array(this, fs_reg
, 3);
101 init(opcode
, dst
, src
, 3);
104 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, fs_reg src
[], int sources
)
106 init(opcode
, dst
, src
, sources
);
109 fs_inst::fs_inst(const fs_inst
&that
)
111 memcpy(this, &that
, sizeof(that
));
113 this->src
= ralloc_array(this, fs_reg
, that
.sources
);
115 for (int i
= 0; i
< that
.sources
; i
++)
116 this->src
[i
] = that
.src
[i
];
120 fs_inst::resize_sources(uint8_t num_sources
)
122 if (this->sources
!= num_sources
) {
123 this->src
= reralloc(this, this->src
, fs_reg
, num_sources
);
124 this->sources
= num_sources
;
130 fs_visitor::op(const fs_reg &dst, const fs_reg &src0) \
132 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0); \
137 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
138 const fs_reg &src1) \
140 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
143 #define ALU2_ACC(op) \
145 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
146 const fs_reg &src1) \
148 fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1);\
149 inst->writes_accumulator = true; \
155 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
156 const fs_reg &src1, const fs_reg &src2) \
158 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2);\
190 /** Gen4 predicated IF. */
192 fs_visitor::IF(enum brw_predicate predicate
)
194 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
);
195 inst
->predicate
= predicate
;
199 /** Gen6 IF with embedded comparison. */
201 fs_visitor::IF(const fs_reg
&src0
, const fs_reg
&src1
,
202 enum brw_conditional_mod condition
)
204 assert(brw
->gen
== 6);
205 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
,
206 reg_null_d
, src0
, src1
);
207 inst
->conditional_mod
= condition
;
212 * CMP: Sets the low bit of the destination channels with the result
213 * of the comparison, while the upper bits are undefined, and updates
214 * the flag register with the packed 16 bits of the result.
217 fs_visitor::CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
,
218 enum brw_conditional_mod condition
)
222 /* Take the instruction:
224 * CMP null<d> src0<f> src1<f>
226 * Original gen4 does type conversion to the destination type before
227 * comparison, producing garbage results for floating point comparisons.
228 * gen5 does the comparison on the execution type (resolved source types),
229 * so dst type doesn't matter. gen6 does comparison and then uses the
230 * result as if it was the dst type with no conversion, which happens to
231 * mostly work out for float-interpreted-as-int since our comparisons are
235 dst
.type
= src0
.type
;
236 if (dst
.file
== HW_REG
)
237 dst
.fixed_hw_reg
.type
= dst
.type
;
240 resolve_ud_negate(&src0
);
241 resolve_ud_negate(&src1
);
243 inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_CMP
, dst
, src0
, src1
);
244 inst
->conditional_mod
= condition
;
250 fs_visitor::LOAD_PAYLOAD(const fs_reg
&dst
, fs_reg
*src
, int sources
)
252 fs_inst
*inst
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
, dst
, src
,
254 inst
->regs_written
= sources
;
260 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_reg
&dst
,
261 const fs_reg
&surf_index
,
262 const fs_reg
&varying_offset
,
263 uint32_t const_offset
)
265 exec_list instructions
;
268 /* We have our constant surface use a pitch of 4 bytes, so our index can
269 * be any component of a vector, and then we load 4 contiguous
270 * components starting from that.
272 * We break down the const_offset to a portion added to the variable
273 * offset and a portion done using reg_offset, which means that if you
274 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
275 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
276 * CSE can later notice that those loads are all the same and eliminate
277 * the redundant ones.
279 fs_reg vec4_offset
= fs_reg(this, glsl_type::int_type
);
280 instructions
.push_tail(ADD(vec4_offset
,
281 varying_offset
, const_offset
& ~3));
284 if (brw
->gen
== 4 && dispatch_width
== 8) {
285 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
286 * u, v, r) as parameters, or we can just use the SIMD16 message
287 * consisting of (header, u). We choose the second, at the cost of a
288 * longer return length.
295 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
297 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
298 fs_reg vec4_result
= fs_reg(GRF
, virtual_grf_alloc(4 * scale
), dst
.type
);
299 inst
= new(mem_ctx
) fs_inst(op
, vec4_result
, surf_index
, vec4_offset
);
300 inst
->regs_written
= 4 * scale
;
301 instructions
.push_tail(inst
);
305 inst
->header_present
= true;
309 inst
->mlen
= 1 + dispatch_width
/ 8;
312 vec4_result
.reg_offset
+= (const_offset
& 3) * scale
;
313 instructions
.push_tail(MOV(dst
, vec4_result
));
319 * A helper for MOV generation for fixing up broken hardware SEND dependency
323 fs_visitor::DEP_RESOLVE_MOV(int grf
)
325 fs_inst
*inst
= MOV(brw_null_reg(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
328 inst
->annotation
= "send dependency resolve";
330 /* The caller always wants uncompressed to emit the minimal extra
331 * dependencies, and to avoid having to deal with aligning its regs to 2.
333 inst
->force_uncompressed
= true;
339 fs_inst::equals(fs_inst
*inst
) const
341 return (opcode
== inst
->opcode
&&
342 dst
.equals(inst
->dst
) &&
343 src
[0].equals(inst
->src
[0]) &&
344 src
[1].equals(inst
->src
[1]) &&
345 src
[2].equals(inst
->src
[2]) &&
346 saturate
== inst
->saturate
&&
347 predicate
== inst
->predicate
&&
348 conditional_mod
== inst
->conditional_mod
&&
349 mlen
== inst
->mlen
&&
350 base_mrf
== inst
->base_mrf
&&
351 target
== inst
->target
&&
353 header_present
== inst
->header_present
&&
354 shadow_compare
== inst
->shadow_compare
&&
355 offset
== inst
->offset
);
359 fs_inst::overwrites_reg(const fs_reg
®
) const
361 return (reg
.file
== dst
.file
&&
362 reg
.reg
== dst
.reg
&&
363 reg
.reg_offset
>= dst
.reg_offset
&&
364 reg
.reg_offset
< dst
.reg_offset
+ regs_written
);
368 fs_inst::is_send_from_grf() const
370 return (opcode
== FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
||
371 opcode
== SHADER_OPCODE_SHADER_TIME_ADD
||
372 opcode
== FS_OPCODE_INTERPOLATE_AT_CENTROID
||
373 opcode
== FS_OPCODE_INTERPOLATE_AT_SAMPLE
||
374 opcode
== FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
||
375 opcode
== FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
||
376 (opcode
== FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
&&
377 src
[1].file
== GRF
) ||
378 (is_tex() && src
[0].file
== GRF
));
382 fs_inst::can_do_source_mods(struct brw_context
*brw
)
384 if (brw
->gen
== 6 && is_math())
387 if (is_send_from_grf())
390 if (!backend_instruction::can_do_source_mods())
399 memset(this, 0, sizeof(*this));
403 /** Generic unset register constructor. */
407 this->file
= BAD_FILE
;
410 /** Immediate value constructor. */
411 fs_reg::fs_reg(float f
)
415 this->type
= BRW_REGISTER_TYPE_F
;
416 this->fixed_hw_reg
.dw1
.f
= f
;
419 /** Immediate value constructor. */
420 fs_reg::fs_reg(int32_t i
)
424 this->type
= BRW_REGISTER_TYPE_D
;
425 this->fixed_hw_reg
.dw1
.d
= i
;
428 /** Immediate value constructor. */
429 fs_reg::fs_reg(uint32_t u
)
433 this->type
= BRW_REGISTER_TYPE_UD
;
434 this->fixed_hw_reg
.dw1
.ud
= u
;
437 /** Fixed brw_reg. */
438 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
442 this->fixed_hw_reg
= fixed_hw_reg
;
443 this->type
= fixed_hw_reg
.type
;
447 fs_reg::equals(const fs_reg
&r
) const
449 return (file
== r
.file
&&
451 reg_offset
== r
.reg_offset
&&
452 subreg_offset
== r
.subreg_offset
&&
454 negate
== r
.negate
&&
456 !reladdr
&& !r
.reladdr
&&
457 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
458 sizeof(fixed_hw_reg
)) == 0 &&
463 fs_reg::apply_stride(unsigned stride
)
465 assert((this->stride
* stride
) <= 4 &&
466 (is_power_of_two(stride
) || stride
== 0) &&
467 file
!= HW_REG
&& file
!= IMM
);
468 this->stride
*= stride
;
473 fs_reg::set_smear(unsigned subreg
)
475 assert(file
!= HW_REG
&& file
!= IMM
);
476 subreg_offset
= subreg
* type_sz(type
);
482 fs_reg::is_contiguous() const
488 fs_reg::is_valid_3src() const
490 return file
== GRF
|| file
== UNIFORM
;
494 fs_visitor::type_size(const struct glsl_type
*type
)
496 unsigned int size
, i
;
498 switch (type
->base_type
) {
501 case GLSL_TYPE_FLOAT
:
503 return type
->components();
504 case GLSL_TYPE_ARRAY
:
505 return type_size(type
->fields
.array
) * type
->length
;
506 case GLSL_TYPE_STRUCT
:
508 for (i
= 0; i
< type
->length
; i
++) {
509 size
+= type_size(type
->fields
.structure
[i
].type
);
512 case GLSL_TYPE_SAMPLER
:
513 /* Samplers take up no register space, since they're baked in at
517 case GLSL_TYPE_ATOMIC_UINT
:
519 case GLSL_TYPE_IMAGE
:
521 case GLSL_TYPE_ERROR
:
522 case GLSL_TYPE_INTERFACE
:
523 unreachable("not reached");
530 fs_visitor::get_timestamp()
532 assert(brw
->gen
>= 7);
534 fs_reg ts
= fs_reg(retype(brw_vec1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
537 BRW_REGISTER_TYPE_UD
));
539 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
541 fs_inst
*mov
= emit(MOV(dst
, ts
));
542 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
543 * even if it's not enabled in the dispatch.
545 mov
->force_writemask_all
= true;
546 mov
->force_uncompressed
= true;
548 /* The caller wants the low 32 bits of the timestamp. Since it's running
549 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
550 * which is plenty of time for our purposes. It is identical across the
551 * EUs, but since it's tracking GPU core speed it will increment at a
552 * varying rate as render P-states change.
554 * The caller could also check if render P-states have changed (or anything
555 * else that might disrupt timing) by setting smear to 2 and checking if
556 * that field is != 0.
564 fs_visitor::emit_shader_time_begin()
566 current_annotation
= "shader time start";
567 shader_start_time
= get_timestamp();
571 fs_visitor::emit_shader_time_end()
573 current_annotation
= "shader time end";
575 enum shader_time_shader_type type
, written_type
, reset_type
;
576 if (dispatch_width
== 8) {
578 written_type
= ST_FS8_WRITTEN
;
579 reset_type
= ST_FS8_RESET
;
581 assert(dispatch_width
== 16);
583 written_type
= ST_FS16_WRITTEN
;
584 reset_type
= ST_FS16_RESET
;
587 fs_reg shader_end_time
= get_timestamp();
589 /* Check that there weren't any timestamp reset events (assuming these
590 * were the only two timestamp reads that happened).
592 fs_reg reset
= shader_end_time
;
594 fs_inst
*test
= emit(AND(reg_null_d
, reset
, fs_reg(1u)));
595 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
596 emit(IF(BRW_PREDICATE_NORMAL
));
598 push_force_uncompressed();
599 fs_reg start
= shader_start_time
;
601 fs_reg diff
= fs_reg(this, glsl_type::uint_type
);
602 emit(ADD(diff
, start
, shader_end_time
));
604 /* If there were no instructions between the two timestamp gets, the diff
605 * is 2 cycles. Remove that overhead, so I can forget about that when
606 * trying to determine the time taken for single instructions.
608 emit(ADD(diff
, diff
, fs_reg(-2u)));
610 emit_shader_time_write(type
, diff
);
611 emit_shader_time_write(written_type
, fs_reg(1u));
612 emit(BRW_OPCODE_ELSE
);
613 emit_shader_time_write(reset_type
, fs_reg(1u));
614 emit(BRW_OPCODE_ENDIF
);
616 pop_force_uncompressed();
620 fs_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
623 int shader_time_index
=
624 brw_get_shader_time_index(brw
, shader_prog
, &fp
->Base
, type
);
625 fs_reg offset
= fs_reg(shader_time_index
* SHADER_TIME_STRIDE
);
628 if (dispatch_width
== 8)
629 payload
= fs_reg(this, glsl_type::uvec2_type
);
631 payload
= fs_reg(this, glsl_type::uint_type
);
633 emit(new(mem_ctx
) fs_inst(SHADER_OPCODE_SHADER_TIME_ADD
,
634 fs_reg(), payload
, offset
, value
));
638 fs_visitor::vfail(const char *format
, va_list va
)
647 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
648 msg
= ralloc_asprintf(mem_ctx
, "FS compile failed: %s\n", msg
);
650 this->fail_msg
= msg
;
652 if (INTEL_DEBUG
& DEBUG_WM
) {
653 fprintf(stderr
, "%s", msg
);
658 fs_visitor::fail(const char *format
, ...)
662 va_start(va
, format
);
668 * Mark this program as impossible to compile in SIMD16 mode.
670 * During the SIMD8 compile (which happens first), we can detect and flag
671 * things that are unsupported in SIMD16 mode, so the compiler can skip
672 * the SIMD16 compile altogether.
674 * During a SIMD16 compile (if one happens anyway), this just calls fail().
677 fs_visitor::no16(const char *format
, ...)
681 va_start(va
, format
);
683 if (dispatch_width
== 16) {
686 simd16_unsupported
= true;
688 if (brw
->perf_debug
) {
690 ralloc_vasprintf_append(&no16_msg
, format
, va
);
692 no16_msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
700 fs_visitor::emit(enum opcode opcode
)
702 return emit(new(mem_ctx
) fs_inst(opcode
));
706 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
)
708 return emit(new(mem_ctx
) fs_inst(opcode
, dst
));
712 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
)
714 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
));
718 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
721 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
, src1
));
725 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
726 const fs_reg
&src1
, const fs_reg
&src2
)
728 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
, src1
, src2
));
732 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
,
733 fs_reg src
[], int sources
)
735 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src
, sources
));
739 fs_visitor::push_force_uncompressed()
741 force_uncompressed_stack
++;
745 fs_visitor::pop_force_uncompressed()
747 force_uncompressed_stack
--;
748 assert(force_uncompressed_stack
>= 0);
752 * Returns true if the instruction has a flag that means it won't
753 * update an entire destination register.
755 * For example, dead code elimination and live variable analysis want to know
756 * when a write to a variable screens off any preceding values that were in
760 fs_inst::is_partial_write() const
762 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
763 this->force_uncompressed
||
764 this->force_sechalf
|| !this->dst
.is_contiguous());
768 fs_inst::regs_read(fs_visitor
*v
, int arg
) const
770 if (is_tex() && arg
== 0 && src
[0].file
== GRF
) {
771 if (v
->dispatch_width
== 16)
772 return (mlen
+ 1) / 2;
780 fs_inst::reads_flag() const
786 fs_inst::writes_flag() const
788 return (conditional_mod
&& opcode
!= BRW_OPCODE_SEL
) ||
789 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
793 * Returns how many MRFs an FS opcode will write over.
795 * Note that this is not the 0 or 1 implied writes in an actual gen
796 * instruction -- the FS opcodes often generate MOVs in addition.
799 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
804 if (inst
->base_mrf
== -1)
807 switch (inst
->opcode
) {
808 case SHADER_OPCODE_RCP
:
809 case SHADER_OPCODE_RSQ
:
810 case SHADER_OPCODE_SQRT
:
811 case SHADER_OPCODE_EXP2
:
812 case SHADER_OPCODE_LOG2
:
813 case SHADER_OPCODE_SIN
:
814 case SHADER_OPCODE_COS
:
815 return 1 * dispatch_width
/ 8;
816 case SHADER_OPCODE_POW
:
817 case SHADER_OPCODE_INT_QUOTIENT
:
818 case SHADER_OPCODE_INT_REMAINDER
:
819 return 2 * dispatch_width
/ 8;
820 case SHADER_OPCODE_TEX
:
822 case SHADER_OPCODE_TXD
:
823 case SHADER_OPCODE_TXF
:
824 case SHADER_OPCODE_TXF_CMS
:
825 case SHADER_OPCODE_TXF_MCS
:
826 case SHADER_OPCODE_TG4
:
827 case SHADER_OPCODE_TG4_OFFSET
:
828 case SHADER_OPCODE_TXL
:
829 case SHADER_OPCODE_TXS
:
830 case SHADER_OPCODE_LOD
:
832 case FS_OPCODE_FB_WRITE
:
834 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
835 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
837 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
839 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
841 case SHADER_OPCODE_UNTYPED_ATOMIC
:
842 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
843 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
844 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
845 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
846 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
849 unreachable("not reached");
854 fs_visitor::virtual_grf_alloc(int size
)
856 if (virtual_grf_array_size
<= virtual_grf_count
) {
857 if (virtual_grf_array_size
== 0)
858 virtual_grf_array_size
= 16;
860 virtual_grf_array_size
*= 2;
861 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
862 virtual_grf_array_size
);
864 virtual_grf_sizes
[virtual_grf_count
] = size
;
865 return virtual_grf_count
++;
868 /** Fixed HW reg constructor. */
869 fs_reg::fs_reg(enum register_file file
, int reg
)
874 this->type
= BRW_REGISTER_TYPE_F
;
877 /** Fixed HW reg constructor. */
878 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
)
886 /** Automatic reg constructor. */
887 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
892 this->reg
= v
->virtual_grf_alloc(v
->type_size(type
));
893 this->reg_offset
= 0;
894 this->type
= brw_type_for_base_type(type
);
898 fs_visitor::variable_storage(ir_variable
*var
)
900 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
904 import_uniforms_callback(const void *key
,
908 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
909 const fs_reg
*reg
= (const fs_reg
*)data
;
911 if (reg
->file
!= UNIFORM
)
914 hash_table_insert(dst_ht
, data
, key
);
917 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
918 * This brings in those uniform definitions
921 fs_visitor::import_uniforms(fs_visitor
*v
)
923 hash_table_call_foreach(v
->variable_ht
,
924 import_uniforms_callback
,
926 this->push_constant_loc
= v
->push_constant_loc
;
927 this->pull_constant_loc
= v
->pull_constant_loc
;
928 this->uniforms
= v
->uniforms
;
929 this->param_size
= v
->param_size
;
932 /* Our support for uniforms is piggy-backed on the struct
933 * gl_fragment_program, because that's where the values actually
934 * get stored, rather than in some global gl_shader_program uniform
938 fs_visitor::setup_uniform_values(ir_variable
*ir
)
940 int namelen
= strlen(ir
->name
);
942 /* The data for our (non-builtin) uniforms is stored in a series of
943 * gl_uniform_driver_storage structs for each subcomponent that
944 * glGetUniformLocation() could name. We know it's been set up in the same
945 * order we'd walk the type, so walk the list of storage and find anything
946 * with our name, or the prefix of a component that starts with our name.
948 unsigned params_before
= uniforms
;
949 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
950 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
952 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
953 (storage
->name
[namelen
] != 0 &&
954 storage
->name
[namelen
] != '.' &&
955 storage
->name
[namelen
] != '[')) {
959 unsigned slots
= storage
->type
->component_slots();
960 if (storage
->array_elements
)
961 slots
*= storage
->array_elements
;
963 for (unsigned i
= 0; i
< slots
; i
++) {
964 stage_prog_data
->param
[uniforms
++] = &storage
->storage
[i
].f
;
968 /* Make sure we actually initialized the right amount of stuff here. */
969 assert(params_before
+ ir
->type
->component_slots() == uniforms
);
974 /* Our support for builtin uniforms is even scarier than non-builtin.
975 * It sits on top of the PROG_STATE_VAR parameters that are
976 * automatically updated from GL context state.
979 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
981 const ir_state_slot
*const slots
= ir
->state_slots
;
982 assert(ir
->state_slots
!= NULL
);
984 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
985 /* This state reference has already been setup by ir_to_mesa, but we'll
986 * get the same index back here.
988 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
989 (gl_state_index
*)slots
[i
].tokens
);
991 /* Add each of the unique swizzles of the element as a parameter.
992 * This'll end up matching the expected layout of the
993 * array/matrix/structure we're trying to fill in.
996 for (unsigned int j
= 0; j
< 4; j
++) {
997 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
998 if (swiz
== last_swiz
)
1002 stage_prog_data
->param
[uniforms
++] =
1003 &fp
->Base
.Parameters
->ParameterValues
[index
][swiz
].f
;
1009 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
1011 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1013 bool flip
= !ir
->data
.origin_upper_left
^ key
->render_to_fbo
;
1015 /* gl_FragCoord.x */
1016 if (ir
->data
.pixel_center_integer
) {
1017 emit(MOV(wpos
, this->pixel_x
));
1019 emit(ADD(wpos
, this->pixel_x
, fs_reg(0.5f
)));
1023 /* gl_FragCoord.y */
1024 if (!flip
&& ir
->data
.pixel_center_integer
) {
1025 emit(MOV(wpos
, this->pixel_y
));
1027 fs_reg pixel_y
= this->pixel_y
;
1028 float offset
= (ir
->data
.pixel_center_integer
? 0.0 : 0.5);
1031 pixel_y
.negate
= true;
1032 offset
+= key
->drawable_height
- 1.0;
1035 emit(ADD(wpos
, pixel_y
, fs_reg(offset
)));
1039 /* gl_FragCoord.z */
1040 if (brw
->gen
>= 6) {
1041 emit(MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0))));
1043 emit(FS_OPCODE_LINTERP
, wpos
,
1044 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1045 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1046 interp_reg(VARYING_SLOT_POS
, 2));
1050 /* gl_FragCoord.w: Already set up in emit_interpolation */
1051 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
1057 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1058 glsl_interp_qualifier interpolation_mode
,
1059 bool is_centroid
, bool is_sample
)
1061 brw_wm_barycentric_interp_mode barycoord_mode
;
1062 if (brw
->gen
>= 6) {
1064 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1065 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1067 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1068 } else if (is_sample
) {
1069 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1070 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1072 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1074 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1075 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1077 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1080 /* On Ironlake and below, there is only one interpolation mode.
1081 * Centroid interpolation doesn't mean anything on this hardware --
1082 * there is no multisampling.
1084 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1086 return emit(FS_OPCODE_LINTERP
, attr
,
1087 this->delta_x
[barycoord_mode
],
1088 this->delta_y
[barycoord_mode
], interp
);
1092 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
1094 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1095 reg
->type
= brw_type_for_base_type(ir
->type
->get_scalar_type());
1098 unsigned int array_elements
;
1099 const glsl_type
*type
;
1101 if (ir
->type
->is_array()) {
1102 array_elements
= ir
->type
->length
;
1103 if (array_elements
== 0) {
1104 fail("dereferenced array '%s' has length 0\n", ir
->name
);
1106 type
= ir
->type
->fields
.array
;
1112 glsl_interp_qualifier interpolation_mode
=
1113 ir
->determine_interpolation_mode(key
->flat_shade
);
1115 int location
= ir
->data
.location
;
1116 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1117 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1118 if (prog_data
->urb_setup
[location
] == -1) {
1119 /* If there's no incoming setup data for this slot, don't
1120 * emit interpolation for it.
1122 attr
.reg_offset
+= type
->vector_elements
;
1127 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1128 /* Constant interpolation (flat shading) case. The SF has
1129 * handed us defined values in only the constant offset
1130 * field of the setup reg.
1132 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1133 struct brw_reg interp
= interp_reg(location
, k
);
1134 interp
= suboffset(interp
, 3);
1135 interp
.type
= reg
->type
;
1136 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1140 /* Smooth/noperspective interpolation case. */
1141 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1142 struct brw_reg interp
= interp_reg(location
, k
);
1143 if (brw
->needs_unlit_centroid_workaround
&& ir
->data
.centroid
) {
1144 /* Get the pixel/sample mask into f0 so that we know
1145 * which pixels are lit. Then, for each channel that is
1146 * unlit, replace the centroid data with non-centroid
1149 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1152 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1154 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1155 inst
->predicate_inverse
= true;
1157 inst
->no_dd_clear
= true;
1159 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1160 ir
->data
.centroid
&& !key
->persample_shading
,
1161 ir
->data
.sample
|| key
->persample_shading
);
1162 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1163 inst
->predicate_inverse
= false;
1165 inst
->no_dd_check
= true;
1168 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1169 ir
->data
.centroid
&& !key
->persample_shading
,
1170 ir
->data
.sample
|| key
->persample_shading
);
1172 if (brw
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1173 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
1187 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
1189 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1191 /* The frontfacing comes in as a bit in the thread payload. */
1192 if (brw
->gen
>= 6) {
1193 emit(BRW_OPCODE_ASR
, *reg
,
1194 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1196 emit(BRW_OPCODE_NOT
, *reg
, *reg
);
1197 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1));
1199 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
1200 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
1203 emit(CMP(*reg
, fs_reg(r1_6ud
), fs_reg(1u << 31), BRW_CONDITIONAL_L
));
1204 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u));
1211 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1213 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1215 if (key
->compute_pos_offset
) {
1216 /* Convert int_sample_pos to floating point */
1217 emit(MOV(dst
, int_sample_pos
));
1218 /* Scale to the range [0, 1] */
1219 emit(MUL(dst
, dst
, fs_reg(1 / 16.0f
)));
1222 /* From ARB_sample_shading specification:
1223 * "When rendering to a non-multisample buffer, or if multisample
1224 * rasterization is disabled, gl_SamplePosition will always be
1227 emit(MOV(dst
, fs_reg(0.5f
)));
1232 fs_visitor::emit_samplepos_setup(ir_variable
*ir
)
1234 assert(brw
->gen
>= 6);
1235 assert(ir
->type
== glsl_type::vec2_type
);
1237 this->current_annotation
= "compute sample position";
1238 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1240 fs_reg int_sample_x
= fs_reg(this, glsl_type::int_type
);
1241 fs_reg int_sample_y
= fs_reg(this, glsl_type::int_type
);
1243 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1244 * mode will be enabled.
1246 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1247 * R31.1:0 Position Offset X/Y for Slot[3:0]
1248 * R31.3:2 Position Offset X/Y for Slot[7:4]
1251 * The X, Y sample positions come in as bytes in thread payload. So, read
1252 * the positions using vstride=16, width=8, hstride=2.
1254 struct brw_reg sample_pos_reg
=
1255 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1256 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1258 fs_inst
*inst
= emit(MOV(int_sample_x
, fs_reg(sample_pos_reg
)));
1259 if (dispatch_width
== 16) {
1260 inst
->force_uncompressed
= true;
1261 inst
= emit(MOV(half(int_sample_x
, 1),
1262 fs_reg(suboffset(sample_pos_reg
, 16))));
1263 inst
->force_sechalf
= true;
1265 /* Compute gl_SamplePosition.x */
1266 compute_sample_position(pos
, int_sample_x
);
1268 inst
= emit(MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1))));
1269 if (dispatch_width
== 16) {
1270 inst
->force_uncompressed
= true;
1271 inst
= emit(MOV(half(int_sample_y
, 1),
1272 fs_reg(suboffset(sample_pos_reg
, 17))));
1273 inst
->force_sechalf
= true;
1275 /* Compute gl_SamplePosition.y */
1276 compute_sample_position(pos
, int_sample_y
);
1281 fs_visitor::emit_sampleid_setup(ir_variable
*ir
)
1283 assert(brw
->gen
>= 6);
1285 this->current_annotation
= "compute sample id";
1286 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1288 if (key
->compute_sample_id
) {
1289 fs_reg t1
= fs_reg(this, glsl_type::int_type
);
1290 fs_reg t2
= fs_reg(this, glsl_type::int_type
);
1291 t2
.type
= BRW_REGISTER_TYPE_UW
;
1293 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1294 * 8x multisampling, subspan 0 will represent sample N (where N
1295 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1296 * 7. We can find the value of N by looking at R0.0 bits 7:6
1297 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1298 * (since samples are always delivered in pairs). That is, we
1299 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1300 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1301 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1302 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1303 * populating a temporary variable with the sequence (0, 1, 2, 3),
1304 * and then reading from it using vstride=1, width=4, hstride=0.
1305 * These computations hold good for 4x multisampling as well.
1307 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1308 * the first four slots are sample 0 of subspan 0; the next four
1309 * are sample 1 of subspan 0; the third group is sample 0 of
1310 * subspan 1, and finally sample 1 of subspan 1.
1313 inst
= emit(BRW_OPCODE_AND
, t1
,
1314 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1316 inst
->force_writemask_all
= true;
1317 inst
= emit(BRW_OPCODE_SHR
, t1
, t1
, fs_reg(5));
1318 inst
->force_writemask_all
= true;
1319 /* This works for both SIMD8 and SIMD16 */
1320 inst
= emit(MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210)));
1321 inst
->force_writemask_all
= true;
1322 /* This special instruction takes care of setting vstride=1,
1323 * width=4, hstride=0 of t2 during an ADD instruction.
1325 emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1327 /* As per GL_ARB_sample_shading specification:
1328 * "When rendering to a non-multisample buffer, or if multisample
1329 * rasterization is disabled, gl_SampleID will always be zero."
1331 emit(BRW_OPCODE_MOV
, *reg
, fs_reg(0));
1338 fs_visitor::fix_math_operand(fs_reg src
)
1340 /* Can't do hstride == 0 args on gen6 math, so expand it out. We
1341 * might be able to do better by doing execsize = 1 math and then
1342 * expanding that result out, but we would need to be careful with
1345 * The hardware ignores source modifiers (negate and abs) on math
1346 * instructions, so we also move to a temp to set those up.
1348 if (brw
->gen
== 6 && src
.file
!= UNIFORM
&& src
.file
!= IMM
&&
1349 !src
.abs
&& !src
.negate
)
1352 /* Gen7 relaxes most of the above restrictions, but still can't use IMM
1355 if (brw
->gen
>= 7 && src
.file
!= IMM
)
1358 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
1359 expanded
.type
= src
.type
;
1360 emit(BRW_OPCODE_MOV
, expanded
, src
);
1365 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src
)
1368 case SHADER_OPCODE_RCP
:
1369 case SHADER_OPCODE_RSQ
:
1370 case SHADER_OPCODE_SQRT
:
1371 case SHADER_OPCODE_EXP2
:
1372 case SHADER_OPCODE_LOG2
:
1373 case SHADER_OPCODE_SIN
:
1374 case SHADER_OPCODE_COS
:
1377 unreachable("not reached: bad math opcode");
1380 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
1381 * might be able to do better by doing execsize = 1 math and then
1382 * expanding that result out, but we would need to be careful with
1385 * Gen 6 hardware ignores source modifiers (negate and abs) on math
1386 * instructions, so we also move to a temp to set those up.
1388 if (brw
->gen
== 6 || brw
->gen
== 7)
1389 src
= fix_math_operand(src
);
1391 fs_inst
*inst
= emit(opcode
, dst
, src
);
1395 inst
->mlen
= dispatch_width
/ 8;
1402 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
1408 case SHADER_OPCODE_INT_QUOTIENT
:
1409 case SHADER_OPCODE_INT_REMAINDER
:
1411 no16("SIMD16 INTDIV unsupported\n");
1413 case SHADER_OPCODE_POW
:
1416 unreachable("not reached: unsupported binary math opcode.");
1419 if (brw
->gen
>= 8) {
1420 inst
= emit(opcode
, dst
, src0
, src1
);
1421 } else if (brw
->gen
>= 6) {
1422 src0
= fix_math_operand(src0
);
1423 src1
= fix_math_operand(src1
);
1425 inst
= emit(opcode
, dst
, src0
, src1
);
1427 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
1428 * "Message Payload":
1430 * "Operand0[7]. For the INT DIV functions, this operand is the
1433 * "Operand1[7]. For the INT DIV functions, this operand is the
1436 bool is_int_div
= opcode
!= SHADER_OPCODE_POW
;
1437 fs_reg
&op0
= is_int_div
? src1
: src0
;
1438 fs_reg
&op1
= is_int_div
? src0
: src1
;
1440 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1, op1
.type
), op1
);
1441 inst
= emit(opcode
, dst
, op0
, reg_null_f
);
1443 inst
->base_mrf
= base_mrf
;
1444 inst
->mlen
= 2 * dispatch_width
/ 8;
1450 fs_visitor::assign_curb_setup()
1452 if (dispatch_width
== 8) {
1453 prog_data
->base
.dispatch_grf_start_reg
= payload
.num_regs
;
1455 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1458 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1460 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1461 foreach_in_list(fs_inst
, inst
, &instructions
) {
1462 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1463 if (inst
->src
[i
].file
== UNIFORM
) {
1464 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1466 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1467 constant_nr
= push_constant_loc
[uniform_nr
];
1469 /* Section 5.11 of the OpenGL 4.1 spec says:
1470 * "Out-of-bounds reads return undefined values, which include
1471 * values from other variables of the active program or zero."
1472 * Just return the first push constant.
1477 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1481 inst
->src
[i
].file
= HW_REG
;
1482 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1483 retype(brw_reg
, inst
->src
[i
].type
),
1484 inst
->src
[i
].subreg_offset
);
1491 fs_visitor::calculate_urb_setup()
1493 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1494 prog_data
->urb_setup
[i
] = -1;
1498 /* Figure out where each of the incoming setup attributes lands. */
1499 if (brw
->gen
>= 6) {
1500 if (_mesa_bitcount_64(fp
->Base
.InputsRead
&
1501 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1502 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1503 * first 16 varying inputs, so we can put them wherever we want.
1504 * Just put them in order.
1506 * This is useful because it means that (a) inputs not used by the
1507 * fragment shader won't take up valuable register space, and (b) we
1508 * won't have to recompile the fragment shader if it gets paired with
1509 * a different vertex (or geometry) shader.
1511 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1512 if (fp
->Base
.InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1513 BITFIELD64_BIT(i
)) {
1514 prog_data
->urb_setup
[i
] = urb_next
++;
1518 /* We have enough input varyings that the SF/SBE pipeline stage can't
1519 * arbitrarily rearrange them to suit our whim; we have to put them
1520 * in an order that matches the output of the previous pipeline stage
1521 * (geometry or vertex shader).
1523 struct brw_vue_map prev_stage_vue_map
;
1524 brw_compute_vue_map(brw
, &prev_stage_vue_map
,
1525 key
->input_slots_valid
);
1526 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1527 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1528 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1530 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1531 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1534 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1535 (fp
->Base
.InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1536 BITFIELD64_BIT(varying
))) {
1537 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1540 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1543 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1544 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1545 /* Point size is packed into the header, not as a general attribute */
1546 if (i
== VARYING_SLOT_PSIZ
)
1549 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1550 /* The back color slot is skipped when the front color is
1551 * also written to. In addition, some slots can be
1552 * written in the vertex shader and not read in the
1553 * fragment shader. So the register number must always be
1554 * incremented, mapped or not.
1556 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1557 prog_data
->urb_setup
[i
] = urb_next
;
1563 * It's a FS only attribute, and we did interpolation for this attribute
1564 * in SF thread. So, count it here, too.
1566 * See compile_sf_prog() for more info.
1568 if (fp
->Base
.InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1569 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1572 prog_data
->num_varying_inputs
= urb_next
;
1576 fs_visitor::assign_urb_setup()
1578 int urb_start
= payload
.num_regs
+ prog_data
->curb_read_length
;
1580 /* Offset all the urb_setup[] index by the actual position of the
1581 * setup regs, now that the location of the constants has been chosen.
1583 foreach_in_list(fs_inst
, inst
, &instructions
) {
1584 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1585 assert(inst
->src
[2].file
== HW_REG
);
1586 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
1589 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1590 assert(inst
->src
[0].file
== HW_REG
);
1591 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1595 /* Each attribute is 4 setup channels, each of which is half a reg. */
1596 this->first_non_payload_grf
=
1597 urb_start
+ prog_data
->num_varying_inputs
* 2;
1601 * Split large virtual GRFs into separate components if we can.
1603 * This is mostly duplicated with what brw_fs_vector_splitting does,
1604 * but that's really conservative because it's afraid of doing
1605 * splitting that doesn't result in real progress after the rest of
1606 * the optimization phases, which would cause infinite looping in
1607 * optimization. We can do it once here, safely. This also has the
1608 * opportunity to split interpolated values, or maybe even uniforms,
1609 * which we don't have at the IR level.
1611 * We want to split, because virtual GRFs are what we register
1612 * allocate and spill (due to contiguousness requirements for some
1613 * instructions), and they're what we naturally generate in the
1614 * codegen process, but most virtual GRFs don't actually need to be
1615 * contiguous sets of GRFs. If we split, we'll end up with reduced
1616 * live intervals and better dead code elimination and coalescing.
1619 fs_visitor::split_virtual_grfs()
1621 int num_vars
= this->virtual_grf_count
;
1622 bool split_grf
[num_vars
];
1623 int new_virtual_grf
[num_vars
];
1625 /* Try to split anything > 0 sized. */
1626 for (int i
= 0; i
< num_vars
; i
++) {
1627 if (this->virtual_grf_sizes
[i
] != 1)
1628 split_grf
[i
] = true;
1630 split_grf
[i
] = false;
1634 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
) {
1635 /* PLN opcodes rely on the delta_xy being contiguous. We only have to
1636 * check this for BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because prior to
1637 * Gen6, that was the only supported interpolation mode, and since Gen6,
1638 * delta_x and delta_y are in fixed hardware registers.
1640 split_grf
[this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
] =
1644 foreach_in_list(fs_inst
, inst
, &instructions
) {
1645 /* If there's a SEND message that requires contiguous destination
1646 * registers, no splitting is allowed.
1648 if (inst
->regs_written
> 1) {
1649 split_grf
[inst
->dst
.reg
] = false;
1652 /* If we're sending from a GRF, don't split it, on the assumption that
1653 * the send is reading the whole thing.
1655 if (inst
->is_send_from_grf()) {
1656 for (int i
= 0; i
< inst
->sources
; i
++) {
1657 if (inst
->src
[i
].file
== GRF
) {
1658 split_grf
[inst
->src
[i
].reg
] = false;
1664 /* Allocate new space for split regs. Note that the virtual
1665 * numbers will be contiguous.
1667 for (int i
= 0; i
< num_vars
; i
++) {
1669 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1670 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1671 int reg
= virtual_grf_alloc(1);
1672 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1675 this->virtual_grf_sizes
[i
] = 1;
1679 foreach_in_list(fs_inst
, inst
, &instructions
) {
1680 if (inst
->dst
.file
== GRF
&&
1681 split_grf
[inst
->dst
.reg
] &&
1682 inst
->dst
.reg_offset
!= 0) {
1683 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1684 inst
->dst
.reg_offset
- 1);
1685 inst
->dst
.reg_offset
= 0;
1687 for (int i
= 0; i
< inst
->sources
; i
++) {
1688 if (inst
->src
[i
].file
== GRF
&&
1689 split_grf
[inst
->src
[i
].reg
] &&
1690 inst
->src
[i
].reg_offset
!= 0) {
1691 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1692 inst
->src
[i
].reg_offset
- 1);
1693 inst
->src
[i
].reg_offset
= 0;
1697 invalidate_live_intervals();
1701 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1703 * During code generation, we create tons of temporary variables, many of
1704 * which get immediately killed and are never used again. Yet, in later
1705 * optimization and analysis passes, such as compute_live_intervals, we need
1706 * to loop over all the virtual GRFs. Compacting them can save a lot of
1710 fs_visitor::compact_virtual_grfs()
1712 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1715 /* Mark which virtual GRFs are used, and count how many. */
1716 int remap_table
[this->virtual_grf_count
];
1717 memset(remap_table
, -1, sizeof(remap_table
));
1719 foreach_in_list(const fs_inst
, inst
, &instructions
) {
1720 if (inst
->dst
.file
== GRF
)
1721 remap_table
[inst
->dst
.reg
] = 0;
1723 for (int i
= 0; i
< inst
->sources
; i
++) {
1724 if (inst
->src
[i
].file
== GRF
)
1725 remap_table
[inst
->src
[i
].reg
] = 0;
1729 /* Compact the GRF arrays. */
1731 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
1732 if (remap_table
[i
] != -1) {
1733 remap_table
[i
] = new_index
;
1734 virtual_grf_sizes
[new_index
] = virtual_grf_sizes
[i
];
1735 invalidate_live_intervals();
1740 this->virtual_grf_count
= new_index
;
1742 /* Patch all the instructions to use the newly renumbered registers */
1743 foreach_in_list(fs_inst
, inst
, &instructions
) {
1744 if (inst
->dst
.file
== GRF
)
1745 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1747 for (int i
= 0; i
< inst
->sources
; i
++) {
1748 if (inst
->src
[i
].file
== GRF
)
1749 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1753 /* Patch all the references to delta_x/delta_y, since they're used in
1754 * register allocation.
1756 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_x
); i
++) {
1757 if (delta_x
[i
].file
== GRF
&& remap_table
[delta_x
[i
].reg
] != -1) {
1758 delta_x
[i
].reg
= remap_table
[delta_x
[i
].reg
];
1761 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_y
); i
++) {
1762 if (delta_y
[i
].file
== GRF
&& remap_table
[delta_y
[i
].reg
] != -1) {
1763 delta_y
[i
].reg
= remap_table
[delta_y
[i
].reg
];
1769 * Implements array access of uniforms by inserting a
1770 * PULL_CONSTANT_LOAD instruction.
1772 * Unlike temporary GRF array access (where we don't support it due to
1773 * the difficulty of doing relative addressing on instruction
1774 * destinations), we could potentially do array access of uniforms
1775 * that were loaded in GRF space as push constants. In real-world
1776 * usage we've seen, though, the arrays being used are always larger
1777 * than we could load as push constants, so just always move all
1778 * uniform array access out to a pull constant buffer.
1781 fs_visitor::move_uniform_array_access_to_pull_constants()
1783 if (dispatch_width
!= 8)
1786 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1788 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1789 pull_constant_loc
[i
] = -1;
1792 /* Walk through and find array access of uniforms. Put a copy of that
1793 * uniform in the pull constant buffer.
1795 * Note that we don't move constant-indexed accesses to arrays. No
1796 * testing has been done of the performance impact of this choice.
1798 foreach_in_list_safe(fs_inst
, inst
, &instructions
) {
1799 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1800 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
1803 int uniform
= inst
->src
[i
].reg
;
1805 /* If this array isn't already present in the pull constant buffer,
1808 if (pull_constant_loc
[uniform
] == -1) {
1809 const float **values
= &stage_prog_data
->param
[uniform
];
1811 assert(param_size
[uniform
]);
1813 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
1814 pull_constant_loc
[uniform
+ j
] = stage_prog_data
->nr_pull_params
;
1816 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
1825 * Assign UNIFORM file registers to either push constants or pull constants.
1827 * We allow a fragment shader to have more than the specified minimum
1828 * maximum number of fragment shader uniform components (64). If
1829 * there are too many of these, they'd fill up all of register space.
1830 * So, this will push some of them out to the pull constant buffer and
1831 * update the program to load them.
1834 fs_visitor::assign_constant_locations()
1836 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1837 if (dispatch_width
!= 8)
1840 /* Find which UNIFORM registers are still in use. */
1841 bool is_live
[uniforms
];
1842 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1846 foreach_in_list(fs_inst
, inst
, &instructions
) {
1847 for (int i
= 0; i
< inst
->sources
; i
++) {
1848 if (inst
->src
[i
].file
!= UNIFORM
)
1851 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1852 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1853 is_live
[constant_nr
] = true;
1857 /* Only allow 16 registers (128 uniform components) as push constants.
1859 * Just demote the end of the list. We could probably do better
1860 * here, demoting things that are rarely used in the program first.
1862 * If changing this value, note the limitation about total_regs in
1865 unsigned int max_push_components
= 16 * 8;
1866 unsigned int num_push_constants
= 0;
1868 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1870 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1871 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1872 /* This UNIFORM register is either dead, or has already been demoted
1873 * to a pull const. Mark it as no longer living in the param[] array.
1875 push_constant_loc
[i
] = -1;
1879 if (num_push_constants
< max_push_components
) {
1880 /* Retain as a push constant. Record the location in the params[]
1883 push_constant_loc
[i
] = num_push_constants
++;
1885 /* Demote to a pull constant. */
1886 push_constant_loc
[i
] = -1;
1888 int pull_index
= stage_prog_data
->nr_pull_params
++;
1889 stage_prog_data
->pull_param
[pull_index
] = stage_prog_data
->param
[i
];
1890 pull_constant_loc
[i
] = pull_index
;
1894 stage_prog_data
->nr_params
= num_push_constants
;
1896 /* Up until now, the param[] array has been indexed by reg + reg_offset
1897 * of UNIFORM registers. Condense it to only contain the uniforms we
1898 * chose to upload as push constants.
1900 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1901 int remapped
= push_constant_loc
[i
];
1906 assert(remapped
<= (int)i
);
1907 stage_prog_data
->param
[remapped
] = stage_prog_data
->param
[i
];
1912 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
1913 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
1916 fs_visitor::demote_pull_constants()
1918 foreach_in_list(fs_inst
, inst
, &instructions
) {
1919 for (int i
= 0; i
< inst
->sources
; i
++) {
1920 if (inst
->src
[i
].file
!= UNIFORM
)
1923 int pull_index
= pull_constant_loc
[inst
->src
[i
].reg
+
1924 inst
->src
[i
].reg_offset
];
1925 if (pull_index
== -1)
1928 /* Set up the annotation tracking for new generated instructions. */
1930 current_annotation
= inst
->annotation
;
1932 fs_reg
surf_index(stage_prog_data
->binding_table
.pull_constants_start
);
1933 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
1935 /* Generate a pull load into dst. */
1936 if (inst
->src
[i
].reladdr
) {
1937 exec_list list
= VARYING_PULL_CONSTANT_LOAD(dst
,
1939 *inst
->src
[i
].reladdr
,
1941 inst
->insert_before(&list
);
1942 inst
->src
[i
].reladdr
= NULL
;
1944 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
1946 new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
1947 dst
, surf_index
, offset
);
1948 inst
->insert_before(pull
);
1949 inst
->src
[i
].set_smear(pull_index
& 3);
1952 /* Rewrite the instruction to use the temporary VGRF. */
1953 inst
->src
[i
].file
= GRF
;
1954 inst
->src
[i
].reg
= dst
.reg
;
1955 inst
->src
[i
].reg_offset
= 0;
1958 invalidate_live_intervals();
1962 fs_visitor::opt_algebraic()
1964 bool progress
= false;
1966 foreach_in_list(fs_inst
, inst
, &instructions
) {
1967 switch (inst
->opcode
) {
1968 case BRW_OPCODE_MUL
:
1969 if (inst
->src
[1].file
!= IMM
)
1973 if (inst
->src
[1].is_one()) {
1974 inst
->opcode
= BRW_OPCODE_MOV
;
1975 inst
->src
[1] = reg_undef
;
1981 if (inst
->src
[1].is_zero()) {
1982 inst
->opcode
= BRW_OPCODE_MOV
;
1983 inst
->src
[0] = inst
->src
[1];
1984 inst
->src
[1] = reg_undef
;
1990 case BRW_OPCODE_ADD
:
1991 if (inst
->src
[1].file
!= IMM
)
1995 if (inst
->src
[1].is_zero()) {
1996 inst
->opcode
= BRW_OPCODE_MOV
;
1997 inst
->src
[1] = reg_undef
;
2003 if (inst
->src
[0].equals(inst
->src
[1])) {
2004 inst
->opcode
= BRW_OPCODE_MOV
;
2005 inst
->src
[1] = reg_undef
;
2010 case BRW_OPCODE_LRP
:
2011 if (inst
->src
[1].equals(inst
->src
[2])) {
2012 inst
->opcode
= BRW_OPCODE_MOV
;
2013 inst
->src
[0] = inst
->src
[1];
2014 inst
->src
[1] = reg_undef
;
2015 inst
->src
[2] = reg_undef
;
2020 case BRW_OPCODE_SEL
:
2021 if (inst
->src
[0].equals(inst
->src
[1])) {
2022 inst
->opcode
= BRW_OPCODE_MOV
;
2023 inst
->src
[1] = reg_undef
;
2024 inst
->predicate
= BRW_PREDICATE_NONE
;
2025 inst
->predicate_inverse
= false;
2027 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2028 switch (inst
->conditional_mod
) {
2029 case BRW_CONDITIONAL_LE
:
2030 case BRW_CONDITIONAL_L
:
2031 switch (inst
->src
[1].type
) {
2032 case BRW_REGISTER_TYPE_F
:
2033 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
>= 1.0f
) {
2034 inst
->opcode
= BRW_OPCODE_MOV
;
2035 inst
->src
[1] = reg_undef
;
2043 case BRW_CONDITIONAL_GE
:
2044 case BRW_CONDITIONAL_G
:
2045 switch (inst
->src
[1].type
) {
2046 case BRW_REGISTER_TYPE_F
:
2047 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
<= 0.0f
) {
2048 inst
->opcode
= BRW_OPCODE_MOV
;
2049 inst
->src
[1] = reg_undef
;
2050 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2071 fs_visitor::compute_to_mrf()
2073 bool progress
= false;
2076 calculate_live_intervals();
2078 foreach_in_list_safe(fs_inst
, inst
, &instructions
) {
2082 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2083 inst
->is_partial_write() ||
2084 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2085 inst
->dst
.type
!= inst
->src
[0].type
||
2086 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2087 !inst
->src
[0].is_contiguous() ||
2088 inst
->src
[0].subreg_offset
)
2091 /* Work out which hardware MRF registers are written by this
2094 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2096 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2097 mrf_high
= mrf_low
+ 4;
2098 } else if (dispatch_width
== 16 &&
2099 (!inst
->force_uncompressed
&& !inst
->force_sechalf
)) {
2100 mrf_high
= mrf_low
+ 1;
2105 /* Can't compute-to-MRF this GRF if someone else was going to
2108 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2111 /* Found a move of a GRF to a MRF. Let's see if we can go
2112 * rewrite the thing that made this GRF to write into the MRF.
2115 for (scan_inst
= (fs_inst
*)inst
->prev
;
2116 !scan_inst
->is_head_sentinel();
2117 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2118 if (scan_inst
->dst
.file
== GRF
&&
2119 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2120 /* Found the last thing to write our reg we want to turn
2121 * into a compute-to-MRF.
2124 /* If this one instruction didn't populate all the
2125 * channels, bail. We might be able to rewrite everything
2126 * that writes that reg, but it would require smarter
2127 * tracking to delay the rewriting until complete success.
2129 if (scan_inst
->is_partial_write())
2132 /* Things returning more than one register would need us to
2133 * understand coalescing out more than one MOV at a time.
2135 if (scan_inst
->regs_written
> 1)
2138 /* SEND instructions can't have MRF as a destination. */
2139 if (scan_inst
->mlen
)
2142 if (brw
->gen
== 6) {
2143 /* gen6 math instructions must have the destination be
2144 * GRF, so no compute-to-MRF for them.
2146 if (scan_inst
->is_math()) {
2151 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2152 /* Found the creator of our MRF's source value. */
2153 scan_inst
->dst
.file
= MRF
;
2154 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2155 scan_inst
->saturate
|= inst
->saturate
;
2162 /* We don't handle control flow here. Most computation of
2163 * values that end up in MRFs are shortly before the MRF
2166 if (scan_inst
->is_control_flow() && scan_inst
->opcode
!= BRW_OPCODE_IF
)
2169 /* You can't read from an MRF, so if someone else reads our
2170 * MRF's source GRF that we wanted to rewrite, that stops us.
2172 bool interfered
= false;
2173 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2174 if (scan_inst
->src
[i
].file
== GRF
&&
2175 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2176 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2183 if (scan_inst
->dst
.file
== MRF
) {
2184 /* If somebody else writes our MRF here, we can't
2185 * compute-to-MRF before that.
2187 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2190 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2191 scan_mrf_high
= scan_mrf_low
+ 4;
2192 } else if (dispatch_width
== 16 &&
2193 (!scan_inst
->force_uncompressed
&&
2194 !scan_inst
->force_sechalf
)) {
2195 scan_mrf_high
= scan_mrf_low
+ 1;
2197 scan_mrf_high
= scan_mrf_low
;
2200 if (mrf_low
== scan_mrf_low
||
2201 mrf_low
== scan_mrf_high
||
2202 mrf_high
== scan_mrf_low
||
2203 mrf_high
== scan_mrf_high
) {
2208 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2209 /* Found a SEND instruction, which means that there are
2210 * live values in MRFs from base_mrf to base_mrf +
2211 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2214 if (mrf_low
>= scan_inst
->base_mrf
&&
2215 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2218 if (mrf_high
>= scan_inst
->base_mrf
&&
2219 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2227 invalidate_live_intervals();
2233 * Walks through basic blocks, looking for repeated MRF writes and
2234 * removing the later ones.
2237 fs_visitor::remove_duplicate_mrf_writes()
2239 fs_inst
*last_mrf_move
[16];
2240 bool progress
= false;
2242 /* Need to update the MRF tracking for compressed instructions. */
2243 if (dispatch_width
== 16)
2246 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2248 foreach_in_list_safe(fs_inst
, inst
, &instructions
) {
2249 if (inst
->is_control_flow()) {
2250 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2253 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2254 inst
->dst
.file
== MRF
) {
2255 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2256 if (prev_inst
&& inst
->equals(prev_inst
)) {
2263 /* Clear out the last-write records for MRFs that were overwritten. */
2264 if (inst
->dst
.file
== MRF
) {
2265 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2268 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2269 /* Found a SEND instruction, which will include two or fewer
2270 * implied MRF writes. We could do better here.
2272 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2273 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2277 /* Clear out any MRF move records whose sources got overwritten. */
2278 if (inst
->dst
.file
== GRF
) {
2279 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
2280 if (last_mrf_move
[i
] &&
2281 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2282 last_mrf_move
[i
] = NULL
;
2287 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2288 inst
->dst
.file
== MRF
&&
2289 inst
->src
[0].file
== GRF
&&
2290 !inst
->is_partial_write()) {
2291 last_mrf_move
[inst
->dst
.reg
] = inst
;
2296 invalidate_live_intervals();
2302 clear_deps_for_inst_src(fs_inst
*inst
, int dispatch_width
, bool *deps
,
2303 int first_grf
, int grf_len
)
2305 bool inst_simd16
= (dispatch_width
> 8 &&
2306 !inst
->force_uncompressed
&&
2307 !inst
->force_sechalf
);
2309 /* Clear the flag for registers that actually got read (as expected). */
2310 for (int i
= 0; i
< inst
->sources
; i
++) {
2312 if (inst
->src
[i
].file
== GRF
) {
2313 grf
= inst
->src
[i
].reg
;
2314 } else if (inst
->src
[i
].file
== HW_REG
&&
2315 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2316 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2321 if (grf
>= first_grf
&&
2322 grf
< first_grf
+ grf_len
) {
2323 deps
[grf
- first_grf
] = false;
2325 deps
[grf
- first_grf
+ 1] = false;
2331 * Implements this workaround for the original 965:
2333 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2334 * check for post destination dependencies on this instruction, software
2335 * must ensure that there is no destination hazard for the case of ‘write
2336 * followed by a posted write’ shown in the following example.
2339 * 2. send r3.xy <rest of send instruction>
2342 * Due to no post-destination dependency check on the ‘send’, the above
2343 * code sequence could have two instructions (1 and 2) in flight at the
2344 * same time that both consider ‘r3’ as the target of their final writes.
2347 fs_visitor::insert_gen4_pre_send_dependency_workarounds(fs_inst
*inst
)
2349 int reg_size
= dispatch_width
/ 8;
2350 int write_len
= inst
->regs_written
* reg_size
;
2351 int first_write_grf
= inst
->dst
.reg
;
2352 bool needs_dep
[BRW_MAX_MRF
];
2353 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2355 memset(needs_dep
, false, sizeof(needs_dep
));
2356 memset(needs_dep
, true, write_len
);
2358 clear_deps_for_inst_src(inst
, dispatch_width
,
2359 needs_dep
, first_write_grf
, write_len
);
2361 /* Walk backwards looking for writes to registers we're writing which
2362 * aren't read since being written. If we hit the start of the program,
2363 * we assume that there are no outstanding dependencies on entry to the
2366 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->prev
;
2367 !scan_inst
->is_head_sentinel();
2368 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2370 /* If we hit control flow, assume that there *are* outstanding
2371 * dependencies, and force their cleanup before our instruction.
2373 if (scan_inst
->is_control_flow()) {
2374 for (int i
= 0; i
< write_len
; i
++) {
2376 inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2382 bool scan_inst_simd16
= (dispatch_width
> 8 &&
2383 !scan_inst
->force_uncompressed
&&
2384 !scan_inst
->force_sechalf
);
2386 /* We insert our reads as late as possible on the assumption that any
2387 * instruction but a MOV that might have left us an outstanding
2388 * dependency has more latency than a MOV.
2390 if (scan_inst
->dst
.file
== GRF
) {
2391 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2392 int reg
= scan_inst
->dst
.reg
+ i
* reg_size
;
2394 if (reg
>= first_write_grf
&&
2395 reg
< first_write_grf
+ write_len
&&
2396 needs_dep
[reg
- first_write_grf
]) {
2397 inst
->insert_before(DEP_RESOLVE_MOV(reg
));
2398 needs_dep
[reg
- first_write_grf
] = false;
2399 if (scan_inst_simd16
)
2400 needs_dep
[reg
- first_write_grf
+ 1] = false;
2405 /* Clear the flag for registers that actually got read (as expected). */
2406 clear_deps_for_inst_src(scan_inst
, dispatch_width
,
2407 needs_dep
, first_write_grf
, write_len
);
2409 /* Continue the loop only if we haven't resolved all the dependencies */
2411 for (i
= 0; i
< write_len
; i
++) {
2421 * Implements this workaround for the original 965:
2423 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2424 * used as a destination register until after it has been sourced by an
2425 * instruction with a different destination register.
2428 fs_visitor::insert_gen4_post_send_dependency_workarounds(fs_inst
*inst
)
2430 int write_len
= inst
->regs_written
* dispatch_width
/ 8;
2431 int first_write_grf
= inst
->dst
.reg
;
2432 bool needs_dep
[BRW_MAX_MRF
];
2433 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2435 memset(needs_dep
, false, sizeof(needs_dep
));
2436 memset(needs_dep
, true, write_len
);
2437 /* Walk forwards looking for writes to registers we're writing which aren't
2438 * read before being written.
2440 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->next
;
2441 !scan_inst
->is_tail_sentinel();
2442 scan_inst
= (fs_inst
*)scan_inst
->next
) {
2443 /* If we hit control flow, force resolve all remaining dependencies. */
2444 if (scan_inst
->is_control_flow()) {
2445 for (int i
= 0; i
< write_len
; i
++) {
2447 scan_inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2452 /* Clear the flag for registers that actually got read (as expected). */
2453 clear_deps_for_inst_src(scan_inst
, dispatch_width
,
2454 needs_dep
, first_write_grf
, write_len
);
2456 /* We insert our reads as late as possible since they're reading the
2457 * result of a SEND, which has massive latency.
2459 if (scan_inst
->dst
.file
== GRF
&&
2460 scan_inst
->dst
.reg
>= first_write_grf
&&
2461 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
2462 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
2463 scan_inst
->insert_before(DEP_RESOLVE_MOV(scan_inst
->dst
.reg
));
2464 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
2467 /* Continue the loop only if we haven't resolved all the dependencies */
2469 for (i
= 0; i
< write_len
; i
++) {
2477 /* If we hit the end of the program, resolve all remaining dependencies out
2480 fs_inst
*last_inst
= (fs_inst
*)this->instructions
.get_tail();
2481 assert(last_inst
->eot
);
2482 for (int i
= 0; i
< write_len
; i
++) {
2484 last_inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2489 fs_visitor::insert_gen4_send_dependency_workarounds()
2491 if (brw
->gen
!= 4 || brw
->is_g4x
)
2494 bool progress
= false;
2496 /* Note that we're done with register allocation, so GRF fs_regs always
2497 * have a .reg_offset of 0.
2500 foreach_in_list_safe(fs_inst
, inst
, &instructions
) {
2501 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
2502 insert_gen4_pre_send_dependency_workarounds(inst
);
2503 insert_gen4_post_send_dependency_workarounds(inst
);
2509 invalidate_live_intervals();
2513 * Turns the generic expression-style uniform pull constant load instruction
2514 * into a hardware-specific series of instructions for loading a pull
2517 * The expression style allows the CSE pass before this to optimize out
2518 * repeated loads from the same offset, and gives the pre-register-allocation
2519 * scheduling full flexibility, while the conversion to native instructions
2520 * allows the post-register-allocation scheduler the best information
2523 * Note that execution masking for setting up pull constant loads is special:
2524 * the channels that need to be written are unrelated to the current execution
2525 * mask, since a later instruction will use one of the result channels as a
2526 * source operand for all 8 or 16 of its channels.
2529 fs_visitor::lower_uniform_pull_constant_loads()
2531 foreach_in_list(fs_inst
, inst
, &instructions
) {
2532 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
2535 if (brw
->gen
>= 7) {
2536 /* The offset arg before was a vec4-aligned byte offset. We need to
2537 * turn it into a dword offset.
2539 fs_reg const_offset_reg
= inst
->src
[1];
2540 assert(const_offset_reg
.file
== IMM
&&
2541 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
2542 const_offset_reg
.fixed_hw_reg
.dw1
.ud
/= 4;
2543 fs_reg payload
= fs_reg(this, glsl_type::uint_type
);
2545 /* This is actually going to be a MOV, but since only the first dword
2546 * is accessed, we have a special opcode to do just that one. Note
2547 * that this needs to be an operation that will be considered a def
2548 * by live variable analysis, or register allocation will explode.
2550 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
2551 payload
, const_offset_reg
);
2552 setup
->force_writemask_all
= true;
2554 setup
->ir
= inst
->ir
;
2555 setup
->annotation
= inst
->annotation
;
2556 inst
->insert_before(setup
);
2558 /* Similarly, this will only populate the first 4 channels of the
2559 * result register (since we only use smear values from 0-3), but we
2560 * don't tell the optimizer.
2562 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
2563 inst
->src
[1] = payload
;
2565 invalidate_live_intervals();
2567 /* Before register allocation, we didn't tell the scheduler about the
2568 * MRF we use. We know it's safe to use this MRF because nothing
2569 * else does except for register spill/unspill, which generates and
2570 * uses its MRF within a single IR instruction.
2572 inst
->base_mrf
= 14;
2579 fs_visitor::lower_load_payload()
2581 bool progress
= false;
2583 foreach_in_list_safe(fs_inst
, inst
, &instructions
) {
2584 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
2585 fs_reg dst
= inst
->dst
;
2587 /* src[0] represents the (optional) message header. */
2588 if (inst
->src
[0].file
!= BAD_FILE
) {
2589 inst
->insert_before(MOV(dst
, inst
->src
[0]));
2593 for (int i
= 1; i
< inst
->sources
; i
++) {
2594 inst
->insert_before(MOV(dst
, inst
->src
[i
]));
2604 invalidate_live_intervals();
2610 fs_visitor::dump_instructions()
2612 dump_instructions(NULL
);
2616 fs_visitor::dump_instructions(const char *name
)
2618 calculate_register_pressure();
2619 FILE *file
= stderr
;
2620 if (name
&& geteuid() != 0) {
2621 file
= fopen(name
, "w");
2626 int ip
= 0, max_pressure
= 0;
2627 foreach_in_list(backend_instruction
, inst
, &instructions
) {
2628 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
2629 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
2630 dump_instruction(inst
, file
);
2633 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
2635 if (file
!= stderr
) {
2641 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
2643 dump_instruction(be_inst
, stderr
);
2647 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
2649 fs_inst
*inst
= (fs_inst
*)be_inst
;
2651 if (inst
->predicate
) {
2652 fprintf(file
, "(%cf0.%d) ",
2653 inst
->predicate_inverse
? '-' : '+',
2657 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
2659 fprintf(file
, ".sat");
2660 if (inst
->conditional_mod
) {
2661 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
2662 if (!inst
->predicate
&&
2663 (brw
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
2664 inst
->opcode
!= BRW_OPCODE_IF
&&
2665 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
2666 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
2672 switch (inst
->dst
.file
) {
2674 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
2675 if (virtual_grf_sizes
[inst
->dst
.reg
] != 1 ||
2676 inst
->dst
.subreg_offset
)
2677 fprintf(file
, "+%d.%d",
2678 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
2681 fprintf(file
, "m%d", inst
->dst
.reg
);
2684 fprintf(file
, "(null)");
2687 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
2690 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
2691 switch (inst
->dst
.fixed_hw_reg
.nr
) {
2693 fprintf(file
, "null");
2695 case BRW_ARF_ADDRESS
:
2696 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
2698 case BRW_ARF_ACCUMULATOR
:
2699 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
2702 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
2703 inst
->dst
.fixed_hw_reg
.subnr
);
2706 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
2707 inst
->dst
.fixed_hw_reg
.subnr
);
2711 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
2713 if (inst
->dst
.fixed_hw_reg
.subnr
)
2714 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
2717 fprintf(file
, "???");
2720 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
2722 for (int i
= 0; i
< inst
->sources
&& inst
->src
[i
].file
!= BAD_FILE
; i
++) {
2723 if (inst
->src
[i
].negate
)
2725 if (inst
->src
[i
].abs
)
2727 switch (inst
->src
[i
].file
) {
2729 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
2730 if (virtual_grf_sizes
[inst
->src
[i
].reg
] != 1 ||
2731 inst
->src
[i
].subreg_offset
)
2732 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
2733 inst
->src
[i
].subreg_offset
);
2736 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
2739 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
2740 if (inst
->src
[i
].reladdr
) {
2741 fprintf(file
, "+reladdr");
2742 } else if (virtual_grf_sizes
[inst
->src
[i
].reg
] != 1 ||
2743 inst
->src
[i
].subreg_offset
) {
2744 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
2745 inst
->src
[i
].subreg_offset
);
2749 fprintf(file
, "(null)");
2752 switch (inst
->src
[i
].type
) {
2753 case BRW_REGISTER_TYPE_F
:
2754 fprintf(file
, "%ff", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
2756 case BRW_REGISTER_TYPE_D
:
2757 fprintf(file
, "%dd", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
2759 case BRW_REGISTER_TYPE_UD
:
2760 fprintf(file
, "%uu", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
2763 fprintf(file
, "???");
2768 if (inst
->src
[i
].fixed_hw_reg
.negate
)
2770 if (inst
->src
[i
].fixed_hw_reg
.abs
)
2772 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
2773 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
2775 fprintf(file
, "null");
2777 case BRW_ARF_ADDRESS
:
2778 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
2780 case BRW_ARF_ACCUMULATOR
:
2781 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
2784 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
2785 inst
->src
[i
].fixed_hw_reg
.subnr
);
2788 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
2789 inst
->src
[i
].fixed_hw_reg
.subnr
);
2793 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
2795 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
2796 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
2797 if (inst
->src
[i
].fixed_hw_reg
.abs
)
2801 fprintf(file
, "???");
2804 if (inst
->src
[i
].abs
)
2807 if (inst
->src
[i
].file
!= IMM
) {
2808 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
2811 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
2812 fprintf(file
, ", ");
2817 if (inst
->force_uncompressed
)
2818 fprintf(file
, "1sthalf ");
2820 if (inst
->force_sechalf
)
2821 fprintf(file
, "2ndhalf ");
2823 fprintf(file
, "\n");
2827 * Possibly returns an instruction that set up @param reg.
2829 * Sometimes we want to take the result of some expression/variable
2830 * dereference tree and rewrite the instruction generating the result
2831 * of the tree. When processing the tree, we know that the
2832 * instructions generated are all writing temporaries that are dead
2833 * outside of this tree. So, if we have some instructions that write
2834 * a temporary, we're free to point that temp write somewhere else.
2836 * Note that this doesn't guarantee that the instruction generated
2837 * only reg -- it might be the size=4 destination of a texture instruction.
2840 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
2845 end
->is_partial_write() ||
2847 !reg
.equals(end
->dst
)) {
2855 fs_visitor::setup_payload_gen6()
2858 (fp
->Base
.InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
2859 unsigned barycentric_interp_modes
= prog_data
->barycentric_interp_modes
;
2861 assert(brw
->gen
>= 6);
2863 /* R0-1: masks, pixel X/Y coordinates. */
2864 payload
.num_regs
= 2;
2865 /* R2: only for 32-pixel dispatch.*/
2867 /* R3-26: barycentric interpolation coordinates. These appear in the
2868 * same order that they appear in the brw_wm_barycentric_interp_mode
2869 * enum. Each set of coordinates occupies 2 registers if dispatch width
2870 * == 8 and 4 registers if dispatch width == 16. Coordinates only
2871 * appear if they were enabled using the "Barycentric Interpolation
2872 * Mode" bits in WM_STATE.
2874 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
2875 if (barycentric_interp_modes
& (1 << i
)) {
2876 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
2877 payload
.num_regs
+= 2;
2878 if (dispatch_width
== 16) {
2879 payload
.num_regs
+= 2;
2884 /* R27: interpolated depth if uses source depth */
2886 payload
.source_depth_reg
= payload
.num_regs
;
2888 if (dispatch_width
== 16) {
2889 /* R28: interpolated depth if not SIMD8. */
2893 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
2895 payload
.source_w_reg
= payload
.num_regs
;
2897 if (dispatch_width
== 16) {
2898 /* R30: interpolated W if not SIMD8. */
2903 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
2904 /* R31: MSAA position offsets. */
2905 if (prog_data
->uses_pos_offset
) {
2906 payload
.sample_pos_reg
= payload
.num_regs
;
2910 /* R32: MSAA input coverage mask */
2911 if (fp
->Base
.SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
2912 assert(brw
->gen
>= 7);
2913 payload
.sample_mask_in_reg
= payload
.num_regs
;
2915 if (dispatch_width
== 16) {
2916 /* R33: input coverage mask if not SIMD8. */
2921 /* R34-: bary for 32-pixel. */
2922 /* R58-59: interp W for 32-pixel. */
2924 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
2925 source_depth_to_render_target
= true;
2930 fs_visitor::assign_binding_table_offsets()
2932 uint32_t next_binding_table_offset
= 0;
2934 /* If there are no color regions, we still perform an FB write to a null
2935 * renderbuffer, which we place at surface index 0.
2937 prog_data
->binding_table
.render_target_start
= next_binding_table_offset
;
2938 next_binding_table_offset
+= MAX2(key
->nr_color_regions
, 1);
2940 assign_common_binding_table_offsets(next_binding_table_offset
);
2944 fs_visitor::calculate_register_pressure()
2946 invalidate_live_intervals();
2947 calculate_live_intervals();
2949 unsigned num_instructions
= instructions
.length();
2951 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
2953 for (int reg
= 0; reg
< virtual_grf_count
; reg
++) {
2954 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
2955 regs_live_at_ip
[ip
] += virtual_grf_sizes
[reg
];
2960 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
2962 * The needs_unlit_centroid_workaround ends up producing one of these per
2963 * channel of centroid input, so it's good to clean them up.
2965 * An assumption here is that nothing ever modifies the dispatched pixels
2966 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
2967 * dictates that anyway.
2970 fs_visitor::opt_drop_redundant_mov_to_flags()
2972 bool flag_mov_found
[2] = {false};
2974 foreach_in_list_safe(fs_inst
, inst
, &instructions
) {
2975 if (inst
->is_control_flow()) {
2976 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
2977 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
2978 if (!flag_mov_found
[inst
->flag_subreg
])
2979 flag_mov_found
[inst
->flag_subreg
] = true;
2982 } else if (inst
->writes_flag()) {
2983 flag_mov_found
[inst
->flag_subreg
] = false;
2991 sanity_param_count
= fp
->Base
.Parameters
->NumParameters
;
2992 bool allocated_without_spills
;
2994 assign_binding_table_offsets();
2997 setup_payload_gen6();
2999 setup_payload_gen4();
3004 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3005 emit_shader_time_begin();
3007 calculate_urb_setup();
3008 if (fp
->Base
.InputsRead
> 0) {
3010 emit_interpolation_setup_gen4();
3012 emit_interpolation_setup_gen6();
3015 /* We handle discards by keeping track of the still-live pixels in f0.1.
3016 * Initialize it with the dispatched pixels.
3018 if (fp
->UsesKill
|| key
->alpha_test_func
) {
3019 fs_inst
*discard_init
= emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
3020 discard_init
->flag_subreg
= 1;
3023 /* Generate FS IR for main(). (the visitor only descends into
3024 * functions called "main").
3027 foreach_in_list(ir_instruction
, ir
, shader
->base
.ir
) {
3029 this->result
= reg_undef
;
3033 emit_fragment_program_code();
3039 emit(FS_OPCODE_PLACEHOLDER_HALT
);
3041 if (key
->alpha_test_func
)
3046 split_virtual_grfs();
3048 move_uniform_array_access_to_pull_constants();
3049 assign_constant_locations();
3050 demote_pull_constants();
3052 opt_drop_redundant_mov_to_flags();
3054 #define OPT(pass, args...) do { \
3056 bool this_progress = pass(args); \
3058 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
3059 char filename[64]; \
3060 snprintf(filename, 64, "fs%d-%04d-%02d-%02d-" #pass, \
3061 dispatch_width, shader_prog->Name, iteration, pass_num); \
3063 backend_visitor::dump_instructions(filename); \
3066 progress = progress || this_progress; \
3069 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
3071 snprintf(filename
, 64, "fs%d-%04d-00-start",
3072 dispatch_width
, shader_prog
->Name
);
3074 backend_visitor::dump_instructions(filename
);
3084 compact_virtual_grfs();
3086 OPT(remove_duplicate_mrf_writes
);
3090 OPT(opt_copy_propagate
);
3091 OPT(opt_peephole_predicated_break
);
3092 OPT(dead_code_eliminate
);
3093 OPT(opt_peephole_sel
);
3094 OPT(dead_control_flow_eliminate
, this);
3095 OPT(opt_saturate_propagation
);
3096 OPT(register_coalesce
);
3097 OPT(compute_to_mrf
);
3100 if (lower_load_payload()) {
3101 register_coalesce();
3102 dead_code_eliminate();
3105 lower_uniform_pull_constant_loads();
3107 assign_curb_setup();
3110 static enum instruction_scheduler_mode pre_modes
[] = {
3112 SCHEDULE_PRE_NON_LIFO
,
3116 /* Try each scheduling heuristic to see if it can successfully register
3117 * allocate without spilling. They should be ordered by decreasing
3118 * performance but increasing likelihood of allocating.
3120 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
3121 schedule_instructions(pre_modes
[i
]);
3124 assign_regs_trivial();
3125 allocated_without_spills
= true;
3127 allocated_without_spills
= assign_regs(false);
3129 if (allocated_without_spills
)
3133 if (!allocated_without_spills
) {
3134 /* We assume that any spilling is worse than just dropping back to
3135 * SIMD8. There's probably actually some intermediate point where
3136 * SIMD16 with a couple of spills is still better.
3138 if (dispatch_width
== 16) {
3139 fail("Failure to register allocate. Reduce number of "
3140 "live scalar values to avoid this.");
3142 perf_debug("Fragment shader triggered register spilling. "
3143 "Try reducing the number of live scalar values to "
3144 "improve performance.\n");
3147 /* Since we're out of heuristics, just go spill registers until we
3148 * get an allocation.
3150 while (!assign_regs(true)) {
3156 assert(force_uncompressed_stack
== 0);
3158 /* This must come after all optimization and register allocation, since
3159 * it inserts dead code that happens to have side effects, and it does
3160 * so based on the actual physical registers in use.
3162 insert_gen4_send_dependency_workarounds();
3167 if (!allocated_without_spills
)
3168 schedule_instructions(SCHEDULE_POST
);
3170 if (last_scratch
> 0) {
3171 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
3174 if (dispatch_width
== 8)
3175 prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
3177 prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
3179 /* If any state parameters were appended, then ParameterValues could have
3180 * been realloced, in which case the driver uniform storage set up by
3181 * _mesa_associate_uniform_storage() would point to freed memory. Make
3182 * sure that didn't happen.
3184 assert(sanity_param_count
== fp
->Base
.Parameters
->NumParameters
);
3190 brw_wm_fs_emit(struct brw_context
*brw
,
3192 const struct brw_wm_prog_key
*key
,
3193 struct brw_wm_prog_data
*prog_data
,
3194 struct gl_fragment_program
*fp
,
3195 struct gl_shader_program
*prog
,
3196 unsigned *final_assembly_size
)
3198 bool start_busy
= false;
3199 double start_time
= 0;
3201 if (unlikely(brw
->perf_debug
)) {
3202 start_busy
= (brw
->batch
.last_bo
&&
3203 drm_intel_bo_busy(brw
->batch
.last_bo
));
3204 start_time
= get_time();
3207 struct brw_shader
*shader
= NULL
;
3209 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3211 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
3212 brw_dump_ir(brw
, "fragment", prog
, &shader
->base
, &fp
->Base
);
3214 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3216 fs_visitor
v(brw
, mem_ctx
, key
, prog_data
, prog
, fp
, 8);
3219 prog
->LinkStatus
= false;
3220 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
3223 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
3229 exec_list
*simd16_instructions
= NULL
;
3230 fs_visitor
v2(brw
, mem_ctx
, key
, prog_data
, prog
, fp
, 16);
3231 if (brw
->gen
>= 5 && likely(!(INTEL_DEBUG
& DEBUG_NO16
))) {
3232 if (!v
.simd16_unsupported
) {
3233 /* Try a SIMD16 compile */
3234 v2
.import_uniforms(&v
);
3236 perf_debug("SIMD16 shader failed to compile, falling back to "
3237 "SIMD8 at a 10-20%% performance cost: %s", v2
.fail_msg
);
3239 simd16_instructions
= &v2
.instructions
;
3242 perf_debug("SIMD16 shader unsupported, falling back to "
3243 "SIMD8 at a 10-20%% performance cost: %s", v
.no16_msg
);
3247 const unsigned *assembly
= NULL
;
3248 fs_generator
g(brw
, mem_ctx
, key
, prog_data
, prog
, fp
,
3249 v
.runtime_check_aads_emit
, INTEL_DEBUG
& DEBUG_WM
);
3250 assembly
= g
.generate_assembly(&v
.instructions
, simd16_instructions
,
3251 final_assembly_size
);
3253 if (unlikely(brw
->perf_debug
) && shader
) {
3254 if (shader
->compiled_once
)
3255 brw_wm_debug_recompile(brw
, prog
, key
);
3256 shader
->compiled_once
= true;
3258 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
3259 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
3260 (get_time() - start_time
) * 1000);
3268 brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
3270 struct brw_context
*brw
= brw_context(ctx
);
3271 struct brw_wm_prog_key key
;
3273 if (!prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
])
3276 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)
3277 prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
]->Program
;
3278 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
3279 bool program_uses_dfdy
= fp
->UsesDFdy
;
3281 memset(&key
, 0, sizeof(key
));
3285 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
3287 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
3288 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
3290 /* Just assume depth testing. */
3291 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
3292 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
3295 if (brw
->gen
< 6 || _mesa_bitcount_64(fp
->Base
.InputsRead
&
3296 BRW_FS_VARYING_INPUT_MASK
) > 16)
3297 key
.input_slots_valid
= fp
->Base
.InputsRead
| VARYING_BIT_POS
;
3299 unsigned sampler_count
= _mesa_fls(fp
->Base
.SamplersUsed
);
3300 for (unsigned i
= 0; i
< sampler_count
; i
++) {
3301 if (fp
->Base
.ShadowSamplers
& (1 << i
)) {
3302 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
3303 key
.tex
.swizzles
[i
] =
3304 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
3306 /* Color sampler: assume no swizzling. */
3307 key
.tex
.swizzles
[i
] = SWIZZLE_XYZW
;
3311 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
) {
3312 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
3315 key
.nr_color_regions
= _mesa_bitcount_64(fp
->Base
.OutputsWritten
&
3316 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
3317 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
)));
3319 if ((fp
->Base
.InputsRead
& VARYING_BIT_POS
) || program_uses_dfdy
) {
3320 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
) ||
3321 key
.nr_color_regions
> 1;
3324 /* GL_FRAGMENT_SHADER_DERIVATIVE_HINT is almost always GL_DONT_CARE. The
3325 * quality of the derivatives is likely to be determined by the driconf
3328 key
.high_quality_derivatives
= brw
->disable_derivative_optimization
;
3330 key
.program_string_id
= bfp
->id
;
3332 uint32_t old_prog_offset
= brw
->wm
.base
.prog_offset
;
3333 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
3335 bool success
= do_wm_prog(brw
, prog
, bfp
, &key
);
3337 brw
->wm
.base
.prog_offset
= old_prog_offset
;
3338 brw
->wm
.prog_data
= old_prog_data
;