2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "../glsl/glsl_types.h"
47 #include "../glsl/ir_optimization.h"
48 #include "../glsl/ir_print_visitor.h"
50 #define MAX_INSTRUCTION (1 << 30)
51 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
54 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
56 struct brw_shader
*shader
;
58 shader
= rzalloc(NULL
, struct brw_shader
);
60 shader
->base
.Type
= type
;
61 shader
->base
.Name
= name
;
62 _mesa_init_shader(ctx
, &shader
->base
);
68 struct gl_shader_program
*
69 brw_new_shader_program(struct gl_context
*ctx
, GLuint name
)
71 struct brw_shader_program
*prog
;
72 prog
= rzalloc(NULL
, struct brw_shader_program
);
74 prog
->base
.Name
= name
;
75 _mesa_init_shader_program(ctx
, &prog
->base
);
81 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
83 struct brw_context
*brw
= brw_context(ctx
);
84 struct intel_context
*intel
= &brw
->intel
;
86 struct brw_shader
*shader
=
87 (struct brw_shader
*)prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
89 void *mem_ctx
= ralloc_context(NULL
);
93 ralloc_free(shader
->ir
);
94 shader
->ir
= new(shader
) exec_list
;
95 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
97 do_mat_op_to_vec(shader
->ir
);
98 lower_instructions(shader
->ir
,
105 /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
106 * if-statements need to be flattened.
109 lower_if_to_cond_assign(shader
->ir
, 16);
111 do_lower_texture_projection(shader
->ir
);
112 do_vec_index_to_cond_assign(shader
->ir
);
113 brw_do_cubemap_normalize(shader
->ir
);
114 lower_noise(shader
->ir
);
115 lower_quadop_vector(shader
->ir
, false);
116 lower_variable_index_to_cond_assign(shader
->ir
,
118 GL_TRUE
, /* output */
120 GL_TRUE
/* uniform */
126 brw_do_channel_expressions(shader
->ir
);
127 brw_do_vector_splitting(shader
->ir
);
129 progress
= do_lower_jumps(shader
->ir
, true, true,
130 true, /* main return */
131 false, /* continue */
135 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
138 validate_ir_tree(shader
->ir
);
140 reparent_ir(shader
->ir
, shader
->ir
);
141 ralloc_free(mem_ctx
);
144 if (!_mesa_ir_link_shader(ctx
, prog
))
151 type_size(const struct glsl_type
*type
)
153 unsigned int size
, i
;
155 switch (type
->base_type
) {
158 case GLSL_TYPE_FLOAT
:
160 return type
->components();
161 case GLSL_TYPE_ARRAY
:
162 return type_size(type
->fields
.array
) * type
->length
;
163 case GLSL_TYPE_STRUCT
:
165 for (i
= 0; i
< type
->length
; i
++) {
166 size
+= type_size(type
->fields
.structure
[i
].type
);
169 case GLSL_TYPE_SAMPLER
:
170 /* Samplers take up no register space, since they're baked in at
175 assert(!"not reached");
181 fs_visitor::fail(const char *format
, ...)
186 if (INTEL_DEBUG
& DEBUG_WM
) {
187 fprintf(stderr
, "FS compile failed: ");
190 va_start(va
, format
);
191 vfprintf(stderr
, format
, va
);
198 fs_visitor::push_force_uncompressed()
200 force_uncompressed_stack
++;
204 fs_visitor::pop_force_uncompressed()
206 force_uncompressed_stack
--;
207 assert(force_uncompressed_stack
>= 0);
211 fs_visitor::push_force_sechalf()
213 force_sechalf_stack
++;
217 fs_visitor::pop_force_sechalf()
219 force_sechalf_stack
--;
220 assert(force_sechalf_stack
>= 0);
224 * Returns how many MRFs an FS opcode will write over.
226 * Note that this is not the 0 or 1 implied writes in an actual gen
227 * instruction -- the FS opcodes often generate MOVs in addition.
230 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
235 switch (inst
->opcode
) {
243 return 1 * c
->dispatch_width
/ 8;
245 return 2 * c
->dispatch_width
/ 8;
251 case FS_OPCODE_FB_WRITE
:
253 case FS_OPCODE_PULL_CONSTANT_LOAD
:
254 case FS_OPCODE_UNSPILL
:
256 case FS_OPCODE_SPILL
:
259 assert(!"not reached");
265 fs_visitor::virtual_grf_alloc(int size
)
267 if (virtual_grf_array_size
<= virtual_grf_next
) {
268 if (virtual_grf_array_size
== 0)
269 virtual_grf_array_size
= 16;
271 virtual_grf_array_size
*= 2;
272 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
273 virtual_grf_array_size
);
275 /* This slot is always unused. */
276 virtual_grf_sizes
[0] = 0;
278 virtual_grf_sizes
[virtual_grf_next
] = size
;
279 return virtual_grf_next
++;
282 /** Fixed HW reg constructor. */
283 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
287 this->hw_reg
= hw_reg
;
288 this->type
= BRW_REGISTER_TYPE_F
;
291 /** Fixed HW reg constructor. */
292 fs_reg::fs_reg(enum register_file file
, int hw_reg
, uint32_t type
)
296 this->hw_reg
= hw_reg
;
301 brw_type_for_base_type(const struct glsl_type
*type
)
303 switch (type
->base_type
) {
304 case GLSL_TYPE_FLOAT
:
305 return BRW_REGISTER_TYPE_F
;
308 return BRW_REGISTER_TYPE_D
;
310 return BRW_REGISTER_TYPE_UD
;
311 case GLSL_TYPE_ARRAY
:
312 case GLSL_TYPE_STRUCT
:
313 case GLSL_TYPE_SAMPLER
:
314 /* These should be overridden with the type of the member when
315 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
316 * way to trip up if we don't.
318 return BRW_REGISTER_TYPE_UD
;
320 assert(!"not reached");
321 return BRW_REGISTER_TYPE_F
;
325 /** Automatic reg constructor. */
326 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
331 this->reg
= v
->virtual_grf_alloc(type_size(type
));
332 this->reg_offset
= 0;
333 this->type
= brw_type_for_base_type(type
);
337 fs_visitor::variable_storage(ir_variable
*var
)
339 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
342 /* Our support for uniforms is piggy-backed on the struct
343 * gl_fragment_program, because that's where the values actually
344 * get stored, rather than in some global gl_shader_program uniform
348 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
350 unsigned int offset
= 0;
352 if (type
->is_matrix()) {
353 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
354 type
->vector_elements
,
357 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
358 offset
+= setup_uniform_values(loc
+ offset
, column
);
364 switch (type
->base_type
) {
365 case GLSL_TYPE_FLOAT
:
369 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
370 unsigned int param
= c
->prog_data
.nr_params
++;
372 assert(param
< ARRAY_SIZE(c
->prog_data
.param
));
374 switch (type
->base_type
) {
375 case GLSL_TYPE_FLOAT
:
376 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
379 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2U
;
382 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2I
;
385 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2B
;
388 assert(!"not reached");
389 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
392 this->param_index
[param
] = loc
;
393 this->param_offset
[param
] = i
;
397 case GLSL_TYPE_STRUCT
:
398 for (unsigned int i
= 0; i
< type
->length
; i
++) {
399 offset
+= setup_uniform_values(loc
+ offset
,
400 type
->fields
.structure
[i
].type
);
404 case GLSL_TYPE_ARRAY
:
405 for (unsigned int i
= 0; i
< type
->length
; i
++) {
406 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
410 case GLSL_TYPE_SAMPLER
:
411 /* The sampler takes up a slot, but we don't use any values from it. */
415 assert(!"not reached");
421 /* Our support for builtin uniforms is even scarier than non-builtin.
422 * It sits on top of the PROG_STATE_VAR parameters that are
423 * automatically updated from GL context state.
426 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
428 const ir_state_slot
*const slots
= ir
->state_slots
;
429 assert(ir
->state_slots
!= NULL
);
431 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
432 /* This state reference has already been setup by ir_to_mesa, but we'll
433 * get the same index back here.
435 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
436 (gl_state_index
*)slots
[i
].tokens
);
438 /* Add each of the unique swizzles of the element as a parameter.
439 * This'll end up matching the expected layout of the
440 * array/matrix/structure we're trying to fill in.
443 for (unsigned int j
= 0; j
< 4; j
++) {
444 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
445 if (swiz
== last_swiz
)
449 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
451 this->param_index
[c
->prog_data
.nr_params
] = index
;
452 this->param_offset
[c
->prog_data
.nr_params
] = swiz
;
453 c
->prog_data
.nr_params
++;
459 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
461 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
463 fs_reg neg_y
= this->pixel_y
;
465 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
468 if (ir
->pixel_center_integer
) {
469 emit(BRW_OPCODE_MOV
, wpos
, this->pixel_x
);
471 emit(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
));
476 if (!flip
&& ir
->pixel_center_integer
) {
477 emit(BRW_OPCODE_MOV
, wpos
, this->pixel_y
);
479 fs_reg pixel_y
= this->pixel_y
;
480 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
483 pixel_y
.negate
= true;
484 offset
+= c
->key
.drawable_height
- 1.0;
487 emit(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
));
492 if (intel
->gen
>= 6) {
493 emit(BRW_OPCODE_MOV
, wpos
,
494 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0)));
496 emit(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
497 interp_reg(FRAG_ATTRIB_WPOS
, 2));
501 /* gl_FragCoord.w: Already set up in emit_interpolation */
502 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
508 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
510 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
511 /* Interpolation is always in floating point regs. */
512 reg
->type
= BRW_REGISTER_TYPE_F
;
515 unsigned int array_elements
;
516 const glsl_type
*type
;
518 if (ir
->type
->is_array()) {
519 array_elements
= ir
->type
->length
;
520 if (array_elements
== 0) {
521 fail("dereferenced array '%s' has length 0\n", ir
->name
);
523 type
= ir
->type
->fields
.array
;
529 int location
= ir
->location
;
530 for (unsigned int i
= 0; i
< array_elements
; i
++) {
531 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
532 if (urb_setup
[location
] == -1) {
533 /* If there's no incoming setup data for this slot, don't
534 * emit interpolation for it.
536 attr
.reg_offset
+= type
->vector_elements
;
542 location
== FRAG_ATTRIB_COL0
|| location
== FRAG_ATTRIB_COL1
;
544 if (c
->key
.flat_shade
&& is_gl_Color
) {
545 /* Constant interpolation (flat shading) case. The SF has
546 * handed us defined values in only the constant offset
547 * field of the setup reg.
549 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
550 struct brw_reg interp
= interp_reg(location
, k
);
551 interp
= suboffset(interp
, 3);
552 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
556 /* Perspective interpolation case. */
557 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
558 struct brw_reg interp
= interp_reg(location
, k
);
559 emit(FS_OPCODE_LINTERP
, attr
,
560 this->delta_x
, this->delta_y
, fs_reg(interp
));
564 if (intel
->gen
< 6 && !(is_gl_Color
&& c
->key
.linear_color
)) {
565 attr
.reg_offset
-= type
->vector_elements
;
566 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
567 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
580 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
582 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
584 /* The frontfacing comes in as a bit in the thread payload. */
585 if (intel
->gen
>= 6) {
586 emit(BRW_OPCODE_ASR
, *reg
,
587 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
589 emit(BRW_OPCODE_NOT
, *reg
, *reg
);
590 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1));
592 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
593 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
596 fs_inst
*inst
= emit(BRW_OPCODE_CMP
, *reg
,
599 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
600 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u));
607 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src
)
619 assert(!"not reached: bad math opcode");
623 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
624 * might be able to do better by doing execsize = 1 math and then
625 * expanding that result out, but we would need to be careful with
628 * The hardware ignores source modifiers (negate and abs) on math
629 * instructions, so we also move to a temp to set those up.
631 if (intel
->gen
>= 6 && (src
.file
== UNIFORM
||
634 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
635 emit(BRW_OPCODE_MOV
, expanded
, src
);
639 fs_inst
*inst
= emit(opcode
, dst
, src
);
641 if (intel
->gen
< 6) {
643 inst
->mlen
= c
->dispatch_width
/ 8;
650 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
655 assert(opcode
== FS_OPCODE_POW
);
657 if (intel
->gen
>= 6) {
658 /* Can't do hstride == 0 args to gen6 math, so expand it out.
660 * The hardware ignores source modifiers (negate and abs) on math
661 * instructions, so we also move to a temp to set those up.
663 if (src0
.file
== UNIFORM
|| src0
.abs
|| src0
.negate
) {
664 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
665 emit(BRW_OPCODE_MOV
, expanded
, src0
);
669 if (src1
.file
== UNIFORM
|| src1
.abs
|| src1
.negate
) {
670 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
671 emit(BRW_OPCODE_MOV
, expanded
, src1
);
675 inst
= emit(opcode
, dst
, src0
, src1
);
677 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1), src1
);
678 inst
= emit(opcode
, dst
, src0
, reg_null_f
);
680 inst
->base_mrf
= base_mrf
;
681 inst
->mlen
= 2 * c
->dispatch_width
/ 8;
687 fs_visitor::visit(ir_variable
*ir
)
691 if (variable_storage(ir
))
694 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
695 this->frag_color
= ir
;
696 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
697 this->frag_data
= ir
;
698 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
699 this->frag_depth
= ir
;
702 if (ir
->mode
== ir_var_in
) {
703 if (!strcmp(ir
->name
, "gl_FragCoord")) {
704 reg
= emit_fragcoord_interpolation(ir
);
705 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
706 reg
= emit_frontfacing_interpolation(ir
);
708 reg
= emit_general_interpolation(ir
);
711 hash_table_insert(this->variable_ht
, reg
, ir
);
715 if (ir
->mode
== ir_var_uniform
) {
716 int param_index
= c
->prog_data
.nr_params
;
718 if (!strncmp(ir
->name
, "gl_", 3)) {
719 setup_builtin_uniform_values(ir
);
721 setup_uniform_values(ir
->location
, ir
->type
);
724 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
725 reg
->type
= brw_type_for_base_type(ir
->type
);
729 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
731 hash_table_insert(this->variable_ht
, reg
, ir
);
735 fs_visitor::visit(ir_dereference_variable
*ir
)
737 fs_reg
*reg
= variable_storage(ir
->var
);
742 fs_visitor::visit(ir_dereference_record
*ir
)
744 const glsl_type
*struct_type
= ir
->record
->type
;
746 ir
->record
->accept(this);
748 unsigned int offset
= 0;
749 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
750 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
752 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
754 this->result
.reg_offset
+= offset
;
755 this->result
.type
= brw_type_for_base_type(ir
->type
);
759 fs_visitor::visit(ir_dereference_array
*ir
)
764 ir
->array
->accept(this);
765 index
= ir
->array_index
->as_constant();
767 element_size
= type_size(ir
->type
);
768 this->result
.type
= brw_type_for_base_type(ir
->type
);
771 assert(this->result
.file
== UNIFORM
||
772 (this->result
.file
== GRF
&&
773 this->result
.reg
!= 0));
774 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
776 assert(!"FINISHME: non-constant array element");
780 /* Instruction selection: Produce a MOV.sat instead of
781 * MIN(MAX(val, 0), 1) when possible.
784 fs_visitor::try_emit_saturate(ir_expression
*ir
)
786 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
791 sat_val
->accept(this);
792 fs_reg src
= this->result
;
794 this->result
= fs_reg(this, ir
->type
);
795 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, this->result
, src
);
796 inst
->saturate
= true;
802 brw_conditional_for_comparison(unsigned int op
)
806 return BRW_CONDITIONAL_L
;
807 case ir_binop_greater
:
808 return BRW_CONDITIONAL_G
;
809 case ir_binop_lequal
:
810 return BRW_CONDITIONAL_LE
;
811 case ir_binop_gequal
:
812 return BRW_CONDITIONAL_GE
;
814 case ir_binop_all_equal
: /* same as equal for scalars */
815 return BRW_CONDITIONAL_Z
;
816 case ir_binop_nequal
:
817 case ir_binop_any_nequal
: /* same as nequal for scalars */
818 return BRW_CONDITIONAL_NZ
;
820 assert(!"not reached: bad operation for comparison");
821 return BRW_CONDITIONAL_NZ
;
826 fs_visitor::visit(ir_expression
*ir
)
828 unsigned int operand
;
832 assert(ir
->get_num_operands() <= 2);
834 if (try_emit_saturate(ir
))
837 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
838 ir
->operands
[operand
]->accept(this);
839 if (this->result
.file
== BAD_FILE
) {
841 fail("Failed to get tree for expression operand:\n");
842 ir
->operands
[operand
]->accept(&v
);
844 op
[operand
] = this->result
;
846 /* Matrix expression operands should have been broken down to vector
847 * operations already.
849 assert(!ir
->operands
[operand
]->type
->is_matrix());
850 /* And then those vector operands should have been broken down to scalar.
852 assert(!ir
->operands
[operand
]->type
->is_vector());
855 /* Storage for our result. If our result goes into an assignment, it will
856 * just get copy-propagated out, so no worries.
858 this->result
= fs_reg(this, ir
->type
);
860 switch (ir
->operation
) {
861 case ir_unop_logic_not
:
862 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
863 * ones complement of the whole register, not just bit 0.
865 emit(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1));
868 op
[0].negate
= !op
[0].negate
;
869 this->result
= op
[0];
873 op
[0].negate
= false;
874 this->result
= op
[0];
877 temp
= fs_reg(this, ir
->type
);
879 emit(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
));
881 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
882 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
883 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
));
884 inst
->predicated
= true;
886 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
887 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
888 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
));
889 inst
->predicated
= true;
893 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
897 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
900 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
904 assert(!"not reached: should be handled by ir_explog_to_explog2");
907 case ir_unop_sin_reduced
:
908 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
911 case ir_unop_cos_reduced
:
912 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
916 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
919 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
923 emit(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]);
926 assert(!"not reached: should be handled by ir_sub_to_add_neg");
930 emit(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]);
933 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
936 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
940 case ir_binop_greater
:
941 case ir_binop_lequal
:
942 case ir_binop_gequal
:
944 case ir_binop_all_equal
:
945 case ir_binop_nequal
:
946 case ir_binop_any_nequal
:
948 /* original gen4 does implicit conversion before comparison. */
950 temp
.type
= op
[0].type
;
952 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
953 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
954 emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1));
957 case ir_binop_logic_xor
:
958 emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
961 case ir_binop_logic_or
:
962 emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
965 case ir_binop_logic_and
:
966 emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
971 assert(!"not reached: should be handled by brw_fs_channel_expressions");
975 assert(!"not reached: should be handled by lower_noise");
978 case ir_quadop_vector
:
979 assert(!"not reached: should be handled by lower_quadop_vector");
983 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
987 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
994 emit(BRW_OPCODE_MOV
, this->result
, op
[0]);
999 /* original gen4 does implicit conversion before comparison. */
1001 temp
.type
= op
[0].type
;
1003 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], fs_reg(0.0f
));
1004 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1005 inst
= emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(1));
1009 emit(BRW_OPCODE_RNDZ
, this->result
, op
[0]);
1012 op
[0].negate
= !op
[0].negate
;
1013 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
1014 this->result
.negate
= true;
1017 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
1020 inst
= emit(BRW_OPCODE_FRC
, this->result
, op
[0]);
1022 case ir_unop_round_even
:
1023 emit(BRW_OPCODE_RNDE
, this->result
, op
[0]);
1027 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
1028 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1030 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
1031 inst
->predicated
= true;
1034 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
1035 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1037 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
1038 inst
->predicated
= true;
1042 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
1045 case ir_unop_bit_not
:
1046 inst
= emit(BRW_OPCODE_NOT
, this->result
, op
[0]);
1048 case ir_binop_bit_and
:
1049 inst
= emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
1051 case ir_binop_bit_xor
:
1052 inst
= emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
1054 case ir_binop_bit_or
:
1055 inst
= emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
1059 case ir_binop_lshift
:
1060 case ir_binop_rshift
:
1061 assert(!"GLSL 1.30 features unsupported");
1067 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1068 const glsl_type
*type
, bool predicated
)
1070 switch (type
->base_type
) {
1071 case GLSL_TYPE_FLOAT
:
1072 case GLSL_TYPE_UINT
:
1074 case GLSL_TYPE_BOOL
:
1075 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1076 l
.type
= brw_type_for_base_type(type
);
1077 r
.type
= brw_type_for_base_type(type
);
1079 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, l
, r
);
1080 inst
->predicated
= predicated
;
1086 case GLSL_TYPE_ARRAY
:
1087 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1088 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1092 case GLSL_TYPE_STRUCT
:
1093 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1094 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1099 case GLSL_TYPE_SAMPLER
:
1103 assert(!"not reached");
1109 fs_visitor::visit(ir_assignment
*ir
)
1114 /* FINISHME: arrays on the lhs */
1115 ir
->lhs
->accept(this);
1118 ir
->rhs
->accept(this);
1121 assert(l
.file
!= BAD_FILE
);
1122 assert(r
.file
!= BAD_FILE
);
1124 if (ir
->condition
) {
1125 emit_bool_to_cond_code(ir
->condition
);
1128 if (ir
->lhs
->type
->is_scalar() ||
1129 ir
->lhs
->type
->is_vector()) {
1130 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1131 if (ir
->write_mask
& (1 << i
)) {
1132 inst
= emit(BRW_OPCODE_MOV
, l
, r
);
1134 inst
->predicated
= true;
1140 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1145 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1149 bool simd16
= false;
1155 if (ir
->shadow_comparitor
) {
1156 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1157 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
1158 coordinate
.reg_offset
++;
1160 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1163 if (ir
->op
== ir_tex
) {
1164 /* There's no plain shadow compare message, so we use shadow
1165 * compare with a bias of 0.0.
1167 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
));
1169 } else if (ir
->op
== ir_txb
) {
1170 ir
->lod_info
.bias
->accept(this);
1171 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1174 assert(ir
->op
== ir_txl
);
1175 ir
->lod_info
.lod
->accept(this);
1176 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1180 ir
->shadow_comparitor
->accept(this);
1181 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1183 } else if (ir
->op
== ir_tex
) {
1184 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1185 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
1186 coordinate
.reg_offset
++;
1188 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1190 } else if (ir
->op
== ir_txd
) {
1191 assert(!"TXD isn't supported on gen4 yet.");
1193 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1194 * instructions. We'll need to do SIMD16 here.
1196 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1198 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1199 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), coordinate
);
1200 coordinate
.reg_offset
++;
1203 /* lod/bias appears after u/v/r. */
1206 if (ir
->op
== ir_txb
) {
1207 ir
->lod_info
.bias
->accept(this);
1208 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1211 ir
->lod_info
.lod
->accept(this);
1212 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1216 /* The unused upper half. */
1219 /* Now, since we're doing simd16, the return is 2 interleaved
1220 * vec4s where the odd-indexed ones are junk. We'll need to move
1221 * this weirdness around to the expected layout.
1225 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1227 dst
.type
= BRW_REGISTER_TYPE_F
;
1230 fs_inst
*inst
= NULL
;
1233 inst
= emit(FS_OPCODE_TEX
, dst
);
1236 inst
= emit(FS_OPCODE_TXB
, dst
);
1239 inst
= emit(FS_OPCODE_TXL
, dst
);
1242 inst
= emit(FS_OPCODE_TXD
, dst
);
1245 assert(!"GLSL 1.30 features unsupported");
1248 inst
->base_mrf
= base_mrf
;
1252 for (int i
= 0; i
< 4; i
++) {
1253 emit(BRW_OPCODE_MOV
, orig_dst
, dst
);
1254 orig_dst
.reg_offset
++;
1255 dst
.reg_offset
+= 2;
1262 /* gen5's sampler has slots for u, v, r, array index, then optional
1263 * parameters like shadow comparitor or LOD bias. If optional
1264 * parameters aren't present, those base slots are optional and don't
1265 * need to be included in the message.
1267 * We don't fill in the unnecessary slots regardless, which may look
1268 * surprising in the disassembly.
1271 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1273 int mlen
= 1; /* g0 header always present. */
1275 int reg_width
= c
->dispatch_width
/ 8;
1277 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1278 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
),
1280 coordinate
.reg_offset
++;
1282 mlen
+= ir
->coordinate
->type
->vector_elements
* reg_width
;
1284 if (ir
->shadow_comparitor
) {
1285 mlen
= MAX2(mlen
, 1 + 4 * reg_width
);
1287 ir
->shadow_comparitor
->accept(this);
1288 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1292 fs_inst
*inst
= NULL
;
1295 inst
= emit(FS_OPCODE_TEX
, dst
);
1298 ir
->lod_info
.bias
->accept(this);
1299 mlen
= MAX2(mlen
, 1 + 4 * reg_width
);
1300 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1303 inst
= emit(FS_OPCODE_TXB
, dst
);
1307 ir
->lod_info
.lod
->accept(this);
1308 mlen
= MAX2(mlen
, 1 + 4 * reg_width
);
1309 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1312 inst
= emit(FS_OPCODE_TXL
, dst
);
1316 assert(!"GLSL 1.30 features unsupported");
1319 inst
->base_mrf
= base_mrf
;
1323 fail("Message length >11 disallowed by hardware\n");
1330 fs_visitor::visit(ir_texture
*ir
)
1333 fs_inst
*inst
= NULL
;
1335 ir
->coordinate
->accept(this);
1336 fs_reg coordinate
= this->result
;
1338 if (ir
->offset
!= NULL
) {
1339 ir_constant
*offset
= ir
->offset
->as_constant();
1340 assert(offset
!= NULL
);
1342 signed char offsets
[3];
1343 for (unsigned i
= 0; i
< ir
->offset
->type
->vector_elements
; i
++)
1344 offsets
[i
] = (signed char) offset
->value
.i
[i
];
1346 /* Combine all three offsets into a single unsigned dword:
1348 * bits 11:8 - U Offset (X component)
1349 * bits 7:4 - V Offset (Y component)
1350 * bits 3:0 - R Offset (Z component)
1352 unsigned offset_bits
= 0;
1353 for (unsigned i
= 0; i
< ir
->offset
->type
->vector_elements
; i
++) {
1354 const unsigned shift
= 4 * (2 - i
);
1355 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
1358 /* Explicitly set up the message header by copying g0 to msg reg m1. */
1359 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 1, BRW_REGISTER_TYPE_UD
),
1360 fs_reg(GRF
, 0, BRW_REGISTER_TYPE_UD
));
1362 /* Then set the offset bits in DWord 2 of the message header. */
1363 emit(BRW_OPCODE_MOV
,
1364 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 1, 2),
1365 BRW_REGISTER_TYPE_UD
)),
1366 fs_reg(brw_imm_uw(offset_bits
)));
1369 /* Should be lowered by do_lower_texture_projection */
1370 assert(!ir
->projector
);
1372 sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
1373 ctx
->Shader
.CurrentFragmentProgram
,
1374 &brw
->fragment_program
->Base
);
1375 sampler
= c
->fp
->program
.Base
.SamplerUnits
[sampler
];
1377 /* The 965 requires the EU to do the normalization of GL rectangle
1378 * texture coordinates. We use the program parameter state
1379 * tracking to get the scaling factor.
1381 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1382 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1383 int tokens
[STATE_LENGTH
] = {
1385 STATE_TEXRECT_SCALE
,
1391 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
1393 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
+ 1] =
1396 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1397 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1398 GLuint index
= _mesa_add_state_reference(params
,
1399 (gl_state_index
*)tokens
);
1401 this->param_index
[c
->prog_data
.nr_params
] = index
;
1402 this->param_offset
[c
->prog_data
.nr_params
] = 0;
1403 c
->prog_data
.nr_params
++;
1404 this->param_index
[c
->prog_data
.nr_params
] = index
;
1405 this->param_offset
[c
->prog_data
.nr_params
] = 1;
1406 c
->prog_data
.nr_params
++;
1408 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1409 fs_reg src
= coordinate
;
1412 emit(BRW_OPCODE_MUL
, dst
, src
, scale_x
);
1415 emit(BRW_OPCODE_MUL
, dst
, src
, scale_y
);
1418 /* Writemasking doesn't eliminate channels on SIMD8 texture
1419 * samples, so don't worry about them.
1421 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1423 if (intel
->gen
< 5) {
1424 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1426 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1429 /* If there's an offset, we already set up m1. To avoid the implied move,
1430 * use the null register. Otherwise, we want an implied move from g0.
1432 if (ir
->offset
!= NULL
)
1433 inst
->src
[0] = fs_reg(brw_null_reg());
1435 inst
->src
[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
));
1437 inst
->sampler
= sampler
;
1441 if (ir
->shadow_comparitor
)
1442 inst
->shadow_compare
= true;
1444 if (ir
->type
== glsl_type::float_type
) {
1445 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1446 assert(ir
->sampler
->type
->sampler_shadow
);
1447 } else if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1448 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1450 for (int i
= 0; i
< 4; i
++) {
1451 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1452 fs_reg l
= swizzle_dst
;
1455 if (swiz
== SWIZZLE_ZERO
) {
1456 emit(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
));
1457 } else if (swiz
== SWIZZLE_ONE
) {
1458 emit(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
));
1461 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1462 emit(BRW_OPCODE_MOV
, l
, r
);
1465 this->result
= swizzle_dst
;
1470 fs_visitor::visit(ir_swizzle
*ir
)
1472 ir
->val
->accept(this);
1473 fs_reg val
= this->result
;
1475 if (ir
->type
->vector_elements
== 1) {
1476 this->result
.reg_offset
+= ir
->mask
.x
;
1480 fs_reg result
= fs_reg(this, ir
->type
);
1481 this->result
= result
;
1483 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1484 fs_reg channel
= val
;
1502 channel
.reg_offset
+= swiz
;
1503 emit(BRW_OPCODE_MOV
, result
, channel
);
1504 result
.reg_offset
++;
1509 fs_visitor::visit(ir_discard
*ir
)
1511 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1513 assert(ir
->condition
== NULL
); /* FINISHME */
1515 emit(FS_OPCODE_DISCARD_NOT
, temp
, reg_null_d
);
1516 emit(FS_OPCODE_DISCARD_AND
, reg_null_d
, temp
);
1517 kill_emitted
= true;
1521 fs_visitor::visit(ir_constant
*ir
)
1523 /* Set this->result to reg at the bottom of the function because some code
1524 * paths will cause this visitor to be applied to other fields. This will
1525 * cause the value stored in this->result to be modified.
1527 * Make reg constant so that it doesn't get accidentally modified along the
1528 * way. Yes, I actually had this problem. :(
1530 const fs_reg
reg(this, ir
->type
);
1531 fs_reg dst_reg
= reg
;
1533 if (ir
->type
->is_array()) {
1534 const unsigned size
= type_size(ir
->type
->fields
.array
);
1536 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1537 ir
->array_elements
[i
]->accept(this);
1538 fs_reg src_reg
= this->result
;
1540 dst_reg
.type
= src_reg
.type
;
1541 for (unsigned j
= 0; j
< size
; j
++) {
1542 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1543 src_reg
.reg_offset
++;
1544 dst_reg
.reg_offset
++;
1547 } else if (ir
->type
->is_record()) {
1548 foreach_list(node
, &ir
->components
) {
1549 ir_instruction
*const field
= (ir_instruction
*) node
;
1550 const unsigned size
= type_size(field
->type
);
1552 field
->accept(this);
1553 fs_reg src_reg
= this->result
;
1555 dst_reg
.type
= src_reg
.type
;
1556 for (unsigned j
= 0; j
< size
; j
++) {
1557 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1558 src_reg
.reg_offset
++;
1559 dst_reg
.reg_offset
++;
1563 const unsigned size
= type_size(ir
->type
);
1565 for (unsigned i
= 0; i
< size
; i
++) {
1566 switch (ir
->type
->base_type
) {
1567 case GLSL_TYPE_FLOAT
:
1568 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.f
[i
]));
1570 case GLSL_TYPE_UINT
:
1571 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.u
[i
]));
1574 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.i
[i
]));
1576 case GLSL_TYPE_BOOL
:
1577 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg((int)ir
->value
.b
[i
]));
1580 assert(!"Non-float/uint/int/bool constant");
1582 dst_reg
.reg_offset
++;
1590 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1592 ir_expression
*expr
= ir
->as_expression();
1598 assert(expr
->get_num_operands() <= 2);
1599 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1600 assert(expr
->operands
[i
]->type
->is_scalar());
1602 expr
->operands
[i
]->accept(this);
1603 op
[i
] = this->result
;
1606 switch (expr
->operation
) {
1607 case ir_unop_logic_not
:
1608 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1));
1609 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1612 case ir_binop_logic_xor
:
1613 inst
= emit(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]);
1614 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1617 case ir_binop_logic_or
:
1618 inst
= emit(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]);
1619 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1622 case ir_binop_logic_and
:
1623 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]);
1624 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1628 if (intel
->gen
>= 6) {
1629 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0.0f
));
1631 inst
= emit(BRW_OPCODE_MOV
, reg_null_f
, op
[0]);
1633 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1637 if (intel
->gen
>= 6) {
1638 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0));
1640 inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, op
[0]);
1642 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1645 case ir_binop_greater
:
1646 case ir_binop_gequal
:
1648 case ir_binop_lequal
:
1649 case ir_binop_equal
:
1650 case ir_binop_all_equal
:
1651 case ir_binop_nequal
:
1652 case ir_binop_any_nequal
:
1653 inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, op
[0], op
[1]);
1654 inst
->conditional_mod
=
1655 brw_conditional_for_comparison(expr
->operation
);
1659 assert(!"not reached");
1660 fail("bad cond code\n");
1668 if (intel
->gen
>= 6) {
1669 fs_inst
*inst
= emit(BRW_OPCODE_AND
, reg_null_d
, this->result
, fs_reg(1));
1670 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1672 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, this->result
);
1673 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1678 * Emit a gen6 IF statement with the comparison folded into the IF
1682 fs_visitor::emit_if_gen6(ir_if
*ir
)
1684 ir_expression
*expr
= ir
->condition
->as_expression();
1691 assert(expr
->get_num_operands() <= 2);
1692 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1693 assert(expr
->operands
[i
]->type
->is_scalar());
1695 expr
->operands
[i
]->accept(this);
1696 op
[i
] = this->result
;
1699 switch (expr
->operation
) {
1700 case ir_unop_logic_not
:
1701 inst
= emit(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(0));
1702 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1705 case ir_binop_logic_xor
:
1706 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1707 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1710 case ir_binop_logic_or
:
1711 temp
= fs_reg(this, glsl_type::bool_type
);
1712 emit(BRW_OPCODE_OR
, temp
, op
[0], op
[1]);
1713 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1714 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1717 case ir_binop_logic_and
:
1718 temp
= fs_reg(this, glsl_type::bool_type
);
1719 emit(BRW_OPCODE_AND
, temp
, op
[0], op
[1]);
1720 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1721 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1725 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1726 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1730 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1731 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1734 case ir_binop_greater
:
1735 case ir_binop_gequal
:
1737 case ir_binop_lequal
:
1738 case ir_binop_equal
:
1739 case ir_binop_all_equal
:
1740 case ir_binop_nequal
:
1741 case ir_binop_any_nequal
:
1742 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1743 inst
->conditional_mod
=
1744 brw_conditional_for_comparison(expr
->operation
);
1747 assert(!"not reached");
1748 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1749 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1750 fail("bad condition\n");
1756 ir
->condition
->accept(this);
1758 fs_inst
*inst
= emit(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0));
1759 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1763 fs_visitor::visit(ir_if
*ir
)
1767 if (c
->dispatch_width
== 16) {
1768 fail("Can't support (non-uniform) control flow on 16-wide\n");
1771 /* Don't point the annotation at the if statement, because then it plus
1772 * the then and else blocks get printed.
1774 this->base_ir
= ir
->condition
;
1776 if (intel
->gen
>= 6) {
1779 emit_bool_to_cond_code(ir
->condition
);
1781 inst
= emit(BRW_OPCODE_IF
);
1782 inst
->predicated
= true;
1785 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1786 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1792 if (!ir
->else_instructions
.is_empty()) {
1793 emit(BRW_OPCODE_ELSE
);
1795 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1796 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1803 emit(BRW_OPCODE_ENDIF
);
1807 fs_visitor::visit(ir_loop
*ir
)
1809 fs_reg counter
= reg_undef
;
1811 if (c
->dispatch_width
== 16) {
1812 fail("Can't support (non-uniform) control flow on 16-wide\n");
1816 this->base_ir
= ir
->counter
;
1817 ir
->counter
->accept(this);
1818 counter
= *(variable_storage(ir
->counter
));
1821 this->base_ir
= ir
->from
;
1822 ir
->from
->accept(this);
1824 emit(BRW_OPCODE_MOV
, counter
, this->result
);
1828 emit(BRW_OPCODE_DO
);
1831 this->base_ir
= ir
->to
;
1832 ir
->to
->accept(this);
1834 fs_inst
*inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, counter
, this->result
);
1835 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->cmp
);
1837 inst
= emit(BRW_OPCODE_BREAK
);
1838 inst
->predicated
= true;
1841 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1842 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1848 if (ir
->increment
) {
1849 this->base_ir
= ir
->increment
;
1850 ir
->increment
->accept(this);
1851 emit(BRW_OPCODE_ADD
, counter
, counter
, this->result
);
1854 emit(BRW_OPCODE_WHILE
);
1858 fs_visitor::visit(ir_loop_jump
*ir
)
1861 case ir_loop_jump::jump_break
:
1862 emit(BRW_OPCODE_BREAK
);
1864 case ir_loop_jump::jump_continue
:
1865 emit(BRW_OPCODE_CONTINUE
);
1871 fs_visitor::visit(ir_call
*ir
)
1873 assert(!"FINISHME");
1877 fs_visitor::visit(ir_return
*ir
)
1879 assert(!"FINISHME");
1883 fs_visitor::visit(ir_function
*ir
)
1885 /* Ignore function bodies other than main() -- we shouldn't see calls to
1886 * them since they should all be inlined before we get to ir_to_mesa.
1888 if (strcmp(ir
->name
, "main") == 0) {
1889 const ir_function_signature
*sig
;
1892 sig
= ir
->matching_signature(&empty
);
1896 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1897 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1906 fs_visitor::visit(ir_function_signature
*ir
)
1908 assert(!"not reached");
1913 fs_visitor::emit(fs_inst inst
)
1915 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1918 if (force_uncompressed_stack
> 0)
1919 list_inst
->force_uncompressed
= true;
1920 else if (force_sechalf_stack
> 0)
1921 list_inst
->force_sechalf
= true;
1923 list_inst
->annotation
= this->current_annotation
;
1924 list_inst
->ir
= this->base_ir
;
1926 this->instructions
.push_tail(list_inst
);
1931 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1933 fs_visitor::emit_dummy_fs()
1935 /* Everyone's favorite color. */
1936 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 2), fs_reg(1.0f
));
1937 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 3), fs_reg(0.0f
));
1938 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 4), fs_reg(1.0f
));
1939 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 5), fs_reg(0.0f
));
1942 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
1943 write
->base_mrf
= 0;
1946 /* The register location here is relative to the start of the URB
1947 * data. It will get adjusted to be a real location before
1948 * generate_code() time.
1951 fs_visitor::interp_reg(int location
, int channel
)
1953 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1954 int stride
= (channel
& 1) * 4;
1956 assert(urb_setup
[location
] != -1);
1958 return brw_vec1_grf(regnr
, stride
);
1961 /** Emits the interpolation for the varying inputs. */
1963 fs_visitor::emit_interpolation_setup_gen4()
1965 this->current_annotation
= "compute pixel centers";
1966 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1967 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1968 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1969 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1971 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
1972 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
1974 this->current_annotation
= "compute pixel deltas from v0";
1976 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1977 this->delta_y
= this->delta_x
;
1978 this->delta_y
.reg_offset
++;
1980 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1981 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1983 emit(BRW_OPCODE_ADD
, this->delta_x
,
1984 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0))));
1985 emit(BRW_OPCODE_ADD
, this->delta_y
,
1986 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1))));
1988 this->current_annotation
= "compute pos.w and 1/pos.w";
1989 /* Compute wpos.w. It's always in our setup, since it's needed to
1990 * interpolate the other attributes.
1992 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1993 emit(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1994 interp_reg(FRAG_ATTRIB_WPOS
, 3));
1995 /* Compute the pixel 1/W value from wpos.w. */
1996 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1997 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1998 this->current_annotation
= NULL
;
2001 /** Emits the interpolation for the varying inputs. */
2003 fs_visitor::emit_interpolation_setup_gen6()
2005 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
2007 /* If the pixel centers end up used, the setup is the same as for gen4. */
2008 this->current_annotation
= "compute pixel centers";
2009 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
2010 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
2011 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2012 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
2013 emit(BRW_OPCODE_ADD
,
2015 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
2016 fs_reg(brw_imm_v(0x10101010)));
2017 emit(BRW_OPCODE_ADD
,
2019 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
2020 fs_reg(brw_imm_v(0x11001100)));
2022 /* As of gen6, we can no longer mix float and int sources. We have
2023 * to turn the integer pixel centers into floats for their actual
2026 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
2027 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
2028 emit(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
);
2029 emit(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
);
2031 this->current_annotation
= "compute pos.w";
2032 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
2033 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
2034 emit_math(FS_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
2036 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
2037 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
2039 this->current_annotation
= NULL
;
2043 fs_visitor::emit_fb_writes()
2045 this->current_annotation
= "FB write header";
2046 GLboolean header_present
= GL_TRUE
;
2048 int reg_width
= c
->dispatch_width
/ 8;
2050 if (intel
->gen
>= 6 &&
2051 !this->kill_emitted
&&
2052 c
->key
.nr_color_regions
== 1) {
2053 header_present
= false;
2056 if (header_present
) {
2061 if (c
->aa_dest_stencil_reg
) {
2062 push_force_uncompressed();
2063 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2064 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0)));
2065 pop_force_uncompressed();
2068 /* Reserve space for color. It'll be filled in per MRT below. */
2070 nr
+= 4 * reg_width
;
2072 if (c
->source_depth_to_render_target
) {
2073 if (intel
->gen
== 6 && c
->dispatch_width
== 16) {
2074 /* For outputting oDepth on gen6, SIMD8 writes have to be
2075 * used. This would require 8-wide moves of each half to
2076 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2077 * Just bail on doing so for now.
2079 fail("Missing support for simd16 depth writes on gen6\n");
2082 if (c
->computes_depth
) {
2083 /* Hand over gl_FragDepth. */
2084 assert(this->frag_depth
);
2085 fs_reg depth
= *(variable_storage(this->frag_depth
));
2087 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
), depth
);
2089 /* Pass through the payload depth. */
2090 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
2091 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0)));
2096 if (c
->dest_depth_reg
) {
2097 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
2098 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0)));
2102 fs_reg color
= reg_undef
;
2103 if (this->frag_color
)
2104 color
= *(variable_storage(this->frag_color
));
2105 else if (this->frag_data
) {
2106 color
= *(variable_storage(this->frag_data
));
2107 color
.type
= BRW_REGISTER_TYPE_F
;
2110 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2111 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2112 "FB write target %d",
2114 if (this->frag_color
|| this->frag_data
) {
2115 for (int i
= 0; i
< 4; i
++) {
2116 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, color_mrf
+ i
* reg_width
), color
);
2121 if (this->frag_color
)
2122 color
.reg_offset
-= 4;
2124 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2125 inst
->target
= target
;
2128 if (target
== c
->key
.nr_color_regions
- 1)
2130 inst
->header_present
= header_present
;
2133 if (c
->key
.nr_color_regions
== 0) {
2134 if (c
->key
.alpha_test
&& (this->frag_color
|| this->frag_data
)) {
2135 /* If the alpha test is enabled but there's no color buffer,
2136 * we still need to send alpha out the pipeline to our null
2139 color
.reg_offset
+= 3;
2140 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, color_mrf
+ 3), color
);
2143 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2147 inst
->header_present
= header_present
;
2150 this->current_annotation
= NULL
;
2154 fs_visitor::generate_fb_write(fs_inst
*inst
)
2156 GLboolean eot
= inst
->eot
;
2157 struct brw_reg implied_header
;
2159 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
2162 brw_push_insn_state(p
);
2163 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2164 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2166 if (inst
->header_present
) {
2167 if (intel
->gen
>= 6) {
2169 brw_message_reg(inst
->base_mrf
),
2170 brw_vec8_grf(0, 0));
2172 if (inst
->target
> 0) {
2173 /* Set the render target index for choosing BLEND_STATE. */
2174 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 2),
2175 BRW_REGISTER_TYPE_UD
),
2176 brw_imm_ud(inst
->target
));
2179 /* Clear viewport index, render target array index. */
2180 brw_AND(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 0),
2181 BRW_REGISTER_TYPE_UD
),
2182 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2183 brw_imm_ud(0xf7ff));
2185 implied_header
= brw_null_reg();
2187 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2191 brw_message_reg(inst
->base_mrf
+ 1),
2192 brw_vec8_grf(1, 0));
2194 implied_header
= brw_null_reg();
2197 brw_pop_insn_state(p
);
2207 inst
->header_present
);
2210 /* Computes the integer pixel x,y values from the origin.
2212 * This is the basis of gl_FragCoord computation, but is also used
2213 * pre-gen6 for computing the deltas from v0 for computing
2217 fs_visitor::generate_pixel_xy(struct brw_reg dst
, bool is_x
)
2219 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
2221 struct brw_reg deltas
;
2224 src
= stride(suboffset(g1_uw
, 4), 2, 4, 0);
2225 deltas
= brw_imm_v(0x10101010);
2227 src
= stride(suboffset(g1_uw
, 5), 2, 4, 0);
2228 deltas
= brw_imm_v(0x11001100);
2231 if (c
->dispatch_width
== 16) {
2235 /* We do this 8 or 16-wide, but since the destination is UW we
2236 * don't do compression in the 16-wide case.
2238 brw_push_insn_state(p
);
2239 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2240 brw_ADD(p
, dst
, src
, deltas
);
2241 brw_pop_insn_state(p
);
2245 fs_visitor::generate_linterp(fs_inst
*inst
,
2246 struct brw_reg dst
, struct brw_reg
*src
)
2248 struct brw_reg delta_x
= src
[0];
2249 struct brw_reg delta_y
= src
[1];
2250 struct brw_reg interp
= src
[2];
2253 delta_y
.nr
== delta_x
.nr
+ 1 &&
2254 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2255 brw_PLN(p
, dst
, interp
, delta_x
);
2257 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2258 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2263 fs_visitor::generate_math(fs_inst
*inst
,
2264 struct brw_reg dst
, struct brw_reg
*src
)
2268 switch (inst
->opcode
) {
2270 op
= BRW_MATH_FUNCTION_INV
;
2273 op
= BRW_MATH_FUNCTION_RSQ
;
2275 case FS_OPCODE_SQRT
:
2276 op
= BRW_MATH_FUNCTION_SQRT
;
2278 case FS_OPCODE_EXP2
:
2279 op
= BRW_MATH_FUNCTION_EXP
;
2281 case FS_OPCODE_LOG2
:
2282 op
= BRW_MATH_FUNCTION_LOG
;
2285 op
= BRW_MATH_FUNCTION_POW
;
2288 op
= BRW_MATH_FUNCTION_SIN
;
2291 op
= BRW_MATH_FUNCTION_COS
;
2294 assert(!"not reached: unknown math function");
2299 if (intel
->gen
>= 6) {
2300 assert(inst
->mlen
== 0);
2302 if (inst
->opcode
== FS_OPCODE_POW
) {
2303 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2304 brw_math2(p
, dst
, op
, src
[0], src
[1]);
2306 if (c
->dispatch_width
== 16) {
2307 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
2308 brw_math2(p
, sechalf(dst
), op
, sechalf(src
[0]), sechalf(src
[1]));
2309 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
2312 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2315 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2316 BRW_MATH_SATURATE_NONE
,
2318 BRW_MATH_DATA_VECTOR
,
2319 BRW_MATH_PRECISION_FULL
);
2321 if (c
->dispatch_width
== 16) {
2322 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
2323 brw_math(p
, sechalf(dst
),
2325 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2326 BRW_MATH_SATURATE_NONE
,
2328 BRW_MATH_DATA_VECTOR
,
2329 BRW_MATH_PRECISION_FULL
);
2330 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
2334 assert(inst
->mlen
>= 1);
2336 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2339 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2340 BRW_MATH_SATURATE_NONE
,
2341 inst
->base_mrf
, src
[0],
2342 BRW_MATH_DATA_VECTOR
,
2343 BRW_MATH_PRECISION_FULL
);
2345 if (c
->dispatch_width
== 16) {
2346 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
2347 brw_math(p
, sechalf(dst
),
2349 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2350 BRW_MATH_SATURATE_NONE
,
2351 inst
->base_mrf
+ 1, sechalf(src
[0]),
2352 BRW_MATH_DATA_VECTOR
,
2353 BRW_MATH_PRECISION_FULL
);
2354 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
2360 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2364 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2366 if (c
->dispatch_width
== 16) {
2369 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2372 if (intel
->gen
>= 5) {
2373 switch (inst
->opcode
) {
2375 if (inst
->shadow_compare
) {
2376 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
2378 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
2382 if (inst
->shadow_compare
) {
2383 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
2385 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
2389 if (inst
->shadow_compare
) {
2390 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
2392 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
2396 assert(!"TXD isn't supported on gen5+ yet.");
2400 switch (inst
->opcode
) {
2402 /* Note that G45 and older determines shadow compare and dispatch width
2403 * from message length for most messages.
2405 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2406 if (inst
->shadow_compare
) {
2407 assert(inst
->mlen
== 6);
2409 assert(inst
->mlen
<= 4);
2413 if (inst
->shadow_compare
) {
2414 assert(inst
->mlen
== 6);
2415 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
2417 assert(inst
->mlen
== 9);
2418 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2419 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2423 if (inst
->shadow_compare
) {
2424 assert(inst
->mlen
== 6);
2425 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
2427 assert(inst
->mlen
== 9);
2428 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
2429 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2433 assert(!"TXD isn't supported on gen4 yet.");
2437 assert(msg_type
!= -1);
2440 retype(dst
, BRW_REGISTER_TYPE_UW
),
2443 SURF_INDEX_TEXTURE(inst
->sampler
),
2455 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2458 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2460 * and we're trying to produce:
2463 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2464 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2465 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2466 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2467 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2468 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2469 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2470 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2472 * and add another set of two more subspans if in 16-pixel dispatch mode.
2474 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2475 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2476 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2477 * between each other. We could probably do it like ddx and swizzle the right
2478 * order later, but bail for now and just produce
2479 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2482 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2484 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2485 BRW_REGISTER_TYPE_F
,
2486 BRW_VERTICAL_STRIDE_2
,
2488 BRW_HORIZONTAL_STRIDE_0
,
2489 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2490 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2491 BRW_REGISTER_TYPE_F
,
2492 BRW_VERTICAL_STRIDE_2
,
2494 BRW_HORIZONTAL_STRIDE_0
,
2495 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2496 brw_ADD(p
, dst
, src0
, negate(src1
));
2500 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2502 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2503 BRW_REGISTER_TYPE_F
,
2504 BRW_VERTICAL_STRIDE_4
,
2506 BRW_HORIZONTAL_STRIDE_0
,
2507 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2508 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2509 BRW_REGISTER_TYPE_F
,
2510 BRW_VERTICAL_STRIDE_4
,
2512 BRW_HORIZONTAL_STRIDE_0
,
2513 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2514 brw_ADD(p
, dst
, src0
, negate(src1
));
2518 fs_visitor::generate_discard_not(fs_inst
*inst
, struct brw_reg mask
)
2520 if (intel
->gen
>= 6) {
2521 /* Gen6 no longer has the mask reg for us to just read the
2522 * active channels from. However, cmp updates just the channels
2523 * of the flag reg that are enabled, so we can get at the
2524 * channel enables that way. In this step, make a reg of ones
2527 brw_MOV(p
, mask
, brw_imm_ud(1));
2529 brw_push_insn_state(p
);
2530 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2531 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2532 brw_NOT(p
, mask
, brw_mask_reg(1)); /* IMASK */
2533 brw_pop_insn_state(p
);
2538 fs_visitor::generate_discard_and(fs_inst
*inst
, struct brw_reg mask
)
2540 if (intel
->gen
>= 6) {
2541 struct brw_reg f0
= brw_flag_reg();
2542 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
2544 brw_push_insn_state(p
);
2545 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2546 brw_MOV(p
, f0
, brw_imm_uw(0xffff)); /* inactive channels undiscarded */
2547 brw_pop_insn_state(p
);
2549 brw_CMP(p
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
2550 BRW_CONDITIONAL_Z
, mask
, brw_imm_ud(0)); /* active channels fail test */
2551 /* Undo CMP's whacking of predication*/
2552 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2554 brw_push_insn_state(p
);
2555 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2556 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2557 brw_AND(p
, g1
, f0
, g1
);
2558 brw_pop_insn_state(p
);
2560 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2562 mask
= brw_uw1_reg(mask
.file
, mask
.nr
, 0);
2564 brw_push_insn_state(p
);
2565 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2566 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2567 brw_AND(p
, g0
, mask
, g0
);
2568 brw_pop_insn_state(p
);
2573 fs_visitor::generate_spill(fs_inst
*inst
, struct brw_reg src
)
2575 assert(inst
->mlen
!= 0);
2578 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
2579 retype(src
, BRW_REGISTER_TYPE_UD
));
2580 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
), 1,
2585 fs_visitor::generate_unspill(fs_inst
*inst
, struct brw_reg dst
)
2587 assert(inst
->mlen
!= 0);
2589 /* Clear any post destination dependencies that would be ignored by
2590 * the block read. See the B-Spec for pre-gen5 send instruction.
2592 * This could use a better solution, since texture sampling and
2593 * math reads could potentially run into it as well -- anywhere
2594 * that we have a SEND with a destination that is a register that
2595 * was written but not read within the last N instructions (what's
2596 * N? unsure). This is rare because of dead code elimination, but
2599 if (intel
->gen
== 4 && !intel
->is_g4x
)
2600 brw_MOV(p
, brw_null_reg(), dst
);
2602 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
), 1,
2605 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2606 /* gen4 errata: destination from a send can't be used as a
2607 * destination until it's been read. Just read it so we don't
2610 brw_MOV(p
, brw_null_reg(), dst
);
2616 fs_visitor::generate_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
)
2618 assert(inst
->mlen
!= 0);
2620 /* Clear any post destination dependencies that would be ignored by
2621 * the block read. See the B-Spec for pre-gen5 send instruction.
2623 * This could use a better solution, since texture sampling and
2624 * math reads could potentially run into it as well -- anywhere
2625 * that we have a SEND with a destination that is a register that
2626 * was written but not read within the last N instructions (what's
2627 * N? unsure). This is rare because of dead code elimination, but
2630 if (intel
->gen
== 4 && !intel
->is_g4x
)
2631 brw_MOV(p
, brw_null_reg(), dst
);
2633 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
2634 inst
->offset
, SURF_INDEX_FRAG_CONST_BUFFER
);
2636 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2637 /* gen4 errata: destination from a send can't be used as a
2638 * destination until it's been read. Just read it so we don't
2641 brw_MOV(p
, brw_null_reg(), dst
);
2646 * To be called after the last _mesa_add_state_reference() call, to
2647 * set up prog_data.param[] for assign_curb_setup() and
2648 * setup_pull_constants().
2651 fs_visitor::setup_paramvalues_refs()
2653 /* Set up the pointers to ParamValues now that that array is finalized. */
2654 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
2655 c
->prog_data
.param
[i
] =
2656 fp
->Base
.Parameters
->ParameterValues
[this->param_index
[i
]] +
2657 this->param_offset
[i
];
2662 fs_visitor::assign_curb_setup()
2664 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2665 if (c
->dispatch_width
== 8) {
2666 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
2668 c
->prog_data
.first_curbe_grf_16
= c
->nr_payload_regs
;
2671 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2672 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2673 fs_inst
*inst
= (fs_inst
*)iter
.get();
2675 for (unsigned int i
= 0; i
< 3; i
++) {
2676 if (inst
->src
[i
].file
== UNIFORM
) {
2677 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2678 struct brw_reg brw_reg
= brw_vec1_grf(c
->nr_payload_regs
+
2682 inst
->src
[i
].file
= FIXED_HW_REG
;
2683 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
2690 fs_visitor::calculate_urb_setup()
2692 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2697 /* Figure out where each of the incoming setup attributes lands. */
2698 if (intel
->gen
>= 6) {
2699 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2700 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2701 urb_setup
[i
] = urb_next
++;
2705 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2706 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2707 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2710 if (i
>= VERT_RESULT_VAR0
)
2711 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2712 else if (i
<= VERT_RESULT_TEX7
)
2718 urb_setup
[fp_index
] = urb_next
++;
2723 /* Each attribute is 4 setup channels, each of which is half a reg. */
2724 c
->prog_data
.urb_read_length
= urb_next
* 2;
2728 fs_visitor::assign_urb_setup()
2730 int urb_start
= c
->nr_payload_regs
+ c
->prog_data
.curb_read_length
;
2732 /* Offset all the urb_setup[] index by the actual position of the
2733 * setup regs, now that the location of the constants has been chosen.
2735 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2736 fs_inst
*inst
= (fs_inst
*)iter
.get();
2738 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
2739 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2740 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2743 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
2744 assert(inst
->src
[0].file
== FIXED_HW_REG
);
2745 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
2749 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2753 * Split large virtual GRFs into separate components if we can.
2755 * This is mostly duplicated with what brw_fs_vector_splitting does,
2756 * but that's really conservative because it's afraid of doing
2757 * splitting that doesn't result in real progress after the rest of
2758 * the optimization phases, which would cause infinite looping in
2759 * optimization. We can do it once here, safely. This also has the
2760 * opportunity to split interpolated values, or maybe even uniforms,
2761 * which we don't have at the IR level.
2763 * We want to split, because virtual GRFs are what we register
2764 * allocate and spill (due to contiguousness requirements for some
2765 * instructions), and they're what we naturally generate in the
2766 * codegen process, but most virtual GRFs don't actually need to be
2767 * contiguous sets of GRFs. If we split, we'll end up with reduced
2768 * live intervals and better dead code elimination and coalescing.
2771 fs_visitor::split_virtual_grfs()
2773 int num_vars
= this->virtual_grf_next
;
2774 bool split_grf
[num_vars
];
2775 int new_virtual_grf
[num_vars
];
2777 /* Try to split anything > 0 sized. */
2778 for (int i
= 0; i
< num_vars
; i
++) {
2779 if (this->virtual_grf_sizes
[i
] != 1)
2780 split_grf
[i
] = true;
2782 split_grf
[i
] = false;
2786 /* PLN opcodes rely on the delta_xy being contiguous. */
2787 split_grf
[this->delta_x
.reg
] = false;
2790 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2791 fs_inst
*inst
= (fs_inst
*)iter
.get();
2793 /* Texturing produces 4 contiguous registers, so no splitting. */
2794 if (inst
->is_tex()) {
2795 split_grf
[inst
->dst
.reg
] = false;
2799 /* Allocate new space for split regs. Note that the virtual
2800 * numbers will be contiguous.
2802 for (int i
= 0; i
< num_vars
; i
++) {
2804 new_virtual_grf
[i
] = virtual_grf_alloc(1);
2805 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
2806 int reg
= virtual_grf_alloc(1);
2807 assert(reg
== new_virtual_grf
[i
] + j
- 1);
2810 this->virtual_grf_sizes
[i
] = 1;
2814 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2815 fs_inst
*inst
= (fs_inst
*)iter
.get();
2817 if (inst
->dst
.file
== GRF
&&
2818 split_grf
[inst
->dst
.reg
] &&
2819 inst
->dst
.reg_offset
!= 0) {
2820 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
2821 inst
->dst
.reg_offset
- 1);
2822 inst
->dst
.reg_offset
= 0;
2824 for (int i
= 0; i
< 3; i
++) {
2825 if (inst
->src
[i
].file
== GRF
&&
2826 split_grf
[inst
->src
[i
].reg
] &&
2827 inst
->src
[i
].reg_offset
!= 0) {
2828 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
2829 inst
->src
[i
].reg_offset
- 1);
2830 inst
->src
[i
].reg_offset
= 0;
2834 this->live_intervals_valid
= false;
2838 * Choose accesses from the UNIFORM file to demote to using the pull
2841 * We allow a fragment shader to have more than the specified minimum
2842 * maximum number of fragment shader uniform components (64). If
2843 * there are too many of these, they'd fill up all of register space.
2844 * So, this will push some of them out to the pull constant buffer and
2845 * update the program to load them.
2848 fs_visitor::setup_pull_constants()
2850 /* Only allow 16 registers (128 uniform components) as push constants. */
2851 unsigned int max_uniform_components
= 16 * 8;
2852 if (c
->prog_data
.nr_params
<= max_uniform_components
)
2855 /* Just demote the end of the list. We could probably do better
2856 * here, demoting things that are rarely used in the program first.
2858 int pull_uniform_base
= max_uniform_components
;
2859 int pull_uniform_count
= c
->prog_data
.nr_params
- pull_uniform_base
;
2861 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2862 fs_inst
*inst
= (fs_inst
*)iter
.get();
2864 for (int i
= 0; i
< 3; i
++) {
2865 if (inst
->src
[i
].file
!= UNIFORM
)
2868 int uniform_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2869 if (uniform_nr
< pull_uniform_base
)
2872 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
2873 fs_inst
*pull
= new(mem_ctx
) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
2875 pull
->offset
= ((uniform_nr
- pull_uniform_base
) * 4) & ~15;
2876 pull
->ir
= inst
->ir
;
2877 pull
->annotation
= inst
->annotation
;
2878 pull
->base_mrf
= 14;
2881 inst
->insert_before(pull
);
2883 inst
->src
[i
].file
= GRF
;
2884 inst
->src
[i
].reg
= dst
.reg
;
2885 inst
->src
[i
].reg_offset
= 0;
2886 inst
->src
[i
].smear
= (uniform_nr
- pull_uniform_base
) & 3;
2890 for (int i
= 0; i
< pull_uniform_count
; i
++) {
2891 c
->prog_data
.pull_param
[i
] = c
->prog_data
.param
[pull_uniform_base
+ i
];
2892 c
->prog_data
.pull_param_convert
[i
] =
2893 c
->prog_data
.param_convert
[pull_uniform_base
+ i
];
2895 c
->prog_data
.nr_params
-= pull_uniform_count
;
2896 c
->prog_data
.nr_pull_params
= pull_uniform_count
;
2900 fs_visitor::calculate_live_intervals()
2902 int num_vars
= this->virtual_grf_next
;
2903 int *def
= ralloc_array(mem_ctx
, int, num_vars
);
2904 int *use
= ralloc_array(mem_ctx
, int, num_vars
);
2907 int bb_header_ip
= 0;
2909 if (this->live_intervals_valid
)
2912 for (int i
= 0; i
< num_vars
; i
++) {
2913 def
[i
] = MAX_INSTRUCTION
;
2918 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2919 fs_inst
*inst
= (fs_inst
*)iter
.get();
2921 if (inst
->opcode
== BRW_OPCODE_DO
) {
2922 if (loop_depth
++ == 0)
2924 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2927 if (loop_depth
== 0) {
2928 /* Patches up the use of vars marked for being live across
2931 for (int i
= 0; i
< num_vars
; i
++) {
2932 if (use
[i
] == loop_start
) {
2938 for (unsigned int i
= 0; i
< 3; i
++) {
2939 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2940 int reg
= inst
->src
[i
].reg
;
2945 def
[reg
] = MIN2(loop_start
, def
[reg
]);
2946 use
[reg
] = loop_start
;
2948 /* Nobody else is going to go smash our start to
2949 * later in the loop now, because def[reg] now
2950 * points before the bb header.
2955 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2956 int reg
= inst
->dst
.reg
;
2959 def
[reg
] = MIN2(def
[reg
], ip
);
2961 def
[reg
] = MIN2(def
[reg
], loop_start
);
2968 /* Set the basic block header IP. This is used for determining
2969 * if a complete def of single-register virtual GRF in a loop
2970 * dominates a use in the same basic block. It's a quick way to
2971 * reduce the live interval range of most register used in a
2974 if (inst
->opcode
== BRW_OPCODE_IF
||
2975 inst
->opcode
== BRW_OPCODE_ELSE
||
2976 inst
->opcode
== BRW_OPCODE_ENDIF
||
2977 inst
->opcode
== BRW_OPCODE_DO
||
2978 inst
->opcode
== BRW_OPCODE_WHILE
||
2979 inst
->opcode
== BRW_OPCODE_BREAK
||
2980 inst
->opcode
== BRW_OPCODE_CONTINUE
) {
2985 ralloc_free(this->virtual_grf_def
);
2986 ralloc_free(this->virtual_grf_use
);
2987 this->virtual_grf_def
= def
;
2988 this->virtual_grf_use
= use
;
2990 this->live_intervals_valid
= true;
2994 * Attempts to move immediate constants into the immediate
2995 * constant slot of following instructions.
2997 * Immediate constants are a bit tricky -- they have to be in the last
2998 * operand slot, you can't do abs/negate on them,
3002 fs_visitor::propagate_constants()
3004 bool progress
= false;
3006 /* Need to update the MRF tracking for compressed instructions. */
3007 if (c
->dispatch_width
== 16)
3010 calculate_live_intervals();
3012 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3013 fs_inst
*inst
= (fs_inst
*)iter
.get();
3015 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3017 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
3018 inst
->dst
.type
!= inst
->src
[0].type
)
3021 /* Don't bother with cases where we should have had the
3022 * operation on the constant folded in GLSL already.
3027 /* Found a move of a constant to a GRF. Find anything else using the GRF
3028 * before it's written, and replace it with the constant if we can.
3030 exec_list_iterator scan_iter
= iter
;
3032 for (; scan_iter
.has_next(); scan_iter
.next()) {
3033 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
3035 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
3036 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
3037 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
3038 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
3042 for (int i
= 2; i
>= 0; i
--) {
3043 if (scan_inst
->src
[i
].file
!= GRF
||
3044 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
3045 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
3048 /* Don't bother with cases where we should have had the
3049 * operation on the constant folded in GLSL already.
3051 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
3054 switch (scan_inst
->opcode
) {
3055 case BRW_OPCODE_MOV
:
3056 scan_inst
->src
[i
] = inst
->src
[0];
3060 case BRW_OPCODE_MUL
:
3061 case BRW_OPCODE_ADD
:
3063 scan_inst
->src
[i
] = inst
->src
[0];
3065 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
3066 /* Fit this constant in by commuting the operands */
3067 scan_inst
->src
[0] = scan_inst
->src
[1];
3068 scan_inst
->src
[1] = inst
->src
[0];
3073 case BRW_OPCODE_CMP
:
3075 scan_inst
->src
[i
] = inst
->src
[0];
3077 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
3080 new_cmod
= brw_swap_cmod(scan_inst
->conditional_mod
);
3081 if (new_cmod
!= ~0u) {
3082 /* Fit this constant in by swapping the operands and
3085 scan_inst
->src
[0] = scan_inst
->src
[1];
3086 scan_inst
->src
[1] = inst
->src
[0];
3087 scan_inst
->conditional_mod
= new_cmod
;
3093 case BRW_OPCODE_SEL
:
3095 scan_inst
->src
[i
] = inst
->src
[0];
3097 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
3098 /* Fit this constant in by swapping the operands and
3099 * flipping the predicate
3101 scan_inst
->src
[0] = scan_inst
->src
[1];
3102 scan_inst
->src
[1] = inst
->src
[0];
3103 scan_inst
->predicate_inverse
= !scan_inst
->predicate_inverse
;
3110 if (scan_inst
->dst
.file
== GRF
&&
3111 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
3112 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
3113 scan_inst
->is_tex())) {
3120 this->live_intervals_valid
= false;
3125 * Must be called after calculate_live_intervales() to remove unused
3126 * writes to registers -- register allocation will fail otherwise
3127 * because something deffed but not used won't be considered to
3128 * interfere with other regs.
3131 fs_visitor::dead_code_eliminate()
3133 bool progress
= false;
3136 calculate_live_intervals();
3138 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3139 fs_inst
*inst
= (fs_inst
*)iter
.get();
3141 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
3150 live_intervals_valid
= false;
3156 fs_visitor::register_coalesce()
3158 bool progress
= false;
3162 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3163 fs_inst
*inst
= (fs_inst
*)iter
.get();
3165 /* Make sure that we dominate the instructions we're going to
3166 * scan for interfering with our coalescing, or we won't have
3167 * scanned enough to see if anything interferes with our
3168 * coalescing. We don't dominate the following instructions if
3169 * we're in a loop or an if block.
3171 switch (inst
->opcode
) {
3175 case BRW_OPCODE_WHILE
:
3181 case BRW_OPCODE_ENDIF
:
3185 if (loop_depth
|| if_depth
)
3188 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3191 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
3192 inst
->dst
.type
!= inst
->src
[0].type
)
3195 bool has_source_modifiers
= inst
->src
[0].abs
|| inst
->src
[0].negate
;
3197 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
3198 * them: check for no writes to either one until the exit of the
3201 bool interfered
= false;
3202 exec_list_iterator scan_iter
= iter
;
3204 for (; scan_iter
.has_next(); scan_iter
.next()) {
3205 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
3207 if (scan_inst
->dst
.file
== GRF
) {
3208 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
3209 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
3210 scan_inst
->is_tex())) {
3214 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
3215 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
3216 scan_inst
->is_tex())) {
3222 /* The gen6 MATH instruction can't handle source modifiers, so avoid
3223 * coalescing those for now. We should do something more specific.
3225 if (intel
->gen
== 6 && scan_inst
->is_math() && has_source_modifiers
) {
3234 /* Rewrite the later usage to point at the source of the move to
3237 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
3239 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
3241 for (int i
= 0; i
< 3; i
++) {
3242 if (scan_inst
->src
[i
].file
== GRF
&&
3243 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
3244 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
3245 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
3246 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
3247 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
3248 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
3249 scan_inst
->src
[i
].smear
= inst
->src
[0].smear
;
3259 live_intervals_valid
= false;
3266 fs_visitor::compute_to_mrf()
3268 bool progress
= false;
3271 /* Need to update the MRF tracking for compressed instructions. */
3272 if (c
->dispatch_width
== 16)
3275 calculate_live_intervals();
3277 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3278 fs_inst
*inst
= (fs_inst
*)iter
.get();
3283 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3285 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
3286 inst
->dst
.type
!= inst
->src
[0].type
||
3287 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
3290 /* Can't compute-to-MRF this GRF if someone else was going to
3293 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
3296 /* Found a move of a GRF to a MRF. Let's see if we can go
3297 * rewrite the thing that made this GRF to write into the MRF.
3300 for (scan_inst
= (fs_inst
*)inst
->prev
;
3301 scan_inst
->prev
!= NULL
;
3302 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
3303 if (scan_inst
->dst
.file
== GRF
&&
3304 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
3305 /* Found the last thing to write our reg we want to turn
3306 * into a compute-to-MRF.
3309 if (scan_inst
->is_tex()) {
3310 /* texturing writes several continuous regs, so we can't
3311 * compute-to-mrf that.
3316 /* If it's predicated, it (probably) didn't populate all
3319 if (scan_inst
->predicated
)
3322 /* SEND instructions can't have MRF as a destination. */
3323 if (scan_inst
->mlen
)
3326 if (intel
->gen
>= 6) {
3327 /* gen6 math instructions must have the destination be
3328 * GRF, so no compute-to-MRF for them.
3330 if (scan_inst
->is_math()) {
3335 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
3336 /* Found the creator of our MRF's source value. */
3337 scan_inst
->dst
.file
= MRF
;
3338 scan_inst
->dst
.hw_reg
= inst
->dst
.hw_reg
;
3339 scan_inst
->saturate
|= inst
->saturate
;
3346 /* We don't handle flow control here. Most computation of
3347 * values that end up in MRFs are shortly before the MRF
3350 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
3351 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
3352 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
3353 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
3357 /* You can't read from an MRF, so if someone else reads our
3358 * MRF's source GRF that we wanted to rewrite, that stops us.
3360 bool interfered
= false;
3361 for (int i
= 0; i
< 3; i
++) {
3362 if (scan_inst
->src
[i
].file
== GRF
&&
3363 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
3364 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
3371 if (scan_inst
->dst
.file
== MRF
&&
3372 scan_inst
->dst
.hw_reg
== inst
->dst
.hw_reg
) {
3373 /* Somebody else wrote our MRF here, so we can't can't
3374 * compute-to-MRF before that.
3379 if (scan_inst
->mlen
> 0) {
3380 /* Found a SEND instruction, which means that there are
3381 * live values in MRFs from base_mrf to base_mrf +
3382 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3385 if (inst
->dst
.hw_reg
>= scan_inst
->base_mrf
&&
3386 inst
->dst
.hw_reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
3397 * Walks through basic blocks, locking for repeated MRF writes and
3398 * removing the later ones.
3401 fs_visitor::remove_duplicate_mrf_writes()
3403 fs_inst
*last_mrf_move
[16];
3404 bool progress
= false;
3406 /* Need to update the MRF tracking for compressed instructions. */
3407 if (c
->dispatch_width
== 16)
3410 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3412 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3413 fs_inst
*inst
= (fs_inst
*)iter
.get();
3415 switch (inst
->opcode
) {
3417 case BRW_OPCODE_WHILE
:
3419 case BRW_OPCODE_ELSE
:
3420 case BRW_OPCODE_ENDIF
:
3421 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3427 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3428 inst
->dst
.file
== MRF
) {
3429 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.hw_reg
];
3430 if (prev_inst
&& inst
->equals(prev_inst
)) {
3437 /* Clear out the last-write records for MRFs that were overwritten. */
3438 if (inst
->dst
.file
== MRF
) {
3439 last_mrf_move
[inst
->dst
.hw_reg
] = NULL
;
3442 if (inst
->mlen
> 0) {
3443 /* Found a SEND instruction, which will include two or fewer
3444 * implied MRF writes. We could do better here.
3446 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3447 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3451 /* Clear out any MRF move records whose sources got overwritten. */
3452 if (inst
->dst
.file
== GRF
) {
3453 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
3454 if (last_mrf_move
[i
] &&
3455 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
3456 last_mrf_move
[i
] = NULL
;
3461 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3462 inst
->dst
.file
== MRF
&&
3463 inst
->src
[0].file
== GRF
&&
3464 !inst
->predicated
) {
3465 last_mrf_move
[inst
->dst
.hw_reg
] = inst
;
3473 fs_visitor::virtual_grf_interferes(int a
, int b
)
3475 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
3476 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
3478 /* We can't handle dead register writes here, without iterating
3479 * over the whole instruction stream to find every single dead
3480 * write to that register to compare to the live interval of the
3481 * other register. Just assert that dead_code_eliminate() has been
3484 assert((this->virtual_grf_use
[a
] != -1 ||
3485 this->virtual_grf_def
[a
] == MAX_INSTRUCTION
) &&
3486 (this->virtual_grf_use
[b
] != -1 ||
3487 this->virtual_grf_def
[b
] == MAX_INSTRUCTION
));
3489 /* If the register is used to store 16 values of less than float
3490 * size (only the case for pixel_[xy]), then we can't allocate
3491 * another dword-sized thing to that register that would be used in
3492 * the same instruction. This is because when the GPU decodes (for
3495 * (declare (in ) vec4 gl_FragCoord@0x97766a0)
3496 * add(16) g6<1>F g6<8,8,1>UW 0.5F { align1 compr };
3498 * it's actually processed as:
3499 * add(8) g6<1>F g6<8,8,1>UW 0.5F { align1 };
3500 * add(8) g7<1>F g6.8<8,8,1>UW 0.5F { align1 sechalf };
3502 * so our second half values in g6 got overwritten in the first
3505 if (c
->dispatch_width
== 16 && (this->pixel_x
.reg
== a
||
3506 this->pixel_x
.reg
== b
||
3507 this->pixel_y
.reg
== a
||
3508 this->pixel_y
.reg
== b
)) {
3509 return start
<= end
;
3515 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
3517 struct brw_reg brw_reg
;
3519 switch (reg
->file
) {
3523 if (reg
->smear
== -1) {
3524 brw_reg
= brw_vec8_reg(reg
->file
,
3527 brw_reg
= brw_vec1_reg(reg
->file
,
3528 reg
->hw_reg
, reg
->smear
);
3530 brw_reg
= retype(brw_reg
, reg
->type
);
3533 switch (reg
->type
) {
3534 case BRW_REGISTER_TYPE_F
:
3535 brw_reg
= brw_imm_f(reg
->imm
.f
);
3537 case BRW_REGISTER_TYPE_D
:
3538 brw_reg
= brw_imm_d(reg
->imm
.i
);
3540 case BRW_REGISTER_TYPE_UD
:
3541 brw_reg
= brw_imm_ud(reg
->imm
.u
);
3544 assert(!"not reached");
3545 brw_reg
= brw_null_reg();
3550 brw_reg
= reg
->fixed_hw_reg
;
3553 /* Probably unused. */
3554 brw_reg
= brw_null_reg();
3557 assert(!"not reached");
3558 brw_reg
= brw_null_reg();
3561 assert(!"not reached");
3562 brw_reg
= brw_null_reg();
3566 brw_reg
= brw_abs(brw_reg
);
3568 brw_reg
= negate(brw_reg
);
3574 fs_visitor::generate_code()
3576 int last_native_inst
= p
->nr_insn
;
3577 const char *last_annotation_string
= NULL
;
3578 ir_instruction
*last_annotation_ir
= NULL
;
3580 int if_stack_array_size
= 16;
3581 int loop_stack_array_size
= 16;
3582 int if_stack_depth
= 0, loop_stack_depth
= 0;
3583 brw_instruction
**if_stack
=
3584 rzalloc_array(this->mem_ctx
, brw_instruction
*, if_stack_array_size
);
3585 brw_instruction
**loop_stack
=
3586 rzalloc_array(this->mem_ctx
, brw_instruction
*, loop_stack_array_size
);
3587 int *if_depth_in_loop
=
3588 rzalloc_array(this->mem_ctx
, int, loop_stack_array_size
);
3591 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3592 printf("Native code for fragment shader %d (%d-wide dispatch):\n",
3593 ctx
->Shader
.CurrentFragmentProgram
->Name
, c
->dispatch_width
);
3596 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3597 fs_inst
*inst
= (fs_inst
*)iter
.get();
3598 struct brw_reg src
[3], dst
;
3600 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3601 if (last_annotation_ir
!= inst
->ir
) {
3602 last_annotation_ir
= inst
->ir
;
3603 if (last_annotation_ir
) {
3605 last_annotation_ir
->print();
3609 if (last_annotation_string
!= inst
->annotation
) {
3610 last_annotation_string
= inst
->annotation
;
3611 if (last_annotation_string
)
3612 printf(" %s\n", last_annotation_string
);
3616 for (unsigned int i
= 0; i
< 3; i
++) {
3617 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
3619 dst
= brw_reg_from_fs_reg(&inst
->dst
);
3621 brw_set_conditionalmod(p
, inst
->conditional_mod
);
3622 brw_set_predicate_control(p
, inst
->predicated
);
3623 brw_set_predicate_inverse(p
, inst
->predicate_inverse
);
3624 brw_set_saturate(p
, inst
->saturate
);
3626 if (inst
->force_uncompressed
|| c
->dispatch_width
== 8) {
3627 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
3628 } else if (inst
->force_sechalf
) {
3629 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
3631 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
3634 switch (inst
->opcode
) {
3635 case BRW_OPCODE_MOV
:
3636 brw_MOV(p
, dst
, src
[0]);
3638 case BRW_OPCODE_ADD
:
3639 brw_ADD(p
, dst
, src
[0], src
[1]);
3641 case BRW_OPCODE_MUL
:
3642 brw_MUL(p
, dst
, src
[0], src
[1]);
3645 case BRW_OPCODE_FRC
:
3646 brw_FRC(p
, dst
, src
[0]);
3648 case BRW_OPCODE_RNDD
:
3649 brw_RNDD(p
, dst
, src
[0]);
3651 case BRW_OPCODE_RNDE
:
3652 brw_RNDE(p
, dst
, src
[0]);
3654 case BRW_OPCODE_RNDZ
:
3655 brw_RNDZ(p
, dst
, src
[0]);
3658 case BRW_OPCODE_AND
:
3659 brw_AND(p
, dst
, src
[0], src
[1]);
3662 brw_OR(p
, dst
, src
[0], src
[1]);
3664 case BRW_OPCODE_XOR
:
3665 brw_XOR(p
, dst
, src
[0], src
[1]);
3667 case BRW_OPCODE_NOT
:
3668 brw_NOT(p
, dst
, src
[0]);
3670 case BRW_OPCODE_ASR
:
3671 brw_ASR(p
, dst
, src
[0], src
[1]);
3673 case BRW_OPCODE_SHR
:
3674 brw_SHR(p
, dst
, src
[0], src
[1]);
3676 case BRW_OPCODE_SHL
:
3677 brw_SHL(p
, dst
, src
[0], src
[1]);
3680 case BRW_OPCODE_CMP
:
3681 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
3683 case BRW_OPCODE_SEL
:
3684 brw_SEL(p
, dst
, src
[0], src
[1]);
3688 if (inst
->src
[0].file
!= BAD_FILE
) {
3689 assert(intel
->gen
>= 6);
3690 if_stack
[if_stack_depth
] = gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
3692 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
3694 if_depth_in_loop
[loop_stack_depth
]++;
3696 if (if_stack_array_size
<= if_stack_depth
) {
3697 if_stack_array_size
*= 2;
3698 if_stack
= reralloc(this->mem_ctx
, if_stack
, brw_instruction
*,
3699 if_stack_array_size
);
3703 case BRW_OPCODE_ELSE
:
3704 if_stack
[if_stack_depth
- 1] =
3705 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
3707 case BRW_OPCODE_ENDIF
:
3709 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
3710 if_depth_in_loop
[loop_stack_depth
]--;
3714 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
3715 if (loop_stack_array_size
<= loop_stack_depth
) {
3716 loop_stack_array_size
*= 2;
3717 loop_stack
= reralloc(this->mem_ctx
, loop_stack
, brw_instruction
*,
3718 loop_stack_array_size
);
3719 if_depth_in_loop
= reralloc(this->mem_ctx
, if_depth_in_loop
, int,
3720 loop_stack_array_size
);
3722 if_depth_in_loop
[loop_stack_depth
] = 0;
3725 case BRW_OPCODE_BREAK
:
3726 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
3727 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3729 case BRW_OPCODE_CONTINUE
:
3730 /* FINISHME: We need to write the loop instruction support still. */
3731 if (intel
->gen
>= 6)
3732 gen6_CONT(p
, loop_stack
[loop_stack_depth
- 1]);
3734 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
3735 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3738 case BRW_OPCODE_WHILE
: {
3739 struct brw_instruction
*inst0
, *inst1
;
3742 if (intel
->gen
>= 5)
3745 assert(loop_stack_depth
> 0);
3747 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
3748 if (intel
->gen
< 6) {
3749 /* patch all the BREAK/CONT instructions from last BGNLOOP */
3750 while (inst0
> loop_stack
[loop_stack_depth
]) {
3752 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
3753 inst0
->bits3
.if_else
.jump_count
== 0) {
3754 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
3756 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
3757 inst0
->bits3
.if_else
.jump_count
== 0) {
3758 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
3767 case FS_OPCODE_SQRT
:
3768 case FS_OPCODE_EXP2
:
3769 case FS_OPCODE_LOG2
:
3773 generate_math(inst
, dst
, src
);
3775 case FS_OPCODE_PIXEL_X
:
3776 generate_pixel_xy(dst
, true);
3778 case FS_OPCODE_PIXEL_Y
:
3779 generate_pixel_xy(dst
, false);
3781 case FS_OPCODE_CINTERP
:
3782 brw_MOV(p
, dst
, src
[0]);
3784 case FS_OPCODE_LINTERP
:
3785 generate_linterp(inst
, dst
, src
);
3791 generate_tex(inst
, dst
, src
[0]);
3793 case FS_OPCODE_DISCARD_NOT
:
3794 generate_discard_not(inst
, dst
);
3796 case FS_OPCODE_DISCARD_AND
:
3797 generate_discard_and(inst
, src
[0]);
3800 generate_ddx(inst
, dst
, src
[0]);
3803 generate_ddy(inst
, dst
, src
[0]);
3806 case FS_OPCODE_SPILL
:
3807 generate_spill(inst
, src
[0]);
3810 case FS_OPCODE_UNSPILL
:
3811 generate_unspill(inst
, dst
);
3814 case FS_OPCODE_PULL_CONSTANT_LOAD
:
3815 generate_pull_constant_load(inst
, dst
);
3818 case FS_OPCODE_FB_WRITE
:
3819 generate_fb_write(inst
);
3822 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
3823 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
3824 brw_opcodes
[inst
->opcode
].name
);
3826 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
3828 fail("unsupported opcode in FS\n");
3831 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3832 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
3834 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3835 ((uint32_t *)&p
->store
[i
])[3],
3836 ((uint32_t *)&p
->store
[i
])[2],
3837 ((uint32_t *)&p
->store
[i
])[1],
3838 ((uint32_t *)&p
->store
[i
])[0]);
3840 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3844 last_native_inst
= p
->nr_insn
;
3847 ralloc_free(if_stack
);
3848 ralloc_free(loop_stack
);
3849 ralloc_free(if_depth_in_loop
);
3853 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
3854 * emit issues, it doesn't get the jump distances into the output,
3855 * which is often something we want to debug. So this is here in
3856 * case you're doing that.
3859 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3860 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3861 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3862 ((uint32_t *)&p
->store
[i
])[3],
3863 ((uint32_t *)&p
->store
[i
])[2],
3864 ((uint32_t *)&p
->store
[i
])[1],
3865 ((uint32_t *)&p
->store
[i
])[0]);
3866 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3875 uint32_t prog_offset_16
= 0;
3877 brw_wm_payload_setup(brw
, c
);
3879 if (c
->dispatch_width
== 16) {
3880 if (c
->prog_data
.curb_read_length
) {
3881 /* Haven't hooked in support for uniforms through the 16-wide
3887 /* align to 64 byte boundary. */
3888 while ((c
->func
.nr_insn
* sizeof(struct brw_instruction
)) % 64) {
3892 /* Save off the start of this 16-wide program in case we succeed. */
3893 prog_offset_16
= c
->func
.nr_insn
* sizeof(struct brw_instruction
);
3895 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
3901 calculate_urb_setup();
3903 emit_interpolation_setup_gen4();
3905 emit_interpolation_setup_gen6();
3907 /* Generate FS IR for main(). (the visitor only descends into
3908 * functions called "main").
3910 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3911 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3918 split_virtual_grfs();
3920 setup_paramvalues_refs();
3921 setup_pull_constants();
3927 progress
= remove_duplicate_mrf_writes() || progress
;
3929 progress
= propagate_constants() || progress
;
3930 progress
= register_coalesce() || progress
;
3931 progress
= compute_to_mrf() || progress
;
3932 progress
= dead_code_eliminate() || progress
;
3935 schedule_instructions();
3937 assign_curb_setup();
3941 /* Debug of register spilling: Go spill everything. */
3942 int virtual_grf_count
= virtual_grf_next
;
3943 for (int i
= 1; i
< virtual_grf_count
; i
++) {
3949 assign_regs_trivial();
3951 while (!assign_regs()) {
3957 assert(force_uncompressed_stack
== 0);
3958 assert(force_sechalf_stack
== 0);
3966 if (c
->dispatch_width
== 8) {
3967 c
->prog_data
.total_grf
= grf_used
;
3969 c
->prog_data
.total_grf_16
= grf_used
;
3970 c
->prog_data
.prog_offset_16
= prog_offset_16
;
3977 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
3979 struct intel_context
*intel
= &brw
->intel
;
3980 struct gl_context
*ctx
= &intel
->ctx
;
3981 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentFragmentProgram
;
3986 struct brw_shader
*shader
=
3987 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3991 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3992 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3993 _mesa_print_ir(shader
->ir
, NULL
);
3997 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3999 c
->dispatch_width
= 8;
4001 fs_visitor
v(c
, shader
);
4003 /* FINISHME: Cleanly fail, test at link time, etc. */
4004 assert(!"not reached");
4008 if (intel
->gen
>= 6) {
4009 c
->dispatch_width
= 16;
4010 fs_visitor
v2(c
, shader
);
4014 c
->prog_data
.dispatch_width
= 8;