2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "main/hash_table.h"
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/fbobject.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/register_allocate.h"
42 #include "program/sampler.h"
43 #include "program/hash_table.h"
44 #include "brw_context.h"
49 #include "brw_dead_control_flow.h"
50 #include "main/uniforms.h"
51 #include "brw_fs_live_variables.h"
52 #include "glsl/glsl_types.h"
57 memset(this, 0, sizeof(*this));
58 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
60 this->dst
= reg_undef
;
61 this->src
[0] = reg_undef
;
62 this->src
[1] = reg_undef
;
63 this->src
[2] = reg_undef
;
65 /* This will be the case for almost all instructions. */
66 this->regs_written
= 1;
72 this->opcode
= BRW_OPCODE_NOP
;
75 fs_inst::fs_inst(enum opcode opcode
)
78 this->opcode
= opcode
;
81 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
)
84 this->opcode
= opcode
;
88 assert(dst
.reg_offset
>= 0);
91 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
)
94 this->opcode
= opcode
;
99 assert(dst
.reg_offset
>= 0);
100 if (src
[0].file
== GRF
)
101 assert(src
[0].reg_offset
>= 0);
104 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
107 this->opcode
= opcode
;
113 assert(dst
.reg_offset
>= 0);
114 if (src
[0].file
== GRF
)
115 assert(src
[0].reg_offset
>= 0);
116 if (src
[1].file
== GRF
)
117 assert(src
[1].reg_offset
>= 0);
120 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
,
121 fs_reg src0
, fs_reg src1
, fs_reg src2
)
124 this->opcode
= opcode
;
131 assert(dst
.reg_offset
>= 0);
132 if (src
[0].file
== GRF
)
133 assert(src
[0].reg_offset
>= 0);
134 if (src
[1].file
== GRF
)
135 assert(src
[1].reg_offset
>= 0);
136 if (src
[2].file
== GRF
)
137 assert(src
[2].reg_offset
>= 0);
142 fs_visitor::op(fs_reg dst, fs_reg src0) \
144 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0); \
149 fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1) \
151 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
156 fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2) \
158 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2);\
189 /** Gen4 predicated IF. */
191 fs_visitor::IF(uint32_t predicate
)
193 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
);
194 inst
->predicate
= predicate
;
198 /** Gen6 IF with embedded comparison. */
200 fs_visitor::IF(fs_reg src0
, fs_reg src1
, uint32_t condition
)
202 assert(brw
->gen
== 6);
203 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
,
204 reg_null_d
, src0
, src1
);
205 inst
->conditional_mod
= condition
;
210 * CMP: Sets the low bit of the destination channels with the result
211 * of the comparison, while the upper bits are undefined, and updates
212 * the flag register with the packed 16 bits of the result.
215 fs_visitor::CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
, uint32_t condition
)
219 /* Take the instruction:
221 * CMP null<d> src0<f> src1<f>
223 * Original gen4 does type conversion to the destination type before
224 * comparison, producing garbage results for floating point comparisons.
225 * gen5 does the comparison on the execution type (resolved source types),
226 * so dst type doesn't matter. gen6 does comparison and then uses the
227 * result as if it was the dst type with no conversion, which happens to
228 * mostly work out for float-interpreted-as-int since our comparisons are
232 dst
.type
= src0
.type
;
233 if (dst
.file
== HW_REG
)
234 dst
.fixed_hw_reg
.type
= dst
.type
;
237 resolve_ud_negate(&src0
);
238 resolve_ud_negate(&src1
);
240 inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_CMP
, dst
, src0
, src1
);
241 inst
->conditional_mod
= condition
;
247 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_reg
&dst
,
248 const fs_reg
&surf_index
,
249 const fs_reg
&varying_offset
,
250 uint32_t const_offset
)
252 exec_list instructions
;
255 /* We have our constant surface use a pitch of 4 bytes, so our index can
256 * be any component of a vector, and then we load 4 contiguous
257 * components starting from that.
259 * We break down the const_offset to a portion added to the variable
260 * offset and a portion done using reg_offset, which means that if you
261 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
262 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
263 * CSE can later notice that those loads are all the same and eliminate
264 * the redundant ones.
266 fs_reg vec4_offset
= fs_reg(this, glsl_type::int_type
);
267 instructions
.push_tail(ADD(vec4_offset
,
268 varying_offset
, const_offset
& ~3));
271 if (brw
->gen
== 4 && dispatch_width
== 8) {
272 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
273 * u, v, r) as parameters, or we can just use the SIMD16 message
274 * consisting of (header, u). We choose the second, at the cost of a
275 * longer return length.
282 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
284 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
285 fs_reg vec4_result
= fs_reg(GRF
, virtual_grf_alloc(4 * scale
), dst
.type
);
286 inst
= new(mem_ctx
) fs_inst(op
, vec4_result
, surf_index
, vec4_offset
);
287 inst
->regs_written
= 4 * scale
;
288 instructions
.push_tail(inst
);
292 inst
->header_present
= true;
296 inst
->mlen
= 1 + dispatch_width
/ 8;
299 vec4_result
.reg_offset
+= (const_offset
& 3) * scale
;
300 instructions
.push_tail(MOV(dst
, vec4_result
));
306 * A helper for MOV generation for fixing up broken hardware SEND dependency
310 fs_visitor::DEP_RESOLVE_MOV(int grf
)
312 fs_inst
*inst
= MOV(brw_null_reg(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
315 inst
->annotation
= "send dependency resolve";
317 /* The caller always wants uncompressed to emit the minimal extra
318 * dependencies, and to avoid having to deal with aligning its regs to 2.
320 inst
->force_uncompressed
= true;
326 fs_inst::equals(fs_inst
*inst
)
328 return (opcode
== inst
->opcode
&&
329 dst
.equals(inst
->dst
) &&
330 src
[0].equals(inst
->src
[0]) &&
331 src
[1].equals(inst
->src
[1]) &&
332 src
[2].equals(inst
->src
[2]) &&
333 saturate
== inst
->saturate
&&
334 predicate
== inst
->predicate
&&
335 conditional_mod
== inst
->conditional_mod
&&
336 mlen
== inst
->mlen
&&
337 base_mrf
== inst
->base_mrf
&&
338 sampler
== inst
->sampler
&&
339 target
== inst
->target
&&
341 header_present
== inst
->header_present
&&
342 shadow_compare
== inst
->shadow_compare
&&
343 offset
== inst
->offset
);
347 fs_inst::overwrites_reg(const fs_reg
®
)
349 return (reg
.file
== dst
.file
&&
350 reg
.reg
== dst
.reg
&&
351 reg
.reg_offset
>= dst
.reg_offset
&&
352 reg
.reg_offset
< dst
.reg_offset
+ regs_written
);
356 fs_inst::is_send_from_grf()
358 return (opcode
== FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
||
359 opcode
== SHADER_OPCODE_SHADER_TIME_ADD
||
360 (opcode
== FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
&&
361 src
[1].file
== GRF
) ||
362 (is_tex() && src
[0].file
== GRF
));
366 fs_visitor::can_do_source_mods(fs_inst
*inst
)
368 if (brw
->gen
== 6 && inst
->is_math())
371 if (inst
->is_send_from_grf())
374 if (!inst
->can_do_source_mods())
383 memset(this, 0, sizeof(*this));
387 /** Generic unset register constructor. */
391 this->file
= BAD_FILE
;
394 /** Immediate value constructor. */
395 fs_reg::fs_reg(float f
)
399 this->type
= BRW_REGISTER_TYPE_F
;
403 /** Immediate value constructor. */
404 fs_reg::fs_reg(int32_t i
)
408 this->type
= BRW_REGISTER_TYPE_D
;
412 /** Immediate value constructor. */
413 fs_reg::fs_reg(uint32_t u
)
417 this->type
= BRW_REGISTER_TYPE_UD
;
421 /** Fixed brw_reg. */
422 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
426 this->fixed_hw_reg
= fixed_hw_reg
;
427 this->type
= fixed_hw_reg
.type
;
431 fs_reg::equals(const fs_reg
&r
) const
433 return (file
== r
.file
&&
435 reg_offset
== r
.reg_offset
&&
436 subreg_offset
== r
.subreg_offset
&&
438 negate
== r
.negate
&&
440 !reladdr
&& !r
.reladdr
&&
441 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
442 sizeof(fixed_hw_reg
)) == 0 &&
443 stride
== r
.stride
&&
448 fs_reg::apply_stride(unsigned stride
)
450 assert((this->stride
* stride
) <= 4 &&
451 (is_power_of_two(stride
) || stride
== 0) &&
452 file
!= HW_REG
&& file
!= IMM
);
453 this->stride
*= stride
;
458 fs_reg::set_smear(unsigned subreg
)
460 assert(file
!= HW_REG
&& file
!= IMM
);
461 subreg_offset
= subreg
* type_sz(type
);
467 fs_reg::is_contiguous() const
473 fs_reg::is_zero() const
478 return type
== BRW_REGISTER_TYPE_F
? imm
.f
== 0.0 : imm
.i
== 0;
482 fs_reg::is_one() const
487 return type
== BRW_REGISTER_TYPE_F
? imm
.f
== 1.0 : imm
.i
== 1;
491 fs_reg::is_null() const
493 return file
== HW_REG
&&
494 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
495 fixed_hw_reg
.nr
== BRW_ARF_NULL
;
499 fs_reg::is_valid_3src() const
501 return file
== GRF
|| file
== UNIFORM
;
505 fs_visitor::type_size(const struct glsl_type
*type
)
507 unsigned int size
, i
;
509 switch (type
->base_type
) {
512 case GLSL_TYPE_FLOAT
:
514 return type
->components();
515 case GLSL_TYPE_ARRAY
:
516 return type_size(type
->fields
.array
) * type
->length
;
517 case GLSL_TYPE_STRUCT
:
519 for (i
= 0; i
< type
->length
; i
++) {
520 size
+= type_size(type
->fields
.structure
[i
].type
);
523 case GLSL_TYPE_SAMPLER
:
524 /* Samplers take up no register space, since they're baked in at
528 case GLSL_TYPE_ATOMIC_UINT
:
530 case GLSL_TYPE_IMAGE
:
532 case GLSL_TYPE_ERROR
:
533 case GLSL_TYPE_INTERFACE
:
534 assert(!"not reached");
542 fs_visitor::get_timestamp()
544 assert(brw
->gen
>= 7);
546 fs_reg ts
= fs_reg(retype(brw_vec1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
549 BRW_REGISTER_TYPE_UD
));
551 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
553 fs_inst
*mov
= emit(MOV(dst
, ts
));
554 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
555 * even if it's not enabled in the dispatch.
557 mov
->force_writemask_all
= true;
558 mov
->force_uncompressed
= true;
560 /* The caller wants the low 32 bits of the timestamp. Since it's running
561 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
562 * which is plenty of time for our purposes. It is identical across the
563 * EUs, but since it's tracking GPU core speed it will increment at a
564 * varying rate as render P-states change.
566 * The caller could also check if render P-states have changed (or anything
567 * else that might disrupt timing) by setting smear to 2 and checking if
568 * that field is != 0.
576 fs_visitor::emit_shader_time_begin()
578 current_annotation
= "shader time start";
579 shader_start_time
= get_timestamp();
583 fs_visitor::emit_shader_time_end()
585 current_annotation
= "shader time end";
587 enum shader_time_shader_type type
, written_type
, reset_type
;
588 if (dispatch_width
== 8) {
590 written_type
= ST_FS8_WRITTEN
;
591 reset_type
= ST_FS8_RESET
;
593 assert(dispatch_width
== 16);
595 written_type
= ST_FS16_WRITTEN
;
596 reset_type
= ST_FS16_RESET
;
599 fs_reg shader_end_time
= get_timestamp();
601 /* Check that there weren't any timestamp reset events (assuming these
602 * were the only two timestamp reads that happened).
604 fs_reg reset
= shader_end_time
;
606 fs_inst
*test
= emit(AND(reg_null_d
, reset
, fs_reg(1u)));
607 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
608 emit(IF(BRW_PREDICATE_NORMAL
));
610 push_force_uncompressed();
611 fs_reg start
= shader_start_time
;
613 fs_reg diff
= fs_reg(this, glsl_type::uint_type
);
614 emit(ADD(diff
, start
, shader_end_time
));
616 /* If there were no instructions between the two timestamp gets, the diff
617 * is 2 cycles. Remove that overhead, so I can forget about that when
618 * trying to determine the time taken for single instructions.
620 emit(ADD(diff
, diff
, fs_reg(-2u)));
622 emit_shader_time_write(type
, diff
);
623 emit_shader_time_write(written_type
, fs_reg(1u));
624 emit(BRW_OPCODE_ELSE
);
625 emit_shader_time_write(reset_type
, fs_reg(1u));
626 emit(BRW_OPCODE_ENDIF
);
628 pop_force_uncompressed();
632 fs_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
635 int shader_time_index
=
636 brw_get_shader_time_index(brw
, shader_prog
, &fp
->Base
, type
);
637 fs_reg offset
= fs_reg(shader_time_index
* SHADER_TIME_STRIDE
);
640 if (dispatch_width
== 8)
641 payload
= fs_reg(this, glsl_type::uvec2_type
);
643 payload
= fs_reg(this, glsl_type::uint_type
);
645 emit(new(mem_ctx
) fs_inst(SHADER_OPCODE_SHADER_TIME_ADD
,
646 fs_reg(), payload
, offset
, value
));
650 fs_visitor::fail(const char *format
, ...)
660 va_start(va
, format
);
661 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
663 msg
= ralloc_asprintf(mem_ctx
, "FS compile failed: %s\n", msg
);
665 this->fail_msg
= msg
;
667 if (INTEL_DEBUG
& DEBUG_WM
) {
668 fprintf(stderr
, "%s", msg
);
673 fs_visitor::emit(enum opcode opcode
)
675 return emit(new(mem_ctx
) fs_inst(opcode
));
679 fs_visitor::emit(enum opcode opcode
, fs_reg dst
)
681 return emit(new(mem_ctx
) fs_inst(opcode
, dst
));
685 fs_visitor::emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
)
687 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
));
691 fs_visitor::emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
693 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
, src1
));
697 fs_visitor::emit(enum opcode opcode
, fs_reg dst
,
698 fs_reg src0
, fs_reg src1
, fs_reg src2
)
700 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
, src1
, src2
));
704 fs_visitor::push_force_uncompressed()
706 force_uncompressed_stack
++;
710 fs_visitor::pop_force_uncompressed()
712 force_uncompressed_stack
--;
713 assert(force_uncompressed_stack
>= 0);
717 * Returns true if the instruction has a flag that means it won't
718 * update an entire destination register.
720 * For example, dead code elimination and live variable analysis want to know
721 * when a write to a variable screens off any preceding values that were in
725 fs_inst::is_partial_write()
727 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
728 this->force_uncompressed
||
729 this->force_sechalf
|| !this->dst
.is_contiguous());
733 fs_inst::regs_read(fs_visitor
*v
, int arg
)
735 if (is_tex() && arg
== 0 && src
[0].file
== GRF
) {
736 if (v
->dispatch_width
== 16)
737 return (mlen
+ 1) / 2;
745 fs_inst::reads_flag()
751 fs_inst::writes_flag()
753 return (conditional_mod
&& opcode
!= BRW_OPCODE_SEL
) ||
754 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
758 * Returns how many MRFs an FS opcode will write over.
760 * Note that this is not the 0 or 1 implied writes in an actual gen
761 * instruction -- the FS opcodes often generate MOVs in addition.
764 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
769 if (inst
->base_mrf
== -1)
772 switch (inst
->opcode
) {
773 case SHADER_OPCODE_RCP
:
774 case SHADER_OPCODE_RSQ
:
775 case SHADER_OPCODE_SQRT
:
776 case SHADER_OPCODE_EXP2
:
777 case SHADER_OPCODE_LOG2
:
778 case SHADER_OPCODE_SIN
:
779 case SHADER_OPCODE_COS
:
780 return 1 * dispatch_width
/ 8;
781 case SHADER_OPCODE_POW
:
782 case SHADER_OPCODE_INT_QUOTIENT
:
783 case SHADER_OPCODE_INT_REMAINDER
:
784 return 2 * dispatch_width
/ 8;
785 case SHADER_OPCODE_TEX
:
787 case SHADER_OPCODE_TXD
:
788 case SHADER_OPCODE_TXF
:
789 case SHADER_OPCODE_TXF_CMS
:
790 case SHADER_OPCODE_TXF_MCS
:
791 case SHADER_OPCODE_TG4
:
792 case SHADER_OPCODE_TG4_OFFSET
:
793 case SHADER_OPCODE_TXL
:
794 case SHADER_OPCODE_TXS
:
795 case SHADER_OPCODE_LOD
:
797 case FS_OPCODE_FB_WRITE
:
799 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
800 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
802 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
804 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
806 case SHADER_OPCODE_UNTYPED_ATOMIC
:
807 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
810 assert(!"not reached");
816 fs_visitor::virtual_grf_alloc(int size
)
818 if (virtual_grf_array_size
<= virtual_grf_count
) {
819 if (virtual_grf_array_size
== 0)
820 virtual_grf_array_size
= 16;
822 virtual_grf_array_size
*= 2;
823 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
824 virtual_grf_array_size
);
826 virtual_grf_sizes
[virtual_grf_count
] = size
;
827 return virtual_grf_count
++;
830 /** Fixed HW reg constructor. */
831 fs_reg::fs_reg(enum register_file file
, int reg
)
836 this->type
= BRW_REGISTER_TYPE_F
;
839 /** Fixed HW reg constructor. */
840 fs_reg::fs_reg(enum register_file file
, int reg
, uint32_t type
)
848 /** Automatic reg constructor. */
849 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
854 this->reg
= v
->virtual_grf_alloc(v
->type_size(type
));
855 this->reg_offset
= 0;
856 this->type
= brw_type_for_base_type(type
);
860 fs_visitor::variable_storage(ir_variable
*var
)
862 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
866 import_uniforms_callback(const void *key
,
870 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
871 const fs_reg
*reg
= (const fs_reg
*)data
;
873 if (reg
->file
!= UNIFORM
)
876 hash_table_insert(dst_ht
, data
, key
);
879 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
880 * This brings in those uniform definitions
883 fs_visitor::import_uniforms(fs_visitor
*v
)
885 hash_table_call_foreach(v
->variable_ht
,
886 import_uniforms_callback
,
888 this->params_remap
= v
->params_remap
;
889 this->nr_params_remap
= v
->nr_params_remap
;
892 /* Our support for uniforms is piggy-backed on the struct
893 * gl_fragment_program, because that's where the values actually
894 * get stored, rather than in some global gl_shader_program uniform
898 fs_visitor::setup_uniform_values(ir_variable
*ir
)
900 int namelen
= strlen(ir
->name
);
902 /* The data for our (non-builtin) uniforms is stored in a series of
903 * gl_uniform_driver_storage structs for each subcomponent that
904 * glGetUniformLocation() could name. We know it's been set up in the same
905 * order we'd walk the type, so walk the list of storage and find anything
906 * with our name, or the prefix of a component that starts with our name.
908 unsigned params_before
= uniforms
;
909 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
910 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
912 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
913 (storage
->name
[namelen
] != 0 &&
914 storage
->name
[namelen
] != '.' &&
915 storage
->name
[namelen
] != '[')) {
919 unsigned slots
= storage
->type
->component_slots();
920 if (storage
->array_elements
)
921 slots
*= storage
->array_elements
;
923 for (unsigned i
= 0; i
< slots
; i
++) {
924 stage_prog_data
->param
[uniforms
++] = &storage
->storage
[i
].f
;
928 /* Make sure we actually initialized the right amount of stuff here. */
929 assert(params_before
+ ir
->type
->component_slots() == uniforms
);
934 /* Our support for builtin uniforms is even scarier than non-builtin.
935 * It sits on top of the PROG_STATE_VAR parameters that are
936 * automatically updated from GL context state.
939 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
941 const ir_state_slot
*const slots
= ir
->state_slots
;
942 assert(ir
->state_slots
!= NULL
);
944 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
945 /* This state reference has already been setup by ir_to_mesa, but we'll
946 * get the same index back here.
948 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
949 (gl_state_index
*)slots
[i
].tokens
);
951 /* Add each of the unique swizzles of the element as a parameter.
952 * This'll end up matching the expected layout of the
953 * array/matrix/structure we're trying to fill in.
956 for (unsigned int j
= 0; j
< 4; j
++) {
957 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
958 if (swiz
== last_swiz
)
962 stage_prog_data
->param
[uniforms
++] =
963 &fp
->Base
.Parameters
->ParameterValues
[index
][swiz
].f
;
969 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
971 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
973 bool flip
= !ir
->data
.origin_upper_left
^ c
->key
.render_to_fbo
;
976 if (ir
->data
.pixel_center_integer
) {
977 emit(MOV(wpos
, this->pixel_x
));
979 emit(ADD(wpos
, this->pixel_x
, fs_reg(0.5f
)));
984 if (!flip
&& ir
->data
.pixel_center_integer
) {
985 emit(MOV(wpos
, this->pixel_y
));
987 fs_reg pixel_y
= this->pixel_y
;
988 float offset
= (ir
->data
.pixel_center_integer
? 0.0 : 0.5);
991 pixel_y
.negate
= true;
992 offset
+= c
->key
.drawable_height
- 1.0;
995 emit(ADD(wpos
, pixel_y
, fs_reg(offset
)));
1000 if (brw
->gen
>= 6) {
1001 emit(MOV(wpos
, fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
1003 emit(FS_OPCODE_LINTERP
, wpos
,
1004 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1005 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1006 interp_reg(VARYING_SLOT_POS
, 2));
1010 /* gl_FragCoord.w: Already set up in emit_interpolation */
1011 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
1017 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1018 glsl_interp_qualifier interpolation_mode
,
1019 bool is_centroid
, bool is_sample
)
1021 brw_wm_barycentric_interp_mode barycoord_mode
;
1022 if (brw
->gen
>= 6) {
1024 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1025 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1027 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1028 } else if (is_sample
) {
1029 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1030 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1032 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1034 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1035 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1037 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1040 /* On Ironlake and below, there is only one interpolation mode.
1041 * Centroid interpolation doesn't mean anything on this hardware --
1042 * there is no multisampling.
1044 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1046 return emit(FS_OPCODE_LINTERP
, attr
,
1047 this->delta_x
[barycoord_mode
],
1048 this->delta_y
[barycoord_mode
], interp
);
1052 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
1054 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1055 reg
->type
= brw_type_for_base_type(ir
->type
->get_scalar_type());
1058 unsigned int array_elements
;
1059 const glsl_type
*type
;
1061 if (ir
->type
->is_array()) {
1062 array_elements
= ir
->type
->length
;
1063 if (array_elements
== 0) {
1064 fail("dereferenced array '%s' has length 0\n", ir
->name
);
1066 type
= ir
->type
->fields
.array
;
1072 glsl_interp_qualifier interpolation_mode
=
1073 ir
->determine_interpolation_mode(c
->key
.flat_shade
);
1075 int location
= ir
->data
.location
;
1076 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1077 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1078 if (c
->prog_data
.urb_setup
[location
] == -1) {
1079 /* If there's no incoming setup data for this slot, don't
1080 * emit interpolation for it.
1082 attr
.reg_offset
+= type
->vector_elements
;
1087 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1088 /* Constant interpolation (flat shading) case. The SF has
1089 * handed us defined values in only the constant offset
1090 * field of the setup reg.
1092 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1093 struct brw_reg interp
= interp_reg(location
, k
);
1094 interp
= suboffset(interp
, 3);
1095 interp
.type
= reg
->type
;
1096 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1100 /* Smooth/noperspective interpolation case. */
1101 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1102 struct brw_reg interp
= interp_reg(location
, k
);
1103 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1104 ir
->data
.centroid
&& !c
->key
.persample_shading
,
1105 ir
->data
.sample
|| c
->key
.persample_shading
);
1106 if (brw
->needs_unlit_centroid_workaround
&& ir
->data
.centroid
) {
1107 /* Get the pixel/sample mask into f0 so that we know
1108 * which pixels are lit. Then, for each channel that is
1109 * unlit, replace the centroid data with non-centroid
1112 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1113 fs_inst
*inst
= emit_linterp(attr
, fs_reg(interp
),
1116 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1117 inst
->predicate_inverse
= true;
1119 if (brw
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1120 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
1134 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
1136 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1138 /* The frontfacing comes in as a bit in the thread payload. */
1139 if (brw
->gen
>= 6) {
1140 emit(BRW_OPCODE_ASR
, *reg
,
1141 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1143 emit(BRW_OPCODE_NOT
, *reg
, *reg
);
1144 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1));
1146 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
1147 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
1150 emit(CMP(*reg
, fs_reg(r1_6ud
), fs_reg(1u << 31), BRW_CONDITIONAL_L
));
1151 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u));
1158 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1160 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1162 if (c
->key
.compute_pos_offset
) {
1163 /* Convert int_sample_pos to floating point */
1164 emit(MOV(dst
, int_sample_pos
));
1165 /* Scale to the range [0, 1] */
1166 emit(MUL(dst
, dst
, fs_reg(1 / 16.0f
)));
1169 /* From ARB_sample_shading specification:
1170 * "When rendering to a non-multisample buffer, or if multisample
1171 * rasterization is disabled, gl_SamplePosition will always be
1174 emit(MOV(dst
, fs_reg(0.5f
)));
1179 fs_visitor::emit_samplepos_setup(ir_variable
*ir
)
1181 assert(brw
->gen
>= 6);
1182 assert(ir
->type
== glsl_type::vec2_type
);
1184 this->current_annotation
= "compute sample position";
1185 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1187 fs_reg int_sample_x
= fs_reg(this, glsl_type::int_type
);
1188 fs_reg int_sample_y
= fs_reg(this, glsl_type::int_type
);
1190 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1191 * mode will be enabled.
1193 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1194 * R31.1:0 Position Offset X/Y for Slot[3:0]
1195 * R31.3:2 Position Offset X/Y for Slot[7:4]
1198 * The X, Y sample positions come in as bytes in thread payload. So, read
1199 * the positions using vstride=16, width=8, hstride=2.
1201 struct brw_reg sample_pos_reg
=
1202 stride(retype(brw_vec1_grf(c
->sample_pos_reg
, 0),
1203 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1205 emit(MOV(int_sample_x
, fs_reg(sample_pos_reg
)));
1206 if (dispatch_width
== 16) {
1207 fs_inst
*inst
= emit(MOV(half(int_sample_x
, 1),
1208 fs_reg(suboffset(sample_pos_reg
, 16))));
1209 inst
->force_sechalf
= true;
1211 /* Compute gl_SamplePosition.x */
1212 compute_sample_position(pos
, int_sample_x
);
1214 emit(MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1))));
1215 if (dispatch_width
== 16) {
1216 fs_inst
*inst
= emit(MOV(half(int_sample_y
, 1),
1217 fs_reg(suboffset(sample_pos_reg
, 17))));
1218 inst
->force_sechalf
= true;
1220 /* Compute gl_SamplePosition.y */
1221 compute_sample_position(pos
, int_sample_y
);
1226 fs_visitor::emit_sampleid_setup(ir_variable
*ir
)
1228 assert(brw
->gen
>= 6);
1230 this->current_annotation
= "compute sample id";
1231 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1233 if (c
->key
.compute_sample_id
) {
1234 fs_reg t1
= fs_reg(this, glsl_type::int_type
);
1235 fs_reg t2
= fs_reg(this, glsl_type::int_type
);
1236 t2
.type
= BRW_REGISTER_TYPE_UW
;
1238 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1239 * 8x multisampling, subspan 0 will represent sample N (where N
1240 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1241 * 7. We can find the value of N by looking at R0.0 bits 7:6
1242 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1243 * (since samples are always delivered in pairs). That is, we
1244 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1245 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1246 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1247 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1248 * populating a temporary variable with the sequence (0, 1, 2, 3),
1249 * and then reading from it using vstride=1, width=4, hstride=0.
1250 * These computations hold good for 4x multisampling as well.
1252 emit(BRW_OPCODE_AND
, t1
,
1253 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1254 fs_reg(brw_imm_d(0xc0)));
1255 emit(BRW_OPCODE_SHR
, t1
, t1
, fs_reg(5));
1256 /* This works for both SIMD8 and SIMD16 */
1257 emit(MOV(t2
, brw_imm_v(0x3210)));
1258 /* This special instruction takes care of setting vstride=1,
1259 * width=4, hstride=0 of t2 during an ADD instruction.
1261 emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1263 /* As per GL_ARB_sample_shading specification:
1264 * "When rendering to a non-multisample buffer, or if multisample
1265 * rasterization is disabled, gl_SampleID will always be zero."
1267 emit(BRW_OPCODE_MOV
, *reg
, fs_reg(0));
1274 fs_visitor::emit_samplemaskin_setup(ir_variable
*ir
)
1276 assert(brw
->gen
>= 7);
1277 this->current_annotation
= "compute gl_SampleMaskIn";
1278 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
1279 emit(MOV(*reg
, fs_reg(retype(brw_vec8_grf(c
->sample_mask_reg
, 0), BRW_REGISTER_TYPE_D
))));
1284 fs_visitor::fix_math_operand(fs_reg src
)
1286 /* Can't do hstride == 0 args on gen6 math, so expand it out. We
1287 * might be able to do better by doing execsize = 1 math and then
1288 * expanding that result out, but we would need to be careful with
1291 * The hardware ignores source modifiers (negate and abs) on math
1292 * instructions, so we also move to a temp to set those up.
1294 if (brw
->gen
== 6 && src
.file
!= UNIFORM
&& src
.file
!= IMM
&&
1295 !src
.abs
&& !src
.negate
)
1298 /* Gen7 relaxes most of the above restrictions, but still can't use IMM
1301 if (brw
->gen
>= 7 && src
.file
!= IMM
)
1304 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
1305 expanded
.type
= src
.type
;
1306 emit(BRW_OPCODE_MOV
, expanded
, src
);
1311 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src
)
1314 case SHADER_OPCODE_RCP
:
1315 case SHADER_OPCODE_RSQ
:
1316 case SHADER_OPCODE_SQRT
:
1317 case SHADER_OPCODE_EXP2
:
1318 case SHADER_OPCODE_LOG2
:
1319 case SHADER_OPCODE_SIN
:
1320 case SHADER_OPCODE_COS
:
1323 assert(!"not reached: bad math opcode");
1327 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
1328 * might be able to do better by doing execsize = 1 math and then
1329 * expanding that result out, but we would need to be careful with
1332 * Gen 6 hardware ignores source modifiers (negate and abs) on math
1333 * instructions, so we also move to a temp to set those up.
1336 src
= fix_math_operand(src
);
1338 fs_inst
*inst
= emit(opcode
, dst
, src
);
1342 inst
->mlen
= dispatch_width
/ 8;
1349 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
1355 case SHADER_OPCODE_INT_QUOTIENT
:
1356 case SHADER_OPCODE_INT_REMAINDER
:
1357 if (brw
->gen
>= 7 && dispatch_width
== 16)
1358 fail("SIMD16 INTDIV unsupported\n");
1360 case SHADER_OPCODE_POW
:
1363 assert(!"not reached: unsupported binary math opcode.");
1367 if (brw
->gen
>= 6) {
1368 src0
= fix_math_operand(src0
);
1369 src1
= fix_math_operand(src1
);
1371 inst
= emit(opcode
, dst
, src0
, src1
);
1373 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
1374 * "Message Payload":
1376 * "Operand0[7]. For the INT DIV functions, this operand is the
1379 * "Operand1[7]. For the INT DIV functions, this operand is the
1382 bool is_int_div
= opcode
!= SHADER_OPCODE_POW
;
1383 fs_reg
&op0
= is_int_div
? src1
: src0
;
1384 fs_reg
&op1
= is_int_div
? src0
: src1
;
1386 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1, op1
.type
), op1
);
1387 inst
= emit(opcode
, dst
, op0
, reg_null_f
);
1389 inst
->base_mrf
= base_mrf
;
1390 inst
->mlen
= 2 * dispatch_width
/ 8;
1396 fs_visitor::assign_curb_setup()
1398 if (dispatch_width
== 8) {
1399 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
1400 stage_prog_data
->nr_params
= uniforms
;
1402 c
->prog_data
.first_curbe_grf_16
= c
->nr_payload_regs
;
1403 /* Make sure we didn't try to sneak in an extra uniform */
1404 assert(uniforms
== 0);
1407 c
->prog_data
.curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1409 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1410 foreach_list(node
, &this->instructions
) {
1411 fs_inst
*inst
= (fs_inst
*)node
;
1413 for (unsigned int i
= 0; i
< 3; i
++) {
1414 if (inst
->src
[i
].file
== UNIFORM
) {
1415 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1416 struct brw_reg brw_reg
= brw_vec1_grf(c
->nr_payload_regs
+
1420 inst
->src
[i
].file
= HW_REG
;
1421 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1422 retype(brw_reg
, inst
->src
[i
].type
),
1423 inst
->src
[i
].subreg_offset
);
1430 fs_visitor::calculate_urb_setup()
1432 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1433 c
->prog_data
.urb_setup
[i
] = -1;
1437 /* Figure out where each of the incoming setup attributes lands. */
1438 if (brw
->gen
>= 6) {
1439 if (_mesa_bitcount_64(fp
->Base
.InputsRead
&
1440 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1441 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1442 * first 16 varying inputs, so we can put them wherever we want.
1443 * Just put them in order.
1445 * This is useful because it means that (a) inputs not used by the
1446 * fragment shader won't take up valuable register space, and (b) we
1447 * won't have to recompile the fragment shader if it gets paired with
1448 * a different vertex (or geometry) shader.
1450 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1451 if (fp
->Base
.InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1452 BITFIELD64_BIT(i
)) {
1453 c
->prog_data
.urb_setup
[i
] = urb_next
++;
1457 /* We have enough input varyings that the SF/SBE pipeline stage can't
1458 * arbitrarily rearrange them to suit our whim; we have to put them
1459 * in an order that matches the output of the previous pipeline stage
1460 * (geometry or vertex shader).
1462 struct brw_vue_map prev_stage_vue_map
;
1463 brw_compute_vue_map(brw
, &prev_stage_vue_map
,
1464 c
->key
.input_slots_valid
);
1465 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1466 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1467 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1469 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1470 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1473 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1474 (fp
->Base
.InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1475 BITFIELD64_BIT(varying
))) {
1476 c
->prog_data
.urb_setup
[varying
] = slot
- first_slot
;
1479 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1482 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1483 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1484 /* Point size is packed into the header, not as a general attribute */
1485 if (i
== VARYING_SLOT_PSIZ
)
1488 if (c
->key
.input_slots_valid
& BITFIELD64_BIT(i
)) {
1489 /* The back color slot is skipped when the front color is
1490 * also written to. In addition, some slots can be
1491 * written in the vertex shader and not read in the
1492 * fragment shader. So the register number must always be
1493 * incremented, mapped or not.
1495 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1496 c
->prog_data
.urb_setup
[i
] = urb_next
;
1502 * It's a FS only attribute, and we did interpolation for this attribute
1503 * in SF thread. So, count it here, too.
1505 * See compile_sf_prog() for more info.
1507 if (fp
->Base
.InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1508 c
->prog_data
.urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1511 c
->prog_data
.num_varying_inputs
= urb_next
;
1515 fs_visitor::assign_urb_setup()
1517 int urb_start
= c
->nr_payload_regs
+ c
->prog_data
.curb_read_length
;
1519 /* Offset all the urb_setup[] index by the actual position of the
1520 * setup regs, now that the location of the constants has been chosen.
1522 foreach_list(node
, &this->instructions
) {
1523 fs_inst
*inst
= (fs_inst
*)node
;
1525 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1526 assert(inst
->src
[2].file
== HW_REG
);
1527 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
1530 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1531 assert(inst
->src
[0].file
== HW_REG
);
1532 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1536 /* Each attribute is 4 setup channels, each of which is half a reg. */
1537 this->first_non_payload_grf
=
1538 urb_start
+ c
->prog_data
.num_varying_inputs
* 2;
1542 * Split large virtual GRFs into separate components if we can.
1544 * This is mostly duplicated with what brw_fs_vector_splitting does,
1545 * but that's really conservative because it's afraid of doing
1546 * splitting that doesn't result in real progress after the rest of
1547 * the optimization phases, which would cause infinite looping in
1548 * optimization. We can do it once here, safely. This also has the
1549 * opportunity to split interpolated values, or maybe even uniforms,
1550 * which we don't have at the IR level.
1552 * We want to split, because virtual GRFs are what we register
1553 * allocate and spill (due to contiguousness requirements for some
1554 * instructions), and they're what we naturally generate in the
1555 * codegen process, but most virtual GRFs don't actually need to be
1556 * contiguous sets of GRFs. If we split, we'll end up with reduced
1557 * live intervals and better dead code elimination and coalescing.
1560 fs_visitor::split_virtual_grfs()
1562 int num_vars
= this->virtual_grf_count
;
1563 bool split_grf
[num_vars
];
1564 int new_virtual_grf
[num_vars
];
1566 /* Try to split anything > 0 sized. */
1567 for (int i
= 0; i
< num_vars
; i
++) {
1568 if (this->virtual_grf_sizes
[i
] != 1)
1569 split_grf
[i
] = true;
1571 split_grf
[i
] = false;
1575 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
) {
1576 /* PLN opcodes rely on the delta_xy being contiguous. We only have to
1577 * check this for BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because prior to
1578 * Gen6, that was the only supported interpolation mode, and since Gen6,
1579 * delta_x and delta_y are in fixed hardware registers.
1581 split_grf
[this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
] =
1585 foreach_list(node
, &this->instructions
) {
1586 fs_inst
*inst
= (fs_inst
*)node
;
1588 /* If there's a SEND message that requires contiguous destination
1589 * registers, no splitting is allowed.
1591 if (inst
->regs_written
> 1) {
1592 split_grf
[inst
->dst
.reg
] = false;
1595 /* If we're sending from a GRF, don't split it, on the assumption that
1596 * the send is reading the whole thing.
1598 if (inst
->is_send_from_grf()) {
1599 for (int i
= 0; i
< 3; i
++) {
1600 if (inst
->src
[i
].file
== GRF
) {
1601 split_grf
[inst
->src
[i
].reg
] = false;
1607 /* Allocate new space for split regs. Note that the virtual
1608 * numbers will be contiguous.
1610 for (int i
= 0; i
< num_vars
; i
++) {
1612 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1613 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1614 int reg
= virtual_grf_alloc(1);
1615 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1618 this->virtual_grf_sizes
[i
] = 1;
1622 foreach_list(node
, &this->instructions
) {
1623 fs_inst
*inst
= (fs_inst
*)node
;
1625 if (inst
->dst
.file
== GRF
&&
1626 split_grf
[inst
->dst
.reg
] &&
1627 inst
->dst
.reg_offset
!= 0) {
1628 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1629 inst
->dst
.reg_offset
- 1);
1630 inst
->dst
.reg_offset
= 0;
1632 for (int i
= 0; i
< 3; i
++) {
1633 if (inst
->src
[i
].file
== GRF
&&
1634 split_grf
[inst
->src
[i
].reg
] &&
1635 inst
->src
[i
].reg_offset
!= 0) {
1636 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1637 inst
->src
[i
].reg_offset
- 1);
1638 inst
->src
[i
].reg_offset
= 0;
1642 invalidate_live_intervals();
1646 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1648 * During code generation, we create tons of temporary variables, many of
1649 * which get immediately killed and are never used again. Yet, in later
1650 * optimization and analysis passes, such as compute_live_intervals, we need
1651 * to loop over all the virtual GRFs. Compacting them can save a lot of
1655 fs_visitor::compact_virtual_grfs()
1657 /* Mark which virtual GRFs are used, and count how many. */
1658 int remap_table
[this->virtual_grf_count
];
1659 memset(remap_table
, -1, sizeof(remap_table
));
1661 foreach_list(node
, &this->instructions
) {
1662 const fs_inst
*inst
= (const fs_inst
*) node
;
1664 if (inst
->dst
.file
== GRF
)
1665 remap_table
[inst
->dst
.reg
] = 0;
1667 for (int i
= 0; i
< 3; i
++) {
1668 if (inst
->src
[i
].file
== GRF
)
1669 remap_table
[inst
->src
[i
].reg
] = 0;
1673 /* In addition to registers used in instructions, fs_visitor keeps
1674 * direct references to certain special values which must be patched:
1676 fs_reg
*special
[] = {
1677 &frag_depth
, &pixel_x
, &pixel_y
, &pixel_w
, &wpos_w
, &dual_src_output
,
1678 &outputs
[0], &outputs
[1], &outputs
[2], &outputs
[3],
1679 &outputs
[4], &outputs
[5], &outputs
[6], &outputs
[7],
1680 &delta_x
[0], &delta_x
[1], &delta_x
[2],
1681 &delta_x
[3], &delta_x
[4], &delta_x
[5],
1682 &delta_y
[0], &delta_y
[1], &delta_y
[2],
1683 &delta_y
[3], &delta_y
[4], &delta_y
[5],
1685 STATIC_ASSERT(BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
== 6);
1686 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
== 8);
1688 /* Treat all special values as used, to be conservative */
1689 for (unsigned i
= 0; i
< ARRAY_SIZE(special
); i
++) {
1690 if (special
[i
]->file
== GRF
)
1691 remap_table
[special
[i
]->reg
] = 0;
1694 /* Compact the GRF arrays. */
1696 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
1697 if (remap_table
[i
] != -1) {
1698 remap_table
[i
] = new_index
;
1699 virtual_grf_sizes
[new_index
] = virtual_grf_sizes
[i
];
1700 invalidate_live_intervals();
1705 this->virtual_grf_count
= new_index
;
1707 /* Patch all the instructions to use the newly renumbered registers */
1708 foreach_list(node
, &this->instructions
) {
1709 fs_inst
*inst
= (fs_inst
*) node
;
1711 if (inst
->dst
.file
== GRF
)
1712 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1714 for (int i
= 0; i
< 3; i
++) {
1715 if (inst
->src
[i
].file
== GRF
)
1716 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1720 /* Patch all the references to special values */
1721 for (unsigned i
= 0; i
< ARRAY_SIZE(special
); i
++) {
1722 if (special
[i
]->file
== GRF
&& remap_table
[special
[i
]->reg
] != -1)
1723 special
[i
]->reg
= remap_table
[special
[i
]->reg
];
1728 fs_visitor::remove_dead_constants()
1730 if (dispatch_width
== 8) {
1731 this->params_remap
= ralloc_array(mem_ctx
, int, uniforms
);
1732 this->nr_params_remap
= uniforms
;
1734 for (unsigned int i
= 0; i
< uniforms
; i
++)
1735 this->params_remap
[i
] = -1;
1737 /* Find which params are still in use. */
1738 foreach_list(node
, &this->instructions
) {
1739 fs_inst
*inst
= (fs_inst
*)node
;
1741 for (int i
= 0; i
< 3; i
++) {
1742 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1744 if (inst
->src
[i
].file
!= UNIFORM
)
1747 /* Section 5.11 of the OpenGL 4.3 spec says:
1749 * "Out-of-bounds reads return undefined values, which include
1750 * values from other variables of the active program or zero."
1752 if (constant_nr
< 0 || constant_nr
>= (int)uniforms
) {
1756 /* For now, set this to non-negative. We'll give it the
1757 * actual new number in a moment, in order to keep the
1758 * register numbers nicely ordered.
1760 this->params_remap
[constant_nr
] = 0;
1764 /* Figure out what the new numbers for the params will be. At some
1765 * point when we're doing uniform array access, we're going to want
1766 * to keep the distinction between .reg and .reg_offset, but for
1767 * now we don't care.
1769 unsigned int new_nr_params
= 0;
1770 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1771 if (this->params_remap
[i
] != -1) {
1772 this->params_remap
[i
] = new_nr_params
++;
1776 /* Update the list of params to be uploaded to match our new numbering. */
1777 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1778 int remapped
= this->params_remap
[i
];
1783 stage_prog_data
->param
[remapped
] = stage_prog_data
->param
[i
];
1786 uniforms
= new_nr_params
;
1788 /* This should have been generated in the SIMD8 pass already. */
1789 assert(this->params_remap
);
1792 /* Now do the renumbering of the shader to remove unused params. */
1793 foreach_list(node
, &this->instructions
) {
1794 fs_inst
*inst
= (fs_inst
*)node
;
1796 for (int i
= 0; i
< 3; i
++) {
1797 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1799 if (inst
->src
[i
].file
!= UNIFORM
)
1802 /* as above alias to 0 */
1803 if (constant_nr
< 0 || constant_nr
>= (int)this->nr_params_remap
) {
1806 assert(this->params_remap
[constant_nr
] != -1);
1807 inst
->src
[i
].reg
= this->params_remap
[constant_nr
];
1808 inst
->src
[i
].reg_offset
= 0;
1816 * Implements array access of uniforms by inserting a
1817 * PULL_CONSTANT_LOAD instruction.
1819 * Unlike temporary GRF array access (where we don't support it due to
1820 * the difficulty of doing relative addressing on instruction
1821 * destinations), we could potentially do array access of uniforms
1822 * that were loaded in GRF space as push constants. In real-world
1823 * usage we've seen, though, the arrays being used are always larger
1824 * than we could load as push constants, so just always move all
1825 * uniform array access out to a pull constant buffer.
1828 fs_visitor::move_uniform_array_access_to_pull_constants()
1830 int pull_constant_loc
[uniforms
];
1832 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1833 pull_constant_loc
[i
] = -1;
1836 /* Walk through and find array access of uniforms. Put a copy of that
1837 * uniform in the pull constant buffer.
1839 * Note that we don't move constant-indexed accesses to arrays. No
1840 * testing has been done of the performance impact of this choice.
1842 foreach_list_safe(node
, &this->instructions
) {
1843 fs_inst
*inst
= (fs_inst
*)node
;
1845 for (int i
= 0 ; i
< 3; i
++) {
1846 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
1849 int uniform
= inst
->src
[i
].reg
;
1851 /* If this array isn't already present in the pull constant buffer,
1854 if (pull_constant_loc
[uniform
] == -1) {
1855 const float **values
= &stage_prog_data
->param
[uniform
];
1857 pull_constant_loc
[uniform
] = stage_prog_data
->nr_pull_params
;
1859 assert(param_size
[uniform
]);
1861 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
1862 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
1867 /* Set up the annotation tracking for new generated instructions. */
1869 current_annotation
= inst
->annotation
;
1871 fs_reg
surf_index(stage_prog_data
->binding_table
.pull_constants_start
);
1872 fs_reg temp
= fs_reg(this, glsl_type::float_type
);
1873 exec_list list
= VARYING_PULL_CONSTANT_LOAD(temp
,
1875 *inst
->src
[i
].reladdr
,
1876 pull_constant_loc
[uniform
] +
1877 inst
->src
[i
].reg_offset
);
1878 inst
->insert_before(&list
);
1880 inst
->src
[i
].file
= temp
.file
;
1881 inst
->src
[i
].reg
= temp
.reg
;
1882 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
1883 inst
->src
[i
].reladdr
= NULL
;
1889 * Choose accesses from the UNIFORM file to demote to using the pull
1892 * We allow a fragment shader to have more than the specified minimum
1893 * maximum number of fragment shader uniform components (64). If
1894 * there are too many of these, they'd fill up all of register space.
1895 * So, this will push some of them out to the pull constant buffer and
1896 * update the program to load them.
1899 fs_visitor::setup_pull_constants()
1901 /* Only allow 16 registers (128 uniform components) as push constants. */
1902 unsigned int max_uniform_components
= 16 * 8;
1903 if (uniforms
<= max_uniform_components
)
1906 if (dispatch_width
== 16) {
1907 fail("Pull constants not supported in SIMD16\n");
1911 /* Just demote the end of the list. We could probably do better
1912 * here, demoting things that are rarely used in the program first.
1914 unsigned int pull_uniform_base
= max_uniform_components
;
1916 int pull_constant_loc
[uniforms
];
1917 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1918 if (i
< pull_uniform_base
) {
1919 pull_constant_loc
[i
] = -1;
1921 pull_constant_loc
[i
] = -1;
1922 /* If our constant is already being uploaded for reladdr purposes,
1925 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
++) {
1926 if (stage_prog_data
->pull_param
[j
] == stage_prog_data
->param
[i
]) {
1927 pull_constant_loc
[i
] = j
;
1931 if (pull_constant_loc
[i
] == -1) {
1932 int pull_index
= stage_prog_data
->nr_pull_params
++;
1933 stage_prog_data
->pull_param
[pull_index
] = stage_prog_data
->param
[i
];
1934 pull_constant_loc
[i
] = pull_index
;
1938 uniforms
= pull_uniform_base
;
1940 foreach_list(node
, &this->instructions
) {
1941 fs_inst
*inst
= (fs_inst
*)node
;
1943 for (int i
= 0; i
< 3; i
++) {
1944 if (inst
->src
[i
].file
!= UNIFORM
)
1947 int pull_index
= pull_constant_loc
[inst
->src
[i
].reg
+
1948 inst
->src
[i
].reg_offset
];
1949 if (pull_index
== -1)
1952 assert(!inst
->src
[i
].reladdr
);
1954 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
1955 fs_reg
index(stage_prog_data
->binding_table
.pull_constants_start
);
1956 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
1958 new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
1959 dst
, index
, offset
);
1960 pull
->ir
= inst
->ir
;
1961 pull
->annotation
= inst
->annotation
;
1963 inst
->insert_before(pull
);
1965 inst
->src
[i
].file
= GRF
;
1966 inst
->src
[i
].reg
= dst
.reg
;
1967 inst
->src
[i
].reg_offset
= 0;
1968 inst
->src
[i
].set_smear(pull_index
& 3);
1974 fs_visitor::opt_algebraic()
1976 bool progress
= false;
1978 foreach_list(node
, &this->instructions
) {
1979 fs_inst
*inst
= (fs_inst
*)node
;
1981 switch (inst
->opcode
) {
1982 case BRW_OPCODE_MUL
:
1983 if (inst
->src
[1].file
!= IMM
)
1987 if (inst
->src
[1].is_one()) {
1988 inst
->opcode
= BRW_OPCODE_MOV
;
1989 inst
->src
[1] = reg_undef
;
1995 if (inst
->src
[1].is_zero()) {
1996 inst
->opcode
= BRW_OPCODE_MOV
;
1997 inst
->src
[0] = inst
->src
[1];
1998 inst
->src
[1] = reg_undef
;
2004 case BRW_OPCODE_ADD
:
2005 if (inst
->src
[1].file
!= IMM
)
2009 if (inst
->src
[1].is_zero()) {
2010 inst
->opcode
= BRW_OPCODE_MOV
;
2011 inst
->src
[1] = reg_undef
;
2017 if (inst
->src
[0].equals(inst
->src
[1])) {
2018 inst
->opcode
= BRW_OPCODE_MOV
;
2019 inst
->src
[1] = reg_undef
;
2024 case BRW_OPCODE_LRP
:
2025 if (inst
->src
[1].equals(inst
->src
[2])) {
2026 inst
->opcode
= BRW_OPCODE_MOV
;
2027 inst
->src
[0] = inst
->src
[1];
2028 inst
->src
[1] = reg_undef
;
2029 inst
->src
[2] = reg_undef
;
2034 case BRW_OPCODE_SEL
:
2035 if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2036 switch (inst
->conditional_mod
) {
2037 case BRW_CONDITIONAL_LE
:
2038 case BRW_CONDITIONAL_L
:
2039 switch (inst
->src
[1].type
) {
2040 case BRW_REGISTER_TYPE_F
:
2041 if (inst
->src
[1].imm
.f
>= 1.0f
) {
2042 inst
->opcode
= BRW_OPCODE_MOV
;
2043 inst
->src
[1] = reg_undef
;
2051 case BRW_CONDITIONAL_GE
:
2052 case BRW_CONDITIONAL_G
:
2053 switch (inst
->src
[1].type
) {
2054 case BRW_REGISTER_TYPE_F
:
2055 if (inst
->src
[1].imm
.f
<= 0.0f
) {
2056 inst
->opcode
= BRW_OPCODE_MOV
;
2057 inst
->src
[1] = reg_undef
;
2058 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2079 * Removes any instructions writing a VGRF where that VGRF is not used by any
2080 * later instruction.
2083 fs_visitor::dead_code_eliminate()
2085 bool progress
= false;
2088 calculate_live_intervals();
2090 foreach_list_safe(node
, &this->instructions
) {
2091 fs_inst
*inst
= (fs_inst
*)node
;
2093 if (inst
->dst
.file
== GRF
&& !inst
->has_side_effects()) {
2096 for (int i
= 0; i
< inst
->regs_written
; i
++) {
2097 int var
= live_intervals
->var_from_vgrf
[inst
->dst
.reg
];
2098 assert(live_intervals
->end
[var
+ inst
->dst
.reg_offset
+ i
] >= pc
);
2099 if (live_intervals
->end
[var
+ inst
->dst
.reg_offset
+ i
] != pc
) {
2106 /* Don't dead code eliminate instructions that write to the
2107 * accumulator as a side-effect. Instead just set the destination
2108 * to the null register to free it.
2110 switch (inst
->opcode
) {
2111 case BRW_OPCODE_ADDC
:
2112 case BRW_OPCODE_SUBB
:
2113 case BRW_OPCODE_MACH
:
2114 inst
->dst
= fs_reg(retype(brw_null_reg(), inst
->dst
.type
));
2128 invalidate_live_intervals();
2133 struct dead_code_hash_key
2140 dead_code_hash_compare(const void *a
, const void *b
)
2142 return memcmp(a
, b
, sizeof(struct dead_code_hash_key
)) == 0;
2146 clear_dead_code_hash(struct hash_table
*ht
)
2148 struct hash_entry
*entry
;
2150 hash_table_foreach(ht
, entry
) {
2151 _mesa_hash_table_remove(ht
, entry
);
2156 insert_dead_code_hash(struct hash_table
*ht
,
2157 int vgrf
, int reg_offset
, fs_inst
*inst
)
2159 /* We don't bother freeing keys, because they'll be GCed with the ht. */
2160 struct dead_code_hash_key
*key
= ralloc(ht
, struct dead_code_hash_key
);
2163 key
->reg_offset
= reg_offset
;
2165 _mesa_hash_table_insert(ht
, _mesa_hash_data(key
, sizeof(*key
)), key
, inst
);
2168 static struct hash_entry
*
2169 get_dead_code_hash_entry(struct hash_table
*ht
, int vgrf
, int reg_offset
)
2171 struct dead_code_hash_key key
;
2174 key
.reg_offset
= reg_offset
;
2176 return _mesa_hash_table_search(ht
, _mesa_hash_data(&key
, sizeof(key
)), &key
);
2180 remove_dead_code_hash(struct hash_table
*ht
,
2181 int vgrf
, int reg_offset
)
2183 struct hash_entry
*entry
= get_dead_code_hash_entry(ht
, vgrf
, reg_offset
);
2187 _mesa_hash_table_remove(ht
, entry
);
2191 * Walks basic blocks, removing any regs that are written but not read before
2194 * The dead_code_eliminate() function implements a global dead code
2195 * elimination, but it only handles the removing the last write to a register
2196 * if it's never read. This one can handle intermediate writes, but only
2197 * within a basic block.
2200 fs_visitor::dead_code_eliminate_local()
2202 struct hash_table
*ht
;
2203 bool progress
= false;
2205 ht
= _mesa_hash_table_create(mem_ctx
, dead_code_hash_compare
);
2211 foreach_list_safe(node
, &this->instructions
) {
2212 fs_inst
*inst
= (fs_inst
*)node
;
2214 /* At a basic block, empty the HT since we don't understand dataflow
2217 if (inst
->is_control_flow()) {
2218 clear_dead_code_hash(ht
);
2222 /* Clear the HT of any instructions that got read. */
2223 for (int i
= 0; i
< 3; i
++) {
2224 fs_reg src
= inst
->src
[i
];
2225 if (src
.file
!= GRF
)
2229 if (inst
->is_send_from_grf())
2230 read
= virtual_grf_sizes
[src
.reg
] - src
.reg_offset
;
2232 for (int reg_offset
= src
.reg_offset
;
2233 reg_offset
< src
.reg_offset
+ read
;
2235 remove_dead_code_hash(ht
, src
.reg
, reg_offset
);
2239 /* Add any update of a GRF to the HT, removing a previous write if it
2242 if (inst
->dst
.file
== GRF
) {
2243 if (inst
->regs_written
> 1) {
2244 /* We don't know how to trim channels from an instruction's
2245 * writes, so we can't incrementally remove unread channels from
2246 * it. Just remove whatever it overwrites from the table
2248 for (int i
= 0; i
< inst
->regs_written
; i
++) {
2249 remove_dead_code_hash(ht
,
2251 inst
->dst
.reg_offset
+ i
);
2254 struct hash_entry
*entry
=
2255 get_dead_code_hash_entry(ht
, inst
->dst
.reg
,
2256 inst
->dst
.reg_offset
);
2259 if (inst
->is_partial_write()) {
2260 /* For a partial write, we can't remove any previous dead code
2261 * candidate, since we're just modifying their result.
2264 /* We're completely updating a channel, and there was a
2265 * previous write to the channel that wasn't read. Kill it!
2267 fs_inst
*inst
= (fs_inst
*)entry
->data
;
2272 _mesa_hash_table_remove(ht
, entry
);
2275 if (!inst
->has_side_effects())
2276 insert_dead_code_hash(ht
, inst
->dst
.reg
, inst
->dst
.reg_offset
,
2282 _mesa_hash_table_destroy(ht
, NULL
);
2285 invalidate_live_intervals();
2291 * Implements register coalescing: Checks if the two registers involved in a
2292 * raw move don't interfere, in which case they can both be stored in the same
2293 * place and the MOV removed.
2295 * To do this, all uses of the source of the MOV in the shader are replaced
2296 * with the destination of the MOV. For example:
2298 * add vgrf3:F, vgrf1:F, vgrf2:F
2299 * mov vgrf4:F, vgrf3:F
2300 * mul vgrf5:F, vgrf5:F, vgrf4:F
2304 * add vgrf4:F, vgrf1:F, vgrf2:F
2305 * mul vgrf5:F, vgrf5:F, vgrf4:F
2308 fs_visitor::register_coalesce()
2310 bool progress
= false;
2312 calculate_live_intervals();
2315 int channels_remaining
= 0;
2316 int reg_from
= -1, reg_to
= -1;
2317 int reg_to_offset
[MAX_SAMPLER_MESSAGE_SIZE
];
2318 fs_inst
*mov
[MAX_SAMPLER_MESSAGE_SIZE
];
2320 foreach_list(node
, &this->instructions
) {
2321 fs_inst
*inst
= (fs_inst
*)node
;
2323 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2324 inst
->is_partial_write() ||
2326 inst
->src
[0].file
!= GRF
||
2327 inst
->src
[0].negate
||
2329 !inst
->src
[0].is_contiguous() ||
2330 inst
->dst
.file
!= GRF
||
2331 inst
->dst
.type
!= inst
->src
[0].type
) {
2335 if (virtual_grf_sizes
[inst
->src
[0].reg
] >
2336 virtual_grf_sizes
[inst
->dst
.reg
])
2339 int var_from
= live_intervals
->var_from_reg(&inst
->src
[0]);
2340 int var_to
= live_intervals
->var_from_reg(&inst
->dst
);
2342 if (live_intervals
->vars_interfere(var_from
, var_to
) &&
2343 !inst
->dst
.equals(inst
->src
[0])) {
2345 /* We know that the live ranges of A (var_from) and B (var_to)
2346 * interfere because of the ->vars_interfere() call above. If the end
2347 * of B's live range is after the end of A's range, then we know two
2349 * - the start of B's live range must be in A's live range (since we
2350 * already know the two ranges interfere, this is the only remaining
2352 * - the interference isn't of the form we're looking for (where B is
2353 * entirely inside A)
2355 if (live_intervals
->end
[var_to
] > live_intervals
->end
[var_from
])
2358 bool overwritten
= false;
2361 foreach_list(n
, &this->instructions
) {
2362 fs_inst
*scan_inst
= (fs_inst
*)n
;
2365 if (scan_inst
->is_control_flow()) {
2370 if (scan_ip
<= live_intervals
->start
[var_to
])
2373 if (scan_ip
> live_intervals
->end
[var_to
])
2376 if (scan_inst
->dst
.equals(inst
->dst
) ||
2377 scan_inst
->dst
.equals(inst
->src
[0])) {
2387 if (reg_from
!= inst
->src
[0].reg
) {
2388 reg_from
= inst
->src
[0].reg
;
2390 src_size
= virtual_grf_sizes
[inst
->src
[0].reg
];
2391 assert(src_size
<= MAX_SAMPLER_MESSAGE_SIZE
);
2393 channels_remaining
= src_size
;
2394 memset(mov
, 0, sizeof(mov
));
2396 reg_to
= inst
->dst
.reg
;
2399 if (reg_to
!= inst
->dst
.reg
)
2402 const int offset
= inst
->src
[0].reg_offset
;
2403 reg_to_offset
[offset
] = inst
->dst
.reg_offset
;
2405 channels_remaining
--;
2407 if (channels_remaining
)
2410 bool removed
= false;
2411 for (int i
= 0; i
< src_size
; i
++) {
2415 mov
[i
]->opcode
= BRW_OPCODE_NOP
;
2416 mov
[i
]->conditional_mod
= BRW_CONDITIONAL_NONE
;
2417 mov
[i
]->dst
= reg_undef
;
2418 mov
[i
]->src
[0] = reg_undef
;
2419 mov
[i
]->src
[1] = reg_undef
;
2420 mov
[i
]->src
[2] = reg_undef
;
2424 foreach_list(node
, &this->instructions
) {
2425 fs_inst
*scan_inst
= (fs_inst
*)node
;
2427 for (int i
= 0; i
< src_size
; i
++) {
2429 if (scan_inst
->dst
.file
== GRF
&&
2430 scan_inst
->dst
.reg
== reg_from
&&
2431 scan_inst
->dst
.reg_offset
== i
) {
2432 scan_inst
->dst
.reg
= reg_to
;
2433 scan_inst
->dst
.reg_offset
= reg_to_offset
[i
];
2435 for (int j
= 0; j
< 3; j
++) {
2436 if (scan_inst
->src
[j
].file
== GRF
&&
2437 scan_inst
->src
[j
].reg
== reg_from
&&
2438 scan_inst
->src
[j
].reg_offset
== i
) {
2439 scan_inst
->src
[j
].reg
= reg_to
;
2440 scan_inst
->src
[j
].reg_offset
= reg_to_offset
[i
];
2448 live_intervals
->start
[var_to
] = MIN2(live_intervals
->start
[var_to
],
2449 live_intervals
->start
[var_from
]);
2450 live_intervals
->end
[var_to
] = MAX2(live_intervals
->end
[var_to
],
2451 live_intervals
->end
[var_from
]);
2456 foreach_list_safe(node
, &this->instructions
) {
2457 fs_inst
*inst
= (fs_inst
*)node
;
2459 if (inst
->opcode
== BRW_OPCODE_NOP
) {
2466 invalidate_live_intervals();
2472 fs_visitor::compute_to_mrf()
2474 bool progress
= false;
2477 calculate_live_intervals();
2479 foreach_list_safe(node
, &this->instructions
) {
2480 fs_inst
*inst
= (fs_inst
*)node
;
2485 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2486 inst
->is_partial_write() ||
2487 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2488 inst
->dst
.type
!= inst
->src
[0].type
||
2489 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2490 !inst
->src
[0].is_contiguous() ||
2491 inst
->src
[0].subreg_offset
)
2494 /* Work out which hardware MRF registers are written by this
2497 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2499 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2500 mrf_high
= mrf_low
+ 4;
2501 } else if (dispatch_width
== 16 &&
2502 (!inst
->force_uncompressed
&& !inst
->force_sechalf
)) {
2503 mrf_high
= mrf_low
+ 1;
2508 /* Can't compute-to-MRF this GRF if someone else was going to
2511 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2514 /* Found a move of a GRF to a MRF. Let's see if we can go
2515 * rewrite the thing that made this GRF to write into the MRF.
2518 for (scan_inst
= (fs_inst
*)inst
->prev
;
2519 scan_inst
->prev
!= NULL
;
2520 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2521 if (scan_inst
->dst
.file
== GRF
&&
2522 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2523 /* Found the last thing to write our reg we want to turn
2524 * into a compute-to-MRF.
2527 /* If this one instruction didn't populate all the
2528 * channels, bail. We might be able to rewrite everything
2529 * that writes that reg, but it would require smarter
2530 * tracking to delay the rewriting until complete success.
2532 if (scan_inst
->is_partial_write())
2535 /* Things returning more than one register would need us to
2536 * understand coalescing out more than one MOV at a time.
2538 if (scan_inst
->regs_written
> 1)
2541 /* SEND instructions can't have MRF as a destination. */
2542 if (scan_inst
->mlen
)
2545 if (brw
->gen
== 6) {
2546 /* gen6 math instructions must have the destination be
2547 * GRF, so no compute-to-MRF for them.
2549 if (scan_inst
->is_math()) {
2554 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2555 /* Found the creator of our MRF's source value. */
2556 scan_inst
->dst
.file
= MRF
;
2557 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2558 scan_inst
->saturate
|= inst
->saturate
;
2565 /* We don't handle control flow here. Most computation of
2566 * values that end up in MRFs are shortly before the MRF
2569 if (scan_inst
->is_control_flow() && scan_inst
->opcode
!= BRW_OPCODE_IF
)
2572 /* You can't read from an MRF, so if someone else reads our
2573 * MRF's source GRF that we wanted to rewrite, that stops us.
2575 bool interfered
= false;
2576 for (int i
= 0; i
< 3; i
++) {
2577 if (scan_inst
->src
[i
].file
== GRF
&&
2578 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2579 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2586 if (scan_inst
->dst
.file
== MRF
) {
2587 /* If somebody else writes our MRF here, we can't
2588 * compute-to-MRF before that.
2590 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2593 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2594 scan_mrf_high
= scan_mrf_low
+ 4;
2595 } else if (dispatch_width
== 16 &&
2596 (!scan_inst
->force_uncompressed
&&
2597 !scan_inst
->force_sechalf
)) {
2598 scan_mrf_high
= scan_mrf_low
+ 1;
2600 scan_mrf_high
= scan_mrf_low
;
2603 if (mrf_low
== scan_mrf_low
||
2604 mrf_low
== scan_mrf_high
||
2605 mrf_high
== scan_mrf_low
||
2606 mrf_high
== scan_mrf_high
) {
2611 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2612 /* Found a SEND instruction, which means that there are
2613 * live values in MRFs from base_mrf to base_mrf +
2614 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2617 if (mrf_low
>= scan_inst
->base_mrf
&&
2618 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2621 if (mrf_high
>= scan_inst
->base_mrf
&&
2622 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2630 invalidate_live_intervals();
2636 * Walks through basic blocks, looking for repeated MRF writes and
2637 * removing the later ones.
2640 fs_visitor::remove_duplicate_mrf_writes()
2642 fs_inst
*last_mrf_move
[16];
2643 bool progress
= false;
2645 /* Need to update the MRF tracking for compressed instructions. */
2646 if (dispatch_width
== 16)
2649 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2651 foreach_list_safe(node
, &this->instructions
) {
2652 fs_inst
*inst
= (fs_inst
*)node
;
2654 if (inst
->is_control_flow()) {
2655 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2658 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2659 inst
->dst
.file
== MRF
) {
2660 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2661 if (prev_inst
&& inst
->equals(prev_inst
)) {
2668 /* Clear out the last-write records for MRFs that were overwritten. */
2669 if (inst
->dst
.file
== MRF
) {
2670 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2673 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2674 /* Found a SEND instruction, which will include two or fewer
2675 * implied MRF writes. We could do better here.
2677 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2678 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2682 /* Clear out any MRF move records whose sources got overwritten. */
2683 if (inst
->dst
.file
== GRF
) {
2684 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
2685 if (last_mrf_move
[i
] &&
2686 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2687 last_mrf_move
[i
] = NULL
;
2692 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2693 inst
->dst
.file
== MRF
&&
2694 inst
->src
[0].file
== GRF
&&
2695 !inst
->is_partial_write()) {
2696 last_mrf_move
[inst
->dst
.reg
] = inst
;
2701 invalidate_live_intervals();
2707 clear_deps_for_inst_src(fs_inst
*inst
, int dispatch_width
, bool *deps
,
2708 int first_grf
, int grf_len
)
2710 bool inst_simd16
= (dispatch_width
> 8 &&
2711 !inst
->force_uncompressed
&&
2712 !inst
->force_sechalf
);
2714 /* Clear the flag for registers that actually got read (as expected). */
2715 for (int i
= 0; i
< 3; i
++) {
2717 if (inst
->src
[i
].file
== GRF
) {
2718 grf
= inst
->src
[i
].reg
;
2719 } else if (inst
->src
[i
].file
== HW_REG
&&
2720 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2721 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2726 if (grf
>= first_grf
&&
2727 grf
< first_grf
+ grf_len
) {
2728 deps
[grf
- first_grf
] = false;
2730 deps
[grf
- first_grf
+ 1] = false;
2736 * Implements this workaround for the original 965:
2738 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2739 * check for post destination dependencies on this instruction, software
2740 * must ensure that there is no destination hazard for the case of ‘write
2741 * followed by a posted write’ shown in the following example.
2744 * 2. send r3.xy <rest of send instruction>
2747 * Due to no post-destination dependency check on the ‘send’, the above
2748 * code sequence could have two instructions (1 and 2) in flight at the
2749 * same time that both consider ‘r3’ as the target of their final writes.
2752 fs_visitor::insert_gen4_pre_send_dependency_workarounds(fs_inst
*inst
)
2754 int reg_size
= dispatch_width
/ 8;
2755 int write_len
= inst
->regs_written
* reg_size
;
2756 int first_write_grf
= inst
->dst
.reg
;
2757 bool needs_dep
[BRW_MAX_MRF
];
2758 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2760 memset(needs_dep
, false, sizeof(needs_dep
));
2761 memset(needs_dep
, true, write_len
);
2763 clear_deps_for_inst_src(inst
, dispatch_width
,
2764 needs_dep
, first_write_grf
, write_len
);
2766 /* Walk backwards looking for writes to registers we're writing which
2767 * aren't read since being written. If we hit the start of the program,
2768 * we assume that there are no outstanding dependencies on entry to the
2771 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->prev
;
2773 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2775 /* If we hit control flow, assume that there *are* outstanding
2776 * dependencies, and force their cleanup before our instruction.
2778 if (scan_inst
->is_control_flow()) {
2779 for (int i
= 0; i
< write_len
; i
++) {
2781 inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2787 bool scan_inst_simd16
= (dispatch_width
> 8 &&
2788 !scan_inst
->force_uncompressed
&&
2789 !scan_inst
->force_sechalf
);
2791 /* We insert our reads as late as possible on the assumption that any
2792 * instruction but a MOV that might have left us an outstanding
2793 * dependency has more latency than a MOV.
2795 if (scan_inst
->dst
.file
== GRF
) {
2796 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2797 int reg
= scan_inst
->dst
.reg
+ i
* reg_size
;
2799 if (reg
>= first_write_grf
&&
2800 reg
< first_write_grf
+ write_len
&&
2801 needs_dep
[reg
- first_write_grf
]) {
2802 inst
->insert_before(DEP_RESOLVE_MOV(reg
));
2803 needs_dep
[reg
- first_write_grf
] = false;
2804 if (scan_inst_simd16
)
2805 needs_dep
[reg
- first_write_grf
+ 1] = false;
2810 /* Clear the flag for registers that actually got read (as expected). */
2811 clear_deps_for_inst_src(scan_inst
, dispatch_width
,
2812 needs_dep
, first_write_grf
, write_len
);
2814 /* Continue the loop only if we haven't resolved all the dependencies */
2816 for (i
= 0; i
< write_len
; i
++) {
2826 * Implements this workaround for the original 965:
2828 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2829 * used as a destination register until after it has been sourced by an
2830 * instruction with a different destination register.
2833 fs_visitor::insert_gen4_post_send_dependency_workarounds(fs_inst
*inst
)
2835 int write_len
= inst
->regs_written
* dispatch_width
/ 8;
2836 int first_write_grf
= inst
->dst
.reg
;
2837 bool needs_dep
[BRW_MAX_MRF
];
2838 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2840 memset(needs_dep
, false, sizeof(needs_dep
));
2841 memset(needs_dep
, true, write_len
);
2842 /* Walk forwards looking for writes to registers we're writing which aren't
2843 * read before being written.
2845 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->next
;
2846 !scan_inst
->is_tail_sentinel();
2847 scan_inst
= (fs_inst
*)scan_inst
->next
) {
2848 /* If we hit control flow, force resolve all remaining dependencies. */
2849 if (scan_inst
->is_control_flow()) {
2850 for (int i
= 0; i
< write_len
; i
++) {
2852 scan_inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2857 /* Clear the flag for registers that actually got read (as expected). */
2858 clear_deps_for_inst_src(scan_inst
, dispatch_width
,
2859 needs_dep
, first_write_grf
, write_len
);
2861 /* We insert our reads as late as possible since they're reading the
2862 * result of a SEND, which has massive latency.
2864 if (scan_inst
->dst
.file
== GRF
&&
2865 scan_inst
->dst
.reg
>= first_write_grf
&&
2866 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
2867 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
2868 scan_inst
->insert_before(DEP_RESOLVE_MOV(scan_inst
->dst
.reg
));
2869 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
2872 /* Continue the loop only if we haven't resolved all the dependencies */
2874 for (i
= 0; i
< write_len
; i
++) {
2882 /* If we hit the end of the program, resolve all remaining dependencies out
2885 fs_inst
*last_inst
= (fs_inst
*)this->instructions
.get_tail();
2886 assert(last_inst
->eot
);
2887 for (int i
= 0; i
< write_len
; i
++) {
2889 last_inst
->insert_before(DEP_RESOLVE_MOV(first_write_grf
+ i
));
2894 fs_visitor::insert_gen4_send_dependency_workarounds()
2896 if (brw
->gen
!= 4 || brw
->is_g4x
)
2899 /* Note that we're done with register allocation, so GRF fs_regs always
2900 * have a .reg_offset of 0.
2903 foreach_list_safe(node
, &this->instructions
) {
2904 fs_inst
*inst
= (fs_inst
*)node
;
2906 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
2907 insert_gen4_pre_send_dependency_workarounds(inst
);
2908 insert_gen4_post_send_dependency_workarounds(inst
);
2914 * Turns the generic expression-style uniform pull constant load instruction
2915 * into a hardware-specific series of instructions for loading a pull
2918 * The expression style allows the CSE pass before this to optimize out
2919 * repeated loads from the same offset, and gives the pre-register-allocation
2920 * scheduling full flexibility, while the conversion to native instructions
2921 * allows the post-register-allocation scheduler the best information
2924 * Note that execution masking for setting up pull constant loads is special:
2925 * the channels that need to be written are unrelated to the current execution
2926 * mask, since a later instruction will use one of the result channels as a
2927 * source operand for all 8 or 16 of its channels.
2930 fs_visitor::lower_uniform_pull_constant_loads()
2932 foreach_list(node
, &this->instructions
) {
2933 fs_inst
*inst
= (fs_inst
*)node
;
2935 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
2938 if (brw
->gen
>= 7) {
2939 /* The offset arg before was a vec4-aligned byte offset. We need to
2940 * turn it into a dword offset.
2942 fs_reg const_offset_reg
= inst
->src
[1];
2943 assert(const_offset_reg
.file
== IMM
&&
2944 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
2945 const_offset_reg
.imm
.u
/= 4;
2946 fs_reg payload
= fs_reg(this, glsl_type::uint_type
);
2948 /* This is actually going to be a MOV, but since only the first dword
2949 * is accessed, we have a special opcode to do just that one. Note
2950 * that this needs to be an operation that will be considered a def
2951 * by live variable analysis, or register allocation will explode.
2953 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
2954 payload
, const_offset_reg
);
2955 setup
->force_writemask_all
= true;
2957 setup
->ir
= inst
->ir
;
2958 setup
->annotation
= inst
->annotation
;
2959 inst
->insert_before(setup
);
2961 /* Similarly, this will only populate the first 4 channels of the
2962 * result register (since we only use smear values from 0-3), but we
2963 * don't tell the optimizer.
2965 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
2966 inst
->src
[1] = payload
;
2968 invalidate_live_intervals();
2970 /* Before register allocation, we didn't tell the scheduler about the
2971 * MRF we use. We know it's safe to use this MRF because nothing
2972 * else does except for register spill/unspill, which generates and
2973 * uses its MRF within a single IR instruction.
2975 inst
->base_mrf
= 14;
2982 fs_visitor::dump_instructions()
2984 calculate_register_pressure();
2986 int ip
= 0, max_pressure
= 0;
2987 foreach_list(node
, &this->instructions
) {
2988 backend_instruction
*inst
= (backend_instruction
*)node
;
2989 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
2990 fprintf(stderr
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
2991 dump_instruction(inst
);
2994 fprintf(stderr
, "Maximum %3d registers live at once.\n", max_pressure
);
2998 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
3000 fs_inst
*inst
= (fs_inst
*)be_inst
;
3002 if (inst
->predicate
) {
3003 fprintf(stderr
, "(%cf0.%d) ",
3004 inst
->predicate_inverse
? '-' : '+',
3008 fprintf(stderr
, "%s", brw_instruction_name(inst
->opcode
));
3010 fprintf(stderr
, ".sat");
3011 if (inst
->conditional_mod
) {
3012 fprintf(stderr
, "%s", conditional_modifier
[inst
->conditional_mod
]);
3013 if (!inst
->predicate
&&
3014 (brw
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
3015 inst
->opcode
!= BRW_OPCODE_IF
&&
3016 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
3017 fprintf(stderr
, ".f0.%d", inst
->flag_subreg
);
3020 fprintf(stderr
, " ");
3023 switch (inst
->dst
.file
) {
3025 fprintf(stderr
, "vgrf%d", inst
->dst
.reg
);
3026 if (virtual_grf_sizes
[inst
->dst
.reg
] != 1 ||
3027 inst
->dst
.subreg_offset
)
3028 fprintf(stderr
, "+%d.%d",
3029 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
3032 fprintf(stderr
, "m%d", inst
->dst
.reg
);
3035 fprintf(stderr
, "(null)");
3038 fprintf(stderr
, "***u%d***", inst
->dst
.reg
);
3041 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3042 switch (inst
->dst
.fixed_hw_reg
.nr
) {
3044 fprintf(stderr
, "null");
3046 case BRW_ARF_ADDRESS
:
3047 fprintf(stderr
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
3049 case BRW_ARF_ACCUMULATOR
:
3050 fprintf(stderr
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
3053 fprintf(stderr
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3054 inst
->dst
.fixed_hw_reg
.subnr
);
3057 fprintf(stderr
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3058 inst
->dst
.fixed_hw_reg
.subnr
);
3062 fprintf(stderr
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
3064 if (inst
->dst
.fixed_hw_reg
.subnr
)
3065 fprintf(stderr
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
3068 fprintf(stderr
, "???");
3071 fprintf(stderr
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
3073 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
3074 if (inst
->src
[i
].negate
)
3075 fprintf(stderr
, "-");
3076 if (inst
->src
[i
].abs
)
3077 fprintf(stderr
, "|");
3078 switch (inst
->src
[i
].file
) {
3080 fprintf(stderr
, "vgrf%d", inst
->src
[i
].reg
);
3081 if (virtual_grf_sizes
[inst
->src
[i
].reg
] != 1 ||
3082 inst
->src
[i
].subreg_offset
)
3083 fprintf(stderr
, "+%d.%d", inst
->src
[i
].reg_offset
,
3084 inst
->src
[i
].subreg_offset
);
3087 fprintf(stderr
, "***m%d***", inst
->src
[i
].reg
);
3090 fprintf(stderr
, "u%d", inst
->src
[i
].reg
);
3091 if (virtual_grf_sizes
[inst
->src
[i
].reg
] != 1 ||
3092 inst
->src
[i
].subreg_offset
)
3093 fprintf(stderr
, "+%d.%d", inst
->src
[i
].reg_offset
,
3094 inst
->src
[i
].subreg_offset
);
3097 fprintf(stderr
, "(null)");
3100 switch (inst
->src
[i
].type
) {
3101 case BRW_REGISTER_TYPE_F
:
3102 fprintf(stderr
, "%ff", inst
->src
[i
].imm
.f
);
3104 case BRW_REGISTER_TYPE_D
:
3105 fprintf(stderr
, "%dd", inst
->src
[i
].imm
.i
);
3107 case BRW_REGISTER_TYPE_UD
:
3108 fprintf(stderr
, "%uu", inst
->src
[i
].imm
.u
);
3111 fprintf(stderr
, "???");
3116 if (inst
->src
[i
].fixed_hw_reg
.negate
)
3117 fprintf(stderr
, "-");
3118 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3119 fprintf(stderr
, "|");
3120 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3121 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
3123 fprintf(stderr
, "null");
3125 case BRW_ARF_ADDRESS
:
3126 fprintf(stderr
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3128 case BRW_ARF_ACCUMULATOR
:
3129 fprintf(stderr
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3132 fprintf(stderr
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3133 inst
->src
[i
].fixed_hw_reg
.subnr
);
3136 fprintf(stderr
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3137 inst
->src
[i
].fixed_hw_reg
.subnr
);
3141 fprintf(stderr
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
3143 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
3144 fprintf(stderr
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3145 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3146 fprintf(stderr
, "|");
3149 fprintf(stderr
, "???");
3152 if (inst
->src
[i
].abs
)
3153 fprintf(stderr
, "|");
3155 if (inst
->src
[i
].file
!= IMM
) {
3156 fprintf(stderr
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
3159 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
3160 fprintf(stderr
, ", ");
3163 fprintf(stderr
, " ");
3165 if (inst
->force_uncompressed
)
3166 fprintf(stderr
, "1sthalf ");
3168 if (inst
->force_sechalf
)
3169 fprintf(stderr
, "2ndhalf ");
3171 fprintf(stderr
, "\n");
3175 * Possibly returns an instruction that set up @param reg.
3177 * Sometimes we want to take the result of some expression/variable
3178 * dereference tree and rewrite the instruction generating the result
3179 * of the tree. When processing the tree, we know that the
3180 * instructions generated are all writing temporaries that are dead
3181 * outside of this tree. So, if we have some instructions that write
3182 * a temporary, we're free to point that temp write somewhere else.
3184 * Note that this doesn't guarantee that the instruction generated
3185 * only reg -- it might be the size=4 destination of a texture instruction.
3188 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
3193 end
->is_partial_write() ||
3195 !reg
.equals(end
->dst
)) {
3203 fs_visitor::setup_payload_gen6()
3206 (fp
->Base
.InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
3207 unsigned barycentric_interp_modes
= c
->prog_data
.barycentric_interp_modes
;
3209 assert(brw
->gen
>= 6);
3211 /* R0-1: masks, pixel X/Y coordinates. */
3212 c
->nr_payload_regs
= 2;
3213 /* R2: only for 32-pixel dispatch.*/
3215 /* R3-26: barycentric interpolation coordinates. These appear in the
3216 * same order that they appear in the brw_wm_barycentric_interp_mode
3217 * enum. Each set of coordinates occupies 2 registers if dispatch width
3218 * == 8 and 4 registers if dispatch width == 16. Coordinates only
3219 * appear if they were enabled using the "Barycentric Interpolation
3220 * Mode" bits in WM_STATE.
3222 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
3223 if (barycentric_interp_modes
& (1 << i
)) {
3224 c
->barycentric_coord_reg
[i
] = c
->nr_payload_regs
;
3225 c
->nr_payload_regs
+= 2;
3226 if (dispatch_width
== 16) {
3227 c
->nr_payload_regs
+= 2;
3232 /* R27: interpolated depth if uses source depth */
3234 c
->source_depth_reg
= c
->nr_payload_regs
;
3235 c
->nr_payload_regs
++;
3236 if (dispatch_width
== 16) {
3237 /* R28: interpolated depth if not SIMD8. */
3238 c
->nr_payload_regs
++;
3241 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
3243 c
->source_w_reg
= c
->nr_payload_regs
;
3244 c
->nr_payload_regs
++;
3245 if (dispatch_width
== 16) {
3246 /* R30: interpolated W if not SIMD8. */
3247 c
->nr_payload_regs
++;
3251 c
->prog_data
.uses_pos_offset
= c
->key
.compute_pos_offset
;
3252 /* R31: MSAA position offsets. */
3253 if (c
->prog_data
.uses_pos_offset
) {
3254 c
->sample_pos_reg
= c
->nr_payload_regs
;
3255 c
->nr_payload_regs
++;
3258 /* R32: MSAA input coverage mask */
3259 if (fp
->Base
.SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
3260 assert(brw
->gen
>= 7);
3261 c
->sample_mask_reg
= c
->nr_payload_regs
;
3262 c
->nr_payload_regs
++;
3263 if (dispatch_width
== 16) {
3264 /* R33: input coverage mask if not SIMD8. */
3265 c
->nr_payload_regs
++;
3269 /* R34-: bary for 32-pixel. */
3270 /* R58-59: interp W for 32-pixel. */
3272 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3273 c
->source_depth_to_render_target
= true;
3278 fs_visitor::assign_binding_table_offsets()
3280 uint32_t next_binding_table_offset
= 0;
3282 /* If there are no color regions, we still perform an FB write to a null
3283 * renderbuffer, which we place at surface index 0.
3285 c
->prog_data
.binding_table
.render_target_start
= next_binding_table_offset
;
3286 next_binding_table_offset
+= MAX2(c
->key
.nr_color_regions
, 1);
3288 assign_common_binding_table_offsets(next_binding_table_offset
);
3292 fs_visitor::calculate_register_pressure()
3294 calculate_live_intervals();
3296 int num_instructions
= 0;
3297 foreach_list(node
, &this->instructions
) {
3301 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
3303 for (int reg
= 0; reg
< virtual_grf_count
; reg
++) {
3304 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
3305 regs_live_at_ip
[ip
] += virtual_grf_sizes
[reg
];
3310 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
3312 * The needs_unlit_centroid_workaround ends up producing one of these per
3313 * channel of centroid input, so it's good to clean them up.
3315 * An assumption here is that nothing ever modifies the dispatched pixels
3316 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
3317 * dictates that anyway.
3320 fs_visitor::opt_drop_redundant_mov_to_flags()
3322 bool flag_mov_found
[2] = {false};
3324 foreach_list_safe(node
, &this->instructions
) {
3325 fs_inst
*inst
= (fs_inst
*)node
;
3327 if (inst
->is_control_flow()) {
3328 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
3329 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
3330 if (!flag_mov_found
[inst
->flag_subreg
])
3331 flag_mov_found
[inst
->flag_subreg
] = true;
3334 } else if (inst
->writes_flag()) {
3335 flag_mov_found
[inst
->flag_subreg
] = false;
3343 sanity_param_count
= fp
->Base
.Parameters
->NumParameters
;
3344 bool allocated_without_spills
;
3346 assign_binding_table_offsets();
3349 setup_payload_gen6();
3351 setup_payload_gen4();
3356 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3357 emit_shader_time_begin();
3359 calculate_urb_setup();
3360 if (fp
->Base
.InputsRead
> 0) {
3362 emit_interpolation_setup_gen4();
3364 emit_interpolation_setup_gen6();
3367 /* We handle discards by keeping track of the still-live pixels in f0.1.
3368 * Initialize it with the dispatched pixels.
3370 if (fp
->UsesKill
|| c
->key
.alpha_test_func
) {
3371 fs_inst
*discard_init
= emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
3372 discard_init
->flag_subreg
= 1;
3375 /* Generate FS IR for main(). (the visitor only descends into
3376 * functions called "main").
3379 foreach_list(node
, &*shader
->base
.ir
) {
3380 ir_instruction
*ir
= (ir_instruction
*)node
;
3382 this->result
= reg_undef
;
3386 emit_fragment_program_code();
3392 emit(FS_OPCODE_PLACEHOLDER_HALT
);
3394 if (c
->key
.alpha_test_func
)
3399 split_virtual_grfs();
3401 move_uniform_array_access_to_pull_constants();
3402 remove_dead_constants();
3403 setup_pull_constants();
3405 opt_drop_redundant_mov_to_flags();
3411 compact_virtual_grfs();
3413 progress
= remove_duplicate_mrf_writes() || progress
;
3415 progress
= opt_algebraic() || progress
;
3416 progress
= opt_cse() || progress
;
3417 progress
= opt_copy_propagate() || progress
;
3418 progress
= opt_peephole_predicated_break() || progress
;
3419 progress
= dead_code_eliminate() || progress
;
3420 progress
= dead_code_eliminate_local() || progress
;
3421 progress
= opt_peephole_sel() || progress
;
3422 progress
= dead_control_flow_eliminate(this) || progress
;
3423 progress
= opt_saturate_propagation() || progress
;
3424 progress
= register_coalesce() || progress
;
3425 progress
= compute_to_mrf() || progress
;
3428 lower_uniform_pull_constant_loads();
3430 assign_curb_setup();
3433 static enum instruction_scheduler_mode pre_modes
[] = {
3435 SCHEDULE_PRE_NON_LIFO
,
3439 /* Try each scheduling heuristic to see if it can successfully register
3440 * allocate without spilling. They should be ordered by decreasing
3441 * performance but increasing likelihood of allocating.
3443 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
3444 schedule_instructions(pre_modes
[i
]);
3447 assign_regs_trivial();
3448 allocated_without_spills
= true;
3450 allocated_without_spills
= assign_regs(false);
3452 if (allocated_without_spills
)
3456 if (!allocated_without_spills
) {
3457 /* We assume that any spilling is worse than just dropping back to
3458 * SIMD8. There's probably actually some intermediate point where
3459 * SIMD16 with a couple of spills is still better.
3461 if (dispatch_width
== 16) {
3462 fail("Failure to register allocate. Reduce number of "
3463 "live scalar values to avoid this.");
3466 /* Since we're out of heuristics, just go spill registers until we
3467 * get an allocation.
3469 while (!assign_regs(true)) {
3475 assert(force_uncompressed_stack
== 0);
3477 /* This must come after all optimization and register allocation, since
3478 * it inserts dead code that happens to have side effects, and it does
3479 * so based on the actual physical registers in use.
3481 insert_gen4_send_dependency_workarounds();
3486 if (!allocated_without_spills
)
3487 schedule_instructions(SCHEDULE_POST
);
3489 if (dispatch_width
== 8)
3490 c
->prog_data
.reg_blocks
= brw_register_blocks(grf_used
);
3492 c
->prog_data
.reg_blocks_16
= brw_register_blocks(grf_used
);
3494 /* If any state parameters were appended, then ParameterValues could have
3495 * been realloced, in which case the driver uniform storage set up by
3496 * _mesa_associate_uniform_storage() would point to freed memory. Make
3497 * sure that didn't happen.
3499 assert(sanity_param_count
== fp
->Base
.Parameters
->NumParameters
);
3505 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
,
3506 struct gl_fragment_program
*fp
,
3507 struct gl_shader_program
*prog
,
3508 unsigned *final_assembly_size
)
3510 bool start_busy
= false;
3511 double start_time
= 0;
3513 if (unlikely(brw
->perf_debug
)) {
3514 start_busy
= (brw
->batch
.last_bo
&&
3515 drm_intel_bo_busy(brw
->batch
.last_bo
));
3516 start_time
= get_time();
3519 struct brw_shader
*shader
= NULL
;
3521 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3523 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
3524 brw_dump_ir(brw
, "fragment", prog
, &shader
->base
, &fp
->Base
);
3526 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3528 fs_visitor
v(brw
, c
, prog
, fp
, 8);
3531 prog
->LinkStatus
= false;
3532 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
3535 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
3541 exec_list
*simd16_instructions
= NULL
;
3542 fs_visitor
v2(brw
, c
, prog
, fp
, 16);
3543 if (brw
->gen
>= 5 && likely(!(INTEL_DEBUG
& DEBUG_NO16
))) {
3544 if (c
->prog_data
.base
.nr_pull_params
== 0) {
3545 /* Try a SIMD16 compile */
3546 v2
.import_uniforms(&v
);
3548 perf_debug("SIMD16 shader failed to compile, falling back to "
3549 "SIMD8 at a 10-20%% performance cost: %s", v2
.fail_msg
);
3551 simd16_instructions
= &v2
.instructions
;
3554 perf_debug("Skipping SIMD16 due to pull parameters.\n");
3558 const unsigned *assembly
= NULL
;
3559 if (brw
->gen
>= 8) {
3560 gen8_fs_generator
g(brw
, c
, prog
, fp
, v
.dual_src_output
.file
!= BAD_FILE
);
3561 assembly
= g
.generate_assembly(&v
.instructions
, simd16_instructions
,
3562 final_assembly_size
);
3564 fs_generator
g(brw
, c
, prog
, fp
, v
.dual_src_output
.file
!= BAD_FILE
);
3565 assembly
= g
.generate_assembly(&v
.instructions
, simd16_instructions
,
3566 final_assembly_size
);
3569 if (unlikely(brw
->perf_debug
) && shader
) {
3570 if (shader
->compiled_once
)
3571 brw_wm_debug_recompile(brw
, prog
, &c
->key
);
3572 shader
->compiled_once
= true;
3574 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
3575 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
3576 (get_time() - start_time
) * 1000);
3584 brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
3586 struct brw_context
*brw
= brw_context(ctx
);
3587 struct brw_wm_prog_key key
;
3589 if (!prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
])
3592 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)
3593 prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
]->Program
;
3594 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
3595 bool program_uses_dfdy
= fp
->UsesDFdy
;
3597 memset(&key
, 0, sizeof(key
));
3601 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
3603 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
3604 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
3606 /* Just assume depth testing. */
3607 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
3608 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
3611 if (brw
->gen
< 6 || _mesa_bitcount_64(fp
->Base
.InputsRead
&
3612 BRW_FS_VARYING_INPUT_MASK
) > 16)
3613 key
.input_slots_valid
= fp
->Base
.InputsRead
| VARYING_BIT_POS
;
3615 key
.clamp_fragment_color
= ctx
->API
== API_OPENGL_COMPAT
;
3617 unsigned sampler_count
= _mesa_fls(fp
->Base
.SamplersUsed
);
3618 for (unsigned i
= 0; i
< sampler_count
; i
++) {
3619 if (fp
->Base
.ShadowSamplers
& (1 << i
)) {
3620 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
3621 key
.tex
.swizzles
[i
] =
3622 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
3624 /* Color sampler: assume no swizzling. */
3625 key
.tex
.swizzles
[i
] = SWIZZLE_XYZW
;
3629 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
) {
3630 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
3633 key
.nr_color_regions
= _mesa_bitcount_64(fp
->Base
.OutputsWritten
&
3634 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
3635 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
)));
3637 if ((fp
->Base
.InputsRead
& VARYING_BIT_POS
) || program_uses_dfdy
) {
3638 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
) ||
3639 key
.nr_color_regions
> 1;
3642 /* GL_FRAGMENT_SHADER_DERIVATIVE_HINT is almost always GL_DONT_CARE. The
3643 * quality of the derivatives is likely to be determined by the driconf
3646 key
.high_quality_derivatives
= brw
->disable_derivative_optimization
;
3648 key
.program_string_id
= bfp
->id
;
3650 uint32_t old_prog_offset
= brw
->wm
.base
.prog_offset
;
3651 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
3653 bool success
= do_wm_prog(brw
, prog
, bfp
, &key
);
3655 brw
->wm
.base
.prog_offset
= old_prog_offset
;
3656 brw
->wm
.prog_data
= old_prog_data
;