2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "main/macros.h"
36 #include "main/shaderobj.h"
37 #include "main/uniforms.h"
38 #include "program/prog_parameter.h"
39 #include "program/prog_print.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
47 #include "brw_shader.h"
49 #include "glsl/glsl_types.h"
50 #include "glsl/ir_print_visitor.h"
52 #define MAX_INSTRUCTION (1 << 30)
55 fs_visitor::type_size(const struct glsl_type
*type
)
59 switch (type
->base_type
) {
64 return type
->components();
66 return type_size(type
->fields
.array
) * type
->length
;
67 case GLSL_TYPE_STRUCT
:
69 for (i
= 0; i
< type
->length
; i
++) {
70 size
+= type_size(type
->fields
.structure
[i
].type
);
73 case GLSL_TYPE_SAMPLER
:
74 /* Samplers take up no register space, since they're baked in at
79 assert(!"not reached");
85 fs_visitor::fail(const char *format
, ...)
96 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
98 msg
= ralloc_asprintf(mem_ctx
, "FS compile failed: %s\n", msg
);
100 this->fail_msg
= msg
;
102 if (INTEL_DEBUG
& DEBUG_WM
) {
103 fprintf(stderr
, "%s", msg
);
108 fs_visitor::push_force_uncompressed()
110 force_uncompressed_stack
++;
114 fs_visitor::pop_force_uncompressed()
116 force_uncompressed_stack
--;
117 assert(force_uncompressed_stack
>= 0);
121 fs_visitor::push_force_sechalf()
123 force_sechalf_stack
++;
127 fs_visitor::pop_force_sechalf()
129 force_sechalf_stack
--;
130 assert(force_sechalf_stack
>= 0);
134 * Returns how many MRFs an FS opcode will write over.
136 * Note that this is not the 0 or 1 implied writes in an actual gen
137 * instruction -- the FS opcodes often generate MOVs in addition.
140 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
145 switch (inst
->opcode
) {
146 case SHADER_OPCODE_RCP
:
147 case SHADER_OPCODE_RSQ
:
148 case SHADER_OPCODE_SQRT
:
149 case SHADER_OPCODE_EXP2
:
150 case SHADER_OPCODE_LOG2
:
151 case SHADER_OPCODE_SIN
:
152 case SHADER_OPCODE_COS
:
153 return 1 * c
->dispatch_width
/ 8;
154 case SHADER_OPCODE_POW
:
155 return 2 * c
->dispatch_width
/ 8;
162 case FS_OPCODE_FB_WRITE
:
164 case FS_OPCODE_PULL_CONSTANT_LOAD
:
165 case FS_OPCODE_UNSPILL
:
167 case FS_OPCODE_SPILL
:
170 assert(!"not reached");
176 fs_visitor::virtual_grf_alloc(int size
)
178 if (virtual_grf_array_size
<= virtual_grf_next
) {
179 if (virtual_grf_array_size
== 0)
180 virtual_grf_array_size
= 16;
182 virtual_grf_array_size
*= 2;
183 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
184 virtual_grf_array_size
);
186 virtual_grf_sizes
[virtual_grf_next
] = size
;
187 return virtual_grf_next
++;
190 /** Fixed HW reg constructor. */
191 fs_reg::fs_reg(enum register_file file
, int reg
)
196 this->type
= BRW_REGISTER_TYPE_F
;
199 /** Fixed HW reg constructor. */
200 fs_reg::fs_reg(enum register_file file
, int reg
, uint32_t type
)
208 /** Automatic reg constructor. */
209 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
214 this->reg
= v
->virtual_grf_alloc(v
->type_size(type
));
215 this->reg_offset
= 0;
216 this->type
= brw_type_for_base_type(type
);
220 fs_visitor::variable_storage(ir_variable
*var
)
222 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
226 import_uniforms_callback(const void *key
,
230 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
231 const fs_reg
*reg
= (const fs_reg
*)data
;
233 if (reg
->file
!= UNIFORM
)
236 hash_table_insert(dst_ht
, data
, key
);
239 /* For 16-wide, we need to follow from the uniform setup of 8-wide dispatch.
240 * This brings in those uniform definitions
243 fs_visitor::import_uniforms(fs_visitor
*v
)
245 hash_table_call_foreach(v
->variable_ht
,
246 import_uniforms_callback
,
248 this->params_remap
= v
->params_remap
;
251 /* Our support for uniforms is piggy-backed on the struct
252 * gl_fragment_program, because that's where the values actually
253 * get stored, rather than in some global gl_shader_program uniform
257 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
259 unsigned int offset
= 0;
261 if (type
->is_matrix()) {
262 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
263 type
->vector_elements
,
266 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
267 offset
+= setup_uniform_values(loc
+ offset
, column
);
273 switch (type
->base_type
) {
274 case GLSL_TYPE_FLOAT
:
278 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
279 unsigned int param
= c
->prog_data
.nr_params
++;
281 assert(param
< ARRAY_SIZE(c
->prog_data
.param
));
283 if (ctx
->Const
.NativeIntegers
) {
284 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
286 switch (type
->base_type
) {
287 case GLSL_TYPE_FLOAT
:
288 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
291 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2U
;
294 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2I
;
297 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2B
;
300 assert(!"not reached");
301 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
305 this->param_index
[param
] = loc
;
306 this->param_offset
[param
] = i
;
310 case GLSL_TYPE_STRUCT
:
311 for (unsigned int i
= 0; i
< type
->length
; i
++) {
312 offset
+= setup_uniform_values(loc
+ offset
,
313 type
->fields
.structure
[i
].type
);
317 case GLSL_TYPE_ARRAY
:
318 for (unsigned int i
= 0; i
< type
->length
; i
++) {
319 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
323 case GLSL_TYPE_SAMPLER
:
324 /* The sampler takes up a slot, but we don't use any values from it. */
328 assert(!"not reached");
334 /* Our support for builtin uniforms is even scarier than non-builtin.
335 * It sits on top of the PROG_STATE_VAR parameters that are
336 * automatically updated from GL context state.
339 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
341 const ir_state_slot
*const slots
= ir
->state_slots
;
342 assert(ir
->state_slots
!= NULL
);
344 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
345 /* This state reference has already been setup by ir_to_mesa, but we'll
346 * get the same index back here.
348 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
349 (gl_state_index
*)slots
[i
].tokens
);
351 /* Add each of the unique swizzles of the element as a parameter.
352 * This'll end up matching the expected layout of the
353 * array/matrix/structure we're trying to fill in.
356 for (unsigned int j
= 0; j
< 4; j
++) {
357 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
358 if (swiz
== last_swiz
)
362 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
364 this->param_index
[c
->prog_data
.nr_params
] = index
;
365 this->param_offset
[c
->prog_data
.nr_params
] = swiz
;
366 c
->prog_data
.nr_params
++;
372 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
374 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
376 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
379 if (ir
->pixel_center_integer
) {
380 emit(BRW_OPCODE_MOV
, wpos
, this->pixel_x
);
382 emit(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
));
387 if (!flip
&& ir
->pixel_center_integer
) {
388 emit(BRW_OPCODE_MOV
, wpos
, this->pixel_y
);
390 fs_reg pixel_y
= this->pixel_y
;
391 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
394 pixel_y
.negate
= true;
395 offset
+= c
->key
.drawable_height
- 1.0;
398 emit(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
));
403 if (intel
->gen
>= 6) {
404 emit(BRW_OPCODE_MOV
, wpos
,
405 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0)));
407 emit(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
408 interp_reg(FRAG_ATTRIB_WPOS
, 2));
412 /* gl_FragCoord.w: Already set up in emit_interpolation */
413 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
419 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
421 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
422 /* Interpolation is always in floating point regs. */
423 reg
->type
= BRW_REGISTER_TYPE_F
;
426 unsigned int array_elements
;
427 const glsl_type
*type
;
429 if (ir
->type
->is_array()) {
430 array_elements
= ir
->type
->length
;
431 if (array_elements
== 0) {
432 fail("dereferenced array '%s' has length 0\n", ir
->name
);
434 type
= ir
->type
->fields
.array
;
440 int location
= ir
->location
;
441 for (unsigned int i
= 0; i
< array_elements
; i
++) {
442 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
443 if (urb_setup
[location
] == -1) {
444 /* If there's no incoming setup data for this slot, don't
445 * emit interpolation for it.
447 attr
.reg_offset
+= type
->vector_elements
;
453 location
== FRAG_ATTRIB_COL0
|| location
== FRAG_ATTRIB_COL1
;
455 if (c
->key
.flat_shade
&& is_gl_Color
) {
456 /* Constant interpolation (flat shading) case. The SF has
457 * handed us defined values in only the constant offset
458 * field of the setup reg.
460 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
461 struct brw_reg interp
= interp_reg(location
, k
);
462 interp
= suboffset(interp
, 3);
463 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
467 /* Perspective interpolation case. */
468 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
469 /* FINISHME: At some point we probably want to push
470 * this farther by giving similar treatment to the
471 * other potentially constant components of the
472 * attribute, as well as making brw_vs_constval.c
473 * handle varyings other than gl_TexCoord.
475 if (location
>= FRAG_ATTRIB_TEX0
&&
476 location
<= FRAG_ATTRIB_TEX7
&&
477 k
== 3 && !(c
->key
.proj_attrib_mask
& (1 << location
))) {
478 emit(BRW_OPCODE_MOV
, attr
, fs_reg(1.0f
));
480 struct brw_reg interp
= interp_reg(location
, k
);
481 emit(FS_OPCODE_LINTERP
, attr
,
482 this->delta_x
, this->delta_y
, fs_reg(interp
));
487 if (intel
->gen
< 6) {
488 attr
.reg_offset
-= type
->vector_elements
;
489 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
490 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
503 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
505 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
507 /* The frontfacing comes in as a bit in the thread payload. */
508 if (intel
->gen
>= 6) {
509 emit(BRW_OPCODE_ASR
, *reg
,
510 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
512 emit(BRW_OPCODE_NOT
, *reg
, *reg
);
513 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1));
515 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
516 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
519 fs_inst
*inst
= emit(BRW_OPCODE_CMP
, *reg
,
522 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
523 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u));
530 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src
)
533 case SHADER_OPCODE_RCP
:
534 case SHADER_OPCODE_RSQ
:
535 case SHADER_OPCODE_SQRT
:
536 case SHADER_OPCODE_EXP2
:
537 case SHADER_OPCODE_LOG2
:
538 case SHADER_OPCODE_SIN
:
539 case SHADER_OPCODE_COS
:
542 assert(!"not reached: bad math opcode");
546 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
547 * might be able to do better by doing execsize = 1 math and then
548 * expanding that result out, but we would need to be careful with
551 * The hardware ignores source modifiers (negate and abs) on math
552 * instructions, so we also move to a temp to set those up.
554 if (intel
->gen
>= 6 && (src
.file
== UNIFORM
||
557 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
558 emit(BRW_OPCODE_MOV
, expanded
, src
);
562 fs_inst
*inst
= emit(opcode
, dst
, src
);
564 if (intel
->gen
< 6) {
566 inst
->mlen
= c
->dispatch_width
/ 8;
573 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
578 assert(opcode
== SHADER_OPCODE_POW
);
580 if (intel
->gen
>= 6) {
581 /* Can't do hstride == 0 args to gen6 math, so expand it out.
583 * The hardware ignores source modifiers (negate and abs) on math
584 * instructions, so we also move to a temp to set those up.
586 if (src0
.file
== UNIFORM
|| src0
.abs
|| src0
.negate
) {
587 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
588 emit(BRW_OPCODE_MOV
, expanded
, src0
);
592 if (src1
.file
== UNIFORM
|| src1
.abs
|| src1
.negate
) {
593 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
594 emit(BRW_OPCODE_MOV
, expanded
, src1
);
598 inst
= emit(opcode
, dst
, src0
, src1
);
600 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1), src1
);
601 inst
= emit(opcode
, dst
, src0
, reg_null_f
);
603 inst
->base_mrf
= base_mrf
;
604 inst
->mlen
= 2 * c
->dispatch_width
/ 8;
610 * To be called after the last _mesa_add_state_reference() call, to
611 * set up prog_data.param[] for assign_curb_setup() and
612 * setup_pull_constants().
615 fs_visitor::setup_paramvalues_refs()
617 if (c
->dispatch_width
!= 8)
620 /* Set up the pointers to ParamValues now that that array is finalized. */
621 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
622 c
->prog_data
.param
[i
] =
623 (const float *)fp
->Base
.Parameters
->ParameterValues
[this->param_index
[i
]] +
624 this->param_offset
[i
];
629 fs_visitor::assign_curb_setup()
631 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
632 if (c
->dispatch_width
== 8) {
633 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
635 c
->prog_data
.first_curbe_grf_16
= c
->nr_payload_regs
;
638 /* Map the offsets in the UNIFORM file to fixed HW regs. */
639 foreach_list(node
, &this->instructions
) {
640 fs_inst
*inst
= (fs_inst
*)node
;
642 for (unsigned int i
= 0; i
< 3; i
++) {
643 if (inst
->src
[i
].file
== UNIFORM
) {
644 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
645 struct brw_reg brw_reg
= brw_vec1_grf(c
->nr_payload_regs
+
649 inst
->src
[i
].file
= FIXED_HW_REG
;
650 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
657 fs_visitor::calculate_urb_setup()
659 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
664 /* Figure out where each of the incoming setup attributes lands. */
665 if (intel
->gen
>= 6) {
666 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
667 if (fp
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
668 urb_setup
[i
] = urb_next
++;
672 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
673 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
674 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
675 int fp_index
= vert_result_to_frag_attrib(i
);
678 urb_setup
[fp_index
] = urb_next
++;
683 /* Each attribute is 4 setup channels, each of which is half a reg. */
684 c
->prog_data
.urb_read_length
= urb_next
* 2;
688 fs_visitor::assign_urb_setup()
690 int urb_start
= c
->nr_payload_regs
+ c
->prog_data
.curb_read_length
;
692 /* Offset all the urb_setup[] index by the actual position of the
693 * setup regs, now that the location of the constants has been chosen.
695 foreach_list(node
, &this->instructions
) {
696 fs_inst
*inst
= (fs_inst
*)node
;
698 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
699 assert(inst
->src
[2].file
== FIXED_HW_REG
);
700 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
703 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
704 assert(inst
->src
[0].file
== FIXED_HW_REG
);
705 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
709 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
713 * Split large virtual GRFs into separate components if we can.
715 * This is mostly duplicated with what brw_fs_vector_splitting does,
716 * but that's really conservative because it's afraid of doing
717 * splitting that doesn't result in real progress after the rest of
718 * the optimization phases, which would cause infinite looping in
719 * optimization. We can do it once here, safely. This also has the
720 * opportunity to split interpolated values, or maybe even uniforms,
721 * which we don't have at the IR level.
723 * We want to split, because virtual GRFs are what we register
724 * allocate and spill (due to contiguousness requirements for some
725 * instructions), and they're what we naturally generate in the
726 * codegen process, but most virtual GRFs don't actually need to be
727 * contiguous sets of GRFs. If we split, we'll end up with reduced
728 * live intervals and better dead code elimination and coalescing.
731 fs_visitor::split_virtual_grfs()
733 int num_vars
= this->virtual_grf_next
;
734 bool split_grf
[num_vars
];
735 int new_virtual_grf
[num_vars
];
737 /* Try to split anything > 0 sized. */
738 for (int i
= 0; i
< num_vars
; i
++) {
739 if (this->virtual_grf_sizes
[i
] != 1)
742 split_grf
[i
] = false;
746 /* PLN opcodes rely on the delta_xy being contiguous. */
747 split_grf
[this->delta_x
.reg
] = false;
750 foreach_list(node
, &this->instructions
) {
751 fs_inst
*inst
= (fs_inst
*)node
;
753 /* Texturing produces 4 contiguous registers, so no splitting. */
754 if (inst
->is_tex()) {
755 split_grf
[inst
->dst
.reg
] = false;
759 /* Allocate new space for split regs. Note that the virtual
760 * numbers will be contiguous.
762 for (int i
= 0; i
< num_vars
; i
++) {
764 new_virtual_grf
[i
] = virtual_grf_alloc(1);
765 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
766 int reg
= virtual_grf_alloc(1);
767 assert(reg
== new_virtual_grf
[i
] + j
- 1);
770 this->virtual_grf_sizes
[i
] = 1;
774 foreach_list(node
, &this->instructions
) {
775 fs_inst
*inst
= (fs_inst
*)node
;
777 if (inst
->dst
.file
== GRF
&&
778 split_grf
[inst
->dst
.reg
] &&
779 inst
->dst
.reg_offset
!= 0) {
780 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
781 inst
->dst
.reg_offset
- 1);
782 inst
->dst
.reg_offset
= 0;
784 for (int i
= 0; i
< 3; i
++) {
785 if (inst
->src
[i
].file
== GRF
&&
786 split_grf
[inst
->src
[i
].reg
] &&
787 inst
->src
[i
].reg_offset
!= 0) {
788 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
789 inst
->src
[i
].reg_offset
- 1);
790 inst
->src
[i
].reg_offset
= 0;
794 this->live_intervals_valid
= false;
798 fs_visitor::remove_dead_constants()
800 if (c
->dispatch_width
== 8) {
801 this->params_remap
= ralloc_array(mem_ctx
, int, c
->prog_data
.nr_params
);
803 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++)
804 this->params_remap
[i
] = -1;
806 /* Find which params are still in use. */
807 foreach_list(node
, &this->instructions
) {
808 fs_inst
*inst
= (fs_inst
*)node
;
810 for (int i
= 0; i
< 3; i
++) {
811 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
813 if (inst
->src
[i
].file
!= UNIFORM
)
816 assert(constant_nr
< (int)c
->prog_data
.nr_params
);
818 /* For now, set this to non-negative. We'll give it the
819 * actual new number in a moment, in order to keep the
820 * register numbers nicely ordered.
822 this->params_remap
[constant_nr
] = 0;
826 /* Figure out what the new numbers for the params will be. At some
827 * point when we're doing uniform array access, we're going to want
828 * to keep the distinction between .reg and .reg_offset, but for
831 unsigned int new_nr_params
= 0;
832 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
833 if (this->params_remap
[i
] != -1) {
834 this->params_remap
[i
] = new_nr_params
++;
838 /* Update the list of params to be uploaded to match our new numbering. */
839 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
840 int remapped
= this->params_remap
[i
];
845 /* We've already done setup_paramvalues_refs() so no need to worry
846 * about param_index and param_offset.
848 c
->prog_data
.param
[remapped
] = c
->prog_data
.param
[i
];
849 c
->prog_data
.param_convert
[remapped
] = c
->prog_data
.param_convert
[i
];
852 c
->prog_data
.nr_params
= new_nr_params
;
854 /* This should have been generated in the 8-wide pass already. */
855 assert(this->params_remap
);
858 /* Now do the renumbering of the shader to remove unused params. */
859 foreach_list(node
, &this->instructions
) {
860 fs_inst
*inst
= (fs_inst
*)node
;
862 for (int i
= 0; i
< 3; i
++) {
863 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
865 if (inst
->src
[i
].file
!= UNIFORM
)
868 assert(this->params_remap
[constant_nr
] != -1);
869 inst
->src
[i
].reg
= this->params_remap
[constant_nr
];
870 inst
->src
[i
].reg_offset
= 0;
878 * Choose accesses from the UNIFORM file to demote to using the pull
881 * We allow a fragment shader to have more than the specified minimum
882 * maximum number of fragment shader uniform components (64). If
883 * there are too many of these, they'd fill up all of register space.
884 * So, this will push some of them out to the pull constant buffer and
885 * update the program to load them.
888 fs_visitor::setup_pull_constants()
890 /* Only allow 16 registers (128 uniform components) as push constants. */
891 unsigned int max_uniform_components
= 16 * 8;
892 if (c
->prog_data
.nr_params
<= max_uniform_components
)
895 if (c
->dispatch_width
== 16) {
896 fail("Pull constants not supported in 16-wide\n");
900 /* Just demote the end of the list. We could probably do better
901 * here, demoting things that are rarely used in the program first.
903 int pull_uniform_base
= max_uniform_components
;
904 int pull_uniform_count
= c
->prog_data
.nr_params
- pull_uniform_base
;
906 foreach_list(node
, &this->instructions
) {
907 fs_inst
*inst
= (fs_inst
*)node
;
909 for (int i
= 0; i
< 3; i
++) {
910 if (inst
->src
[i
].file
!= UNIFORM
)
913 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
914 if (uniform_nr
< pull_uniform_base
)
917 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
918 fs_inst
*pull
= new(mem_ctx
) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
920 pull
->offset
= ((uniform_nr
- pull_uniform_base
) * 4) & ~15;
922 pull
->annotation
= inst
->annotation
;
926 inst
->insert_before(pull
);
928 inst
->src
[i
].file
= GRF
;
929 inst
->src
[i
].reg
= dst
.reg
;
930 inst
->src
[i
].reg_offset
= 0;
931 inst
->src
[i
].smear
= (uniform_nr
- pull_uniform_base
) & 3;
935 for (int i
= 0; i
< pull_uniform_count
; i
++) {
936 c
->prog_data
.pull_param
[i
] = c
->prog_data
.param
[pull_uniform_base
+ i
];
937 c
->prog_data
.pull_param_convert
[i
] =
938 c
->prog_data
.param_convert
[pull_uniform_base
+ i
];
940 c
->prog_data
.nr_params
-= pull_uniform_count
;
941 c
->prog_data
.nr_pull_params
= pull_uniform_count
;
945 fs_visitor::calculate_live_intervals()
947 int num_vars
= this->virtual_grf_next
;
948 int *def
= ralloc_array(mem_ctx
, int, num_vars
);
949 int *use
= ralloc_array(mem_ctx
, int, num_vars
);
953 if (this->live_intervals_valid
)
956 for (int i
= 0; i
< num_vars
; i
++) {
957 def
[i
] = MAX_INSTRUCTION
;
962 foreach_list(node
, &this->instructions
) {
963 fs_inst
*inst
= (fs_inst
*)node
;
965 if (inst
->opcode
== BRW_OPCODE_DO
) {
966 if (loop_depth
++ == 0)
968 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
971 if (loop_depth
== 0) {
972 /* Patches up the use of vars marked for being live across
975 for (int i
= 0; i
< num_vars
; i
++) {
976 if (use
[i
] == loop_start
) {
982 for (unsigned int i
= 0; i
< 3; i
++) {
983 if (inst
->src
[i
].file
== GRF
) {
984 int reg
= inst
->src
[i
].reg
;
989 def
[reg
] = MIN2(loop_start
, def
[reg
]);
990 use
[reg
] = loop_start
;
992 /* Nobody else is going to go smash our start to
993 * later in the loop now, because def[reg] now
994 * points before the bb header.
999 if (inst
->dst
.file
== GRF
) {
1000 int reg
= inst
->dst
.reg
;
1003 def
[reg
] = MIN2(def
[reg
], ip
);
1005 def
[reg
] = MIN2(def
[reg
], loop_start
);
1013 ralloc_free(this->virtual_grf_def
);
1014 ralloc_free(this->virtual_grf_use
);
1015 this->virtual_grf_def
= def
;
1016 this->virtual_grf_use
= use
;
1018 this->live_intervals_valid
= true;
1022 * Attempts to move immediate constants into the immediate
1023 * constant slot of following instructions.
1025 * Immediate constants are a bit tricky -- they have to be in the last
1026 * operand slot, you can't do abs/negate on them,
1030 fs_visitor::propagate_constants()
1032 bool progress
= false;
1034 calculate_live_intervals();
1036 foreach_list(node
, &this->instructions
) {
1037 fs_inst
*inst
= (fs_inst
*)node
;
1039 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1041 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
1042 inst
->dst
.type
!= inst
->src
[0].type
||
1043 (c
->dispatch_width
== 16 &&
1044 (inst
->force_uncompressed
|| inst
->force_sechalf
)))
1047 /* Don't bother with cases where we should have had the
1048 * operation on the constant folded in GLSL already.
1053 /* Found a move of a constant to a GRF. Find anything else using the GRF
1054 * before it's written, and replace it with the constant if we can.
1056 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->next
;
1057 !scan_inst
->is_tail_sentinel();
1058 scan_inst
= (fs_inst
*)scan_inst
->next
) {
1059 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
1060 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
1061 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
1062 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
1066 for (int i
= 2; i
>= 0; i
--) {
1067 if (scan_inst
->src
[i
].file
!= GRF
||
1068 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
1069 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
1072 /* Don't bother with cases where we should have had the
1073 * operation on the constant folded in GLSL already.
1075 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
1078 switch (scan_inst
->opcode
) {
1079 case BRW_OPCODE_MOV
:
1080 scan_inst
->src
[i
] = inst
->src
[0];
1084 case BRW_OPCODE_MUL
:
1085 case BRW_OPCODE_ADD
:
1087 scan_inst
->src
[i
] = inst
->src
[0];
1089 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
1090 /* Fit this constant in by commuting the operands */
1091 scan_inst
->src
[0] = scan_inst
->src
[1];
1092 scan_inst
->src
[1] = inst
->src
[0];
1097 case BRW_OPCODE_CMP
:
1099 scan_inst
->src
[i
] = inst
->src
[0];
1101 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
1104 new_cmod
= brw_swap_cmod(scan_inst
->conditional_mod
);
1105 if (new_cmod
!= ~0u) {
1106 /* Fit this constant in by swapping the operands and
1109 scan_inst
->src
[0] = scan_inst
->src
[1];
1110 scan_inst
->src
[1] = inst
->src
[0];
1111 scan_inst
->conditional_mod
= new_cmod
;
1117 case BRW_OPCODE_SEL
:
1119 scan_inst
->src
[i
] = inst
->src
[0];
1121 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
1122 scan_inst
->src
[0] = scan_inst
->src
[1];
1123 scan_inst
->src
[1] = inst
->src
[0];
1125 /* If this was predicated, flipping operands means
1126 * we also need to flip the predicate.
1128 if (scan_inst
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
1129 scan_inst
->predicate_inverse
=
1130 !scan_inst
->predicate_inverse
;
1136 case SHADER_OPCODE_RCP
:
1137 /* The hardware doesn't do math on immediate values
1138 * (because why are you doing that, seriously?), but
1139 * the correct answer is to just constant fold it
1143 if (inst
->src
[0].imm
.f
!= 0.0f
) {
1144 scan_inst
->opcode
= BRW_OPCODE_MOV
;
1145 scan_inst
->src
[0] = inst
->src
[0];
1146 scan_inst
->src
[0].imm
.f
= 1.0f
/ scan_inst
->src
[0].imm
.f
;
1156 if (scan_inst
->dst
.file
== GRF
&&
1157 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
1158 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
1159 scan_inst
->is_tex())) {
1166 this->live_intervals_valid
= false;
1173 * Attempts to move immediate constants into the immediate
1174 * constant slot of following instructions.
1176 * Immediate constants are a bit tricky -- they have to be in the last
1177 * operand slot, you can't do abs/negate on them,
1181 fs_visitor::opt_algebraic()
1183 bool progress
= false;
1185 calculate_live_intervals();
1187 foreach_list(node
, &this->instructions
) {
1188 fs_inst
*inst
= (fs_inst
*)node
;
1190 switch (inst
->opcode
) {
1191 case BRW_OPCODE_MUL
:
1192 if (inst
->src
[1].file
!= IMM
)
1196 if (inst
->src
[1].type
== BRW_REGISTER_TYPE_F
&&
1197 inst
->src
[1].imm
.f
== 1.0) {
1198 inst
->opcode
= BRW_OPCODE_MOV
;
1199 inst
->src
[1] = reg_undef
;
1214 * Must be called after calculate_live_intervales() to remove unused
1215 * writes to registers -- register allocation will fail otherwise
1216 * because something deffed but not used won't be considered to
1217 * interfere with other regs.
1220 fs_visitor::dead_code_eliminate()
1222 bool progress
= false;
1225 calculate_live_intervals();
1227 foreach_list_safe(node
, &this->instructions
) {
1228 fs_inst
*inst
= (fs_inst
*)node
;
1230 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
1239 live_intervals_valid
= false;
1245 fs_visitor::register_coalesce()
1247 bool progress
= false;
1251 foreach_list_safe(node
, &this->instructions
) {
1252 fs_inst
*inst
= (fs_inst
*)node
;
1254 /* Make sure that we dominate the instructions we're going to
1255 * scan for interfering with our coalescing, or we won't have
1256 * scanned enough to see if anything interferes with our
1257 * coalescing. We don't dominate the following instructions if
1258 * we're in a loop or an if block.
1260 switch (inst
->opcode
) {
1264 case BRW_OPCODE_WHILE
:
1270 case BRW_OPCODE_ENDIF
:
1276 if (loop_depth
|| if_depth
)
1279 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1282 inst
->dst
.file
!= GRF
|| (inst
->src
[0].file
!= GRF
&&
1283 inst
->src
[0].file
!= UNIFORM
)||
1284 inst
->dst
.type
!= inst
->src
[0].type
)
1287 bool has_source_modifiers
= inst
->src
[0].abs
|| inst
->src
[0].negate
;
1289 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
1290 * them: check for no writes to either one until the exit of the
1293 bool interfered
= false;
1295 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->next
;
1296 !scan_inst
->is_tail_sentinel();
1297 scan_inst
= (fs_inst
*)scan_inst
->next
) {
1298 if (scan_inst
->dst
.file
== GRF
) {
1299 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
1300 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
1301 scan_inst
->is_tex())) {
1305 if (inst
->src
[0].file
== GRF
&&
1306 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1307 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
1308 scan_inst
->is_tex())) {
1314 /* The gen6 MATH instruction can't handle source modifiers or
1315 * unusual register regions, so avoid coalescing those for
1316 * now. We should do something more specific.
1318 if (intel
->gen
>= 6 &&
1319 scan_inst
->is_math() &&
1320 (has_source_modifiers
|| inst
->src
[0].file
== UNIFORM
)) {
1329 /* Rewrite the later usage to point at the source of the move to
1332 for (fs_inst
*scan_inst
= inst
;
1333 !scan_inst
->is_tail_sentinel();
1334 scan_inst
= (fs_inst
*)scan_inst
->next
) {
1335 for (int i
= 0; i
< 3; i
++) {
1336 if (scan_inst
->src
[i
].file
== GRF
&&
1337 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
1338 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
1339 fs_reg new_src
= inst
->src
[0];
1340 new_src
.negate
^= scan_inst
->src
[i
].negate
;
1341 new_src
.abs
|= scan_inst
->src
[i
].abs
;
1342 scan_inst
->src
[i
] = new_src
;
1352 live_intervals_valid
= false;
1359 fs_visitor::compute_to_mrf()
1361 bool progress
= false;
1364 calculate_live_intervals();
1366 foreach_list_safe(node
, &this->instructions
) {
1367 fs_inst
*inst
= (fs_inst
*)node
;
1372 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1374 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
1375 inst
->dst
.type
!= inst
->src
[0].type
||
1376 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
1379 /* Work out which hardware MRF registers are written by this
1382 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
1384 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
1385 mrf_high
= mrf_low
+ 4;
1386 } else if (c
->dispatch_width
== 16 &&
1387 (!inst
->force_uncompressed
&& !inst
->force_sechalf
)) {
1388 mrf_high
= mrf_low
+ 1;
1393 /* Can't compute-to-MRF this GRF if someone else was going to
1396 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
1399 /* Found a move of a GRF to a MRF. Let's see if we can go
1400 * rewrite the thing that made this GRF to write into the MRF.
1403 for (scan_inst
= (fs_inst
*)inst
->prev
;
1404 scan_inst
->prev
!= NULL
;
1405 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
1406 if (scan_inst
->dst
.file
== GRF
&&
1407 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
1408 /* Found the last thing to write our reg we want to turn
1409 * into a compute-to-MRF.
1412 if (scan_inst
->is_tex()) {
1413 /* texturing writes several continuous regs, so we can't
1414 * compute-to-mrf that.
1419 /* If it's predicated, it (probably) didn't populate all
1420 * the channels. We might be able to rewrite everything
1421 * that writes that reg, but it would require smarter
1422 * tracking to delay the rewriting until complete success.
1424 if (scan_inst
->predicated
)
1427 /* If it's half of register setup and not the same half as
1428 * our MOV we're trying to remove, bail for now.
1430 if (scan_inst
->force_uncompressed
!= inst
->force_uncompressed
||
1431 scan_inst
->force_sechalf
!= inst
->force_sechalf
) {
1435 /* SEND instructions can't have MRF as a destination. */
1436 if (scan_inst
->mlen
)
1439 if (intel
->gen
>= 6) {
1440 /* gen6 math instructions must have the destination be
1441 * GRF, so no compute-to-MRF for them.
1443 if (scan_inst
->is_math()) {
1448 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1449 /* Found the creator of our MRF's source value. */
1450 scan_inst
->dst
.file
= MRF
;
1451 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1452 scan_inst
->saturate
|= inst
->saturate
;
1459 /* We don't handle flow control here. Most computation of
1460 * values that end up in MRFs are shortly before the MRF
1463 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
1464 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
1465 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
1466 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
1470 /* You can't read from an MRF, so if someone else reads our
1471 * MRF's source GRF that we wanted to rewrite, that stops us.
1473 bool interfered
= false;
1474 for (int i
= 0; i
< 3; i
++) {
1475 if (scan_inst
->src
[i
].file
== GRF
&&
1476 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
1477 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1484 if (scan_inst
->dst
.file
== MRF
) {
1485 /* If somebody else writes our MRF here, we can't
1486 * compute-to-MRF before that.
1488 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
1491 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
1492 scan_mrf_high
= scan_mrf_low
+ 4;
1493 } else if (c
->dispatch_width
== 16 &&
1494 (!scan_inst
->force_uncompressed
&&
1495 !scan_inst
->force_sechalf
)) {
1496 scan_mrf_high
= scan_mrf_low
+ 1;
1498 scan_mrf_high
= scan_mrf_low
;
1501 if (mrf_low
== scan_mrf_low
||
1502 mrf_low
== scan_mrf_high
||
1503 mrf_high
== scan_mrf_low
||
1504 mrf_high
== scan_mrf_high
) {
1509 if (scan_inst
->mlen
> 0) {
1510 /* Found a SEND instruction, which means that there are
1511 * live values in MRFs from base_mrf to base_mrf +
1512 * scan_inst->mlen - 1. Don't go pushing our MRF write up
1515 if (mrf_low
>= scan_inst
->base_mrf
&&
1516 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1519 if (mrf_high
>= scan_inst
->base_mrf
&&
1520 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1531 * Walks through basic blocks, locking for repeated MRF writes and
1532 * removing the later ones.
1535 fs_visitor::remove_duplicate_mrf_writes()
1537 fs_inst
*last_mrf_move
[16];
1538 bool progress
= false;
1540 /* Need to update the MRF tracking for compressed instructions. */
1541 if (c
->dispatch_width
== 16)
1544 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
1546 foreach_list_safe(node
, &this->instructions
) {
1547 fs_inst
*inst
= (fs_inst
*)node
;
1549 switch (inst
->opcode
) {
1551 case BRW_OPCODE_WHILE
:
1553 case BRW_OPCODE_ELSE
:
1554 case BRW_OPCODE_ENDIF
:
1555 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
1561 if (inst
->opcode
== BRW_OPCODE_MOV
&&
1562 inst
->dst
.file
== MRF
) {
1563 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
1564 if (prev_inst
&& inst
->equals(prev_inst
)) {
1571 /* Clear out the last-write records for MRFs that were overwritten. */
1572 if (inst
->dst
.file
== MRF
) {
1573 last_mrf_move
[inst
->dst
.reg
] = NULL
;
1576 if (inst
->mlen
> 0) {
1577 /* Found a SEND instruction, which will include two or fewer
1578 * implied MRF writes. We could do better here.
1580 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
1581 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
1585 /* Clear out any MRF move records whose sources got overwritten. */
1586 if (inst
->dst
.file
== GRF
) {
1587 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
1588 if (last_mrf_move
[i
] &&
1589 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
1590 last_mrf_move
[i
] = NULL
;
1595 if (inst
->opcode
== BRW_OPCODE_MOV
&&
1596 inst
->dst
.file
== MRF
&&
1597 inst
->src
[0].file
== GRF
&&
1598 !inst
->predicated
) {
1599 last_mrf_move
[inst
->dst
.reg
] = inst
;
1607 fs_visitor::virtual_grf_interferes(int a
, int b
)
1609 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
1610 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
1612 /* We can't handle dead register writes here, without iterating
1613 * over the whole instruction stream to find every single dead
1614 * write to that register to compare to the live interval of the
1615 * other register. Just assert that dead_code_eliminate() has been
1618 assert((this->virtual_grf_use
[a
] != -1 ||
1619 this->virtual_grf_def
[a
] == MAX_INSTRUCTION
) &&
1620 (this->virtual_grf_use
[b
] != -1 ||
1621 this->virtual_grf_def
[b
] == MAX_INSTRUCTION
));
1623 /* If the register is used to store 16 values of less than float
1624 * size (only the case for pixel_[xy]), then we can't allocate
1625 * another dword-sized thing to that register that would be used in
1626 * the same instruction. This is because when the GPU decodes (for
1629 * (declare (in ) vec4 gl_FragCoord@0x97766a0)
1630 * add(16) g6<1>F g6<8,8,1>UW 0.5F { align1 compr };
1632 * it's actually processed as:
1633 * add(8) g6<1>F g6<8,8,1>UW 0.5F { align1 };
1634 * add(8) g7<1>F g6.8<8,8,1>UW 0.5F { align1 sechalf };
1636 * so our second half values in g6 got overwritten in the first
1639 if (c
->dispatch_width
== 16 && (this->pixel_x
.reg
== a
||
1640 this->pixel_x
.reg
== b
||
1641 this->pixel_y
.reg
== a
||
1642 this->pixel_y
.reg
== b
)) {
1643 return start
<= end
;
1652 uint32_t prog_offset_16
= 0;
1653 uint32_t orig_nr_params
= c
->prog_data
.nr_params
;
1655 brw_wm_payload_setup(brw
, c
);
1657 if (c
->dispatch_width
== 16) {
1658 /* align to 64 byte boundary. */
1659 while ((c
->func
.nr_insn
* sizeof(struct brw_instruction
)) % 64) {
1663 /* Save off the start of this 16-wide program in case we succeed. */
1664 prog_offset_16
= c
->func
.nr_insn
* sizeof(struct brw_instruction
);
1666 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1672 calculate_urb_setup();
1674 emit_interpolation_setup_gen4();
1676 emit_interpolation_setup_gen6();
1678 /* Generate FS IR for main(). (the visitor only descends into
1679 * functions called "main").
1681 foreach_list(node
, &*shader
->ir
) {
1682 ir_instruction
*ir
= (ir_instruction
*)node
;
1684 this->result
= reg_undef
;
1692 split_virtual_grfs();
1694 setup_paramvalues_refs();
1695 setup_pull_constants();
1701 progress
= remove_duplicate_mrf_writes() || progress
;
1703 progress
= propagate_constants() || progress
;
1704 progress
= opt_algebraic() || progress
;
1705 progress
= register_coalesce() || progress
;
1706 progress
= compute_to_mrf() || progress
;
1707 progress
= dead_code_eliminate() || progress
;
1710 remove_dead_constants();
1712 schedule_instructions();
1714 assign_curb_setup();
1718 /* Debug of register spilling: Go spill everything. */
1719 int virtual_grf_count
= virtual_grf_next
;
1720 for (int i
= 0; i
< virtual_grf_count
; i
++) {
1726 assign_regs_trivial();
1728 while (!assign_regs()) {
1734 assert(force_uncompressed_stack
== 0);
1735 assert(force_sechalf_stack
== 0);
1742 if (c
->dispatch_width
== 8) {
1743 c
->prog_data
.reg_blocks
= brw_register_blocks(grf_used
);
1745 c
->prog_data
.reg_blocks_16
= brw_register_blocks(grf_used
);
1746 c
->prog_data
.prog_offset_16
= prog_offset_16
;
1748 /* Make sure we didn't try to sneak in an extra uniform */
1749 assert(orig_nr_params
== c
->prog_data
.nr_params
);
1756 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
,
1757 struct gl_shader_program
*prog
)
1759 struct intel_context
*intel
= &brw
->intel
;
1764 struct brw_shader
*shader
=
1765 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
1769 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1770 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
1771 _mesa_print_ir(shader
->ir
, NULL
);
1775 /* Now the main event: Visit the shader IR and generate our FS IR for it.
1777 c
->dispatch_width
= 8;
1779 fs_visitor
v(c
, prog
, shader
);
1781 prog
->LinkStatus
= GL_FALSE
;
1782 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1787 if (intel
->gen
>= 5 && c
->prog_data
.nr_pull_params
== 0) {
1788 c
->dispatch_width
= 16;
1789 fs_visitor
v2(c
, prog
, shader
);
1790 v2
.import_uniforms(&v
);
1794 c
->prog_data
.dispatch_width
= 8;
1800 brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
1802 struct brw_context
*brw
= brw_context(ctx
);
1803 struct brw_wm_prog_key key
;
1804 struct gl_fragment_program
*fp
= prog
->FragmentProgram
;
1805 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
1810 memset(&key
, 0, sizeof(key
));
1813 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
1815 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
1816 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
1818 /* Just assume depth testing. */
1819 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
1820 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
1822 key
.vp_outputs_written
|= BITFIELD64_BIT(FRAG_ATTRIB_WPOS
);
1823 for (int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
1824 if (!(fp
->Base
.InputsRead
& BITFIELD64_BIT(i
)))
1827 key
.proj_attrib_mask
|= 1 << i
;
1829 int vp_index
= vert_result_to_frag_attrib(i
);
1832 key
.vp_outputs_written
|= BITFIELD64_BIT(vp_index
);
1835 key
.clamp_fragment_color
= true;
1837 for (int i
= 0; i
< BRW_MAX_TEX_UNIT
; i
++) {
1838 if (fp
->Base
.ShadowSamplers
& (1 << i
))
1839 key
.compare_funcs
[i
] = GL_LESS
;
1841 /* FINISHME: depth compares might use (0,0,0,W) for example */
1842 key
.tex_swizzles
[i
] = SWIZZLE_XYZW
;
1845 if (fp
->Base
.InputsRead
& FRAG_BIT_WPOS
) {
1846 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
1847 key
.render_to_fbo
= ctx
->DrawBuffer
->Name
!= 0;
1850 key
.nr_color_regions
= 1;
1852 key
.program_string_id
= bfp
->id
;
1854 uint32_t old_prog_offset
= brw
->wm
.prog_offset
;
1855 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
1857 bool success
= do_wm_prog(brw
, prog
, bfp
, &key
);
1859 brw
->wm
.prog_offset
= old_prog_offset
;
1860 brw
->wm
.prog_data
= old_prog_data
;