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i965: Add real support for pre-gen5 texture sampling to the new FS.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 extern "C" {
29
30 #include <sys/types.h>
31
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
42 #include "brw_eu.h"
43 #include "brw_wm.h"
44 #include "talloc.h"
45 }
46 #include "../glsl/glsl_types.h"
47 #include "../glsl/ir_optimization.h"
48 #include "../glsl/ir_print_visitor.h"
49
50 enum register_file {
51 ARF = BRW_ARCHITECTURE_REGISTER_FILE,
52 GRF = BRW_GENERAL_REGISTER_FILE,
53 MRF = BRW_MESSAGE_REGISTER_FILE,
54 IMM = BRW_IMMEDIATE_VALUE,
55 FIXED_HW_REG, /* a struct brw_reg */
56 UNIFORM, /* prog_data->params[hw_reg] */
57 BAD_FILE
58 };
59
60 enum fs_opcodes {
61 FS_OPCODE_FB_WRITE = 256,
62 FS_OPCODE_RCP,
63 FS_OPCODE_RSQ,
64 FS_OPCODE_SQRT,
65 FS_OPCODE_EXP2,
66 FS_OPCODE_LOG2,
67 FS_OPCODE_POW,
68 FS_OPCODE_SIN,
69 FS_OPCODE_COS,
70 FS_OPCODE_DDX,
71 FS_OPCODE_DDY,
72 FS_OPCODE_LINTERP,
73 FS_OPCODE_TEX,
74 FS_OPCODE_TXB,
75 FS_OPCODE_TXL,
76 FS_OPCODE_DISCARD,
77 };
78
79 static int using_new_fs = -1;
80 static struct brw_reg brw_reg_from_fs_reg(class fs_reg *reg);
81
82 struct gl_shader *
83 brw_new_shader(GLcontext *ctx, GLuint name, GLuint type)
84 {
85 struct brw_shader *shader;
86
87 shader = talloc_zero(NULL, struct brw_shader);
88 if (shader) {
89 shader->base.Type = type;
90 shader->base.Name = name;
91 _mesa_init_shader(ctx, &shader->base);
92 }
93
94 return &shader->base;
95 }
96
97 struct gl_shader_program *
98 brw_new_shader_program(GLcontext *ctx, GLuint name)
99 {
100 struct brw_shader_program *prog;
101 prog = talloc_zero(NULL, struct brw_shader_program);
102 if (prog) {
103 prog->base.Name = name;
104 _mesa_init_shader_program(ctx, &prog->base);
105 }
106 return &prog->base;
107 }
108
109 GLboolean
110 brw_compile_shader(GLcontext *ctx, struct gl_shader *shader)
111 {
112 if (!_mesa_ir_compile_shader(ctx, shader))
113 return GL_FALSE;
114
115 return GL_TRUE;
116 }
117
118 GLboolean
119 brw_link_shader(GLcontext *ctx, struct gl_shader_program *prog)
120 {
121 if (using_new_fs == -1)
122 using_new_fs = getenv("INTEL_NEW_FS") != NULL;
123
124 for (unsigned i = 0; i < prog->_NumLinkedShaders; i++) {
125 struct brw_shader *shader = (struct brw_shader *)prog->_LinkedShaders[i];
126
127 if (using_new_fs && shader->base.Type == GL_FRAGMENT_SHADER) {
128 void *mem_ctx = talloc_new(NULL);
129 bool progress;
130
131 if (shader->ir)
132 talloc_free(shader->ir);
133 shader->ir = new(shader) exec_list;
134 clone_ir_list(mem_ctx, shader->ir, shader->base.ir);
135
136 do_mat_op_to_vec(shader->ir);
137 do_mod_to_fract(shader->ir);
138 do_div_to_mul_rcp(shader->ir);
139 do_sub_to_add_neg(shader->ir);
140 do_explog_to_explog2(shader->ir);
141 do_lower_texture_projection(shader->ir);
142
143 do {
144 progress = false;
145
146 brw_do_channel_expressions(shader->ir);
147 brw_do_vector_splitting(shader->ir);
148
149 progress = do_lower_jumps(shader->ir, true, true,
150 true, /* main return */
151 false, /* continue */
152 false /* loops */
153 ) || progress;
154
155 progress = do_common_optimization(shader->ir, true, 32) || progress;
156
157 progress = lower_noise(shader->ir) || progress;
158 progress =
159 lower_variable_index_to_cond_assign(shader->ir,
160 GL_TRUE, /* input */
161 GL_TRUE, /* output */
162 GL_TRUE, /* temp */
163 GL_TRUE /* uniform */
164 ) || progress;
165 } while (progress);
166
167 validate_ir_tree(shader->ir);
168
169 reparent_ir(shader->ir, shader->ir);
170 talloc_free(mem_ctx);
171 }
172 }
173
174 if (!_mesa_ir_link_shader(ctx, prog))
175 return GL_FALSE;
176
177 return GL_TRUE;
178 }
179
180 static int
181 type_size(const struct glsl_type *type)
182 {
183 unsigned int size, i;
184
185 switch (type->base_type) {
186 case GLSL_TYPE_UINT:
187 case GLSL_TYPE_INT:
188 case GLSL_TYPE_FLOAT:
189 case GLSL_TYPE_BOOL:
190 return type->components();
191 case GLSL_TYPE_ARRAY:
192 return type_size(type->fields.array) * type->length;
193 case GLSL_TYPE_STRUCT:
194 size = 0;
195 for (i = 0; i < type->length; i++) {
196 size += type_size(type->fields.structure[i].type);
197 }
198 return size;
199 case GLSL_TYPE_SAMPLER:
200 /* Samplers take up no register space, since they're baked in at
201 * link time.
202 */
203 return 0;
204 default:
205 assert(!"not reached");
206 return 0;
207 }
208 }
209
210 class fs_reg {
211 public:
212 /* Callers of this talloc-based new need not call delete. It's
213 * easier to just talloc_free 'ctx' (or any of its ancestors). */
214 static void* operator new(size_t size, void *ctx)
215 {
216 void *node;
217
218 node = talloc_size(ctx, size);
219 assert(node != NULL);
220
221 return node;
222 }
223
224 void init()
225 {
226 this->reg = 0;
227 this->reg_offset = 0;
228 this->negate = 0;
229 this->abs = 0;
230 this->hw_reg = -1;
231 }
232
233 /** Generic unset register constructor. */
234 fs_reg()
235 {
236 init();
237 this->file = BAD_FILE;
238 }
239
240 /** Immediate value constructor. */
241 fs_reg(float f)
242 {
243 init();
244 this->file = IMM;
245 this->type = BRW_REGISTER_TYPE_F;
246 this->imm.f = f;
247 }
248
249 /** Immediate value constructor. */
250 fs_reg(int32_t i)
251 {
252 init();
253 this->file = IMM;
254 this->type = BRW_REGISTER_TYPE_D;
255 this->imm.i = i;
256 }
257
258 /** Immediate value constructor. */
259 fs_reg(uint32_t u)
260 {
261 init();
262 this->file = IMM;
263 this->type = BRW_REGISTER_TYPE_UD;
264 this->imm.u = u;
265 }
266
267 /** Fixed brw_reg Immediate value constructor. */
268 fs_reg(struct brw_reg fixed_hw_reg)
269 {
270 init();
271 this->file = FIXED_HW_REG;
272 this->fixed_hw_reg = fixed_hw_reg;
273 this->type = fixed_hw_reg.type;
274 }
275
276 fs_reg(enum register_file file, int hw_reg);
277 fs_reg(class fs_visitor *v, const struct glsl_type *type);
278
279 /** Register file: ARF, GRF, MRF, IMM. */
280 enum register_file file;
281 /** virtual register number. 0 = fixed hw reg */
282 int reg;
283 /** Offset within the virtual register. */
284 int reg_offset;
285 /** HW register number. Generally unset until register allocation. */
286 int hw_reg;
287 /** Register type. BRW_REGISTER_TYPE_* */
288 int type;
289 bool negate;
290 bool abs;
291 struct brw_reg fixed_hw_reg;
292
293 /** Value for file == BRW_IMMMEDIATE_FILE */
294 union {
295 int32_t i;
296 uint32_t u;
297 float f;
298 } imm;
299 };
300
301 static const fs_reg reg_undef;
302 static const fs_reg reg_null(ARF, BRW_ARF_NULL);
303
304 class fs_inst : public exec_node {
305 public:
306 /* Callers of this talloc-based new need not call delete. It's
307 * easier to just talloc_free 'ctx' (or any of its ancestors). */
308 static void* operator new(size_t size, void *ctx)
309 {
310 void *node;
311
312 node = talloc_zero_size(ctx, size);
313 assert(node != NULL);
314
315 return node;
316 }
317
318 void init()
319 {
320 this->opcode = BRW_OPCODE_NOP;
321 this->saturate = false;
322 this->conditional_mod = BRW_CONDITIONAL_NONE;
323 this->predicated = false;
324 this->sampler = 0;
325 this->target = 0;
326 this->eot = false;
327 this->shadow_compare = false;
328 }
329
330 fs_inst()
331 {
332 init();
333 }
334
335 fs_inst(int opcode)
336 {
337 init();
338 this->opcode = opcode;
339 }
340
341 fs_inst(int opcode, fs_reg dst, fs_reg src0)
342 {
343 init();
344 this->opcode = opcode;
345 this->dst = dst;
346 this->src[0] = src0;
347 }
348
349 fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1)
350 {
351 init();
352 this->opcode = opcode;
353 this->dst = dst;
354 this->src[0] = src0;
355 this->src[1] = src1;
356 }
357
358 fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2)
359 {
360 init();
361 this->opcode = opcode;
362 this->dst = dst;
363 this->src[0] = src0;
364 this->src[1] = src1;
365 this->src[2] = src2;
366 }
367
368 int opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
369 fs_reg dst;
370 fs_reg src[3];
371 bool saturate;
372 bool predicated;
373 int conditional_mod; /**< BRW_CONDITIONAL_* */
374
375 int mlen; /**< SEND message length */
376 int sampler;
377 int target; /**< MRT target. */
378 bool eot;
379 bool shadow_compare;
380
381 /** @{
382 * Annotation for the generated IR. One of the two can be set.
383 */
384 ir_instruction *ir;
385 const char *annotation;
386 /** @} */
387 };
388
389 class fs_visitor : public ir_visitor
390 {
391 public:
392
393 fs_visitor(struct brw_wm_compile *c, struct brw_shader *shader)
394 {
395 this->c = c;
396 this->p = &c->func;
397 this->brw = p->brw;
398 this->fp = brw->fragment_program;
399 this->intel = &brw->intel;
400 this->ctx = &intel->ctx;
401 this->mem_ctx = talloc_new(NULL);
402 this->shader = shader;
403 this->fail = false;
404 this->variable_ht = hash_table_ctor(0,
405 hash_table_pointer_hash,
406 hash_table_pointer_compare);
407
408 this->frag_color = NULL;
409 this->frag_data = NULL;
410 this->frag_depth = NULL;
411 this->first_non_payload_grf = 0;
412
413 this->current_annotation = NULL;
414 this->annotation_string = NULL;
415 this->annotation_ir = NULL;
416 this->base_ir = NULL;
417
418 this->virtual_grf_sizes = NULL;
419 this->virtual_grf_next = 1;
420 this->virtual_grf_array_size = 0;
421 this->virtual_grf_def = NULL;
422 this->virtual_grf_use = NULL;
423 }
424 ~fs_visitor()
425 {
426 talloc_free(this->mem_ctx);
427 hash_table_dtor(this->variable_ht);
428 }
429
430 fs_reg *variable_storage(ir_variable *var);
431 int virtual_grf_alloc(int size);
432
433 void visit(ir_variable *ir);
434 void visit(ir_assignment *ir);
435 void visit(ir_dereference_variable *ir);
436 void visit(ir_dereference_record *ir);
437 void visit(ir_dereference_array *ir);
438 void visit(ir_expression *ir);
439 void visit(ir_texture *ir);
440 void visit(ir_if *ir);
441 void visit(ir_constant *ir);
442 void visit(ir_swizzle *ir);
443 void visit(ir_return *ir);
444 void visit(ir_loop *ir);
445 void visit(ir_loop_jump *ir);
446 void visit(ir_discard *ir);
447 void visit(ir_call *ir);
448 void visit(ir_function *ir);
449 void visit(ir_function_signature *ir);
450
451 fs_inst *emit(fs_inst inst);
452 void assign_curb_setup();
453 void calculate_urb_setup();
454 void assign_urb_setup();
455 void assign_regs();
456 void assign_regs_trivial();
457 void calculate_live_intervals();
458 bool virtual_grf_interferes(int a, int b);
459 void generate_code();
460 void generate_fb_write(fs_inst *inst);
461 void generate_linterp(fs_inst *inst, struct brw_reg dst,
462 struct brw_reg *src);
463 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
464 void generate_math(fs_inst *inst, struct brw_reg dst, struct brw_reg *src);
465 void generate_discard(fs_inst *inst, struct brw_reg temp);
466 void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
467 void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
468
469 void emit_dummy_fs();
470 void emit_fragcoord_interpolation(ir_variable *ir);
471 void emit_general_interpolation(ir_variable *ir);
472 void emit_interpolation_setup_gen4();
473 void emit_interpolation_setup_gen6();
474 fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate);
475 fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate);
476 void emit_fb_writes();
477 void emit_assignment_writes(fs_reg &l, fs_reg &r,
478 const glsl_type *type, bool predicated);
479
480 struct brw_reg interp_reg(int location, int channel);
481 int setup_uniform_values(int loc, const glsl_type *type);
482 void setup_builtin_uniform_values(ir_variable *ir);
483
484 struct brw_context *brw;
485 const struct gl_fragment_program *fp;
486 struct intel_context *intel;
487 GLcontext *ctx;
488 struct brw_wm_compile *c;
489 struct brw_compile *p;
490 struct brw_shader *shader;
491 void *mem_ctx;
492 exec_list instructions;
493
494 int *virtual_grf_sizes;
495 int virtual_grf_next;
496 int virtual_grf_array_size;
497 int *virtual_grf_def;
498 int *virtual_grf_use;
499
500 struct hash_table *variable_ht;
501 ir_variable *frag_color, *frag_data, *frag_depth;
502 int first_non_payload_grf;
503 int urb_setup[FRAG_ATTRIB_MAX];
504
505 /** @{ debug annotation info */
506 const char *current_annotation;
507 ir_instruction *base_ir;
508 const char **annotation_string;
509 ir_instruction **annotation_ir;
510 /** @} */
511
512 bool fail;
513
514 /* Result of last visit() method. */
515 fs_reg result;
516
517 fs_reg pixel_x;
518 fs_reg pixel_y;
519 fs_reg wpos_w;
520 fs_reg pixel_w;
521 fs_reg delta_x;
522 fs_reg delta_y;
523
524 int grf_used;
525
526 };
527
528 int
529 fs_visitor::virtual_grf_alloc(int size)
530 {
531 if (virtual_grf_array_size <= virtual_grf_next) {
532 if (virtual_grf_array_size == 0)
533 virtual_grf_array_size = 16;
534 else
535 virtual_grf_array_size *= 2;
536 virtual_grf_sizes = talloc_realloc(mem_ctx, virtual_grf_sizes,
537 int, virtual_grf_array_size);
538
539 /* This slot is always unused. */
540 virtual_grf_sizes[0] = 0;
541 }
542 virtual_grf_sizes[virtual_grf_next] = size;
543 return virtual_grf_next++;
544 }
545
546 /** Fixed HW reg constructor. */
547 fs_reg::fs_reg(enum register_file file, int hw_reg)
548 {
549 init();
550 this->file = file;
551 this->hw_reg = hw_reg;
552 this->type = BRW_REGISTER_TYPE_F;
553 }
554
555 int
556 brw_type_for_base_type(const struct glsl_type *type)
557 {
558 switch (type->base_type) {
559 case GLSL_TYPE_FLOAT:
560 return BRW_REGISTER_TYPE_F;
561 case GLSL_TYPE_INT:
562 case GLSL_TYPE_BOOL:
563 return BRW_REGISTER_TYPE_D;
564 case GLSL_TYPE_UINT:
565 return BRW_REGISTER_TYPE_UD;
566 case GLSL_TYPE_ARRAY:
567 case GLSL_TYPE_STRUCT:
568 /* These should be overridden with the type of the member when
569 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
570 * way to trip up if we don't.
571 */
572 return BRW_REGISTER_TYPE_UD;
573 default:
574 assert(!"not reached");
575 return BRW_REGISTER_TYPE_F;
576 }
577 }
578
579 /** Automatic reg constructor. */
580 fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type)
581 {
582 init();
583
584 this->file = GRF;
585 this->reg = v->virtual_grf_alloc(type_size(type));
586 this->reg_offset = 0;
587 this->type = brw_type_for_base_type(type);
588 }
589
590 fs_reg *
591 fs_visitor::variable_storage(ir_variable *var)
592 {
593 return (fs_reg *)hash_table_find(this->variable_ht, var);
594 }
595
596 /* Our support for uniforms is piggy-backed on the struct
597 * gl_fragment_program, because that's where the values actually
598 * get stored, rather than in some global gl_shader_program uniform
599 * store.
600 */
601 int
602 fs_visitor::setup_uniform_values(int loc, const glsl_type *type)
603 {
604 unsigned int offset = 0;
605 float *vec_values;
606
607 if (type->is_matrix()) {
608 const glsl_type *column = glsl_type::get_instance(GLSL_TYPE_FLOAT,
609 type->vector_elements,
610 1);
611
612 for (unsigned int i = 0; i < type->matrix_columns; i++) {
613 offset += setup_uniform_values(loc + offset, column);
614 }
615
616 return offset;
617 }
618
619 switch (type->base_type) {
620 case GLSL_TYPE_FLOAT:
621 case GLSL_TYPE_UINT:
622 case GLSL_TYPE_INT:
623 case GLSL_TYPE_BOOL:
624 vec_values = fp->Base.Parameters->ParameterValues[loc];
625 for (unsigned int i = 0; i < type->vector_elements; i++) {
626 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[i];
627 }
628 return 1;
629
630 case GLSL_TYPE_STRUCT:
631 for (unsigned int i = 0; i < type->length; i++) {
632 offset += setup_uniform_values(loc + offset,
633 type->fields.structure[i].type);
634 }
635 return offset;
636
637 case GLSL_TYPE_ARRAY:
638 for (unsigned int i = 0; i < type->length; i++) {
639 offset += setup_uniform_values(loc + offset, type->fields.array);
640 }
641 return offset;
642
643 case GLSL_TYPE_SAMPLER:
644 /* The sampler takes up a slot, but we don't use any values from it. */
645 return 1;
646
647 default:
648 assert(!"not reached");
649 return 0;
650 }
651 }
652
653
654 /* Our support for builtin uniforms is even scarier than non-builtin.
655 * It sits on top of the PROG_STATE_VAR parameters that are
656 * automatically updated from GL context state.
657 */
658 void
659 fs_visitor::setup_builtin_uniform_values(ir_variable *ir)
660 {
661 const struct gl_builtin_uniform_desc *statevar = NULL;
662
663 for (unsigned int i = 0; _mesa_builtin_uniform_desc[i].name; i++) {
664 statevar = &_mesa_builtin_uniform_desc[i];
665 if (strcmp(ir->name, _mesa_builtin_uniform_desc[i].name) == 0)
666 break;
667 }
668
669 if (!statevar->name) {
670 this->fail = true;
671 printf("Failed to find builtin uniform `%s'\n", ir->name);
672 return;
673 }
674
675 int array_count;
676 if (ir->type->is_array()) {
677 array_count = ir->type->length;
678 } else {
679 array_count = 1;
680 }
681
682 for (int a = 0; a < array_count; a++) {
683 for (unsigned int i = 0; i < statevar->num_elements; i++) {
684 struct gl_builtin_uniform_element *element = &statevar->elements[i];
685 int tokens[STATE_LENGTH];
686
687 memcpy(tokens, element->tokens, sizeof(element->tokens));
688 if (ir->type->is_array()) {
689 tokens[1] = a;
690 }
691
692 /* This state reference has already been setup by ir_to_mesa,
693 * but we'll get the same index back here.
694 */
695 int index = _mesa_add_state_reference(this->fp->Base.Parameters,
696 (gl_state_index *)tokens);
697 float *vec_values = this->fp->Base.Parameters->ParameterValues[index];
698
699 /* Add each of the unique swizzles of the element as a
700 * parameter. This'll end up matching the expected layout of
701 * the array/matrix/structure we're trying to fill in.
702 */
703 int last_swiz = -1;
704 for (unsigned int i = 0; i < 4; i++) {
705 int swiz = GET_SWZ(element->swizzle, i);
706 if (swiz == last_swiz)
707 break;
708 last_swiz = swiz;
709
710 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[swiz];
711 }
712 }
713 }
714 }
715
716 void
717 fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
718 {
719 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
720 fs_reg wpos = *reg;
721 fs_reg neg_y = this->pixel_y;
722 neg_y.negate = true;
723
724 /* gl_FragCoord.x */
725 if (ir->pixel_center_integer) {
726 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_x));
727 } else {
728 emit(fs_inst(BRW_OPCODE_ADD, wpos, this->pixel_x, fs_reg(0.5f)));
729 }
730 wpos.reg_offset++;
731
732 /* gl_FragCoord.y */
733 if (ir->origin_upper_left && ir->pixel_center_integer) {
734 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_y));
735 } else {
736 fs_reg pixel_y = this->pixel_y;
737 float offset = (ir->pixel_center_integer ? 0.0 : 0.5);
738
739 if (!ir->origin_upper_left) {
740 pixel_y.negate = true;
741 offset += c->key.drawable_height - 1.0;
742 }
743
744 emit(fs_inst(BRW_OPCODE_ADD, wpos, pixel_y, fs_reg(offset)));
745 }
746 wpos.reg_offset++;
747
748 /* gl_FragCoord.z */
749 emit(fs_inst(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y,
750 interp_reg(FRAG_ATTRIB_WPOS, 2)));
751 wpos.reg_offset++;
752
753 /* gl_FragCoord.w: Already set up in emit_interpolation */
754 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->wpos_w));
755
756 hash_table_insert(this->variable_ht, reg, ir);
757 }
758
759
760 void
761 fs_visitor::emit_general_interpolation(ir_variable *ir)
762 {
763 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
764 /* Interpolation is always in floating point regs. */
765 reg->type = BRW_REGISTER_TYPE_F;
766 fs_reg attr = *reg;
767
768 unsigned int array_elements;
769 const glsl_type *type;
770
771 if (ir->type->is_array()) {
772 array_elements = ir->type->length;
773 if (array_elements == 0) {
774 this->fail = true;
775 }
776 type = ir->type->fields.array;
777 } else {
778 array_elements = 1;
779 type = ir->type;
780 }
781
782 int location = ir->location;
783 for (unsigned int i = 0; i < array_elements; i++) {
784 for (unsigned int j = 0; j < type->matrix_columns; j++) {
785 if (urb_setup[location] == -1) {
786 /* If there's no incoming setup data for this slot, don't
787 * emit interpolation for it.
788 */
789 attr.reg_offset += type->vector_elements;
790 location++;
791 continue;
792 }
793
794 for (unsigned int c = 0; c < type->vector_elements; c++) {
795 struct brw_reg interp = interp_reg(location, c);
796 emit(fs_inst(FS_OPCODE_LINTERP,
797 attr,
798 this->delta_x,
799 this->delta_y,
800 fs_reg(interp)));
801 attr.reg_offset++;
802 }
803 attr.reg_offset -= type->vector_elements;
804
805 for (unsigned int c = 0; c < type->vector_elements; c++) {
806 emit(fs_inst(BRW_OPCODE_MUL,
807 attr,
808 attr,
809 this->pixel_w));
810 attr.reg_offset++;
811 }
812 location++;
813 }
814 }
815
816 hash_table_insert(this->variable_ht, reg, ir);
817 }
818
819 void
820 fs_visitor::visit(ir_variable *ir)
821 {
822 fs_reg *reg = NULL;
823
824 if (variable_storage(ir))
825 return;
826
827 if (strcmp(ir->name, "gl_FragColor") == 0) {
828 this->frag_color = ir;
829 } else if (strcmp(ir->name, "gl_FragData") == 0) {
830 this->frag_data = ir;
831 } else if (strcmp(ir->name, "gl_FragDepth") == 0) {
832 this->frag_depth = ir;
833 }
834
835 if (ir->mode == ir_var_in) {
836 if (!strcmp(ir->name, "gl_FragCoord")) {
837 emit_fragcoord_interpolation(ir);
838 return;
839 } else if (!strcmp(ir->name, "gl_FrontFacing")) {
840 reg = new(this->mem_ctx) fs_reg(this, ir->type);
841 struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD);
842 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
843 * us front face
844 */
845 fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP,
846 *reg,
847 fs_reg(r1_6ud),
848 fs_reg(1u << 31)));
849 inst->conditional_mod = BRW_CONDITIONAL_L;
850 emit(fs_inst(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u)));
851 } else {
852 emit_general_interpolation(ir);
853 return;
854 }
855 }
856
857 if (ir->mode == ir_var_uniform) {
858 int param_index = c->prog_data.nr_params;
859
860 if (!strncmp(ir->name, "gl_", 3)) {
861 setup_builtin_uniform_values(ir);
862 } else {
863 setup_uniform_values(ir->location, ir->type);
864 }
865
866 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index);
867 }
868
869 if (!reg)
870 reg = new(this->mem_ctx) fs_reg(this, ir->type);
871
872 hash_table_insert(this->variable_ht, reg, ir);
873 }
874
875 void
876 fs_visitor::visit(ir_dereference_variable *ir)
877 {
878 fs_reg *reg = variable_storage(ir->var);
879 this->result = *reg;
880 }
881
882 void
883 fs_visitor::visit(ir_dereference_record *ir)
884 {
885 const glsl_type *struct_type = ir->record->type;
886
887 ir->record->accept(this);
888
889 unsigned int offset = 0;
890 for (unsigned int i = 0; i < struct_type->length; i++) {
891 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0)
892 break;
893 offset += type_size(struct_type->fields.structure[i].type);
894 }
895 this->result.reg_offset += offset;
896 this->result.type = brw_type_for_base_type(ir->type);
897 }
898
899 void
900 fs_visitor::visit(ir_dereference_array *ir)
901 {
902 ir_constant *index;
903 int element_size;
904
905 ir->array->accept(this);
906 index = ir->array_index->as_constant();
907
908 element_size = type_size(ir->type);
909 this->result.type = brw_type_for_base_type(ir->type);
910
911 if (index) {
912 assert(this->result.file == UNIFORM ||
913 (this->result.file == GRF &&
914 this->result.reg != 0));
915 this->result.reg_offset += index->value.i[0] * element_size;
916 } else {
917 assert(!"FINISHME: non-constant array element");
918 }
919 }
920
921 void
922 fs_visitor::visit(ir_expression *ir)
923 {
924 unsigned int operand;
925 fs_reg op[2], temp;
926 fs_reg result;
927 fs_inst *inst;
928
929 for (operand = 0; operand < ir->get_num_operands(); operand++) {
930 ir->operands[operand]->accept(this);
931 if (this->result.file == BAD_FILE) {
932 ir_print_visitor v;
933 printf("Failed to get tree for expression operand:\n");
934 ir->operands[operand]->accept(&v);
935 this->fail = true;
936 }
937 op[operand] = this->result;
938
939 /* Matrix expression operands should have been broken down to vector
940 * operations already.
941 */
942 assert(!ir->operands[operand]->type->is_matrix());
943 /* And then those vector operands should have been broken down to scalar.
944 */
945 assert(!ir->operands[operand]->type->is_vector());
946 }
947
948 /* Storage for our result. If our result goes into an assignment, it will
949 * just get copy-propagated out, so no worries.
950 */
951 this->result = fs_reg(this, ir->type);
952
953 switch (ir->operation) {
954 case ir_unop_logic_not:
955 emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], fs_reg(-1)));
956 break;
957 case ir_unop_neg:
958 op[0].negate = !op[0].negate;
959 this->result = op[0];
960 break;
961 case ir_unop_abs:
962 op[0].abs = true;
963 this->result = op[0];
964 break;
965 case ir_unop_sign:
966 temp = fs_reg(this, ir->type);
967
968 emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)));
969
970 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, op[0], fs_reg(0.0f)));
971 inst->conditional_mod = BRW_CONDITIONAL_G;
972 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)));
973 inst->predicated = true;
974
975 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, op[0], fs_reg(0.0f)));
976 inst->conditional_mod = BRW_CONDITIONAL_L;
977 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)));
978 inst->predicated = true;
979
980 break;
981 case ir_unop_rcp:
982 emit(fs_inst(FS_OPCODE_RCP, this->result, op[0]));
983 break;
984
985 case ir_unop_exp2:
986 emit(fs_inst(FS_OPCODE_EXP2, this->result, op[0]));
987 break;
988 case ir_unop_log2:
989 emit(fs_inst(FS_OPCODE_LOG2, this->result, op[0]));
990 break;
991 case ir_unop_exp:
992 case ir_unop_log:
993 assert(!"not reached: should be handled by ir_explog_to_explog2");
994 break;
995 case ir_unop_sin:
996 emit(fs_inst(FS_OPCODE_SIN, this->result, op[0]));
997 break;
998 case ir_unop_cos:
999 emit(fs_inst(FS_OPCODE_COS, this->result, op[0]));
1000 break;
1001
1002 case ir_unop_dFdx:
1003 emit(fs_inst(FS_OPCODE_DDX, this->result, op[0]));
1004 break;
1005 case ir_unop_dFdy:
1006 emit(fs_inst(FS_OPCODE_DDY, this->result, op[0]));
1007 break;
1008
1009 case ir_binop_add:
1010 emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], op[1]));
1011 break;
1012 case ir_binop_sub:
1013 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1014 break;
1015
1016 case ir_binop_mul:
1017 emit(fs_inst(BRW_OPCODE_MUL, this->result, op[0], op[1]));
1018 break;
1019 case ir_binop_div:
1020 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1021 break;
1022 case ir_binop_mod:
1023 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1024 break;
1025
1026 case ir_binop_less:
1027 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1028 inst->conditional_mod = BRW_CONDITIONAL_L;
1029 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
1030 break;
1031 case ir_binop_greater:
1032 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1033 inst->conditional_mod = BRW_CONDITIONAL_G;
1034 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
1035 break;
1036 case ir_binop_lequal:
1037 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1038 inst->conditional_mod = BRW_CONDITIONAL_LE;
1039 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
1040 break;
1041 case ir_binop_gequal:
1042 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1043 inst->conditional_mod = BRW_CONDITIONAL_GE;
1044 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
1045 break;
1046 case ir_binop_equal:
1047 case ir_binop_all_equal: /* same as nequal for scalars */
1048 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1049 inst->conditional_mod = BRW_CONDITIONAL_Z;
1050 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
1051 break;
1052 case ir_binop_nequal:
1053 case ir_binop_any_nequal: /* same as nequal for scalars */
1054 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1055 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1056 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
1057 break;
1058
1059 case ir_binop_logic_xor:
1060 emit(fs_inst(BRW_OPCODE_XOR, this->result, op[0], op[1]));
1061 break;
1062
1063 case ir_binop_logic_or:
1064 emit(fs_inst(BRW_OPCODE_OR, this->result, op[0], op[1]));
1065 break;
1066
1067 case ir_binop_logic_and:
1068 emit(fs_inst(BRW_OPCODE_AND, this->result, op[0], op[1]));
1069 break;
1070
1071 case ir_binop_dot:
1072 case ir_binop_cross:
1073 case ir_unop_any:
1074 assert(!"not reached: should be handled by brw_fs_channel_expressions");
1075 break;
1076
1077 case ir_unop_noise:
1078 assert(!"not reached: should be handled by lower_noise");
1079 break;
1080
1081 case ir_unop_sqrt:
1082 emit(fs_inst(FS_OPCODE_SQRT, this->result, op[0]));
1083 break;
1084
1085 case ir_unop_rsq:
1086 emit(fs_inst(FS_OPCODE_RSQ, this->result, op[0]));
1087 break;
1088
1089 case ir_unop_i2f:
1090 case ir_unop_b2f:
1091 case ir_unop_b2i:
1092 emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0]));
1093 break;
1094 case ir_unop_f2i:
1095 emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0]));
1096 break;
1097 case ir_unop_f2b:
1098 case ir_unop_i2b:
1099 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], fs_reg(0.0f)));
1100 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1101
1102 case ir_unop_trunc:
1103 emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
1104 break;
1105 case ir_unop_ceil:
1106 op[0].negate = ~op[0].negate;
1107 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
1108 this->result.negate = true;
1109 break;
1110 case ir_unop_floor:
1111 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
1112 break;
1113 case ir_unop_fract:
1114 inst = emit(fs_inst(BRW_OPCODE_FRC, this->result, op[0]));
1115 break;
1116
1117 case ir_binop_min:
1118 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1119 inst->conditional_mod = BRW_CONDITIONAL_L;
1120
1121 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1]));
1122 inst->predicated = true;
1123 break;
1124 case ir_binop_max:
1125 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1126 inst->conditional_mod = BRW_CONDITIONAL_G;
1127
1128 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1]));
1129 inst->predicated = true;
1130 break;
1131
1132 case ir_binop_pow:
1133 inst = emit(fs_inst(FS_OPCODE_POW, this->result, op[0], op[1]));
1134 break;
1135
1136 case ir_unop_bit_not:
1137 case ir_unop_u2f:
1138 case ir_binop_lshift:
1139 case ir_binop_rshift:
1140 case ir_binop_bit_and:
1141 case ir_binop_bit_xor:
1142 case ir_binop_bit_or:
1143 assert(!"GLSL 1.30 features unsupported");
1144 break;
1145 }
1146 }
1147
1148 void
1149 fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r,
1150 const glsl_type *type, bool predicated)
1151 {
1152 switch (type->base_type) {
1153 case GLSL_TYPE_FLOAT:
1154 case GLSL_TYPE_UINT:
1155 case GLSL_TYPE_INT:
1156 case GLSL_TYPE_BOOL:
1157 for (unsigned int i = 0; i < type->components(); i++) {
1158 l.type = brw_type_for_base_type(type);
1159 r.type = brw_type_for_base_type(type);
1160
1161 fs_inst *inst = emit(fs_inst(BRW_OPCODE_MOV, l, r));
1162 inst->predicated = predicated;
1163
1164 l.reg_offset++;
1165 r.reg_offset++;
1166 }
1167 break;
1168 case GLSL_TYPE_ARRAY:
1169 for (unsigned int i = 0; i < type->length; i++) {
1170 emit_assignment_writes(l, r, type->fields.array, predicated);
1171 }
1172
1173 case GLSL_TYPE_STRUCT:
1174 for (unsigned int i = 0; i < type->length; i++) {
1175 emit_assignment_writes(l, r, type->fields.structure[i].type,
1176 predicated);
1177 }
1178 break;
1179
1180 case GLSL_TYPE_SAMPLER:
1181 break;
1182
1183 default:
1184 assert(!"not reached");
1185 break;
1186 }
1187 }
1188
1189 void
1190 fs_visitor::visit(ir_assignment *ir)
1191 {
1192 struct fs_reg l, r;
1193 fs_inst *inst;
1194
1195 /* FINISHME: arrays on the lhs */
1196 ir->lhs->accept(this);
1197 l = this->result;
1198
1199 ir->rhs->accept(this);
1200 r = this->result;
1201
1202 assert(l.file != BAD_FILE);
1203 assert(r.file != BAD_FILE);
1204
1205 if (ir->condition) {
1206 /* Get the condition bool into the predicate. */
1207 ir->condition->accept(this);
1208 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, this->result, fs_reg(0)));
1209 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1210 }
1211
1212 if (ir->lhs->type->is_scalar() ||
1213 ir->lhs->type->is_vector()) {
1214 for (int i = 0; i < ir->lhs->type->vector_elements; i++) {
1215 if (ir->write_mask & (1 << i)) {
1216 inst = emit(fs_inst(BRW_OPCODE_MOV, l, r));
1217 if (ir->condition)
1218 inst->predicated = true;
1219 r.reg_offset++;
1220 }
1221 l.reg_offset++;
1222 }
1223 } else {
1224 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL);
1225 }
1226 }
1227
1228 fs_inst *
1229 fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate)
1230 {
1231 int mlen;
1232 int base_mrf = 2;
1233 bool simd16 = false;
1234 fs_reg orig_dst;
1235
1236 if (ir->shadow_comparitor) {
1237 for (mlen = 0; mlen < ir->coordinate->type->vector_elements; mlen++) {
1238 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1239 coordinate));
1240 coordinate.reg_offset++;
1241 mlen++;
1242 }
1243 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1244 mlen = 3;
1245
1246 if (ir->op == ir_tex) {
1247 /* There's no plain shadow compare message, so we use shadow
1248 * compare with a bias of 0.0.
1249 */
1250 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1251 fs_reg(0.0f)));
1252 mlen++;
1253 } else if (ir->op == ir_txb) {
1254 ir->lod_info.bias->accept(this);
1255 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1256 this->result));
1257 mlen++;
1258 } else {
1259 assert(ir->op == ir_txl);
1260 ir->lod_info.lod->accept(this);
1261 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1262 this->result));
1263 mlen++;
1264 }
1265
1266 ir->shadow_comparitor->accept(this);
1267 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1268 mlen++;
1269 } else if (ir->op == ir_tex) {
1270 for (mlen = 0; mlen < ir->coordinate->type->vector_elements; mlen++) {
1271 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1272 coordinate));
1273 coordinate.reg_offset++;
1274 }
1275 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1276 mlen = 3;
1277 } else {
1278 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1279 * instructions. We'll need to do SIMD16 here.
1280 */
1281 assert(ir->op == ir_txb || ir->op == ir_txl);
1282
1283 for (mlen = 0; mlen < ir->coordinate->type->vector_elements * 2;) {
1284 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1285 coordinate));
1286 coordinate.reg_offset++;
1287 mlen++;
1288
1289 /* The unused upper half. */
1290 mlen++;
1291 }
1292
1293 /* lod/bias appears after u/v/r. */
1294 mlen = 6;
1295
1296 if (ir->op == ir_txb) {
1297 ir->lod_info.bias->accept(this);
1298 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1299 this->result));
1300 mlen++;
1301 } else {
1302 ir->lod_info.lod->accept(this);
1303 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1304 this->result));
1305 mlen++;
1306 }
1307
1308 /* The unused upper half. */
1309 mlen++;
1310
1311 /* Now, since we're doing simd16, the return is 2 interleaved
1312 * vec4s where the odd-indexed ones are junk. We'll need to move
1313 * this weirdness around to the expected layout.
1314 */
1315 simd16 = true;
1316 orig_dst = dst;
1317 dst = fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type,
1318 2));
1319 dst.type = BRW_REGISTER_TYPE_F;
1320 }
1321
1322 fs_inst *inst = NULL;
1323 switch (ir->op) {
1324 case ir_tex:
1325 inst = emit(fs_inst(FS_OPCODE_TEX, dst, fs_reg(MRF, base_mrf)));
1326 break;
1327 case ir_txb:
1328 inst = emit(fs_inst(FS_OPCODE_TXB, dst, fs_reg(MRF, base_mrf)));
1329 break;
1330 case ir_txl:
1331 inst = emit(fs_inst(FS_OPCODE_TXL, dst, fs_reg(MRF, base_mrf)));
1332 break;
1333 case ir_txd:
1334 case ir_txf:
1335 assert(!"GLSL 1.30 features unsupported");
1336 break;
1337 }
1338 inst->mlen = mlen;
1339
1340 if (simd16) {
1341 for (int i = 0; i < 4; i++) {
1342 emit(fs_inst(BRW_OPCODE_MOV, orig_dst, dst));
1343 orig_dst.reg_offset++;
1344 dst.reg_offset += 2;
1345 }
1346 }
1347
1348 return inst;
1349 }
1350
1351 fs_inst *
1352 fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate)
1353 {
1354 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1355 * optional parameters like shadow comparitor or LOD bias. If
1356 * optional parameters aren't present, those base slots are
1357 * optional and don't need to be included in the message.
1358 *
1359 * We don't fill in the unnecessary slots regardless, which may
1360 * look surprising in the disassembly.
1361 */
1362 int mlen;
1363 int base_mrf = 2;
1364
1365 for (mlen = 0; mlen < ir->coordinate->type->vector_elements; mlen++) {
1366 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate));
1367 coordinate.reg_offset++;
1368 mlen++;
1369 }
1370
1371 if (ir->shadow_comparitor) {
1372 mlen = MAX2(mlen, 4);
1373
1374 ir->shadow_comparitor->accept(this);
1375 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1376 mlen++;
1377 }
1378
1379 fs_inst *inst = NULL;
1380 switch (ir->op) {
1381 case ir_tex:
1382 inst = emit(fs_inst(FS_OPCODE_TEX, dst, fs_reg(MRF, base_mrf)));
1383 break;
1384 case ir_txb:
1385 ir->lod_info.bias->accept(this);
1386 mlen = MAX2(mlen, 4);
1387 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1388 mlen++;
1389
1390 inst = emit(fs_inst(FS_OPCODE_TXB, dst, fs_reg(MRF, base_mrf)));
1391 break;
1392 case ir_txl:
1393 ir->lod_info.lod->accept(this);
1394 mlen = MAX2(mlen, 4);
1395 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1396 mlen++;
1397
1398 inst = emit(fs_inst(FS_OPCODE_TXL, dst, fs_reg(MRF, base_mrf)));
1399 break;
1400 case ir_txd:
1401 case ir_txf:
1402 assert(!"GLSL 1.30 features unsupported");
1403 break;
1404 }
1405 inst->mlen = mlen;
1406
1407 return inst;
1408 }
1409
1410 void
1411 fs_visitor::visit(ir_texture *ir)
1412 {
1413 fs_inst *inst = NULL;
1414
1415 ir->coordinate->accept(this);
1416 fs_reg coordinate = this->result;
1417
1418 /* Should be lowered by do_lower_texture_projection */
1419 assert(!ir->projector);
1420
1421 /* Writemasking doesn't eliminate channels on SIMD8 texture
1422 * samples, so don't worry about them.
1423 */
1424 fs_reg dst = fs_reg(this, glsl_type::vec4_type);
1425
1426 if (intel->gen < 5) {
1427 inst = emit_texture_gen4(ir, dst, coordinate);
1428 } else {
1429 inst = emit_texture_gen5(ir, dst, coordinate);
1430 }
1431
1432 inst->sampler =
1433 _mesa_get_sampler_uniform_value(ir->sampler,
1434 ctx->Shader.CurrentProgram,
1435 &brw->fragment_program->Base);
1436 inst->sampler = c->fp->program.Base.SamplerUnits[inst->sampler];
1437
1438 this->result = dst;
1439
1440 if (ir->shadow_comparitor)
1441 inst->shadow_compare = true;
1442 }
1443
1444 void
1445 fs_visitor::visit(ir_swizzle *ir)
1446 {
1447 ir->val->accept(this);
1448 fs_reg val = this->result;
1449
1450 fs_reg result = fs_reg(this, ir->type);
1451 this->result = result;
1452
1453 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1454 fs_reg channel = val;
1455 int swiz = 0;
1456
1457 switch (i) {
1458 case 0:
1459 swiz = ir->mask.x;
1460 break;
1461 case 1:
1462 swiz = ir->mask.y;
1463 break;
1464 case 2:
1465 swiz = ir->mask.z;
1466 break;
1467 case 3:
1468 swiz = ir->mask.w;
1469 break;
1470 }
1471
1472 channel.reg_offset += swiz;
1473 emit(fs_inst(BRW_OPCODE_MOV, result, channel));
1474 result.reg_offset++;
1475 }
1476 }
1477
1478 void
1479 fs_visitor::visit(ir_discard *ir)
1480 {
1481 fs_reg temp = fs_reg(this, glsl_type::uint_type);
1482
1483 assert(ir->condition == NULL); /* FINISHME */
1484
1485 emit(fs_inst(FS_OPCODE_DISCARD, temp, temp));
1486 }
1487
1488 void
1489 fs_visitor::visit(ir_constant *ir)
1490 {
1491 fs_reg reg(this, ir->type);
1492 this->result = reg;
1493
1494 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1495 switch (ir->type->base_type) {
1496 case GLSL_TYPE_FLOAT:
1497 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.f[i])));
1498 break;
1499 case GLSL_TYPE_UINT:
1500 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.u[i])));
1501 break;
1502 case GLSL_TYPE_INT:
1503 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.i[i])));
1504 break;
1505 case GLSL_TYPE_BOOL:
1506 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg((int)ir->value.b[i])));
1507 break;
1508 default:
1509 assert(!"Non-float/uint/int/bool constant");
1510 }
1511 reg.reg_offset++;
1512 }
1513 }
1514
1515 void
1516 fs_visitor::visit(ir_if *ir)
1517 {
1518 fs_inst *inst;
1519
1520 /* Don't point the annotation at the if statement, because then it plus
1521 * the then and else blocks get printed.
1522 */
1523 this->base_ir = ir->condition;
1524
1525 /* Generate the condition into the condition code. */
1526 ir->condition->accept(this);
1527 inst = emit(fs_inst(BRW_OPCODE_MOV, fs_reg(brw_null_reg()), this->result));
1528 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1529
1530 inst = emit(fs_inst(BRW_OPCODE_IF));
1531 inst->predicated = true;
1532
1533 foreach_iter(exec_list_iterator, iter, ir->then_instructions) {
1534 ir_instruction *ir = (ir_instruction *)iter.get();
1535 this->base_ir = ir;
1536
1537 ir->accept(this);
1538 }
1539
1540 if (!ir->else_instructions.is_empty()) {
1541 emit(fs_inst(BRW_OPCODE_ELSE));
1542
1543 foreach_iter(exec_list_iterator, iter, ir->else_instructions) {
1544 ir_instruction *ir = (ir_instruction *)iter.get();
1545 this->base_ir = ir;
1546
1547 ir->accept(this);
1548 }
1549 }
1550
1551 emit(fs_inst(BRW_OPCODE_ENDIF));
1552 }
1553
1554 void
1555 fs_visitor::visit(ir_loop *ir)
1556 {
1557 fs_reg counter = reg_undef;
1558
1559 if (ir->counter) {
1560 this->base_ir = ir->counter;
1561 ir->counter->accept(this);
1562 counter = *(variable_storage(ir->counter));
1563
1564 if (ir->from) {
1565 this->base_ir = ir->from;
1566 ir->from->accept(this);
1567
1568 emit(fs_inst(BRW_OPCODE_MOV, counter, this->result));
1569 }
1570 }
1571
1572 emit(fs_inst(BRW_OPCODE_DO));
1573
1574 if (ir->to) {
1575 this->base_ir = ir->to;
1576 ir->to->accept(this);
1577
1578 fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null,
1579 counter, this->result));
1580 switch (ir->cmp) {
1581 case ir_binop_equal:
1582 inst->conditional_mod = BRW_CONDITIONAL_Z;
1583 break;
1584 case ir_binop_nequal:
1585 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1586 break;
1587 case ir_binop_gequal:
1588 inst->conditional_mod = BRW_CONDITIONAL_GE;
1589 break;
1590 case ir_binop_lequal:
1591 inst->conditional_mod = BRW_CONDITIONAL_LE;
1592 break;
1593 case ir_binop_greater:
1594 inst->conditional_mod = BRW_CONDITIONAL_G;
1595 break;
1596 case ir_binop_less:
1597 inst->conditional_mod = BRW_CONDITIONAL_L;
1598 break;
1599 default:
1600 assert(!"not reached: unknown loop condition");
1601 this->fail = true;
1602 break;
1603 }
1604
1605 inst = emit(fs_inst(BRW_OPCODE_BREAK));
1606 inst->predicated = true;
1607 }
1608
1609 foreach_iter(exec_list_iterator, iter, ir->body_instructions) {
1610 ir_instruction *ir = (ir_instruction *)iter.get();
1611
1612 this->base_ir = ir;
1613 ir->accept(this);
1614 }
1615
1616 if (ir->increment) {
1617 this->base_ir = ir->increment;
1618 ir->increment->accept(this);
1619 emit(fs_inst(BRW_OPCODE_ADD, counter, counter, this->result));
1620 }
1621
1622 emit(fs_inst(BRW_OPCODE_WHILE));
1623 }
1624
1625 void
1626 fs_visitor::visit(ir_loop_jump *ir)
1627 {
1628 switch (ir->mode) {
1629 case ir_loop_jump::jump_break:
1630 emit(fs_inst(BRW_OPCODE_BREAK));
1631 break;
1632 case ir_loop_jump::jump_continue:
1633 emit(fs_inst(BRW_OPCODE_CONTINUE));
1634 break;
1635 }
1636 }
1637
1638 void
1639 fs_visitor::visit(ir_call *ir)
1640 {
1641 assert(!"FINISHME");
1642 }
1643
1644 void
1645 fs_visitor::visit(ir_return *ir)
1646 {
1647 assert(!"FINISHME");
1648 }
1649
1650 void
1651 fs_visitor::visit(ir_function *ir)
1652 {
1653 /* Ignore function bodies other than main() -- we shouldn't see calls to
1654 * them since they should all be inlined before we get to ir_to_mesa.
1655 */
1656 if (strcmp(ir->name, "main") == 0) {
1657 const ir_function_signature *sig;
1658 exec_list empty;
1659
1660 sig = ir->matching_signature(&empty);
1661
1662 assert(sig);
1663
1664 foreach_iter(exec_list_iterator, iter, sig->body) {
1665 ir_instruction *ir = (ir_instruction *)iter.get();
1666 this->base_ir = ir;
1667
1668 ir->accept(this);
1669 }
1670 }
1671 }
1672
1673 void
1674 fs_visitor::visit(ir_function_signature *ir)
1675 {
1676 assert(!"not reached");
1677 (void)ir;
1678 }
1679
1680 fs_inst *
1681 fs_visitor::emit(fs_inst inst)
1682 {
1683 fs_inst *list_inst = new(mem_ctx) fs_inst;
1684 *list_inst = inst;
1685
1686 list_inst->annotation = this->current_annotation;
1687 list_inst->ir = this->base_ir;
1688
1689 this->instructions.push_tail(list_inst);
1690
1691 return list_inst;
1692 }
1693
1694 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1695 void
1696 fs_visitor::emit_dummy_fs()
1697 {
1698 /* Everyone's favorite color. */
1699 emit(fs_inst(BRW_OPCODE_MOV,
1700 fs_reg(MRF, 2),
1701 fs_reg(1.0f)));
1702 emit(fs_inst(BRW_OPCODE_MOV,
1703 fs_reg(MRF, 3),
1704 fs_reg(0.0f)));
1705 emit(fs_inst(BRW_OPCODE_MOV,
1706 fs_reg(MRF, 4),
1707 fs_reg(1.0f)));
1708 emit(fs_inst(BRW_OPCODE_MOV,
1709 fs_reg(MRF, 5),
1710 fs_reg(0.0f)));
1711
1712 fs_inst *write;
1713 write = emit(fs_inst(FS_OPCODE_FB_WRITE,
1714 fs_reg(0),
1715 fs_reg(0)));
1716 }
1717
1718 /* The register location here is relative to the start of the URB
1719 * data. It will get adjusted to be a real location before
1720 * generate_code() time.
1721 */
1722 struct brw_reg
1723 fs_visitor::interp_reg(int location, int channel)
1724 {
1725 int regnr = urb_setup[location] * 2 + channel / 2;
1726 int stride = (channel & 1) * 4;
1727
1728 assert(urb_setup[location] != -1);
1729
1730 return brw_vec1_grf(regnr, stride);
1731 }
1732
1733 /** Emits the interpolation for the varying inputs. */
1734 void
1735 fs_visitor::emit_interpolation_setup_gen4()
1736 {
1737 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
1738
1739 this->current_annotation = "compute pixel centers";
1740 this->pixel_x = fs_reg(this, glsl_type::uint_type);
1741 this->pixel_y = fs_reg(this, glsl_type::uint_type);
1742 this->pixel_x.type = BRW_REGISTER_TYPE_UW;
1743 this->pixel_y.type = BRW_REGISTER_TYPE_UW;
1744 emit(fs_inst(BRW_OPCODE_ADD,
1745 this->pixel_x,
1746 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
1747 fs_reg(brw_imm_v(0x10101010))));
1748 emit(fs_inst(BRW_OPCODE_ADD,
1749 this->pixel_y,
1750 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
1751 fs_reg(brw_imm_v(0x11001100))));
1752
1753 this->current_annotation = "compute pixel deltas from v0";
1754 this->delta_x = fs_reg(this, glsl_type::float_type);
1755 this->delta_y = fs_reg(this, glsl_type::float_type);
1756 emit(fs_inst(BRW_OPCODE_ADD,
1757 this->delta_x,
1758 this->pixel_x,
1759 fs_reg(negate(brw_vec1_grf(1, 0)))));
1760 emit(fs_inst(BRW_OPCODE_ADD,
1761 this->delta_y,
1762 this->pixel_y,
1763 fs_reg(negate(brw_vec1_grf(1, 1)))));
1764
1765 this->current_annotation = "compute pos.w and 1/pos.w";
1766 /* Compute wpos.w. It's always in our setup, since it's needed to
1767 * interpolate the other attributes.
1768 */
1769 this->wpos_w = fs_reg(this, glsl_type::float_type);
1770 emit(fs_inst(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y,
1771 interp_reg(FRAG_ATTRIB_WPOS, 3)));
1772 /* Compute the pixel 1/W value from wpos.w. */
1773 this->pixel_w = fs_reg(this, glsl_type::float_type);
1774 emit(fs_inst(FS_OPCODE_RCP, this->pixel_w, wpos_w));
1775 this->current_annotation = NULL;
1776 }
1777
1778 /** Emits the interpolation for the varying inputs. */
1779 void
1780 fs_visitor::emit_interpolation_setup_gen6()
1781 {
1782 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
1783
1784 /* If the pixel centers end up used, the setup is the same as for gen4. */
1785 this->current_annotation = "compute pixel centers";
1786 this->pixel_x = fs_reg(this, glsl_type::uint_type);
1787 this->pixel_y = fs_reg(this, glsl_type::uint_type);
1788 this->pixel_x.type = BRW_REGISTER_TYPE_UW;
1789 this->pixel_y.type = BRW_REGISTER_TYPE_UW;
1790 emit(fs_inst(BRW_OPCODE_ADD,
1791 this->pixel_x,
1792 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
1793 fs_reg(brw_imm_v(0x10101010))));
1794 emit(fs_inst(BRW_OPCODE_ADD,
1795 this->pixel_y,
1796 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
1797 fs_reg(brw_imm_v(0x11001100))));
1798
1799 this->current_annotation = "compute 1/pos.w";
1800 this->wpos_w = fs_reg(brw_vec8_grf(c->key.source_w_reg, 0));
1801 this->pixel_w = fs_reg(this, glsl_type::float_type);
1802 emit(fs_inst(FS_OPCODE_RCP, this->pixel_w, wpos_w));
1803
1804 this->delta_x = fs_reg(brw_vec8_grf(2, 0));
1805 this->delta_y = fs_reg(brw_vec8_grf(3, 0));
1806
1807 this->current_annotation = NULL;
1808 }
1809
1810 void
1811 fs_visitor::emit_fb_writes()
1812 {
1813 this->current_annotation = "FB write header";
1814 int nr = 0;
1815
1816 /* m0, m1 header */
1817 nr += 2;
1818
1819 if (c->key.aa_dest_stencil_reg) {
1820 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
1821 fs_reg(brw_vec8_grf(c->key.aa_dest_stencil_reg, 0))));
1822 }
1823
1824 /* Reserve space for color. It'll be filled in per MRT below. */
1825 int color_mrf = nr;
1826 nr += 4;
1827
1828 if (c->key.source_depth_to_render_target) {
1829 if (c->key.computes_depth) {
1830 /* Hand over gl_FragDepth. */
1831 assert(this->frag_depth);
1832 fs_reg depth = *(variable_storage(this->frag_depth));
1833
1834 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++), depth));
1835 } else {
1836 /* Pass through the payload depth. */
1837 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
1838 fs_reg(brw_vec8_grf(c->key.source_depth_reg, 0))));
1839 }
1840 }
1841
1842 if (c->key.dest_depth_reg) {
1843 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
1844 fs_reg(brw_vec8_grf(c->key.dest_depth_reg, 0))));
1845 }
1846
1847 fs_reg color = reg_undef;
1848 if (this->frag_color)
1849 color = *(variable_storage(this->frag_color));
1850 else if (this->frag_data)
1851 color = *(variable_storage(this->frag_data));
1852
1853 for (int target = 0; target < c->key.nr_color_regions; target++) {
1854 this->current_annotation = talloc_asprintf(this->mem_ctx,
1855 "FB write target %d",
1856 target);
1857 if (this->frag_color || this->frag_data) {
1858 for (int i = 0; i < 4; i++) {
1859 emit(fs_inst(BRW_OPCODE_MOV,
1860 fs_reg(MRF, color_mrf + i),
1861 color));
1862 color.reg_offset++;
1863 }
1864 }
1865
1866 if (this->frag_color)
1867 color.reg_offset -= 4;
1868
1869 fs_inst *inst = emit(fs_inst(FS_OPCODE_FB_WRITE,
1870 reg_undef, reg_undef));
1871 inst->target = target;
1872 inst->mlen = nr;
1873 if (target == c->key.nr_color_regions - 1)
1874 inst->eot = true;
1875 }
1876
1877 if (c->key.nr_color_regions == 0) {
1878 fs_inst *inst = emit(fs_inst(FS_OPCODE_FB_WRITE,
1879 reg_undef, reg_undef));
1880 inst->mlen = nr;
1881 inst->eot = true;
1882 }
1883
1884 this->current_annotation = NULL;
1885 }
1886
1887 void
1888 fs_visitor::generate_fb_write(fs_inst *inst)
1889 {
1890 GLboolean eot = inst->eot;
1891
1892 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1893 * move, here's g1.
1894 */
1895 brw_push_insn_state(p);
1896 brw_set_mask_control(p, BRW_MASK_DISABLE);
1897 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1898 brw_MOV(p,
1899 brw_message_reg(1),
1900 brw_vec8_grf(1, 0));
1901 brw_pop_insn_state(p);
1902
1903 brw_fb_WRITE(p,
1904 8, /* dispatch_width */
1905 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW),
1906 0, /* base MRF */
1907 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
1908 inst->target,
1909 inst->mlen,
1910 0,
1911 eot);
1912 }
1913
1914 void
1915 fs_visitor::generate_linterp(fs_inst *inst,
1916 struct brw_reg dst, struct brw_reg *src)
1917 {
1918 struct brw_reg delta_x = src[0];
1919 struct brw_reg delta_y = src[1];
1920 struct brw_reg interp = src[2];
1921
1922 if (brw->has_pln &&
1923 delta_y.nr == delta_x.nr + 1 &&
1924 (intel->gen >= 6 || (delta_x.nr & 1) == 0)) {
1925 brw_PLN(p, dst, interp, delta_x);
1926 } else {
1927 brw_LINE(p, brw_null_reg(), interp, delta_x);
1928 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
1929 }
1930 }
1931
1932 void
1933 fs_visitor::generate_math(fs_inst *inst,
1934 struct brw_reg dst, struct brw_reg *src)
1935 {
1936 int op;
1937
1938 switch (inst->opcode) {
1939 case FS_OPCODE_RCP:
1940 op = BRW_MATH_FUNCTION_INV;
1941 break;
1942 case FS_OPCODE_RSQ:
1943 op = BRW_MATH_FUNCTION_RSQ;
1944 break;
1945 case FS_OPCODE_SQRT:
1946 op = BRW_MATH_FUNCTION_SQRT;
1947 break;
1948 case FS_OPCODE_EXP2:
1949 op = BRW_MATH_FUNCTION_EXP;
1950 break;
1951 case FS_OPCODE_LOG2:
1952 op = BRW_MATH_FUNCTION_LOG;
1953 break;
1954 case FS_OPCODE_POW:
1955 op = BRW_MATH_FUNCTION_POW;
1956 break;
1957 case FS_OPCODE_SIN:
1958 op = BRW_MATH_FUNCTION_SIN;
1959 break;
1960 case FS_OPCODE_COS:
1961 op = BRW_MATH_FUNCTION_COS;
1962 break;
1963 default:
1964 assert(!"not reached: unknown math function");
1965 op = 0;
1966 break;
1967 }
1968
1969 if (inst->opcode == FS_OPCODE_POW) {
1970 brw_MOV(p, brw_message_reg(3), src[1]);
1971 }
1972
1973 brw_math(p, dst,
1974 op,
1975 inst->saturate ? BRW_MATH_SATURATE_SATURATE :
1976 BRW_MATH_SATURATE_NONE,
1977 2, src[0],
1978 BRW_MATH_DATA_VECTOR,
1979 BRW_MATH_PRECISION_FULL);
1980 }
1981
1982 void
1983 fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
1984 {
1985 int msg_type = -1;
1986 int rlen = 4;
1987 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1988
1989 if (intel->gen == 5) {
1990 switch (inst->opcode) {
1991 case FS_OPCODE_TEX:
1992 if (inst->shadow_compare) {
1993 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5;
1994 } else {
1995 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_GEN5;
1996 }
1997 break;
1998 case FS_OPCODE_TXB:
1999 if (inst->shadow_compare) {
2000 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5;
2001 } else {
2002 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5;
2003 }
2004 break;
2005 }
2006 } else {
2007 switch (inst->opcode) {
2008 case FS_OPCODE_TEX:
2009 /* Note that G45 and older determines shadow compare and dispatch width
2010 * from message length for most messages.
2011 */
2012 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
2013 if (inst->shadow_compare) {
2014 assert(inst->mlen == 5);
2015 } else {
2016 assert(inst->mlen <= 6);
2017 }
2018 break;
2019 case FS_OPCODE_TXB:
2020 if (inst->shadow_compare) {
2021 assert(inst->mlen == 5);
2022 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
2023 } else {
2024 assert(inst->mlen == 8);
2025 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
2026 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
2027 }
2028 break;
2029 }
2030 }
2031 assert(msg_type != -1);
2032
2033 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
2034 rlen = 8;
2035 dst = vec16(dst);
2036 }
2037
2038 /* g0 header. */
2039 src.nr--;
2040
2041 brw_SAMPLE(p,
2042 retype(dst, BRW_REGISTER_TYPE_UW),
2043 src.nr,
2044 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
2045 SURF_INDEX_TEXTURE(inst->sampler),
2046 inst->sampler,
2047 WRITEMASK_XYZW,
2048 msg_type,
2049 rlen,
2050 inst->mlen + 1,
2051 0,
2052 1,
2053 simd_mode);
2054 }
2055
2056
2057 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2058 * looking like:
2059 *
2060 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2061 *
2062 * and we're trying to produce:
2063 *
2064 * DDX DDY
2065 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2066 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2067 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2068 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2069 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2070 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2071 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2072 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2073 *
2074 * and add another set of two more subspans if in 16-pixel dispatch mode.
2075 *
2076 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2077 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2078 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2079 * between each other. We could probably do it like ddx and swizzle the right
2080 * order later, but bail for now and just produce
2081 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2082 */
2083 void
2084 fs_visitor::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
2085 {
2086 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
2087 BRW_REGISTER_TYPE_F,
2088 BRW_VERTICAL_STRIDE_2,
2089 BRW_WIDTH_2,
2090 BRW_HORIZONTAL_STRIDE_0,
2091 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
2092 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
2093 BRW_REGISTER_TYPE_F,
2094 BRW_VERTICAL_STRIDE_2,
2095 BRW_WIDTH_2,
2096 BRW_HORIZONTAL_STRIDE_0,
2097 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
2098 brw_ADD(p, dst, src0, negate(src1));
2099 }
2100
2101 void
2102 fs_visitor::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
2103 {
2104 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
2105 BRW_REGISTER_TYPE_F,
2106 BRW_VERTICAL_STRIDE_4,
2107 BRW_WIDTH_4,
2108 BRW_HORIZONTAL_STRIDE_0,
2109 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
2110 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
2111 BRW_REGISTER_TYPE_F,
2112 BRW_VERTICAL_STRIDE_4,
2113 BRW_WIDTH_4,
2114 BRW_HORIZONTAL_STRIDE_0,
2115 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
2116 brw_ADD(p, dst, src0, negate(src1));
2117 }
2118
2119 void
2120 fs_visitor::generate_discard(fs_inst *inst, struct brw_reg temp)
2121 {
2122 struct brw_reg g0 = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
2123 temp = brw_uw1_reg(temp.file, temp.nr, 0);
2124
2125 brw_push_insn_state(p);
2126 brw_set_mask_control(p, BRW_MASK_DISABLE);
2127 brw_NOT(p, temp, brw_mask_reg(1)); /* IMASK */
2128 brw_AND(p, g0, temp, g0);
2129 brw_pop_insn_state(p);
2130 }
2131
2132 void
2133 fs_visitor::assign_curb_setup()
2134 {
2135 c->prog_data.first_curbe_grf = c->key.nr_payload_regs;
2136 c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8;
2137
2138 if (intel->gen == 5 && (c->prog_data.first_curbe_grf +
2139 c->prog_data.curb_read_length) & 1) {
2140 /* Align the start of the interpolation coefficients so that we can use
2141 * the PLN instruction.
2142 */
2143 c->prog_data.first_curbe_grf++;
2144 }
2145
2146 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2147 foreach_iter(exec_list_iterator, iter, this->instructions) {
2148 fs_inst *inst = (fs_inst *)iter.get();
2149
2150 for (unsigned int i = 0; i < 3; i++) {
2151 if (inst->src[i].file == UNIFORM) {
2152 int constant_nr = inst->src[i].hw_reg + inst->src[i].reg_offset;
2153 struct brw_reg brw_reg = brw_vec1_grf(c->prog_data.first_curbe_grf +
2154 constant_nr / 8,
2155 constant_nr % 8);
2156
2157 inst->src[i].file = FIXED_HW_REG;
2158 inst->src[i].fixed_hw_reg = brw_reg;
2159 }
2160 }
2161 }
2162 }
2163
2164 void
2165 fs_visitor::calculate_urb_setup()
2166 {
2167 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
2168 urb_setup[i] = -1;
2169 }
2170
2171 int urb_next = 0;
2172 /* Figure out where each of the incoming setup attributes lands. */
2173 if (intel->gen >= 6) {
2174 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
2175 if (i == FRAG_ATTRIB_WPOS ||
2176 (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(i))) {
2177 urb_setup[i] = urb_next++;
2178 }
2179 }
2180 } else {
2181 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2182 for (unsigned int i = 0; i < VERT_RESULT_MAX; i++) {
2183 if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) {
2184 int fp_index;
2185
2186 if (i >= VERT_RESULT_VAR0)
2187 fp_index = i - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
2188 else if (i <= VERT_RESULT_TEX7)
2189 fp_index = i;
2190 else
2191 fp_index = -1;
2192
2193 if (fp_index >= 0)
2194 urb_setup[fp_index] = urb_next++;
2195 }
2196 }
2197 }
2198
2199 /* Each attribute is 4 setup channels, each of which is half a reg. */
2200 c->prog_data.urb_read_length = urb_next * 2;
2201 }
2202
2203 void
2204 fs_visitor::assign_urb_setup()
2205 {
2206 int urb_start = c->prog_data.first_curbe_grf + c->prog_data.curb_read_length;
2207
2208 /* Offset all the urb_setup[] index by the actual position of the
2209 * setup regs, now that the location of the constants has been chosen.
2210 */
2211 foreach_iter(exec_list_iterator, iter, this->instructions) {
2212 fs_inst *inst = (fs_inst *)iter.get();
2213
2214 if (inst->opcode != FS_OPCODE_LINTERP)
2215 continue;
2216
2217 assert(inst->src[2].file == FIXED_HW_REG);
2218
2219 inst->src[2].fixed_hw_reg.nr += urb_start;
2220 }
2221
2222 this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length;
2223 }
2224
2225 static void
2226 assign_reg(int *reg_hw_locations, fs_reg *reg)
2227 {
2228 if (reg->file == GRF && reg->reg != 0) {
2229 reg->hw_reg = reg_hw_locations[reg->reg] + reg->reg_offset;
2230 reg->reg = 0;
2231 }
2232 }
2233
2234 void
2235 fs_visitor::assign_regs_trivial()
2236 {
2237 int last_grf = 0;
2238 int hw_reg_mapping[this->virtual_grf_next];
2239 int i;
2240
2241 hw_reg_mapping[0] = 0;
2242 hw_reg_mapping[1] = this->first_non_payload_grf;
2243 for (i = 2; i < this->virtual_grf_next; i++) {
2244 hw_reg_mapping[i] = (hw_reg_mapping[i - 1] +
2245 this->virtual_grf_sizes[i - 1]);
2246 }
2247 last_grf = hw_reg_mapping[i - 1] + this->virtual_grf_sizes[i - 1];
2248
2249 foreach_iter(exec_list_iterator, iter, this->instructions) {
2250 fs_inst *inst = (fs_inst *)iter.get();
2251
2252 assign_reg(hw_reg_mapping, &inst->dst);
2253 assign_reg(hw_reg_mapping, &inst->src[0]);
2254 assign_reg(hw_reg_mapping, &inst->src[1]);
2255 }
2256
2257 this->grf_used = last_grf + 1;
2258 }
2259
2260 void
2261 fs_visitor::assign_regs()
2262 {
2263 int last_grf = 0;
2264 int hw_reg_mapping[this->virtual_grf_next + 1];
2265 int base_reg_count = BRW_MAX_GRF - this->first_non_payload_grf;
2266 int class_sizes[base_reg_count];
2267 int class_count = 0;
2268
2269 calculate_live_intervals();
2270
2271 /* Set up the register classes.
2272 *
2273 * The base registers store a scalar value. For texture samples,
2274 * we get virtual GRFs composed of 4 contiguous hw register. For
2275 * structures and arrays, we store them as contiguous larger things
2276 * than that, though we should be able to do better most of the
2277 * time.
2278 */
2279 class_sizes[class_count++] = 1;
2280 for (int r = 1; r < this->virtual_grf_next; r++) {
2281 int i;
2282
2283 for (i = 0; i < class_count; i++) {
2284 if (class_sizes[i] == this->virtual_grf_sizes[r])
2285 break;
2286 }
2287 if (i == class_count) {
2288 class_sizes[class_count++] = this->virtual_grf_sizes[r];
2289 }
2290 }
2291
2292 int ra_reg_count = 0;
2293 int class_base_reg[class_count];
2294 int class_reg_count[class_count];
2295 int classes[class_count];
2296
2297 for (int i = 0; i < class_count; i++) {
2298 class_base_reg[i] = ra_reg_count;
2299 class_reg_count[i] = base_reg_count - (class_sizes[i] - 1);
2300 ra_reg_count += class_reg_count[i];
2301 }
2302
2303 struct ra_regs *regs = ra_alloc_reg_set(ra_reg_count);
2304 for (int i = 0; i < class_count; i++) {
2305 classes[i] = ra_alloc_reg_class(regs);
2306
2307 for (int i_r = 0; i_r < class_reg_count[i]; i_r++) {
2308 ra_class_add_reg(regs, classes[i], class_base_reg[i] + i_r);
2309 }
2310
2311 /* Add conflicts between our contiguous registers aliasing
2312 * base regs and other register classes' contiguous registers
2313 * that alias base regs, or the base regs themselves for classes[0].
2314 */
2315 for (int c = 0; c <= i; c++) {
2316 for (int i_r = 0; i_r < class_reg_count[i] - 1; i_r++) {
2317 for (int c_r = MAX2(0, i_r - (class_sizes[c] - 1));
2318 c_r <= MIN2(class_reg_count[c] - 1, i_r + class_sizes[i] - 1);
2319 c_r++) {
2320
2321 if (0) {
2322 printf("%d/%d conflicts %d/%d\n",
2323 class_sizes[i], i_r,
2324 class_sizes[c], c_r);
2325 }
2326
2327 ra_add_reg_conflict(regs,
2328 class_base_reg[i] + i_r,
2329 class_base_reg[c] + c_r);
2330 }
2331 }
2332 }
2333 }
2334
2335 ra_set_finalize(regs);
2336
2337 struct ra_graph *g = ra_alloc_interference_graph(regs,
2338 this->virtual_grf_next);
2339 /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
2340 * with nodes.
2341 */
2342 ra_set_node_class(g, 0, classes[0]);
2343
2344 for (int i = 1; i < this->virtual_grf_next; i++) {
2345 for (int c = 0; c < class_count; c++) {
2346 if (class_sizes[c] == this->virtual_grf_sizes[i]) {
2347 ra_set_node_class(g, i, classes[c]);
2348 break;
2349 }
2350 }
2351
2352 for (int j = 1; j < i; j++) {
2353 if (virtual_grf_interferes(i, j)) {
2354 ra_add_node_interference(g, i, j);
2355 }
2356 }
2357 }
2358
2359 /* FINISHME: Handle spilling */
2360 if (!ra_allocate_no_spills(g)) {
2361 fprintf(stderr, "Failed to allocate registers.\n");
2362 this->fail = true;
2363 return;
2364 }
2365
2366 /* Get the chosen virtual registers for each node, and map virtual
2367 * regs in the register classes back down to real hardware reg
2368 * numbers.
2369 */
2370 hw_reg_mapping[0] = 0; /* unused */
2371 for (int i = 1; i < this->virtual_grf_next; i++) {
2372 int reg = ra_get_node_reg(g, i);
2373 int hw_reg = -1;
2374
2375 for (int c = 0; c < class_count; c++) {
2376 if (reg >= class_base_reg[c] &&
2377 reg < class_base_reg[c] + class_reg_count[c] - 1) {
2378 hw_reg = reg - class_base_reg[c];
2379 break;
2380 }
2381 }
2382
2383 assert(hw_reg != -1);
2384 hw_reg_mapping[i] = this->first_non_payload_grf + hw_reg;
2385 last_grf = MAX2(last_grf,
2386 hw_reg_mapping[i] + this->virtual_grf_sizes[i] - 1);
2387 }
2388
2389 foreach_iter(exec_list_iterator, iter, this->instructions) {
2390 fs_inst *inst = (fs_inst *)iter.get();
2391
2392 assign_reg(hw_reg_mapping, &inst->dst);
2393 assign_reg(hw_reg_mapping, &inst->src[0]);
2394 assign_reg(hw_reg_mapping, &inst->src[1]);
2395 }
2396
2397 this->grf_used = last_grf + 1;
2398
2399 talloc_free(g);
2400 talloc_free(regs);
2401 }
2402
2403 void
2404 fs_visitor::calculate_live_intervals()
2405 {
2406 int num_vars = this->virtual_grf_next;
2407 int *def = talloc_array(mem_ctx, int, num_vars);
2408 int *use = talloc_array(mem_ctx, int, num_vars);
2409 int loop_depth = 0;
2410 int loop_start = 0;
2411
2412 for (int i = 0; i < num_vars; i++) {
2413 def[i] = 1 << 30;
2414 use[i] = 0;
2415 }
2416
2417 int ip = 0;
2418 foreach_iter(exec_list_iterator, iter, this->instructions) {
2419 fs_inst *inst = (fs_inst *)iter.get();
2420
2421 if (inst->opcode == BRW_OPCODE_DO) {
2422 if (loop_depth++ == 0)
2423 loop_start = ip;
2424 } else if (inst->opcode == BRW_OPCODE_WHILE) {
2425 loop_depth--;
2426
2427 if (loop_depth == 0) {
2428 /* FINISHME:
2429 *
2430 * Patches up any vars marked for use within the loop as
2431 * live until the end. This is conservative, as there
2432 * will often be variables defined and used inside the
2433 * loop but dead at the end of the loop body.
2434 */
2435 for (int i = 0; i < num_vars; i++) {
2436 if (use[i] == loop_start) {
2437 use[i] = ip;
2438 }
2439 }
2440 }
2441 } else {
2442 int eip = ip;
2443
2444 if (loop_depth)
2445 eip = loop_start;
2446
2447 for (unsigned int i = 0; i < 3; i++) {
2448 if (inst->src[i].file == GRF && inst->src[i].reg != 0) {
2449 def[inst->src[i].reg] = MIN2(def[inst->src[i].reg], eip);
2450 use[inst->src[i].reg] = MAX2(use[inst->src[i].reg], eip);
2451 }
2452 }
2453 if (inst->dst.file == GRF && inst->dst.reg != 0) {
2454 def[inst->dst.reg] = MIN2(def[inst->dst.reg], eip);
2455 use[inst->dst.reg] = MAX2(use[inst->dst.reg], eip);
2456 }
2457 }
2458
2459 ip++;
2460 }
2461
2462 this->virtual_grf_def = def;
2463 this->virtual_grf_use = use;
2464 }
2465
2466 bool
2467 fs_visitor::virtual_grf_interferes(int a, int b)
2468 {
2469 int start = MAX2(this->virtual_grf_def[a], this->virtual_grf_def[b]);
2470 int end = MIN2(this->virtual_grf_use[a], this->virtual_grf_use[b]);
2471
2472 return start <= end;
2473 }
2474
2475 static struct brw_reg brw_reg_from_fs_reg(fs_reg *reg)
2476 {
2477 struct brw_reg brw_reg;
2478
2479 switch (reg->file) {
2480 case GRF:
2481 case ARF:
2482 case MRF:
2483 brw_reg = brw_vec8_reg(reg->file,
2484 reg->hw_reg, 0);
2485 brw_reg = retype(brw_reg, reg->type);
2486 break;
2487 case IMM:
2488 switch (reg->type) {
2489 case BRW_REGISTER_TYPE_F:
2490 brw_reg = brw_imm_f(reg->imm.f);
2491 break;
2492 case BRW_REGISTER_TYPE_D:
2493 brw_reg = brw_imm_d(reg->imm.i);
2494 break;
2495 case BRW_REGISTER_TYPE_UD:
2496 brw_reg = brw_imm_ud(reg->imm.u);
2497 break;
2498 default:
2499 assert(!"not reached");
2500 break;
2501 }
2502 break;
2503 case FIXED_HW_REG:
2504 brw_reg = reg->fixed_hw_reg;
2505 break;
2506 case BAD_FILE:
2507 /* Probably unused. */
2508 brw_reg = brw_null_reg();
2509 break;
2510 case UNIFORM:
2511 assert(!"not reached");
2512 brw_reg = brw_null_reg();
2513 break;
2514 }
2515 if (reg->abs)
2516 brw_reg = brw_abs(brw_reg);
2517 if (reg->negate)
2518 brw_reg = negate(brw_reg);
2519
2520 return brw_reg;
2521 }
2522
2523 void
2524 fs_visitor::generate_code()
2525 {
2526 unsigned int annotation_len = 0;
2527 int last_native_inst = 0;
2528 struct brw_instruction *if_stack[16], *loop_stack[16];
2529 int if_stack_depth = 0, loop_stack_depth = 0;
2530 int if_depth_in_loop[16];
2531
2532 if_depth_in_loop[loop_stack_depth] = 0;
2533
2534 memset(&if_stack, 0, sizeof(if_stack));
2535 foreach_iter(exec_list_iterator, iter, this->instructions) {
2536 fs_inst *inst = (fs_inst *)iter.get();
2537 struct brw_reg src[3], dst;
2538
2539 for (unsigned int i = 0; i < 3; i++) {
2540 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
2541 }
2542 dst = brw_reg_from_fs_reg(&inst->dst);
2543
2544 brw_set_conditionalmod(p, inst->conditional_mod);
2545 brw_set_predicate_control(p, inst->predicated);
2546
2547 switch (inst->opcode) {
2548 case BRW_OPCODE_MOV:
2549 brw_MOV(p, dst, src[0]);
2550 break;
2551 case BRW_OPCODE_ADD:
2552 brw_ADD(p, dst, src[0], src[1]);
2553 break;
2554 case BRW_OPCODE_MUL:
2555 brw_MUL(p, dst, src[0], src[1]);
2556 break;
2557
2558 case BRW_OPCODE_FRC:
2559 brw_FRC(p, dst, src[0]);
2560 break;
2561 case BRW_OPCODE_RNDD:
2562 brw_RNDD(p, dst, src[0]);
2563 break;
2564 case BRW_OPCODE_RNDZ:
2565 brw_RNDZ(p, dst, src[0]);
2566 break;
2567
2568 case BRW_OPCODE_AND:
2569 brw_AND(p, dst, src[0], src[1]);
2570 break;
2571 case BRW_OPCODE_OR:
2572 brw_OR(p, dst, src[0], src[1]);
2573 break;
2574 case BRW_OPCODE_XOR:
2575 brw_XOR(p, dst, src[0], src[1]);
2576 break;
2577
2578 case BRW_OPCODE_CMP:
2579 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
2580 break;
2581 case BRW_OPCODE_SEL:
2582 brw_SEL(p, dst, src[0], src[1]);
2583 break;
2584
2585 case BRW_OPCODE_IF:
2586 assert(if_stack_depth < 16);
2587 if_stack[if_stack_depth] = brw_IF(p, BRW_EXECUTE_8);
2588 if_depth_in_loop[loop_stack_depth]++;
2589 if_stack_depth++;
2590 break;
2591 case BRW_OPCODE_ELSE:
2592 if_stack[if_stack_depth - 1] =
2593 brw_ELSE(p, if_stack[if_stack_depth - 1]);
2594 break;
2595 case BRW_OPCODE_ENDIF:
2596 if_stack_depth--;
2597 brw_ENDIF(p , if_stack[if_stack_depth]);
2598 if_depth_in_loop[loop_stack_depth]--;
2599 break;
2600
2601 case BRW_OPCODE_DO:
2602 loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
2603 if_depth_in_loop[loop_stack_depth] = 0;
2604 break;
2605
2606 case BRW_OPCODE_BREAK:
2607 brw_BREAK(p, if_depth_in_loop[loop_stack_depth]);
2608 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
2609 break;
2610 case BRW_OPCODE_CONTINUE:
2611 brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
2612 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
2613 break;
2614
2615 case BRW_OPCODE_WHILE: {
2616 struct brw_instruction *inst0, *inst1;
2617 GLuint br = 1;
2618
2619 if (intel->gen >= 5)
2620 br = 2;
2621
2622 assert(loop_stack_depth > 0);
2623 loop_stack_depth--;
2624 inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
2625 /* patch all the BREAK/CONT instructions from last BGNLOOP */
2626 while (inst0 > loop_stack[loop_stack_depth]) {
2627 inst0--;
2628 if (inst0->header.opcode == BRW_OPCODE_BREAK &&
2629 inst0->bits3.if_else.jump_count == 0) {
2630 inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
2631 }
2632 else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
2633 inst0->bits3.if_else.jump_count == 0) {
2634 inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
2635 }
2636 }
2637 }
2638 break;
2639
2640 case FS_OPCODE_RCP:
2641 case FS_OPCODE_RSQ:
2642 case FS_OPCODE_SQRT:
2643 case FS_OPCODE_EXP2:
2644 case FS_OPCODE_LOG2:
2645 case FS_OPCODE_POW:
2646 case FS_OPCODE_SIN:
2647 case FS_OPCODE_COS:
2648 generate_math(inst, dst, src);
2649 break;
2650 case FS_OPCODE_LINTERP:
2651 generate_linterp(inst, dst, src);
2652 break;
2653 case FS_OPCODE_TEX:
2654 case FS_OPCODE_TXB:
2655 case FS_OPCODE_TXL:
2656 generate_tex(inst, dst, src[0]);
2657 break;
2658 case FS_OPCODE_DISCARD:
2659 generate_discard(inst, dst /* src0 == dst */);
2660 break;
2661 case FS_OPCODE_DDX:
2662 generate_ddx(inst, dst, src[0]);
2663 break;
2664 case FS_OPCODE_DDY:
2665 generate_ddy(inst, dst, src[0]);
2666 break;
2667 case FS_OPCODE_FB_WRITE:
2668 generate_fb_write(inst);
2669 break;
2670 default:
2671 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
2672 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
2673 brw_opcodes[inst->opcode].name);
2674 } else {
2675 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
2676 }
2677 this->fail = true;
2678 }
2679
2680 if (annotation_len < p->nr_insn) {
2681 annotation_len *= 2;
2682 if (annotation_len < 16)
2683 annotation_len = 16;
2684
2685 this->annotation_string = talloc_realloc(this->mem_ctx,
2686 annotation_string,
2687 const char *,
2688 annotation_len);
2689 this->annotation_ir = talloc_realloc(this->mem_ctx,
2690 annotation_ir,
2691 ir_instruction *,
2692 annotation_len);
2693 }
2694
2695 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
2696 this->annotation_string[i] = inst->annotation;
2697 this->annotation_ir[i] = inst->ir;
2698 }
2699 last_native_inst = p->nr_insn;
2700 }
2701 }
2702
2703 GLboolean
2704 brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c)
2705 {
2706 struct brw_compile *p = &c->func;
2707 struct intel_context *intel = &brw->intel;
2708 GLcontext *ctx = &intel->ctx;
2709 struct brw_shader *shader = NULL;
2710 struct gl_shader_program *prog = ctx->Shader.CurrentProgram;
2711
2712 if (!prog)
2713 return GL_FALSE;
2714
2715 if (!using_new_fs)
2716 return GL_FALSE;
2717
2718 for (unsigned int i = 0; i < prog->_NumLinkedShaders; i++) {
2719 if (prog->_LinkedShaders[i]->Type == GL_FRAGMENT_SHADER) {
2720 shader = (struct brw_shader *)prog->_LinkedShaders[i];
2721 break;
2722 }
2723 }
2724 if (!shader)
2725 return GL_FALSE;
2726
2727 /* We always use 8-wide mode, at least for now. For one, flow
2728 * control only works in 8-wide. Also, when we're fragment shader
2729 * bound, we're almost always under register pressure as well, so
2730 * 8-wide would save us from the performance cliff of spilling
2731 * regs.
2732 */
2733 c->dispatch_width = 8;
2734
2735 if (INTEL_DEBUG & DEBUG_WM) {
2736 printf("GLSL IR for native fragment shader %d:\n", prog->Name);
2737 _mesa_print_ir(shader->ir, NULL);
2738 printf("\n");
2739 }
2740
2741 /* Now the main event: Visit the shader IR and generate our FS IR for it.
2742 */
2743 fs_visitor v(c, shader);
2744
2745 if (0) {
2746 v.emit_dummy_fs();
2747 } else {
2748 v.calculate_urb_setup();
2749 if (intel->gen < 6)
2750 v.emit_interpolation_setup_gen4();
2751 else
2752 v.emit_interpolation_setup_gen6();
2753
2754 /* Generate FS IR for main(). (the visitor only descends into
2755 * functions called "main").
2756 */
2757 foreach_iter(exec_list_iterator, iter, *shader->ir) {
2758 ir_instruction *ir = (ir_instruction *)iter.get();
2759 v.base_ir = ir;
2760 ir->accept(&v);
2761 }
2762
2763 v.emit_fb_writes();
2764 v.assign_curb_setup();
2765 v.assign_urb_setup();
2766 if (0)
2767 v.assign_regs_trivial();
2768 else
2769 v.assign_regs();
2770 }
2771
2772 v.generate_code();
2773
2774 assert(!v.fail); /* FINISHME: Cleanly fail, tested at link time, etc. */
2775
2776 if (v.fail)
2777 return GL_FALSE;
2778
2779 if (INTEL_DEBUG & DEBUG_WM) {
2780 const char *last_annotation_string = NULL;
2781 ir_instruction *last_annotation_ir = NULL;
2782
2783 printf("Native code for fragment shader %d:\n", prog->Name);
2784 for (unsigned int i = 0; i < p->nr_insn; i++) {
2785 if (last_annotation_ir != v.annotation_ir[i]) {
2786 last_annotation_ir = v.annotation_ir[i];
2787 if (last_annotation_ir) {
2788 printf(" ");
2789 last_annotation_ir->print();
2790 printf("\n");
2791 }
2792 }
2793 if (last_annotation_string != v.annotation_string[i]) {
2794 last_annotation_string = v.annotation_string[i];
2795 if (last_annotation_string)
2796 printf(" %s\n", last_annotation_string);
2797 }
2798 brw_disasm(stdout, &p->store[i], intel->gen);
2799 }
2800 printf("\n");
2801 }
2802
2803 c->prog_data.total_grf = v.grf_used;
2804 c->prog_data.total_scratch = 0;
2805
2806 return GL_TRUE;
2807 }