2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "../glsl/glsl_types.h"
48 #include "../glsl/ir_optimization.h"
49 #include "../glsl/ir_print_visitor.h"
51 #define MAX_INSTRUCTION (1 << 30)
52 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
55 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
57 struct brw_shader
*shader
;
59 shader
= talloc_zero(NULL
, struct brw_shader
);
61 shader
->base
.Type
= type
;
62 shader
->base
.Name
= name
;
63 _mesa_init_shader(ctx
, &shader
->base
);
69 struct gl_shader_program
*
70 brw_new_shader_program(struct gl_context
*ctx
, GLuint name
)
72 struct brw_shader_program
*prog
;
73 prog
= talloc_zero(NULL
, struct brw_shader_program
);
75 prog
->base
.Name
= name
;
76 _mesa_init_shader_program(ctx
, &prog
->base
);
82 brw_compile_shader(struct gl_context
*ctx
, struct gl_shader
*shader
)
84 if (!_mesa_ir_compile_shader(ctx
, shader
))
91 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
93 struct brw_context
*brw
= brw_context(ctx
);
94 struct intel_context
*intel
= &brw
->intel
;
96 struct brw_shader
*shader
=
97 (struct brw_shader
*)prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
99 void *mem_ctx
= talloc_new(NULL
);
103 talloc_free(shader
->ir
);
104 shader
->ir
= new(shader
) exec_list
;
105 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
107 do_mat_op_to_vec(shader
->ir
);
108 lower_instructions(shader
->ir
,
115 /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
116 * if-statements need to be flattened.
119 lower_if_to_cond_assign(shader
->ir
, 16);
121 do_lower_texture_projection(shader
->ir
);
122 do_vec_index_to_cond_assign(shader
->ir
);
123 brw_do_cubemap_normalize(shader
->ir
);
128 brw_do_channel_expressions(shader
->ir
);
129 brw_do_vector_splitting(shader
->ir
);
131 progress
= do_lower_jumps(shader
->ir
, true, true,
132 true, /* main return */
133 false, /* continue */
137 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
139 progress
= lower_noise(shader
->ir
) || progress
;
141 lower_variable_index_to_cond_assign(shader
->ir
,
143 GL_TRUE
, /* output */
145 GL_TRUE
/* uniform */
147 progress
= lower_quadop_vector(shader
->ir
, false) || progress
;
150 validate_ir_tree(shader
->ir
);
152 reparent_ir(shader
->ir
, shader
->ir
);
153 talloc_free(mem_ctx
);
156 if (!_mesa_ir_link_shader(ctx
, prog
))
163 type_size(const struct glsl_type
*type
)
165 unsigned int size
, i
;
167 switch (type
->base_type
) {
170 case GLSL_TYPE_FLOAT
:
172 return type
->components();
173 case GLSL_TYPE_ARRAY
:
174 return type_size(type
->fields
.array
) * type
->length
;
175 case GLSL_TYPE_STRUCT
:
177 for (i
= 0; i
< type
->length
; i
++) {
178 size
+= type_size(type
->fields
.structure
[i
].type
);
181 case GLSL_TYPE_SAMPLER
:
182 /* Samplers take up no register space, since they're baked in at
187 assert(!"not reached");
193 * Returns how many MRFs an FS opcode will write over.
195 * Note that this is not the 0 or 1 implied writes in an actual gen
196 * instruction -- the FS opcodes often generate MOVs in addition.
199 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
204 switch (inst
->opcode
) {
219 case FS_OPCODE_FB_WRITE
:
221 case FS_OPCODE_PULL_CONSTANT_LOAD
:
222 case FS_OPCODE_UNSPILL
:
224 case FS_OPCODE_SPILL
:
227 assert(!"not reached");
233 fs_visitor::virtual_grf_alloc(int size
)
235 if (virtual_grf_array_size
<= virtual_grf_next
) {
236 if (virtual_grf_array_size
== 0)
237 virtual_grf_array_size
= 16;
239 virtual_grf_array_size
*= 2;
240 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
241 int, virtual_grf_array_size
);
243 /* This slot is always unused. */
244 virtual_grf_sizes
[0] = 0;
246 virtual_grf_sizes
[virtual_grf_next
] = size
;
247 return virtual_grf_next
++;
250 /** Fixed HW reg constructor. */
251 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
255 this->hw_reg
= hw_reg
;
256 this->type
= BRW_REGISTER_TYPE_F
;
259 /** Fixed HW reg constructor. */
260 fs_reg::fs_reg(enum register_file file
, int hw_reg
, uint32_t type
)
264 this->hw_reg
= hw_reg
;
269 brw_type_for_base_type(const struct glsl_type
*type
)
271 switch (type
->base_type
) {
272 case GLSL_TYPE_FLOAT
:
273 return BRW_REGISTER_TYPE_F
;
276 return BRW_REGISTER_TYPE_D
;
278 return BRW_REGISTER_TYPE_UD
;
279 case GLSL_TYPE_ARRAY
:
280 case GLSL_TYPE_STRUCT
:
281 case GLSL_TYPE_SAMPLER
:
282 /* These should be overridden with the type of the member when
283 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
284 * way to trip up if we don't.
286 return BRW_REGISTER_TYPE_UD
;
288 assert(!"not reached");
289 return BRW_REGISTER_TYPE_F
;
293 /** Automatic reg constructor. */
294 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
299 this->reg
= v
->virtual_grf_alloc(type_size(type
));
300 this->reg_offset
= 0;
301 this->type
= brw_type_for_base_type(type
);
305 fs_visitor::variable_storage(ir_variable
*var
)
307 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
310 /* Our support for uniforms is piggy-backed on the struct
311 * gl_fragment_program, because that's where the values actually
312 * get stored, rather than in some global gl_shader_program uniform
316 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
318 unsigned int offset
= 0;
321 if (type
->is_matrix()) {
322 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
323 type
->vector_elements
,
326 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
327 offset
+= setup_uniform_values(loc
+ offset
, column
);
333 switch (type
->base_type
) {
334 case GLSL_TYPE_FLOAT
:
338 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
339 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
340 unsigned int param
= c
->prog_data
.nr_params
++;
342 assert(param
< ARRAY_SIZE(c
->prog_data
.param
));
344 switch (type
->base_type
) {
345 case GLSL_TYPE_FLOAT
:
346 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
349 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2U
;
352 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2I
;
355 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2B
;
358 assert(!"not reached");
359 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
363 c
->prog_data
.param
[param
] = &vec_values
[i
];
367 case GLSL_TYPE_STRUCT
:
368 for (unsigned int i
= 0; i
< type
->length
; i
++) {
369 offset
+= setup_uniform_values(loc
+ offset
,
370 type
->fields
.structure
[i
].type
);
374 case GLSL_TYPE_ARRAY
:
375 for (unsigned int i
= 0; i
< type
->length
; i
++) {
376 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
380 case GLSL_TYPE_SAMPLER
:
381 /* The sampler takes up a slot, but we don't use any values from it. */
385 assert(!"not reached");
391 /* Our support for builtin uniforms is even scarier than non-builtin.
392 * It sits on top of the PROG_STATE_VAR parameters that are
393 * automatically updated from GL context state.
396 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
398 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
400 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
401 statevar
= &_mesa_builtin_uniform_desc
[i
];
402 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
406 if (!statevar
->name
) {
408 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
413 if (ir
->type
->is_array()) {
414 array_count
= ir
->type
->length
;
419 for (int a
= 0; a
< array_count
; a
++) {
420 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
421 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
422 int tokens
[STATE_LENGTH
];
424 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
425 if (ir
->type
->is_array()) {
429 /* This state reference has already been setup by ir_to_mesa,
430 * but we'll get the same index back here.
432 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
433 (gl_state_index
*)tokens
);
434 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
436 /* Add each of the unique swizzles of the element as a
437 * parameter. This'll end up matching the expected layout of
438 * the array/matrix/structure we're trying to fill in.
441 for (unsigned int i
= 0; i
< 4; i
++) {
442 int swiz
= GET_SWZ(element
->swizzle
, i
);
443 if (swiz
== last_swiz
)
447 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
449 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
456 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
458 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
460 fs_reg neg_y
= this->pixel_y
;
462 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
465 if (ir
->pixel_center_integer
) {
466 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
468 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
473 if (!flip
&& ir
->pixel_center_integer
) {
474 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
476 fs_reg pixel_y
= this->pixel_y
;
477 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
480 pixel_y
.negate
= true;
481 offset
+= c
->key
.drawable_height
- 1.0;
484 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
489 if (intel
->gen
>= 6) {
490 emit(fs_inst(BRW_OPCODE_MOV
, wpos
,
491 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
493 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
494 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
498 /* gl_FragCoord.w: Already set up in emit_interpolation */
499 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
505 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
507 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
508 /* Interpolation is always in floating point regs. */
509 reg
->type
= BRW_REGISTER_TYPE_F
;
512 unsigned int array_elements
;
513 const glsl_type
*type
;
515 if (ir
->type
->is_array()) {
516 array_elements
= ir
->type
->length
;
517 if (array_elements
== 0) {
520 type
= ir
->type
->fields
.array
;
526 int location
= ir
->location
;
527 for (unsigned int i
= 0; i
< array_elements
; i
++) {
528 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
529 if (urb_setup
[location
] == -1) {
530 /* If there's no incoming setup data for this slot, don't
531 * emit interpolation for it.
533 attr
.reg_offset
+= type
->vector_elements
;
538 if (c
->key
.flat_shade
&& (location
== FRAG_ATTRIB_COL0
||
539 location
== FRAG_ATTRIB_COL1
)) {
540 /* Constant interpolation (flat shading) case. The SF has
541 * handed us defined values in only the constant offset
542 * field of the setup reg.
544 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
545 struct brw_reg interp
= interp_reg(location
, c
);
546 interp
= suboffset(interp
, 3);
547 emit(fs_inst(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
)));
551 /* Perspective interpolation case. */
552 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
553 struct brw_reg interp
= interp_reg(location
, c
);
554 emit(fs_inst(FS_OPCODE_LINTERP
,
562 if (intel
->gen
< 6) {
563 attr
.reg_offset
-= type
->vector_elements
;
564 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
565 emit(fs_inst(BRW_OPCODE_MUL
,
581 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
583 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
585 /* The frontfacing comes in as a bit in the thread payload. */
586 if (intel
->gen
>= 6) {
587 emit(fs_inst(BRW_OPCODE_ASR
,
589 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
591 emit(fs_inst(BRW_OPCODE_NOT
,
594 emit(fs_inst(BRW_OPCODE_AND
,
599 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
600 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
603 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
607 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
608 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
615 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src
)
627 assert(!"not reached: bad math opcode");
631 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
632 * might be able to do better by doing execsize = 1 math and then
633 * expanding that result out, but we would need to be careful with
636 * The hardware ignores source modifiers (negate and abs) on math
637 * instructions, so we also move to a temp to set those up.
639 if (intel
->gen
>= 6 && (src
.file
== UNIFORM
||
642 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
643 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src
));
647 fs_inst
*inst
= emit(fs_inst(opcode
, dst
, src
));
649 if (intel
->gen
< 6) {
658 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
663 assert(opcode
== FS_OPCODE_POW
);
665 if (intel
->gen
>= 6) {
666 /* Can't do hstride == 0 args to gen6 math, so expand it out. */
667 if (src0
.file
== UNIFORM
) {
668 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
669 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src0
));
673 if (src1
.file
== UNIFORM
) {
674 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
675 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src1
));
679 inst
= emit(fs_inst(opcode
, dst
, src0
, src1
));
681 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1), src1
));
682 inst
= emit(fs_inst(opcode
, dst
, src0
, reg_null_f
));
684 inst
->base_mrf
= base_mrf
;
691 fs_visitor::visit(ir_variable
*ir
)
695 if (variable_storage(ir
))
698 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
699 this->frag_color
= ir
;
700 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
701 this->frag_data
= ir
;
702 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
703 this->frag_depth
= ir
;
706 if (ir
->mode
== ir_var_in
) {
707 if (!strcmp(ir
->name
, "gl_FragCoord")) {
708 reg
= emit_fragcoord_interpolation(ir
);
709 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
710 reg
= emit_frontfacing_interpolation(ir
);
712 reg
= emit_general_interpolation(ir
);
715 hash_table_insert(this->variable_ht
, reg
, ir
);
719 if (ir
->mode
== ir_var_uniform
) {
720 int param_index
= c
->prog_data
.nr_params
;
722 if (!strncmp(ir
->name
, "gl_", 3)) {
723 setup_builtin_uniform_values(ir
);
725 setup_uniform_values(ir
->location
, ir
->type
);
728 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
729 reg
->type
= brw_type_for_base_type(ir
->type
);
733 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
735 hash_table_insert(this->variable_ht
, reg
, ir
);
739 fs_visitor::visit(ir_dereference_variable
*ir
)
741 fs_reg
*reg
= variable_storage(ir
->var
);
746 fs_visitor::visit(ir_dereference_record
*ir
)
748 const glsl_type
*struct_type
= ir
->record
->type
;
750 ir
->record
->accept(this);
752 unsigned int offset
= 0;
753 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
754 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
756 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
758 this->result
.reg_offset
+= offset
;
759 this->result
.type
= brw_type_for_base_type(ir
->type
);
763 fs_visitor::visit(ir_dereference_array
*ir
)
768 ir
->array
->accept(this);
769 index
= ir
->array_index
->as_constant();
771 element_size
= type_size(ir
->type
);
772 this->result
.type
= brw_type_for_base_type(ir
->type
);
775 assert(this->result
.file
== UNIFORM
||
776 (this->result
.file
== GRF
&&
777 this->result
.reg
!= 0));
778 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
780 assert(!"FINISHME: non-constant array element");
784 /* Instruction selection: Produce a MOV.sat instead of
785 * MIN(MAX(val, 0), 1) when possible.
788 fs_visitor::try_emit_saturate(ir_expression
*ir
)
790 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
795 sat_val
->accept(this);
796 fs_reg src
= this->result
;
798 this->result
= fs_reg(this, ir
->type
);
799 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, src
));
800 inst
->saturate
= true;
806 brw_conditional_for_comparison(unsigned int op
)
810 return BRW_CONDITIONAL_L
;
811 case ir_binop_greater
:
812 return BRW_CONDITIONAL_G
;
813 case ir_binop_lequal
:
814 return BRW_CONDITIONAL_LE
;
815 case ir_binop_gequal
:
816 return BRW_CONDITIONAL_GE
;
818 case ir_binop_all_equal
: /* same as equal for scalars */
819 return BRW_CONDITIONAL_Z
;
820 case ir_binop_nequal
:
821 case ir_binop_any_nequal
: /* same as nequal for scalars */
822 return BRW_CONDITIONAL_NZ
;
824 assert(!"not reached: bad operation for comparison");
825 return BRW_CONDITIONAL_NZ
;
830 fs_visitor::visit(ir_expression
*ir
)
832 unsigned int operand
;
836 assert(ir
->get_num_operands() <= 2);
838 if (try_emit_saturate(ir
))
841 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
842 ir
->operands
[operand
]->accept(this);
843 if (this->result
.file
== BAD_FILE
) {
845 printf("Failed to get tree for expression operand:\n");
846 ir
->operands
[operand
]->accept(&v
);
849 op
[operand
] = this->result
;
851 /* Matrix expression operands should have been broken down to vector
852 * operations already.
854 assert(!ir
->operands
[operand
]->type
->is_matrix());
855 /* And then those vector operands should have been broken down to scalar.
857 assert(!ir
->operands
[operand
]->type
->is_vector());
860 /* Storage for our result. If our result goes into an assignment, it will
861 * just get copy-propagated out, so no worries.
863 this->result
= fs_reg(this, ir
->type
);
865 switch (ir
->operation
) {
866 case ir_unop_logic_not
:
867 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
868 * ones complement of the whole register, not just bit 0.
870 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1)));
873 op
[0].negate
= !op
[0].negate
;
874 this->result
= op
[0];
878 op
[0].negate
= false;
879 this->result
= op
[0];
882 temp
= fs_reg(this, ir
->type
);
884 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
886 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
887 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
888 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
889 inst
->predicated
= true;
891 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
892 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
893 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
894 inst
->predicated
= true;
898 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
902 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
905 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
909 assert(!"not reached: should be handled by ir_explog_to_explog2");
912 case ir_unop_sin_reduced
:
913 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
916 case ir_unop_cos_reduced
:
917 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
921 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
924 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
928 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
931 assert(!"not reached: should be handled by ir_sub_to_add_neg");
935 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
938 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
941 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
945 case ir_binop_greater
:
946 case ir_binop_lequal
:
947 case ir_binop_gequal
:
949 case ir_binop_all_equal
:
950 case ir_binop_nequal
:
951 case ir_binop_any_nequal
:
953 /* original gen4 does implicit conversion before comparison. */
955 temp
.type
= op
[0].type
;
957 inst
= emit(fs_inst(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]));
958 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
959 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
962 case ir_binop_logic_xor
:
963 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
966 case ir_binop_logic_or
:
967 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
970 case ir_binop_logic_and
:
971 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
976 assert(!"not reached: should be handled by brw_fs_channel_expressions");
980 assert(!"not reached: should be handled by lower_noise");
983 case ir_quadop_vector
:
984 assert(!"not reached: should be handled by lower_quadop_vector");
988 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
992 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
999 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1003 temp
= this->result
;
1004 /* original gen4 does implicit conversion before comparison. */
1006 temp
.type
= op
[0].type
;
1008 inst
= emit(fs_inst(BRW_OPCODE_CMP
, temp
, op
[0], fs_reg(0.0f
)));
1009 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1010 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
,
1011 this->result
, fs_reg(1)));
1015 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
1018 op
[0].negate
= !op
[0].negate
;
1019 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1020 this->result
.negate
= true;
1023 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1026 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
1028 case ir_unop_round_even
:
1029 emit(fs_inst(BRW_OPCODE_RNDE
, this->result
, op
[0]));
1033 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1034 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1036 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1037 inst
->predicated
= true;
1040 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1041 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1043 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1044 inst
->predicated
= true;
1048 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
1051 case ir_unop_bit_not
:
1052 inst
= emit(fs_inst(BRW_OPCODE_NOT
, this->result
, op
[0]));
1054 case ir_binop_bit_and
:
1055 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
1057 case ir_binop_bit_xor
:
1058 inst
= emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
1060 case ir_binop_bit_or
:
1061 inst
= emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
1065 case ir_binop_lshift
:
1066 case ir_binop_rshift
:
1067 assert(!"GLSL 1.30 features unsupported");
1073 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1074 const glsl_type
*type
, bool predicated
)
1076 switch (type
->base_type
) {
1077 case GLSL_TYPE_FLOAT
:
1078 case GLSL_TYPE_UINT
:
1080 case GLSL_TYPE_BOOL
:
1081 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1082 l
.type
= brw_type_for_base_type(type
);
1083 r
.type
= brw_type_for_base_type(type
);
1085 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1086 inst
->predicated
= predicated
;
1092 case GLSL_TYPE_ARRAY
:
1093 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1094 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1098 case GLSL_TYPE_STRUCT
:
1099 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1100 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1105 case GLSL_TYPE_SAMPLER
:
1109 assert(!"not reached");
1115 fs_visitor::visit(ir_assignment
*ir
)
1120 /* FINISHME: arrays on the lhs */
1121 ir
->lhs
->accept(this);
1124 ir
->rhs
->accept(this);
1127 assert(l
.file
!= BAD_FILE
);
1128 assert(r
.file
!= BAD_FILE
);
1130 if (ir
->condition
) {
1131 emit_bool_to_cond_code(ir
->condition
);
1134 if (ir
->lhs
->type
->is_scalar() ||
1135 ir
->lhs
->type
->is_vector()) {
1136 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1137 if (ir
->write_mask
& (1 << i
)) {
1138 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1140 inst
->predicated
= true;
1146 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1151 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1155 bool simd16
= false;
1161 if (ir
->shadow_comparitor
) {
1162 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1163 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1165 coordinate
.reg_offset
++;
1167 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1170 if (ir
->op
== ir_tex
) {
1171 /* There's no plain shadow compare message, so we use shadow
1172 * compare with a bias of 0.0.
1174 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1177 } else if (ir
->op
== ir_txb
) {
1178 ir
->lod_info
.bias
->accept(this);
1179 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1183 assert(ir
->op
== ir_txl
);
1184 ir
->lod_info
.lod
->accept(this);
1185 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1190 ir
->shadow_comparitor
->accept(this);
1191 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1193 } else if (ir
->op
== ir_tex
) {
1194 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1195 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1197 coordinate
.reg_offset
++;
1199 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1202 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1203 * instructions. We'll need to do SIMD16 here.
1205 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1207 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1208 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2),
1210 coordinate
.reg_offset
++;
1213 /* lod/bias appears after u/v/r. */
1216 if (ir
->op
== ir_txb
) {
1217 ir
->lod_info
.bias
->accept(this);
1218 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1222 ir
->lod_info
.lod
->accept(this);
1223 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1228 /* The unused upper half. */
1231 /* Now, since we're doing simd16, the return is 2 interleaved
1232 * vec4s where the odd-indexed ones are junk. We'll need to move
1233 * this weirdness around to the expected layout.
1237 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1239 dst
.type
= BRW_REGISTER_TYPE_F
;
1242 fs_inst
*inst
= NULL
;
1245 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1248 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1251 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1255 assert(!"GLSL 1.30 features unsupported");
1258 inst
->base_mrf
= base_mrf
;
1262 for (int i
= 0; i
< 4; i
++) {
1263 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1264 orig_dst
.reg_offset
++;
1265 dst
.reg_offset
+= 2;
1273 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1275 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1276 * optional parameters like shadow comparitor or LOD bias. If
1277 * optional parameters aren't present, those base slots are
1278 * optional and don't need to be included in the message.
1280 * We don't fill in the unnecessary slots regardless, which may
1281 * look surprising in the disassembly.
1283 int mlen
= 1; /* g0 header always present. */
1286 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1287 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1289 coordinate
.reg_offset
++;
1291 mlen
+= ir
->coordinate
->type
->vector_elements
;
1293 if (ir
->shadow_comparitor
) {
1294 mlen
= MAX2(mlen
, 5);
1296 ir
->shadow_comparitor
->accept(this);
1297 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1301 fs_inst
*inst
= NULL
;
1304 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1307 ir
->lod_info
.bias
->accept(this);
1308 mlen
= MAX2(mlen
, 5);
1309 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1312 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1315 ir
->lod_info
.lod
->accept(this);
1316 mlen
= MAX2(mlen
, 5);
1317 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1320 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1324 assert(!"GLSL 1.30 features unsupported");
1327 inst
->base_mrf
= base_mrf
;
1334 fs_visitor::visit(ir_texture
*ir
)
1337 fs_inst
*inst
= NULL
;
1339 ir
->coordinate
->accept(this);
1340 fs_reg coordinate
= this->result
;
1342 /* Should be lowered by do_lower_texture_projection */
1343 assert(!ir
->projector
);
1345 sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
1346 ctx
->Shader
.CurrentFragmentProgram
,
1347 &brw
->fragment_program
->Base
);
1348 sampler
= c
->fp
->program
.Base
.SamplerUnits
[sampler
];
1350 /* The 965 requires the EU to do the normalization of GL rectangle
1351 * texture coordinates. We use the program parameter state
1352 * tracking to get the scaling factor.
1354 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1355 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1356 int tokens
[STATE_LENGTH
] = {
1358 STATE_TEXRECT_SCALE
,
1364 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
1366 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
+ 1] =
1369 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1370 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1371 GLuint index
= _mesa_add_state_reference(params
,
1372 (gl_state_index
*)tokens
);
1373 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
1375 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[0];
1376 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[1];
1378 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1379 fs_reg src
= coordinate
;
1382 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_x
));
1385 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_y
));
1388 /* Writemasking doesn't eliminate channels on SIMD8 texture
1389 * samples, so don't worry about them.
1391 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1393 if (intel
->gen
< 5) {
1394 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1396 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1399 inst
->sampler
= sampler
;
1403 if (ir
->shadow_comparitor
)
1404 inst
->shadow_compare
= true;
1406 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1407 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1409 for (int i
= 0; i
< 4; i
++) {
1410 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1411 fs_reg l
= swizzle_dst
;
1414 if (swiz
== SWIZZLE_ZERO
) {
1415 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1416 } else if (swiz
== SWIZZLE_ONE
) {
1417 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1420 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1421 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1424 this->result
= swizzle_dst
;
1429 fs_visitor::visit(ir_swizzle
*ir
)
1431 ir
->val
->accept(this);
1432 fs_reg val
= this->result
;
1434 if (ir
->type
->vector_elements
== 1) {
1435 this->result
.reg_offset
+= ir
->mask
.x
;
1439 fs_reg result
= fs_reg(this, ir
->type
);
1440 this->result
= result
;
1442 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1443 fs_reg channel
= val
;
1461 channel
.reg_offset
+= swiz
;
1462 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1463 result
.reg_offset
++;
1468 fs_visitor::visit(ir_discard
*ir
)
1470 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1472 assert(ir
->condition
== NULL
); /* FINISHME */
1474 emit(fs_inst(FS_OPCODE_DISCARD_NOT
, temp
, reg_null_d
));
1475 emit(fs_inst(FS_OPCODE_DISCARD_AND
, reg_null_d
, temp
));
1476 kill_emitted
= true;
1480 fs_visitor::visit(ir_constant
*ir
)
1482 /* Set this->result to reg at the bottom of the function because some code
1483 * paths will cause this visitor to be applied to other fields. This will
1484 * cause the value stored in this->result to be modified.
1486 * Make reg constant so that it doesn't get accidentally modified along the
1487 * way. Yes, I actually had this problem. :(
1489 const fs_reg
reg(this, ir
->type
);
1490 fs_reg dst_reg
= reg
;
1492 if (ir
->type
->is_array()) {
1493 const unsigned size
= type_size(ir
->type
->fields
.array
);
1495 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1496 ir
->array_elements
[i
]->accept(this);
1497 fs_reg src_reg
= this->result
;
1499 dst_reg
.type
= src_reg
.type
;
1500 for (unsigned j
= 0; j
< size
; j
++) {
1501 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, src_reg
));
1502 src_reg
.reg_offset
++;
1503 dst_reg
.reg_offset
++;
1506 } else if (ir
->type
->is_record()) {
1507 foreach_list(node
, &ir
->components
) {
1508 ir_instruction
*const field
= (ir_instruction
*) node
;
1509 const unsigned size
= type_size(field
->type
);
1511 field
->accept(this);
1512 fs_reg src_reg
= this->result
;
1514 dst_reg
.type
= src_reg
.type
;
1515 for (unsigned j
= 0; j
< size
; j
++) {
1516 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, src_reg
));
1517 src_reg
.reg_offset
++;
1518 dst_reg
.reg_offset
++;
1522 const unsigned size
= type_size(ir
->type
);
1524 for (unsigned i
= 0; i
< size
; i
++) {
1525 switch (ir
->type
->base_type
) {
1526 case GLSL_TYPE_FLOAT
:
1527 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.f
[i
])));
1529 case GLSL_TYPE_UINT
:
1530 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.u
[i
])));
1533 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.i
[i
])));
1535 case GLSL_TYPE_BOOL
:
1536 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg((int)ir
->value
.b
[i
])));
1539 assert(!"Non-float/uint/int/bool constant");
1541 dst_reg
.reg_offset
++;
1549 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1551 ir_expression
*expr
= ir
->as_expression();
1557 assert(expr
->get_num_operands() <= 2);
1558 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1559 assert(expr
->operands
[i
]->type
->is_scalar());
1561 expr
->operands
[i
]->accept(this);
1562 op
[i
] = this->result
;
1565 switch (expr
->operation
) {
1566 case ir_unop_logic_not
:
1567 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1)));
1568 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1571 case ir_binop_logic_xor
:
1572 inst
= emit(fs_inst(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]));
1573 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1576 case ir_binop_logic_or
:
1577 inst
= emit(fs_inst(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]));
1578 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1581 case ir_binop_logic_and
:
1582 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]));
1583 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1587 if (intel
->gen
>= 6) {
1588 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1589 op
[0], fs_reg(0.0f
)));
1591 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_f
, op
[0]));
1593 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1597 if (intel
->gen
>= 6) {
1598 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0)));
1600 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1602 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1605 case ir_binop_greater
:
1606 case ir_binop_gequal
:
1608 case ir_binop_lequal
:
1609 case ir_binop_equal
:
1610 case ir_binop_all_equal
:
1611 case ir_binop_nequal
:
1612 case ir_binop_any_nequal
:
1613 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_cmp
, op
[0], op
[1]));
1614 inst
->conditional_mod
=
1615 brw_conditional_for_comparison(expr
->operation
);
1619 assert(!"not reached");
1628 if (intel
->gen
>= 6) {
1629 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
,
1630 this->result
, fs_reg(1)));
1631 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1633 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, this->result
));
1634 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1639 * Emit a gen6 IF statement with the comparison folded into the IF
1643 fs_visitor::emit_if_gen6(ir_if
*ir
)
1645 ir_expression
*expr
= ir
->condition
->as_expression();
1652 assert(expr
->get_num_operands() <= 2);
1653 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1654 assert(expr
->operands
[i
]->type
->is_scalar());
1656 expr
->operands
[i
]->accept(this);
1657 op
[i
] = this->result
;
1660 switch (expr
->operation
) {
1661 case ir_unop_logic_not
:
1662 inst
= emit(fs_inst(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(0)));
1663 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1666 case ir_binop_logic_xor
:
1667 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1668 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1671 case ir_binop_logic_or
:
1672 temp
= fs_reg(this, glsl_type::bool_type
);
1673 emit(fs_inst(BRW_OPCODE_OR
, temp
, op
[0], op
[1]));
1674 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1675 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1678 case ir_binop_logic_and
:
1679 temp
= fs_reg(this, glsl_type::bool_type
);
1680 emit(fs_inst(BRW_OPCODE_AND
, temp
, op
[0], op
[1]));
1681 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1682 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1686 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0)));
1687 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1691 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1692 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1695 case ir_binop_greater
:
1696 case ir_binop_gequal
:
1698 case ir_binop_lequal
:
1699 case ir_binop_equal
:
1700 case ir_binop_all_equal
:
1701 case ir_binop_nequal
:
1702 case ir_binop_any_nequal
:
1703 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1704 inst
->conditional_mod
=
1705 brw_conditional_for_comparison(expr
->operation
);
1708 assert(!"not reached");
1709 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1710 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1717 ir
->condition
->accept(this);
1719 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0)));
1720 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1724 fs_visitor::visit(ir_if
*ir
)
1728 /* Don't point the annotation at the if statement, because then it plus
1729 * the then and else blocks get printed.
1731 this->base_ir
= ir
->condition
;
1733 if (intel
->gen
>= 6) {
1736 emit_bool_to_cond_code(ir
->condition
);
1738 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1739 inst
->predicated
= true;
1742 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1743 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1749 if (!ir
->else_instructions
.is_empty()) {
1750 emit(fs_inst(BRW_OPCODE_ELSE
));
1752 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1753 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1760 emit(fs_inst(BRW_OPCODE_ENDIF
));
1764 fs_visitor::visit(ir_loop
*ir
)
1766 fs_reg counter
= reg_undef
;
1769 this->base_ir
= ir
->counter
;
1770 ir
->counter
->accept(this);
1771 counter
= *(variable_storage(ir
->counter
));
1774 this->base_ir
= ir
->from
;
1775 ir
->from
->accept(this);
1777 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1781 emit(fs_inst(BRW_OPCODE_DO
));
1784 this->base_ir
= ir
->to
;
1785 ir
->to
->accept(this);
1787 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_cmp
,
1788 counter
, this->result
));
1789 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->cmp
);
1791 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1792 inst
->predicated
= true;
1795 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1796 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1802 if (ir
->increment
) {
1803 this->base_ir
= ir
->increment
;
1804 ir
->increment
->accept(this);
1805 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1808 emit(fs_inst(BRW_OPCODE_WHILE
));
1812 fs_visitor::visit(ir_loop_jump
*ir
)
1815 case ir_loop_jump::jump_break
:
1816 emit(fs_inst(BRW_OPCODE_BREAK
));
1818 case ir_loop_jump::jump_continue
:
1819 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1825 fs_visitor::visit(ir_call
*ir
)
1827 assert(!"FINISHME");
1831 fs_visitor::visit(ir_return
*ir
)
1833 assert(!"FINISHME");
1837 fs_visitor::visit(ir_function
*ir
)
1839 /* Ignore function bodies other than main() -- we shouldn't see calls to
1840 * them since they should all be inlined before we get to ir_to_mesa.
1842 if (strcmp(ir
->name
, "main") == 0) {
1843 const ir_function_signature
*sig
;
1846 sig
= ir
->matching_signature(&empty
);
1850 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1851 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1860 fs_visitor::visit(ir_function_signature
*ir
)
1862 assert(!"not reached");
1867 fs_visitor::emit(fs_inst inst
)
1869 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1872 list_inst
->annotation
= this->current_annotation
;
1873 list_inst
->ir
= this->base_ir
;
1875 this->instructions
.push_tail(list_inst
);
1880 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1882 fs_visitor::emit_dummy_fs()
1884 /* Everyone's favorite color. */
1885 emit(fs_inst(BRW_OPCODE_MOV
,
1888 emit(fs_inst(BRW_OPCODE_MOV
,
1891 emit(fs_inst(BRW_OPCODE_MOV
,
1894 emit(fs_inst(BRW_OPCODE_MOV
,
1899 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1902 write
->base_mrf
= 0;
1905 /* The register location here is relative to the start of the URB
1906 * data. It will get adjusted to be a real location before
1907 * generate_code() time.
1910 fs_visitor::interp_reg(int location
, int channel
)
1912 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1913 int stride
= (channel
& 1) * 4;
1915 assert(urb_setup
[location
] != -1);
1917 return brw_vec1_grf(regnr
, stride
);
1920 /** Emits the interpolation for the varying inputs. */
1922 fs_visitor::emit_interpolation_setup_gen4()
1924 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1926 this->current_annotation
= "compute pixel centers";
1927 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1928 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1929 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1930 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1931 emit(fs_inst(BRW_OPCODE_ADD
,
1933 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1934 fs_reg(brw_imm_v(0x10101010))));
1935 emit(fs_inst(BRW_OPCODE_ADD
,
1937 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1938 fs_reg(brw_imm_v(0x11001100))));
1940 this->current_annotation
= "compute pixel deltas from v0";
1942 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1943 this->delta_y
= this->delta_x
;
1944 this->delta_y
.reg_offset
++;
1946 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1947 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1949 emit(fs_inst(BRW_OPCODE_ADD
,
1952 fs_reg(negate(brw_vec1_grf(1, 0)))));
1953 emit(fs_inst(BRW_OPCODE_ADD
,
1956 fs_reg(negate(brw_vec1_grf(1, 1)))));
1958 this->current_annotation
= "compute pos.w and 1/pos.w";
1959 /* Compute wpos.w. It's always in our setup, since it's needed to
1960 * interpolate the other attributes.
1962 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1963 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1964 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1965 /* Compute the pixel 1/W value from wpos.w. */
1966 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1967 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1968 this->current_annotation
= NULL
;
1971 /** Emits the interpolation for the varying inputs. */
1973 fs_visitor::emit_interpolation_setup_gen6()
1975 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1977 /* If the pixel centers end up used, the setup is the same as for gen4. */
1978 this->current_annotation
= "compute pixel centers";
1979 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1980 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1981 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1982 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1983 emit(fs_inst(BRW_OPCODE_ADD
,
1985 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1986 fs_reg(brw_imm_v(0x10101010))));
1987 emit(fs_inst(BRW_OPCODE_ADD
,
1989 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1990 fs_reg(brw_imm_v(0x11001100))));
1992 /* As of gen6, we can no longer mix float and int sources. We have
1993 * to turn the integer pixel centers into floats for their actual
1996 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1997 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1998 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
));
1999 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
));
2001 this->current_annotation
= "compute 1/pos.w";
2002 this->wpos_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
2003 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
2004 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
2006 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
2007 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
2009 this->current_annotation
= NULL
;
2013 fs_visitor::emit_fb_writes()
2015 this->current_annotation
= "FB write header";
2016 GLboolean header_present
= GL_TRUE
;
2019 if (intel
->gen
>= 6 &&
2020 !this->kill_emitted
&&
2021 c
->key
.nr_color_regions
== 1) {
2022 header_present
= false;
2025 if (header_present
) {
2030 if (c
->aa_dest_stencil_reg
) {
2031 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2032 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0))));
2035 /* Reserve space for color. It'll be filled in per MRT below. */
2039 if (c
->source_depth_to_render_target
) {
2040 if (c
->computes_depth
) {
2041 /* Hand over gl_FragDepth. */
2042 assert(this->frag_depth
);
2043 fs_reg depth
= *(variable_storage(this->frag_depth
));
2045 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
2047 /* Pass through the payload depth. */
2048 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2049 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
2053 if (c
->dest_depth_reg
) {
2054 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2055 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0))));
2058 fs_reg color
= reg_undef
;
2059 if (this->frag_color
)
2060 color
= *(variable_storage(this->frag_color
));
2061 else if (this->frag_data
) {
2062 color
= *(variable_storage(this->frag_data
));
2063 color
.type
= BRW_REGISTER_TYPE_F
;
2066 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2067 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
2068 "FB write target %d",
2070 if (this->frag_color
|| this->frag_data
) {
2071 for (int i
= 0; i
< 4; i
++) {
2072 emit(fs_inst(BRW_OPCODE_MOV
,
2073 fs_reg(MRF
, color_mrf
+ i
),
2079 if (this->frag_color
)
2080 color
.reg_offset
-= 4;
2082 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
2083 reg_undef
, reg_undef
));
2084 inst
->target
= target
;
2087 if (target
== c
->key
.nr_color_regions
- 1)
2089 inst
->header_present
= header_present
;
2092 if (c
->key
.nr_color_regions
== 0) {
2093 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
2094 reg_undef
, reg_undef
));
2098 inst
->header_present
= header_present
;
2101 this->current_annotation
= NULL
;
2105 fs_visitor::generate_fb_write(fs_inst
*inst
)
2107 GLboolean eot
= inst
->eot
;
2108 struct brw_reg implied_header
;
2110 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
2113 brw_push_insn_state(p
);
2114 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2115 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2117 if (inst
->header_present
) {
2118 if (intel
->gen
>= 6) {
2120 brw_message_reg(inst
->base_mrf
),
2121 brw_vec8_grf(0, 0));
2123 if (inst
->target
> 0) {
2124 /* Set the render target index for choosing BLEND_STATE. */
2125 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 2),
2126 BRW_REGISTER_TYPE_UD
),
2127 brw_imm_ud(inst
->target
));
2130 /* Clear viewport index, render target array index. */
2131 brw_AND(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 0),
2132 BRW_REGISTER_TYPE_UD
),
2133 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2134 brw_imm_ud(0xf7ff));
2136 implied_header
= brw_null_reg();
2138 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2142 brw_message_reg(inst
->base_mrf
+ 1),
2143 brw_vec8_grf(1, 0));
2145 implied_header
= brw_null_reg();
2148 brw_pop_insn_state(p
);
2151 8, /* dispatch_width */
2152 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
2159 inst
->header_present
);
2163 fs_visitor::generate_linterp(fs_inst
*inst
,
2164 struct brw_reg dst
, struct brw_reg
*src
)
2166 struct brw_reg delta_x
= src
[0];
2167 struct brw_reg delta_y
= src
[1];
2168 struct brw_reg interp
= src
[2];
2171 delta_y
.nr
== delta_x
.nr
+ 1 &&
2172 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2173 brw_PLN(p
, dst
, interp
, delta_x
);
2175 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2176 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2181 fs_visitor::generate_math(fs_inst
*inst
,
2182 struct brw_reg dst
, struct brw_reg
*src
)
2186 switch (inst
->opcode
) {
2188 op
= BRW_MATH_FUNCTION_INV
;
2191 op
= BRW_MATH_FUNCTION_RSQ
;
2193 case FS_OPCODE_SQRT
:
2194 op
= BRW_MATH_FUNCTION_SQRT
;
2196 case FS_OPCODE_EXP2
:
2197 op
= BRW_MATH_FUNCTION_EXP
;
2199 case FS_OPCODE_LOG2
:
2200 op
= BRW_MATH_FUNCTION_LOG
;
2203 op
= BRW_MATH_FUNCTION_POW
;
2206 op
= BRW_MATH_FUNCTION_SIN
;
2209 op
= BRW_MATH_FUNCTION_COS
;
2212 assert(!"not reached: unknown math function");
2217 if (intel
->gen
>= 6) {
2218 assert(inst
->mlen
== 0);
2220 if (inst
->opcode
== FS_OPCODE_POW
) {
2221 brw_math2(p
, dst
, op
, src
[0], src
[1]);
2225 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2226 BRW_MATH_SATURATE_NONE
,
2228 BRW_MATH_DATA_VECTOR
,
2229 BRW_MATH_PRECISION_FULL
);
2232 assert(inst
->mlen
>= 1);
2236 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2237 BRW_MATH_SATURATE_NONE
,
2238 inst
->base_mrf
, src
[0],
2239 BRW_MATH_DATA_VECTOR
,
2240 BRW_MATH_PRECISION_FULL
);
2245 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
)
2249 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2251 if (intel
->gen
>= 5) {
2252 switch (inst
->opcode
) {
2254 if (inst
->shadow_compare
) {
2255 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2257 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2261 if (inst
->shadow_compare
) {
2262 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2264 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2269 switch (inst
->opcode
) {
2271 /* Note that G45 and older determines shadow compare and dispatch width
2272 * from message length for most messages.
2274 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2275 if (inst
->shadow_compare
) {
2276 assert(inst
->mlen
== 6);
2278 assert(inst
->mlen
<= 4);
2282 if (inst
->shadow_compare
) {
2283 assert(inst
->mlen
== 6);
2284 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2286 assert(inst
->mlen
== 9);
2287 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2288 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2293 assert(msg_type
!= -1);
2295 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2301 retype(dst
, BRW_REGISTER_TYPE_UW
),
2303 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2304 SURF_INDEX_TEXTURE(inst
->sampler
),
2316 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2319 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2321 * and we're trying to produce:
2324 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2325 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2326 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2327 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2328 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2329 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2330 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2331 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2333 * and add another set of two more subspans if in 16-pixel dispatch mode.
2335 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2336 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2337 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2338 * between each other. We could probably do it like ddx and swizzle the right
2339 * order later, but bail for now and just produce
2340 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2343 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2345 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2346 BRW_REGISTER_TYPE_F
,
2347 BRW_VERTICAL_STRIDE_2
,
2349 BRW_HORIZONTAL_STRIDE_0
,
2350 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2351 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2352 BRW_REGISTER_TYPE_F
,
2353 BRW_VERTICAL_STRIDE_2
,
2355 BRW_HORIZONTAL_STRIDE_0
,
2356 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2357 brw_ADD(p
, dst
, src0
, negate(src1
));
2361 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2363 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2364 BRW_REGISTER_TYPE_F
,
2365 BRW_VERTICAL_STRIDE_4
,
2367 BRW_HORIZONTAL_STRIDE_0
,
2368 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2369 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2370 BRW_REGISTER_TYPE_F
,
2371 BRW_VERTICAL_STRIDE_4
,
2373 BRW_HORIZONTAL_STRIDE_0
,
2374 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2375 brw_ADD(p
, dst
, src0
, negate(src1
));
2379 fs_visitor::generate_discard_not(fs_inst
*inst
, struct brw_reg mask
)
2381 if (intel
->gen
>= 6) {
2382 /* Gen6 no longer has the mask reg for us to just read the
2383 * active channels from. However, cmp updates just the channels
2384 * of the flag reg that are enabled, so we can get at the
2385 * channel enables that way. In this step, make a reg of ones
2388 brw_MOV(p
, mask
, brw_imm_ud(1));
2390 brw_push_insn_state(p
);
2391 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2392 brw_NOT(p
, mask
, brw_mask_reg(1)); /* IMASK */
2393 brw_pop_insn_state(p
);
2398 fs_visitor::generate_discard_and(fs_inst
*inst
, struct brw_reg mask
)
2400 if (intel
->gen
>= 6) {
2401 struct brw_reg f0
= brw_flag_reg();
2402 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
2404 brw_push_insn_state(p
);
2405 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2406 brw_MOV(p
, f0
, brw_imm_uw(0xffff)); /* inactive channels undiscarded */
2407 brw_pop_insn_state(p
);
2409 brw_CMP(p
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
2410 BRW_CONDITIONAL_Z
, mask
, brw_imm_ud(0)); /* active channels fail test */
2411 /* Undo CMP's whacking of predication*/
2412 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2414 brw_push_insn_state(p
);
2415 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2416 brw_AND(p
, g1
, f0
, g1
);
2417 brw_pop_insn_state(p
);
2419 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2421 mask
= brw_uw1_reg(mask
.file
, mask
.nr
, 0);
2423 brw_push_insn_state(p
);
2424 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2425 brw_AND(p
, g0
, mask
, g0
);
2426 brw_pop_insn_state(p
);
2431 fs_visitor::generate_spill(fs_inst
*inst
, struct brw_reg src
)
2433 assert(inst
->mlen
!= 0);
2436 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
2437 retype(src
, BRW_REGISTER_TYPE_UD
));
2438 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
), 1,
2443 fs_visitor::generate_unspill(fs_inst
*inst
, struct brw_reg dst
)
2445 assert(inst
->mlen
!= 0);
2447 /* Clear any post destination dependencies that would be ignored by
2448 * the block read. See the B-Spec for pre-gen5 send instruction.
2450 * This could use a better solution, since texture sampling and
2451 * math reads could potentially run into it as well -- anywhere
2452 * that we have a SEND with a destination that is a register that
2453 * was written but not read within the last N instructions (what's
2454 * N? unsure). This is rare because of dead code elimination, but
2457 if (intel
->gen
== 4 && !intel
->is_g4x
)
2458 brw_MOV(p
, brw_null_reg(), dst
);
2460 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
), 1,
2463 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2464 /* gen4 errata: destination from a send can't be used as a
2465 * destination until it's been read. Just read it so we don't
2468 brw_MOV(p
, brw_null_reg(), dst
);
2474 fs_visitor::generate_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
)
2476 assert(inst
->mlen
!= 0);
2478 /* Clear any post destination dependencies that would be ignored by
2479 * the block read. See the B-Spec for pre-gen5 send instruction.
2481 * This could use a better solution, since texture sampling and
2482 * math reads could potentially run into it as well -- anywhere
2483 * that we have a SEND with a destination that is a register that
2484 * was written but not read within the last N instructions (what's
2485 * N? unsure). This is rare because of dead code elimination, but
2488 if (intel
->gen
== 4 && !intel
->is_g4x
)
2489 brw_MOV(p
, brw_null_reg(), dst
);
2491 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
2492 inst
->offset
, SURF_INDEX_FRAG_CONST_BUFFER
);
2494 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2495 /* gen4 errata: destination from a send can't be used as a
2496 * destination until it's been read. Just read it so we don't
2499 brw_MOV(p
, brw_null_reg(), dst
);
2504 fs_visitor::assign_curb_setup()
2506 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
2507 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2509 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2510 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2511 fs_inst
*inst
= (fs_inst
*)iter
.get();
2513 for (unsigned int i
= 0; i
< 3; i
++) {
2514 if (inst
->src
[i
].file
== UNIFORM
) {
2515 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2516 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2520 inst
->src
[i
].file
= FIXED_HW_REG
;
2521 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
2528 fs_visitor::calculate_urb_setup()
2530 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2535 /* Figure out where each of the incoming setup attributes lands. */
2536 if (intel
->gen
>= 6) {
2537 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2538 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2539 urb_setup
[i
] = urb_next
++;
2543 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2544 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2545 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2548 if (i
>= VERT_RESULT_VAR0
)
2549 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2550 else if (i
<= VERT_RESULT_TEX7
)
2556 urb_setup
[fp_index
] = urb_next
++;
2561 /* Each attribute is 4 setup channels, each of which is half a reg. */
2562 c
->prog_data
.urb_read_length
= urb_next
* 2;
2566 fs_visitor::assign_urb_setup()
2568 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2570 /* Offset all the urb_setup[] index by the actual position of the
2571 * setup regs, now that the location of the constants has been chosen.
2573 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2574 fs_inst
*inst
= (fs_inst
*)iter
.get();
2576 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
2577 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2578 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2581 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
2582 assert(inst
->src
[0].file
== FIXED_HW_REG
);
2583 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
2587 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2591 * Split large virtual GRFs into separate components if we can.
2593 * This is mostly duplicated with what brw_fs_vector_splitting does,
2594 * but that's really conservative because it's afraid of doing
2595 * splitting that doesn't result in real progress after the rest of
2596 * the optimization phases, which would cause infinite looping in
2597 * optimization. We can do it once here, safely. This also has the
2598 * opportunity to split interpolated values, or maybe even uniforms,
2599 * which we don't have at the IR level.
2601 * We want to split, because virtual GRFs are what we register
2602 * allocate and spill (due to contiguousness requirements for some
2603 * instructions), and they're what we naturally generate in the
2604 * codegen process, but most virtual GRFs don't actually need to be
2605 * contiguous sets of GRFs. If we split, we'll end up with reduced
2606 * live intervals and better dead code elimination and coalescing.
2609 fs_visitor::split_virtual_grfs()
2611 int num_vars
= this->virtual_grf_next
;
2612 bool split_grf
[num_vars
];
2613 int new_virtual_grf
[num_vars
];
2615 /* Try to split anything > 0 sized. */
2616 for (int i
= 0; i
< num_vars
; i
++) {
2617 if (this->virtual_grf_sizes
[i
] != 1)
2618 split_grf
[i
] = true;
2620 split_grf
[i
] = false;
2624 /* PLN opcodes rely on the delta_xy being contiguous. */
2625 split_grf
[this->delta_x
.reg
] = false;
2628 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2629 fs_inst
*inst
= (fs_inst
*)iter
.get();
2631 /* Texturing produces 4 contiguous registers, so no splitting. */
2632 if ((inst
->opcode
== FS_OPCODE_TEX
||
2633 inst
->opcode
== FS_OPCODE_TXB
||
2634 inst
->opcode
== FS_OPCODE_TXL
) &&
2635 inst
->dst
.file
== GRF
) {
2636 split_grf
[inst
->dst
.reg
] = false;
2640 /* Allocate new space for split regs. Note that the virtual
2641 * numbers will be contiguous.
2643 for (int i
= 0; i
< num_vars
; i
++) {
2645 new_virtual_grf
[i
] = virtual_grf_alloc(1);
2646 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
2647 int reg
= virtual_grf_alloc(1);
2648 assert(reg
== new_virtual_grf
[i
] + j
- 1);
2651 this->virtual_grf_sizes
[i
] = 1;
2655 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2656 fs_inst
*inst
= (fs_inst
*)iter
.get();
2658 if (inst
->dst
.file
== GRF
&&
2659 split_grf
[inst
->dst
.reg
] &&
2660 inst
->dst
.reg_offset
!= 0) {
2661 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
2662 inst
->dst
.reg_offset
- 1);
2663 inst
->dst
.reg_offset
= 0;
2665 for (int i
= 0; i
< 3; i
++) {
2666 if (inst
->src
[i
].file
== GRF
&&
2667 split_grf
[inst
->src
[i
].reg
] &&
2668 inst
->src
[i
].reg_offset
!= 0) {
2669 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
2670 inst
->src
[i
].reg_offset
- 1);
2671 inst
->src
[i
].reg_offset
= 0;
2675 this->live_intervals_valid
= false;
2679 * Choose accesses from the UNIFORM file to demote to using the pull
2682 * We allow a fragment shader to have more than the specified minimum
2683 * maximum number of fragment shader uniform components (64). If
2684 * there are too many of these, they'd fill up all of register space.
2685 * So, this will push some of them out to the pull constant buffer and
2686 * update the program to load them.
2689 fs_visitor::setup_pull_constants()
2691 /* Only allow 16 registers (128 uniform components) as push constants. */
2692 unsigned int max_uniform_components
= 16 * 8;
2693 if (c
->prog_data
.nr_params
<= max_uniform_components
)
2696 /* Just demote the end of the list. We could probably do better
2697 * here, demoting things that are rarely used in the program first.
2699 int pull_uniform_base
= max_uniform_components
;
2700 int pull_uniform_count
= c
->prog_data
.nr_params
- pull_uniform_base
;
2702 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2703 fs_inst
*inst
= (fs_inst
*)iter
.get();
2705 for (int i
= 0; i
< 3; i
++) {
2706 if (inst
->src
[i
].file
!= UNIFORM
)
2709 int uniform_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2710 if (uniform_nr
< pull_uniform_base
)
2713 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
2714 fs_inst
*pull
= new(mem_ctx
) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
2716 pull
->offset
= ((uniform_nr
- pull_uniform_base
) * 4) & ~15;
2717 pull
->ir
= inst
->ir
;
2718 pull
->annotation
= inst
->annotation
;
2719 pull
->base_mrf
= 14;
2722 inst
->insert_before(pull
);
2724 inst
->src
[i
].file
= GRF
;
2725 inst
->src
[i
].reg
= dst
.reg
;
2726 inst
->src
[i
].reg_offset
= 0;
2727 inst
->src
[i
].smear
= (uniform_nr
- pull_uniform_base
) & 3;
2731 for (int i
= 0; i
< pull_uniform_count
; i
++) {
2732 c
->prog_data
.pull_param
[i
] = c
->prog_data
.param
[pull_uniform_base
+ i
];
2733 c
->prog_data
.pull_param_convert
[i
] =
2734 c
->prog_data
.param_convert
[pull_uniform_base
+ i
];
2736 c
->prog_data
.nr_params
-= pull_uniform_count
;
2737 c
->prog_data
.nr_pull_params
= pull_uniform_count
;
2741 fs_visitor::calculate_live_intervals()
2743 int num_vars
= this->virtual_grf_next
;
2744 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2745 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2748 int bb_header_ip
= 0;
2750 if (this->live_intervals_valid
)
2753 for (int i
= 0; i
< num_vars
; i
++) {
2754 def
[i
] = MAX_INSTRUCTION
;
2759 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2760 fs_inst
*inst
= (fs_inst
*)iter
.get();
2762 if (inst
->opcode
== BRW_OPCODE_DO
) {
2763 if (loop_depth
++ == 0)
2765 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2768 if (loop_depth
== 0) {
2769 /* Patches up the use of vars marked for being live across
2772 for (int i
= 0; i
< num_vars
; i
++) {
2773 if (use
[i
] == loop_start
) {
2779 for (unsigned int i
= 0; i
< 3; i
++) {
2780 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2781 int reg
= inst
->src
[i
].reg
;
2783 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2784 def
[reg
] >= bb_header_ip
)) {
2787 def
[reg
] = MIN2(loop_start
, def
[reg
]);
2788 use
[reg
] = loop_start
;
2790 /* Nobody else is going to go smash our start to
2791 * later in the loop now, because def[reg] now
2792 * points before the bb header.
2797 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2798 int reg
= inst
->dst
.reg
;
2800 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2801 !inst
->predicated
)) {
2802 def
[reg
] = MIN2(def
[reg
], ip
);
2804 def
[reg
] = MIN2(def
[reg
], loop_start
);
2811 /* Set the basic block header IP. This is used for determining
2812 * if a complete def of single-register virtual GRF in a loop
2813 * dominates a use in the same basic block. It's a quick way to
2814 * reduce the live interval range of most register used in a
2817 if (inst
->opcode
== BRW_OPCODE_IF
||
2818 inst
->opcode
== BRW_OPCODE_ELSE
||
2819 inst
->opcode
== BRW_OPCODE_ENDIF
||
2820 inst
->opcode
== BRW_OPCODE_DO
||
2821 inst
->opcode
== BRW_OPCODE_WHILE
||
2822 inst
->opcode
== BRW_OPCODE_BREAK
||
2823 inst
->opcode
== BRW_OPCODE_CONTINUE
) {
2828 talloc_free(this->virtual_grf_def
);
2829 talloc_free(this->virtual_grf_use
);
2830 this->virtual_grf_def
= def
;
2831 this->virtual_grf_use
= use
;
2833 this->live_intervals_valid
= true;
2837 * Attempts to move immediate constants into the immediate
2838 * constant slot of following instructions.
2840 * Immediate constants are a bit tricky -- they have to be in the last
2841 * operand slot, you can't do abs/negate on them,
2845 fs_visitor::propagate_constants()
2847 bool progress
= false;
2849 calculate_live_intervals();
2851 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2852 fs_inst
*inst
= (fs_inst
*)iter
.get();
2854 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2856 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2857 inst
->dst
.type
!= inst
->src
[0].type
)
2860 /* Don't bother with cases where we should have had the
2861 * operation on the constant folded in GLSL already.
2866 /* Found a move of a constant to a GRF. Find anything else using the GRF
2867 * before it's written, and replace it with the constant if we can.
2869 exec_list_iterator scan_iter
= iter
;
2871 for (; scan_iter
.has_next(); scan_iter
.next()) {
2872 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2874 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2875 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2876 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2877 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2881 for (int i
= 2; i
>= 0; i
--) {
2882 if (scan_inst
->src
[i
].file
!= GRF
||
2883 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2884 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2887 /* Don't bother with cases where we should have had the
2888 * operation on the constant folded in GLSL already.
2890 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2893 switch (scan_inst
->opcode
) {
2894 case BRW_OPCODE_MOV
:
2895 scan_inst
->src
[i
] = inst
->src
[0];
2899 case BRW_OPCODE_MUL
:
2900 case BRW_OPCODE_ADD
:
2902 scan_inst
->src
[i
] = inst
->src
[0];
2904 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2905 /* Fit this constant in by commuting the operands */
2906 scan_inst
->src
[0] = scan_inst
->src
[1];
2907 scan_inst
->src
[1] = inst
->src
[0];
2911 case BRW_OPCODE_CMP
:
2912 case BRW_OPCODE_SEL
:
2914 scan_inst
->src
[i
] = inst
->src
[0];
2920 if (scan_inst
->dst
.file
== GRF
&&
2921 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2922 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2923 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2930 this->live_intervals_valid
= false;
2935 * Must be called after calculate_live_intervales() to remove unused
2936 * writes to registers -- register allocation will fail otherwise
2937 * because something deffed but not used won't be considered to
2938 * interfere with other regs.
2941 fs_visitor::dead_code_eliminate()
2943 bool progress
= false;
2946 calculate_live_intervals();
2948 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2949 fs_inst
*inst
= (fs_inst
*)iter
.get();
2951 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
2960 live_intervals_valid
= false;
2966 fs_visitor::register_coalesce()
2968 bool progress
= false;
2972 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2973 fs_inst
*inst
= (fs_inst
*)iter
.get();
2975 /* Make sure that we dominate the instructions we're going to
2976 * scan for interfering with our coalescing, or we won't have
2977 * scanned enough to see if anything interferes with our
2978 * coalescing. We don't dominate the following instructions if
2979 * we're in a loop or an if block.
2981 switch (inst
->opcode
) {
2985 case BRW_OPCODE_WHILE
:
2991 case BRW_OPCODE_ENDIF
:
2995 if (loop_depth
|| if_depth
)
2998 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3001 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
3002 inst
->dst
.type
!= inst
->src
[0].type
)
3005 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
3006 * them: check for no writes to either one until the exit of the
3009 bool interfered
= false;
3010 exec_list_iterator scan_iter
= iter
;
3012 for (; scan_iter
.has_next(); scan_iter
.next()) {
3013 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
3015 if (scan_inst
->dst
.file
== GRF
) {
3016 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
3017 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
3018 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
3022 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
3023 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
3024 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
3034 /* Rewrite the later usage to point at the source of the move to
3037 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
3039 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
3041 for (int i
= 0; i
< 3; i
++) {
3042 if (scan_inst
->src
[i
].file
== GRF
&&
3043 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
3044 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
3045 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
3046 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
3047 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
3048 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
3049 scan_inst
->src
[i
].smear
= inst
->src
[0].smear
;
3059 live_intervals_valid
= false;
3066 fs_visitor::compute_to_mrf()
3068 bool progress
= false;
3071 calculate_live_intervals();
3073 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3074 fs_inst
*inst
= (fs_inst
*)iter
.get();
3079 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3081 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
3082 inst
->dst
.type
!= inst
->src
[0].type
||
3083 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
3086 /* Can't compute-to-MRF this GRF if someone else was going to
3089 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
3092 /* Found a move of a GRF to a MRF. Let's see if we can go
3093 * rewrite the thing that made this GRF to write into the MRF.
3096 for (scan_inst
= (fs_inst
*)inst
->prev
;
3097 scan_inst
->prev
!= NULL
;
3098 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
3099 if (scan_inst
->dst
.file
== GRF
&&
3100 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
3101 /* Found the last thing to write our reg we want to turn
3102 * into a compute-to-MRF.
3105 if (scan_inst
->opcode
== FS_OPCODE_TEX
) {
3106 /* texturing writes several continuous regs, so we can't
3107 * compute-to-mrf that.
3112 /* If it's predicated, it (probably) didn't populate all
3115 if (scan_inst
->predicated
)
3118 /* SEND instructions can't have MRF as a destination. */
3119 if (scan_inst
->mlen
)
3122 if (intel
->gen
>= 6) {
3123 /* gen6 math instructions must have the destination be
3124 * GRF, so no compute-to-MRF for them.
3126 if (scan_inst
->opcode
== FS_OPCODE_RCP
||
3127 scan_inst
->opcode
== FS_OPCODE_RSQ
||
3128 scan_inst
->opcode
== FS_OPCODE_SQRT
||
3129 scan_inst
->opcode
== FS_OPCODE_EXP2
||
3130 scan_inst
->opcode
== FS_OPCODE_LOG2
||
3131 scan_inst
->opcode
== FS_OPCODE_SIN
||
3132 scan_inst
->opcode
== FS_OPCODE_COS
||
3133 scan_inst
->opcode
== FS_OPCODE_POW
) {
3138 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
3139 /* Found the creator of our MRF's source value. */
3140 scan_inst
->dst
.file
= MRF
;
3141 scan_inst
->dst
.hw_reg
= inst
->dst
.hw_reg
;
3142 scan_inst
->saturate
|= inst
->saturate
;
3149 /* We don't handle flow control here. Most computation of
3150 * values that end up in MRFs are shortly before the MRF
3153 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
3154 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
3155 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
3159 /* You can't read from an MRF, so if someone else reads our
3160 * MRF's source GRF that we wanted to rewrite, that stops us.
3162 bool interfered
= false;
3163 for (int i
= 0; i
< 3; i
++) {
3164 if (scan_inst
->src
[i
].file
== GRF
&&
3165 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
3166 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
3173 if (scan_inst
->dst
.file
== MRF
&&
3174 scan_inst
->dst
.hw_reg
== inst
->dst
.hw_reg
) {
3175 /* Somebody else wrote our MRF here, so we can't can't
3176 * compute-to-MRF before that.
3181 if (scan_inst
->mlen
> 0) {
3182 /* Found a SEND instruction, which means that there are
3183 * live values in MRFs from base_mrf to base_mrf +
3184 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3187 if (inst
->dst
.hw_reg
>= scan_inst
->base_mrf
&&
3188 inst
->dst
.hw_reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
3199 * Walks through basic blocks, locking for repeated MRF writes and
3200 * removing the later ones.
3203 fs_visitor::remove_duplicate_mrf_writes()
3205 fs_inst
*last_mrf_move
[16];
3206 bool progress
= false;
3208 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3210 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3211 fs_inst
*inst
= (fs_inst
*)iter
.get();
3213 switch (inst
->opcode
) {
3215 case BRW_OPCODE_WHILE
:
3217 case BRW_OPCODE_ELSE
:
3218 case BRW_OPCODE_ENDIF
:
3219 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3225 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3226 inst
->dst
.file
== MRF
) {
3227 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.hw_reg
];
3228 if (prev_inst
&& inst
->equals(prev_inst
)) {
3235 /* Clear out the last-write records for MRFs that were overwritten. */
3236 if (inst
->dst
.file
== MRF
) {
3237 last_mrf_move
[inst
->dst
.hw_reg
] = NULL
;
3240 if (inst
->mlen
> 0) {
3241 /* Found a SEND instruction, which will include two of fewer
3242 * implied MRF writes. We could do better here.
3244 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3245 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3249 /* Clear out any MRF move records whose sources got overwritten. */
3250 if (inst
->dst
.file
== GRF
) {
3251 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
3252 if (last_mrf_move
[i
] &&
3253 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
3254 last_mrf_move
[i
] = NULL
;
3259 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3260 inst
->dst
.file
== MRF
&&
3261 inst
->src
[0].file
== GRF
&&
3262 !inst
->predicated
) {
3263 last_mrf_move
[inst
->dst
.hw_reg
] = inst
;
3271 fs_visitor::virtual_grf_interferes(int a
, int b
)
3273 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
3274 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
3276 /* We can't handle dead register writes here, without iterating
3277 * over the whole instruction stream to find every single dead
3278 * write to that register to compare to the live interval of the
3279 * other register. Just assert that dead_code_eliminate() has been
3282 assert((this->virtual_grf_use
[a
] != -1 ||
3283 this->virtual_grf_def
[a
] == MAX_INSTRUCTION
) &&
3284 (this->virtual_grf_use
[b
] != -1 ||
3285 this->virtual_grf_def
[b
] == MAX_INSTRUCTION
));
3290 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
3292 struct brw_reg brw_reg
;
3294 switch (reg
->file
) {
3298 if (reg
->smear
== -1) {
3299 brw_reg
= brw_vec8_reg(reg
->file
,
3302 brw_reg
= brw_vec1_reg(reg
->file
,
3303 reg
->hw_reg
, reg
->smear
);
3305 brw_reg
= retype(brw_reg
, reg
->type
);
3308 switch (reg
->type
) {
3309 case BRW_REGISTER_TYPE_F
:
3310 brw_reg
= brw_imm_f(reg
->imm
.f
);
3312 case BRW_REGISTER_TYPE_D
:
3313 brw_reg
= brw_imm_d(reg
->imm
.i
);
3315 case BRW_REGISTER_TYPE_UD
:
3316 brw_reg
= brw_imm_ud(reg
->imm
.u
);
3319 assert(!"not reached");
3320 brw_reg
= brw_null_reg();
3325 brw_reg
= reg
->fixed_hw_reg
;
3328 /* Probably unused. */
3329 brw_reg
= brw_null_reg();
3332 assert(!"not reached");
3333 brw_reg
= brw_null_reg();
3336 assert(!"not reached");
3337 brw_reg
= brw_null_reg();
3341 brw_reg
= brw_abs(brw_reg
);
3343 brw_reg
= negate(brw_reg
);
3349 fs_visitor::generate_code()
3351 int last_native_inst
= 0;
3352 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
3353 int if_stack_depth
= 0, loop_stack_depth
= 0;
3354 int if_depth_in_loop
[16];
3355 const char *last_annotation_string
= NULL
;
3356 ir_instruction
*last_annotation_ir
= NULL
;
3358 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3359 printf("Native code for fragment shader %d:\n",
3360 ctx
->Shader
.CurrentFragmentProgram
->Name
);
3363 if_depth_in_loop
[loop_stack_depth
] = 0;
3365 memset(&if_stack
, 0, sizeof(if_stack
));
3366 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3367 fs_inst
*inst
= (fs_inst
*)iter
.get();
3368 struct brw_reg src
[3], dst
;
3370 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3371 if (last_annotation_ir
!= inst
->ir
) {
3372 last_annotation_ir
= inst
->ir
;
3373 if (last_annotation_ir
) {
3375 last_annotation_ir
->print();
3379 if (last_annotation_string
!= inst
->annotation
) {
3380 last_annotation_string
= inst
->annotation
;
3381 if (last_annotation_string
)
3382 printf(" %s\n", last_annotation_string
);
3386 for (unsigned int i
= 0; i
< 3; i
++) {
3387 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
3389 dst
= brw_reg_from_fs_reg(&inst
->dst
);
3391 brw_set_conditionalmod(p
, inst
->conditional_mod
);
3392 brw_set_predicate_control(p
, inst
->predicated
);
3393 brw_set_saturate(p
, inst
->saturate
);
3395 switch (inst
->opcode
) {
3396 case BRW_OPCODE_MOV
:
3397 brw_MOV(p
, dst
, src
[0]);
3399 case BRW_OPCODE_ADD
:
3400 brw_ADD(p
, dst
, src
[0], src
[1]);
3402 case BRW_OPCODE_MUL
:
3403 brw_MUL(p
, dst
, src
[0], src
[1]);
3406 case BRW_OPCODE_FRC
:
3407 brw_FRC(p
, dst
, src
[0]);
3409 case BRW_OPCODE_RNDD
:
3410 brw_RNDD(p
, dst
, src
[0]);
3412 case BRW_OPCODE_RNDE
:
3413 brw_RNDE(p
, dst
, src
[0]);
3415 case BRW_OPCODE_RNDZ
:
3416 brw_RNDZ(p
, dst
, src
[0]);
3419 case BRW_OPCODE_AND
:
3420 brw_AND(p
, dst
, src
[0], src
[1]);
3423 brw_OR(p
, dst
, src
[0], src
[1]);
3425 case BRW_OPCODE_XOR
:
3426 brw_XOR(p
, dst
, src
[0], src
[1]);
3428 case BRW_OPCODE_NOT
:
3429 brw_NOT(p
, dst
, src
[0]);
3431 case BRW_OPCODE_ASR
:
3432 brw_ASR(p
, dst
, src
[0], src
[1]);
3434 case BRW_OPCODE_SHR
:
3435 brw_SHR(p
, dst
, src
[0], src
[1]);
3437 case BRW_OPCODE_SHL
:
3438 brw_SHL(p
, dst
, src
[0], src
[1]);
3441 case BRW_OPCODE_CMP
:
3442 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
3444 case BRW_OPCODE_SEL
:
3445 brw_SEL(p
, dst
, src
[0], src
[1]);
3449 assert(if_stack_depth
< 16);
3450 if (inst
->src
[0].file
!= BAD_FILE
) {
3451 assert(intel
->gen
>= 6);
3452 if_stack
[if_stack_depth
] = brw_IF_gen6(p
, inst
->conditional_mod
, src
[0], src
[1]);
3454 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
3456 if_depth_in_loop
[loop_stack_depth
]++;
3460 case BRW_OPCODE_ELSE
:
3461 if_stack
[if_stack_depth
- 1] =
3462 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
3464 case BRW_OPCODE_ENDIF
:
3466 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
3467 if_depth_in_loop
[loop_stack_depth
]--;
3471 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
3472 if_depth_in_loop
[loop_stack_depth
] = 0;
3475 case BRW_OPCODE_BREAK
:
3476 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
3477 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3479 case BRW_OPCODE_CONTINUE
:
3480 /* FINISHME: We need to write the loop instruction support still. */
3481 if (intel
->gen
>= 6)
3482 brw_CONT_gen6(p
, loop_stack
[loop_stack_depth
- 1]);
3484 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
3485 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3488 case BRW_OPCODE_WHILE
: {
3489 struct brw_instruction
*inst0
, *inst1
;
3492 if (intel
->gen
>= 5)
3495 assert(loop_stack_depth
> 0);
3497 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
3498 if (intel
->gen
< 6) {
3499 /* patch all the BREAK/CONT instructions from last BGNLOOP */
3500 while (inst0
> loop_stack
[loop_stack_depth
]) {
3502 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
3503 inst0
->bits3
.if_else
.jump_count
== 0) {
3504 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
3506 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
3507 inst0
->bits3
.if_else
.jump_count
== 0) {
3508 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
3517 case FS_OPCODE_SQRT
:
3518 case FS_OPCODE_EXP2
:
3519 case FS_OPCODE_LOG2
:
3523 generate_math(inst
, dst
, src
);
3525 case FS_OPCODE_CINTERP
:
3526 brw_MOV(p
, dst
, src
[0]);
3528 case FS_OPCODE_LINTERP
:
3529 generate_linterp(inst
, dst
, src
);
3534 generate_tex(inst
, dst
);
3536 case FS_OPCODE_DISCARD_NOT
:
3537 generate_discard_not(inst
, dst
);
3539 case FS_OPCODE_DISCARD_AND
:
3540 generate_discard_and(inst
, src
[0]);
3543 generate_ddx(inst
, dst
, src
[0]);
3546 generate_ddy(inst
, dst
, src
[0]);
3549 case FS_OPCODE_SPILL
:
3550 generate_spill(inst
, src
[0]);
3553 case FS_OPCODE_UNSPILL
:
3554 generate_unspill(inst
, dst
);
3557 case FS_OPCODE_PULL_CONSTANT_LOAD
:
3558 generate_pull_constant_load(inst
, dst
);
3561 case FS_OPCODE_FB_WRITE
:
3562 generate_fb_write(inst
);
3565 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
3566 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
3567 brw_opcodes
[inst
->opcode
].name
);
3569 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
3574 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3575 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
3577 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3578 ((uint32_t *)&p
->store
[i
])[3],
3579 ((uint32_t *)&p
->store
[i
])[2],
3580 ((uint32_t *)&p
->store
[i
])[1],
3581 ((uint32_t *)&p
->store
[i
])[0]);
3583 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3587 last_native_inst
= p
->nr_insn
;
3592 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
3593 * emit issues, it doesn't get the jump distances into the output,
3594 * which is often something we want to debug. So this is here in
3595 * case you're doing that.
3598 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3599 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3600 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3601 ((uint32_t *)&p
->store
[i
])[3],
3602 ((uint32_t *)&p
->store
[i
])[2],
3603 ((uint32_t *)&p
->store
[i
])[1],
3604 ((uint32_t *)&p
->store
[i
])[0]);
3605 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3612 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
3614 struct intel_context
*intel
= &brw
->intel
;
3615 struct gl_context
*ctx
= &intel
->ctx
;
3616 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentFragmentProgram
;
3621 struct brw_shader
*shader
=
3622 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3626 /* We always use 8-wide mode, at least for now. For one, flow
3627 * control only works in 8-wide. Also, when we're fragment shader
3628 * bound, we're almost always under register pressure as well, so
3629 * 8-wide would save us from the performance cliff of spilling
3632 c
->dispatch_width
= 8;
3634 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3635 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3636 _mesa_print_ir(shader
->ir
, NULL
);
3640 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3642 fs_visitor
v(c
, shader
);
3647 v
.calculate_urb_setup();
3649 v
.emit_interpolation_setup_gen4();
3651 v
.emit_interpolation_setup_gen6();
3653 /* Generate FS IR for main(). (the visitor only descends into
3654 * functions called "main").
3656 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3657 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3664 v
.split_virtual_grfs();
3665 v
.setup_pull_constants();
3667 v
.assign_curb_setup();
3668 v
.assign_urb_setup();
3674 progress
= v
.remove_duplicate_mrf_writes() || progress
;
3676 progress
= v
.propagate_constants() || progress
;
3677 progress
= v
.register_coalesce() || progress
;
3678 progress
= v
.compute_to_mrf() || progress
;
3679 progress
= v
.dead_code_eliminate() || progress
;
3683 /* Debug of register spilling: Go spill everything. */
3684 int virtual_grf_count
= v
.virtual_grf_next
;
3685 for (int i
= 1; i
< virtual_grf_count
; i
++) {
3691 v
.assign_regs_trivial();
3693 while (!v
.assign_regs()) {
3703 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3708 c
->prog_data
.total_grf
= v
.grf_used
;