2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "../glsl/glsl_types.h"
48 #include "../glsl/ir_optimization.h"
49 #include "../glsl/ir_print_visitor.h"
51 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
54 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
56 struct brw_shader
*shader
;
58 shader
= talloc_zero(NULL
, struct brw_shader
);
60 shader
->base
.Type
= type
;
61 shader
->base
.Name
= name
;
62 _mesa_init_shader(ctx
, &shader
->base
);
68 struct gl_shader_program
*
69 brw_new_shader_program(struct gl_context
*ctx
, GLuint name
)
71 struct brw_shader_program
*prog
;
72 prog
= talloc_zero(NULL
, struct brw_shader_program
);
74 prog
->base
.Name
= name
;
75 _mesa_init_shader_program(ctx
, &prog
->base
);
81 brw_compile_shader(struct gl_context
*ctx
, struct gl_shader
*shader
)
83 if (!_mesa_ir_compile_shader(ctx
, shader
))
90 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
92 struct brw_shader
*shader
=
93 (struct brw_shader
*)prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
95 void *mem_ctx
= talloc_new(NULL
);
99 talloc_free(shader
->ir
);
100 shader
->ir
= new(shader
) exec_list
;
101 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
103 do_mat_op_to_vec(shader
->ir
);
104 lower_instructions(shader
->ir
,
110 do_lower_texture_projection(shader
->ir
);
111 brw_do_cubemap_normalize(shader
->ir
);
116 brw_do_channel_expressions(shader
->ir
);
117 brw_do_vector_splitting(shader
->ir
);
119 progress
= do_lower_jumps(shader
->ir
, true, true,
120 true, /* main return */
121 false, /* continue */
125 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
127 progress
= lower_noise(shader
->ir
) || progress
;
129 lower_variable_index_to_cond_assign(shader
->ir
,
131 GL_TRUE
, /* output */
133 GL_TRUE
/* uniform */
135 progress
= lower_quadop_vector(shader
->ir
, false) || progress
;
138 validate_ir_tree(shader
->ir
);
140 reparent_ir(shader
->ir
, shader
->ir
);
141 talloc_free(mem_ctx
);
144 if (!_mesa_ir_link_shader(ctx
, prog
))
151 type_size(const struct glsl_type
*type
)
153 unsigned int size
, i
;
155 switch (type
->base_type
) {
158 case GLSL_TYPE_FLOAT
:
160 return type
->components();
161 case GLSL_TYPE_ARRAY
:
162 return type_size(type
->fields
.array
) * type
->length
;
163 case GLSL_TYPE_STRUCT
:
165 for (i
= 0; i
< type
->length
; i
++) {
166 size
+= type_size(type
->fields
.structure
[i
].type
);
169 case GLSL_TYPE_SAMPLER
:
170 /* Samplers take up no register space, since they're baked in at
175 assert(!"not reached");
181 * Returns how many MRFs an FS opcode will write over.
183 * Note that this is not the 0 or 1 implied writes in an actual gen
184 * instruction -- the FS opcodes often generate MOVs in addition.
187 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
192 switch (inst
->opcode
) {
207 case FS_OPCODE_FB_WRITE
:
209 case FS_OPCODE_PULL_CONSTANT_LOAD
:
210 case FS_OPCODE_UNSPILL
:
212 case FS_OPCODE_SPILL
:
215 assert(!"not reached");
221 fs_visitor::virtual_grf_alloc(int size
)
223 if (virtual_grf_array_size
<= virtual_grf_next
) {
224 if (virtual_grf_array_size
== 0)
225 virtual_grf_array_size
= 16;
227 virtual_grf_array_size
*= 2;
228 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
229 int, virtual_grf_array_size
);
231 /* This slot is always unused. */
232 virtual_grf_sizes
[0] = 0;
234 virtual_grf_sizes
[virtual_grf_next
] = size
;
235 return virtual_grf_next
++;
238 /** Fixed HW reg constructor. */
239 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
243 this->hw_reg
= hw_reg
;
244 this->type
= BRW_REGISTER_TYPE_F
;
247 /** Fixed HW reg constructor. */
248 fs_reg::fs_reg(enum register_file file
, int hw_reg
, uint32_t type
)
252 this->hw_reg
= hw_reg
;
257 brw_type_for_base_type(const struct glsl_type
*type
)
259 switch (type
->base_type
) {
260 case GLSL_TYPE_FLOAT
:
261 return BRW_REGISTER_TYPE_F
;
264 return BRW_REGISTER_TYPE_D
;
266 return BRW_REGISTER_TYPE_UD
;
267 case GLSL_TYPE_ARRAY
:
268 case GLSL_TYPE_STRUCT
:
269 case GLSL_TYPE_SAMPLER
:
270 /* These should be overridden with the type of the member when
271 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
272 * way to trip up if we don't.
274 return BRW_REGISTER_TYPE_UD
;
276 assert(!"not reached");
277 return BRW_REGISTER_TYPE_F
;
281 /** Automatic reg constructor. */
282 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
287 this->reg
= v
->virtual_grf_alloc(type_size(type
));
288 this->reg_offset
= 0;
289 this->type
= brw_type_for_base_type(type
);
293 fs_visitor::variable_storage(ir_variable
*var
)
295 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
298 /* Our support for uniforms is piggy-backed on the struct
299 * gl_fragment_program, because that's where the values actually
300 * get stored, rather than in some global gl_shader_program uniform
304 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
306 unsigned int offset
= 0;
309 if (type
->is_matrix()) {
310 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
311 type
->vector_elements
,
314 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
315 offset
+= setup_uniform_values(loc
+ offset
, column
);
321 switch (type
->base_type
) {
322 case GLSL_TYPE_FLOAT
:
326 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
327 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
328 unsigned int param
= c
->prog_data
.nr_params
++;
330 assert(param
< ARRAY_SIZE(c
->prog_data
.param
));
332 switch (type
->base_type
) {
333 case GLSL_TYPE_FLOAT
:
334 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
337 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2U
;
340 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2I
;
343 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2B
;
346 assert(!"not reached");
347 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
351 c
->prog_data
.param
[param
] = &vec_values
[i
];
355 case GLSL_TYPE_STRUCT
:
356 for (unsigned int i
= 0; i
< type
->length
; i
++) {
357 offset
+= setup_uniform_values(loc
+ offset
,
358 type
->fields
.structure
[i
].type
);
362 case GLSL_TYPE_ARRAY
:
363 for (unsigned int i
= 0; i
< type
->length
; i
++) {
364 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
368 case GLSL_TYPE_SAMPLER
:
369 /* The sampler takes up a slot, but we don't use any values from it. */
373 assert(!"not reached");
379 /* Our support for builtin uniforms is even scarier than non-builtin.
380 * It sits on top of the PROG_STATE_VAR parameters that are
381 * automatically updated from GL context state.
384 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
386 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
388 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
389 statevar
= &_mesa_builtin_uniform_desc
[i
];
390 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
394 if (!statevar
->name
) {
396 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
401 if (ir
->type
->is_array()) {
402 array_count
= ir
->type
->length
;
407 for (int a
= 0; a
< array_count
; a
++) {
408 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
409 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
410 int tokens
[STATE_LENGTH
];
412 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
413 if (ir
->type
->is_array()) {
417 /* This state reference has already been setup by ir_to_mesa,
418 * but we'll get the same index back here.
420 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
421 (gl_state_index
*)tokens
);
422 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
424 /* Add each of the unique swizzles of the element as a
425 * parameter. This'll end up matching the expected layout of
426 * the array/matrix/structure we're trying to fill in.
429 for (unsigned int i
= 0; i
< 4; i
++) {
430 int swiz
= GET_SWZ(element
->swizzle
, i
);
431 if (swiz
== last_swiz
)
435 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
437 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
444 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
446 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
448 fs_reg neg_y
= this->pixel_y
;
450 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
453 if (ir
->pixel_center_integer
) {
454 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
456 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
461 if (!flip
&& ir
->pixel_center_integer
) {
462 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
464 fs_reg pixel_y
= this->pixel_y
;
465 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
468 pixel_y
.negate
= true;
469 offset
+= c
->key
.drawable_height
- 1.0;
472 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
477 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
478 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
481 /* gl_FragCoord.w: Already set up in emit_interpolation */
482 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
488 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
490 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
491 /* Interpolation is always in floating point regs. */
492 reg
->type
= BRW_REGISTER_TYPE_F
;
495 unsigned int array_elements
;
496 const glsl_type
*type
;
498 if (ir
->type
->is_array()) {
499 array_elements
= ir
->type
->length
;
500 if (array_elements
== 0) {
503 type
= ir
->type
->fields
.array
;
509 int location
= ir
->location
;
510 for (unsigned int i
= 0; i
< array_elements
; i
++) {
511 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
512 if (urb_setup
[location
] == -1) {
513 /* If there's no incoming setup data for this slot, don't
514 * emit interpolation for it.
516 attr
.reg_offset
+= type
->vector_elements
;
521 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
522 struct brw_reg interp
= interp_reg(location
, c
);
523 emit(fs_inst(FS_OPCODE_LINTERP
,
531 if (intel
->gen
< 6) {
532 attr
.reg_offset
-= type
->vector_elements
;
533 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
534 emit(fs_inst(BRW_OPCODE_MUL
,
549 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
551 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
553 /* The frontfacing comes in as a bit in the thread payload. */
554 if (intel
->gen
>= 6) {
555 emit(fs_inst(BRW_OPCODE_ASR
,
557 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
559 emit(fs_inst(BRW_OPCODE_NOT
,
562 emit(fs_inst(BRW_OPCODE_AND
,
567 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
568 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
571 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
575 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
576 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
583 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src
)
595 assert(!"not reached: bad math opcode");
599 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
600 * might be able to do better by doing execsize = 1 math and then
601 * expanding that result out, but we would need to be careful with
604 if (intel
->gen
>= 6 && src
.file
== UNIFORM
) {
605 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
606 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src
));
610 fs_inst
*inst
= emit(fs_inst(opcode
, dst
, src
));
612 if (intel
->gen
< 6) {
621 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
626 assert(opcode
== FS_OPCODE_POW
);
628 if (intel
->gen
>= 6) {
629 /* Can't do hstride == 0 args to gen6 math, so expand it out. */
630 if (src0
.file
== UNIFORM
) {
631 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
632 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src0
));
636 if (src1
.file
== UNIFORM
) {
637 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
638 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src1
));
642 inst
= emit(fs_inst(opcode
, dst
, src0
, src1
));
644 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1), src1
));
645 inst
= emit(fs_inst(opcode
, dst
, src0
, reg_null_f
));
647 inst
->base_mrf
= base_mrf
;
654 fs_visitor::visit(ir_variable
*ir
)
658 if (variable_storage(ir
))
661 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
662 this->frag_color
= ir
;
663 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
664 this->frag_data
= ir
;
665 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
666 this->frag_depth
= ir
;
669 if (ir
->mode
== ir_var_in
) {
670 if (!strcmp(ir
->name
, "gl_FragCoord")) {
671 reg
= emit_fragcoord_interpolation(ir
);
672 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
673 reg
= emit_frontfacing_interpolation(ir
);
675 reg
= emit_general_interpolation(ir
);
678 hash_table_insert(this->variable_ht
, reg
, ir
);
682 if (ir
->mode
== ir_var_uniform
) {
683 int param_index
= c
->prog_data
.nr_params
;
685 if (!strncmp(ir
->name
, "gl_", 3)) {
686 setup_builtin_uniform_values(ir
);
688 setup_uniform_values(ir
->location
, ir
->type
);
691 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
692 reg
->type
= brw_type_for_base_type(ir
->type
);
696 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
698 hash_table_insert(this->variable_ht
, reg
, ir
);
702 fs_visitor::visit(ir_dereference_variable
*ir
)
704 fs_reg
*reg
= variable_storage(ir
->var
);
709 fs_visitor::visit(ir_dereference_record
*ir
)
711 const glsl_type
*struct_type
= ir
->record
->type
;
713 ir
->record
->accept(this);
715 unsigned int offset
= 0;
716 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
717 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
719 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
721 this->result
.reg_offset
+= offset
;
722 this->result
.type
= brw_type_for_base_type(ir
->type
);
726 fs_visitor::visit(ir_dereference_array
*ir
)
731 ir
->array
->accept(this);
732 index
= ir
->array_index
->as_constant();
734 element_size
= type_size(ir
->type
);
735 this->result
.type
= brw_type_for_base_type(ir
->type
);
738 assert(this->result
.file
== UNIFORM
||
739 (this->result
.file
== GRF
&&
740 this->result
.reg
!= 0));
741 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
743 assert(!"FINISHME: non-constant array element");
747 /* Instruction selection: Produce a MOV.sat instead of
748 * MIN(MAX(val, 0), 1) when possible.
751 fs_visitor::try_emit_saturate(ir_expression
*ir
)
753 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
758 sat_val
->accept(this);
759 fs_reg src
= this->result
;
761 this->result
= fs_reg(this, ir
->type
);
762 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, src
));
763 inst
->saturate
= true;
769 fs_visitor::visit(ir_expression
*ir
)
771 unsigned int operand
;
775 assert(ir
->get_num_operands() <= 2);
777 if (try_emit_saturate(ir
))
780 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
781 ir
->operands
[operand
]->accept(this);
782 if (this->result
.file
== BAD_FILE
) {
784 printf("Failed to get tree for expression operand:\n");
785 ir
->operands
[operand
]->accept(&v
);
788 op
[operand
] = this->result
;
790 /* Matrix expression operands should have been broken down to vector
791 * operations already.
793 assert(!ir
->operands
[operand
]->type
->is_matrix());
794 /* And then those vector operands should have been broken down to scalar.
796 assert(!ir
->operands
[operand
]->type
->is_vector());
799 /* Storage for our result. If our result goes into an assignment, it will
800 * just get copy-propagated out, so no worries.
802 this->result
= fs_reg(this, ir
->type
);
804 switch (ir
->operation
) {
805 case ir_unop_logic_not
:
806 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
807 * ones complement of the whole register, not just bit 0.
809 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1)));
812 op
[0].negate
= !op
[0].negate
;
813 this->result
= op
[0];
817 this->result
= op
[0];
820 temp
= fs_reg(this, ir
->type
);
822 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
824 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
825 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
826 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
827 inst
->predicated
= true;
829 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
830 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
831 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
832 inst
->predicated
= true;
836 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
840 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
843 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
847 assert(!"not reached: should be handled by ir_explog_to_explog2");
850 case ir_unop_sin_reduced
:
851 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
854 case ir_unop_cos_reduced
:
855 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
859 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
862 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
866 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
869 assert(!"not reached: should be handled by ir_sub_to_add_neg");
873 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
876 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
879 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
883 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
884 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
885 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
887 case ir_binop_greater
:
888 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
889 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
890 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
892 case ir_binop_lequal
:
893 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
894 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
895 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
897 case ir_binop_gequal
:
898 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
899 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
900 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
903 case ir_binop_all_equal
: /* same as nequal for scalars */
904 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
905 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
906 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
908 case ir_binop_nequal
:
909 case ir_binop_any_nequal
: /* same as nequal for scalars */
910 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
911 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
912 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
915 case ir_binop_logic_xor
:
916 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
919 case ir_binop_logic_or
:
920 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
923 case ir_binop_logic_and
:
924 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
929 assert(!"not reached: should be handled by brw_fs_channel_expressions");
933 assert(!"not reached: should be handled by lower_noise");
936 case ir_quadop_vector
:
937 assert(!"not reached: should be handled by lower_quadop_vector");
941 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
945 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
952 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
956 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
957 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
958 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
,
959 this->result
, fs_reg(1)));
963 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
966 op
[0].negate
= !op
[0].negate
;
967 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
968 this->result
.negate
= true;
971 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
974 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
976 case ir_unop_round_even
:
977 emit(fs_inst(BRW_OPCODE_RNDE
, this->result
, op
[0]));
981 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
982 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
984 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
985 inst
->predicated
= true;
988 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
989 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
991 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
992 inst
->predicated
= true;
996 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
999 case ir_unop_bit_not
:
1000 inst
= emit(fs_inst(BRW_OPCODE_NOT
, this->result
, op
[0]));
1002 case ir_binop_bit_and
:
1003 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
1005 case ir_binop_bit_xor
:
1006 inst
= emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
1008 case ir_binop_bit_or
:
1009 inst
= emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
1013 case ir_binop_lshift
:
1014 case ir_binop_rshift
:
1015 assert(!"GLSL 1.30 features unsupported");
1021 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1022 const glsl_type
*type
, bool predicated
)
1024 switch (type
->base_type
) {
1025 case GLSL_TYPE_FLOAT
:
1026 case GLSL_TYPE_UINT
:
1028 case GLSL_TYPE_BOOL
:
1029 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1030 l
.type
= brw_type_for_base_type(type
);
1031 r
.type
= brw_type_for_base_type(type
);
1033 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1034 inst
->predicated
= predicated
;
1040 case GLSL_TYPE_ARRAY
:
1041 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1042 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1046 case GLSL_TYPE_STRUCT
:
1047 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1048 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1053 case GLSL_TYPE_SAMPLER
:
1057 assert(!"not reached");
1063 fs_visitor::visit(ir_assignment
*ir
)
1068 /* FINISHME: arrays on the lhs */
1069 ir
->lhs
->accept(this);
1072 ir
->rhs
->accept(this);
1075 assert(l
.file
!= BAD_FILE
);
1076 assert(r
.file
!= BAD_FILE
);
1078 if (ir
->condition
) {
1079 emit_bool_to_cond_code(ir
->condition
);
1082 if (ir
->lhs
->type
->is_scalar() ||
1083 ir
->lhs
->type
->is_vector()) {
1084 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1085 if (ir
->write_mask
& (1 << i
)) {
1086 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1088 inst
->predicated
= true;
1094 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1099 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1103 bool simd16
= false;
1109 if (ir
->shadow_comparitor
) {
1110 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1111 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1113 coordinate
.reg_offset
++;
1115 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1118 if (ir
->op
== ir_tex
) {
1119 /* There's no plain shadow compare message, so we use shadow
1120 * compare with a bias of 0.0.
1122 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1125 } else if (ir
->op
== ir_txb
) {
1126 ir
->lod_info
.bias
->accept(this);
1127 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1131 assert(ir
->op
== ir_txl
);
1132 ir
->lod_info
.lod
->accept(this);
1133 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1138 ir
->shadow_comparitor
->accept(this);
1139 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1141 } else if (ir
->op
== ir_tex
) {
1142 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1143 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1145 coordinate
.reg_offset
++;
1147 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1150 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1151 * instructions. We'll need to do SIMD16 here.
1153 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1155 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1156 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2),
1158 coordinate
.reg_offset
++;
1161 /* lod/bias appears after u/v/r. */
1164 if (ir
->op
== ir_txb
) {
1165 ir
->lod_info
.bias
->accept(this);
1166 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1170 ir
->lod_info
.lod
->accept(this);
1171 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1176 /* The unused upper half. */
1179 /* Now, since we're doing simd16, the return is 2 interleaved
1180 * vec4s where the odd-indexed ones are junk. We'll need to move
1181 * this weirdness around to the expected layout.
1185 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1187 dst
.type
= BRW_REGISTER_TYPE_F
;
1190 fs_inst
*inst
= NULL
;
1193 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1196 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1199 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1203 assert(!"GLSL 1.30 features unsupported");
1206 inst
->base_mrf
= base_mrf
;
1210 for (int i
= 0; i
< 4; i
++) {
1211 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1212 orig_dst
.reg_offset
++;
1213 dst
.reg_offset
+= 2;
1221 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1223 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1224 * optional parameters like shadow comparitor or LOD bias. If
1225 * optional parameters aren't present, those base slots are
1226 * optional and don't need to be included in the message.
1228 * We don't fill in the unnecessary slots regardless, which may
1229 * look surprising in the disassembly.
1231 int mlen
= 1; /* g0 header always present. */
1234 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1235 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1237 coordinate
.reg_offset
++;
1239 mlen
+= ir
->coordinate
->type
->vector_elements
;
1241 if (ir
->shadow_comparitor
) {
1242 mlen
= MAX2(mlen
, 5);
1244 ir
->shadow_comparitor
->accept(this);
1245 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1249 fs_inst
*inst
= NULL
;
1252 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1255 ir
->lod_info
.bias
->accept(this);
1256 mlen
= MAX2(mlen
, 5);
1257 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1260 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1263 ir
->lod_info
.lod
->accept(this);
1264 mlen
= MAX2(mlen
, 5);
1265 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1268 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1272 assert(!"GLSL 1.30 features unsupported");
1275 inst
->base_mrf
= base_mrf
;
1282 fs_visitor::visit(ir_texture
*ir
)
1285 fs_inst
*inst
= NULL
;
1287 ir
->coordinate
->accept(this);
1288 fs_reg coordinate
= this->result
;
1290 /* Should be lowered by do_lower_texture_projection */
1291 assert(!ir
->projector
);
1293 sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
1294 ctx
->Shader
.CurrentFragmentProgram
,
1295 &brw
->fragment_program
->Base
);
1296 sampler
= c
->fp
->program
.Base
.SamplerUnits
[sampler
];
1298 /* The 965 requires the EU to do the normalization of GL rectangle
1299 * texture coordinates. We use the program parameter state
1300 * tracking to get the scaling factor.
1302 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1303 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1304 int tokens
[STATE_LENGTH
] = {
1306 STATE_TEXRECT_SCALE
,
1312 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
1314 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
+ 1] =
1317 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1318 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1319 GLuint index
= _mesa_add_state_reference(params
,
1320 (gl_state_index
*)tokens
);
1321 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
1323 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[0];
1324 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[1];
1326 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1327 fs_reg src
= coordinate
;
1330 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_x
));
1333 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_y
));
1336 /* Writemasking doesn't eliminate channels on SIMD8 texture
1337 * samples, so don't worry about them.
1339 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1341 if (intel
->gen
< 5) {
1342 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1344 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1347 inst
->sampler
= sampler
;
1351 if (ir
->shadow_comparitor
)
1352 inst
->shadow_compare
= true;
1354 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1355 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1357 for (int i
= 0; i
< 4; i
++) {
1358 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1359 fs_reg l
= swizzle_dst
;
1362 if (swiz
== SWIZZLE_ZERO
) {
1363 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1364 } else if (swiz
== SWIZZLE_ONE
) {
1365 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1368 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1369 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1372 this->result
= swizzle_dst
;
1377 fs_visitor::visit(ir_swizzle
*ir
)
1379 ir
->val
->accept(this);
1380 fs_reg val
= this->result
;
1382 if (ir
->type
->vector_elements
== 1) {
1383 this->result
.reg_offset
+= ir
->mask
.x
;
1387 fs_reg result
= fs_reg(this, ir
->type
);
1388 this->result
= result
;
1390 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1391 fs_reg channel
= val
;
1409 channel
.reg_offset
+= swiz
;
1410 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1411 result
.reg_offset
++;
1416 fs_visitor::visit(ir_discard
*ir
)
1418 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1420 assert(ir
->condition
== NULL
); /* FINISHME */
1422 emit(fs_inst(FS_OPCODE_DISCARD_NOT
, temp
, reg_null_d
));
1423 emit(fs_inst(FS_OPCODE_DISCARD_AND
, reg_null_d
, temp
));
1424 kill_emitted
= true;
1428 fs_visitor::visit(ir_constant
*ir
)
1430 /* Set this->result to reg at the bottom of the function because some code
1431 * paths will cause this visitor to be applied to other fields. This will
1432 * cause the value stored in this->result to be modified.
1434 * Make reg constant so that it doesn't get accidentally modified along the
1435 * way. Yes, I actually had this problem. :(
1437 const fs_reg
reg(this, ir
->type
);
1438 fs_reg dst_reg
= reg
;
1440 if (ir
->type
->is_array()) {
1441 const unsigned size
= type_size(ir
->type
->fields
.array
);
1443 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1444 ir
->array_elements
[i
]->accept(this);
1445 fs_reg src_reg
= this->result
;
1447 dst_reg
.type
= src_reg
.type
;
1448 for (unsigned j
= 0; j
< size
; j
++) {
1449 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, src_reg
));
1450 src_reg
.reg_offset
++;
1451 dst_reg
.reg_offset
++;
1454 } else if (ir
->type
->is_record()) {
1455 foreach_list(node
, &ir
->components
) {
1456 ir_instruction
*const field
= (ir_instruction
*) node
;
1457 const unsigned size
= type_size(field
->type
);
1459 field
->accept(this);
1460 fs_reg src_reg
= this->result
;
1462 dst_reg
.type
= src_reg
.type
;
1463 for (unsigned j
= 0; j
< size
; j
++) {
1464 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, src_reg
));
1465 src_reg
.reg_offset
++;
1466 dst_reg
.reg_offset
++;
1470 const unsigned size
= type_size(ir
->type
);
1472 for (unsigned i
= 0; i
< size
; i
++) {
1473 switch (ir
->type
->base_type
) {
1474 case GLSL_TYPE_FLOAT
:
1475 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.f
[i
])));
1477 case GLSL_TYPE_UINT
:
1478 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.u
[i
])));
1481 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.i
[i
])));
1483 case GLSL_TYPE_BOOL
:
1484 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg((int)ir
->value
.b
[i
])));
1487 assert(!"Non-float/uint/int/bool constant");
1489 dst_reg
.reg_offset
++;
1497 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1499 ir_expression
*expr
= ir
->as_expression();
1505 assert(expr
->get_num_operands() <= 2);
1506 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1507 assert(expr
->operands
[i
]->type
->is_scalar());
1509 expr
->operands
[i
]->accept(this);
1510 op
[i
] = this->result
;
1513 switch (expr
->operation
) {
1514 case ir_unop_logic_not
:
1515 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1)));
1516 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1519 case ir_binop_logic_xor
:
1520 inst
= emit(fs_inst(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]));
1521 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1524 case ir_binop_logic_or
:
1525 inst
= emit(fs_inst(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]));
1526 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1529 case ir_binop_logic_and
:
1530 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]));
1531 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1535 if (intel
->gen
>= 6) {
1536 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1537 op
[0], fs_reg(0.0f
)));
1539 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1541 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1545 if (intel
->gen
>= 6) {
1546 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0)));
1548 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1550 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1553 case ir_binop_greater
:
1554 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1555 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1557 case ir_binop_gequal
:
1558 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1559 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1562 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1563 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1565 case ir_binop_lequal
:
1566 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1567 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1569 case ir_binop_equal
:
1570 case ir_binop_all_equal
:
1571 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1572 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1574 case ir_binop_nequal
:
1575 case ir_binop_any_nequal
:
1576 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1577 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1580 assert(!"not reached");
1589 if (intel
->gen
>= 6) {
1590 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
,
1591 this->result
, fs_reg(1)));
1592 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1594 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, this->result
));
1595 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1600 * Emit a gen6 IF statement with the comparison folded into the IF
1604 fs_visitor::emit_if_gen6(ir_if
*ir
)
1606 ir_expression
*expr
= ir
->condition
->as_expression();
1613 assert(expr
->get_num_operands() <= 2);
1614 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1615 assert(expr
->operands
[i
]->type
->is_scalar());
1617 expr
->operands
[i
]->accept(this);
1618 op
[i
] = this->result
;
1621 switch (expr
->operation
) {
1622 case ir_unop_logic_not
:
1623 inst
= emit(fs_inst(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(1)));
1624 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1627 case ir_binop_logic_xor
:
1628 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1629 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1632 case ir_binop_logic_or
:
1633 temp
= fs_reg(this, glsl_type::bool_type
);
1634 emit(fs_inst(BRW_OPCODE_OR
, temp
, op
[0], op
[1]));
1635 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1636 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1639 case ir_binop_logic_and
:
1640 temp
= fs_reg(this, glsl_type::bool_type
);
1641 emit(fs_inst(BRW_OPCODE_AND
, temp
, op
[0], op
[1]));
1642 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1643 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1647 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0)));
1648 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1652 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1653 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1656 case ir_binop_greater
:
1657 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1658 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1660 case ir_binop_gequal
:
1661 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1662 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1665 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1666 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1668 case ir_binop_lequal
:
1669 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1670 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1672 case ir_binop_equal
:
1673 case ir_binop_all_equal
:
1674 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1675 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1677 case ir_binop_nequal
:
1678 case ir_binop_any_nequal
:
1679 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1680 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1683 assert(!"not reached");
1684 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1685 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1692 ir
->condition
->accept(this);
1694 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0)));
1695 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1699 fs_visitor::visit(ir_if
*ir
)
1703 /* Don't point the annotation at the if statement, because then it plus
1704 * the then and else blocks get printed.
1706 this->base_ir
= ir
->condition
;
1708 if (intel
->gen
>= 6) {
1711 emit_bool_to_cond_code(ir
->condition
);
1713 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1714 inst
->predicated
= true;
1717 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1718 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1724 if (!ir
->else_instructions
.is_empty()) {
1725 emit(fs_inst(BRW_OPCODE_ELSE
));
1727 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1728 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1735 emit(fs_inst(BRW_OPCODE_ENDIF
));
1739 fs_visitor::visit(ir_loop
*ir
)
1741 fs_reg counter
= reg_undef
;
1744 this->base_ir
= ir
->counter
;
1745 ir
->counter
->accept(this);
1746 counter
= *(variable_storage(ir
->counter
));
1749 this->base_ir
= ir
->from
;
1750 ir
->from
->accept(this);
1752 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1756 emit(fs_inst(BRW_OPCODE_DO
));
1759 this->base_ir
= ir
->to
;
1760 ir
->to
->accept(this);
1762 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1763 counter
, this->result
));
1765 case ir_binop_equal
:
1766 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1768 case ir_binop_nequal
:
1769 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1771 case ir_binop_gequal
:
1772 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1774 case ir_binop_lequal
:
1775 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1777 case ir_binop_greater
:
1778 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1781 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1784 assert(!"not reached: unknown loop condition");
1789 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1790 inst
->predicated
= true;
1793 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1794 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1800 if (ir
->increment
) {
1801 this->base_ir
= ir
->increment
;
1802 ir
->increment
->accept(this);
1803 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1806 emit(fs_inst(BRW_OPCODE_WHILE
));
1810 fs_visitor::visit(ir_loop_jump
*ir
)
1813 case ir_loop_jump::jump_break
:
1814 emit(fs_inst(BRW_OPCODE_BREAK
));
1816 case ir_loop_jump::jump_continue
:
1817 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1823 fs_visitor::visit(ir_call
*ir
)
1825 assert(!"FINISHME");
1829 fs_visitor::visit(ir_return
*ir
)
1831 assert(!"FINISHME");
1835 fs_visitor::visit(ir_function
*ir
)
1837 /* Ignore function bodies other than main() -- we shouldn't see calls to
1838 * them since they should all be inlined before we get to ir_to_mesa.
1840 if (strcmp(ir
->name
, "main") == 0) {
1841 const ir_function_signature
*sig
;
1844 sig
= ir
->matching_signature(&empty
);
1848 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1849 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1858 fs_visitor::visit(ir_function_signature
*ir
)
1860 assert(!"not reached");
1865 fs_visitor::emit(fs_inst inst
)
1867 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1870 list_inst
->annotation
= this->current_annotation
;
1871 list_inst
->ir
= this->base_ir
;
1873 this->instructions
.push_tail(list_inst
);
1878 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1880 fs_visitor::emit_dummy_fs()
1882 /* Everyone's favorite color. */
1883 emit(fs_inst(BRW_OPCODE_MOV
,
1886 emit(fs_inst(BRW_OPCODE_MOV
,
1889 emit(fs_inst(BRW_OPCODE_MOV
,
1892 emit(fs_inst(BRW_OPCODE_MOV
,
1897 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1900 write
->base_mrf
= 0;
1903 /* The register location here is relative to the start of the URB
1904 * data. It will get adjusted to be a real location before
1905 * generate_code() time.
1908 fs_visitor::interp_reg(int location
, int channel
)
1910 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1911 int stride
= (channel
& 1) * 4;
1913 assert(urb_setup
[location
] != -1);
1915 return brw_vec1_grf(regnr
, stride
);
1918 /** Emits the interpolation for the varying inputs. */
1920 fs_visitor::emit_interpolation_setup_gen4()
1922 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1924 this->current_annotation
= "compute pixel centers";
1925 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1926 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1927 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1928 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1929 emit(fs_inst(BRW_OPCODE_ADD
,
1931 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1932 fs_reg(brw_imm_v(0x10101010))));
1933 emit(fs_inst(BRW_OPCODE_ADD
,
1935 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1936 fs_reg(brw_imm_v(0x11001100))));
1938 this->current_annotation
= "compute pixel deltas from v0";
1940 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1941 this->delta_y
= this->delta_x
;
1942 this->delta_y
.reg_offset
++;
1944 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1945 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1947 emit(fs_inst(BRW_OPCODE_ADD
,
1950 fs_reg(negate(brw_vec1_grf(1, 0)))));
1951 emit(fs_inst(BRW_OPCODE_ADD
,
1954 fs_reg(negate(brw_vec1_grf(1, 1)))));
1956 this->current_annotation
= "compute pos.w and 1/pos.w";
1957 /* Compute wpos.w. It's always in our setup, since it's needed to
1958 * interpolate the other attributes.
1960 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1961 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1962 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1963 /* Compute the pixel 1/W value from wpos.w. */
1964 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1965 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1966 this->current_annotation
= NULL
;
1969 /** Emits the interpolation for the varying inputs. */
1971 fs_visitor::emit_interpolation_setup_gen6()
1973 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1975 /* If the pixel centers end up used, the setup is the same as for gen4. */
1976 this->current_annotation
= "compute pixel centers";
1977 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1978 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1979 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1980 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1981 emit(fs_inst(BRW_OPCODE_ADD
,
1983 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1984 fs_reg(brw_imm_v(0x10101010))));
1985 emit(fs_inst(BRW_OPCODE_ADD
,
1987 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1988 fs_reg(brw_imm_v(0x11001100))));
1990 /* As of gen6, we can no longer mix float and int sources. We have
1991 * to turn the integer pixel centers into floats for their actual
1994 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1995 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1996 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
));
1997 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
));
1999 this->current_annotation
= "compute 1/pos.w";
2000 this->wpos_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
2001 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
2002 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
2004 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
2005 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
2007 this->current_annotation
= NULL
;
2011 fs_visitor::emit_fb_writes()
2013 this->current_annotation
= "FB write header";
2014 GLboolean header_present
= GL_TRUE
;
2017 if (intel
->gen
>= 6 &&
2018 !this->kill_emitted
&&
2019 c
->key
.nr_color_regions
== 1) {
2020 header_present
= false;
2023 if (header_present
) {
2028 if (c
->aa_dest_stencil_reg
) {
2029 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2030 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0))));
2033 /* Reserve space for color. It'll be filled in per MRT below. */
2037 if (c
->source_depth_to_render_target
) {
2038 if (c
->computes_depth
) {
2039 /* Hand over gl_FragDepth. */
2040 assert(this->frag_depth
);
2041 fs_reg depth
= *(variable_storage(this->frag_depth
));
2043 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
2045 /* Pass through the payload depth. */
2046 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2047 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
2051 if (c
->dest_depth_reg
) {
2052 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2053 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0))));
2056 fs_reg color
= reg_undef
;
2057 if (this->frag_color
)
2058 color
= *(variable_storage(this->frag_color
));
2059 else if (this->frag_data
) {
2060 color
= *(variable_storage(this->frag_data
));
2061 color
.type
= BRW_REGISTER_TYPE_F
;
2064 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2065 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
2066 "FB write target %d",
2068 if (this->frag_color
|| this->frag_data
) {
2069 for (int i
= 0; i
< 4; i
++) {
2070 emit(fs_inst(BRW_OPCODE_MOV
,
2071 fs_reg(MRF
, color_mrf
+ i
),
2077 if (this->frag_color
)
2078 color
.reg_offset
-= 4;
2080 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
2081 reg_undef
, reg_undef
));
2082 inst
->target
= target
;
2085 if (target
== c
->key
.nr_color_regions
- 1)
2087 inst
->header_present
= header_present
;
2090 if (c
->key
.nr_color_regions
== 0) {
2091 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
2092 reg_undef
, reg_undef
));
2096 inst
->header_present
= header_present
;
2099 this->current_annotation
= NULL
;
2103 fs_visitor::generate_fb_write(fs_inst
*inst
)
2105 GLboolean eot
= inst
->eot
;
2106 struct brw_reg implied_header
;
2108 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
2111 brw_push_insn_state(p
);
2112 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2113 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2115 if (inst
->header_present
) {
2116 if (intel
->gen
>= 6) {
2118 brw_message_reg(inst
->base_mrf
),
2119 brw_vec8_grf(0, 0));
2121 if (inst
->target
> 0) {
2122 /* Set the render target index for choosing BLEND_STATE. */
2123 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 2),
2124 BRW_REGISTER_TYPE_UD
),
2125 brw_imm_ud(inst
->target
));
2128 /* Clear viewport index, render target array index. */
2129 brw_AND(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 0),
2130 BRW_REGISTER_TYPE_UD
),
2131 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2132 brw_imm_ud(0xf7ff));
2134 implied_header
= brw_null_reg();
2136 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2140 brw_message_reg(inst
->base_mrf
+ 1),
2141 brw_vec8_grf(1, 0));
2143 implied_header
= brw_null_reg();
2146 brw_pop_insn_state(p
);
2149 8, /* dispatch_width */
2150 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
2160 fs_visitor::generate_linterp(fs_inst
*inst
,
2161 struct brw_reg dst
, struct brw_reg
*src
)
2163 struct brw_reg delta_x
= src
[0];
2164 struct brw_reg delta_y
= src
[1];
2165 struct brw_reg interp
= src
[2];
2168 delta_y
.nr
== delta_x
.nr
+ 1 &&
2169 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2170 brw_PLN(p
, dst
, interp
, delta_x
);
2172 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2173 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2178 fs_visitor::generate_math(fs_inst
*inst
,
2179 struct brw_reg dst
, struct brw_reg
*src
)
2183 switch (inst
->opcode
) {
2185 op
= BRW_MATH_FUNCTION_INV
;
2188 op
= BRW_MATH_FUNCTION_RSQ
;
2190 case FS_OPCODE_SQRT
:
2191 op
= BRW_MATH_FUNCTION_SQRT
;
2193 case FS_OPCODE_EXP2
:
2194 op
= BRW_MATH_FUNCTION_EXP
;
2196 case FS_OPCODE_LOG2
:
2197 op
= BRW_MATH_FUNCTION_LOG
;
2200 op
= BRW_MATH_FUNCTION_POW
;
2203 op
= BRW_MATH_FUNCTION_SIN
;
2206 op
= BRW_MATH_FUNCTION_COS
;
2209 assert(!"not reached: unknown math function");
2214 if (intel
->gen
>= 6) {
2215 assert(inst
->mlen
== 0);
2217 if (inst
->opcode
== FS_OPCODE_POW
) {
2218 brw_math2(p
, dst
, op
, src
[0], src
[1]);
2222 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2223 BRW_MATH_SATURATE_NONE
,
2225 BRW_MATH_DATA_VECTOR
,
2226 BRW_MATH_PRECISION_FULL
);
2229 assert(inst
->mlen
>= 1);
2233 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2234 BRW_MATH_SATURATE_NONE
,
2235 inst
->base_mrf
, src
[0],
2236 BRW_MATH_DATA_VECTOR
,
2237 BRW_MATH_PRECISION_FULL
);
2242 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
)
2246 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2248 if (intel
->gen
>= 5) {
2249 switch (inst
->opcode
) {
2251 if (inst
->shadow_compare
) {
2252 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2254 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2258 if (inst
->shadow_compare
) {
2259 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2261 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2266 switch (inst
->opcode
) {
2268 /* Note that G45 and older determines shadow compare and dispatch width
2269 * from message length for most messages.
2271 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2272 if (inst
->shadow_compare
) {
2273 assert(inst
->mlen
== 6);
2275 assert(inst
->mlen
<= 4);
2279 if (inst
->shadow_compare
) {
2280 assert(inst
->mlen
== 6);
2281 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2283 assert(inst
->mlen
== 9);
2284 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2285 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2290 assert(msg_type
!= -1);
2292 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2298 retype(dst
, BRW_REGISTER_TYPE_UW
),
2300 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2301 SURF_INDEX_TEXTURE(inst
->sampler
),
2313 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2316 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2318 * and we're trying to produce:
2321 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2322 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2323 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2324 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2325 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2326 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2327 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2328 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2330 * and add another set of two more subspans if in 16-pixel dispatch mode.
2332 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2333 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2334 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2335 * between each other. We could probably do it like ddx and swizzle the right
2336 * order later, but bail for now and just produce
2337 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2340 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2342 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2343 BRW_REGISTER_TYPE_F
,
2344 BRW_VERTICAL_STRIDE_2
,
2346 BRW_HORIZONTAL_STRIDE_0
,
2347 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2348 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2349 BRW_REGISTER_TYPE_F
,
2350 BRW_VERTICAL_STRIDE_2
,
2352 BRW_HORIZONTAL_STRIDE_0
,
2353 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2354 brw_ADD(p
, dst
, src0
, negate(src1
));
2358 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2360 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2361 BRW_REGISTER_TYPE_F
,
2362 BRW_VERTICAL_STRIDE_4
,
2364 BRW_HORIZONTAL_STRIDE_0
,
2365 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2366 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2367 BRW_REGISTER_TYPE_F
,
2368 BRW_VERTICAL_STRIDE_4
,
2370 BRW_HORIZONTAL_STRIDE_0
,
2371 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2372 brw_ADD(p
, dst
, src0
, negate(src1
));
2376 fs_visitor::generate_discard_not(fs_inst
*inst
, struct brw_reg mask
)
2378 if (intel
->gen
>= 6) {
2379 /* Gen6 no longer has the mask reg for us to just read the
2380 * active channels from. However, cmp updates just the channels
2381 * of the flag reg that are enabled, so we can get at the
2382 * channel enables that way. In this step, make a reg of ones
2385 brw_MOV(p
, mask
, brw_imm_ud(1));
2387 brw_push_insn_state(p
);
2388 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2389 brw_NOT(p
, mask
, brw_mask_reg(1)); /* IMASK */
2390 brw_pop_insn_state(p
);
2395 fs_visitor::generate_discard_and(fs_inst
*inst
, struct brw_reg mask
)
2397 if (intel
->gen
>= 6) {
2398 struct brw_reg f0
= brw_flag_reg();
2399 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
2401 brw_push_insn_state(p
);
2402 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2403 brw_MOV(p
, f0
, brw_imm_uw(0xffff)); /* inactive channels undiscarded */
2404 brw_pop_insn_state(p
);
2406 brw_CMP(p
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
2407 BRW_CONDITIONAL_Z
, mask
, brw_imm_ud(0)); /* active channels fail test */
2408 /* Undo CMP's whacking of predication*/
2409 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2411 brw_push_insn_state(p
);
2412 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2413 brw_AND(p
, g1
, f0
, g1
);
2414 brw_pop_insn_state(p
);
2416 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2418 mask
= brw_uw1_reg(mask
.file
, mask
.nr
, 0);
2420 brw_push_insn_state(p
);
2421 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2422 brw_AND(p
, g0
, mask
, g0
);
2423 brw_pop_insn_state(p
);
2428 fs_visitor::generate_spill(fs_inst
*inst
, struct brw_reg src
)
2430 assert(inst
->mlen
!= 0);
2433 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
2434 retype(src
, BRW_REGISTER_TYPE_UD
));
2435 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
), 1,
2440 fs_visitor::generate_unspill(fs_inst
*inst
, struct brw_reg dst
)
2442 assert(inst
->mlen
!= 0);
2444 /* Clear any post destination dependencies that would be ignored by
2445 * the block read. See the B-Spec for pre-gen5 send instruction.
2447 * This could use a better solution, since texture sampling and
2448 * math reads could potentially run into it as well -- anywhere
2449 * that we have a SEND with a destination that is a register that
2450 * was written but not read within the last N instructions (what's
2451 * N? unsure). This is rare because of dead code elimination, but
2454 if (intel
->gen
== 4 && !intel
->is_g4x
)
2455 brw_MOV(p
, brw_null_reg(), dst
);
2457 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
), 1,
2460 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2461 /* gen4 errata: destination from a send can't be used as a
2462 * destination until it's been read. Just read it so we don't
2465 brw_MOV(p
, brw_null_reg(), dst
);
2471 fs_visitor::generate_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
)
2473 assert(inst
->mlen
!= 0);
2475 /* Clear any post destination dependencies that would be ignored by
2476 * the block read. See the B-Spec for pre-gen5 send instruction.
2478 * This could use a better solution, since texture sampling and
2479 * math reads could potentially run into it as well -- anywhere
2480 * that we have a SEND with a destination that is a register that
2481 * was written but not read within the last N instructions (what's
2482 * N? unsure). This is rare because of dead code elimination, but
2485 if (intel
->gen
== 4 && !intel
->is_g4x
)
2486 brw_MOV(p
, brw_null_reg(), dst
);
2488 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
2489 inst
->offset
, SURF_INDEX_FRAG_CONST_BUFFER
);
2491 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2492 /* gen4 errata: destination from a send can't be used as a
2493 * destination until it's been read. Just read it so we don't
2496 brw_MOV(p
, brw_null_reg(), dst
);
2501 fs_visitor::assign_curb_setup()
2503 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
2504 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2506 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2507 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2508 fs_inst
*inst
= (fs_inst
*)iter
.get();
2510 for (unsigned int i
= 0; i
< 3; i
++) {
2511 if (inst
->src
[i
].file
== UNIFORM
) {
2512 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2513 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2517 inst
->src
[i
].file
= FIXED_HW_REG
;
2518 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
2525 fs_visitor::calculate_urb_setup()
2527 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2532 /* Figure out where each of the incoming setup attributes lands. */
2533 if (intel
->gen
>= 6) {
2534 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2535 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2536 urb_setup
[i
] = urb_next
++;
2540 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2541 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2542 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2545 if (i
>= VERT_RESULT_VAR0
)
2546 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2547 else if (i
<= VERT_RESULT_TEX7
)
2553 urb_setup
[fp_index
] = urb_next
++;
2558 /* Each attribute is 4 setup channels, each of which is half a reg. */
2559 c
->prog_data
.urb_read_length
= urb_next
* 2;
2563 fs_visitor::assign_urb_setup()
2565 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2567 /* Offset all the urb_setup[] index by the actual position of the
2568 * setup regs, now that the location of the constants has been chosen.
2570 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2571 fs_inst
*inst
= (fs_inst
*)iter
.get();
2573 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2576 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2578 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2581 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2585 * Split large virtual GRFs into separate components if we can.
2587 * This is mostly duplicated with what brw_fs_vector_splitting does,
2588 * but that's really conservative because it's afraid of doing
2589 * splitting that doesn't result in real progress after the rest of
2590 * the optimization phases, which would cause infinite looping in
2591 * optimization. We can do it once here, safely. This also has the
2592 * opportunity to split interpolated values, or maybe even uniforms,
2593 * which we don't have at the IR level.
2595 * We want to split, because virtual GRFs are what we register
2596 * allocate and spill (due to contiguousness requirements for some
2597 * instructions), and they're what we naturally generate in the
2598 * codegen process, but most virtual GRFs don't actually need to be
2599 * contiguous sets of GRFs. If we split, we'll end up with reduced
2600 * live intervals and better dead code elimination and coalescing.
2603 fs_visitor::split_virtual_grfs()
2605 int num_vars
= this->virtual_grf_next
;
2606 bool split_grf
[num_vars
];
2607 int new_virtual_grf
[num_vars
];
2609 /* Try to split anything > 0 sized. */
2610 for (int i
= 0; i
< num_vars
; i
++) {
2611 if (this->virtual_grf_sizes
[i
] != 1)
2612 split_grf
[i
] = true;
2614 split_grf
[i
] = false;
2618 /* PLN opcodes rely on the delta_xy being contiguous. */
2619 split_grf
[this->delta_x
.reg
] = false;
2622 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2623 fs_inst
*inst
= (fs_inst
*)iter
.get();
2625 /* Texturing produces 4 contiguous registers, so no splitting. */
2626 if ((inst
->opcode
== FS_OPCODE_TEX
||
2627 inst
->opcode
== FS_OPCODE_TXB
||
2628 inst
->opcode
== FS_OPCODE_TXL
) &&
2629 inst
->dst
.file
== GRF
) {
2630 split_grf
[inst
->dst
.reg
] = false;
2634 /* Allocate new space for split regs. Note that the virtual
2635 * numbers will be contiguous.
2637 for (int i
= 0; i
< num_vars
; i
++) {
2639 new_virtual_grf
[i
] = virtual_grf_alloc(1);
2640 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
2641 int reg
= virtual_grf_alloc(1);
2642 assert(reg
== new_virtual_grf
[i
] + j
- 1);
2645 this->virtual_grf_sizes
[i
] = 1;
2649 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2650 fs_inst
*inst
= (fs_inst
*)iter
.get();
2652 if (inst
->dst
.file
== GRF
&&
2653 split_grf
[inst
->dst
.reg
] &&
2654 inst
->dst
.reg_offset
!= 0) {
2655 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
2656 inst
->dst
.reg_offset
- 1);
2657 inst
->dst
.reg_offset
= 0;
2659 for (int i
= 0; i
< 3; i
++) {
2660 if (inst
->src
[i
].file
== GRF
&&
2661 split_grf
[inst
->src
[i
].reg
] &&
2662 inst
->src
[i
].reg_offset
!= 0) {
2663 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
2664 inst
->src
[i
].reg_offset
- 1);
2665 inst
->src
[i
].reg_offset
= 0;
2672 * Choose accesses from the UNIFORM file to demote to using the pull
2675 * We allow a fragment shader to have more than the specified minimum
2676 * maximum number of fragment shader uniform components (64). If
2677 * there are too many of these, they'd fill up all of register space.
2678 * So, this will push some of them out to the pull constant buffer and
2679 * update the program to load them.
2682 fs_visitor::setup_pull_constants()
2684 /* Only allow 16 registers (128 uniform components) as push constants. */
2685 unsigned int max_uniform_components
= 16 * 8;
2686 if (c
->prog_data
.nr_params
<= max_uniform_components
)
2689 /* Just demote the end of the list. We could probably do better
2690 * here, demoting things that are rarely used in the program first.
2692 int pull_uniform_base
= max_uniform_components
;
2693 int pull_uniform_count
= c
->prog_data
.nr_params
- pull_uniform_base
;
2695 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2696 fs_inst
*inst
= (fs_inst
*)iter
.get();
2698 for (int i
= 0; i
< 3; i
++) {
2699 if (inst
->src
[i
].file
!= UNIFORM
)
2702 int uniform_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2703 if (uniform_nr
< pull_uniform_base
)
2706 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
2707 fs_inst
*pull
= new(mem_ctx
) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
2709 pull
->offset
= ((uniform_nr
- pull_uniform_base
) * 4) & ~15;
2710 pull
->ir
= inst
->ir
;
2711 pull
->annotation
= inst
->annotation
;
2712 pull
->base_mrf
= 14;
2715 inst
->insert_before(pull
);
2717 inst
->src
[i
].file
= GRF
;
2718 inst
->src
[i
].reg
= dst
.reg
;
2719 inst
->src
[i
].reg_offset
= 0;
2720 inst
->src
[i
].smear
= (uniform_nr
- pull_uniform_base
) & 3;
2724 for (int i
= 0; i
< pull_uniform_count
; i
++) {
2725 c
->prog_data
.pull_param
[i
] = c
->prog_data
.param
[pull_uniform_base
+ i
];
2726 c
->prog_data
.pull_param_convert
[i
] =
2727 c
->prog_data
.param_convert
[pull_uniform_base
+ i
];
2729 c
->prog_data
.nr_params
-= pull_uniform_count
;
2730 c
->prog_data
.nr_pull_params
= pull_uniform_count
;
2734 fs_visitor::calculate_live_intervals()
2736 int num_vars
= this->virtual_grf_next
;
2737 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2738 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2741 int bb_header_ip
= 0;
2743 for (int i
= 0; i
< num_vars
; i
++) {
2749 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2750 fs_inst
*inst
= (fs_inst
*)iter
.get();
2752 if (inst
->opcode
== BRW_OPCODE_DO
) {
2753 if (loop_depth
++ == 0)
2755 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2758 if (loop_depth
== 0) {
2759 /* Patches up the use of vars marked for being live across
2762 for (int i
= 0; i
< num_vars
; i
++) {
2763 if (use
[i
] == loop_start
) {
2769 for (unsigned int i
= 0; i
< 3; i
++) {
2770 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2771 int reg
= inst
->src
[i
].reg
;
2773 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2774 def
[reg
] >= bb_header_ip
)) {
2777 def
[reg
] = MIN2(loop_start
, def
[reg
]);
2778 use
[reg
] = loop_start
;
2780 /* Nobody else is going to go smash our start to
2781 * later in the loop now, because def[reg] now
2782 * points before the bb header.
2787 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2788 int reg
= inst
->dst
.reg
;
2790 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2791 !inst
->predicated
)) {
2792 def
[reg
] = MIN2(def
[reg
], ip
);
2794 def
[reg
] = MIN2(def
[reg
], loop_start
);
2801 /* Set the basic block header IP. This is used for determining
2802 * if a complete def of single-register virtual GRF in a loop
2803 * dominates a use in the same basic block. It's a quick way to
2804 * reduce the live interval range of most register used in a
2807 if (inst
->opcode
== BRW_OPCODE_IF
||
2808 inst
->opcode
== BRW_OPCODE_ELSE
||
2809 inst
->opcode
== BRW_OPCODE_ENDIF
||
2810 inst
->opcode
== BRW_OPCODE_DO
||
2811 inst
->opcode
== BRW_OPCODE_WHILE
||
2812 inst
->opcode
== BRW_OPCODE_BREAK
||
2813 inst
->opcode
== BRW_OPCODE_CONTINUE
) {
2818 talloc_free(this->virtual_grf_def
);
2819 talloc_free(this->virtual_grf_use
);
2820 this->virtual_grf_def
= def
;
2821 this->virtual_grf_use
= use
;
2825 * Attempts to move immediate constants into the immediate
2826 * constant slot of following instructions.
2828 * Immediate constants are a bit tricky -- they have to be in the last
2829 * operand slot, you can't do abs/negate on them,
2833 fs_visitor::propagate_constants()
2835 bool progress
= false;
2837 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2838 fs_inst
*inst
= (fs_inst
*)iter
.get();
2840 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2842 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2843 inst
->dst
.type
!= inst
->src
[0].type
)
2846 /* Don't bother with cases where we should have had the
2847 * operation on the constant folded in GLSL already.
2852 /* Found a move of a constant to a GRF. Find anything else using the GRF
2853 * before it's written, and replace it with the constant if we can.
2855 exec_list_iterator scan_iter
= iter
;
2857 for (; scan_iter
.has_next(); scan_iter
.next()) {
2858 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2860 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2861 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2862 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2863 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2867 for (int i
= 2; i
>= 0; i
--) {
2868 if (scan_inst
->src
[i
].file
!= GRF
||
2869 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2870 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2873 /* Don't bother with cases where we should have had the
2874 * operation on the constant folded in GLSL already.
2876 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2879 switch (scan_inst
->opcode
) {
2880 case BRW_OPCODE_MOV
:
2881 scan_inst
->src
[i
] = inst
->src
[0];
2885 case BRW_OPCODE_MUL
:
2886 case BRW_OPCODE_ADD
:
2888 scan_inst
->src
[i
] = inst
->src
[0];
2890 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2891 /* Fit this constant in by commuting the operands */
2892 scan_inst
->src
[0] = scan_inst
->src
[1];
2893 scan_inst
->src
[1] = inst
->src
[0];
2896 case BRW_OPCODE_CMP
:
2897 case BRW_OPCODE_SEL
:
2899 scan_inst
->src
[i
] = inst
->src
[0];
2905 if (scan_inst
->dst
.file
== GRF
&&
2906 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2907 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2908 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2917 * Must be called after calculate_live_intervales() to remove unused
2918 * writes to registers -- register allocation will fail otherwise
2919 * because something deffed but not used won't be considered to
2920 * interfere with other regs.
2923 fs_visitor::dead_code_eliminate()
2925 bool progress
= false;
2928 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2929 fs_inst
*inst
= (fs_inst
*)iter
.get();
2931 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
2943 fs_visitor::register_coalesce()
2945 bool progress
= false;
2947 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2948 fs_inst
*inst
= (fs_inst
*)iter
.get();
2950 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2953 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
2954 inst
->dst
.type
!= inst
->src
[0].type
)
2957 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
2958 * them: check for no writes to either one until the exit of the
2961 bool interfered
= false;
2962 exec_list_iterator scan_iter
= iter
;
2964 for (; scan_iter
.has_next(); scan_iter
.next()) {
2965 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2967 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2968 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2969 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2975 if (scan_inst
->dst
.file
== GRF
) {
2976 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2977 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2978 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2982 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
2983 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
2984 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2994 /* Update live interval so we don't have to recalculate. */
2995 this->virtual_grf_use
[inst
->src
[0].reg
] = MAX2(virtual_grf_use
[inst
->src
[0].reg
],
2996 virtual_grf_use
[inst
->dst
.reg
]);
2998 /* Rewrite the later usage to point at the source of the move to
3001 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
3003 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
3005 for (int i
= 0; i
< 3; i
++) {
3006 if (scan_inst
->src
[i
].file
== GRF
&&
3007 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
3008 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
3009 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
3010 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
3011 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
3012 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
3013 scan_inst
->src
[i
].smear
= inst
->src
[0].smear
;
3027 fs_visitor::compute_to_mrf()
3029 bool progress
= false;
3032 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3033 fs_inst
*inst
= (fs_inst
*)iter
.get();
3038 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3040 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
3041 inst
->dst
.type
!= inst
->src
[0].type
||
3042 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
3045 /* Can't compute-to-MRF this GRF if someone else was going to
3048 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
3051 /* Found a move of a GRF to a MRF. Let's see if we can go
3052 * rewrite the thing that made this GRF to write into the MRF.
3055 for (scan_inst
= (fs_inst
*)inst
->prev
;
3056 scan_inst
->prev
!= NULL
;
3057 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
3058 if (scan_inst
->dst
.file
== GRF
&&
3059 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
3060 /* Found the last thing to write our reg we want to turn
3061 * into a compute-to-MRF.
3064 if (scan_inst
->opcode
== FS_OPCODE_TEX
) {
3065 /* texturing writes several continuous regs, so we can't
3066 * compute-to-mrf that.
3071 /* If it's predicated, it (probably) didn't populate all
3074 if (scan_inst
->predicated
)
3077 /* SEND instructions can't have MRF as a destination. */
3078 if (scan_inst
->mlen
)
3081 if (intel
->gen
>= 6) {
3082 /* gen6 math instructions must have the destination be
3083 * GRF, so no compute-to-MRF for them.
3085 if (scan_inst
->opcode
== FS_OPCODE_RCP
||
3086 scan_inst
->opcode
== FS_OPCODE_RSQ
||
3087 scan_inst
->opcode
== FS_OPCODE_SQRT
||
3088 scan_inst
->opcode
== FS_OPCODE_EXP2
||
3089 scan_inst
->opcode
== FS_OPCODE_LOG2
||
3090 scan_inst
->opcode
== FS_OPCODE_SIN
||
3091 scan_inst
->opcode
== FS_OPCODE_COS
||
3092 scan_inst
->opcode
== FS_OPCODE_POW
) {
3097 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
3098 /* Found the creator of our MRF's source value. */
3099 scan_inst
->dst
.file
= MRF
;
3100 scan_inst
->dst
.hw_reg
= inst
->dst
.hw_reg
;
3101 scan_inst
->saturate
|= inst
->saturate
;
3108 /* We don't handle flow control here. Most computation of
3109 * values that end up in MRFs are shortly before the MRF
3112 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
3113 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
3114 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
3118 /* You can't read from an MRF, so if someone else reads our
3119 * MRF's source GRF that we wanted to rewrite, that stops us.
3121 bool interfered
= false;
3122 for (int i
= 0; i
< 3; i
++) {
3123 if (scan_inst
->src
[i
].file
== GRF
&&
3124 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
3125 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
3132 if (scan_inst
->dst
.file
== MRF
&&
3133 scan_inst
->dst
.hw_reg
== inst
->dst
.hw_reg
) {
3134 /* Somebody else wrote our MRF here, so we can't can't
3135 * compute-to-MRF before that.
3140 if (scan_inst
->mlen
> 0) {
3141 /* Found a SEND instruction, which means that there are
3142 * live values in MRFs from base_mrf to base_mrf +
3143 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3146 if (inst
->dst
.hw_reg
>= scan_inst
->base_mrf
&&
3147 inst
->dst
.hw_reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
3158 * Walks through basic blocks, locking for repeated MRF writes and
3159 * removing the later ones.
3162 fs_visitor::remove_duplicate_mrf_writes()
3164 fs_inst
*last_mrf_move
[16];
3165 bool progress
= false;
3167 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3169 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3170 fs_inst
*inst
= (fs_inst
*)iter
.get();
3172 switch (inst
->opcode
) {
3174 case BRW_OPCODE_WHILE
:
3176 case BRW_OPCODE_ELSE
:
3177 case BRW_OPCODE_ENDIF
:
3178 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3184 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3185 inst
->dst
.file
== MRF
) {
3186 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.hw_reg
];
3187 if (prev_inst
&& inst
->equals(prev_inst
)) {
3194 /* Clear out the last-write records for MRFs that were overwritten. */
3195 if (inst
->dst
.file
== MRF
) {
3196 last_mrf_move
[inst
->dst
.hw_reg
] = NULL
;
3199 if (inst
->mlen
> 0) {
3200 /* Found a SEND instruction, which will include two of fewer
3201 * implied MRF writes. We could do better here.
3203 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3204 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3208 /* Clear out any MRF move records whose sources got overwritten. */
3209 if (inst
->dst
.file
== GRF
) {
3210 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
3211 if (last_mrf_move
[i
] &&
3212 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
3213 last_mrf_move
[i
] = NULL
;
3218 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3219 inst
->dst
.file
== MRF
&&
3220 inst
->src
[0].file
== GRF
&&
3221 !inst
->predicated
) {
3222 last_mrf_move
[inst
->dst
.hw_reg
] = inst
;
3230 fs_visitor::virtual_grf_interferes(int a
, int b
)
3232 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
3233 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
3235 /* For dead code, just check if the def interferes with the other range. */
3236 if (this->virtual_grf_use
[a
] == -1) {
3237 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
3238 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
3240 if (this->virtual_grf_use
[b
] == -1) {
3241 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
3242 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
3248 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
3250 struct brw_reg brw_reg
;
3252 switch (reg
->file
) {
3256 if (reg
->smear
== -1) {
3257 brw_reg
= brw_vec8_reg(reg
->file
,
3260 brw_reg
= brw_vec1_reg(reg
->file
,
3261 reg
->hw_reg
, reg
->smear
);
3263 brw_reg
= retype(brw_reg
, reg
->type
);
3266 switch (reg
->type
) {
3267 case BRW_REGISTER_TYPE_F
:
3268 brw_reg
= brw_imm_f(reg
->imm
.f
);
3270 case BRW_REGISTER_TYPE_D
:
3271 brw_reg
= brw_imm_d(reg
->imm
.i
);
3273 case BRW_REGISTER_TYPE_UD
:
3274 brw_reg
= brw_imm_ud(reg
->imm
.u
);
3277 assert(!"not reached");
3282 brw_reg
= reg
->fixed_hw_reg
;
3285 /* Probably unused. */
3286 brw_reg
= brw_null_reg();
3289 assert(!"not reached");
3290 brw_reg
= brw_null_reg();
3294 brw_reg
= brw_abs(brw_reg
);
3296 brw_reg
= negate(brw_reg
);
3302 fs_visitor::generate_code()
3304 int last_native_inst
= 0;
3305 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
3306 int if_stack_depth
= 0, loop_stack_depth
= 0;
3307 int if_depth_in_loop
[16];
3308 const char *last_annotation_string
= NULL
;
3309 ir_instruction
*last_annotation_ir
= NULL
;
3311 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3312 printf("Native code for fragment shader %d:\n",
3313 ctx
->Shader
.CurrentFragmentProgram
->Name
);
3316 if_depth_in_loop
[loop_stack_depth
] = 0;
3318 memset(&if_stack
, 0, sizeof(if_stack
));
3319 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3320 fs_inst
*inst
= (fs_inst
*)iter
.get();
3321 struct brw_reg src
[3], dst
;
3323 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3324 if (last_annotation_ir
!= inst
->ir
) {
3325 last_annotation_ir
= inst
->ir
;
3326 if (last_annotation_ir
) {
3328 last_annotation_ir
->print();
3332 if (last_annotation_string
!= inst
->annotation
) {
3333 last_annotation_string
= inst
->annotation
;
3334 if (last_annotation_string
)
3335 printf(" %s\n", last_annotation_string
);
3339 for (unsigned int i
= 0; i
< 3; i
++) {
3340 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
3342 dst
= brw_reg_from_fs_reg(&inst
->dst
);
3344 brw_set_conditionalmod(p
, inst
->conditional_mod
);
3345 brw_set_predicate_control(p
, inst
->predicated
);
3346 brw_set_saturate(p
, inst
->saturate
);
3348 switch (inst
->opcode
) {
3349 case BRW_OPCODE_MOV
:
3350 brw_MOV(p
, dst
, src
[0]);
3352 case BRW_OPCODE_ADD
:
3353 brw_ADD(p
, dst
, src
[0], src
[1]);
3355 case BRW_OPCODE_MUL
:
3356 brw_MUL(p
, dst
, src
[0], src
[1]);
3359 case BRW_OPCODE_FRC
:
3360 brw_FRC(p
, dst
, src
[0]);
3362 case BRW_OPCODE_RNDD
:
3363 brw_RNDD(p
, dst
, src
[0]);
3365 case BRW_OPCODE_RNDE
:
3366 brw_RNDE(p
, dst
, src
[0]);
3368 case BRW_OPCODE_RNDZ
:
3369 brw_RNDZ(p
, dst
, src
[0]);
3372 case BRW_OPCODE_AND
:
3373 brw_AND(p
, dst
, src
[0], src
[1]);
3376 brw_OR(p
, dst
, src
[0], src
[1]);
3378 case BRW_OPCODE_XOR
:
3379 brw_XOR(p
, dst
, src
[0], src
[1]);
3381 case BRW_OPCODE_NOT
:
3382 brw_NOT(p
, dst
, src
[0]);
3384 case BRW_OPCODE_ASR
:
3385 brw_ASR(p
, dst
, src
[0], src
[1]);
3387 case BRW_OPCODE_SHR
:
3388 brw_SHR(p
, dst
, src
[0], src
[1]);
3390 case BRW_OPCODE_SHL
:
3391 brw_SHL(p
, dst
, src
[0], src
[1]);
3394 case BRW_OPCODE_CMP
:
3395 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
3397 case BRW_OPCODE_SEL
:
3398 brw_SEL(p
, dst
, src
[0], src
[1]);
3402 assert(if_stack_depth
< 16);
3403 if (inst
->src
[0].file
!= BAD_FILE
) {
3404 assert(intel
->gen
>= 6);
3405 if_stack
[if_stack_depth
] = brw_IF_gen6(p
, inst
->conditional_mod
, src
[0], src
[1]);
3407 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
3409 if_depth_in_loop
[loop_stack_depth
]++;
3413 case BRW_OPCODE_ELSE
:
3414 if_stack
[if_stack_depth
- 1] =
3415 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
3417 case BRW_OPCODE_ENDIF
:
3419 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
3420 if_depth_in_loop
[loop_stack_depth
]--;
3424 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
3425 if_depth_in_loop
[loop_stack_depth
] = 0;
3428 case BRW_OPCODE_BREAK
:
3429 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
3430 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3432 case BRW_OPCODE_CONTINUE
:
3433 /* FINISHME: We need to write the loop instruction support still. */
3434 if (intel
->gen
>= 6)
3435 brw_CONT_gen6(p
, loop_stack
[loop_stack_depth
- 1]);
3437 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
3438 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3441 case BRW_OPCODE_WHILE
: {
3442 struct brw_instruction
*inst0
, *inst1
;
3445 if (intel
->gen
>= 5)
3448 assert(loop_stack_depth
> 0);
3450 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
3451 if (intel
->gen
< 6) {
3452 /* patch all the BREAK/CONT instructions from last BGNLOOP */
3453 while (inst0
> loop_stack
[loop_stack_depth
]) {
3455 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
3456 inst0
->bits3
.if_else
.jump_count
== 0) {
3457 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
3459 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
3460 inst0
->bits3
.if_else
.jump_count
== 0) {
3461 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
3470 case FS_OPCODE_SQRT
:
3471 case FS_OPCODE_EXP2
:
3472 case FS_OPCODE_LOG2
:
3476 generate_math(inst
, dst
, src
);
3478 case FS_OPCODE_LINTERP
:
3479 generate_linterp(inst
, dst
, src
);
3484 generate_tex(inst
, dst
);
3486 case FS_OPCODE_DISCARD_NOT
:
3487 generate_discard_not(inst
, dst
);
3489 case FS_OPCODE_DISCARD_AND
:
3490 generate_discard_and(inst
, src
[0]);
3493 generate_ddx(inst
, dst
, src
[0]);
3496 generate_ddy(inst
, dst
, src
[0]);
3499 case FS_OPCODE_SPILL
:
3500 generate_spill(inst
, src
[0]);
3503 case FS_OPCODE_UNSPILL
:
3504 generate_unspill(inst
, dst
);
3507 case FS_OPCODE_PULL_CONSTANT_LOAD
:
3508 generate_pull_constant_load(inst
, dst
);
3511 case FS_OPCODE_FB_WRITE
:
3512 generate_fb_write(inst
);
3515 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
3516 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
3517 brw_opcodes
[inst
->opcode
].name
);
3519 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
3524 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3525 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
3527 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3528 ((uint32_t *)&p
->store
[i
])[3],
3529 ((uint32_t *)&p
->store
[i
])[2],
3530 ((uint32_t *)&p
->store
[i
])[1],
3531 ((uint32_t *)&p
->store
[i
])[0]);
3533 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3537 last_native_inst
= p
->nr_insn
;
3542 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
3543 * emit issues, it doesn't get the jump distances into the output,
3544 * which is often something we want to debug. So this is here in
3545 * case you're doing that.
3548 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3549 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3550 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3551 ((uint32_t *)&p
->store
[i
])[3],
3552 ((uint32_t *)&p
->store
[i
])[2],
3553 ((uint32_t *)&p
->store
[i
])[1],
3554 ((uint32_t *)&p
->store
[i
])[0]);
3555 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3562 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
3564 struct intel_context
*intel
= &brw
->intel
;
3565 struct gl_context
*ctx
= &intel
->ctx
;
3566 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentFragmentProgram
;
3571 struct brw_shader
*shader
=
3572 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3576 /* We always use 8-wide mode, at least for now. For one, flow
3577 * control only works in 8-wide. Also, when we're fragment shader
3578 * bound, we're almost always under register pressure as well, so
3579 * 8-wide would save us from the performance cliff of spilling
3582 c
->dispatch_width
= 8;
3584 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3585 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3586 _mesa_print_ir(shader
->ir
, NULL
);
3590 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3592 fs_visitor
v(c
, shader
);
3597 v
.calculate_urb_setup();
3599 v
.emit_interpolation_setup_gen4();
3601 v
.emit_interpolation_setup_gen6();
3603 /* Generate FS IR for main(). (the visitor only descends into
3604 * functions called "main").
3606 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3607 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3614 v
.split_virtual_grfs();
3615 v
.setup_pull_constants();
3617 v
.assign_curb_setup();
3618 v
.assign_urb_setup();
3624 progress
= v
.remove_duplicate_mrf_writes() || progress
;
3626 v
.calculate_live_intervals();
3627 progress
= v
.propagate_constants() || progress
;
3628 progress
= v
.register_coalesce() || progress
;
3629 progress
= v
.compute_to_mrf() || progress
;
3630 progress
= v
.dead_code_eliminate() || progress
;
3634 /* Debug of register spilling: Go spill everything. */
3635 int virtual_grf_count
= v
.virtual_grf_next
;
3636 for (int i
= 1; i
< virtual_grf_count
; i
++) {
3639 v
.calculate_live_intervals();
3643 v
.assign_regs_trivial();
3645 while (!v
.assign_regs()) {
3649 v
.calculate_live_intervals();
3657 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3662 c
->prog_data
.total_grf
= v
.grf_used
;