2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "brw_dead_control_flow.h"
47 #include "main/uniforms.h"
48 #include "brw_fs_live_variables.h"
49 #include "glsl/glsl_types.h"
50 #include "program/sampler.h"
55 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
56 const fs_reg
*src
, unsigned sources
)
58 memset(this, 0, sizeof(*this));
60 this->src
= new fs_reg
[MAX2(sources
, 3)];
61 for (unsigned i
= 0; i
< sources
; i
++)
62 this->src
[i
] = src
[i
];
64 this->opcode
= opcode
;
66 this->sources
= sources
;
67 this->exec_size
= exec_size
;
69 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
71 assert(this->exec_size
!= 0);
73 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
75 /* This will be the case for almost all instructions. */
81 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
85 this->regs_written
= 0;
89 unreachable("Invalid destination register file");
91 unreachable("Invalid register file");
94 this->writes_accumulator
= false;
99 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
104 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
107 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
109 init(opcode
, exec_size
, dst
, NULL
, 0);
112 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
115 const fs_reg src
[1] = { src0
};
116 init(opcode
, exec_size
, dst
, src
, 1);
119 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
120 const fs_reg
&src0
, const fs_reg
&src1
)
122 const fs_reg src
[2] = { src0
, src1
};
123 init(opcode
, exec_size
, dst
, src
, 2);
126 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
127 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
129 const fs_reg src
[3] = { src0
, src1
, src2
};
130 init(opcode
, exec_size
, dst
, src
, 3);
133 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
134 const fs_reg src
[], unsigned sources
)
136 init(opcode
, exec_width
, dst
, src
, sources
);
139 fs_inst::fs_inst(const fs_inst
&that
)
141 memcpy(this, &that
, sizeof(that
));
143 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
145 for (unsigned i
= 0; i
< that
.sources
; i
++)
146 this->src
[i
] = that
.src
[i
];
155 fs_inst::resize_sources(uint8_t num_sources
)
157 if (this->sources
!= num_sources
) {
158 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
160 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
161 src
[i
] = this->src
[i
];
165 this->sources
= num_sources
;
170 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
172 const fs_reg
&surf_index
,
173 const fs_reg
&varying_offset
,
174 uint32_t const_offset
)
176 /* We have our constant surface use a pitch of 4 bytes, so our index can
177 * be any component of a vector, and then we load 4 contiguous
178 * components starting from that.
180 * We break down the const_offset to a portion added to the variable
181 * offset and a portion done using reg_offset, which means that if you
182 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
183 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
184 * CSE can later notice that those loads are all the same and eliminate
185 * the redundant ones.
187 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
188 bld
.ADD(vec4_offset
, varying_offset
, fs_reg(const_offset
& ~3));
191 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
192 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
193 * u, v, r) as parameters, or we can just use the SIMD16 message
194 * consisting of (header, u). We choose the second, at the cost of a
195 * longer return length.
201 if (devinfo
->gen
>= 7)
202 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
204 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
206 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
207 fs_reg vec4_result
= fs_reg(GRF
, alloc
.allocate(regs_written
), dst
.type
);
208 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
209 inst
->regs_written
= regs_written
;
211 if (devinfo
->gen
< 7) {
213 inst
->header_size
= 1;
214 if (devinfo
->gen
== 4)
217 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
220 bld
.MOV(dst
, offset(vec4_result
, bld
, (const_offset
& 3) * scale
));
224 * A helper for MOV generation for fixing up broken hardware SEND dependency
228 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
230 /* The caller always wants uncompressed to emit the minimal extra
231 * dependencies, and to avoid having to deal with aligning its regs to 2.
233 const fs_builder ubld
= bld
.annotate("send dependency resolve")
236 ubld
.MOV(ubld
.null_reg_f(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
240 fs_inst::equals(fs_inst
*inst
) const
242 return (opcode
== inst
->opcode
&&
243 dst
.equals(inst
->dst
) &&
244 src
[0].equals(inst
->src
[0]) &&
245 src
[1].equals(inst
->src
[1]) &&
246 src
[2].equals(inst
->src
[2]) &&
247 saturate
== inst
->saturate
&&
248 predicate
== inst
->predicate
&&
249 conditional_mod
== inst
->conditional_mod
&&
250 mlen
== inst
->mlen
&&
251 base_mrf
== inst
->base_mrf
&&
252 target
== inst
->target
&&
254 header_size
== inst
->header_size
&&
255 shadow_compare
== inst
->shadow_compare
&&
256 exec_size
== inst
->exec_size
&&
257 offset
== inst
->offset
);
261 fs_inst::overwrites_reg(const fs_reg
®
) const
263 return reg
.in_range(dst
, regs_written
);
267 fs_inst::is_send_from_grf() const
270 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
271 case SHADER_OPCODE_SHADER_TIME_ADD
:
272 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
273 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
274 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
275 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
276 case SHADER_OPCODE_UNTYPED_ATOMIC
:
277 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
278 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
279 case SHADER_OPCODE_TYPED_ATOMIC
:
280 case SHADER_OPCODE_TYPED_SURFACE_READ
:
281 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
282 case SHADER_OPCODE_URB_WRITE_SIMD8
:
284 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
285 return src
[1].file
== GRF
;
286 case FS_OPCODE_FB_WRITE
:
287 return src
[0].file
== GRF
;
290 return src
[0].file
== GRF
;
297 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
299 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
302 fs_reg reg
= this->src
[0];
303 if (reg
.file
!= GRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
306 if (grf_alloc
.sizes
[reg
.reg
] != this->regs_written
)
309 for (int i
= 0; i
< this->sources
; i
++) {
310 reg
.type
= this->src
[i
].type
;
311 if (!this->src
[i
].equals(reg
))
314 if (i
< this->header_size
) {
317 reg
.reg_offset
+= this->exec_size
/ 8;
325 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
327 if (devinfo
->gen
== 6 && is_math())
330 if (is_send_from_grf())
333 if (!backend_instruction::can_do_source_mods())
340 fs_inst::has_side_effects() const
342 return this->eot
|| backend_instruction::has_side_effects();
348 memset(this, 0, sizeof(*this));
352 /** Generic unset register constructor. */
356 this->file
= BAD_FILE
;
359 /** Immediate value constructor. */
360 fs_reg::fs_reg(float f
)
364 this->type
= BRW_REGISTER_TYPE_F
;
366 this->fixed_hw_reg
.dw1
.f
= f
;
369 /** Immediate value constructor. */
370 fs_reg::fs_reg(int32_t i
)
374 this->type
= BRW_REGISTER_TYPE_D
;
376 this->fixed_hw_reg
.dw1
.d
= i
;
379 /** Immediate value constructor. */
380 fs_reg::fs_reg(uint32_t u
)
384 this->type
= BRW_REGISTER_TYPE_UD
;
386 this->fixed_hw_reg
.dw1
.ud
= u
;
389 /** Vector float immediate value constructor. */
390 fs_reg::fs_reg(uint8_t vf
[4])
394 this->type
= BRW_REGISTER_TYPE_VF
;
395 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
398 /** Vector float immediate value constructor. */
399 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
403 this->type
= BRW_REGISTER_TYPE_VF
;
404 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
410 /** Fixed brw_reg. */
411 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
415 this->fixed_hw_reg
= fixed_hw_reg
;
416 this->type
= fixed_hw_reg
.type
;
420 fs_reg::equals(const fs_reg
&r
) const
422 return (file
== r
.file
&&
424 reg_offset
== r
.reg_offset
&&
425 subreg_offset
== r
.subreg_offset
&&
427 negate
== r
.negate
&&
429 !reladdr
&& !r
.reladdr
&&
430 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
, sizeof(fixed_hw_reg
)) == 0 &&
435 fs_reg::set_smear(unsigned subreg
)
437 assert(file
!= HW_REG
&& file
!= IMM
);
438 subreg_offset
= subreg
* type_sz(type
);
444 fs_reg::is_contiguous() const
450 fs_reg::component_size(unsigned width
) const
452 const unsigned stride
= (file
!= HW_REG
? this->stride
:
453 fixed_hw_reg
.hstride
== 0 ? 0 :
454 1 << (fixed_hw_reg
.hstride
- 1));
455 return MAX2(width
* stride
, 1) * type_sz(type
);
459 fs_visitor::type_size(const struct glsl_type
*type
)
461 unsigned int size
, i
;
463 switch (type
->base_type
) {
466 case GLSL_TYPE_FLOAT
:
468 return type
->components();
469 case GLSL_TYPE_ARRAY
:
470 return type_size(type
->fields
.array
) * type
->length
;
471 case GLSL_TYPE_STRUCT
:
473 for (i
= 0; i
< type
->length
; i
++) {
474 size
+= type_size(type
->fields
.structure
[i
].type
);
477 case GLSL_TYPE_SAMPLER
:
478 /* Samplers take up no register space, since they're baked in at
482 case GLSL_TYPE_ATOMIC_UINT
:
484 case GLSL_TYPE_SUBROUTINE
:
486 case GLSL_TYPE_IMAGE
:
488 case GLSL_TYPE_ERROR
:
489 case GLSL_TYPE_INTERFACE
:
490 case GLSL_TYPE_DOUBLE
:
491 unreachable("not reached");
498 * Create a MOV to read the timestamp register.
500 * The caller is responsible for emitting the MOV. The return value is
501 * the destination of the MOV, with extra parameters set.
504 fs_visitor::get_timestamp(const fs_builder
&bld
)
506 assert(devinfo
->gen
>= 7);
508 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
511 BRW_REGISTER_TYPE_UD
));
513 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
515 /* We want to read the 3 fields we care about even if it's not enabled in
518 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
520 /* The caller wants the low 32 bits of the timestamp. Since it's running
521 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
522 * which is plenty of time for our purposes. It is identical across the
523 * EUs, but since it's tracking GPU core speed it will increment at a
524 * varying rate as render P-states change.
526 * The caller could also check if render P-states have changed (or anything
527 * else that might disrupt timing) by setting smear to 2 and checking if
528 * that field is != 0.
536 fs_visitor::emit_shader_time_begin()
538 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
542 fs_visitor::emit_shader_time_end()
544 /* Insert our code just before the final SEND with EOT. */
545 exec_node
*end
= this->instructions
.get_tail();
546 assert(end
&& ((fs_inst
*) end
)->eot
);
547 const fs_builder ibld
= bld
.annotate("shader time end")
548 .exec_all().at(NULL
, end
);
550 fs_reg shader_end_time
= get_timestamp(ibld
);
552 /* Check that there weren't any timestamp reset events (assuming these
553 * were the only two timestamp reads that happened).
555 fs_reg reset
= shader_end_time
;
557 set_condmod(BRW_CONDITIONAL_Z
,
558 ibld
.AND(ibld
.null_reg_ud(), reset
, fs_reg(1u)));
559 ibld
.IF(BRW_PREDICATE_NORMAL
);
561 fs_reg start
= shader_start_time
;
563 fs_reg diff
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
566 const fs_builder cbld
= ibld
.group(1, 0);
567 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
569 /* If there were no instructions between the two timestamp gets, the diff
570 * is 2 cycles. Remove that overhead, so I can forget about that when
571 * trying to determine the time taken for single instructions.
573 cbld
.ADD(diff
, diff
, fs_reg(-2u));
574 SHADER_TIME_ADD(cbld
, 0, diff
);
575 SHADER_TIME_ADD(cbld
, 1, fs_reg(1u));
576 ibld
.emit(BRW_OPCODE_ELSE
);
577 SHADER_TIME_ADD(cbld
, 2, fs_reg(1u));
578 ibld
.emit(BRW_OPCODE_ENDIF
);
582 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
583 int shader_time_subindex
,
586 int index
= shader_time_index
* 3 + shader_time_subindex
;
587 fs_reg offset
= fs_reg(index
* SHADER_TIME_STRIDE
);
590 if (dispatch_width
== 8)
591 payload
= vgrf(glsl_type::uvec2_type
);
593 payload
= vgrf(glsl_type::uint_type
);
595 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
599 fs_visitor::vfail(const char *format
, va_list va
)
608 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
609 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
611 this->fail_msg
= msg
;
614 fprintf(stderr
, "%s", msg
);
619 fs_visitor::fail(const char *format
, ...)
623 va_start(va
, format
);
629 * Mark this program as impossible to compile in SIMD16 mode.
631 * During the SIMD8 compile (which happens first), we can detect and flag
632 * things that are unsupported in SIMD16 mode, so the compiler can skip
633 * the SIMD16 compile altogether.
635 * During a SIMD16 compile (if one happens anyway), this just calls fail().
638 fs_visitor::no16(const char *msg
)
640 if (dispatch_width
== 16) {
643 simd16_unsupported
= true;
645 compiler
->shader_perf_log(log_data
,
646 "SIMD16 shader failed to compile: %s", msg
);
651 * Returns true if the instruction has a flag that means it won't
652 * update an entire destination register.
654 * For example, dead code elimination and live variable analysis want to know
655 * when a write to a variable screens off any preceding values that were in
659 fs_inst::is_partial_write() const
661 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
662 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
663 !this->dst
.is_contiguous());
667 fs_inst::components_read(unsigned i
) const
670 case FS_OPCODE_LINTERP
:
676 case FS_OPCODE_PIXEL_X
:
677 case FS_OPCODE_PIXEL_Y
:
681 case FS_OPCODE_FB_WRITE_LOGICAL
:
682 assert(src
[6].file
== IMM
);
683 /* First/second FB write color. */
685 return src
[6].fixed_hw_reg
.dw1
.ud
;
689 case SHADER_OPCODE_TEX_LOGICAL
:
690 case SHADER_OPCODE_TXD_LOGICAL
:
691 case SHADER_OPCODE_TXF_LOGICAL
:
692 case SHADER_OPCODE_TXL_LOGICAL
:
693 case SHADER_OPCODE_TXS_LOGICAL
:
694 case FS_OPCODE_TXB_LOGICAL
:
695 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
696 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
697 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
698 case SHADER_OPCODE_LOD_LOGICAL
:
699 case SHADER_OPCODE_TG4_LOGICAL
:
700 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
701 assert(src
[8].file
== IMM
&& src
[9].file
== IMM
);
702 /* Texture coordinates. */
704 return src
[8].fixed_hw_reg
.dw1
.ud
;
705 /* Texture derivatives. */
706 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
707 return src
[9].fixed_hw_reg
.dw1
.ud
;
708 /* Texture offset. */
714 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
715 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
716 assert(src
[3].file
== IMM
);
717 /* Surface coordinates. */
719 return src
[3].fixed_hw_reg
.dw1
.ud
;
720 /* Surface operation source (ignored for reads). */
726 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
727 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
728 assert(src
[3].file
== IMM
&&
730 /* Surface coordinates. */
732 return src
[3].fixed_hw_reg
.dw1
.ud
;
733 /* Surface operation source. */
735 return src
[4].fixed_hw_reg
.dw1
.ud
;
739 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
740 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
741 assert(src
[3].file
== IMM
&&
743 const unsigned op
= src
[4].fixed_hw_reg
.dw1
.ud
;
744 /* Surface coordinates. */
746 return src
[3].fixed_hw_reg
.dw1
.ud
;
747 /* Surface operation source. */
748 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
750 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
751 op
== BRW_AOP_PREDEC
))
763 fs_inst::regs_read(int arg
) const
766 case FS_OPCODE_FB_WRITE
:
767 case SHADER_OPCODE_URB_WRITE_SIMD8
:
768 case SHADER_OPCODE_UNTYPED_ATOMIC
:
769 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
770 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
771 case SHADER_OPCODE_TYPED_ATOMIC
:
772 case SHADER_OPCODE_TYPED_SURFACE_READ
:
773 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
774 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
779 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
780 /* The payload is actually stored in src1 */
785 case FS_OPCODE_LINTERP
:
790 case SHADER_OPCODE_LOAD_PAYLOAD
:
791 if (arg
< this->header_size
)
795 case CS_OPCODE_CS_TERMINATE
:
799 if (is_tex() && arg
== 0 && src
[0].file
== GRF
)
804 switch (src
[arg
].file
) {
812 return DIV_ROUND_UP(components_read(arg
) *
813 src
[arg
].component_size(exec_size
),
816 unreachable("MRF registers are not allowed as sources");
818 unreachable("Invalid register file");
823 fs_inst::reads_flag() const
829 fs_inst::writes_flag() const
831 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
832 opcode
!= BRW_OPCODE_IF
&&
833 opcode
!= BRW_OPCODE_WHILE
)) ||
834 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
838 * Returns how many MRFs an FS opcode will write over.
840 * Note that this is not the 0 or 1 implied writes in an actual gen
841 * instruction -- the FS opcodes often generate MOVs in addition.
844 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
849 if (inst
->base_mrf
== -1)
852 switch (inst
->opcode
) {
853 case SHADER_OPCODE_RCP
:
854 case SHADER_OPCODE_RSQ
:
855 case SHADER_OPCODE_SQRT
:
856 case SHADER_OPCODE_EXP2
:
857 case SHADER_OPCODE_LOG2
:
858 case SHADER_OPCODE_SIN
:
859 case SHADER_OPCODE_COS
:
860 return 1 * dispatch_width
/ 8;
861 case SHADER_OPCODE_POW
:
862 case SHADER_OPCODE_INT_QUOTIENT
:
863 case SHADER_OPCODE_INT_REMAINDER
:
864 return 2 * dispatch_width
/ 8;
865 case SHADER_OPCODE_TEX
:
867 case SHADER_OPCODE_TXD
:
868 case SHADER_OPCODE_TXF
:
869 case SHADER_OPCODE_TXF_CMS
:
870 case SHADER_OPCODE_TXF_MCS
:
871 case SHADER_OPCODE_TG4
:
872 case SHADER_OPCODE_TG4_OFFSET
:
873 case SHADER_OPCODE_TXL
:
874 case SHADER_OPCODE_TXS
:
875 case SHADER_OPCODE_LOD
:
877 case FS_OPCODE_FB_WRITE
:
879 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
880 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
882 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
884 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
886 case SHADER_OPCODE_UNTYPED_ATOMIC
:
887 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
888 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
889 case SHADER_OPCODE_TYPED_ATOMIC
:
890 case SHADER_OPCODE_TYPED_SURFACE_READ
:
891 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
892 case SHADER_OPCODE_URB_WRITE_SIMD8
:
893 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
894 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
895 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
896 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
899 unreachable("not reached");
904 fs_visitor::vgrf(const glsl_type
*const type
)
906 int reg_width
= dispatch_width
/ 8;
907 return fs_reg(GRF
, alloc
.allocate(type_size(type
) * reg_width
),
908 brw_type_for_base_type(type
));
911 /** Fixed HW reg constructor. */
912 fs_reg::fs_reg(enum register_file file
, int reg
)
917 this->type
= BRW_REGISTER_TYPE_F
;
918 this->stride
= (file
== UNIFORM
? 0 : 1);
921 /** Fixed HW reg constructor. */
922 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
)
928 this->stride
= (file
== UNIFORM
? 0 : 1);
931 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
932 * This brings in those uniform definitions
935 fs_visitor::import_uniforms(fs_visitor
*v
)
937 this->push_constant_loc
= v
->push_constant_loc
;
938 this->pull_constant_loc
= v
->pull_constant_loc
;
939 this->uniforms
= v
->uniforms
;
940 this->param_size
= v
->param_size
;
944 fs_visitor::setup_vector_uniform_values(const gl_constant_value
*values
, unsigned n
)
946 static const gl_constant_value zero
= { 0 };
948 for (unsigned i
= 0; i
< n
; ++i
)
949 stage_prog_data
->param
[uniforms
++] = &values
[i
];
951 for (unsigned i
= n
; i
< 4; ++i
)
952 stage_prog_data
->param
[uniforms
++] = &zero
;
956 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
957 bool origin_upper_left
)
959 assert(stage
== MESA_SHADER_FRAGMENT
);
960 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
961 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
963 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
966 if (pixel_center_integer
) {
967 bld
.MOV(wpos
, this->pixel_x
);
969 bld
.ADD(wpos
, this->pixel_x
, fs_reg(0.5f
));
971 wpos
= offset(wpos
, bld
, 1);
974 if (!flip
&& pixel_center_integer
) {
975 bld
.MOV(wpos
, this->pixel_y
);
977 fs_reg pixel_y
= this->pixel_y
;
978 float offset
= (pixel_center_integer
? 0.0 : 0.5);
981 pixel_y
.negate
= true;
982 offset
+= key
->drawable_height
- 1.0;
985 bld
.ADD(wpos
, pixel_y
, fs_reg(offset
));
987 wpos
= offset(wpos
, bld
, 1);
990 if (devinfo
->gen
>= 6) {
991 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
993 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
994 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
995 interp_reg(VARYING_SLOT_POS
, 2));
997 wpos
= offset(wpos
, bld
, 1);
999 /* gl_FragCoord.w: Already set up in emit_interpolation */
1000 bld
.MOV(wpos
, this->wpos_w
);
1006 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1007 glsl_interp_qualifier interpolation_mode
,
1008 bool is_centroid
, bool is_sample
)
1010 brw_wm_barycentric_interp_mode barycoord_mode
;
1011 if (devinfo
->gen
>= 6) {
1013 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1014 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1016 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1017 } else if (is_sample
) {
1018 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1019 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1021 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1023 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1024 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1026 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1029 /* On Ironlake and below, there is only one interpolation mode.
1030 * Centroid interpolation doesn't mean anything on this hardware --
1031 * there is no multisampling.
1033 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1035 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1036 this->delta_xy
[barycoord_mode
], interp
);
1040 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1041 const glsl_type
*type
,
1042 glsl_interp_qualifier interpolation_mode
,
1043 int location
, bool mod_centroid
,
1046 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1048 assert(stage
== MESA_SHADER_FRAGMENT
);
1049 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1050 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1052 unsigned int array_elements
;
1054 if (type
->is_array()) {
1055 array_elements
= type
->length
;
1056 if (array_elements
== 0) {
1057 fail("dereferenced array '%s' has length 0\n", name
);
1059 type
= type
->fields
.array
;
1064 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1066 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1067 if (key
->flat_shade
&& is_gl_Color
) {
1068 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1070 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1074 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1075 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1076 if (prog_data
->urb_setup
[location
] == -1) {
1077 /* If there's no incoming setup data for this slot, don't
1078 * emit interpolation for it.
1080 attr
= offset(attr
, bld
, type
->vector_elements
);
1085 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1086 /* Constant interpolation (flat shading) case. The SF has
1087 * handed us defined values in only the constant offset
1088 * field of the setup reg.
1090 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1091 struct brw_reg interp
= interp_reg(location
, k
);
1092 interp
= suboffset(interp
, 3);
1093 interp
.type
= attr
.type
;
1094 bld
.emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1095 attr
= offset(attr
, bld
, 1);
1098 /* Smooth/noperspective interpolation case. */
1099 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1100 struct brw_reg interp
= interp_reg(location
, k
);
1101 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1102 /* Get the pixel/sample mask into f0 so that we know
1103 * which pixels are lit. Then, for each channel that is
1104 * unlit, replace the centroid data with non-centroid
1107 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1110 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1112 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1113 inst
->predicate_inverse
= true;
1114 if (devinfo
->has_pln
)
1115 inst
->no_dd_clear
= true;
1117 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1118 mod_centroid
&& !key
->persample_shading
,
1119 mod_sample
|| key
->persample_shading
);
1120 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1121 inst
->predicate_inverse
= false;
1122 if (devinfo
->has_pln
)
1123 inst
->no_dd_check
= true;
1126 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1127 mod_centroid
&& !key
->persample_shading
,
1128 mod_sample
|| key
->persample_shading
);
1130 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1131 bld
.MUL(attr
, attr
, this->pixel_w
);
1133 attr
= offset(attr
, bld
, 1);
1143 fs_visitor::emit_frontfacing_interpolation()
1145 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1147 if (devinfo
->gen
>= 6) {
1148 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1149 * a boolean result from this (~0/true or 0/false).
1151 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1152 * this task in only one instruction:
1153 * - a negation source modifier will flip the bit; and
1154 * - a W -> D type conversion will sign extend the bit into the high
1155 * word of the destination.
1157 * An ASR 15 fills the low word of the destination.
1159 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1162 bld
.ASR(*reg
, g0
, fs_reg(15));
1164 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1165 * a boolean result from this (1/true or 0/false).
1167 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1168 * the negation source modifier to flip it. Unfortunately the SHR
1169 * instruction only operates on UD (or D with an abs source modifier)
1170 * sources without negation.
1172 * Instead, use ASR (which will give ~0/true or 0/false).
1174 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1177 bld
.ASR(*reg
, g1_6
, fs_reg(31));
1184 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1186 assert(stage
== MESA_SHADER_FRAGMENT
);
1187 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1188 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1190 if (key
->compute_pos_offset
) {
1191 /* Convert int_sample_pos to floating point */
1192 bld
.MOV(dst
, int_sample_pos
);
1193 /* Scale to the range [0, 1] */
1194 bld
.MUL(dst
, dst
, fs_reg(1 / 16.0f
));
1197 /* From ARB_sample_shading specification:
1198 * "When rendering to a non-multisample buffer, or if multisample
1199 * rasterization is disabled, gl_SamplePosition will always be
1202 bld
.MOV(dst
, fs_reg(0.5f
));
1207 fs_visitor::emit_samplepos_setup()
1209 assert(devinfo
->gen
>= 6);
1211 const fs_builder abld
= bld
.annotate("compute sample position");
1212 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1214 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1215 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1217 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1218 * mode will be enabled.
1220 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1221 * R31.1:0 Position Offset X/Y for Slot[3:0]
1222 * R31.3:2 Position Offset X/Y for Slot[7:4]
1225 * The X, Y sample positions come in as bytes in thread payload. So, read
1226 * the positions using vstride=16, width=8, hstride=2.
1228 struct brw_reg sample_pos_reg
=
1229 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1230 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1232 if (dispatch_width
== 8) {
1233 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1235 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1236 abld
.half(1).MOV(half(int_sample_x
, 1),
1237 fs_reg(suboffset(sample_pos_reg
, 16)));
1239 /* Compute gl_SamplePosition.x */
1240 compute_sample_position(pos
, int_sample_x
);
1241 pos
= offset(pos
, abld
, 1);
1242 if (dispatch_width
== 8) {
1243 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1245 abld
.half(0).MOV(half(int_sample_y
, 0),
1246 fs_reg(suboffset(sample_pos_reg
, 1)));
1247 abld
.half(1).MOV(half(int_sample_y
, 1),
1248 fs_reg(suboffset(sample_pos_reg
, 17)));
1250 /* Compute gl_SamplePosition.y */
1251 compute_sample_position(pos
, int_sample_y
);
1256 fs_visitor::emit_sampleid_setup()
1258 assert(stage
== MESA_SHADER_FRAGMENT
);
1259 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1260 assert(devinfo
->gen
>= 6);
1262 const fs_builder abld
= bld
.annotate("compute sample id");
1263 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1265 if (key
->compute_sample_id
) {
1266 fs_reg t1
= vgrf(glsl_type::int_type
);
1267 fs_reg t2
= vgrf(glsl_type::int_type
);
1268 t2
.type
= BRW_REGISTER_TYPE_UW
;
1270 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1271 * 8x multisampling, subspan 0 will represent sample N (where N
1272 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1273 * 7. We can find the value of N by looking at R0.0 bits 7:6
1274 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1275 * (since samples are always delivered in pairs). That is, we
1276 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1277 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1278 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1279 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1280 * populating a temporary variable with the sequence (0, 1, 2, 3),
1281 * and then reading from it using vstride=1, width=4, hstride=0.
1282 * These computations hold good for 4x multisampling as well.
1284 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1285 * the first four slots are sample 0 of subspan 0; the next four
1286 * are sample 1 of subspan 0; the third group is sample 0 of
1287 * subspan 1, and finally sample 1 of subspan 1.
1290 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1292 abld
.exec_all().SHR(t1
, t1
, fs_reg(5));
1294 /* This works for both SIMD8 and SIMD16 */
1296 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1298 /* This special instruction takes care of setting vstride=1,
1299 * width=4, hstride=0 of t2 during an ADD instruction.
1301 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1303 /* As per GL_ARB_sample_shading specification:
1304 * "When rendering to a non-multisample buffer, or if multisample
1305 * rasterization is disabled, gl_SampleID will always be zero."
1307 abld
.MOV(*reg
, fs_reg(0));
1314 fs_visitor::resolve_source_modifiers(fs_reg
*src
)
1316 if (!src
->abs
&& !src
->negate
)
1319 fs_reg temp
= bld
.vgrf(src
->type
);
1320 bld
.MOV(temp
, *src
);
1325 fs_visitor::emit_discard_jump()
1327 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1329 /* For performance, after a discard, jump to the end of the
1330 * shader if all relevant channels have been discarded.
1332 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1333 discard_jump
->flag_subreg
= 1;
1335 discard_jump
->predicate
= (dispatch_width
== 8)
1336 ? BRW_PREDICATE_ALIGN1_ANY8H
1337 : BRW_PREDICATE_ALIGN1_ANY16H
;
1338 discard_jump
->predicate_inverse
= true;
1342 fs_visitor::assign_curb_setup()
1344 if (dispatch_width
== 8) {
1345 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1347 if (stage
== MESA_SHADER_FRAGMENT
) {
1348 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1349 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1350 } else if (stage
== MESA_SHADER_COMPUTE
) {
1351 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1352 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1354 unreachable("Unsupported shader type!");
1358 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1360 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1361 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1362 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1363 if (inst
->src
[i
].file
== UNIFORM
) {
1364 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1366 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1367 constant_nr
= push_constant_loc
[uniform_nr
];
1369 /* Section 5.11 of the OpenGL 4.1 spec says:
1370 * "Out-of-bounds reads return undefined values, which include
1371 * values from other variables of the active program or zero."
1372 * Just return the first push constant.
1377 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1381 assert(inst
->src
[i
].stride
== 0);
1382 inst
->src
[i
].file
= HW_REG
;
1383 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1384 retype(brw_reg
, inst
->src
[i
].type
),
1385 inst
->src
[i
].subreg_offset
);
1392 fs_visitor::calculate_urb_setup()
1394 assert(stage
== MESA_SHADER_FRAGMENT
);
1395 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1396 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1398 memset(prog_data
->urb_setup
, -1,
1399 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1402 /* Figure out where each of the incoming setup attributes lands. */
1403 if (devinfo
->gen
>= 6) {
1404 if (_mesa_bitcount_64(prog
->InputsRead
&
1405 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1406 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1407 * first 16 varying inputs, so we can put them wherever we want.
1408 * Just put them in order.
1410 * This is useful because it means that (a) inputs not used by the
1411 * fragment shader won't take up valuable register space, and (b) we
1412 * won't have to recompile the fragment shader if it gets paired with
1413 * a different vertex (or geometry) shader.
1415 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1416 if (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1417 BITFIELD64_BIT(i
)) {
1418 prog_data
->urb_setup
[i
] = urb_next
++;
1422 /* We have enough input varyings that the SF/SBE pipeline stage can't
1423 * arbitrarily rearrange them to suit our whim; we have to put them
1424 * in an order that matches the output of the previous pipeline stage
1425 * (geometry or vertex shader).
1427 struct brw_vue_map prev_stage_vue_map
;
1428 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1429 key
->input_slots_valid
);
1430 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1431 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1432 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1434 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1435 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1438 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1439 (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1440 BITFIELD64_BIT(varying
))) {
1441 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1444 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1447 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1448 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1449 /* Point size is packed into the header, not as a general attribute */
1450 if (i
== VARYING_SLOT_PSIZ
)
1453 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1454 /* The back color slot is skipped when the front color is
1455 * also written to. In addition, some slots can be
1456 * written in the vertex shader and not read in the
1457 * fragment shader. So the register number must always be
1458 * incremented, mapped or not.
1460 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1461 prog_data
->urb_setup
[i
] = urb_next
;
1467 * It's a FS only attribute, and we did interpolation for this attribute
1468 * in SF thread. So, count it here, too.
1470 * See compile_sf_prog() for more info.
1472 if (prog
->InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1473 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1476 prog_data
->num_varying_inputs
= urb_next
;
1480 fs_visitor::assign_urb_setup()
1482 assert(stage
== MESA_SHADER_FRAGMENT
);
1483 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1485 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1487 /* Offset all the urb_setup[] index by the actual position of the
1488 * setup regs, now that the location of the constants has been chosen.
1490 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1491 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1492 assert(inst
->src
[1].file
== HW_REG
);
1493 inst
->src
[1].fixed_hw_reg
.nr
+= urb_start
;
1496 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1497 assert(inst
->src
[0].file
== HW_REG
);
1498 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1502 /* Each attribute is 4 setup channels, each of which is half a reg. */
1503 this->first_non_payload_grf
=
1504 urb_start
+ prog_data
->num_varying_inputs
* 2;
1508 fs_visitor::assign_vs_urb_setup()
1510 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1511 int grf
, count
, slot
, channel
, attr
;
1513 assert(stage
== MESA_SHADER_VERTEX
);
1514 count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1515 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1518 /* Each attribute is 4 regs. */
1519 this->first_non_payload_grf
=
1520 payload
.num_regs
+ prog_data
->curb_read_length
+ count
* 4;
1522 unsigned vue_entries
=
1523 MAX2(count
, vs_prog_data
->base
.vue_map
.num_slots
);
1525 vs_prog_data
->base
.urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1526 vs_prog_data
->base
.urb_read_length
= (count
+ 1) / 2;
1528 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1530 /* Rewrite all ATTR file references to the hw grf that they land in. */
1531 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1532 for (int i
= 0; i
< inst
->sources
; i
++) {
1533 if (inst
->src
[i
].file
== ATTR
) {
1535 if (inst
->src
[i
].reg
== VERT_ATTRIB_MAX
) {
1538 /* Attributes come in in a contiguous block, ordered by their
1539 * gl_vert_attrib value. That means we can compute the slot
1540 * number for an attribute by masking out the enabled
1541 * attributes before it and counting the bits.
1543 attr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
/ 4;
1544 slot
= _mesa_bitcount_64(vs_prog_data
->inputs_read
&
1545 BITFIELD64_MASK(attr
));
1548 channel
= inst
->src
[i
].reg_offset
& 3;
1550 grf
= payload
.num_regs
+
1551 prog_data
->curb_read_length
+
1554 inst
->src
[i
].file
= HW_REG
;
1555 inst
->src
[i
].fixed_hw_reg
=
1556 retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
);
1563 * Split large virtual GRFs into separate components if we can.
1565 * This is mostly duplicated with what brw_fs_vector_splitting does,
1566 * but that's really conservative because it's afraid of doing
1567 * splitting that doesn't result in real progress after the rest of
1568 * the optimization phases, which would cause infinite looping in
1569 * optimization. We can do it once here, safely. This also has the
1570 * opportunity to split interpolated values, or maybe even uniforms,
1571 * which we don't have at the IR level.
1573 * We want to split, because virtual GRFs are what we register
1574 * allocate and spill (due to contiguousness requirements for some
1575 * instructions), and they're what we naturally generate in the
1576 * codegen process, but most virtual GRFs don't actually need to be
1577 * contiguous sets of GRFs. If we split, we'll end up with reduced
1578 * live intervals and better dead code elimination and coalescing.
1581 fs_visitor::split_virtual_grfs()
1583 int num_vars
= this->alloc
.count
;
1585 /* Count the total number of registers */
1587 int vgrf_to_reg
[num_vars
];
1588 for (int i
= 0; i
< num_vars
; i
++) {
1589 vgrf_to_reg
[i
] = reg_count
;
1590 reg_count
+= alloc
.sizes
[i
];
1593 /* An array of "split points". For each register slot, this indicates
1594 * if this slot can be separated from the previous slot. Every time an
1595 * instruction uses multiple elements of a register (as a source or
1596 * destination), we mark the used slots as inseparable. Then we go
1597 * through and split the registers into the smallest pieces we can.
1599 bool split_points
[reg_count
];
1600 memset(split_points
, 0, sizeof(split_points
));
1602 /* Mark all used registers as fully splittable */
1603 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1604 if (inst
->dst
.file
== GRF
) {
1605 int reg
= vgrf_to_reg
[inst
->dst
.reg
];
1606 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.reg
]; j
++)
1607 split_points
[reg
+ j
] = true;
1610 for (int i
= 0; i
< inst
->sources
; i
++) {
1611 if (inst
->src
[i
].file
== GRF
) {
1612 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
];
1613 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].reg
]; j
++)
1614 split_points
[reg
+ j
] = true;
1619 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1620 if (inst
->dst
.file
== GRF
) {
1621 int reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1622 for (int j
= 1; j
< inst
->regs_written
; j
++)
1623 split_points
[reg
+ j
] = false;
1625 for (int i
= 0; i
< inst
->sources
; i
++) {
1626 if (inst
->src
[i
].file
== GRF
) {
1627 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1628 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1629 split_points
[reg
+ j
] = false;
1634 int new_virtual_grf
[reg_count
];
1635 int new_reg_offset
[reg_count
];
1638 for (int i
= 0; i
< num_vars
; i
++) {
1639 /* The first one should always be 0 as a quick sanity check. */
1640 assert(split_points
[reg
] == false);
1643 new_reg_offset
[reg
] = 0;
1648 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1649 /* If this is a split point, reset the offset to 0 and allocate a
1650 * new virtual GRF for the previous offset many registers
1652 if (split_points
[reg
]) {
1653 assert(offset
<= MAX_VGRF_SIZE
);
1654 int grf
= alloc
.allocate(offset
);
1655 for (int k
= reg
- offset
; k
< reg
; k
++)
1656 new_virtual_grf
[k
] = grf
;
1659 new_reg_offset
[reg
] = offset
;
1664 /* The last one gets the original register number */
1665 assert(offset
<= MAX_VGRF_SIZE
);
1666 alloc
.sizes
[i
] = offset
;
1667 for (int k
= reg
- offset
; k
< reg
; k
++)
1668 new_virtual_grf
[k
] = i
;
1670 assert(reg
== reg_count
);
1672 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1673 if (inst
->dst
.file
== GRF
) {
1674 reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1675 inst
->dst
.reg
= new_virtual_grf
[reg
];
1676 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1677 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1679 for (int i
= 0; i
< inst
->sources
; i
++) {
1680 if (inst
->src
[i
].file
== GRF
) {
1681 reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1682 inst
->src
[i
].reg
= new_virtual_grf
[reg
];
1683 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1684 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1688 invalidate_live_intervals();
1692 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1694 * During code generation, we create tons of temporary variables, many of
1695 * which get immediately killed and are never used again. Yet, in later
1696 * optimization and analysis passes, such as compute_live_intervals, we need
1697 * to loop over all the virtual GRFs. Compacting them can save a lot of
1701 fs_visitor::compact_virtual_grfs()
1703 bool progress
= false;
1704 int remap_table
[this->alloc
.count
];
1705 memset(remap_table
, -1, sizeof(remap_table
));
1707 /* Mark which virtual GRFs are used. */
1708 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1709 if (inst
->dst
.file
== GRF
)
1710 remap_table
[inst
->dst
.reg
] = 0;
1712 for (int i
= 0; i
< inst
->sources
; i
++) {
1713 if (inst
->src
[i
].file
== GRF
)
1714 remap_table
[inst
->src
[i
].reg
] = 0;
1718 /* Compact the GRF arrays. */
1720 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1721 if (remap_table
[i
] == -1) {
1722 /* We just found an unused register. This means that we are
1723 * actually going to compact something.
1727 remap_table
[i
] = new_index
;
1728 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1729 invalidate_live_intervals();
1734 this->alloc
.count
= new_index
;
1736 /* Patch all the instructions to use the newly renumbered registers */
1737 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1738 if (inst
->dst
.file
== GRF
)
1739 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1741 for (int i
= 0; i
< inst
->sources
; i
++) {
1742 if (inst
->src
[i
].file
== GRF
)
1743 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1747 /* Patch all the references to delta_xy, since they're used in register
1748 * allocation. If they're unused, switch them to BAD_FILE so we don't
1749 * think some random VGRF is delta_xy.
1751 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1752 if (delta_xy
[i
].file
== GRF
) {
1753 if (remap_table
[delta_xy
[i
].reg
] != -1) {
1754 delta_xy
[i
].reg
= remap_table
[delta_xy
[i
].reg
];
1756 delta_xy
[i
].file
= BAD_FILE
;
1765 * Implements array access of uniforms by inserting a
1766 * PULL_CONSTANT_LOAD instruction.
1768 * Unlike temporary GRF array access (where we don't support it due to
1769 * the difficulty of doing relative addressing on instruction
1770 * destinations), we could potentially do array access of uniforms
1771 * that were loaded in GRF space as push constants. In real-world
1772 * usage we've seen, though, the arrays being used are always larger
1773 * than we could load as push constants, so just always move all
1774 * uniform array access out to a pull constant buffer.
1777 fs_visitor::move_uniform_array_access_to_pull_constants()
1779 if (dispatch_width
!= 8)
1782 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1783 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1785 /* Walk through and find array access of uniforms. Put a copy of that
1786 * uniform in the pull constant buffer.
1788 * Note that we don't move constant-indexed accesses to arrays. No
1789 * testing has been done of the performance impact of this choice.
1791 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1792 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1793 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
1796 int uniform
= inst
->src
[i
].reg
;
1798 /* If this array isn't already present in the pull constant buffer,
1801 if (pull_constant_loc
[uniform
] == -1) {
1802 const gl_constant_value
**values
= &stage_prog_data
->param
[uniform
];
1804 assert(param_size
[uniform
]);
1806 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
1807 pull_constant_loc
[uniform
+ j
] = stage_prog_data
->nr_pull_params
;
1809 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
1818 * Assign UNIFORM file registers to either push constants or pull constants.
1820 * We allow a fragment shader to have more than the specified minimum
1821 * maximum number of fragment shader uniform components (64). If
1822 * there are too many of these, they'd fill up all of register space.
1823 * So, this will push some of them out to the pull constant buffer and
1824 * update the program to load them.
1827 fs_visitor::assign_constant_locations()
1829 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1830 if (dispatch_width
!= 8)
1833 /* Find which UNIFORM registers are still in use. */
1834 bool is_live
[uniforms
];
1835 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1839 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1840 for (int i
= 0; i
< inst
->sources
; i
++) {
1841 if (inst
->src
[i
].file
!= UNIFORM
)
1844 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1845 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1846 is_live
[constant_nr
] = true;
1850 /* Only allow 16 registers (128 uniform components) as push constants.
1852 * Just demote the end of the list. We could probably do better
1853 * here, demoting things that are rarely used in the program first.
1855 * If changing this value, note the limitation about total_regs in
1858 unsigned int max_push_components
= 16 * 8;
1859 unsigned int num_push_constants
= 0;
1861 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1863 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1864 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1865 /* This UNIFORM register is either dead, or has already been demoted
1866 * to a pull const. Mark it as no longer living in the param[] array.
1868 push_constant_loc
[i
] = -1;
1872 if (num_push_constants
< max_push_components
) {
1873 /* Retain as a push constant. Record the location in the params[]
1876 push_constant_loc
[i
] = num_push_constants
++;
1878 /* Demote to a pull constant. */
1879 push_constant_loc
[i
] = -1;
1881 int pull_index
= stage_prog_data
->nr_pull_params
++;
1882 stage_prog_data
->pull_param
[pull_index
] = stage_prog_data
->param
[i
];
1883 pull_constant_loc
[i
] = pull_index
;
1887 stage_prog_data
->nr_params
= num_push_constants
;
1889 /* Up until now, the param[] array has been indexed by reg + reg_offset
1890 * of UNIFORM registers. Condense it to only contain the uniforms we
1891 * chose to upload as push constants.
1893 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1894 int remapped
= push_constant_loc
[i
];
1899 assert(remapped
<= (int)i
);
1900 stage_prog_data
->param
[remapped
] = stage_prog_data
->param
[i
];
1905 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
1906 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
1909 fs_visitor::demote_pull_constants()
1911 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1912 for (int i
= 0; i
< inst
->sources
; i
++) {
1913 if (inst
->src
[i
].file
!= UNIFORM
)
1917 unsigned location
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1918 if (location
>= uniforms
) /* Out of bounds access */
1921 pull_index
= pull_constant_loc
[location
];
1923 if (pull_index
== -1)
1926 /* Set up the annotation tracking for new generated instructions. */
1927 const fs_builder ibld
= bld
.annotate(inst
->annotation
, inst
->ir
)
1929 fs_reg
surf_index(stage_prog_data
->binding_table
.pull_constants_start
);
1930 fs_reg dst
= vgrf(glsl_type::float_type
);
1932 assert(inst
->src
[i
].stride
== 0);
1934 /* Generate a pull load into dst. */
1935 if (inst
->src
[i
].reladdr
) {
1936 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
1938 *inst
->src
[i
].reladdr
,
1940 inst
->src
[i
].reladdr
= NULL
;
1941 inst
->src
[i
].stride
= 1;
1943 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
1944 ibld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
1945 dst
, surf_index
, offset
);
1946 inst
->src
[i
].set_smear(pull_index
& 3);
1949 /* Rewrite the instruction to use the temporary VGRF. */
1950 inst
->src
[i
].file
= GRF
;
1951 inst
->src
[i
].reg
= dst
.reg
;
1952 inst
->src
[i
].reg_offset
= 0;
1955 invalidate_live_intervals();
1959 fs_visitor::opt_algebraic()
1961 bool progress
= false;
1963 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1964 switch (inst
->opcode
) {
1965 case BRW_OPCODE_MOV
:
1966 if (inst
->src
[0].file
!= IMM
)
1969 if (inst
->saturate
) {
1970 if (inst
->dst
.type
!= inst
->src
[0].type
)
1971 assert(!"unimplemented: saturate mixed types");
1973 if (brw_saturate_immediate(inst
->dst
.type
,
1974 &inst
->src
[0].fixed_hw_reg
)) {
1975 inst
->saturate
= false;
1981 case BRW_OPCODE_MUL
:
1982 if (inst
->src
[1].file
!= IMM
)
1986 if (inst
->src
[1].is_one()) {
1987 inst
->opcode
= BRW_OPCODE_MOV
;
1988 inst
->src
[1] = reg_undef
;
1994 if (inst
->src
[1].is_negative_one()) {
1995 inst
->opcode
= BRW_OPCODE_MOV
;
1996 inst
->src
[0].negate
= !inst
->src
[0].negate
;
1997 inst
->src
[1] = reg_undef
;
2003 if (inst
->src
[1].is_zero()) {
2004 inst
->opcode
= BRW_OPCODE_MOV
;
2005 inst
->src
[0] = inst
->src
[1];
2006 inst
->src
[1] = reg_undef
;
2011 if (inst
->src
[0].file
== IMM
) {
2012 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2013 inst
->opcode
= BRW_OPCODE_MOV
;
2014 inst
->src
[0].fixed_hw_reg
.dw1
.f
*= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2015 inst
->src
[1] = reg_undef
;
2020 case BRW_OPCODE_ADD
:
2021 if (inst
->src
[1].file
!= IMM
)
2025 if (inst
->src
[1].is_zero()) {
2026 inst
->opcode
= BRW_OPCODE_MOV
;
2027 inst
->src
[1] = reg_undef
;
2032 if (inst
->src
[0].file
== IMM
) {
2033 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2034 inst
->opcode
= BRW_OPCODE_MOV
;
2035 inst
->src
[0].fixed_hw_reg
.dw1
.f
+= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2036 inst
->src
[1] = reg_undef
;
2042 if (inst
->src
[0].equals(inst
->src
[1])) {
2043 inst
->opcode
= BRW_OPCODE_MOV
;
2044 inst
->src
[1] = reg_undef
;
2049 case BRW_OPCODE_LRP
:
2050 if (inst
->src
[1].equals(inst
->src
[2])) {
2051 inst
->opcode
= BRW_OPCODE_MOV
;
2052 inst
->src
[0] = inst
->src
[1];
2053 inst
->src
[1] = reg_undef
;
2054 inst
->src
[2] = reg_undef
;
2059 case BRW_OPCODE_CMP
:
2060 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2062 inst
->src
[0].negate
&&
2063 inst
->src
[1].is_zero()) {
2064 inst
->src
[0].abs
= false;
2065 inst
->src
[0].negate
= false;
2066 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2071 case BRW_OPCODE_SEL
:
2072 if (inst
->src
[0].equals(inst
->src
[1])) {
2073 inst
->opcode
= BRW_OPCODE_MOV
;
2074 inst
->src
[1] = reg_undef
;
2075 inst
->predicate
= BRW_PREDICATE_NONE
;
2076 inst
->predicate_inverse
= false;
2078 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2079 switch (inst
->conditional_mod
) {
2080 case BRW_CONDITIONAL_LE
:
2081 case BRW_CONDITIONAL_L
:
2082 switch (inst
->src
[1].type
) {
2083 case BRW_REGISTER_TYPE_F
:
2084 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
>= 1.0f
) {
2085 inst
->opcode
= BRW_OPCODE_MOV
;
2086 inst
->src
[1] = reg_undef
;
2087 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2095 case BRW_CONDITIONAL_GE
:
2096 case BRW_CONDITIONAL_G
:
2097 switch (inst
->src
[1].type
) {
2098 case BRW_REGISTER_TYPE_F
:
2099 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
<= 0.0f
) {
2100 inst
->opcode
= BRW_OPCODE_MOV
;
2101 inst
->src
[1] = reg_undef
;
2102 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2114 case BRW_OPCODE_MAD
:
2115 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2116 inst
->opcode
= BRW_OPCODE_MOV
;
2117 inst
->src
[1] = reg_undef
;
2118 inst
->src
[2] = reg_undef
;
2120 } else if (inst
->src
[0].is_zero()) {
2121 inst
->opcode
= BRW_OPCODE_MUL
;
2122 inst
->src
[0] = inst
->src
[2];
2123 inst
->src
[2] = reg_undef
;
2125 } else if (inst
->src
[1].is_one()) {
2126 inst
->opcode
= BRW_OPCODE_ADD
;
2127 inst
->src
[1] = inst
->src
[2];
2128 inst
->src
[2] = reg_undef
;
2130 } else if (inst
->src
[2].is_one()) {
2131 inst
->opcode
= BRW_OPCODE_ADD
;
2132 inst
->src
[2] = reg_undef
;
2134 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2135 inst
->opcode
= BRW_OPCODE_ADD
;
2136 inst
->src
[1].fixed_hw_reg
.dw1
.f
*= inst
->src
[2].fixed_hw_reg
.dw1
.f
;
2137 inst
->src
[2] = reg_undef
;
2141 case SHADER_OPCODE_RCP
: {
2142 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2143 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2144 if (inst
->src
[0].equals(prev
->dst
)) {
2145 inst
->opcode
= SHADER_OPCODE_RSQ
;
2146 inst
->src
[0] = prev
->src
[0];
2152 case SHADER_OPCODE_BROADCAST
:
2153 if (is_uniform(inst
->src
[0])) {
2154 inst
->opcode
= BRW_OPCODE_MOV
;
2156 inst
->force_writemask_all
= true;
2158 } else if (inst
->src
[1].file
== IMM
) {
2159 inst
->opcode
= BRW_OPCODE_MOV
;
2160 inst
->src
[0] = component(inst
->src
[0],
2161 inst
->src
[1].fixed_hw_reg
.dw1
.ud
);
2163 inst
->force_writemask_all
= true;
2172 /* Swap if src[0] is immediate. */
2173 if (progress
&& inst
->is_commutative()) {
2174 if (inst
->src
[0].file
== IMM
) {
2175 fs_reg tmp
= inst
->src
[1];
2176 inst
->src
[1] = inst
->src
[0];
2185 * Optimize sample messages that have constant zero values for the trailing
2186 * texture coordinates. We can just reduce the message length for these
2187 * instructions instead of reserving a register for it. Trailing parameters
2188 * that aren't sent default to zero anyway. This will cause the dead code
2189 * eliminator to remove the MOV instruction that would otherwise be emitted to
2190 * set up the zero value.
2193 fs_visitor::opt_zero_samples()
2195 /* Gen4 infers the texturing opcode based on the message length so we can't
2198 if (devinfo
->gen
< 5)
2201 bool progress
= false;
2203 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2204 if (!inst
->is_tex())
2207 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2209 if (load_payload
->is_head_sentinel() ||
2210 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2213 /* We don't want to remove the message header or the first parameter.
2214 * Removing the first parameter is not allowed, see the Haswell PRM
2215 * volume 7, page 149:
2217 * "Parameter 0 is required except for the sampleinfo message, which
2218 * has no parameter 0"
2220 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2221 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2222 (inst
->exec_size
/ 8) +
2223 inst
->header_size
- 1].is_zero()) {
2224 inst
->mlen
-= inst
->exec_size
/ 8;
2230 invalidate_live_intervals();
2236 * Optimize sample messages which are followed by the final RT write.
2238 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2239 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2240 * final texturing results copied to the framebuffer write payload and modify
2241 * them to write to the framebuffer directly.
2244 fs_visitor::opt_sampler_eot()
2246 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2248 if (stage
!= MESA_SHADER_FRAGMENT
)
2251 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2254 /* FINISHME: It should be possible to implement this optimization when there
2255 * are multiple drawbuffers.
2257 if (key
->nr_color_regions
!= 1)
2260 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2261 fs_inst
*fb_write
= (fs_inst
*) cfg
->blocks
[cfg
->num_blocks
- 1]->end();
2262 assert(fb_write
->eot
);
2263 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2265 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2267 /* There wasn't one; nothing to do. */
2268 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2271 /* This optimisation doesn't seem to work for textureGather for some
2272 * reason. I can't find any documentation or known workarounds to indicate
2273 * that this is expected, but considering that it is probably pretty
2274 * unlikely that a shader would directly write out the results from
2275 * textureGather we might as well just disable it.
2277 if (tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2278 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2281 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2282 * It's very likely to be the previous instruction.
2284 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2285 if (load_payload
->is_head_sentinel() ||
2286 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2289 assert(!tex_inst
->eot
); /* We can't get here twice */
2290 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2292 tex_inst
->offset
|= fb_write
->target
<< 24;
2293 tex_inst
->eot
= true;
2294 tex_inst
->dst
= bld
.null_reg_ud();
2295 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2297 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2298 * to create a new LOAD_PAYLOAD command with the same sources and a space
2299 * saved for the header. Using a new destination register not only makes sure
2300 * we have enough space, but it will make sure the dead code eliminator kills
2301 * the instruction that this will replace.
2303 if (tex_inst
->header_size
!= 0)
2306 fs_reg send_header
= bld
.vgrf(BRW_REGISTER_TYPE_F
,
2307 load_payload
->sources
+ 1);
2308 fs_reg
*new_sources
=
2309 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2311 new_sources
[0] = fs_reg();
2312 for (int i
= 0; i
< load_payload
->sources
; i
++)
2313 new_sources
[i
+1] = load_payload
->src
[i
];
2315 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2316 * requires a lot of information about the sources to appropriately figure
2317 * out the number of registers needed to be used. Given this stage in our
2318 * optimization, we may not have the appropriate GRFs required by
2319 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2320 * manually emit the instruction.
2322 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2323 load_payload
->exec_size
,
2326 load_payload
->sources
+ 1);
2328 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2329 new_load_payload
->header_size
= 1;
2331 tex_inst
->header_size
= 1;
2332 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2333 tex_inst
->src
[0] = send_header
;
2339 fs_visitor::opt_register_renaming()
2341 bool progress
= false;
2344 int remap
[alloc
.count
];
2345 memset(remap
, -1, sizeof(int) * alloc
.count
);
2347 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2348 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2350 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2351 inst
->opcode
== BRW_OPCODE_WHILE
) {
2355 /* Rewrite instruction sources. */
2356 for (int i
= 0; i
< inst
->sources
; i
++) {
2357 if (inst
->src
[i
].file
== GRF
&&
2358 remap
[inst
->src
[i
].reg
] != -1 &&
2359 remap
[inst
->src
[i
].reg
] != inst
->src
[i
].reg
) {
2360 inst
->src
[i
].reg
= remap
[inst
->src
[i
].reg
];
2365 const int dst
= inst
->dst
.reg
;
2368 inst
->dst
.file
== GRF
&&
2369 alloc
.sizes
[inst
->dst
.reg
] == inst
->exec_size
/ 8 &&
2370 !inst
->is_partial_write()) {
2371 if (remap
[dst
] == -1) {
2374 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2375 inst
->dst
.reg
= remap
[dst
];
2378 } else if (inst
->dst
.file
== GRF
&&
2380 remap
[dst
] != dst
) {
2381 inst
->dst
.reg
= remap
[dst
];
2387 invalidate_live_intervals();
2389 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2390 if (delta_xy
[i
].file
== GRF
&& remap
[delta_xy
[i
].reg
] != -1) {
2391 delta_xy
[i
].reg
= remap
[delta_xy
[i
].reg
];
2400 * Remove redundant or useless discard jumps.
2402 * For example, we can eliminate jumps in the following sequence:
2404 * discard-jump (redundant with the next jump)
2405 * discard-jump (useless; jumps to the next instruction)
2409 fs_visitor::opt_redundant_discard_jumps()
2411 bool progress
= false;
2413 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2415 fs_inst
*placeholder_halt
= NULL
;
2416 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2417 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2418 placeholder_halt
= inst
;
2423 if (!placeholder_halt
)
2426 /* Delete any HALTs immediately before the placeholder halt. */
2427 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2428 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2429 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2430 prev
->remove(last_bblock
);
2435 invalidate_live_intervals();
2441 fs_visitor::compute_to_mrf()
2443 bool progress
= false;
2446 /* No MRFs on Gen >= 7. */
2447 if (devinfo
->gen
>= 7)
2450 calculate_live_intervals();
2452 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2456 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2457 inst
->is_partial_write() ||
2458 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2459 inst
->dst
.type
!= inst
->src
[0].type
||
2460 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2461 !inst
->src
[0].is_contiguous() ||
2462 inst
->src
[0].subreg_offset
)
2465 /* Work out which hardware MRF registers are written by this
2468 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2470 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2471 mrf_high
= mrf_low
+ 4;
2472 } else if (inst
->exec_size
== 16) {
2473 mrf_high
= mrf_low
+ 1;
2478 /* Can't compute-to-MRF this GRF if someone else was going to
2481 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2484 /* Found a move of a GRF to a MRF. Let's see if we can go
2485 * rewrite the thing that made this GRF to write into the MRF.
2487 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2488 if (scan_inst
->dst
.file
== GRF
&&
2489 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2490 /* Found the last thing to write our reg we want to turn
2491 * into a compute-to-MRF.
2494 /* If this one instruction didn't populate all the
2495 * channels, bail. We might be able to rewrite everything
2496 * that writes that reg, but it would require smarter
2497 * tracking to delay the rewriting until complete success.
2499 if (scan_inst
->is_partial_write())
2502 /* Things returning more than one register would need us to
2503 * understand coalescing out more than one MOV at a time.
2505 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2508 /* SEND instructions can't have MRF as a destination. */
2509 if (scan_inst
->mlen
)
2512 if (devinfo
->gen
== 6) {
2513 /* gen6 math instructions must have the destination be
2514 * GRF, so no compute-to-MRF for them.
2516 if (scan_inst
->is_math()) {
2521 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2522 /* Found the creator of our MRF's source value. */
2523 scan_inst
->dst
.file
= MRF
;
2524 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2525 scan_inst
->saturate
|= inst
->saturate
;
2526 inst
->remove(block
);
2532 /* We don't handle control flow here. Most computation of
2533 * values that end up in MRFs are shortly before the MRF
2536 if (block
->start() == scan_inst
)
2539 /* You can't read from an MRF, so if someone else reads our
2540 * MRF's source GRF that we wanted to rewrite, that stops us.
2542 bool interfered
= false;
2543 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2544 if (scan_inst
->src
[i
].file
== GRF
&&
2545 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2546 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2553 if (scan_inst
->dst
.file
== MRF
) {
2554 /* If somebody else writes our MRF here, we can't
2555 * compute-to-MRF before that.
2557 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2560 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2561 scan_mrf_high
= scan_mrf_low
+ 4;
2562 } else if (scan_inst
->exec_size
== 16) {
2563 scan_mrf_high
= scan_mrf_low
+ 1;
2565 scan_mrf_high
= scan_mrf_low
;
2568 if (mrf_low
== scan_mrf_low
||
2569 mrf_low
== scan_mrf_high
||
2570 mrf_high
== scan_mrf_low
||
2571 mrf_high
== scan_mrf_high
) {
2576 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2577 /* Found a SEND instruction, which means that there are
2578 * live values in MRFs from base_mrf to base_mrf +
2579 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2582 if (mrf_low
>= scan_inst
->base_mrf
&&
2583 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2586 if (mrf_high
>= scan_inst
->base_mrf
&&
2587 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2595 invalidate_live_intervals();
2601 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2602 * flow. We could probably do better here with some form of divergence
2606 fs_visitor::eliminate_find_live_channel()
2608 bool progress
= false;
2611 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2612 switch (inst
->opcode
) {
2618 case BRW_OPCODE_ENDIF
:
2619 case BRW_OPCODE_WHILE
:
2623 case FS_OPCODE_DISCARD_JUMP
:
2624 /* This can potentially make control flow non-uniform until the end
2629 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2631 inst
->opcode
= BRW_OPCODE_MOV
;
2632 inst
->src
[0] = fs_reg(0);
2634 inst
->force_writemask_all
= true;
2648 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2649 * instructions to FS_OPCODE_REP_FB_WRITE.
2652 fs_visitor::emit_repclear_shader()
2654 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2656 int color_mrf
= base_mrf
+ 2;
2658 fs_inst
*mov
= bld
.exec_all().MOV(vec4(brw_message_reg(color_mrf
)),
2659 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2662 if (key
->nr_color_regions
== 1) {
2663 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2664 write
->saturate
= key
->clamp_fragment_color
;
2665 write
->base_mrf
= color_mrf
;
2667 write
->header_size
= 0;
2670 assume(key
->nr_color_regions
> 0);
2671 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2672 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2673 write
->saturate
= key
->clamp_fragment_color
;
2674 write
->base_mrf
= base_mrf
;
2676 write
->header_size
= 2;
2684 assign_constant_locations();
2685 assign_curb_setup();
2687 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2688 assert(mov
->src
[0].file
== HW_REG
);
2689 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].fixed_hw_reg
.nr
, 0);
2693 * Walks through basic blocks, looking for repeated MRF writes and
2694 * removing the later ones.
2697 fs_visitor::remove_duplicate_mrf_writes()
2699 fs_inst
*last_mrf_move
[16];
2700 bool progress
= false;
2702 /* Need to update the MRF tracking for compressed instructions. */
2703 if (dispatch_width
== 16)
2706 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2708 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2709 if (inst
->is_control_flow()) {
2710 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2713 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2714 inst
->dst
.file
== MRF
) {
2715 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2716 if (prev_inst
&& inst
->equals(prev_inst
)) {
2717 inst
->remove(block
);
2723 /* Clear out the last-write records for MRFs that were overwritten. */
2724 if (inst
->dst
.file
== MRF
) {
2725 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2728 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2729 /* Found a SEND instruction, which will include two or fewer
2730 * implied MRF writes. We could do better here.
2732 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2733 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2737 /* Clear out any MRF move records whose sources got overwritten. */
2738 if (inst
->dst
.file
== GRF
) {
2739 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2740 if (last_mrf_move
[i
] &&
2741 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2742 last_mrf_move
[i
] = NULL
;
2747 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2748 inst
->dst
.file
== MRF
&&
2749 inst
->src
[0].file
== GRF
&&
2750 !inst
->is_partial_write()) {
2751 last_mrf_move
[inst
->dst
.reg
] = inst
;
2756 invalidate_live_intervals();
2762 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2764 /* Clear the flag for registers that actually got read (as expected). */
2765 for (int i
= 0; i
< inst
->sources
; i
++) {
2767 if (inst
->src
[i
].file
== GRF
) {
2768 grf
= inst
->src
[i
].reg
;
2769 } else if (inst
->src
[i
].file
== HW_REG
&&
2770 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2771 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2776 if (grf
>= first_grf
&&
2777 grf
< first_grf
+ grf_len
) {
2778 deps
[grf
- first_grf
] = false;
2779 if (inst
->exec_size
== 16)
2780 deps
[grf
- first_grf
+ 1] = false;
2786 * Implements this workaround for the original 965:
2788 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2789 * check for post destination dependencies on this instruction, software
2790 * must ensure that there is no destination hazard for the case of ‘write
2791 * followed by a posted write’ shown in the following example.
2794 * 2. send r3.xy <rest of send instruction>
2797 * Due to no post-destination dependency check on the ‘send’, the above
2798 * code sequence could have two instructions (1 and 2) in flight at the
2799 * same time that both consider ‘r3’ as the target of their final writes.
2802 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2805 int write_len
= inst
->regs_written
;
2806 int first_write_grf
= inst
->dst
.reg
;
2807 bool needs_dep
[BRW_MAX_MRF
];
2808 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2810 memset(needs_dep
, false, sizeof(needs_dep
));
2811 memset(needs_dep
, true, write_len
);
2813 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2815 /* Walk backwards looking for writes to registers we're writing which
2816 * aren't read since being written. If we hit the start of the program,
2817 * we assume that there are no outstanding dependencies on entry to the
2820 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2821 /* If we hit control flow, assume that there *are* outstanding
2822 * dependencies, and force their cleanup before our instruction.
2824 if (block
->start() == scan_inst
) {
2825 for (int i
= 0; i
< write_len
; i
++) {
2827 DEP_RESOLVE_MOV(bld
.at(block
, inst
), first_write_grf
+ i
);
2832 /* We insert our reads as late as possible on the assumption that any
2833 * instruction but a MOV that might have left us an outstanding
2834 * dependency has more latency than a MOV.
2836 if (scan_inst
->dst
.file
== GRF
) {
2837 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2838 int reg
= scan_inst
->dst
.reg
+ i
;
2840 if (reg
>= first_write_grf
&&
2841 reg
< first_write_grf
+ write_len
&&
2842 needs_dep
[reg
- first_write_grf
]) {
2843 DEP_RESOLVE_MOV(bld
.at(block
, inst
), reg
);
2844 needs_dep
[reg
- first_write_grf
] = false;
2845 if (scan_inst
->exec_size
== 16)
2846 needs_dep
[reg
- first_write_grf
+ 1] = false;
2851 /* Clear the flag for registers that actually got read (as expected). */
2852 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2854 /* Continue the loop only if we haven't resolved all the dependencies */
2856 for (i
= 0; i
< write_len
; i
++) {
2866 * Implements this workaround for the original 965:
2868 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2869 * used as a destination register until after it has been sourced by an
2870 * instruction with a different destination register.
2873 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2875 int write_len
= inst
->regs_written
;
2876 int first_write_grf
= inst
->dst
.reg
;
2877 bool needs_dep
[BRW_MAX_MRF
];
2878 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2880 memset(needs_dep
, false, sizeof(needs_dep
));
2881 memset(needs_dep
, true, write_len
);
2882 /* Walk forwards looking for writes to registers we're writing which aren't
2883 * read before being written.
2885 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2886 /* If we hit control flow, force resolve all remaining dependencies. */
2887 if (block
->end() == scan_inst
) {
2888 for (int i
= 0; i
< write_len
; i
++) {
2890 DEP_RESOLVE_MOV(bld
.at(block
, scan_inst
), first_write_grf
+ i
);
2895 /* Clear the flag for registers that actually got read (as expected). */
2896 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2898 /* We insert our reads as late as possible since they're reading the
2899 * result of a SEND, which has massive latency.
2901 if (scan_inst
->dst
.file
== GRF
&&
2902 scan_inst
->dst
.reg
>= first_write_grf
&&
2903 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
2904 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
2905 DEP_RESOLVE_MOV(bld
.at(block
, scan_inst
), scan_inst
->dst
.reg
);
2906 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
2909 /* Continue the loop only if we haven't resolved all the dependencies */
2911 for (i
= 0; i
< write_len
; i
++) {
2921 fs_visitor::insert_gen4_send_dependency_workarounds()
2923 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
2926 bool progress
= false;
2928 /* Note that we're done with register allocation, so GRF fs_regs always
2929 * have a .reg_offset of 0.
2932 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2933 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
2934 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
2935 insert_gen4_post_send_dependency_workarounds(block
, inst
);
2941 invalidate_live_intervals();
2945 * Turns the generic expression-style uniform pull constant load instruction
2946 * into a hardware-specific series of instructions for loading a pull
2949 * The expression style allows the CSE pass before this to optimize out
2950 * repeated loads from the same offset, and gives the pre-register-allocation
2951 * scheduling full flexibility, while the conversion to native instructions
2952 * allows the post-register-allocation scheduler the best information
2955 * Note that execution masking for setting up pull constant loads is special:
2956 * the channels that need to be written are unrelated to the current execution
2957 * mask, since a later instruction will use one of the result channels as a
2958 * source operand for all 8 or 16 of its channels.
2961 fs_visitor::lower_uniform_pull_constant_loads()
2963 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2964 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
2967 if (devinfo
->gen
>= 7) {
2968 /* The offset arg before was a vec4-aligned byte offset. We need to
2969 * turn it into a dword offset.
2971 fs_reg const_offset_reg
= inst
->src
[1];
2972 assert(const_offset_reg
.file
== IMM
&&
2973 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
2974 const_offset_reg
.fixed_hw_reg
.dw1
.ud
/= 4;
2976 fs_reg payload
, offset
;
2977 if (devinfo
->gen
>= 9) {
2978 /* We have to use a message header on Skylake to get SIMD4x2
2979 * mode. Reserve space for the register.
2981 offset
= payload
= fs_reg(GRF
, alloc
.allocate(2));
2982 offset
.reg_offset
++;
2985 offset
= payload
= fs_reg(GRF
, alloc
.allocate(1));
2989 /* This is actually going to be a MOV, but since only the first dword
2990 * is accessed, we have a special opcode to do just that one. Note
2991 * that this needs to be an operation that will be considered a def
2992 * by live variable analysis, or register allocation will explode.
2994 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
2995 8, offset
, const_offset_reg
);
2996 setup
->force_writemask_all
= true;
2998 setup
->ir
= inst
->ir
;
2999 setup
->annotation
= inst
->annotation
;
3000 inst
->insert_before(block
, setup
);
3002 /* Similarly, this will only populate the first 4 channels of the
3003 * result register (since we only use smear values from 0-3), but we
3004 * don't tell the optimizer.
3006 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3007 inst
->src
[1] = payload
;
3008 inst
->base_mrf
= -1;
3010 invalidate_live_intervals();
3012 /* Before register allocation, we didn't tell the scheduler about the
3013 * MRF we use. We know it's safe to use this MRF because nothing
3014 * else does except for register spill/unspill, which generates and
3015 * uses its MRF within a single IR instruction.
3017 inst
->base_mrf
= 14;
3024 fs_visitor::lower_load_payload()
3026 bool progress
= false;
3028 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3029 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3032 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== GRF
);
3033 assert(inst
->saturate
== false);
3034 fs_reg dst
= inst
->dst
;
3036 /* Get rid of COMPR4. We'll add it back in if we need it */
3037 if (dst
.file
== MRF
)
3038 dst
.reg
= dst
.reg
& ~BRW_MRF_COMPR4
;
3040 const fs_builder hbld
= bld
.exec_all().group(8, 0).at(block
, inst
);
3042 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3043 if (inst
->src
[i
].file
!= BAD_FILE
) {
3044 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3045 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3046 hbld
.MOV(mov_dst
, mov_src
);
3048 dst
= offset(dst
, hbld
, 1);
3051 const fs_builder ibld
= bld
.exec_all(inst
->force_writemask_all
)
3052 .group(inst
->exec_size
, inst
->force_sechalf
)
3055 if (inst
->dst
.file
== MRF
&& (inst
->dst
.reg
& BRW_MRF_COMPR4
) &&
3056 inst
->exec_size
> 8) {
3057 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3058 * a straightforward copy. Instead, the result of the
3059 * LOAD_PAYLOAD is treated as interleaved and the first four
3060 * non-header sources are unpacked as:
3071 * This is used for gen <= 5 fb writes.
3073 assert(inst
->exec_size
== 16);
3074 assert(inst
->header_size
+ 4 <= inst
->sources
);
3075 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3076 if (inst
->src
[i
].file
!= BAD_FILE
) {
3077 if (devinfo
->has_compr4
) {
3078 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3079 compr4_dst
.reg
|= BRW_MRF_COMPR4
;
3080 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3082 /* Platform doesn't have COMPR4. We have to fake it */
3083 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3084 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3086 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3093 /* The loop above only ever incremented us through the first set
3094 * of 4 registers. However, thanks to the magic of COMPR4, we
3095 * actually wrote to the first 8 registers, so we need to take
3096 * that into account now.
3100 /* The COMPR4 code took care of the first 4 sources. We'll let
3101 * the regular path handle any remaining sources. Yes, we are
3102 * modifying the instruction but we're about to delete it so
3103 * this really doesn't hurt anything.
3105 inst
->header_size
+= 4;
3108 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3109 if (inst
->src
[i
].file
!= BAD_FILE
)
3110 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3111 dst
= offset(dst
, ibld
, 1);
3114 inst
->remove(block
);
3119 invalidate_live_intervals();
3125 fs_visitor::lower_integer_multiplication()
3127 bool progress
= false;
3129 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit operation
3130 * directly, but Cherryview cannot.
3132 if (devinfo
->gen
>= 8 && !devinfo
->is_cherryview
)
3135 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3136 if (inst
->opcode
!= BRW_OPCODE_MUL
||
3137 inst
->dst
.is_accumulator() ||
3138 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3139 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3142 const fs_builder ibld
= bld
.at(block
, inst
);
3144 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3145 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3148 * If multiplying by an immediate value that fits in 16-bits, do a
3149 * single MUL instruction with that value in the proper location.
3151 if (inst
->src
[1].file
== IMM
&&
3152 inst
->src
[1].fixed_hw_reg
.dw1
.ud
< (1 << 16)) {
3153 if (devinfo
->gen
< 7) {
3154 fs_reg
imm(GRF
, alloc
.allocate(dispatch_width
/ 8),
3156 ibld
.MOV(imm
, inst
->src
[1]);
3157 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3159 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3162 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3163 * do 32-bit integer multiplication in one instruction, but instead
3164 * must do a sequence (which actually calculates a 64-bit result):
3166 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3167 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3168 * mov(8) g2<1>D acc0<8,8,1>D
3170 * But on Gen > 6, the ability to use second accumulator register
3171 * (acc1) for non-float data types was removed, preventing a simple
3172 * implementation in SIMD16. A 16-channel result can be calculated by
3173 * executing the three instructions twice in SIMD8, once with quarter
3174 * control of 1Q for the first eight channels and again with 2Q for
3175 * the second eight channels.
3177 * Which accumulator register is implicitly accessed (by AccWrEnable
3178 * for instance) is determined by the quarter control. Unfortunately
3179 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3180 * implicit accumulator access by an instruction with 2Q will access
3181 * acc1 regardless of whether the data type is usable in acc1.
3183 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3184 * integer data types.
3186 * Since we only want the low 32-bits of the result, we can do two
3187 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3188 * adjust the high result and add them (like the mach is doing):
3190 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3191 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3192 * shl(8) g9<1>D g8<8,8,1>D 16D
3193 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3195 * We avoid the shl instruction by realizing that we only want to add
3196 * the low 16-bits of the "high" result to the high 16-bits of the
3197 * "low" result and using proper regioning on the add:
3199 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3200 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3201 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3203 * Since it does not use the (single) accumulator register, we can
3204 * schedule multi-component multiplications much better.
3207 if (inst
->conditional_mod
&& inst
->dst
.is_null()) {
3208 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
3211 fs_reg low
= inst
->dst
;
3212 fs_reg
high(GRF
, alloc
.allocate(dispatch_width
/ 8),
3215 if (devinfo
->gen
>= 7) {
3216 fs_reg src1_0_w
= inst
->src
[1];
3217 fs_reg src1_1_w
= inst
->src
[1];
3219 if (inst
->src
[1].file
== IMM
) {
3220 src1_0_w
.fixed_hw_reg
.dw1
.ud
&= 0xffff;
3221 src1_1_w
.fixed_hw_reg
.dw1
.ud
>>= 16;
3223 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3224 if (src1_0_w
.stride
!= 0) {
3225 assert(src1_0_w
.stride
== 1);
3226 src1_0_w
.stride
= 2;
3229 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3230 if (src1_1_w
.stride
!= 0) {
3231 assert(src1_1_w
.stride
== 1);
3232 src1_1_w
.stride
= 2;
3234 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3236 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3237 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3239 fs_reg src0_0_w
= inst
->src
[0];
3240 fs_reg src0_1_w
= inst
->src
[0];
3242 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3243 if (src0_0_w
.stride
!= 0) {
3244 assert(src0_0_w
.stride
== 1);
3245 src0_0_w
.stride
= 2;
3248 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3249 if (src0_1_w
.stride
!= 0) {
3250 assert(src0_1_w
.stride
== 1);
3251 src0_1_w
.stride
= 2;
3253 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3255 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3256 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3259 fs_reg dst
= inst
->dst
;
3260 dst
.type
= BRW_REGISTER_TYPE_UW
;
3261 dst
.subreg_offset
= 2;
3264 high
.type
= BRW_REGISTER_TYPE_UW
;
3267 low
.type
= BRW_REGISTER_TYPE_UW
;
3268 low
.subreg_offset
= 2;
3271 ibld
.ADD(dst
, low
, high
);
3273 if (inst
->conditional_mod
) {
3274 fs_reg
null(retype(ibld
.null_reg_f(), inst
->dst
.type
));
3275 set_condmod(inst
->conditional_mod
,
3276 ibld
.MOV(null
, inst
->dst
));
3280 inst
->remove(block
);
3285 invalidate_live_intervals();
3291 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3292 fs_reg
*dst
, fs_reg color
, unsigned components
)
3294 if (key
->clamp_fragment_color
) {
3295 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3296 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3298 for (unsigned i
= 0; i
< components
; i
++)
3300 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3305 for (unsigned i
= 0; i
< components
; i
++)
3306 dst
[i
] = offset(color
, bld
, i
);
3310 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3311 const brw_wm_prog_data
*prog_data
,
3312 const brw_wm_prog_key
*key
,
3313 const fs_visitor::thread_payload
&payload
)
3315 assert(inst
->src
[6].file
== IMM
);
3316 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3317 const fs_reg
&color0
= inst
->src
[0];
3318 const fs_reg
&color1
= inst
->src
[1];
3319 const fs_reg
&src0_alpha
= inst
->src
[2];
3320 const fs_reg
&src_depth
= inst
->src
[3];
3321 const fs_reg
&dst_depth
= inst
->src
[4];
3322 fs_reg sample_mask
= inst
->src
[5];
3323 const unsigned components
= inst
->src
[6].fixed_hw_reg
.dw1
.ud
;
3325 /* We can potentially have a message length of up to 15, so we have to set
3326 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3329 int header_size
= 2, payload_header_size
;
3330 unsigned length
= 0;
3332 /* From the Sandy Bridge PRM, volume 4, page 198:
3334 * "Dispatched Pixel Enables. One bit per pixel indicating
3335 * which pixels were originally enabled when the thread was
3336 * dispatched. This field is only required for the end-of-
3337 * thread message and on all dual-source messages."
3339 if (devinfo
->gen
>= 6 &&
3340 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3341 color1
.file
== BAD_FILE
&&
3342 key
->nr_color_regions
== 1) {
3346 if (header_size
!= 0) {
3347 assert(header_size
== 2);
3348 /* Allocate 2 registers for a header */
3352 if (payload
.aa_dest_stencil_reg
) {
3353 sources
[length
] = fs_reg(GRF
, bld
.shader
->alloc
.allocate(1));
3354 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3355 .MOV(sources
[length
],
3356 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3360 if (prog_data
->uses_omask
) {
3361 sources
[length
] = fs_reg(GRF
, bld
.shader
->alloc
.allocate(1),
3362 BRW_REGISTER_TYPE_UD
);
3364 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3365 * relevant. Since it's unsigned single words one vgrf is always
3366 * 16-wide, but only the lower or higher 8 channels will be used by the
3367 * hardware when doing a SIMD8 write depending on whether we have
3368 * selected the subspans for the first or second half respectively.
3370 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3371 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3372 sample_mask
.stride
*= 2;
3374 bld
.exec_all().annotate("FB write oMask")
3375 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3376 inst
->force_sechalf
),
3381 payload_header_size
= length
;
3383 if (src0_alpha
.file
!= BAD_FILE
) {
3384 /* FIXME: This is being passed at the wrong location in the payload and
3385 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3386 * It's supposed to be immediately before oMask but there seems to be no
3387 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3388 * requires header sources to form a contiguous segment at the beginning
3389 * of the message and src0_alpha has per-channel semantics.
3391 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3395 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3398 if (color1
.file
!= BAD_FILE
) {
3399 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3403 if (src_depth
.file
!= BAD_FILE
) {
3404 sources
[length
] = src_depth
;
3408 if (dst_depth
.file
!= BAD_FILE
) {
3409 sources
[length
] = dst_depth
;
3414 if (devinfo
->gen
>= 7) {
3415 /* Send from the GRF */
3416 fs_reg payload
= fs_reg(GRF
, -1, BRW_REGISTER_TYPE_F
);
3417 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3418 payload
.reg
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3419 load
->dst
= payload
;
3421 inst
->src
[0] = payload
;
3422 inst
->resize_sources(1);
3423 inst
->base_mrf
= -1;
3425 /* Send from the MRF */
3426 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3427 sources
, length
, payload_header_size
);
3429 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3430 * will do this for us if we just give it a COMPR4 destination.
3432 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3433 load
->dst
.reg
|= BRW_MRF_COMPR4
;
3435 inst
->resize_sources(0);
3439 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3440 inst
->mlen
= load
->regs_written
;
3441 inst
->header_size
= header_size
;
3445 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3446 const fs_reg
&coordinate
,
3447 const fs_reg
&shadow_c
,
3448 const fs_reg
&lod
, const fs_reg
&lod2
,
3449 const fs_reg
&sampler
,
3450 unsigned coord_components
,
3451 unsigned grad_components
)
3453 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3454 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3455 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3456 fs_reg msg_end
= msg_begin
;
3459 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3461 for (unsigned i
= 0; i
< coord_components
; i
++)
3462 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3463 offset(coordinate
, bld
, i
));
3465 msg_end
= offset(msg_end
, bld
, coord_components
);
3467 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3468 * require all three components to be present and zero if they are unused.
3470 if (coord_components
> 0 &&
3471 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3472 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3473 for (unsigned i
= coord_components
; i
< 3; i
++)
3474 bld
.MOV(offset(msg_end
, bld
, i
), fs_reg(0.0f
));
3476 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3479 if (op
== SHADER_OPCODE_TXD
) {
3480 /* TXD unsupported in SIMD16 mode. */
3481 assert(bld
.dispatch_width() == 8);
3483 /* the slots for u and v are always present, but r is optional */
3484 if (coord_components
< 2)
3485 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3488 * dPdx = dudx, dvdx, drdx
3489 * dPdy = dudy, dvdy, drdy
3491 * 1-arg: Does not exist.
3493 * 2-arg: dudx dvdx dudy dvdy
3494 * dPdx.x dPdx.y dPdy.x dPdy.y
3497 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3498 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3499 * m5 m6 m7 m8 m9 m10
3501 for (unsigned i
= 0; i
< grad_components
; i
++)
3502 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3504 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3506 for (unsigned i
= 0; i
< grad_components
; i
++)
3507 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3509 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3513 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3514 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3516 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3517 bld
.dispatch_width() == 16);
3519 const brw_reg_type type
=
3520 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3521 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3522 bld
.MOV(retype(msg_end
, type
), lod
);
3523 msg_end
= offset(msg_end
, bld
, 1);
3526 if (shadow_c
.file
!= BAD_FILE
) {
3527 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3528 /* There's no plain shadow compare message, so we use shadow
3529 * compare with a bias of 0.0.
3531 bld
.MOV(msg_end
, fs_reg(0.0f
));
3532 msg_end
= offset(msg_end
, bld
, 1);
3535 bld
.MOV(msg_end
, shadow_c
);
3536 msg_end
= offset(msg_end
, bld
, 1);
3540 inst
->src
[0] = reg_undef
;
3541 inst
->src
[1] = sampler
;
3542 inst
->resize_sources(2);
3543 inst
->base_mrf
= msg_begin
.reg
;
3544 inst
->mlen
= msg_end
.reg
- msg_begin
.reg
;
3545 inst
->header_size
= 1;
3549 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3551 const fs_reg
&shadow_c
,
3552 fs_reg lod
, fs_reg lod2
,
3553 const fs_reg
&sample_index
,
3554 const fs_reg
&sampler
,
3555 const fs_reg
&offset_value
,
3556 unsigned coord_components
,
3557 unsigned grad_components
)
3559 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3560 fs_reg msg_coords
= message
;
3561 unsigned header_size
= 0;
3563 if (offset_value
.file
!= BAD_FILE
) {
3564 /* The offsets set up by the visitor are in the m1 header, so we can't
3571 for (unsigned i
= 0; i
< coord_components
; i
++) {
3572 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3573 coordinate
= offset(coordinate
, bld
, 1);
3575 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3576 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3578 if (shadow_c
.file
!= BAD_FILE
) {
3579 fs_reg msg_shadow
= msg_lod
;
3580 bld
.MOV(msg_shadow
, shadow_c
);
3581 msg_lod
= offset(msg_shadow
, bld
, 1);
3586 case SHADER_OPCODE_TXL
:
3588 bld
.MOV(msg_lod
, lod
);
3589 msg_end
= offset(msg_lod
, bld
, 1);
3591 case SHADER_OPCODE_TXD
:
3594 * dPdx = dudx, dvdx, drdx
3595 * dPdy = dudy, dvdy, drdy
3597 * Load up these values:
3598 * - dudx dudy dvdx dvdy drdx drdy
3599 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3602 for (unsigned i
= 0; i
< grad_components
; i
++) {
3603 bld
.MOV(msg_end
, lod
);
3604 lod
= offset(lod
, bld
, 1);
3605 msg_end
= offset(msg_end
, bld
, 1);
3607 bld
.MOV(msg_end
, lod2
);
3608 lod2
= offset(lod2
, bld
, 1);
3609 msg_end
= offset(msg_end
, bld
, 1);
3612 case SHADER_OPCODE_TXS
:
3613 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3614 bld
.MOV(msg_lod
, lod
);
3615 msg_end
= offset(msg_lod
, bld
, 1);
3617 case SHADER_OPCODE_TXF
:
3618 msg_lod
= offset(msg_coords
, bld
, 3);
3619 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3620 msg_end
= offset(msg_lod
, bld
, 1);
3622 case SHADER_OPCODE_TXF_CMS
:
3623 msg_lod
= offset(msg_coords
, bld
, 3);
3625 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
3627 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3628 msg_end
= offset(msg_lod
, bld
, 2);
3635 inst
->src
[0] = reg_undef
;
3636 inst
->src
[1] = sampler
;
3637 inst
->resize_sources(2);
3638 inst
->base_mrf
= message
.reg
;
3639 inst
->mlen
= msg_end
.reg
- message
.reg
;
3640 inst
->header_size
= header_size
;
3642 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3643 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3647 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3649 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3652 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
3656 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3658 const fs_reg
&shadow_c
,
3659 fs_reg lod
, fs_reg lod2
,
3660 const fs_reg
&sample_index
,
3661 const fs_reg
&mcs
, const fs_reg
&sampler
,
3662 fs_reg offset_value
,
3663 unsigned coord_components
,
3664 unsigned grad_components
)
3666 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3667 int reg_width
= bld
.dispatch_width() / 8;
3668 unsigned header_size
= 0, length
= 0;
3669 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3670 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3671 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3673 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3674 offset_value
.file
!= BAD_FILE
||
3675 is_high_sampler(devinfo
, sampler
)) {
3676 /* For general texture offsets (no txf workaround), we need a header to
3677 * put them in. Note that we're only reserving space for it in the
3678 * message payload as it will be initialized implicitly by the
3681 * TG4 needs to place its channel select in the header, for interaction
3682 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3683 * larger sampler numbers we need to offset the Sampler State Pointer in
3687 sources
[0] = fs_reg();
3691 if (shadow_c
.file
!= BAD_FILE
) {
3692 bld
.MOV(sources
[length
], shadow_c
);
3696 bool coordinate_done
= false;
3698 /* The sampler can only meaningfully compute LOD for fragment shader
3699 * messages. For all other stages, we change the opcode to TXL and
3700 * hardcode the LOD to 0.
3702 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3703 op
== SHADER_OPCODE_TEX
) {
3704 op
= SHADER_OPCODE_TXL
;
3708 /* Set up the LOD info */
3711 case SHADER_OPCODE_TXL
:
3712 bld
.MOV(sources
[length
], lod
);
3715 case SHADER_OPCODE_TXD
:
3716 /* TXD should have been lowered in SIMD16 mode. */
3717 assert(bld
.dispatch_width() == 8);
3719 /* Load dPdx and the coordinate together:
3720 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3722 for (unsigned i
= 0; i
< coord_components
; i
++) {
3723 bld
.MOV(sources
[length
], coordinate
);
3724 coordinate
= offset(coordinate
, bld
, 1);
3727 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3728 * only derivatives for (u, v, r).
3730 if (i
< grad_components
) {
3731 bld
.MOV(sources
[length
], lod
);
3732 lod
= offset(lod
, bld
, 1);
3735 bld
.MOV(sources
[length
], lod2
);
3736 lod2
= offset(lod2
, bld
, 1);
3741 coordinate_done
= true;
3743 case SHADER_OPCODE_TXS
:
3744 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3747 case SHADER_OPCODE_TXF
:
3748 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3749 * On Gen9 they are u, v, lod, r
3751 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3752 coordinate
= offset(coordinate
, bld
, 1);
3755 if (devinfo
->gen
>= 9) {
3756 if (coord_components
>= 2) {
3757 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3758 coordinate
= offset(coordinate
, bld
, 1);
3763 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
3766 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
3767 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3768 coordinate
= offset(coordinate
, bld
, 1);
3772 coordinate_done
= true;
3774 case SHADER_OPCODE_TXF_CMS
:
3775 case SHADER_OPCODE_TXF_UMS
:
3776 case SHADER_OPCODE_TXF_MCS
:
3777 if (op
== SHADER_OPCODE_TXF_UMS
|| op
== SHADER_OPCODE_TXF_CMS
) {
3778 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
3782 if (op
== SHADER_OPCODE_TXF_CMS
) {
3783 /* Data from the multisample control surface. */
3784 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
3788 /* There is no offsetting for this message; just copy in the integer
3789 * texture coordinates.
3791 for (unsigned i
= 0; i
< coord_components
; i
++) {
3792 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3793 coordinate
= offset(coordinate
, bld
, 1);
3797 coordinate_done
= true;
3799 case SHADER_OPCODE_TG4_OFFSET
:
3800 /* gather4_po_c should have been lowered in SIMD16 mode. */
3801 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
3803 /* More crazy intermixing */
3804 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
3805 bld
.MOV(sources
[length
], coordinate
);
3806 coordinate
= offset(coordinate
, bld
, 1);
3810 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
3811 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
3812 offset_value
= offset(offset_value
, bld
, 1);
3816 if (coord_components
== 3) { /* r if present */
3817 bld
.MOV(sources
[length
], coordinate
);
3818 coordinate
= offset(coordinate
, bld
, 1);
3822 coordinate_done
= true;
3828 /* Set up the coordinate (except for cases where it was done above) */
3829 if (!coordinate_done
) {
3830 for (unsigned i
= 0; i
< coord_components
; i
++) {
3831 bld
.MOV(sources
[length
], coordinate
);
3832 coordinate
= offset(coordinate
, bld
, 1);
3839 mlen
= length
* reg_width
- header_size
;
3841 mlen
= length
* reg_width
;
3843 const fs_reg src_payload
= fs_reg(GRF
, bld
.shader
->alloc
.allocate(mlen
),
3844 BRW_REGISTER_TYPE_F
);
3845 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
3847 /* Generate the SEND. */
3849 inst
->src
[0] = src_payload
;
3850 inst
->src
[1] = sampler
;
3851 inst
->resize_sources(2);
3852 inst
->base_mrf
= -1;
3854 inst
->header_size
= header_size
;
3856 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3857 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3861 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
3863 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3864 const fs_reg
&coordinate
= inst
->src
[0];
3865 const fs_reg
&shadow_c
= inst
->src
[1];
3866 const fs_reg
&lod
= inst
->src
[2];
3867 const fs_reg
&lod2
= inst
->src
[3];
3868 const fs_reg
&sample_index
= inst
->src
[4];
3869 const fs_reg
&mcs
= inst
->src
[5];
3870 const fs_reg
&sampler
= inst
->src
[6];
3871 const fs_reg
&offset_value
= inst
->src
[7];
3872 assert(inst
->src
[8].file
== IMM
&& inst
->src
[9].file
== IMM
);
3873 const unsigned coord_components
= inst
->src
[8].fixed_hw_reg
.dw1
.ud
;
3874 const unsigned grad_components
= inst
->src
[9].fixed_hw_reg
.dw1
.ud
;
3876 if (devinfo
->gen
>= 7) {
3877 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
3878 shadow_c
, lod
, lod2
, sample_index
,
3879 mcs
, sampler
, offset_value
,
3880 coord_components
, grad_components
);
3881 } else if (devinfo
->gen
>= 5) {
3882 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
3883 shadow_c
, lod
, lod2
, sample_index
,
3884 sampler
, offset_value
,
3885 coord_components
, grad_components
);
3887 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
3888 shadow_c
, lod
, lod2
, sampler
,
3889 coord_components
, grad_components
);
3894 * Initialize the header present in some typed and untyped surface
3898 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
3900 fs_builder ubld
= bld
.exec_all().group(8, 0);
3901 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3902 ubld
.MOV(dst
, fs_reg(0));
3903 ubld
.MOV(component(dst
, 7), sample_mask
);
3908 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3909 const fs_reg
&sample_mask
)
3911 /* Get the logical send arguments. */
3912 const fs_reg
&addr
= inst
->src
[0];
3913 const fs_reg
&src
= inst
->src
[1];
3914 const fs_reg
&surface
= inst
->src
[2];
3915 const UNUSED fs_reg
&dims
= inst
->src
[3];
3916 const fs_reg
&arg
= inst
->src
[4];
3918 /* Calculate the total number of components of the payload. */
3919 const unsigned addr_sz
= inst
->components_read(0);
3920 const unsigned src_sz
= inst
->components_read(1);
3921 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
3922 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
3924 /* Allocate space for the payload. */
3925 fs_reg
*const components
= new fs_reg
[sz
];
3926 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
3929 /* Construct the payload. */
3931 components
[n
++] = emit_surface_header(bld
, sample_mask
);
3933 for (unsigned i
= 0; i
< addr_sz
; i
++)
3934 components
[n
++] = offset(addr
, bld
, i
);
3936 for (unsigned i
= 0; i
< src_sz
; i
++)
3937 components
[n
++] = offset(src
, bld
, i
);
3939 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
3941 /* Update the original instruction. */
3943 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
3944 inst
->header_size
= header_sz
;
3946 inst
->src
[0] = payload
;
3947 inst
->src
[1] = surface
;
3949 inst
->resize_sources(3);
3951 delete[] components
;
3955 fs_visitor::lower_logical_sends()
3957 bool progress
= false;
3959 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3960 const fs_builder ibld
= bld
.exec_all(inst
->force_writemask_all
)
3961 .group(inst
->exec_size
, inst
->force_sechalf
)
3964 switch (inst
->opcode
) {
3965 case FS_OPCODE_FB_WRITE_LOGICAL
:
3966 assert(stage
== MESA_SHADER_FRAGMENT
);
3967 lower_fb_write_logical_send(ibld
, inst
,
3968 (const brw_wm_prog_data
*)prog_data
,
3969 (const brw_wm_prog_key
*)key
,
3973 case SHADER_OPCODE_TEX_LOGICAL
:
3974 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
3977 case SHADER_OPCODE_TXD_LOGICAL
:
3978 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
3981 case SHADER_OPCODE_TXF_LOGICAL
:
3982 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
3985 case SHADER_OPCODE_TXL_LOGICAL
:
3986 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
3989 case SHADER_OPCODE_TXS_LOGICAL
:
3990 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
3993 case FS_OPCODE_TXB_LOGICAL
:
3994 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
3997 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
3998 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4001 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4002 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4005 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4006 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4009 case SHADER_OPCODE_LOD_LOGICAL
:
4010 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4013 case SHADER_OPCODE_TG4_LOGICAL
:
4014 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4017 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4018 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4021 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4022 lower_surface_logical_send(ibld
, inst
,
4023 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4027 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4028 lower_surface_logical_send(ibld
, inst
,
4029 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4030 ibld
.sample_mask_reg());
4033 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4034 lower_surface_logical_send(ibld
, inst
,
4035 SHADER_OPCODE_UNTYPED_ATOMIC
,
4036 ibld
.sample_mask_reg());
4039 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4040 lower_surface_logical_send(ibld
, inst
,
4041 SHADER_OPCODE_TYPED_SURFACE_READ
,
4045 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4046 lower_surface_logical_send(ibld
, inst
,
4047 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4048 ibld
.sample_mask_reg());
4051 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4052 lower_surface_logical_send(ibld
, inst
,
4053 SHADER_OPCODE_TYPED_ATOMIC
,
4054 ibld
.sample_mask_reg());
4065 invalidate_live_intervals();
4071 * Get the closest native SIMD width supported by the hardware for instruction
4072 * \p inst. The instruction will be left untouched by
4073 * fs_visitor::lower_simd_width() if the returned value is equal to the
4074 * original execution size.
4077 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4078 const fs_inst
*inst
)
4080 switch (inst
->opcode
) {
4081 case FS_OPCODE_FB_WRITE_LOGICAL
:
4082 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4085 assert(devinfo
->gen
!= 6 || inst
->src
[3].file
== BAD_FILE
||
4086 inst
->exec_size
== 8);
4087 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4088 return (inst
->src
[1].file
!= BAD_FILE
? 8 : inst
->exec_size
);
4090 case SHADER_OPCODE_TXD_LOGICAL
:
4091 /* TXD is unsupported in SIMD16 mode. */
4094 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4095 /* gather4_po_c is unsupported in SIMD16 mode. */
4096 const fs_reg
&shadow_c
= inst
->src
[1];
4097 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4099 case SHADER_OPCODE_TXL_LOGICAL
:
4100 case FS_OPCODE_TXB_LOGICAL
: {
4101 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4102 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4103 * mode because the message exceeds the maximum length of 11.
4105 const fs_reg
&shadow_c
= inst
->src
[1];
4106 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4108 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4111 return inst
->exec_size
;
4113 case SHADER_OPCODE_TXF_LOGICAL
:
4114 case SHADER_OPCODE_TXS_LOGICAL
:
4115 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4116 * messages. Use SIMD16 instead.
4118 if (devinfo
->gen
== 4)
4121 return inst
->exec_size
;
4123 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4124 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4125 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4129 return inst
->exec_size
;
4134 * The \p rows array of registers represents a \p num_rows by \p num_columns
4135 * matrix in row-major order, write it in column-major order into the register
4136 * passed as destination. \p stride gives the separation between matrix
4137 * elements in the input in fs_builder::dispatch_width() units.
4140 emit_transpose(const fs_builder
&bld
,
4141 const fs_reg
&dst
, const fs_reg
*rows
,
4142 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4144 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4146 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4147 for (unsigned j
= 0; j
< num_rows
; ++j
)
4148 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4151 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4153 delete[] components
;
4157 fs_visitor::lower_simd_width()
4159 bool progress
= false;
4161 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4162 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4164 if (lower_width
!= inst
->exec_size
) {
4165 /* Builder matching the original instruction. */
4166 const fs_builder ibld
= bld
.at(block
, inst
)
4167 .exec_all(inst
->force_writemask_all
)
4168 .group(inst
->exec_size
, inst
->force_sechalf
);
4170 /* Split the copies in chunks of the execution width of either the
4171 * original or the lowered instruction, whichever is lower.
4173 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4174 const unsigned n
= inst
->exec_size
/ copy_width
;
4175 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4176 inst
->dst
.component_size(inst
->exec_size
);
4179 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4180 !inst
->writes_accumulator
&& !inst
->mlen
);
4182 for (unsigned i
= 0; i
< n
; i
++) {
4183 /* Emit a copy of the original instruction with the lowered width.
4184 * If the EOT flag was set throw it away except for the last
4185 * instruction to avoid killing the thread prematurely.
4187 fs_inst split_inst
= *inst
;
4188 split_inst
.exec_size
= lower_width
;
4189 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4191 /* Set exec_all if the lowered width is higher than the original
4192 * to avoid breaking the compiler invariant that no control
4193 * flow-masked instruction is wider than the shader's
4194 * dispatch_width. Then transform the sources and destination and
4195 * emit the lowered instruction.
4197 const fs_builder lbld
= ibld
.exec_all(lower_width
> inst
->exec_size
)
4198 .group(lower_width
, i
);
4200 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4201 if (inst
->src
[j
].file
!= BAD_FILE
&&
4202 !is_uniform(inst
->src
[j
])) {
4203 /* Get the i-th copy_width-wide chunk of the source. */
4204 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4205 const unsigned src_size
= inst
->components_read(j
);
4207 /* Use a trivial transposition to copy one every n
4208 * copy_width-wide components of the register into a
4209 * temporary passed as source to the lowered instruction.
4211 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4212 emit_transpose(lbld
.group(copy_width
, 0),
4213 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4217 if (inst
->regs_written
) {
4218 /* Allocate enough space to hold the result of the lowered
4219 * instruction and fix up the number of registers written.
4221 split_inst
.dst
= dsts
[i
] =
4222 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4223 split_inst
.regs_written
=
4224 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4228 lbld
.emit(split_inst
);
4231 if (inst
->regs_written
) {
4232 /* Distance between useful channels in the temporaries, skipping
4233 * garbage if the lowered instruction is wider than the original.
4235 const unsigned m
= lower_width
/ copy_width
;
4237 /* Interleave the components of the result from the lowered
4238 * instructions. We need to set exec_all() when copying more than
4239 * one half per component, because LOAD_PAYLOAD (in terms of which
4240 * emit_transpose is implemented) can only use the same channel
4241 * enable signals for all of its non-header sources.
4243 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4244 .group(copy_width
, 0),
4245 inst
->dst
, dsts
, n
, dst_size
, m
);
4248 inst
->remove(block
);
4254 invalidate_live_intervals();
4260 fs_visitor::dump_instructions()
4262 dump_instructions(NULL
);
4266 fs_visitor::dump_instructions(const char *name
)
4268 FILE *file
= stderr
;
4269 if (name
&& geteuid() != 0) {
4270 file
= fopen(name
, "w");
4276 calculate_register_pressure();
4277 int ip
= 0, max_pressure
= 0;
4278 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4279 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4280 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4281 dump_instruction(inst
, file
);
4284 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4287 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4288 fprintf(file
, "%4d: ", ip
++);
4289 dump_instruction(inst
, file
);
4293 if (file
!= stderr
) {
4299 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4301 dump_instruction(be_inst
, stderr
);
4305 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4307 fs_inst
*inst
= (fs_inst
*)be_inst
;
4309 if (inst
->predicate
) {
4310 fprintf(file
, "(%cf0.%d) ",
4311 inst
->predicate_inverse
? '-' : '+',
4315 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4317 fprintf(file
, ".sat");
4318 if (inst
->conditional_mod
) {
4319 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4320 if (!inst
->predicate
&&
4321 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4322 inst
->opcode
!= BRW_OPCODE_IF
&&
4323 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4324 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4327 fprintf(file
, "(%d) ", inst
->exec_size
);
4330 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4333 switch (inst
->dst
.file
) {
4335 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
4336 if (alloc
.sizes
[inst
->dst
.reg
] != inst
->regs_written
||
4337 inst
->dst
.subreg_offset
)
4338 fprintf(file
, "+%d.%d",
4339 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4342 fprintf(file
, "m%d", inst
->dst
.reg
);
4345 fprintf(file
, "(null)");
4348 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
4351 fprintf(file
, "***attr%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
4354 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
4355 switch (inst
->dst
.fixed_hw_reg
.nr
) {
4357 fprintf(file
, "null");
4359 case BRW_ARF_ADDRESS
:
4360 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
4362 case BRW_ARF_ACCUMULATOR
:
4363 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
4366 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
4367 inst
->dst
.fixed_hw_reg
.subnr
);
4370 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
4371 inst
->dst
.fixed_hw_reg
.subnr
);
4375 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
4377 if (inst
->dst
.fixed_hw_reg
.subnr
)
4378 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
4381 fprintf(file
, "???");
4384 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4386 for (int i
= 0; i
< inst
->sources
; i
++) {
4387 if (inst
->src
[i
].negate
)
4389 if (inst
->src
[i
].abs
)
4391 switch (inst
->src
[i
].file
) {
4393 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
4394 if (alloc
.sizes
[inst
->src
[i
].reg
] != (unsigned)inst
->regs_read(i
) ||
4395 inst
->src
[i
].subreg_offset
)
4396 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4397 inst
->src
[i
].subreg_offset
);
4400 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
4403 fprintf(file
, "attr%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
4406 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
4407 if (inst
->src
[i
].reladdr
) {
4408 fprintf(file
, "+reladdr");
4409 } else if (inst
->src
[i
].subreg_offset
) {
4410 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4411 inst
->src
[i
].subreg_offset
);
4415 fprintf(file
, "(null)");
4418 switch (inst
->src
[i
].type
) {
4419 case BRW_REGISTER_TYPE_F
:
4420 fprintf(file
, "%ff", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
4422 case BRW_REGISTER_TYPE_W
:
4423 case BRW_REGISTER_TYPE_D
:
4424 fprintf(file
, "%dd", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
4426 case BRW_REGISTER_TYPE_UW
:
4427 case BRW_REGISTER_TYPE_UD
:
4428 fprintf(file
, "%uu", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
4430 case BRW_REGISTER_TYPE_VF
:
4431 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4432 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
4433 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
4434 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
4435 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
4438 fprintf(file
, "???");
4443 if (inst
->src
[i
].fixed_hw_reg
.negate
)
4445 if (inst
->src
[i
].fixed_hw_reg
.abs
)
4447 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
4448 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
4450 fprintf(file
, "null");
4452 case BRW_ARF_ADDRESS
:
4453 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4455 case BRW_ARF_ACCUMULATOR
:
4456 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4459 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
4460 inst
->src
[i
].fixed_hw_reg
.subnr
);
4463 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
4464 inst
->src
[i
].fixed_hw_reg
.subnr
);
4468 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
4470 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
4471 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4472 if (inst
->src
[i
].fixed_hw_reg
.abs
)
4476 fprintf(file
, "???");
4479 if (inst
->src
[i
].abs
)
4482 if (inst
->src
[i
].file
!= IMM
) {
4483 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4486 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4487 fprintf(file
, ", ");
4492 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4493 if (inst
->force_sechalf
)
4494 fprintf(file
, "2ndhalf ");
4496 fprintf(file
, "1sthalf ");
4499 fprintf(file
, "\n");
4503 * Possibly returns an instruction that set up @param reg.
4505 * Sometimes we want to take the result of some expression/variable
4506 * dereference tree and rewrite the instruction generating the result
4507 * of the tree. When processing the tree, we know that the
4508 * instructions generated are all writing temporaries that are dead
4509 * outside of this tree. So, if we have some instructions that write
4510 * a temporary, we're free to point that temp write somewhere else.
4512 * Note that this doesn't guarantee that the instruction generated
4513 * only reg -- it might be the size=4 destination of a texture instruction.
4516 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4521 end
->is_partial_write() ||
4523 !reg
.equals(end
->dst
)) {
4531 fs_visitor::setup_payload_gen6()
4534 (prog
->InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
4535 unsigned barycentric_interp_modes
=
4536 (stage
== MESA_SHADER_FRAGMENT
) ?
4537 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4539 assert(devinfo
->gen
>= 6);
4541 /* R0-1: masks, pixel X/Y coordinates. */
4542 payload
.num_regs
= 2;
4543 /* R2: only for 32-pixel dispatch.*/
4545 /* R3-26: barycentric interpolation coordinates. These appear in the
4546 * same order that they appear in the brw_wm_barycentric_interp_mode
4547 * enum. Each set of coordinates occupies 2 registers if dispatch width
4548 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4549 * appear if they were enabled using the "Barycentric Interpolation
4550 * Mode" bits in WM_STATE.
4552 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4553 if (barycentric_interp_modes
& (1 << i
)) {
4554 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4555 payload
.num_regs
+= 2;
4556 if (dispatch_width
== 16) {
4557 payload
.num_regs
+= 2;
4562 /* R27: interpolated depth if uses source depth */
4564 payload
.source_depth_reg
= payload
.num_regs
;
4566 if (dispatch_width
== 16) {
4567 /* R28: interpolated depth if not SIMD8. */
4571 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4573 payload
.source_w_reg
= payload
.num_regs
;
4575 if (dispatch_width
== 16) {
4576 /* R30: interpolated W if not SIMD8. */
4581 if (stage
== MESA_SHADER_FRAGMENT
) {
4582 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4583 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4584 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4585 /* R31: MSAA position offsets. */
4586 if (prog_data
->uses_pos_offset
) {
4587 payload
.sample_pos_reg
= payload
.num_regs
;
4592 /* R32: MSAA input coverage mask */
4593 if (prog
->SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4594 assert(devinfo
->gen
>= 7);
4595 payload
.sample_mask_in_reg
= payload
.num_regs
;
4597 if (dispatch_width
== 16) {
4598 /* R33: input coverage mask if not SIMD8. */
4603 /* R34-: bary for 32-pixel. */
4604 /* R58-59: interp W for 32-pixel. */
4606 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4607 source_depth_to_render_target
= true;
4612 fs_visitor::setup_vs_payload()
4614 /* R0: thread header, R1: urb handles */
4615 payload
.num_regs
= 2;
4619 fs_visitor::setup_cs_payload()
4621 assert(devinfo
->gen
>= 7);
4623 payload
.num_regs
= 1;
4627 fs_visitor::assign_binding_table_offsets()
4629 assert(stage
== MESA_SHADER_FRAGMENT
);
4630 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4631 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4632 uint32_t next_binding_table_offset
= 0;
4634 /* If there are no color regions, we still perform an FB write to a null
4635 * renderbuffer, which we place at surface index 0.
4637 prog_data
->binding_table
.render_target_start
= next_binding_table_offset
;
4638 next_binding_table_offset
+= MAX2(key
->nr_color_regions
, 1);
4640 assign_common_binding_table_offsets(next_binding_table_offset
);
4644 fs_visitor::calculate_register_pressure()
4646 invalidate_live_intervals();
4647 calculate_live_intervals();
4649 unsigned num_instructions
= 0;
4650 foreach_block(block
, cfg
)
4651 num_instructions
+= block
->instructions
.length();
4653 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
4655 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
4656 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
4657 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
4662 fs_visitor::optimize()
4664 /* bld is the common builder object pointing at the end of the program we
4665 * used to translate it into i965 IR. For the optimization and lowering
4666 * passes coming next, any code added after the end of the program without
4667 * having explicitly called fs_builder::at() clearly points at a mistake.
4668 * Ideally optimization passes wouldn't be part of the visitor so they
4669 * wouldn't have access to bld at all, but they do, so just in case some
4670 * pass forgets to ask for a location explicitly set it to NULL here to
4673 bld
= bld
.at(NULL
, NULL
);
4675 split_virtual_grfs();
4677 move_uniform_array_access_to_pull_constants();
4678 assign_constant_locations();
4679 demote_pull_constants();
4681 #define OPT(pass, args...) ({ \
4683 bool this_progress = pass(args); \
4685 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
4686 char filename[64]; \
4687 snprintf(filename, 64, "%s%d-%04d-%02d-%02d-" #pass, \
4688 stage_abbrev, dispatch_width, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
4690 backend_shader::dump_instructions(filename); \
4693 progress = progress || this_progress; \
4697 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
4699 snprintf(filename
, 64, "%s%d-%04d-00-start",
4700 stage_abbrev
, dispatch_width
,
4701 shader_prog
? shader_prog
->Name
: 0);
4703 backend_shader::dump_instructions(filename
);
4706 bool progress
= false;
4710 OPT(lower_simd_width
);
4711 OPT(lower_logical_sends
);
4718 OPT(remove_duplicate_mrf_writes
);
4722 OPT(opt_copy_propagate
);
4723 OPT(opt_peephole_predicated_break
);
4724 OPT(opt_cmod_propagation
);
4725 OPT(dead_code_eliminate
);
4726 OPT(opt_peephole_sel
);
4727 OPT(dead_control_flow_eliminate
, this);
4728 OPT(opt_register_renaming
);
4729 OPT(opt_redundant_discard_jumps
);
4730 OPT(opt_saturate_propagation
);
4731 OPT(opt_zero_samples
);
4732 OPT(register_coalesce
);
4733 OPT(compute_to_mrf
);
4734 OPT(eliminate_find_live_channel
);
4736 OPT(compact_virtual_grfs
);
4741 OPT(opt_sampler_eot
);
4743 if (OPT(lower_load_payload
)) {
4744 split_virtual_grfs();
4745 OPT(register_coalesce
);
4746 OPT(compute_to_mrf
);
4747 OPT(dead_code_eliminate
);
4750 OPT(opt_combine_constants
);
4751 OPT(lower_integer_multiplication
);
4753 lower_uniform_pull_constant_loads();
4757 * Three source instruction must have a GRF/MRF destination register.
4758 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
4761 fs_visitor::fixup_3src_null_dest()
4763 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
4764 if (inst
->is_3src() && inst
->dst
.is_null()) {
4765 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
4772 fs_visitor::allocate_registers()
4774 bool allocated_without_spills
;
4776 static const enum instruction_scheduler_mode pre_modes
[] = {
4778 SCHEDULE_PRE_NON_LIFO
,
4782 /* Try each scheduling heuristic to see if it can successfully register
4783 * allocate without spilling. They should be ordered by decreasing
4784 * performance but increasing likelihood of allocating.
4786 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
4787 schedule_instructions(pre_modes
[i
]);
4790 assign_regs_trivial();
4791 allocated_without_spills
= true;
4793 allocated_without_spills
= assign_regs(false);
4795 if (allocated_without_spills
)
4799 if (!allocated_without_spills
) {
4800 /* We assume that any spilling is worse than just dropping back to
4801 * SIMD8. There's probably actually some intermediate point where
4802 * SIMD16 with a couple of spills is still better.
4804 if (dispatch_width
== 16) {
4805 fail("Failure to register allocate. Reduce number of "
4806 "live scalar values to avoid this.");
4808 compiler
->shader_perf_log(log_data
,
4809 "%s shader triggered register spilling. "
4810 "Try reducing the number of live scalar "
4811 "values to improve performance.\n",
4815 /* Since we're out of heuristics, just go spill registers until we
4816 * get an allocation.
4818 while (!assign_regs(true)) {
4824 /* This must come after all optimization and register allocation, since
4825 * it inserts dead code that happens to have side effects, and it does
4826 * so based on the actual physical registers in use.
4828 insert_gen4_send_dependency_workarounds();
4833 if (!allocated_without_spills
)
4834 schedule_instructions(SCHEDULE_POST
);
4836 if (last_scratch
> 0)
4837 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
4841 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
4843 assert(stage
== MESA_SHADER_VERTEX
);
4845 assign_common_binding_table_offsets(0);
4848 if (shader_time_index
>= 0)
4849 emit_shader_time_begin();
4856 compute_clip_distance(clip_planes
);
4860 if (shader_time_index
>= 0)
4861 emit_shader_time_end();
4867 assign_curb_setup();
4868 assign_vs_urb_setup();
4870 fixup_3src_null_dest();
4871 allocate_registers();
4877 fs_visitor::run_fs(bool do_rep_send
)
4879 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4880 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
4882 assert(stage
== MESA_SHADER_FRAGMENT
);
4884 sanity_param_count
= prog
->Parameters
->NumParameters
;
4886 assign_binding_table_offsets();
4888 if (devinfo
->gen
>= 6)
4889 setup_payload_gen6();
4891 setup_payload_gen4();
4895 } else if (do_rep_send
) {
4896 assert(dispatch_width
== 16);
4897 emit_repclear_shader();
4899 if (shader_time_index
>= 0)
4900 emit_shader_time_begin();
4902 calculate_urb_setup();
4903 if (prog
->InputsRead
> 0) {
4904 if (devinfo
->gen
< 6)
4905 emit_interpolation_setup_gen4();
4907 emit_interpolation_setup_gen6();
4910 /* We handle discards by keeping track of the still-live pixels in f0.1.
4911 * Initialize it with the dispatched pixels.
4913 if (wm_prog_data
->uses_kill
) {
4914 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
4915 discard_init
->flag_subreg
= 1;
4918 /* Generate FS IR for main(). (the visitor only descends into
4919 * functions called "main").
4926 if (wm_prog_data
->uses_kill
)
4927 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
4929 if (wm_key
->alpha_test_func
)
4934 if (shader_time_index
>= 0)
4935 emit_shader_time_end();
4941 assign_curb_setup();
4944 fixup_3src_null_dest();
4945 allocate_registers();
4951 if (dispatch_width
== 8)
4952 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
4954 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
4956 /* If any state parameters were appended, then ParameterValues could have
4957 * been realloced, in which case the driver uniform storage set up by
4958 * _mesa_associate_uniform_storage() would point to freed memory. Make
4959 * sure that didn't happen.
4961 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
4967 fs_visitor::run_cs()
4969 assert(stage
== MESA_SHADER_COMPUTE
);
4972 sanity_param_count
= prog
->Parameters
->NumParameters
;
4974 assign_common_binding_table_offsets(0);
4978 if (shader_time_index
>= 0)
4979 emit_shader_time_begin();
4986 emit_cs_terminate();
4988 if (shader_time_index
>= 0)
4989 emit_shader_time_end();
4995 assign_curb_setup();
4997 fixup_3src_null_dest();
4998 allocate_registers();
5003 /* If any state parameters were appended, then ParameterValues could have
5004 * been realloced, in which case the driver uniform storage set up by
5005 * _mesa_associate_uniform_storage() would point to freed memory. Make
5006 * sure that didn't happen.
5008 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
5014 brw_wm_fs_emit(struct brw_context
*brw
,
5016 const struct brw_wm_prog_key
*key
,
5017 struct brw_wm_prog_data
*prog_data
,
5018 struct gl_fragment_program
*fp
,
5019 struct gl_shader_program
*prog
,
5020 unsigned *final_assembly_size
)
5022 bool start_busy
= false;
5023 double start_time
= 0;
5025 if (unlikely(brw
->perf_debug
)) {
5026 start_busy
= (brw
->batch
.last_bo
&&
5027 drm_intel_bo_busy(brw
->batch
.last_bo
));
5028 start_time
= get_time();
5031 struct brw_shader
*shader
= NULL
;
5033 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
5035 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
5036 brw_dump_ir("fragment", prog
, &shader
->base
, &fp
->Base
);
5038 int st_index8
= -1, st_index16
= -1;
5039 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
5040 st_index8
= brw_get_shader_time_index(brw
, prog
, &fp
->Base
, ST_FS8
);
5041 st_index16
= brw_get_shader_time_index(brw
, prog
, &fp
->Base
, ST_FS16
);
5044 /* Now the main event: Visit the shader IR and generate our FS IR for it.
5046 fs_visitor
v(brw
->intelScreen
->compiler
, brw
,
5047 mem_ctx
, MESA_SHADER_FRAGMENT
, key
, &prog_data
->base
,
5048 prog
, &fp
->Base
, 8, st_index8
);
5049 if (!v
.run_fs(false /* do_rep_send */)) {
5051 prog
->LinkStatus
= false;
5052 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
5055 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
5061 cfg_t
*simd16_cfg
= NULL
;
5062 fs_visitor
v2(brw
->intelScreen
->compiler
, brw
,
5063 mem_ctx
, MESA_SHADER_FRAGMENT
, key
, &prog_data
->base
,
5064 prog
, &fp
->Base
, 16, st_index16
);
5065 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || brw
->use_rep_send
)) {
5066 if (!v
.simd16_unsupported
) {
5067 /* Try a SIMD16 compile */
5068 v2
.import_uniforms(&v
);
5069 if (!v2
.run_fs(brw
->use_rep_send
)) {
5070 perf_debug("SIMD16 shader failed to compile: %s", v2
.fail_msg
);
5072 simd16_cfg
= v2
.cfg
;
5078 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || brw
->no_simd8
;
5079 if ((no_simd8
|| brw
->gen
< 5) && simd16_cfg
) {
5081 prog_data
->no_8
= true;
5084 prog_data
->no_8
= false;
5087 fs_generator
g(brw
->intelScreen
->compiler
, brw
,
5088 mem_ctx
, (void *) key
, &prog_data
->base
,
5089 &fp
->Base
, v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
5091 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5094 name
= ralloc_asprintf(mem_ctx
, "%s fragment shader %d",
5095 prog
->Label
? prog
->Label
: "unnamed",
5098 name
= ralloc_asprintf(mem_ctx
, "fragment program %d", fp
->Base
.Id
);
5100 g
.enable_debug(name
);
5104 g
.generate_code(simd8_cfg
, 8);
5106 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5108 if (unlikely(brw
->perf_debug
) && shader
) {
5109 if (shader
->compiled_once
)
5110 brw_wm_debug_recompile(brw
, prog
, key
);
5111 shader
->compiled_once
= true;
5113 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
5114 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
5115 (get_time() - start_time
) * 1000);
5119 return g
.get_assembly(final_assembly_size
);
5123 brw_fs_precompile(struct gl_context
*ctx
,
5124 struct gl_shader_program
*shader_prog
,
5125 struct gl_program
*prog
)
5127 struct brw_context
*brw
= brw_context(ctx
);
5128 struct brw_wm_prog_key key
;
5130 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*) prog
;
5131 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
5132 bool program_uses_dfdy
= fp
->UsesDFdy
;
5134 memset(&key
, 0, sizeof(key
));
5138 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
5140 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
5141 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
5143 /* Just assume depth testing. */
5144 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
5145 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
5148 if (brw
->gen
< 6 || _mesa_bitcount_64(fp
->Base
.InputsRead
&
5149 BRW_FS_VARYING_INPUT_MASK
) > 16)
5150 key
.input_slots_valid
= fp
->Base
.InputsRead
| VARYING_BIT_POS
;
5152 brw_setup_tex_for_precompile(brw
, &key
.tex
, &fp
->Base
);
5154 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
) {
5155 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
5158 key
.nr_color_regions
= _mesa_bitcount_64(fp
->Base
.OutputsWritten
&
5159 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
5160 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
)));
5162 if ((fp
->Base
.InputsRead
& VARYING_BIT_POS
) || program_uses_dfdy
) {
5163 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
) ||
5164 key
.nr_color_regions
> 1;
5167 key
.program_string_id
= bfp
->id
;
5169 uint32_t old_prog_offset
= brw
->wm
.base
.prog_offset
;
5170 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
5172 bool success
= brw_codegen_wm_prog(brw
, shader_prog
, bfp
, &key
);
5174 brw
->wm
.base
.prog_offset
= old_prog_offset
;
5175 brw
->wm
.prog_data
= old_prog_data
;
5181 brw_setup_tex_for_precompile(struct brw_context
*brw
,
5182 struct brw_sampler_prog_key_data
*tex
,
5183 struct gl_program
*prog
)
5185 const bool has_shader_channel_select
= brw
->is_haswell
|| brw
->gen
>= 8;
5186 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
5187 for (unsigned i
= 0; i
< sampler_count
; i
++) {
5188 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
5189 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
5191 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
5193 /* Color sampler: assume no swizzling. */
5194 tex
->swizzles
[i
] = SWIZZLE_XYZW
;