2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "../glsl/glsl_types.h"
48 #include "../glsl/ir_optimization.h"
49 #include "../glsl/ir_print_visitor.h"
51 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
54 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
56 struct brw_shader
*shader
;
58 shader
= talloc_zero(NULL
, struct brw_shader
);
60 shader
->base
.Type
= type
;
61 shader
->base
.Name
= name
;
62 _mesa_init_shader(ctx
, &shader
->base
);
68 struct gl_shader_program
*
69 brw_new_shader_program(struct gl_context
*ctx
, GLuint name
)
71 struct brw_shader_program
*prog
;
72 prog
= talloc_zero(NULL
, struct brw_shader_program
);
74 prog
->base
.Name
= name
;
75 _mesa_init_shader_program(ctx
, &prog
->base
);
81 brw_compile_shader(struct gl_context
*ctx
, struct gl_shader
*shader
)
83 if (!_mesa_ir_compile_shader(ctx
, shader
))
90 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
92 struct intel_context
*intel
= intel_context(ctx
);
94 struct brw_shader
*shader
=
95 (struct brw_shader
*)prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
97 void *mem_ctx
= talloc_new(NULL
);
101 talloc_free(shader
->ir
);
102 shader
->ir
= new(shader
) exec_list
;
103 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
105 do_mat_op_to_vec(shader
->ir
);
106 do_mod_to_fract(shader
->ir
);
107 do_div_to_mul_rcp(shader
->ir
);
108 do_sub_to_add_neg(shader
->ir
);
109 do_explog_to_explog2(shader
->ir
);
110 do_lower_texture_projection(shader
->ir
);
111 brw_do_cubemap_normalize(shader
->ir
);
116 brw_do_channel_expressions(shader
->ir
);
117 brw_do_vector_splitting(shader
->ir
);
119 progress
= do_lower_jumps(shader
->ir
, true, true,
120 true, /* main return */
121 false, /* continue */
125 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
127 progress
= lower_noise(shader
->ir
) || progress
;
129 lower_variable_index_to_cond_assign(shader
->ir
,
131 GL_TRUE
, /* output */
133 GL_TRUE
/* uniform */
135 if (intel
->gen
== 6) {
136 progress
= do_if_to_cond_assign(shader
->ir
) || progress
;
140 validate_ir_tree(shader
->ir
);
142 reparent_ir(shader
->ir
, shader
->ir
);
143 talloc_free(mem_ctx
);
146 if (!_mesa_ir_link_shader(ctx
, prog
))
153 type_size(const struct glsl_type
*type
)
155 unsigned int size
, i
;
157 switch (type
->base_type
) {
160 case GLSL_TYPE_FLOAT
:
162 return type
->components();
163 case GLSL_TYPE_ARRAY
:
164 return type_size(type
->fields
.array
) * type
->length
;
165 case GLSL_TYPE_STRUCT
:
167 for (i
= 0; i
< type
->length
; i
++) {
168 size
+= type_size(type
->fields
.structure
[i
].type
);
171 case GLSL_TYPE_SAMPLER
:
172 /* Samplers take up no register space, since they're baked in at
177 assert(!"not reached");
183 fs_visitor::virtual_grf_alloc(int size
)
185 if (virtual_grf_array_size
<= virtual_grf_next
) {
186 if (virtual_grf_array_size
== 0)
187 virtual_grf_array_size
= 16;
189 virtual_grf_array_size
*= 2;
190 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
191 int, virtual_grf_array_size
);
193 /* This slot is always unused. */
194 virtual_grf_sizes
[0] = 0;
196 virtual_grf_sizes
[virtual_grf_next
] = size
;
197 return virtual_grf_next
++;
200 /** Fixed HW reg constructor. */
201 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
205 this->hw_reg
= hw_reg
;
206 this->type
= BRW_REGISTER_TYPE_F
;
209 /** Fixed HW reg constructor. */
210 fs_reg::fs_reg(enum register_file file
, int hw_reg
, uint32_t type
)
214 this->hw_reg
= hw_reg
;
219 brw_type_for_base_type(const struct glsl_type
*type
)
221 switch (type
->base_type
) {
222 case GLSL_TYPE_FLOAT
:
223 return BRW_REGISTER_TYPE_F
;
226 return BRW_REGISTER_TYPE_D
;
228 return BRW_REGISTER_TYPE_UD
;
229 case GLSL_TYPE_ARRAY
:
230 case GLSL_TYPE_STRUCT
:
231 /* These should be overridden with the type of the member when
232 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
233 * way to trip up if we don't.
235 return BRW_REGISTER_TYPE_UD
;
237 assert(!"not reached");
238 return BRW_REGISTER_TYPE_F
;
242 /** Automatic reg constructor. */
243 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
248 this->reg
= v
->virtual_grf_alloc(type_size(type
));
249 this->reg_offset
= 0;
250 this->type
= brw_type_for_base_type(type
);
254 fs_visitor::variable_storage(ir_variable
*var
)
256 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
259 /* Our support for uniforms is piggy-backed on the struct
260 * gl_fragment_program, because that's where the values actually
261 * get stored, rather than in some global gl_shader_program uniform
265 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
267 unsigned int offset
= 0;
270 if (type
->is_matrix()) {
271 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
272 type
->vector_elements
,
275 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
276 offset
+= setup_uniform_values(loc
+ offset
, column
);
282 switch (type
->base_type
) {
283 case GLSL_TYPE_FLOAT
:
287 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
288 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
289 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
293 case GLSL_TYPE_STRUCT
:
294 for (unsigned int i
= 0; i
< type
->length
; i
++) {
295 offset
+= setup_uniform_values(loc
+ offset
,
296 type
->fields
.structure
[i
].type
);
300 case GLSL_TYPE_ARRAY
:
301 for (unsigned int i
= 0; i
< type
->length
; i
++) {
302 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
306 case GLSL_TYPE_SAMPLER
:
307 /* The sampler takes up a slot, but we don't use any values from it. */
311 assert(!"not reached");
317 /* Our support for builtin uniforms is even scarier than non-builtin.
318 * It sits on top of the PROG_STATE_VAR parameters that are
319 * automatically updated from GL context state.
322 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
324 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
326 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
327 statevar
= &_mesa_builtin_uniform_desc
[i
];
328 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
332 if (!statevar
->name
) {
334 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
339 if (ir
->type
->is_array()) {
340 array_count
= ir
->type
->length
;
345 for (int a
= 0; a
< array_count
; a
++) {
346 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
347 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
348 int tokens
[STATE_LENGTH
];
350 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
351 if (ir
->type
->is_array()) {
355 /* This state reference has already been setup by ir_to_mesa,
356 * but we'll get the same index back here.
358 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
359 (gl_state_index
*)tokens
);
360 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
362 /* Add each of the unique swizzles of the element as a
363 * parameter. This'll end up matching the expected layout of
364 * the array/matrix/structure we're trying to fill in.
367 for (unsigned int i
= 0; i
< 4; i
++) {
368 int swiz
= GET_SWZ(element
->swizzle
, i
);
369 if (swiz
== last_swiz
)
373 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
380 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
382 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
384 fs_reg neg_y
= this->pixel_y
;
388 if (ir
->pixel_center_integer
) {
389 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
391 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
396 if (ir
->origin_upper_left
&& ir
->pixel_center_integer
) {
397 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
399 fs_reg pixel_y
= this->pixel_y
;
400 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
402 if (!ir
->origin_upper_left
) {
403 pixel_y
.negate
= true;
404 offset
+= c
->key
.drawable_height
- 1.0;
407 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
412 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
413 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
416 /* gl_FragCoord.w: Already set up in emit_interpolation */
417 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
423 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
425 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
426 /* Interpolation is always in floating point regs. */
427 reg
->type
= BRW_REGISTER_TYPE_F
;
430 unsigned int array_elements
;
431 const glsl_type
*type
;
433 if (ir
->type
->is_array()) {
434 array_elements
= ir
->type
->length
;
435 if (array_elements
== 0) {
438 type
= ir
->type
->fields
.array
;
444 int location
= ir
->location
;
445 for (unsigned int i
= 0; i
< array_elements
; i
++) {
446 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
447 if (urb_setup
[location
] == -1) {
448 /* If there's no incoming setup data for this slot, don't
449 * emit interpolation for it.
451 attr
.reg_offset
+= type
->vector_elements
;
456 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
457 struct brw_reg interp
= interp_reg(location
, c
);
458 emit(fs_inst(FS_OPCODE_LINTERP
,
466 if (intel
->gen
< 6) {
467 attr
.reg_offset
-= type
->vector_elements
;
468 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
469 emit(fs_inst(BRW_OPCODE_MUL
,
484 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
486 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
488 /* The frontfacing comes in as a bit in the thread payload. */
489 if (intel
->gen
>= 6) {
490 emit(fs_inst(BRW_OPCODE_ASR
,
492 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
494 emit(fs_inst(BRW_OPCODE_NOT
,
497 emit(fs_inst(BRW_OPCODE_AND
,
502 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
503 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
506 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
510 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
511 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
518 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src
)
530 assert(!"not reached: bad math opcode");
534 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
535 * might be able to do better by doing execsize = 1 math and then
536 * expanding that result out, but we would need to be careful with
539 if (intel
->gen
>= 6 && src
.file
== UNIFORM
) {
540 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
541 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src
));
545 fs_inst
*inst
= emit(fs_inst(opcode
, dst
, src
));
547 if (intel
->gen
< 6) {
556 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
561 assert(opcode
== FS_OPCODE_POW
);
563 if (intel
->gen
>= 6) {
564 /* Can't do hstride == 0 args to gen6 math, so expand it out. */
565 if (src0
.file
== UNIFORM
) {
566 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
567 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src0
));
571 if (src1
.file
== UNIFORM
) {
572 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
573 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src1
));
577 inst
= emit(fs_inst(opcode
, dst
, src0
, src1
));
579 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1), src1
));
580 inst
= emit(fs_inst(opcode
, dst
, src0
, reg_null_f
));
582 inst
->base_mrf
= base_mrf
;
589 fs_visitor::visit(ir_variable
*ir
)
593 if (variable_storage(ir
))
596 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
597 this->frag_color
= ir
;
598 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
599 this->frag_data
= ir
;
600 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
601 this->frag_depth
= ir
;
604 if (ir
->mode
== ir_var_in
) {
605 if (!strcmp(ir
->name
, "gl_FragCoord")) {
606 reg
= emit_fragcoord_interpolation(ir
);
607 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
608 reg
= emit_frontfacing_interpolation(ir
);
610 reg
= emit_general_interpolation(ir
);
613 hash_table_insert(this->variable_ht
, reg
, ir
);
617 if (ir
->mode
== ir_var_uniform
) {
618 int param_index
= c
->prog_data
.nr_params
;
620 if (!strncmp(ir
->name
, "gl_", 3)) {
621 setup_builtin_uniform_values(ir
);
623 setup_uniform_values(ir
->location
, ir
->type
);
626 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
630 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
632 hash_table_insert(this->variable_ht
, reg
, ir
);
636 fs_visitor::visit(ir_dereference_variable
*ir
)
638 fs_reg
*reg
= variable_storage(ir
->var
);
643 fs_visitor::visit(ir_dereference_record
*ir
)
645 const glsl_type
*struct_type
= ir
->record
->type
;
647 ir
->record
->accept(this);
649 unsigned int offset
= 0;
650 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
651 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
653 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
655 this->result
.reg_offset
+= offset
;
656 this->result
.type
= brw_type_for_base_type(ir
->type
);
660 fs_visitor::visit(ir_dereference_array
*ir
)
665 ir
->array
->accept(this);
666 index
= ir
->array_index
->as_constant();
668 element_size
= type_size(ir
->type
);
669 this->result
.type
= brw_type_for_base_type(ir
->type
);
672 assert(this->result
.file
== UNIFORM
||
673 (this->result
.file
== GRF
&&
674 this->result
.reg
!= 0));
675 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
677 assert(!"FINISHME: non-constant array element");
682 fs_visitor::visit(ir_expression
*ir
)
684 unsigned int operand
;
688 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
689 ir
->operands
[operand
]->accept(this);
690 if (this->result
.file
== BAD_FILE
) {
692 printf("Failed to get tree for expression operand:\n");
693 ir
->operands
[operand
]->accept(&v
);
696 op
[operand
] = this->result
;
698 /* Matrix expression operands should have been broken down to vector
699 * operations already.
701 assert(!ir
->operands
[operand
]->type
->is_matrix());
702 /* And then those vector operands should have been broken down to scalar.
704 assert(!ir
->operands
[operand
]->type
->is_vector());
707 /* Storage for our result. If our result goes into an assignment, it will
708 * just get copy-propagated out, so no worries.
710 this->result
= fs_reg(this, ir
->type
);
712 switch (ir
->operation
) {
713 case ir_unop_logic_not
:
714 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
715 * ones complement of the whole register, not just bit 0.
717 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1)));
720 op
[0].negate
= !op
[0].negate
;
721 this->result
= op
[0];
725 this->result
= op
[0];
728 temp
= fs_reg(this, ir
->type
);
730 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
732 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
733 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
734 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
735 inst
->predicated
= true;
737 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
738 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
739 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
740 inst
->predicated
= true;
744 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
748 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
751 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
755 assert(!"not reached: should be handled by ir_explog_to_explog2");
758 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
761 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
765 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
768 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
772 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
775 assert(!"not reached: should be handled by ir_sub_to_add_neg");
779 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
782 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
785 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
789 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
790 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
791 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
793 case ir_binop_greater
:
794 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
795 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
796 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
798 case ir_binop_lequal
:
799 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
800 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
801 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
803 case ir_binop_gequal
:
804 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
805 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
806 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
809 case ir_binop_all_equal
: /* same as nequal for scalars */
810 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
811 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
812 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
814 case ir_binop_nequal
:
815 case ir_binop_any_nequal
: /* same as nequal for scalars */
816 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
817 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
818 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
821 case ir_binop_logic_xor
:
822 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
825 case ir_binop_logic_or
:
826 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
829 case ir_binop_logic_and
:
830 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
836 assert(!"not reached: should be handled by brw_fs_channel_expressions");
840 assert(!"not reached: should be handled by lower_noise");
844 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
848 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
855 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
859 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
860 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
861 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
,
862 this->result
, fs_reg(1)));
866 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
869 op
[0].negate
= !op
[0].negate
;
870 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
871 this->result
.negate
= true;
874 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
877 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
879 case ir_unop_round_even
:
880 emit(fs_inst(BRW_OPCODE_RNDE
, this->result
, op
[0]));
884 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
885 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
887 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
888 inst
->predicated
= true;
891 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
892 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
894 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
895 inst
->predicated
= true;
899 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
902 case ir_unop_bit_not
:
904 case ir_binop_lshift
:
905 case ir_binop_rshift
:
906 case ir_binop_bit_and
:
907 case ir_binop_bit_xor
:
908 case ir_binop_bit_or
:
909 assert(!"GLSL 1.30 features unsupported");
915 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
916 const glsl_type
*type
, bool predicated
)
918 switch (type
->base_type
) {
919 case GLSL_TYPE_FLOAT
:
923 for (unsigned int i
= 0; i
< type
->components(); i
++) {
924 l
.type
= brw_type_for_base_type(type
);
925 r
.type
= brw_type_for_base_type(type
);
927 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
928 inst
->predicated
= predicated
;
934 case GLSL_TYPE_ARRAY
:
935 for (unsigned int i
= 0; i
< type
->length
; i
++) {
936 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
940 case GLSL_TYPE_STRUCT
:
941 for (unsigned int i
= 0; i
< type
->length
; i
++) {
942 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
947 case GLSL_TYPE_SAMPLER
:
951 assert(!"not reached");
957 fs_visitor::visit(ir_assignment
*ir
)
962 /* FINISHME: arrays on the lhs */
963 ir
->lhs
->accept(this);
966 ir
->rhs
->accept(this);
969 assert(l
.file
!= BAD_FILE
);
970 assert(r
.file
!= BAD_FILE
);
973 emit_bool_to_cond_code(ir
->condition
);
976 if (ir
->lhs
->type
->is_scalar() ||
977 ir
->lhs
->type
->is_vector()) {
978 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
979 if (ir
->write_mask
& (1 << i
)) {
980 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
982 inst
->predicated
= true;
988 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
993 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1003 if (ir
->shadow_comparitor
) {
1004 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1005 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1007 coordinate
.reg_offset
++;
1009 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1012 if (ir
->op
== ir_tex
) {
1013 /* There's no plain shadow compare message, so we use shadow
1014 * compare with a bias of 0.0.
1016 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1019 } else if (ir
->op
== ir_txb
) {
1020 ir
->lod_info
.bias
->accept(this);
1021 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1025 assert(ir
->op
== ir_txl
);
1026 ir
->lod_info
.lod
->accept(this);
1027 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1032 ir
->shadow_comparitor
->accept(this);
1033 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1035 } else if (ir
->op
== ir_tex
) {
1036 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1037 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1039 coordinate
.reg_offset
++;
1041 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1044 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1045 * instructions. We'll need to do SIMD16 here.
1047 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1049 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1050 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2),
1052 coordinate
.reg_offset
++;
1055 /* lod/bias appears after u/v/r. */
1058 if (ir
->op
== ir_txb
) {
1059 ir
->lod_info
.bias
->accept(this);
1060 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1064 ir
->lod_info
.lod
->accept(this);
1065 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1070 /* The unused upper half. */
1073 /* Now, since we're doing simd16, the return is 2 interleaved
1074 * vec4s where the odd-indexed ones are junk. We'll need to move
1075 * this weirdness around to the expected layout.
1079 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1081 dst
.type
= BRW_REGISTER_TYPE_F
;
1084 fs_inst
*inst
= NULL
;
1087 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1090 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1093 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1097 assert(!"GLSL 1.30 features unsupported");
1100 inst
->base_mrf
= base_mrf
;
1104 for (int i
= 0; i
< 4; i
++) {
1105 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1106 orig_dst
.reg_offset
++;
1107 dst
.reg_offset
+= 2;
1115 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1117 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1118 * optional parameters like shadow comparitor or LOD bias. If
1119 * optional parameters aren't present, those base slots are
1120 * optional and don't need to be included in the message.
1122 * We don't fill in the unnecessary slots regardless, which may
1123 * look surprising in the disassembly.
1125 int mlen
= 1; /* g0 header always present. */
1128 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1129 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1131 coordinate
.reg_offset
++;
1133 mlen
+= ir
->coordinate
->type
->vector_elements
;
1135 if (ir
->shadow_comparitor
) {
1136 mlen
= MAX2(mlen
, 5);
1138 ir
->shadow_comparitor
->accept(this);
1139 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1143 fs_inst
*inst
= NULL
;
1146 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1149 ir
->lod_info
.bias
->accept(this);
1150 mlen
= MAX2(mlen
, 5);
1151 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1154 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1157 ir
->lod_info
.lod
->accept(this);
1158 mlen
= MAX2(mlen
, 5);
1159 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1162 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1166 assert(!"GLSL 1.30 features unsupported");
1169 inst
->base_mrf
= base_mrf
;
1176 fs_visitor::visit(ir_texture
*ir
)
1179 fs_inst
*inst
= NULL
;
1181 ir
->coordinate
->accept(this);
1182 fs_reg coordinate
= this->result
;
1184 /* Should be lowered by do_lower_texture_projection */
1185 assert(!ir
->projector
);
1187 sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
1188 ctx
->Shader
.CurrentProgram
,
1189 &brw
->fragment_program
->Base
);
1190 sampler
= c
->fp
->program
.Base
.SamplerUnits
[sampler
];
1192 /* The 965 requires the EU to do the normalization of GL rectangle
1193 * texture coordinates. We use the program parameter state
1194 * tracking to get the scaling factor.
1196 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1197 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1198 int tokens
[STATE_LENGTH
] = {
1200 STATE_TEXRECT_SCALE
,
1206 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1207 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1208 GLuint index
= _mesa_add_state_reference(params
,
1209 (gl_state_index
*)tokens
);
1210 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
1212 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[0];
1213 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[1];
1215 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1216 fs_reg src
= coordinate
;
1219 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_x
));
1222 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_y
));
1225 /* Writemasking doesn't eliminate channels on SIMD8 texture
1226 * samples, so don't worry about them.
1228 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1230 if (intel
->gen
< 5) {
1231 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1233 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1236 inst
->sampler
= sampler
;
1240 if (ir
->shadow_comparitor
)
1241 inst
->shadow_compare
= true;
1243 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1244 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1246 for (int i
= 0; i
< 4; i
++) {
1247 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1248 fs_reg l
= swizzle_dst
;
1251 if (swiz
== SWIZZLE_ZERO
) {
1252 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1253 } else if (swiz
== SWIZZLE_ONE
) {
1254 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1257 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1258 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1261 this->result
= swizzle_dst
;
1266 fs_visitor::visit(ir_swizzle
*ir
)
1268 ir
->val
->accept(this);
1269 fs_reg val
= this->result
;
1271 if (ir
->type
->vector_elements
== 1) {
1272 this->result
.reg_offset
+= ir
->mask
.x
;
1276 fs_reg result
= fs_reg(this, ir
->type
);
1277 this->result
= result
;
1279 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1280 fs_reg channel
= val
;
1298 channel
.reg_offset
+= swiz
;
1299 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1300 result
.reg_offset
++;
1305 fs_visitor::visit(ir_discard
*ir
)
1307 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1309 assert(ir
->condition
== NULL
); /* FINISHME */
1311 emit(fs_inst(FS_OPCODE_DISCARD_NOT
, temp
, reg_null_d
));
1312 emit(fs_inst(FS_OPCODE_DISCARD_AND
, reg_null_d
, temp
));
1313 kill_emitted
= true;
1317 fs_visitor::visit(ir_constant
*ir
)
1319 fs_reg
reg(this, ir
->type
);
1322 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1323 switch (ir
->type
->base_type
) {
1324 case GLSL_TYPE_FLOAT
:
1325 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1327 case GLSL_TYPE_UINT
:
1328 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1331 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1333 case GLSL_TYPE_BOOL
:
1334 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1337 assert(!"Non-float/uint/int/bool constant");
1344 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1346 ir_expression
*expr
= ir
->as_expression();
1352 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1353 assert(expr
->operands
[i
]->type
->is_scalar());
1355 expr
->operands
[i
]->accept(this);
1356 op
[i
] = this->result
;
1359 switch (expr
->operation
) {
1360 case ir_unop_logic_not
:
1361 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1)));
1362 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1365 case ir_binop_logic_xor
:
1366 inst
= emit(fs_inst(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]));
1367 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1370 case ir_binop_logic_or
:
1371 inst
= emit(fs_inst(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]));
1372 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1375 case ir_binop_logic_and
:
1376 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]));
1377 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1381 if (intel
->gen
>= 6) {
1382 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1383 op
[0], fs_reg(0.0f
)));
1385 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1387 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1391 if (intel
->gen
>= 6) {
1392 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0)));
1394 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1396 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1399 case ir_binop_greater
:
1400 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1401 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1403 case ir_binop_gequal
:
1404 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1405 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1408 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1409 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1411 case ir_binop_lequal
:
1412 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1413 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1415 case ir_binop_equal
:
1416 case ir_binop_all_equal
:
1417 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1418 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1420 case ir_binop_nequal
:
1421 case ir_binop_any_nequal
:
1422 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1423 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1426 assert(!"not reached");
1435 if (intel
->gen
>= 6) {
1436 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
,
1437 this->result
, fs_reg(1)));
1438 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1440 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, this->result
));
1441 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1446 * Emit a gen6 IF statement with the comparison folded into the IF
1450 fs_visitor::emit_if_gen6(ir_if
*ir
)
1452 ir_expression
*expr
= ir
->condition
->as_expression();
1459 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1460 assert(expr
->operands
[i
]->type
->is_scalar());
1462 expr
->operands
[i
]->accept(this);
1463 op
[i
] = this->result
;
1466 switch (expr
->operation
) {
1467 case ir_unop_logic_not
:
1468 inst
= emit(fs_inst(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(1)));
1469 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1472 case ir_binop_logic_xor
:
1473 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1474 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1477 case ir_binop_logic_or
:
1478 temp
= fs_reg(this, glsl_type::bool_type
);
1479 emit(fs_inst(BRW_OPCODE_OR
, temp
, op
[0], op
[1]));
1480 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1481 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1484 case ir_binop_logic_and
:
1485 temp
= fs_reg(this, glsl_type::bool_type
);
1486 emit(fs_inst(BRW_OPCODE_AND
, temp
, op
[0], op
[1]));
1487 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1488 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1492 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0)));
1493 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1497 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1498 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1501 case ir_binop_greater
:
1502 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1503 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1505 case ir_binop_gequal
:
1506 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1507 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1510 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1511 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1513 case ir_binop_lequal
:
1514 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1515 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1517 case ir_binop_equal
:
1518 case ir_binop_all_equal
:
1519 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1520 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1522 case ir_binop_nequal
:
1523 case ir_binop_any_nequal
:
1524 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1525 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1528 assert(!"not reached");
1529 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1530 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1537 ir
->condition
->accept(this);
1539 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0)));
1540 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1544 fs_visitor::visit(ir_if
*ir
)
1548 /* Don't point the annotation at the if statement, because then it plus
1549 * the then and else blocks get printed.
1551 this->base_ir
= ir
->condition
;
1553 if (intel
->gen
>= 6) {
1556 emit_bool_to_cond_code(ir
->condition
);
1558 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1559 inst
->predicated
= true;
1562 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1563 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1569 if (!ir
->else_instructions
.is_empty()) {
1570 emit(fs_inst(BRW_OPCODE_ELSE
));
1572 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1573 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1580 emit(fs_inst(BRW_OPCODE_ENDIF
));
1584 fs_visitor::visit(ir_loop
*ir
)
1586 fs_reg counter
= reg_undef
;
1589 this->base_ir
= ir
->counter
;
1590 ir
->counter
->accept(this);
1591 counter
= *(variable_storage(ir
->counter
));
1594 this->base_ir
= ir
->from
;
1595 ir
->from
->accept(this);
1597 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1601 emit(fs_inst(BRW_OPCODE_DO
));
1604 this->base_ir
= ir
->to
;
1605 ir
->to
->accept(this);
1607 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1608 counter
, this->result
));
1610 case ir_binop_equal
:
1611 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1613 case ir_binop_nequal
:
1614 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1616 case ir_binop_gequal
:
1617 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1619 case ir_binop_lequal
:
1620 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1622 case ir_binop_greater
:
1623 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1626 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1629 assert(!"not reached: unknown loop condition");
1634 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1635 inst
->predicated
= true;
1638 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1639 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1645 if (ir
->increment
) {
1646 this->base_ir
= ir
->increment
;
1647 ir
->increment
->accept(this);
1648 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1651 emit(fs_inst(BRW_OPCODE_WHILE
));
1655 fs_visitor::visit(ir_loop_jump
*ir
)
1658 case ir_loop_jump::jump_break
:
1659 emit(fs_inst(BRW_OPCODE_BREAK
));
1661 case ir_loop_jump::jump_continue
:
1662 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1668 fs_visitor::visit(ir_call
*ir
)
1670 assert(!"FINISHME");
1674 fs_visitor::visit(ir_return
*ir
)
1676 assert(!"FINISHME");
1680 fs_visitor::visit(ir_function
*ir
)
1682 /* Ignore function bodies other than main() -- we shouldn't see calls to
1683 * them since they should all be inlined before we get to ir_to_mesa.
1685 if (strcmp(ir
->name
, "main") == 0) {
1686 const ir_function_signature
*sig
;
1689 sig
= ir
->matching_signature(&empty
);
1693 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1694 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1703 fs_visitor::visit(ir_function_signature
*ir
)
1705 assert(!"not reached");
1710 fs_visitor::emit(fs_inst inst
)
1712 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1715 list_inst
->annotation
= this->current_annotation
;
1716 list_inst
->ir
= this->base_ir
;
1718 this->instructions
.push_tail(list_inst
);
1723 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1725 fs_visitor::emit_dummy_fs()
1727 /* Everyone's favorite color. */
1728 emit(fs_inst(BRW_OPCODE_MOV
,
1731 emit(fs_inst(BRW_OPCODE_MOV
,
1734 emit(fs_inst(BRW_OPCODE_MOV
,
1737 emit(fs_inst(BRW_OPCODE_MOV
,
1742 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1745 write
->base_mrf
= 0;
1748 /* The register location here is relative to the start of the URB
1749 * data. It will get adjusted to be a real location before
1750 * generate_code() time.
1753 fs_visitor::interp_reg(int location
, int channel
)
1755 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1756 int stride
= (channel
& 1) * 4;
1758 assert(urb_setup
[location
] != -1);
1760 return brw_vec1_grf(regnr
, stride
);
1763 /** Emits the interpolation for the varying inputs. */
1765 fs_visitor::emit_interpolation_setup_gen4()
1767 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1769 this->current_annotation
= "compute pixel centers";
1770 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1771 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1772 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1773 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1774 emit(fs_inst(BRW_OPCODE_ADD
,
1776 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1777 fs_reg(brw_imm_v(0x10101010))));
1778 emit(fs_inst(BRW_OPCODE_ADD
,
1780 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1781 fs_reg(brw_imm_v(0x11001100))));
1783 this->current_annotation
= "compute pixel deltas from v0";
1785 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1786 this->delta_y
= this->delta_x
;
1787 this->delta_y
.reg_offset
++;
1789 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1790 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1792 emit(fs_inst(BRW_OPCODE_ADD
,
1795 fs_reg(negate(brw_vec1_grf(1, 0)))));
1796 emit(fs_inst(BRW_OPCODE_ADD
,
1799 fs_reg(negate(brw_vec1_grf(1, 1)))));
1801 this->current_annotation
= "compute pos.w and 1/pos.w";
1802 /* Compute wpos.w. It's always in our setup, since it's needed to
1803 * interpolate the other attributes.
1805 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1806 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1807 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1808 /* Compute the pixel 1/W value from wpos.w. */
1809 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1810 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1811 this->current_annotation
= NULL
;
1814 /** Emits the interpolation for the varying inputs. */
1816 fs_visitor::emit_interpolation_setup_gen6()
1818 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1820 /* If the pixel centers end up used, the setup is the same as for gen4. */
1821 this->current_annotation
= "compute pixel centers";
1822 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1823 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1824 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1825 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1826 emit(fs_inst(BRW_OPCODE_ADD
,
1828 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1829 fs_reg(brw_imm_v(0x10101010))));
1830 emit(fs_inst(BRW_OPCODE_ADD
,
1832 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1833 fs_reg(brw_imm_v(0x11001100))));
1835 /* As of gen6, we can no longer mix float and int sources. We have
1836 * to turn the integer pixel centers into floats for their actual
1839 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1840 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1841 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
));
1842 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
));
1844 this->current_annotation
= "compute 1/pos.w";
1845 this->wpos_w
= fs_reg(brw_vec8_grf(c
->key
.source_w_reg
, 0));
1846 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1847 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1849 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1850 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1852 this->current_annotation
= NULL
;
1856 fs_visitor::emit_fb_writes()
1858 this->current_annotation
= "FB write header";
1859 GLboolean header_present
= GL_TRUE
;
1862 if (intel
->gen
>= 6 &&
1863 !this->kill_emitted
&&
1864 c
->key
.nr_color_regions
== 1) {
1865 header_present
= false;
1868 if (header_present
) {
1873 if (c
->key
.aa_dest_stencil_reg
) {
1874 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1875 fs_reg(brw_vec8_grf(c
->key
.aa_dest_stencil_reg
, 0))));
1878 /* Reserve space for color. It'll be filled in per MRT below. */
1882 if (c
->key
.source_depth_to_render_target
) {
1883 if (c
->key
.computes_depth
) {
1884 /* Hand over gl_FragDepth. */
1885 assert(this->frag_depth
);
1886 fs_reg depth
= *(variable_storage(this->frag_depth
));
1888 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
1890 /* Pass through the payload depth. */
1891 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1892 fs_reg(brw_vec8_grf(c
->key
.source_depth_reg
, 0))));
1896 if (c
->key
.dest_depth_reg
) {
1897 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1898 fs_reg(brw_vec8_grf(c
->key
.dest_depth_reg
, 0))));
1901 fs_reg color
= reg_undef
;
1902 if (this->frag_color
)
1903 color
= *(variable_storage(this->frag_color
));
1904 else if (this->frag_data
)
1905 color
= *(variable_storage(this->frag_data
));
1907 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1908 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1909 "FB write target %d",
1911 if (this->frag_color
|| this->frag_data
) {
1912 for (int i
= 0; i
< 4; i
++) {
1913 emit(fs_inst(BRW_OPCODE_MOV
,
1914 fs_reg(MRF
, color_mrf
+ i
),
1920 if (this->frag_color
)
1921 color
.reg_offset
-= 4;
1923 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1924 reg_undef
, reg_undef
));
1925 inst
->target
= target
;
1928 if (target
== c
->key
.nr_color_regions
- 1)
1930 inst
->header_present
= header_present
;
1933 if (c
->key
.nr_color_regions
== 0) {
1934 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1935 reg_undef
, reg_undef
));
1939 inst
->header_present
= header_present
;
1942 this->current_annotation
= NULL
;
1946 fs_visitor::generate_fb_write(fs_inst
*inst
)
1948 GLboolean eot
= inst
->eot
;
1949 struct brw_reg implied_header
;
1951 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1954 brw_push_insn_state(p
);
1955 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1956 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1958 if (inst
->header_present
) {
1959 if (intel
->gen
>= 6) {
1961 brw_message_reg(inst
->base_mrf
),
1962 brw_vec8_grf(0, 0));
1963 implied_header
= brw_null_reg();
1965 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1969 brw_message_reg(inst
->base_mrf
+ 1),
1970 brw_vec8_grf(1, 0));
1972 implied_header
= brw_null_reg();
1975 brw_pop_insn_state(p
);
1978 8, /* dispatch_width */
1979 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
1989 fs_visitor::generate_linterp(fs_inst
*inst
,
1990 struct brw_reg dst
, struct brw_reg
*src
)
1992 struct brw_reg delta_x
= src
[0];
1993 struct brw_reg delta_y
= src
[1];
1994 struct brw_reg interp
= src
[2];
1997 delta_y
.nr
== delta_x
.nr
+ 1 &&
1998 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
1999 brw_PLN(p
, dst
, interp
, delta_x
);
2001 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2002 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2007 fs_visitor::generate_math(fs_inst
*inst
,
2008 struct brw_reg dst
, struct brw_reg
*src
)
2012 switch (inst
->opcode
) {
2014 op
= BRW_MATH_FUNCTION_INV
;
2017 op
= BRW_MATH_FUNCTION_RSQ
;
2019 case FS_OPCODE_SQRT
:
2020 op
= BRW_MATH_FUNCTION_SQRT
;
2022 case FS_OPCODE_EXP2
:
2023 op
= BRW_MATH_FUNCTION_EXP
;
2025 case FS_OPCODE_LOG2
:
2026 op
= BRW_MATH_FUNCTION_LOG
;
2029 op
= BRW_MATH_FUNCTION_POW
;
2032 op
= BRW_MATH_FUNCTION_SIN
;
2035 op
= BRW_MATH_FUNCTION_COS
;
2038 assert(!"not reached: unknown math function");
2043 if (intel
->gen
>= 6) {
2044 assert(inst
->mlen
== 0);
2046 if (inst
->opcode
== FS_OPCODE_POW
) {
2047 brw_math2(p
, dst
, op
, src
[0], src
[1]);
2051 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2052 BRW_MATH_SATURATE_NONE
,
2054 BRW_MATH_DATA_VECTOR
,
2055 BRW_MATH_PRECISION_FULL
);
2058 assert(inst
->mlen
>= 1);
2062 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2063 BRW_MATH_SATURATE_NONE
,
2064 inst
->base_mrf
, src
[0],
2065 BRW_MATH_DATA_VECTOR
,
2066 BRW_MATH_PRECISION_FULL
);
2071 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
)
2075 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2077 if (intel
->gen
>= 5) {
2078 switch (inst
->opcode
) {
2080 if (inst
->shadow_compare
) {
2081 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2083 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2087 if (inst
->shadow_compare
) {
2088 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2090 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2095 switch (inst
->opcode
) {
2097 /* Note that G45 and older determines shadow compare and dispatch width
2098 * from message length for most messages.
2100 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2101 if (inst
->shadow_compare
) {
2102 assert(inst
->mlen
== 6);
2104 assert(inst
->mlen
<= 4);
2108 if (inst
->shadow_compare
) {
2109 assert(inst
->mlen
== 6);
2110 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2112 assert(inst
->mlen
== 9);
2113 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2114 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2119 assert(msg_type
!= -1);
2121 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2127 retype(dst
, BRW_REGISTER_TYPE_UW
),
2129 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2130 SURF_INDEX_TEXTURE(inst
->sampler
),
2142 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2145 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2147 * and we're trying to produce:
2150 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2151 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2152 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2153 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2154 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2155 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2156 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2157 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2159 * and add another set of two more subspans if in 16-pixel dispatch mode.
2161 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2162 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2163 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2164 * between each other. We could probably do it like ddx and swizzle the right
2165 * order later, but bail for now and just produce
2166 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2169 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2171 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2172 BRW_REGISTER_TYPE_F
,
2173 BRW_VERTICAL_STRIDE_2
,
2175 BRW_HORIZONTAL_STRIDE_0
,
2176 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2177 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2178 BRW_REGISTER_TYPE_F
,
2179 BRW_VERTICAL_STRIDE_2
,
2181 BRW_HORIZONTAL_STRIDE_0
,
2182 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2183 brw_ADD(p
, dst
, src0
, negate(src1
));
2187 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2189 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2190 BRW_REGISTER_TYPE_F
,
2191 BRW_VERTICAL_STRIDE_4
,
2193 BRW_HORIZONTAL_STRIDE_0
,
2194 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2195 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2196 BRW_REGISTER_TYPE_F
,
2197 BRW_VERTICAL_STRIDE_4
,
2199 BRW_HORIZONTAL_STRIDE_0
,
2200 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2201 brw_ADD(p
, dst
, src0
, negate(src1
));
2205 fs_visitor::generate_discard_not(fs_inst
*inst
, struct brw_reg mask
)
2207 brw_push_insn_state(p
);
2208 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2209 brw_NOT(p
, mask
, brw_mask_reg(1)); /* IMASK */
2210 brw_pop_insn_state(p
);
2214 fs_visitor::generate_discard_and(fs_inst
*inst
, struct brw_reg mask
)
2216 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2217 mask
= brw_uw1_reg(mask
.file
, mask
.nr
, 0);
2219 brw_push_insn_state(p
);
2220 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2221 brw_AND(p
, g0
, mask
, g0
);
2222 brw_pop_insn_state(p
);
2226 fs_visitor::generate_spill(fs_inst
*inst
, struct brw_reg src
)
2228 assert(inst
->mlen
!= 0);
2231 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
2232 retype(src
, BRW_REGISTER_TYPE_UD
));
2233 brw_oword_block_write(p
, brw_message_reg(inst
->base_mrf
), 1, inst
->offset
);
2237 fs_visitor::generate_unspill(fs_inst
*inst
, struct brw_reg dst
)
2239 assert(inst
->mlen
!= 0);
2241 /* Clear any post destination dependencies that would be ignored by
2242 * the block read. See the B-Spec for pre-gen5 send instruction.
2244 * This could use a better solution, since texture sampling and
2245 * math reads could potentially run into it as well -- anywhere
2246 * that we have a SEND with a destination that is a register that
2247 * was written but not read within the last N instructions (what's
2248 * N? unsure). This is rare because of dead code elimination, but
2251 if (intel
->gen
== 4 && !intel
->is_g4x
)
2252 brw_MOV(p
, brw_null_reg(), dst
);
2254 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
), 1,
2257 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2258 /* gen4 errata: destination from a send can't be used as a
2259 * destination until it's been read. Just read it so we don't
2262 brw_MOV(p
, brw_null_reg(), dst
);
2267 fs_visitor::assign_curb_setup()
2269 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
2270 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2272 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2273 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2274 fs_inst
*inst
= (fs_inst
*)iter
.get();
2276 for (unsigned int i
= 0; i
< 3; i
++) {
2277 if (inst
->src
[i
].file
== UNIFORM
) {
2278 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2279 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2283 inst
->src
[i
].file
= FIXED_HW_REG
;
2284 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
2291 fs_visitor::calculate_urb_setup()
2293 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2298 /* Figure out where each of the incoming setup attributes lands. */
2299 if (intel
->gen
>= 6) {
2300 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2301 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2302 urb_setup
[i
] = urb_next
++;
2306 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2307 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2308 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2311 if (i
>= VERT_RESULT_VAR0
)
2312 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2313 else if (i
<= VERT_RESULT_TEX7
)
2319 urb_setup
[fp_index
] = urb_next
++;
2324 /* Each attribute is 4 setup channels, each of which is half a reg. */
2325 c
->prog_data
.urb_read_length
= urb_next
* 2;
2329 fs_visitor::assign_urb_setup()
2331 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2333 /* Offset all the urb_setup[] index by the actual position of the
2334 * setup regs, now that the location of the constants has been chosen.
2336 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2337 fs_inst
*inst
= (fs_inst
*)iter
.get();
2339 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2342 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2344 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2347 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2351 * Split large virtual GRFs into separate components if we can.
2353 * This is mostly duplicated with what brw_fs_vector_splitting does,
2354 * but that's really conservative because it's afraid of doing
2355 * splitting that doesn't result in real progress after the rest of
2356 * the optimization phases, which would cause infinite looping in
2357 * optimization. We can do it once here, safely. This also has the
2358 * opportunity to split interpolated values, or maybe even uniforms,
2359 * which we don't have at the IR level.
2361 * We want to split, because virtual GRFs are what we register
2362 * allocate and spill (due to contiguousness requirements for some
2363 * instructions), and they're what we naturally generate in the
2364 * codegen process, but most virtual GRFs don't actually need to be
2365 * contiguous sets of GRFs. If we split, we'll end up with reduced
2366 * live intervals and better dead code elimination and coalescing.
2369 fs_visitor::split_virtual_grfs()
2371 int num_vars
= this->virtual_grf_next
;
2372 bool split_grf
[num_vars
];
2373 int new_virtual_grf
[num_vars
];
2375 /* Try to split anything > 0 sized. */
2376 for (int i
= 0; i
< num_vars
; i
++) {
2377 if (this->virtual_grf_sizes
[i
] != 1)
2378 split_grf
[i
] = true;
2380 split_grf
[i
] = false;
2384 /* PLN opcodes rely on the delta_xy being contiguous. */
2385 split_grf
[this->delta_x
.reg
] = false;
2388 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2389 fs_inst
*inst
= (fs_inst
*)iter
.get();
2391 /* Texturing produces 4 contiguous registers, so no splitting. */
2392 if ((inst
->opcode
== FS_OPCODE_TEX
||
2393 inst
->opcode
== FS_OPCODE_TXB
||
2394 inst
->opcode
== FS_OPCODE_TXL
) &&
2395 inst
->dst
.file
== GRF
) {
2396 split_grf
[inst
->dst
.reg
] = false;
2400 /* Allocate new space for split regs. Note that the virtual
2401 * numbers will be contiguous.
2403 for (int i
= 0; i
< num_vars
; i
++) {
2405 new_virtual_grf
[i
] = virtual_grf_alloc(1);
2406 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
2407 int reg
= virtual_grf_alloc(1);
2408 assert(reg
== new_virtual_grf
[i
] + j
- 1);
2410 this->virtual_grf_sizes
[i
] = 1;
2414 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2415 fs_inst
*inst
= (fs_inst
*)iter
.get();
2417 if (inst
->dst
.file
== GRF
&&
2418 split_grf
[inst
->dst
.reg
] &&
2419 inst
->dst
.reg_offset
!= 0) {
2420 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
2421 inst
->dst
.reg_offset
- 1);
2422 inst
->dst
.reg_offset
= 0;
2424 for (int i
= 0; i
< 3; i
++) {
2425 if (inst
->src
[i
].file
== GRF
&&
2426 split_grf
[inst
->src
[i
].reg
] &&
2427 inst
->src
[i
].reg_offset
!= 0) {
2428 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
2429 inst
->src
[i
].reg_offset
- 1);
2430 inst
->src
[i
].reg_offset
= 0;
2437 fs_visitor::calculate_live_intervals()
2439 int num_vars
= this->virtual_grf_next
;
2440 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2441 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2445 for (int i
= 0; i
< num_vars
; i
++) {
2451 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2452 fs_inst
*inst
= (fs_inst
*)iter
.get();
2454 if (inst
->opcode
== BRW_OPCODE_DO
) {
2455 if (loop_depth
++ == 0)
2457 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2460 if (loop_depth
== 0) {
2463 * Patches up any vars marked for use within the loop as
2464 * live until the end. This is conservative, as there
2465 * will often be variables defined and used inside the
2466 * loop but dead at the end of the loop body.
2468 for (int i
= 0; i
< num_vars
; i
++) {
2469 if (use
[i
] == loop_start
) {
2480 for (unsigned int i
= 0; i
< 3; i
++) {
2481 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2482 use
[inst
->src
[i
].reg
] = MAX2(use
[inst
->src
[i
].reg
], eip
);
2485 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2486 def
[inst
->dst
.reg
] = MIN2(def
[inst
->dst
.reg
], eip
);
2493 talloc_free(this->virtual_grf_def
);
2494 talloc_free(this->virtual_grf_use
);
2495 this->virtual_grf_def
= def
;
2496 this->virtual_grf_use
= use
;
2500 * Attempts to move immediate constants into the immediate
2501 * constant slot of following instructions.
2503 * Immediate constants are a bit tricky -- they have to be in the last
2504 * operand slot, you can't do abs/negate on them,
2508 fs_visitor::propagate_constants()
2510 bool progress
= false;
2512 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2513 fs_inst
*inst
= (fs_inst
*)iter
.get();
2515 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2517 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2518 inst
->dst
.type
!= inst
->src
[0].type
)
2521 /* Don't bother with cases where we should have had the
2522 * operation on the constant folded in GLSL already.
2527 /* Found a move of a constant to a GRF. Find anything else using the GRF
2528 * before it's written, and replace it with the constant if we can.
2530 exec_list_iterator scan_iter
= iter
;
2532 for (; scan_iter
.has_next(); scan_iter
.next()) {
2533 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2535 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2536 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2537 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2538 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2542 for (int i
= 2; i
>= 0; i
--) {
2543 if (scan_inst
->src
[i
].file
!= GRF
||
2544 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2545 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2548 /* Don't bother with cases where we should have had the
2549 * operation on the constant folded in GLSL already.
2551 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2554 switch (scan_inst
->opcode
) {
2555 case BRW_OPCODE_MOV
:
2556 scan_inst
->src
[i
] = inst
->src
[0];
2560 case BRW_OPCODE_MUL
:
2561 case BRW_OPCODE_ADD
:
2563 scan_inst
->src
[i
] = inst
->src
[0];
2565 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2566 /* Fit this constant in by commuting the operands */
2567 scan_inst
->src
[0] = scan_inst
->src
[1];
2568 scan_inst
->src
[1] = inst
->src
[0];
2571 case BRW_OPCODE_CMP
:
2573 scan_inst
->src
[i
] = inst
->src
[0];
2579 if (scan_inst
->dst
.file
== GRF
&&
2580 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2581 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2582 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2591 * Must be called after calculate_live_intervales() to remove unused
2592 * writes to registers -- register allocation will fail otherwise
2593 * because something deffed but not used won't be considered to
2594 * interfere with other regs.
2597 fs_visitor::dead_code_eliminate()
2599 bool progress
= false;
2600 int num_vars
= this->virtual_grf_next
;
2601 bool dead
[num_vars
];
2603 for (int i
= 0; i
< num_vars
; i
++) {
2604 dead
[i
] = this->virtual_grf_def
[i
] >= this->virtual_grf_use
[i
];
2607 /* Mark off its interval so it won't interfere with anything. */
2608 this->virtual_grf_def
[i
] = -1;
2609 this->virtual_grf_use
[i
] = -1;
2613 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2614 fs_inst
*inst
= (fs_inst
*)iter
.get();
2616 if (inst
->dst
.file
== GRF
&& dead
[inst
->dst
.reg
]) {
2626 fs_visitor::register_coalesce()
2628 bool progress
= false;
2630 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2631 fs_inst
*inst
= (fs_inst
*)iter
.get();
2633 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2636 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
2637 inst
->dst
.type
!= inst
->src
[0].type
)
2640 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
2641 * them: check for no writes to either one until the exit of the
2644 bool interfered
= false;
2645 exec_list_iterator scan_iter
= iter
;
2647 for (; scan_iter
.has_next(); scan_iter
.next()) {
2648 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2650 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2651 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2652 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2658 if (scan_inst
->dst
.file
== GRF
) {
2659 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2660 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2661 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2665 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
2666 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
2667 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2677 /* Update live interval so we don't have to recalculate. */
2678 this->virtual_grf_use
[inst
->src
[0].reg
] = MAX2(virtual_grf_use
[inst
->src
[0].reg
],
2679 virtual_grf_use
[inst
->dst
.reg
]);
2681 /* Rewrite the later usage to point at the source of the move to
2684 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
2686 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2688 for (int i
= 0; i
< 3; i
++) {
2689 if (scan_inst
->src
[i
].file
== GRF
&&
2690 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
2691 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
2692 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
2693 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
2694 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
2695 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
2709 fs_visitor::compute_to_mrf()
2711 bool progress
= false;
2714 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2715 fs_inst
*inst
= (fs_inst
*)iter
.get();
2720 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2722 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2723 inst
->dst
.type
!= inst
->src
[0].type
||
2724 inst
->src
[0].abs
|| inst
->src
[0].negate
)
2727 /* Can't compute-to-MRF this GRF if someone else was going to
2730 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
2733 /* Found a move of a GRF to a MRF. Let's see if we can go
2734 * rewrite the thing that made this GRF to write into the MRF.
2738 for (scan_inst
= (fs_inst
*)inst
->prev
;
2739 scan_inst
->prev
!= NULL
;
2740 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2741 /* We don't handle flow control here. Most computation of
2742 * values that end up in MRFs are shortly before the MRF
2745 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2746 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2747 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2751 /* You can't read from an MRF, so if someone else reads our
2752 * MRF's source GRF that we wanted to rewrite, that stops us.
2754 bool interfered
= false;
2755 for (int i
= 0; i
< 3; i
++) {
2756 if (scan_inst
->src
[i
].file
== GRF
&&
2757 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2758 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2765 if (scan_inst
->dst
.file
== MRF
&&
2766 scan_inst
->dst
.hw_reg
== inst
->dst
.hw_reg
) {
2767 /* Somebody else wrote our MRF here, so we can't can't
2768 * compute-to-MRF before that.
2773 if (scan_inst
->mlen
> 0) {
2774 /* Found a SEND instruction, which will do some amount of
2775 * implied write that may overwrite our MRF that we were
2776 * hoping to compute-to-MRF somewhere above it. Nothing
2777 * we have implied-writes more than 2 MRFs from base_mrf,
2780 int implied_write_len
= MIN2(scan_inst
->mlen
, 2);
2781 if (inst
->dst
.hw_reg
>= scan_inst
->base_mrf
&&
2782 inst
->dst
.hw_reg
< scan_inst
->base_mrf
+ implied_write_len
) {
2787 if (scan_inst
->dst
.file
== GRF
&&
2788 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2789 /* Found the last thing to write our reg we want to turn
2790 * into a compute-to-MRF.
2793 if (scan_inst
->opcode
== FS_OPCODE_TEX
) {
2794 /* texturing writes several continuous regs, so we can't
2795 * compute-to-mrf that.
2800 /* If it's predicated, it (probably) didn't populate all
2803 if (scan_inst
->predicated
)
2806 /* SEND instructions can't have MRF as a destination. */
2807 if (scan_inst
->mlen
)
2810 if (intel
->gen
>= 6) {
2811 /* gen6 math instructions must have the destination be
2812 * GRF, so no compute-to-MRF for them.
2814 if (scan_inst
->opcode
== FS_OPCODE_RCP
||
2815 scan_inst
->opcode
== FS_OPCODE_RSQ
||
2816 scan_inst
->opcode
== FS_OPCODE_SQRT
||
2817 scan_inst
->opcode
== FS_OPCODE_EXP2
||
2818 scan_inst
->opcode
== FS_OPCODE_LOG2
||
2819 scan_inst
->opcode
== FS_OPCODE_SIN
||
2820 scan_inst
->opcode
== FS_OPCODE_COS
||
2821 scan_inst
->opcode
== FS_OPCODE_POW
) {
2826 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2827 /* Found the creator of our MRF's source value. */
2834 scan_inst
->dst
.file
= MRF
;
2835 scan_inst
->dst
.hw_reg
= inst
->dst
.hw_reg
;
2836 scan_inst
->saturate
|= inst
->saturate
;
2846 fs_visitor::virtual_grf_interferes(int a
, int b
)
2848 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
2849 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
2851 /* For dead code, just check if the def interferes with the other range. */
2852 if (this->virtual_grf_use
[a
] == -1) {
2853 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
2854 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
2856 if (this->virtual_grf_use
[b
] == -1) {
2857 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
2858 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
2864 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
2866 struct brw_reg brw_reg
;
2868 switch (reg
->file
) {
2872 brw_reg
= brw_vec8_reg(reg
->file
,
2874 brw_reg
= retype(brw_reg
, reg
->type
);
2877 switch (reg
->type
) {
2878 case BRW_REGISTER_TYPE_F
:
2879 brw_reg
= brw_imm_f(reg
->imm
.f
);
2881 case BRW_REGISTER_TYPE_D
:
2882 brw_reg
= brw_imm_d(reg
->imm
.i
);
2884 case BRW_REGISTER_TYPE_UD
:
2885 brw_reg
= brw_imm_ud(reg
->imm
.u
);
2888 assert(!"not reached");
2893 brw_reg
= reg
->fixed_hw_reg
;
2896 /* Probably unused. */
2897 brw_reg
= brw_null_reg();
2900 assert(!"not reached");
2901 brw_reg
= brw_null_reg();
2905 brw_reg
= brw_abs(brw_reg
);
2907 brw_reg
= negate(brw_reg
);
2913 fs_visitor::generate_code()
2915 unsigned int annotation_len
= 0;
2916 int last_native_inst
= 0;
2917 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
2918 int if_stack_depth
= 0, loop_stack_depth
= 0;
2919 int if_depth_in_loop
[16];
2921 if_depth_in_loop
[loop_stack_depth
] = 0;
2923 memset(&if_stack
, 0, sizeof(if_stack
));
2924 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2925 fs_inst
*inst
= (fs_inst
*)iter
.get();
2926 struct brw_reg src
[3], dst
;
2928 for (unsigned int i
= 0; i
< 3; i
++) {
2929 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
2931 dst
= brw_reg_from_fs_reg(&inst
->dst
);
2933 brw_set_conditionalmod(p
, inst
->conditional_mod
);
2934 brw_set_predicate_control(p
, inst
->predicated
);
2936 switch (inst
->opcode
) {
2937 case BRW_OPCODE_MOV
:
2938 brw_MOV(p
, dst
, src
[0]);
2940 case BRW_OPCODE_ADD
:
2941 brw_ADD(p
, dst
, src
[0], src
[1]);
2943 case BRW_OPCODE_MUL
:
2944 brw_MUL(p
, dst
, src
[0], src
[1]);
2947 case BRW_OPCODE_FRC
:
2948 brw_FRC(p
, dst
, src
[0]);
2950 case BRW_OPCODE_RNDD
:
2951 brw_RNDD(p
, dst
, src
[0]);
2953 case BRW_OPCODE_RNDE
:
2954 brw_RNDE(p
, dst
, src
[0]);
2956 case BRW_OPCODE_RNDZ
:
2957 brw_RNDZ(p
, dst
, src
[0]);
2960 case BRW_OPCODE_AND
:
2961 brw_AND(p
, dst
, src
[0], src
[1]);
2964 brw_OR(p
, dst
, src
[0], src
[1]);
2966 case BRW_OPCODE_XOR
:
2967 brw_XOR(p
, dst
, src
[0], src
[1]);
2969 case BRW_OPCODE_NOT
:
2970 brw_NOT(p
, dst
, src
[0]);
2972 case BRW_OPCODE_ASR
:
2973 brw_ASR(p
, dst
, src
[0], src
[1]);
2975 case BRW_OPCODE_SHR
:
2976 brw_SHR(p
, dst
, src
[0], src
[1]);
2978 case BRW_OPCODE_SHL
:
2979 brw_SHL(p
, dst
, src
[0], src
[1]);
2982 case BRW_OPCODE_CMP
:
2983 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
2985 case BRW_OPCODE_SEL
:
2986 brw_SEL(p
, dst
, src
[0], src
[1]);
2990 assert(if_stack_depth
< 16);
2991 if (inst
->src
[0].file
!= BAD_FILE
) {
2992 assert(intel
->gen
>= 6);
2993 if_stack
[if_stack_depth
] = brw_IF_gen6(p
, inst
->conditional_mod
, src
[0], src
[1]);
2995 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
2997 if_depth_in_loop
[loop_stack_depth
]++;
3001 case BRW_OPCODE_ELSE
:
3002 if_stack
[if_stack_depth
- 1] =
3003 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
3005 case BRW_OPCODE_ENDIF
:
3007 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
3008 if_depth_in_loop
[loop_stack_depth
]--;
3012 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
3013 if_depth_in_loop
[loop_stack_depth
] = 0;
3016 case BRW_OPCODE_BREAK
:
3017 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
3018 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3020 case BRW_OPCODE_CONTINUE
:
3021 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
3022 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3025 case BRW_OPCODE_WHILE
: {
3026 struct brw_instruction
*inst0
, *inst1
;
3029 if (intel
->gen
>= 5)
3032 assert(loop_stack_depth
> 0);
3034 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
3035 /* patch all the BREAK/CONT instructions from last BGNLOOP */
3036 while (inst0
> loop_stack
[loop_stack_depth
]) {
3038 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
3039 inst0
->bits3
.if_else
.jump_count
== 0) {
3040 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
3042 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
3043 inst0
->bits3
.if_else
.jump_count
== 0) {
3044 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
3052 case FS_OPCODE_SQRT
:
3053 case FS_OPCODE_EXP2
:
3054 case FS_OPCODE_LOG2
:
3058 generate_math(inst
, dst
, src
);
3060 case FS_OPCODE_LINTERP
:
3061 generate_linterp(inst
, dst
, src
);
3066 generate_tex(inst
, dst
);
3068 case FS_OPCODE_DISCARD_NOT
:
3069 generate_discard_not(inst
, dst
);
3071 case FS_OPCODE_DISCARD_AND
:
3072 generate_discard_and(inst
, src
[0]);
3075 generate_ddx(inst
, dst
, src
[0]);
3078 generate_ddy(inst
, dst
, src
[0]);
3081 case FS_OPCODE_SPILL
:
3082 generate_spill(inst
, src
[0]);
3085 case FS_OPCODE_UNSPILL
:
3086 generate_unspill(inst
, dst
);
3089 case FS_OPCODE_FB_WRITE
:
3090 generate_fb_write(inst
);
3093 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
3094 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
3095 brw_opcodes
[inst
->opcode
].name
);
3097 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
3102 if (annotation_len
< p
->nr_insn
) {
3103 annotation_len
*= 2;
3104 if (annotation_len
< 16)
3105 annotation_len
= 16;
3107 this->annotation_string
= talloc_realloc(this->mem_ctx
,
3111 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
3117 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
3118 this->annotation_string
[i
] = inst
->annotation
;
3119 this->annotation_ir
[i
] = inst
->ir
;
3121 last_native_inst
= p
->nr_insn
;
3126 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
3128 struct brw_compile
*p
= &c
->func
;
3129 struct intel_context
*intel
= &brw
->intel
;
3130 struct gl_context
*ctx
= &intel
->ctx
;
3131 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
3136 struct brw_shader
*shader
=
3137 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3141 /* We always use 8-wide mode, at least for now. For one, flow
3142 * control only works in 8-wide. Also, when we're fragment shader
3143 * bound, we're almost always under register pressure as well, so
3144 * 8-wide would save us from the performance cliff of spilling
3147 c
->dispatch_width
= 8;
3149 if (INTEL_DEBUG
& DEBUG_WM
) {
3150 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3151 _mesa_print_ir(shader
->ir
, NULL
);
3155 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3157 fs_visitor
v(c
, shader
);
3162 v
.calculate_urb_setup();
3164 v
.emit_interpolation_setup_gen4();
3166 v
.emit_interpolation_setup_gen6();
3168 /* Generate FS IR for main(). (the visitor only descends into
3169 * functions called "main").
3171 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3172 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3179 v
.split_virtual_grfs();
3181 v
.assign_curb_setup();
3182 v
.assign_urb_setup();
3187 v
.calculate_live_intervals();
3188 progress
= v
.propagate_constants() || progress
;
3189 progress
= v
.register_coalesce() || progress
;
3190 progress
= v
.compute_to_mrf() || progress
;
3191 progress
= v
.dead_code_eliminate() || progress
;
3195 /* Debug of register spilling: Go spill everything. */
3196 int virtual_grf_count
= v
.virtual_grf_next
;
3197 for (int i
= 1; i
< virtual_grf_count
; i
++) {
3200 v
.calculate_live_intervals();
3204 v
.assign_regs_trivial();
3206 while (!v
.assign_regs()) {
3210 v
.calculate_live_intervals();
3218 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3223 if (INTEL_DEBUG
& DEBUG_WM
) {
3224 const char *last_annotation_string
= NULL
;
3225 ir_instruction
*last_annotation_ir
= NULL
;
3227 printf("Native code for fragment shader %d:\n", prog
->Name
);
3228 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3229 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
3230 last_annotation_ir
= v
.annotation_ir
[i
];
3231 if (last_annotation_ir
) {
3233 last_annotation_ir
->print();
3237 if (last_annotation_string
!= v
.annotation_string
[i
]) {
3238 last_annotation_string
= v
.annotation_string
[i
];
3239 if (last_annotation_string
)
3240 printf(" %s\n", last_annotation_string
);
3243 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3244 ((uint32_t *)&p
->store
[i
])[3],
3245 ((uint32_t *)&p
->store
[i
])[2],
3246 ((uint32_t *)&p
->store
[i
])[1],
3247 ((uint32_t *)&p
->store
[i
])[0]);
3249 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3254 c
->prog_data
.total_grf
= v
.grf_used
;