2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "../glsl/glsl_types.h"
48 #include "../glsl/ir_optimization.h"
49 #include "../glsl/ir_print_visitor.h"
51 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
54 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
56 struct brw_shader
*shader
;
58 shader
= talloc_zero(NULL
, struct brw_shader
);
60 shader
->base
.Type
= type
;
61 shader
->base
.Name
= name
;
62 _mesa_init_shader(ctx
, &shader
->base
);
68 struct gl_shader_program
*
69 brw_new_shader_program(struct gl_context
*ctx
, GLuint name
)
71 struct brw_shader_program
*prog
;
72 prog
= talloc_zero(NULL
, struct brw_shader_program
);
74 prog
->base
.Name
= name
;
75 _mesa_init_shader_program(ctx
, &prog
->base
);
81 brw_compile_shader(struct gl_context
*ctx
, struct gl_shader
*shader
)
83 if (!_mesa_ir_compile_shader(ctx
, shader
))
90 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
92 struct brw_context
*brw
= brw_context(ctx
);
93 struct intel_context
*intel
= &brw
->intel
;
95 struct brw_shader
*shader
=
96 (struct brw_shader
*)prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
98 void *mem_ctx
= talloc_new(NULL
);
102 talloc_free(shader
->ir
);
103 shader
->ir
= new(shader
) exec_list
;
104 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
106 do_mat_op_to_vec(shader
->ir
);
107 lower_instructions(shader
->ir
,
114 /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
115 * if-statements need to be flattened.
118 lower_if_to_cond_assign(shader
->ir
, 16);
120 do_lower_texture_projection(shader
->ir
);
121 do_vec_index_to_cond_assign(shader
->ir
);
122 brw_do_cubemap_normalize(shader
->ir
);
127 brw_do_channel_expressions(shader
->ir
);
128 brw_do_vector_splitting(shader
->ir
);
130 progress
= do_lower_jumps(shader
->ir
, true, true,
131 true, /* main return */
132 false, /* continue */
136 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
138 progress
= lower_noise(shader
->ir
) || progress
;
140 lower_variable_index_to_cond_assign(shader
->ir
,
142 GL_TRUE
, /* output */
144 GL_TRUE
/* uniform */
146 progress
= lower_quadop_vector(shader
->ir
, false) || progress
;
149 validate_ir_tree(shader
->ir
);
151 reparent_ir(shader
->ir
, shader
->ir
);
152 talloc_free(mem_ctx
);
155 if (!_mesa_ir_link_shader(ctx
, prog
))
162 type_size(const struct glsl_type
*type
)
164 unsigned int size
, i
;
166 switch (type
->base_type
) {
169 case GLSL_TYPE_FLOAT
:
171 return type
->components();
172 case GLSL_TYPE_ARRAY
:
173 return type_size(type
->fields
.array
) * type
->length
;
174 case GLSL_TYPE_STRUCT
:
176 for (i
= 0; i
< type
->length
; i
++) {
177 size
+= type_size(type
->fields
.structure
[i
].type
);
180 case GLSL_TYPE_SAMPLER
:
181 /* Samplers take up no register space, since they're baked in at
186 assert(!"not reached");
192 * Returns how many MRFs an FS opcode will write over.
194 * Note that this is not the 0 or 1 implied writes in an actual gen
195 * instruction -- the FS opcodes often generate MOVs in addition.
198 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
203 switch (inst
->opcode
) {
218 case FS_OPCODE_FB_WRITE
:
220 case FS_OPCODE_PULL_CONSTANT_LOAD
:
221 case FS_OPCODE_UNSPILL
:
223 case FS_OPCODE_SPILL
:
226 assert(!"not reached");
232 fs_visitor::virtual_grf_alloc(int size
)
234 if (virtual_grf_array_size
<= virtual_grf_next
) {
235 if (virtual_grf_array_size
== 0)
236 virtual_grf_array_size
= 16;
238 virtual_grf_array_size
*= 2;
239 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
240 int, virtual_grf_array_size
);
242 /* This slot is always unused. */
243 virtual_grf_sizes
[0] = 0;
245 virtual_grf_sizes
[virtual_grf_next
] = size
;
246 return virtual_grf_next
++;
249 /** Fixed HW reg constructor. */
250 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
254 this->hw_reg
= hw_reg
;
255 this->type
= BRW_REGISTER_TYPE_F
;
258 /** Fixed HW reg constructor. */
259 fs_reg::fs_reg(enum register_file file
, int hw_reg
, uint32_t type
)
263 this->hw_reg
= hw_reg
;
268 brw_type_for_base_type(const struct glsl_type
*type
)
270 switch (type
->base_type
) {
271 case GLSL_TYPE_FLOAT
:
272 return BRW_REGISTER_TYPE_F
;
275 return BRW_REGISTER_TYPE_D
;
277 return BRW_REGISTER_TYPE_UD
;
278 case GLSL_TYPE_ARRAY
:
279 case GLSL_TYPE_STRUCT
:
280 case GLSL_TYPE_SAMPLER
:
281 /* These should be overridden with the type of the member when
282 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
283 * way to trip up if we don't.
285 return BRW_REGISTER_TYPE_UD
;
287 assert(!"not reached");
288 return BRW_REGISTER_TYPE_F
;
292 /** Automatic reg constructor. */
293 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
298 this->reg
= v
->virtual_grf_alloc(type_size(type
));
299 this->reg_offset
= 0;
300 this->type
= brw_type_for_base_type(type
);
304 fs_visitor::variable_storage(ir_variable
*var
)
306 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
309 /* Our support for uniforms is piggy-backed on the struct
310 * gl_fragment_program, because that's where the values actually
311 * get stored, rather than in some global gl_shader_program uniform
315 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
317 unsigned int offset
= 0;
320 if (type
->is_matrix()) {
321 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
322 type
->vector_elements
,
325 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
326 offset
+= setup_uniform_values(loc
+ offset
, column
);
332 switch (type
->base_type
) {
333 case GLSL_TYPE_FLOAT
:
337 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
338 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
339 unsigned int param
= c
->prog_data
.nr_params
++;
341 assert(param
< ARRAY_SIZE(c
->prog_data
.param
));
343 switch (type
->base_type
) {
344 case GLSL_TYPE_FLOAT
:
345 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
348 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2U
;
351 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2I
;
354 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2B
;
357 assert(!"not reached");
358 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
362 c
->prog_data
.param
[param
] = &vec_values
[i
];
366 case GLSL_TYPE_STRUCT
:
367 for (unsigned int i
= 0; i
< type
->length
; i
++) {
368 offset
+= setup_uniform_values(loc
+ offset
,
369 type
->fields
.structure
[i
].type
);
373 case GLSL_TYPE_ARRAY
:
374 for (unsigned int i
= 0; i
< type
->length
; i
++) {
375 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
379 case GLSL_TYPE_SAMPLER
:
380 /* The sampler takes up a slot, but we don't use any values from it. */
384 assert(!"not reached");
390 /* Our support for builtin uniforms is even scarier than non-builtin.
391 * It sits on top of the PROG_STATE_VAR parameters that are
392 * automatically updated from GL context state.
395 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
397 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
399 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
400 statevar
= &_mesa_builtin_uniform_desc
[i
];
401 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
405 if (!statevar
->name
) {
407 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
412 if (ir
->type
->is_array()) {
413 array_count
= ir
->type
->length
;
418 for (int a
= 0; a
< array_count
; a
++) {
419 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
420 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
421 int tokens
[STATE_LENGTH
];
423 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
424 if (ir
->type
->is_array()) {
428 /* This state reference has already been setup by ir_to_mesa,
429 * but we'll get the same index back here.
431 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
432 (gl_state_index
*)tokens
);
433 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
435 /* Add each of the unique swizzles of the element as a
436 * parameter. This'll end up matching the expected layout of
437 * the array/matrix/structure we're trying to fill in.
440 for (unsigned int i
= 0; i
< 4; i
++) {
441 int swiz
= GET_SWZ(element
->swizzle
, i
);
442 if (swiz
== last_swiz
)
446 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
448 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
455 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
457 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
459 fs_reg neg_y
= this->pixel_y
;
461 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
464 if (ir
->pixel_center_integer
) {
465 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
467 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
472 if (!flip
&& ir
->pixel_center_integer
) {
473 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
475 fs_reg pixel_y
= this->pixel_y
;
476 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
479 pixel_y
.negate
= true;
480 offset
+= c
->key
.drawable_height
- 1.0;
483 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
488 if (intel
->gen
>= 6) {
489 emit(fs_inst(BRW_OPCODE_MOV
, wpos
,
490 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
492 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
493 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
497 /* gl_FragCoord.w: Already set up in emit_interpolation */
498 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
504 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
506 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
507 /* Interpolation is always in floating point regs. */
508 reg
->type
= BRW_REGISTER_TYPE_F
;
511 unsigned int array_elements
;
512 const glsl_type
*type
;
514 if (ir
->type
->is_array()) {
515 array_elements
= ir
->type
->length
;
516 if (array_elements
== 0) {
519 type
= ir
->type
->fields
.array
;
525 int location
= ir
->location
;
526 for (unsigned int i
= 0; i
< array_elements
; i
++) {
527 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
528 if (urb_setup
[location
] == -1) {
529 /* If there's no incoming setup data for this slot, don't
530 * emit interpolation for it.
532 attr
.reg_offset
+= type
->vector_elements
;
537 if (c
->key
.flat_shade
&& (location
== FRAG_ATTRIB_COL0
||
538 location
== FRAG_ATTRIB_COL1
)) {
539 /* Constant interpolation (flat shading) case. The SF has
540 * handed us defined values in only the constant offset
541 * field of the setup reg.
543 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
544 struct brw_reg interp
= interp_reg(location
, c
);
545 interp
= suboffset(interp
, 3);
546 emit(fs_inst(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
)));
550 /* Perspective interpolation case. */
551 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
552 struct brw_reg interp
= interp_reg(location
, c
);
553 emit(fs_inst(FS_OPCODE_LINTERP
,
561 if (intel
->gen
< 6) {
562 attr
.reg_offset
-= type
->vector_elements
;
563 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
564 emit(fs_inst(BRW_OPCODE_MUL
,
580 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
582 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
584 /* The frontfacing comes in as a bit in the thread payload. */
585 if (intel
->gen
>= 6) {
586 emit(fs_inst(BRW_OPCODE_ASR
,
588 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
590 emit(fs_inst(BRW_OPCODE_NOT
,
593 emit(fs_inst(BRW_OPCODE_AND
,
598 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
599 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
602 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
606 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
607 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
614 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src
)
626 assert(!"not reached: bad math opcode");
630 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
631 * might be able to do better by doing execsize = 1 math and then
632 * expanding that result out, but we would need to be careful with
635 * The hardware ignores source modifiers (negate and abs) on math
636 * instructions, so we also move to a temp to set those up.
638 if (intel
->gen
>= 6 && (src
.file
== UNIFORM
||
641 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
642 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src
));
646 fs_inst
*inst
= emit(fs_inst(opcode
, dst
, src
));
648 if (intel
->gen
< 6) {
657 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
662 assert(opcode
== FS_OPCODE_POW
);
664 if (intel
->gen
>= 6) {
665 /* Can't do hstride == 0 args to gen6 math, so expand it out. */
666 if (src0
.file
== UNIFORM
) {
667 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
668 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src0
));
672 if (src1
.file
== UNIFORM
) {
673 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
674 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src1
));
678 inst
= emit(fs_inst(opcode
, dst
, src0
, src1
));
680 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1), src1
));
681 inst
= emit(fs_inst(opcode
, dst
, src0
, reg_null_f
));
683 inst
->base_mrf
= base_mrf
;
690 fs_visitor::visit(ir_variable
*ir
)
694 if (variable_storage(ir
))
697 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
698 this->frag_color
= ir
;
699 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
700 this->frag_data
= ir
;
701 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
702 this->frag_depth
= ir
;
705 if (ir
->mode
== ir_var_in
) {
706 if (!strcmp(ir
->name
, "gl_FragCoord")) {
707 reg
= emit_fragcoord_interpolation(ir
);
708 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
709 reg
= emit_frontfacing_interpolation(ir
);
711 reg
= emit_general_interpolation(ir
);
714 hash_table_insert(this->variable_ht
, reg
, ir
);
718 if (ir
->mode
== ir_var_uniform
) {
719 int param_index
= c
->prog_data
.nr_params
;
721 if (!strncmp(ir
->name
, "gl_", 3)) {
722 setup_builtin_uniform_values(ir
);
724 setup_uniform_values(ir
->location
, ir
->type
);
727 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
728 reg
->type
= brw_type_for_base_type(ir
->type
);
732 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
734 hash_table_insert(this->variable_ht
, reg
, ir
);
738 fs_visitor::visit(ir_dereference_variable
*ir
)
740 fs_reg
*reg
= variable_storage(ir
->var
);
745 fs_visitor::visit(ir_dereference_record
*ir
)
747 const glsl_type
*struct_type
= ir
->record
->type
;
749 ir
->record
->accept(this);
751 unsigned int offset
= 0;
752 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
753 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
755 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
757 this->result
.reg_offset
+= offset
;
758 this->result
.type
= brw_type_for_base_type(ir
->type
);
762 fs_visitor::visit(ir_dereference_array
*ir
)
767 ir
->array
->accept(this);
768 index
= ir
->array_index
->as_constant();
770 element_size
= type_size(ir
->type
);
771 this->result
.type
= brw_type_for_base_type(ir
->type
);
774 assert(this->result
.file
== UNIFORM
||
775 (this->result
.file
== GRF
&&
776 this->result
.reg
!= 0));
777 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
779 assert(!"FINISHME: non-constant array element");
783 /* Instruction selection: Produce a MOV.sat instead of
784 * MIN(MAX(val, 0), 1) when possible.
787 fs_visitor::try_emit_saturate(ir_expression
*ir
)
789 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
794 sat_val
->accept(this);
795 fs_reg src
= this->result
;
797 this->result
= fs_reg(this, ir
->type
);
798 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, src
));
799 inst
->saturate
= true;
805 brw_conditional_for_comparison(unsigned int op
)
809 return BRW_CONDITIONAL_L
;
810 case ir_binop_greater
:
811 return BRW_CONDITIONAL_G
;
812 case ir_binop_lequal
:
813 return BRW_CONDITIONAL_LE
;
814 case ir_binop_gequal
:
815 return BRW_CONDITIONAL_GE
;
817 case ir_binop_all_equal
: /* same as equal for scalars */
818 return BRW_CONDITIONAL_Z
;
819 case ir_binop_nequal
:
820 case ir_binop_any_nequal
: /* same as nequal for scalars */
821 return BRW_CONDITIONAL_NZ
;
823 assert(!"not reached: bad operation for comparison");
824 return BRW_CONDITIONAL_NZ
;
829 fs_visitor::visit(ir_expression
*ir
)
831 unsigned int operand
;
835 assert(ir
->get_num_operands() <= 2);
837 if (try_emit_saturate(ir
))
840 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
841 ir
->operands
[operand
]->accept(this);
842 if (this->result
.file
== BAD_FILE
) {
844 printf("Failed to get tree for expression operand:\n");
845 ir
->operands
[operand
]->accept(&v
);
848 op
[operand
] = this->result
;
850 /* Matrix expression operands should have been broken down to vector
851 * operations already.
853 assert(!ir
->operands
[operand
]->type
->is_matrix());
854 /* And then those vector operands should have been broken down to scalar.
856 assert(!ir
->operands
[operand
]->type
->is_vector());
859 /* Storage for our result. If our result goes into an assignment, it will
860 * just get copy-propagated out, so no worries.
862 this->result
= fs_reg(this, ir
->type
);
864 switch (ir
->operation
) {
865 case ir_unop_logic_not
:
866 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
867 * ones complement of the whole register, not just bit 0.
869 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1)));
872 op
[0].negate
= !op
[0].negate
;
873 this->result
= op
[0];
877 op
[0].negate
= false;
878 this->result
= op
[0];
881 temp
= fs_reg(this, ir
->type
);
883 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
885 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
886 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
887 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
888 inst
->predicated
= true;
890 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
891 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
892 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
893 inst
->predicated
= true;
897 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
901 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
904 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
908 assert(!"not reached: should be handled by ir_explog_to_explog2");
911 case ir_unop_sin_reduced
:
912 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
915 case ir_unop_cos_reduced
:
916 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
920 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
923 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
927 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
930 assert(!"not reached: should be handled by ir_sub_to_add_neg");
934 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
937 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
940 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
944 case ir_binop_greater
:
945 case ir_binop_lequal
:
946 case ir_binop_gequal
:
948 case ir_binop_all_equal
:
949 case ir_binop_nequal
:
950 case ir_binop_any_nequal
:
952 /* original gen4 does implicit conversion before comparison. */
954 temp
.type
= op
[0].type
;
956 inst
= emit(fs_inst(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]));
957 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
958 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
961 case ir_binop_logic_xor
:
962 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
965 case ir_binop_logic_or
:
966 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
969 case ir_binop_logic_and
:
970 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
975 assert(!"not reached: should be handled by brw_fs_channel_expressions");
979 assert(!"not reached: should be handled by lower_noise");
982 case ir_quadop_vector
:
983 assert(!"not reached: should be handled by lower_quadop_vector");
987 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
991 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
998 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1002 temp
= this->result
;
1003 /* original gen4 does implicit conversion before comparison. */
1005 temp
.type
= op
[0].type
;
1007 inst
= emit(fs_inst(BRW_OPCODE_CMP
, temp
, op
[0], fs_reg(0.0f
)));
1008 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1009 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
,
1010 this->result
, fs_reg(1)));
1014 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
1017 op
[0].negate
= !op
[0].negate
;
1018 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1019 this->result
.negate
= true;
1022 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1025 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
1027 case ir_unop_round_even
:
1028 emit(fs_inst(BRW_OPCODE_RNDE
, this->result
, op
[0]));
1032 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1033 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1035 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1036 inst
->predicated
= true;
1039 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1040 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1042 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1043 inst
->predicated
= true;
1047 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
1050 case ir_unop_bit_not
:
1051 inst
= emit(fs_inst(BRW_OPCODE_NOT
, this->result
, op
[0]));
1053 case ir_binop_bit_and
:
1054 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
1056 case ir_binop_bit_xor
:
1057 inst
= emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
1059 case ir_binop_bit_or
:
1060 inst
= emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
1064 case ir_binop_lshift
:
1065 case ir_binop_rshift
:
1066 assert(!"GLSL 1.30 features unsupported");
1072 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1073 const glsl_type
*type
, bool predicated
)
1075 switch (type
->base_type
) {
1076 case GLSL_TYPE_FLOAT
:
1077 case GLSL_TYPE_UINT
:
1079 case GLSL_TYPE_BOOL
:
1080 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1081 l
.type
= brw_type_for_base_type(type
);
1082 r
.type
= brw_type_for_base_type(type
);
1084 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1085 inst
->predicated
= predicated
;
1091 case GLSL_TYPE_ARRAY
:
1092 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1093 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1097 case GLSL_TYPE_STRUCT
:
1098 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1099 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1104 case GLSL_TYPE_SAMPLER
:
1108 assert(!"not reached");
1114 fs_visitor::visit(ir_assignment
*ir
)
1119 /* FINISHME: arrays on the lhs */
1120 ir
->lhs
->accept(this);
1123 ir
->rhs
->accept(this);
1126 assert(l
.file
!= BAD_FILE
);
1127 assert(r
.file
!= BAD_FILE
);
1129 if (ir
->condition
) {
1130 emit_bool_to_cond_code(ir
->condition
);
1133 if (ir
->lhs
->type
->is_scalar() ||
1134 ir
->lhs
->type
->is_vector()) {
1135 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1136 if (ir
->write_mask
& (1 << i
)) {
1137 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1139 inst
->predicated
= true;
1145 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1150 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1154 bool simd16
= false;
1160 if (ir
->shadow_comparitor
) {
1161 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1162 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1164 coordinate
.reg_offset
++;
1166 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1169 if (ir
->op
== ir_tex
) {
1170 /* There's no plain shadow compare message, so we use shadow
1171 * compare with a bias of 0.0.
1173 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1176 } else if (ir
->op
== ir_txb
) {
1177 ir
->lod_info
.bias
->accept(this);
1178 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1182 assert(ir
->op
== ir_txl
);
1183 ir
->lod_info
.lod
->accept(this);
1184 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1189 ir
->shadow_comparitor
->accept(this);
1190 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1192 } else if (ir
->op
== ir_tex
) {
1193 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1194 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1196 coordinate
.reg_offset
++;
1198 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1201 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1202 * instructions. We'll need to do SIMD16 here.
1204 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1206 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1207 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2),
1209 coordinate
.reg_offset
++;
1212 /* lod/bias appears after u/v/r. */
1215 if (ir
->op
== ir_txb
) {
1216 ir
->lod_info
.bias
->accept(this);
1217 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1221 ir
->lod_info
.lod
->accept(this);
1222 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1227 /* The unused upper half. */
1230 /* Now, since we're doing simd16, the return is 2 interleaved
1231 * vec4s where the odd-indexed ones are junk. We'll need to move
1232 * this weirdness around to the expected layout.
1236 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1238 dst
.type
= BRW_REGISTER_TYPE_F
;
1241 fs_inst
*inst
= NULL
;
1244 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1247 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1250 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1254 assert(!"GLSL 1.30 features unsupported");
1257 inst
->base_mrf
= base_mrf
;
1261 for (int i
= 0; i
< 4; i
++) {
1262 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1263 orig_dst
.reg_offset
++;
1264 dst
.reg_offset
+= 2;
1272 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1274 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1275 * optional parameters like shadow comparitor or LOD bias. If
1276 * optional parameters aren't present, those base slots are
1277 * optional and don't need to be included in the message.
1279 * We don't fill in the unnecessary slots regardless, which may
1280 * look surprising in the disassembly.
1282 int mlen
= 1; /* g0 header always present. */
1285 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1286 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1288 coordinate
.reg_offset
++;
1290 mlen
+= ir
->coordinate
->type
->vector_elements
;
1292 if (ir
->shadow_comparitor
) {
1293 mlen
= MAX2(mlen
, 5);
1295 ir
->shadow_comparitor
->accept(this);
1296 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1300 fs_inst
*inst
= NULL
;
1303 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1306 ir
->lod_info
.bias
->accept(this);
1307 mlen
= MAX2(mlen
, 5);
1308 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1311 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1314 ir
->lod_info
.lod
->accept(this);
1315 mlen
= MAX2(mlen
, 5);
1316 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1319 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1323 assert(!"GLSL 1.30 features unsupported");
1326 inst
->base_mrf
= base_mrf
;
1333 fs_visitor::visit(ir_texture
*ir
)
1336 fs_inst
*inst
= NULL
;
1338 ir
->coordinate
->accept(this);
1339 fs_reg coordinate
= this->result
;
1341 /* Should be lowered by do_lower_texture_projection */
1342 assert(!ir
->projector
);
1344 sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
1345 ctx
->Shader
.CurrentFragmentProgram
,
1346 &brw
->fragment_program
->Base
);
1347 sampler
= c
->fp
->program
.Base
.SamplerUnits
[sampler
];
1349 /* The 965 requires the EU to do the normalization of GL rectangle
1350 * texture coordinates. We use the program parameter state
1351 * tracking to get the scaling factor.
1353 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1354 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1355 int tokens
[STATE_LENGTH
] = {
1357 STATE_TEXRECT_SCALE
,
1363 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
1365 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
+ 1] =
1368 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1369 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1370 GLuint index
= _mesa_add_state_reference(params
,
1371 (gl_state_index
*)tokens
);
1372 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
1374 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[0];
1375 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[1];
1377 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1378 fs_reg src
= coordinate
;
1381 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_x
));
1384 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_y
));
1387 /* Writemasking doesn't eliminate channels on SIMD8 texture
1388 * samples, so don't worry about them.
1390 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1392 if (intel
->gen
< 5) {
1393 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1395 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1398 inst
->sampler
= sampler
;
1402 if (ir
->shadow_comparitor
)
1403 inst
->shadow_compare
= true;
1405 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1406 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1408 for (int i
= 0; i
< 4; i
++) {
1409 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1410 fs_reg l
= swizzle_dst
;
1413 if (swiz
== SWIZZLE_ZERO
) {
1414 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1415 } else if (swiz
== SWIZZLE_ONE
) {
1416 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1419 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1420 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1423 this->result
= swizzle_dst
;
1428 fs_visitor::visit(ir_swizzle
*ir
)
1430 ir
->val
->accept(this);
1431 fs_reg val
= this->result
;
1433 if (ir
->type
->vector_elements
== 1) {
1434 this->result
.reg_offset
+= ir
->mask
.x
;
1438 fs_reg result
= fs_reg(this, ir
->type
);
1439 this->result
= result
;
1441 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1442 fs_reg channel
= val
;
1460 channel
.reg_offset
+= swiz
;
1461 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1462 result
.reg_offset
++;
1467 fs_visitor::visit(ir_discard
*ir
)
1469 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1471 assert(ir
->condition
== NULL
); /* FINISHME */
1473 emit(fs_inst(FS_OPCODE_DISCARD_NOT
, temp
, reg_null_d
));
1474 emit(fs_inst(FS_OPCODE_DISCARD_AND
, reg_null_d
, temp
));
1475 kill_emitted
= true;
1479 fs_visitor::visit(ir_constant
*ir
)
1481 /* Set this->result to reg at the bottom of the function because some code
1482 * paths will cause this visitor to be applied to other fields. This will
1483 * cause the value stored in this->result to be modified.
1485 * Make reg constant so that it doesn't get accidentally modified along the
1486 * way. Yes, I actually had this problem. :(
1488 const fs_reg
reg(this, ir
->type
);
1489 fs_reg dst_reg
= reg
;
1491 if (ir
->type
->is_array()) {
1492 const unsigned size
= type_size(ir
->type
->fields
.array
);
1494 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1495 ir
->array_elements
[i
]->accept(this);
1496 fs_reg src_reg
= this->result
;
1498 dst_reg
.type
= src_reg
.type
;
1499 for (unsigned j
= 0; j
< size
; j
++) {
1500 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, src_reg
));
1501 src_reg
.reg_offset
++;
1502 dst_reg
.reg_offset
++;
1505 } else if (ir
->type
->is_record()) {
1506 foreach_list(node
, &ir
->components
) {
1507 ir_instruction
*const field
= (ir_instruction
*) node
;
1508 const unsigned size
= type_size(field
->type
);
1510 field
->accept(this);
1511 fs_reg src_reg
= this->result
;
1513 dst_reg
.type
= src_reg
.type
;
1514 for (unsigned j
= 0; j
< size
; j
++) {
1515 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, src_reg
));
1516 src_reg
.reg_offset
++;
1517 dst_reg
.reg_offset
++;
1521 const unsigned size
= type_size(ir
->type
);
1523 for (unsigned i
= 0; i
< size
; i
++) {
1524 switch (ir
->type
->base_type
) {
1525 case GLSL_TYPE_FLOAT
:
1526 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.f
[i
])));
1528 case GLSL_TYPE_UINT
:
1529 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.u
[i
])));
1532 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.i
[i
])));
1534 case GLSL_TYPE_BOOL
:
1535 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg((int)ir
->value
.b
[i
])));
1538 assert(!"Non-float/uint/int/bool constant");
1540 dst_reg
.reg_offset
++;
1548 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1550 ir_expression
*expr
= ir
->as_expression();
1556 assert(expr
->get_num_operands() <= 2);
1557 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1558 assert(expr
->operands
[i
]->type
->is_scalar());
1560 expr
->operands
[i
]->accept(this);
1561 op
[i
] = this->result
;
1564 switch (expr
->operation
) {
1565 case ir_unop_logic_not
:
1566 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1)));
1567 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1570 case ir_binop_logic_xor
:
1571 inst
= emit(fs_inst(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]));
1572 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1575 case ir_binop_logic_or
:
1576 inst
= emit(fs_inst(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]));
1577 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1580 case ir_binop_logic_and
:
1581 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]));
1582 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1586 if (intel
->gen
>= 6) {
1587 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1588 op
[0], fs_reg(0.0f
)));
1590 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_f
, op
[0]));
1592 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1596 if (intel
->gen
>= 6) {
1597 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0)));
1599 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1601 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1604 case ir_binop_greater
:
1605 case ir_binop_gequal
:
1607 case ir_binop_lequal
:
1608 case ir_binop_equal
:
1609 case ir_binop_all_equal
:
1610 case ir_binop_nequal
:
1611 case ir_binop_any_nequal
:
1612 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_cmp
, op
[0], op
[1]));
1613 inst
->conditional_mod
=
1614 brw_conditional_for_comparison(expr
->operation
);
1618 assert(!"not reached");
1627 if (intel
->gen
>= 6) {
1628 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
,
1629 this->result
, fs_reg(1)));
1630 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1632 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, this->result
));
1633 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1638 * Emit a gen6 IF statement with the comparison folded into the IF
1642 fs_visitor::emit_if_gen6(ir_if
*ir
)
1644 ir_expression
*expr
= ir
->condition
->as_expression();
1651 assert(expr
->get_num_operands() <= 2);
1652 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1653 assert(expr
->operands
[i
]->type
->is_scalar());
1655 expr
->operands
[i
]->accept(this);
1656 op
[i
] = this->result
;
1659 switch (expr
->operation
) {
1660 case ir_unop_logic_not
:
1661 inst
= emit(fs_inst(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(0)));
1662 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1665 case ir_binop_logic_xor
:
1666 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1667 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1670 case ir_binop_logic_or
:
1671 temp
= fs_reg(this, glsl_type::bool_type
);
1672 emit(fs_inst(BRW_OPCODE_OR
, temp
, op
[0], op
[1]));
1673 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1674 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1677 case ir_binop_logic_and
:
1678 temp
= fs_reg(this, glsl_type::bool_type
);
1679 emit(fs_inst(BRW_OPCODE_AND
, temp
, op
[0], op
[1]));
1680 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1681 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1685 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0)));
1686 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1690 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1691 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1694 case ir_binop_greater
:
1695 case ir_binop_gequal
:
1697 case ir_binop_lequal
:
1698 case ir_binop_equal
:
1699 case ir_binop_all_equal
:
1700 case ir_binop_nequal
:
1701 case ir_binop_any_nequal
:
1702 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1703 inst
->conditional_mod
=
1704 brw_conditional_for_comparison(expr
->operation
);
1707 assert(!"not reached");
1708 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1709 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1716 ir
->condition
->accept(this);
1718 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0)));
1719 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1723 fs_visitor::visit(ir_if
*ir
)
1727 /* Don't point the annotation at the if statement, because then it plus
1728 * the then and else blocks get printed.
1730 this->base_ir
= ir
->condition
;
1732 if (intel
->gen
>= 6) {
1735 emit_bool_to_cond_code(ir
->condition
);
1737 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1738 inst
->predicated
= true;
1741 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1742 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1748 if (!ir
->else_instructions
.is_empty()) {
1749 emit(fs_inst(BRW_OPCODE_ELSE
));
1751 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1752 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1759 emit(fs_inst(BRW_OPCODE_ENDIF
));
1763 fs_visitor::visit(ir_loop
*ir
)
1765 fs_reg counter
= reg_undef
;
1768 this->base_ir
= ir
->counter
;
1769 ir
->counter
->accept(this);
1770 counter
= *(variable_storage(ir
->counter
));
1773 this->base_ir
= ir
->from
;
1774 ir
->from
->accept(this);
1776 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1780 emit(fs_inst(BRW_OPCODE_DO
));
1783 this->base_ir
= ir
->to
;
1784 ir
->to
->accept(this);
1786 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_cmp
,
1787 counter
, this->result
));
1788 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->cmp
);
1790 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1791 inst
->predicated
= true;
1794 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1795 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1801 if (ir
->increment
) {
1802 this->base_ir
= ir
->increment
;
1803 ir
->increment
->accept(this);
1804 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1807 emit(fs_inst(BRW_OPCODE_WHILE
));
1811 fs_visitor::visit(ir_loop_jump
*ir
)
1814 case ir_loop_jump::jump_break
:
1815 emit(fs_inst(BRW_OPCODE_BREAK
));
1817 case ir_loop_jump::jump_continue
:
1818 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1824 fs_visitor::visit(ir_call
*ir
)
1826 assert(!"FINISHME");
1830 fs_visitor::visit(ir_return
*ir
)
1832 assert(!"FINISHME");
1836 fs_visitor::visit(ir_function
*ir
)
1838 /* Ignore function bodies other than main() -- we shouldn't see calls to
1839 * them since they should all be inlined before we get to ir_to_mesa.
1841 if (strcmp(ir
->name
, "main") == 0) {
1842 const ir_function_signature
*sig
;
1845 sig
= ir
->matching_signature(&empty
);
1849 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1850 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1859 fs_visitor::visit(ir_function_signature
*ir
)
1861 assert(!"not reached");
1866 fs_visitor::emit(fs_inst inst
)
1868 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1871 list_inst
->annotation
= this->current_annotation
;
1872 list_inst
->ir
= this->base_ir
;
1874 this->instructions
.push_tail(list_inst
);
1879 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1881 fs_visitor::emit_dummy_fs()
1883 /* Everyone's favorite color. */
1884 emit(fs_inst(BRW_OPCODE_MOV
,
1887 emit(fs_inst(BRW_OPCODE_MOV
,
1890 emit(fs_inst(BRW_OPCODE_MOV
,
1893 emit(fs_inst(BRW_OPCODE_MOV
,
1898 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1901 write
->base_mrf
= 0;
1904 /* The register location here is relative to the start of the URB
1905 * data. It will get adjusted to be a real location before
1906 * generate_code() time.
1909 fs_visitor::interp_reg(int location
, int channel
)
1911 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1912 int stride
= (channel
& 1) * 4;
1914 assert(urb_setup
[location
] != -1);
1916 return brw_vec1_grf(regnr
, stride
);
1919 /** Emits the interpolation for the varying inputs. */
1921 fs_visitor::emit_interpolation_setup_gen4()
1923 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1925 this->current_annotation
= "compute pixel centers";
1926 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1927 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1928 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1929 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1930 emit(fs_inst(BRW_OPCODE_ADD
,
1932 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1933 fs_reg(brw_imm_v(0x10101010))));
1934 emit(fs_inst(BRW_OPCODE_ADD
,
1936 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1937 fs_reg(brw_imm_v(0x11001100))));
1939 this->current_annotation
= "compute pixel deltas from v0";
1941 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1942 this->delta_y
= this->delta_x
;
1943 this->delta_y
.reg_offset
++;
1945 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1946 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1948 emit(fs_inst(BRW_OPCODE_ADD
,
1951 fs_reg(negate(brw_vec1_grf(1, 0)))));
1952 emit(fs_inst(BRW_OPCODE_ADD
,
1955 fs_reg(negate(brw_vec1_grf(1, 1)))));
1957 this->current_annotation
= "compute pos.w and 1/pos.w";
1958 /* Compute wpos.w. It's always in our setup, since it's needed to
1959 * interpolate the other attributes.
1961 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1962 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1963 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1964 /* Compute the pixel 1/W value from wpos.w. */
1965 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1966 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1967 this->current_annotation
= NULL
;
1970 /** Emits the interpolation for the varying inputs. */
1972 fs_visitor::emit_interpolation_setup_gen6()
1974 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1976 /* If the pixel centers end up used, the setup is the same as for gen4. */
1977 this->current_annotation
= "compute pixel centers";
1978 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1979 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1980 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1981 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1982 emit(fs_inst(BRW_OPCODE_ADD
,
1984 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1985 fs_reg(brw_imm_v(0x10101010))));
1986 emit(fs_inst(BRW_OPCODE_ADD
,
1988 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1989 fs_reg(brw_imm_v(0x11001100))));
1991 /* As of gen6, we can no longer mix float and int sources. We have
1992 * to turn the integer pixel centers into floats for their actual
1995 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1996 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1997 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
));
1998 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
));
2000 this->current_annotation
= "compute 1/pos.w";
2001 this->wpos_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
2002 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
2003 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
2005 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
2006 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
2008 this->current_annotation
= NULL
;
2012 fs_visitor::emit_fb_writes()
2014 this->current_annotation
= "FB write header";
2015 GLboolean header_present
= GL_TRUE
;
2018 if (intel
->gen
>= 6 &&
2019 !this->kill_emitted
&&
2020 c
->key
.nr_color_regions
== 1) {
2021 header_present
= false;
2024 if (header_present
) {
2029 if (c
->aa_dest_stencil_reg
) {
2030 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2031 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0))));
2034 /* Reserve space for color. It'll be filled in per MRT below. */
2038 if (c
->source_depth_to_render_target
) {
2039 if (c
->computes_depth
) {
2040 /* Hand over gl_FragDepth. */
2041 assert(this->frag_depth
);
2042 fs_reg depth
= *(variable_storage(this->frag_depth
));
2044 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
2046 /* Pass through the payload depth. */
2047 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2048 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
2052 if (c
->dest_depth_reg
) {
2053 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2054 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0))));
2057 fs_reg color
= reg_undef
;
2058 if (this->frag_color
)
2059 color
= *(variable_storage(this->frag_color
));
2060 else if (this->frag_data
) {
2061 color
= *(variable_storage(this->frag_data
));
2062 color
.type
= BRW_REGISTER_TYPE_F
;
2065 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2066 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
2067 "FB write target %d",
2069 if (this->frag_color
|| this->frag_data
) {
2070 for (int i
= 0; i
< 4; i
++) {
2071 emit(fs_inst(BRW_OPCODE_MOV
,
2072 fs_reg(MRF
, color_mrf
+ i
),
2078 if (this->frag_color
)
2079 color
.reg_offset
-= 4;
2081 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
2082 reg_undef
, reg_undef
));
2083 inst
->target
= target
;
2086 if (target
== c
->key
.nr_color_regions
- 1)
2088 inst
->header_present
= header_present
;
2091 if (c
->key
.nr_color_regions
== 0) {
2092 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
2093 reg_undef
, reg_undef
));
2097 inst
->header_present
= header_present
;
2100 this->current_annotation
= NULL
;
2104 fs_visitor::generate_fb_write(fs_inst
*inst
)
2106 GLboolean eot
= inst
->eot
;
2107 struct brw_reg implied_header
;
2109 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
2112 brw_push_insn_state(p
);
2113 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2114 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2116 if (inst
->header_present
) {
2117 if (intel
->gen
>= 6) {
2119 brw_message_reg(inst
->base_mrf
),
2120 brw_vec8_grf(0, 0));
2122 if (inst
->target
> 0) {
2123 /* Set the render target index for choosing BLEND_STATE. */
2124 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 2),
2125 BRW_REGISTER_TYPE_UD
),
2126 brw_imm_ud(inst
->target
));
2129 /* Clear viewport index, render target array index. */
2130 brw_AND(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 0),
2131 BRW_REGISTER_TYPE_UD
),
2132 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2133 brw_imm_ud(0xf7ff));
2135 implied_header
= brw_null_reg();
2137 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2141 brw_message_reg(inst
->base_mrf
+ 1),
2142 brw_vec8_grf(1, 0));
2144 implied_header
= brw_null_reg();
2147 brw_pop_insn_state(p
);
2150 8, /* dispatch_width */
2151 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
2158 inst
->header_present
);
2162 fs_visitor::generate_linterp(fs_inst
*inst
,
2163 struct brw_reg dst
, struct brw_reg
*src
)
2165 struct brw_reg delta_x
= src
[0];
2166 struct brw_reg delta_y
= src
[1];
2167 struct brw_reg interp
= src
[2];
2170 delta_y
.nr
== delta_x
.nr
+ 1 &&
2171 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2172 brw_PLN(p
, dst
, interp
, delta_x
);
2174 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2175 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2180 fs_visitor::generate_math(fs_inst
*inst
,
2181 struct brw_reg dst
, struct brw_reg
*src
)
2185 switch (inst
->opcode
) {
2187 op
= BRW_MATH_FUNCTION_INV
;
2190 op
= BRW_MATH_FUNCTION_RSQ
;
2192 case FS_OPCODE_SQRT
:
2193 op
= BRW_MATH_FUNCTION_SQRT
;
2195 case FS_OPCODE_EXP2
:
2196 op
= BRW_MATH_FUNCTION_EXP
;
2198 case FS_OPCODE_LOG2
:
2199 op
= BRW_MATH_FUNCTION_LOG
;
2202 op
= BRW_MATH_FUNCTION_POW
;
2205 op
= BRW_MATH_FUNCTION_SIN
;
2208 op
= BRW_MATH_FUNCTION_COS
;
2211 assert(!"not reached: unknown math function");
2216 if (intel
->gen
>= 6) {
2217 assert(inst
->mlen
== 0);
2219 if (inst
->opcode
== FS_OPCODE_POW
) {
2220 brw_math2(p
, dst
, op
, src
[0], src
[1]);
2224 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2225 BRW_MATH_SATURATE_NONE
,
2227 BRW_MATH_DATA_VECTOR
,
2228 BRW_MATH_PRECISION_FULL
);
2231 assert(inst
->mlen
>= 1);
2235 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2236 BRW_MATH_SATURATE_NONE
,
2237 inst
->base_mrf
, src
[0],
2238 BRW_MATH_DATA_VECTOR
,
2239 BRW_MATH_PRECISION_FULL
);
2244 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
)
2248 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2250 if (intel
->gen
>= 5) {
2251 switch (inst
->opcode
) {
2253 if (inst
->shadow_compare
) {
2254 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2256 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2260 if (inst
->shadow_compare
) {
2261 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2263 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2268 switch (inst
->opcode
) {
2270 /* Note that G45 and older determines shadow compare and dispatch width
2271 * from message length for most messages.
2273 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2274 if (inst
->shadow_compare
) {
2275 assert(inst
->mlen
== 6);
2277 assert(inst
->mlen
<= 4);
2281 if (inst
->shadow_compare
) {
2282 assert(inst
->mlen
== 6);
2283 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2285 assert(inst
->mlen
== 9);
2286 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2287 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2292 assert(msg_type
!= -1);
2294 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2300 retype(dst
, BRW_REGISTER_TYPE_UW
),
2302 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2303 SURF_INDEX_TEXTURE(inst
->sampler
),
2315 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2318 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2320 * and we're trying to produce:
2323 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2324 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2325 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2326 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2327 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2328 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2329 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2330 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2332 * and add another set of two more subspans if in 16-pixel dispatch mode.
2334 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2335 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2336 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2337 * between each other. We could probably do it like ddx and swizzle the right
2338 * order later, but bail for now and just produce
2339 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2342 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2344 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2345 BRW_REGISTER_TYPE_F
,
2346 BRW_VERTICAL_STRIDE_2
,
2348 BRW_HORIZONTAL_STRIDE_0
,
2349 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2350 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2351 BRW_REGISTER_TYPE_F
,
2352 BRW_VERTICAL_STRIDE_2
,
2354 BRW_HORIZONTAL_STRIDE_0
,
2355 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2356 brw_ADD(p
, dst
, src0
, negate(src1
));
2360 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2362 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2363 BRW_REGISTER_TYPE_F
,
2364 BRW_VERTICAL_STRIDE_4
,
2366 BRW_HORIZONTAL_STRIDE_0
,
2367 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2368 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2369 BRW_REGISTER_TYPE_F
,
2370 BRW_VERTICAL_STRIDE_4
,
2372 BRW_HORIZONTAL_STRIDE_0
,
2373 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2374 brw_ADD(p
, dst
, src0
, negate(src1
));
2378 fs_visitor::generate_discard_not(fs_inst
*inst
, struct brw_reg mask
)
2380 if (intel
->gen
>= 6) {
2381 /* Gen6 no longer has the mask reg for us to just read the
2382 * active channels from. However, cmp updates just the channels
2383 * of the flag reg that are enabled, so we can get at the
2384 * channel enables that way. In this step, make a reg of ones
2387 brw_MOV(p
, mask
, brw_imm_ud(1));
2389 brw_push_insn_state(p
);
2390 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2391 brw_NOT(p
, mask
, brw_mask_reg(1)); /* IMASK */
2392 brw_pop_insn_state(p
);
2397 fs_visitor::generate_discard_and(fs_inst
*inst
, struct brw_reg mask
)
2399 if (intel
->gen
>= 6) {
2400 struct brw_reg f0
= brw_flag_reg();
2401 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
2403 brw_push_insn_state(p
);
2404 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2405 brw_MOV(p
, f0
, brw_imm_uw(0xffff)); /* inactive channels undiscarded */
2406 brw_pop_insn_state(p
);
2408 brw_CMP(p
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
2409 BRW_CONDITIONAL_Z
, mask
, brw_imm_ud(0)); /* active channels fail test */
2410 /* Undo CMP's whacking of predication*/
2411 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2413 brw_push_insn_state(p
);
2414 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2415 brw_AND(p
, g1
, f0
, g1
);
2416 brw_pop_insn_state(p
);
2418 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2420 mask
= brw_uw1_reg(mask
.file
, mask
.nr
, 0);
2422 brw_push_insn_state(p
);
2423 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2424 brw_AND(p
, g0
, mask
, g0
);
2425 brw_pop_insn_state(p
);
2430 fs_visitor::generate_spill(fs_inst
*inst
, struct brw_reg src
)
2432 assert(inst
->mlen
!= 0);
2435 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
2436 retype(src
, BRW_REGISTER_TYPE_UD
));
2437 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
), 1,
2442 fs_visitor::generate_unspill(fs_inst
*inst
, struct brw_reg dst
)
2444 assert(inst
->mlen
!= 0);
2446 /* Clear any post destination dependencies that would be ignored by
2447 * the block read. See the B-Spec for pre-gen5 send instruction.
2449 * This could use a better solution, since texture sampling and
2450 * math reads could potentially run into it as well -- anywhere
2451 * that we have a SEND with a destination that is a register that
2452 * was written but not read within the last N instructions (what's
2453 * N? unsure). This is rare because of dead code elimination, but
2456 if (intel
->gen
== 4 && !intel
->is_g4x
)
2457 brw_MOV(p
, brw_null_reg(), dst
);
2459 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
), 1,
2462 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2463 /* gen4 errata: destination from a send can't be used as a
2464 * destination until it's been read. Just read it so we don't
2467 brw_MOV(p
, brw_null_reg(), dst
);
2473 fs_visitor::generate_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
)
2475 assert(inst
->mlen
!= 0);
2477 /* Clear any post destination dependencies that would be ignored by
2478 * the block read. See the B-Spec for pre-gen5 send instruction.
2480 * This could use a better solution, since texture sampling and
2481 * math reads could potentially run into it as well -- anywhere
2482 * that we have a SEND with a destination that is a register that
2483 * was written but not read within the last N instructions (what's
2484 * N? unsure). This is rare because of dead code elimination, but
2487 if (intel
->gen
== 4 && !intel
->is_g4x
)
2488 brw_MOV(p
, brw_null_reg(), dst
);
2490 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
2491 inst
->offset
, SURF_INDEX_FRAG_CONST_BUFFER
);
2493 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2494 /* gen4 errata: destination from a send can't be used as a
2495 * destination until it's been read. Just read it so we don't
2498 brw_MOV(p
, brw_null_reg(), dst
);
2503 fs_visitor::assign_curb_setup()
2505 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
2506 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2508 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2509 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2510 fs_inst
*inst
= (fs_inst
*)iter
.get();
2512 for (unsigned int i
= 0; i
< 3; i
++) {
2513 if (inst
->src
[i
].file
== UNIFORM
) {
2514 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2515 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2519 inst
->src
[i
].file
= FIXED_HW_REG
;
2520 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
2527 fs_visitor::calculate_urb_setup()
2529 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2534 /* Figure out where each of the incoming setup attributes lands. */
2535 if (intel
->gen
>= 6) {
2536 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2537 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2538 urb_setup
[i
] = urb_next
++;
2542 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2543 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2544 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2547 if (i
>= VERT_RESULT_VAR0
)
2548 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2549 else if (i
<= VERT_RESULT_TEX7
)
2555 urb_setup
[fp_index
] = urb_next
++;
2560 /* Each attribute is 4 setup channels, each of which is half a reg. */
2561 c
->prog_data
.urb_read_length
= urb_next
* 2;
2565 fs_visitor::assign_urb_setup()
2567 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2569 /* Offset all the urb_setup[] index by the actual position of the
2570 * setup regs, now that the location of the constants has been chosen.
2572 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2573 fs_inst
*inst
= (fs_inst
*)iter
.get();
2575 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
2576 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2577 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2580 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
2581 assert(inst
->src
[0].file
== FIXED_HW_REG
);
2582 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
2586 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2590 * Split large virtual GRFs into separate components if we can.
2592 * This is mostly duplicated with what brw_fs_vector_splitting does,
2593 * but that's really conservative because it's afraid of doing
2594 * splitting that doesn't result in real progress after the rest of
2595 * the optimization phases, which would cause infinite looping in
2596 * optimization. We can do it once here, safely. This also has the
2597 * opportunity to split interpolated values, or maybe even uniforms,
2598 * which we don't have at the IR level.
2600 * We want to split, because virtual GRFs are what we register
2601 * allocate and spill (due to contiguousness requirements for some
2602 * instructions), and they're what we naturally generate in the
2603 * codegen process, but most virtual GRFs don't actually need to be
2604 * contiguous sets of GRFs. If we split, we'll end up with reduced
2605 * live intervals and better dead code elimination and coalescing.
2608 fs_visitor::split_virtual_grfs()
2610 int num_vars
= this->virtual_grf_next
;
2611 bool split_grf
[num_vars
];
2612 int new_virtual_grf
[num_vars
];
2614 /* Try to split anything > 0 sized. */
2615 for (int i
= 0; i
< num_vars
; i
++) {
2616 if (this->virtual_grf_sizes
[i
] != 1)
2617 split_grf
[i
] = true;
2619 split_grf
[i
] = false;
2623 /* PLN opcodes rely on the delta_xy being contiguous. */
2624 split_grf
[this->delta_x
.reg
] = false;
2627 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2628 fs_inst
*inst
= (fs_inst
*)iter
.get();
2630 /* Texturing produces 4 contiguous registers, so no splitting. */
2631 if ((inst
->opcode
== FS_OPCODE_TEX
||
2632 inst
->opcode
== FS_OPCODE_TXB
||
2633 inst
->opcode
== FS_OPCODE_TXL
) &&
2634 inst
->dst
.file
== GRF
) {
2635 split_grf
[inst
->dst
.reg
] = false;
2639 /* Allocate new space for split regs. Note that the virtual
2640 * numbers will be contiguous.
2642 for (int i
= 0; i
< num_vars
; i
++) {
2644 new_virtual_grf
[i
] = virtual_grf_alloc(1);
2645 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
2646 int reg
= virtual_grf_alloc(1);
2647 assert(reg
== new_virtual_grf
[i
] + j
- 1);
2650 this->virtual_grf_sizes
[i
] = 1;
2654 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2655 fs_inst
*inst
= (fs_inst
*)iter
.get();
2657 if (inst
->dst
.file
== GRF
&&
2658 split_grf
[inst
->dst
.reg
] &&
2659 inst
->dst
.reg_offset
!= 0) {
2660 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
2661 inst
->dst
.reg_offset
- 1);
2662 inst
->dst
.reg_offset
= 0;
2664 for (int i
= 0; i
< 3; i
++) {
2665 if (inst
->src
[i
].file
== GRF
&&
2666 split_grf
[inst
->src
[i
].reg
] &&
2667 inst
->src
[i
].reg_offset
!= 0) {
2668 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
2669 inst
->src
[i
].reg_offset
- 1);
2670 inst
->src
[i
].reg_offset
= 0;
2674 this->live_intervals_valid
= false;
2678 * Choose accesses from the UNIFORM file to demote to using the pull
2681 * We allow a fragment shader to have more than the specified minimum
2682 * maximum number of fragment shader uniform components (64). If
2683 * there are too many of these, they'd fill up all of register space.
2684 * So, this will push some of them out to the pull constant buffer and
2685 * update the program to load them.
2688 fs_visitor::setup_pull_constants()
2690 /* Only allow 16 registers (128 uniform components) as push constants. */
2691 unsigned int max_uniform_components
= 16 * 8;
2692 if (c
->prog_data
.nr_params
<= max_uniform_components
)
2695 /* Just demote the end of the list. We could probably do better
2696 * here, demoting things that are rarely used in the program first.
2698 int pull_uniform_base
= max_uniform_components
;
2699 int pull_uniform_count
= c
->prog_data
.nr_params
- pull_uniform_base
;
2701 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2702 fs_inst
*inst
= (fs_inst
*)iter
.get();
2704 for (int i
= 0; i
< 3; i
++) {
2705 if (inst
->src
[i
].file
!= UNIFORM
)
2708 int uniform_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2709 if (uniform_nr
< pull_uniform_base
)
2712 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
2713 fs_inst
*pull
= new(mem_ctx
) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
2715 pull
->offset
= ((uniform_nr
- pull_uniform_base
) * 4) & ~15;
2716 pull
->ir
= inst
->ir
;
2717 pull
->annotation
= inst
->annotation
;
2718 pull
->base_mrf
= 14;
2721 inst
->insert_before(pull
);
2723 inst
->src
[i
].file
= GRF
;
2724 inst
->src
[i
].reg
= dst
.reg
;
2725 inst
->src
[i
].reg_offset
= 0;
2726 inst
->src
[i
].smear
= (uniform_nr
- pull_uniform_base
) & 3;
2730 for (int i
= 0; i
< pull_uniform_count
; i
++) {
2731 c
->prog_data
.pull_param
[i
] = c
->prog_data
.param
[pull_uniform_base
+ i
];
2732 c
->prog_data
.pull_param_convert
[i
] =
2733 c
->prog_data
.param_convert
[pull_uniform_base
+ i
];
2735 c
->prog_data
.nr_params
-= pull_uniform_count
;
2736 c
->prog_data
.nr_pull_params
= pull_uniform_count
;
2740 fs_visitor::calculate_live_intervals()
2742 int num_vars
= this->virtual_grf_next
;
2743 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2744 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2747 int bb_header_ip
= 0;
2749 if (this->live_intervals_valid
)
2752 for (int i
= 0; i
< num_vars
; i
++) {
2758 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2759 fs_inst
*inst
= (fs_inst
*)iter
.get();
2761 if (inst
->opcode
== BRW_OPCODE_DO
) {
2762 if (loop_depth
++ == 0)
2764 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2767 if (loop_depth
== 0) {
2768 /* Patches up the use of vars marked for being live across
2771 for (int i
= 0; i
< num_vars
; i
++) {
2772 if (use
[i
] == loop_start
) {
2778 for (unsigned int i
= 0; i
< 3; i
++) {
2779 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2780 int reg
= inst
->src
[i
].reg
;
2782 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2783 def
[reg
] >= bb_header_ip
)) {
2786 def
[reg
] = MIN2(loop_start
, def
[reg
]);
2787 use
[reg
] = loop_start
;
2789 /* Nobody else is going to go smash our start to
2790 * later in the loop now, because def[reg] now
2791 * points before the bb header.
2796 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2797 int reg
= inst
->dst
.reg
;
2799 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2800 !inst
->predicated
)) {
2801 def
[reg
] = MIN2(def
[reg
], ip
);
2803 def
[reg
] = MIN2(def
[reg
], loop_start
);
2810 /* Set the basic block header IP. This is used for determining
2811 * if a complete def of single-register virtual GRF in a loop
2812 * dominates a use in the same basic block. It's a quick way to
2813 * reduce the live interval range of most register used in a
2816 if (inst
->opcode
== BRW_OPCODE_IF
||
2817 inst
->opcode
== BRW_OPCODE_ELSE
||
2818 inst
->opcode
== BRW_OPCODE_ENDIF
||
2819 inst
->opcode
== BRW_OPCODE_DO
||
2820 inst
->opcode
== BRW_OPCODE_WHILE
||
2821 inst
->opcode
== BRW_OPCODE_BREAK
||
2822 inst
->opcode
== BRW_OPCODE_CONTINUE
) {
2827 talloc_free(this->virtual_grf_def
);
2828 talloc_free(this->virtual_grf_use
);
2829 this->virtual_grf_def
= def
;
2830 this->virtual_grf_use
= use
;
2832 this->live_intervals_valid
= true;
2836 * Attempts to move immediate constants into the immediate
2837 * constant slot of following instructions.
2839 * Immediate constants are a bit tricky -- they have to be in the last
2840 * operand slot, you can't do abs/negate on them,
2844 fs_visitor::propagate_constants()
2846 bool progress
= false;
2848 calculate_live_intervals();
2850 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2851 fs_inst
*inst
= (fs_inst
*)iter
.get();
2853 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2855 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2856 inst
->dst
.type
!= inst
->src
[0].type
)
2859 /* Don't bother with cases where we should have had the
2860 * operation on the constant folded in GLSL already.
2865 /* Found a move of a constant to a GRF. Find anything else using the GRF
2866 * before it's written, and replace it with the constant if we can.
2868 exec_list_iterator scan_iter
= iter
;
2870 for (; scan_iter
.has_next(); scan_iter
.next()) {
2871 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2873 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2874 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2875 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2876 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2880 for (int i
= 2; i
>= 0; i
--) {
2881 if (scan_inst
->src
[i
].file
!= GRF
||
2882 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2883 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2886 /* Don't bother with cases where we should have had the
2887 * operation on the constant folded in GLSL already.
2889 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2892 switch (scan_inst
->opcode
) {
2893 case BRW_OPCODE_MOV
:
2894 scan_inst
->src
[i
] = inst
->src
[0];
2898 case BRW_OPCODE_MUL
:
2899 case BRW_OPCODE_ADD
:
2901 scan_inst
->src
[i
] = inst
->src
[0];
2903 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2904 /* Fit this constant in by commuting the operands */
2905 scan_inst
->src
[0] = scan_inst
->src
[1];
2906 scan_inst
->src
[1] = inst
->src
[0];
2910 case BRW_OPCODE_CMP
:
2911 case BRW_OPCODE_SEL
:
2913 scan_inst
->src
[i
] = inst
->src
[0];
2919 if (scan_inst
->dst
.file
== GRF
&&
2920 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2921 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2922 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2929 this->live_intervals_valid
= false;
2934 * Must be called after calculate_live_intervales() to remove unused
2935 * writes to registers -- register allocation will fail otherwise
2936 * because something deffed but not used won't be considered to
2937 * interfere with other regs.
2940 fs_visitor::dead_code_eliminate()
2942 bool progress
= false;
2945 calculate_live_intervals();
2947 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2948 fs_inst
*inst
= (fs_inst
*)iter
.get();
2950 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
2959 live_intervals_valid
= false;
2965 fs_visitor::register_coalesce()
2967 bool progress
= false;
2971 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2972 fs_inst
*inst
= (fs_inst
*)iter
.get();
2974 /* Make sure that we dominate the instructions we're going to
2975 * scan for interfering with our coalescing, or we won't have
2976 * scanned enough to see if anything interferes with our
2977 * coalescing. We don't dominate the following instructions if
2978 * we're in a loop or an if block.
2980 switch (inst
->opcode
) {
2984 case BRW_OPCODE_WHILE
:
2990 case BRW_OPCODE_ENDIF
:
2994 if (loop_depth
|| if_depth
)
2997 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3000 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
3001 inst
->dst
.type
!= inst
->src
[0].type
)
3004 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
3005 * them: check for no writes to either one until the exit of the
3008 bool interfered
= false;
3009 exec_list_iterator scan_iter
= iter
;
3011 for (; scan_iter
.has_next(); scan_iter
.next()) {
3012 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
3014 if (scan_inst
->dst
.file
== GRF
) {
3015 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
3016 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
3017 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
3021 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
3022 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
3023 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
3033 /* Rewrite the later usage to point at the source of the move to
3036 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
3038 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
3040 for (int i
= 0; i
< 3; i
++) {
3041 if (scan_inst
->src
[i
].file
== GRF
&&
3042 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
3043 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
3044 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
3045 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
3046 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
3047 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
3048 scan_inst
->src
[i
].smear
= inst
->src
[0].smear
;
3058 live_intervals_valid
= false;
3065 fs_visitor::compute_to_mrf()
3067 bool progress
= false;
3070 calculate_live_intervals();
3072 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3073 fs_inst
*inst
= (fs_inst
*)iter
.get();
3078 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3080 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
3081 inst
->dst
.type
!= inst
->src
[0].type
||
3082 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
3085 /* Can't compute-to-MRF this GRF if someone else was going to
3088 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
3091 /* Found a move of a GRF to a MRF. Let's see if we can go
3092 * rewrite the thing that made this GRF to write into the MRF.
3095 for (scan_inst
= (fs_inst
*)inst
->prev
;
3096 scan_inst
->prev
!= NULL
;
3097 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
3098 if (scan_inst
->dst
.file
== GRF
&&
3099 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
3100 /* Found the last thing to write our reg we want to turn
3101 * into a compute-to-MRF.
3104 if (scan_inst
->opcode
== FS_OPCODE_TEX
) {
3105 /* texturing writes several continuous regs, so we can't
3106 * compute-to-mrf that.
3111 /* If it's predicated, it (probably) didn't populate all
3114 if (scan_inst
->predicated
)
3117 /* SEND instructions can't have MRF as a destination. */
3118 if (scan_inst
->mlen
)
3121 if (intel
->gen
>= 6) {
3122 /* gen6 math instructions must have the destination be
3123 * GRF, so no compute-to-MRF for them.
3125 if (scan_inst
->opcode
== FS_OPCODE_RCP
||
3126 scan_inst
->opcode
== FS_OPCODE_RSQ
||
3127 scan_inst
->opcode
== FS_OPCODE_SQRT
||
3128 scan_inst
->opcode
== FS_OPCODE_EXP2
||
3129 scan_inst
->opcode
== FS_OPCODE_LOG2
||
3130 scan_inst
->opcode
== FS_OPCODE_SIN
||
3131 scan_inst
->opcode
== FS_OPCODE_COS
||
3132 scan_inst
->opcode
== FS_OPCODE_POW
) {
3137 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
3138 /* Found the creator of our MRF's source value. */
3139 scan_inst
->dst
.file
= MRF
;
3140 scan_inst
->dst
.hw_reg
= inst
->dst
.hw_reg
;
3141 scan_inst
->saturate
|= inst
->saturate
;
3148 /* We don't handle flow control here. Most computation of
3149 * values that end up in MRFs are shortly before the MRF
3152 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
3153 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
3154 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
3158 /* You can't read from an MRF, so if someone else reads our
3159 * MRF's source GRF that we wanted to rewrite, that stops us.
3161 bool interfered
= false;
3162 for (int i
= 0; i
< 3; i
++) {
3163 if (scan_inst
->src
[i
].file
== GRF
&&
3164 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
3165 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
3172 if (scan_inst
->dst
.file
== MRF
&&
3173 scan_inst
->dst
.hw_reg
== inst
->dst
.hw_reg
) {
3174 /* Somebody else wrote our MRF here, so we can't can't
3175 * compute-to-MRF before that.
3180 if (scan_inst
->mlen
> 0) {
3181 /* Found a SEND instruction, which means that there are
3182 * live values in MRFs from base_mrf to base_mrf +
3183 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3186 if (inst
->dst
.hw_reg
>= scan_inst
->base_mrf
&&
3187 inst
->dst
.hw_reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
3198 * Walks through basic blocks, locking for repeated MRF writes and
3199 * removing the later ones.
3202 fs_visitor::remove_duplicate_mrf_writes()
3204 fs_inst
*last_mrf_move
[16];
3205 bool progress
= false;
3207 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3209 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3210 fs_inst
*inst
= (fs_inst
*)iter
.get();
3212 switch (inst
->opcode
) {
3214 case BRW_OPCODE_WHILE
:
3216 case BRW_OPCODE_ELSE
:
3217 case BRW_OPCODE_ENDIF
:
3218 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3224 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3225 inst
->dst
.file
== MRF
) {
3226 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.hw_reg
];
3227 if (prev_inst
&& inst
->equals(prev_inst
)) {
3234 /* Clear out the last-write records for MRFs that were overwritten. */
3235 if (inst
->dst
.file
== MRF
) {
3236 last_mrf_move
[inst
->dst
.hw_reg
] = NULL
;
3239 if (inst
->mlen
> 0) {
3240 /* Found a SEND instruction, which will include two of fewer
3241 * implied MRF writes. We could do better here.
3243 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3244 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3248 /* Clear out any MRF move records whose sources got overwritten. */
3249 if (inst
->dst
.file
== GRF
) {
3250 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
3251 if (last_mrf_move
[i
] &&
3252 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
3253 last_mrf_move
[i
] = NULL
;
3258 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3259 inst
->dst
.file
== MRF
&&
3260 inst
->src
[0].file
== GRF
&&
3261 !inst
->predicated
) {
3262 last_mrf_move
[inst
->dst
.hw_reg
] = inst
;
3270 fs_visitor::virtual_grf_interferes(int a
, int b
)
3272 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
3273 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
3275 /* For dead code, just check if the def interferes with the other range. */
3276 if (this->virtual_grf_use
[a
] == -1) {
3277 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
3278 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
3280 if (this->virtual_grf_use
[b
] == -1) {
3281 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
3282 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
3288 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
3290 struct brw_reg brw_reg
;
3292 switch (reg
->file
) {
3296 if (reg
->smear
== -1) {
3297 brw_reg
= brw_vec8_reg(reg
->file
,
3300 brw_reg
= brw_vec1_reg(reg
->file
,
3301 reg
->hw_reg
, reg
->smear
);
3303 brw_reg
= retype(brw_reg
, reg
->type
);
3306 switch (reg
->type
) {
3307 case BRW_REGISTER_TYPE_F
:
3308 brw_reg
= brw_imm_f(reg
->imm
.f
);
3310 case BRW_REGISTER_TYPE_D
:
3311 brw_reg
= brw_imm_d(reg
->imm
.i
);
3313 case BRW_REGISTER_TYPE_UD
:
3314 brw_reg
= brw_imm_ud(reg
->imm
.u
);
3317 assert(!"not reached");
3318 brw_reg
= brw_null_reg();
3323 brw_reg
= reg
->fixed_hw_reg
;
3326 /* Probably unused. */
3327 brw_reg
= brw_null_reg();
3330 assert(!"not reached");
3331 brw_reg
= brw_null_reg();
3334 assert(!"not reached");
3335 brw_reg
= brw_null_reg();
3339 brw_reg
= brw_abs(brw_reg
);
3341 brw_reg
= negate(brw_reg
);
3347 fs_visitor::generate_code()
3349 int last_native_inst
= 0;
3350 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
3351 int if_stack_depth
= 0, loop_stack_depth
= 0;
3352 int if_depth_in_loop
[16];
3353 const char *last_annotation_string
= NULL
;
3354 ir_instruction
*last_annotation_ir
= NULL
;
3356 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3357 printf("Native code for fragment shader %d:\n",
3358 ctx
->Shader
.CurrentFragmentProgram
->Name
);
3361 if_depth_in_loop
[loop_stack_depth
] = 0;
3363 memset(&if_stack
, 0, sizeof(if_stack
));
3364 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3365 fs_inst
*inst
= (fs_inst
*)iter
.get();
3366 struct brw_reg src
[3], dst
;
3368 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3369 if (last_annotation_ir
!= inst
->ir
) {
3370 last_annotation_ir
= inst
->ir
;
3371 if (last_annotation_ir
) {
3373 last_annotation_ir
->print();
3377 if (last_annotation_string
!= inst
->annotation
) {
3378 last_annotation_string
= inst
->annotation
;
3379 if (last_annotation_string
)
3380 printf(" %s\n", last_annotation_string
);
3384 for (unsigned int i
= 0; i
< 3; i
++) {
3385 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
3387 dst
= brw_reg_from_fs_reg(&inst
->dst
);
3389 brw_set_conditionalmod(p
, inst
->conditional_mod
);
3390 brw_set_predicate_control(p
, inst
->predicated
);
3391 brw_set_saturate(p
, inst
->saturate
);
3393 switch (inst
->opcode
) {
3394 case BRW_OPCODE_MOV
:
3395 brw_MOV(p
, dst
, src
[0]);
3397 case BRW_OPCODE_ADD
:
3398 brw_ADD(p
, dst
, src
[0], src
[1]);
3400 case BRW_OPCODE_MUL
:
3401 brw_MUL(p
, dst
, src
[0], src
[1]);
3404 case BRW_OPCODE_FRC
:
3405 brw_FRC(p
, dst
, src
[0]);
3407 case BRW_OPCODE_RNDD
:
3408 brw_RNDD(p
, dst
, src
[0]);
3410 case BRW_OPCODE_RNDE
:
3411 brw_RNDE(p
, dst
, src
[0]);
3413 case BRW_OPCODE_RNDZ
:
3414 brw_RNDZ(p
, dst
, src
[0]);
3417 case BRW_OPCODE_AND
:
3418 brw_AND(p
, dst
, src
[0], src
[1]);
3421 brw_OR(p
, dst
, src
[0], src
[1]);
3423 case BRW_OPCODE_XOR
:
3424 brw_XOR(p
, dst
, src
[0], src
[1]);
3426 case BRW_OPCODE_NOT
:
3427 brw_NOT(p
, dst
, src
[0]);
3429 case BRW_OPCODE_ASR
:
3430 brw_ASR(p
, dst
, src
[0], src
[1]);
3432 case BRW_OPCODE_SHR
:
3433 brw_SHR(p
, dst
, src
[0], src
[1]);
3435 case BRW_OPCODE_SHL
:
3436 brw_SHL(p
, dst
, src
[0], src
[1]);
3439 case BRW_OPCODE_CMP
:
3440 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
3442 case BRW_OPCODE_SEL
:
3443 brw_SEL(p
, dst
, src
[0], src
[1]);
3447 assert(if_stack_depth
< 16);
3448 if (inst
->src
[0].file
!= BAD_FILE
) {
3449 assert(intel
->gen
>= 6);
3450 if_stack
[if_stack_depth
] = brw_IF_gen6(p
, inst
->conditional_mod
, src
[0], src
[1]);
3452 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
3454 if_depth_in_loop
[loop_stack_depth
]++;
3458 case BRW_OPCODE_ELSE
:
3459 if_stack
[if_stack_depth
- 1] =
3460 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
3462 case BRW_OPCODE_ENDIF
:
3464 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
3465 if_depth_in_loop
[loop_stack_depth
]--;
3469 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
3470 if_depth_in_loop
[loop_stack_depth
] = 0;
3473 case BRW_OPCODE_BREAK
:
3474 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
3475 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3477 case BRW_OPCODE_CONTINUE
:
3478 /* FINISHME: We need to write the loop instruction support still. */
3479 if (intel
->gen
>= 6)
3480 brw_CONT_gen6(p
, loop_stack
[loop_stack_depth
- 1]);
3482 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
3483 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3486 case BRW_OPCODE_WHILE
: {
3487 struct brw_instruction
*inst0
, *inst1
;
3490 if (intel
->gen
>= 5)
3493 assert(loop_stack_depth
> 0);
3495 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
3496 if (intel
->gen
< 6) {
3497 /* patch all the BREAK/CONT instructions from last BGNLOOP */
3498 while (inst0
> loop_stack
[loop_stack_depth
]) {
3500 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
3501 inst0
->bits3
.if_else
.jump_count
== 0) {
3502 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
3504 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
3505 inst0
->bits3
.if_else
.jump_count
== 0) {
3506 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
3515 case FS_OPCODE_SQRT
:
3516 case FS_OPCODE_EXP2
:
3517 case FS_OPCODE_LOG2
:
3521 generate_math(inst
, dst
, src
);
3523 case FS_OPCODE_CINTERP
:
3524 brw_MOV(p
, dst
, src
[0]);
3526 case FS_OPCODE_LINTERP
:
3527 generate_linterp(inst
, dst
, src
);
3532 generate_tex(inst
, dst
);
3534 case FS_OPCODE_DISCARD_NOT
:
3535 generate_discard_not(inst
, dst
);
3537 case FS_OPCODE_DISCARD_AND
:
3538 generate_discard_and(inst
, src
[0]);
3541 generate_ddx(inst
, dst
, src
[0]);
3544 generate_ddy(inst
, dst
, src
[0]);
3547 case FS_OPCODE_SPILL
:
3548 generate_spill(inst
, src
[0]);
3551 case FS_OPCODE_UNSPILL
:
3552 generate_unspill(inst
, dst
);
3555 case FS_OPCODE_PULL_CONSTANT_LOAD
:
3556 generate_pull_constant_load(inst
, dst
);
3559 case FS_OPCODE_FB_WRITE
:
3560 generate_fb_write(inst
);
3563 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
3564 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
3565 brw_opcodes
[inst
->opcode
].name
);
3567 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
3572 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3573 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
3575 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3576 ((uint32_t *)&p
->store
[i
])[3],
3577 ((uint32_t *)&p
->store
[i
])[2],
3578 ((uint32_t *)&p
->store
[i
])[1],
3579 ((uint32_t *)&p
->store
[i
])[0]);
3581 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3585 last_native_inst
= p
->nr_insn
;
3590 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
3591 * emit issues, it doesn't get the jump distances into the output,
3592 * which is often something we want to debug. So this is here in
3593 * case you're doing that.
3596 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3597 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3598 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3599 ((uint32_t *)&p
->store
[i
])[3],
3600 ((uint32_t *)&p
->store
[i
])[2],
3601 ((uint32_t *)&p
->store
[i
])[1],
3602 ((uint32_t *)&p
->store
[i
])[0]);
3603 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3610 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
3612 struct intel_context
*intel
= &brw
->intel
;
3613 struct gl_context
*ctx
= &intel
->ctx
;
3614 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentFragmentProgram
;
3619 struct brw_shader
*shader
=
3620 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3624 /* We always use 8-wide mode, at least for now. For one, flow
3625 * control only works in 8-wide. Also, when we're fragment shader
3626 * bound, we're almost always under register pressure as well, so
3627 * 8-wide would save us from the performance cliff of spilling
3630 c
->dispatch_width
= 8;
3632 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3633 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3634 _mesa_print_ir(shader
->ir
, NULL
);
3638 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3640 fs_visitor
v(c
, shader
);
3645 v
.calculate_urb_setup();
3647 v
.emit_interpolation_setup_gen4();
3649 v
.emit_interpolation_setup_gen6();
3651 /* Generate FS IR for main(). (the visitor only descends into
3652 * functions called "main").
3654 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3655 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3662 v
.split_virtual_grfs();
3663 v
.setup_pull_constants();
3665 v
.assign_curb_setup();
3666 v
.assign_urb_setup();
3672 progress
= v
.remove_duplicate_mrf_writes() || progress
;
3674 progress
= v
.propagate_constants() || progress
;
3675 progress
= v
.register_coalesce() || progress
;
3676 progress
= v
.compute_to_mrf() || progress
;
3677 progress
= v
.dead_code_eliminate() || progress
;
3681 /* Debug of register spilling: Go spill everything. */
3682 int virtual_grf_count
= v
.virtual_grf_next
;
3683 for (int i
= 1; i
< virtual_grf_count
; i
++) {
3689 v
.assign_regs_trivial();
3691 while (!v
.assign_regs()) {
3701 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3706 c
->prog_data
.total_grf
= v
.grf_used
;