2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "main/macros.h"
36 #include "main/shaderobj.h"
37 #include "main/uniforms.h"
38 #include "main/fbobject.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/register_allocate.h"
42 #include "program/sampler.h"
43 #include "program/hash_table.h"
44 #include "brw_context.h"
48 #include "brw_shader.h"
50 #include "glsl/glsl_types.h"
51 #include "glsl/ir_print_visitor.h"
54 fs_visitor::type_size(const struct glsl_type
*type
)
58 switch (type
->base_type
) {
63 return type
->components();
65 return type_size(type
->fields
.array
) * type
->length
;
66 case GLSL_TYPE_STRUCT
:
68 for (i
= 0; i
< type
->length
; i
++) {
69 size
+= type_size(type
->fields
.structure
[i
].type
);
72 case GLSL_TYPE_SAMPLER
:
73 /* Samplers take up no register space, since they're baked in at
78 assert(!"not reached");
84 fs_visitor::fail(const char *format
, ...)
95 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
97 msg
= ralloc_asprintf(mem_ctx
, "FS compile failed: %s\n", msg
);
101 if (INTEL_DEBUG
& DEBUG_WM
) {
102 fprintf(stderr
, "%s", msg
);
107 fs_visitor::push_force_uncompressed()
109 force_uncompressed_stack
++;
113 fs_visitor::pop_force_uncompressed()
115 force_uncompressed_stack
--;
116 assert(force_uncompressed_stack
>= 0);
120 fs_visitor::push_force_sechalf()
122 force_sechalf_stack
++;
126 fs_visitor::pop_force_sechalf()
128 force_sechalf_stack
--;
129 assert(force_sechalf_stack
>= 0);
133 * Returns how many MRFs an FS opcode will write over.
135 * Note that this is not the 0 or 1 implied writes in an actual gen
136 * instruction -- the FS opcodes often generate MOVs in addition.
139 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
144 switch (inst
->opcode
) {
145 case SHADER_OPCODE_RCP
:
146 case SHADER_OPCODE_RSQ
:
147 case SHADER_OPCODE_SQRT
:
148 case SHADER_OPCODE_EXP2
:
149 case SHADER_OPCODE_LOG2
:
150 case SHADER_OPCODE_SIN
:
151 case SHADER_OPCODE_COS
:
152 return 1 * c
->dispatch_width
/ 8;
153 case SHADER_OPCODE_POW
:
154 case SHADER_OPCODE_INT_QUOTIENT
:
155 case SHADER_OPCODE_INT_REMAINDER
:
156 return 2 * c
->dispatch_width
/ 8;
157 case SHADER_OPCODE_TEX
:
159 case SHADER_OPCODE_TXD
:
160 case SHADER_OPCODE_TXF
:
161 case SHADER_OPCODE_TXL
:
162 case SHADER_OPCODE_TXS
:
164 case FS_OPCODE_FB_WRITE
:
166 case FS_OPCODE_PULL_CONSTANT_LOAD
:
167 case FS_OPCODE_UNSPILL
:
169 case FS_OPCODE_SPILL
:
172 assert(!"not reached");
178 fs_visitor::virtual_grf_alloc(int size
)
180 if (virtual_grf_array_size
<= virtual_grf_next
) {
181 if (virtual_grf_array_size
== 0)
182 virtual_grf_array_size
= 16;
184 virtual_grf_array_size
*= 2;
185 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
186 virtual_grf_array_size
);
188 virtual_grf_sizes
[virtual_grf_next
] = size
;
189 return virtual_grf_next
++;
192 /** Fixed HW reg constructor. */
193 fs_reg::fs_reg(enum register_file file
, int reg
)
198 this->type
= BRW_REGISTER_TYPE_F
;
201 /** Fixed HW reg constructor. */
202 fs_reg::fs_reg(enum register_file file
, int reg
, uint32_t type
)
210 /** Automatic reg constructor. */
211 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
216 this->reg
= v
->virtual_grf_alloc(v
->type_size(type
));
217 this->reg_offset
= 0;
218 this->type
= brw_type_for_base_type(type
);
222 fs_visitor::variable_storage(ir_variable
*var
)
224 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
228 import_uniforms_callback(const void *key
,
232 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
233 const fs_reg
*reg
= (const fs_reg
*)data
;
235 if (reg
->file
!= UNIFORM
)
238 hash_table_insert(dst_ht
, data
, key
);
241 /* For 16-wide, we need to follow from the uniform setup of 8-wide dispatch.
242 * This brings in those uniform definitions
245 fs_visitor::import_uniforms(fs_visitor
*v
)
247 hash_table_call_foreach(v
->variable_ht
,
248 import_uniforms_callback
,
250 this->params_remap
= v
->params_remap
;
253 /* Our support for uniforms is piggy-backed on the struct
254 * gl_fragment_program, because that's where the values actually
255 * get stored, rather than in some global gl_shader_program uniform
259 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
261 unsigned int offset
= 0;
263 if (type
->is_matrix()) {
264 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
265 type
->vector_elements
,
268 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
269 offset
+= setup_uniform_values(loc
+ offset
, column
);
275 switch (type
->base_type
) {
276 case GLSL_TYPE_FLOAT
:
280 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
281 unsigned int param
= c
->prog_data
.nr_params
++;
283 assert(param
< ARRAY_SIZE(c
->prog_data
.param
));
285 if (ctx
->Const
.NativeIntegers
) {
286 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
288 switch (type
->base_type
) {
289 case GLSL_TYPE_FLOAT
:
290 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
293 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2U
;
296 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2I
;
299 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2B
;
302 assert(!"not reached");
303 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
307 this->param_index
[param
] = loc
;
308 this->param_offset
[param
] = i
;
312 case GLSL_TYPE_STRUCT
:
313 for (unsigned int i
= 0; i
< type
->length
; i
++) {
314 offset
+= setup_uniform_values(loc
+ offset
,
315 type
->fields
.structure
[i
].type
);
319 case GLSL_TYPE_ARRAY
:
320 for (unsigned int i
= 0; i
< type
->length
; i
++) {
321 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
325 case GLSL_TYPE_SAMPLER
:
326 /* The sampler takes up a slot, but we don't use any values from it. */
330 assert(!"not reached");
336 /* Our support for builtin uniforms is even scarier than non-builtin.
337 * It sits on top of the PROG_STATE_VAR parameters that are
338 * automatically updated from GL context state.
341 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
343 const ir_state_slot
*const slots
= ir
->state_slots
;
344 assert(ir
->state_slots
!= NULL
);
346 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
347 /* This state reference has already been setup by ir_to_mesa, but we'll
348 * get the same index back here.
350 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
351 (gl_state_index
*)slots
[i
].tokens
);
353 /* Add each of the unique swizzles of the element as a parameter.
354 * This'll end up matching the expected layout of the
355 * array/matrix/structure we're trying to fill in.
358 for (unsigned int j
= 0; j
< 4; j
++) {
359 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
360 if (swiz
== last_swiz
)
364 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
366 this->param_index
[c
->prog_data
.nr_params
] = index
;
367 this->param_offset
[c
->prog_data
.nr_params
] = swiz
;
368 c
->prog_data
.nr_params
++;
374 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
376 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
378 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
381 if (ir
->pixel_center_integer
) {
382 emit(BRW_OPCODE_MOV
, wpos
, this->pixel_x
);
384 emit(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
));
389 if (!flip
&& ir
->pixel_center_integer
) {
390 emit(BRW_OPCODE_MOV
, wpos
, this->pixel_y
);
392 fs_reg pixel_y
= this->pixel_y
;
393 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
396 pixel_y
.negate
= true;
397 offset
+= c
->key
.drawable_height
- 1.0;
400 emit(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
));
405 if (intel
->gen
>= 6) {
406 emit(BRW_OPCODE_MOV
, wpos
,
407 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0)));
409 emit(FS_OPCODE_LINTERP
, wpos
,
410 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
411 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
412 interp_reg(FRAG_ATTRIB_WPOS
, 2));
416 /* gl_FragCoord.w: Already set up in emit_interpolation */
417 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
423 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
425 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
426 reg
->type
= brw_type_for_base_type(ir
->type
->get_scalar_type());
429 unsigned int array_elements
;
430 const glsl_type
*type
;
432 if (ir
->type
->is_array()) {
433 array_elements
= ir
->type
->length
;
434 if (array_elements
== 0) {
435 fail("dereferenced array '%s' has length 0\n", ir
->name
);
437 type
= ir
->type
->fields
.array
;
443 glsl_interp_qualifier interpolation_mode
=
444 ir
->determine_interpolation_mode(c
->key
.flat_shade
);
446 int location
= ir
->location
;
447 for (unsigned int i
= 0; i
< array_elements
; i
++) {
448 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
449 if (urb_setup
[location
] == -1) {
450 /* If there's no incoming setup data for this slot, don't
451 * emit interpolation for it.
453 attr
.reg_offset
+= type
->vector_elements
;
458 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
459 /* Constant interpolation (flat shading) case. The SF has
460 * handed us defined values in only the constant offset
461 * field of the setup reg.
463 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
464 struct brw_reg interp
= interp_reg(location
, k
);
465 interp
= suboffset(interp
, 3);
466 interp
.type
= reg
->type
;
467 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
471 /* Smooth/noperspective interpolation case. */
472 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
473 /* FINISHME: At some point we probably want to push
474 * this farther by giving similar treatment to the
475 * other potentially constant components of the
476 * attribute, as well as making brw_vs_constval.c
477 * handle varyings other than gl_TexCoord.
479 if (location
>= FRAG_ATTRIB_TEX0
&&
480 location
<= FRAG_ATTRIB_TEX7
&&
481 k
== 3 && !(c
->key
.proj_attrib_mask
& (1 << location
))) {
482 emit(BRW_OPCODE_MOV
, attr
, fs_reg(1.0f
));
484 struct brw_reg interp
= interp_reg(location
, k
);
485 brw_wm_barycentric_interp_mode barycoord_mode
;
486 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
487 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
489 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
490 emit(FS_OPCODE_LINTERP
, attr
,
491 this->delta_x
[barycoord_mode
],
492 this->delta_y
[barycoord_mode
], fs_reg(interp
));
493 if (intel
->gen
< 6) {
494 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
509 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
511 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
513 /* The frontfacing comes in as a bit in the thread payload. */
514 if (intel
->gen
>= 6) {
515 emit(BRW_OPCODE_ASR
, *reg
,
516 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
518 emit(BRW_OPCODE_NOT
, *reg
, *reg
);
519 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1));
521 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
522 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
525 fs_inst
*inst
= emit(BRW_OPCODE_CMP
, *reg
,
528 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
529 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u));
536 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src
)
539 case SHADER_OPCODE_RCP
:
540 case SHADER_OPCODE_RSQ
:
541 case SHADER_OPCODE_SQRT
:
542 case SHADER_OPCODE_EXP2
:
543 case SHADER_OPCODE_LOG2
:
544 case SHADER_OPCODE_SIN
:
545 case SHADER_OPCODE_COS
:
548 assert(!"not reached: bad math opcode");
552 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
553 * might be able to do better by doing execsize = 1 math and then
554 * expanding that result out, but we would need to be careful with
557 * Gen 6 hardware ignores source modifiers (negate and abs) on math
558 * instructions, so we also move to a temp to set those up.
560 if (intel
->gen
== 6 && (src
.file
== UNIFORM
||
563 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
564 emit(BRW_OPCODE_MOV
, expanded
, src
);
568 fs_inst
*inst
= emit(opcode
, dst
, src
);
570 if (intel
->gen
< 6) {
572 inst
->mlen
= c
->dispatch_width
/ 8;
579 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
585 case SHADER_OPCODE_POW
:
586 case SHADER_OPCODE_INT_QUOTIENT
:
587 case SHADER_OPCODE_INT_REMAINDER
:
590 assert(!"not reached: unsupported binary math opcode.");
594 if (intel
->gen
>= 7) {
595 inst
= emit(opcode
, dst
, src0
, src1
);
596 } else if (intel
->gen
== 6) {
597 /* Can't do hstride == 0 args to gen6 math, so expand it out.
599 * The hardware ignores source modifiers (negate and abs) on math
600 * instructions, so we also move to a temp to set those up.
602 if (src0
.file
== UNIFORM
|| src0
.abs
|| src0
.negate
) {
603 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
604 expanded
.type
= src0
.type
;
605 emit(BRW_OPCODE_MOV
, expanded
, src0
);
609 if (src1
.file
== UNIFORM
|| src1
.abs
|| src1
.negate
) {
610 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
611 expanded
.type
= src1
.type
;
612 emit(BRW_OPCODE_MOV
, expanded
, src1
);
616 inst
= emit(opcode
, dst
, src0
, src1
);
618 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
621 * "Operand0[7]. For the INT DIV functions, this operand is the
624 * "Operand1[7]. For the INT DIV functions, this operand is the
627 bool is_int_div
= opcode
!= SHADER_OPCODE_POW
;
628 fs_reg
&op0
= is_int_div
? src1
: src0
;
629 fs_reg
&op1
= is_int_div
? src0
: src1
;
631 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1, op1
.type
), op1
);
632 inst
= emit(opcode
, dst
, op0
, reg_null_f
);
634 inst
->base_mrf
= base_mrf
;
635 inst
->mlen
= 2 * c
->dispatch_width
/ 8;
641 * To be called after the last _mesa_add_state_reference() call, to
642 * set up prog_data.param[] for assign_curb_setup() and
643 * setup_pull_constants().
646 fs_visitor::setup_paramvalues_refs()
648 if (c
->dispatch_width
!= 8)
651 /* Set up the pointers to ParamValues now that that array is finalized. */
652 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
653 c
->prog_data
.param
[i
] =
654 (const float *)fp
->Base
.Parameters
->ParameterValues
[this->param_index
[i
]] +
655 this->param_offset
[i
];
660 fs_visitor::assign_curb_setup()
662 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
663 if (c
->dispatch_width
== 8) {
664 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
666 c
->prog_data
.first_curbe_grf_16
= c
->nr_payload_regs
;
669 /* Map the offsets in the UNIFORM file to fixed HW regs. */
670 foreach_list(node
, &this->instructions
) {
671 fs_inst
*inst
= (fs_inst
*)node
;
673 for (unsigned int i
= 0; i
< 3; i
++) {
674 if (inst
->src
[i
].file
== UNIFORM
) {
675 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
676 struct brw_reg brw_reg
= brw_vec1_grf(c
->nr_payload_regs
+
680 inst
->src
[i
].file
= FIXED_HW_REG
;
681 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
688 fs_visitor::calculate_urb_setup()
690 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
695 /* Figure out where each of the incoming setup attributes lands. */
696 if (intel
->gen
>= 6) {
697 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
698 if (fp
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
699 urb_setup
[i
] = urb_next
++;
703 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
704 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
705 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
706 int fp_index
= _mesa_vert_result_to_frag_attrib((gl_vert_result
) i
);
709 urb_setup
[fp_index
] = urb_next
++;
714 * It's a FS only attribute, and we did interpolation for this attribute
715 * in SF thread. So, count it here, too.
717 * See compile_sf_prog() for more info.
719 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(FRAG_ATTRIB_PNTC
))
720 urb_setup
[FRAG_ATTRIB_PNTC
] = urb_next
++;
723 /* Each attribute is 4 setup channels, each of which is half a reg. */
724 c
->prog_data
.urb_read_length
= urb_next
* 2;
728 fs_visitor::assign_urb_setup()
730 int urb_start
= c
->nr_payload_regs
+ c
->prog_data
.curb_read_length
;
732 /* Offset all the urb_setup[] index by the actual position of the
733 * setup regs, now that the location of the constants has been chosen.
735 foreach_list(node
, &this->instructions
) {
736 fs_inst
*inst
= (fs_inst
*)node
;
738 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
739 assert(inst
->src
[2].file
== FIXED_HW_REG
);
740 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
743 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
744 assert(inst
->src
[0].file
== FIXED_HW_REG
);
745 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
749 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
753 * Split large virtual GRFs into separate components if we can.
755 * This is mostly duplicated with what brw_fs_vector_splitting does,
756 * but that's really conservative because it's afraid of doing
757 * splitting that doesn't result in real progress after the rest of
758 * the optimization phases, which would cause infinite looping in
759 * optimization. We can do it once here, safely. This also has the
760 * opportunity to split interpolated values, or maybe even uniforms,
761 * which we don't have at the IR level.
763 * We want to split, because virtual GRFs are what we register
764 * allocate and spill (due to contiguousness requirements for some
765 * instructions), and they're what we naturally generate in the
766 * codegen process, but most virtual GRFs don't actually need to be
767 * contiguous sets of GRFs. If we split, we'll end up with reduced
768 * live intervals and better dead code elimination and coalescing.
771 fs_visitor::split_virtual_grfs()
773 int num_vars
= this->virtual_grf_next
;
774 bool split_grf
[num_vars
];
775 int new_virtual_grf
[num_vars
];
777 /* Try to split anything > 0 sized. */
778 for (int i
= 0; i
< num_vars
; i
++) {
779 if (this->virtual_grf_sizes
[i
] != 1)
782 split_grf
[i
] = false;
786 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
) {
787 /* PLN opcodes rely on the delta_xy being contiguous. We only have to
788 * check this for BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because prior to
789 * Gen6, that was the only supported interpolation mode, and since Gen6,
790 * delta_x and delta_y are in fixed hardware registers.
792 split_grf
[this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
] =
796 foreach_list(node
, &this->instructions
) {
797 fs_inst
*inst
= (fs_inst
*)node
;
799 /* Texturing produces 4 contiguous registers, so no splitting. */
800 if (inst
->is_tex()) {
801 split_grf
[inst
->dst
.reg
] = false;
805 /* Allocate new space for split regs. Note that the virtual
806 * numbers will be contiguous.
808 for (int i
= 0; i
< num_vars
; i
++) {
810 new_virtual_grf
[i
] = virtual_grf_alloc(1);
811 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
812 int reg
= virtual_grf_alloc(1);
813 assert(reg
== new_virtual_grf
[i
] + j
- 1);
816 this->virtual_grf_sizes
[i
] = 1;
820 foreach_list(node
, &this->instructions
) {
821 fs_inst
*inst
= (fs_inst
*)node
;
823 if (inst
->dst
.file
== GRF
&&
824 split_grf
[inst
->dst
.reg
] &&
825 inst
->dst
.reg_offset
!= 0) {
826 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
827 inst
->dst
.reg_offset
- 1);
828 inst
->dst
.reg_offset
= 0;
830 for (int i
= 0; i
< 3; i
++) {
831 if (inst
->src
[i
].file
== GRF
&&
832 split_grf
[inst
->src
[i
].reg
] &&
833 inst
->src
[i
].reg_offset
!= 0) {
834 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
835 inst
->src
[i
].reg_offset
- 1);
836 inst
->src
[i
].reg_offset
= 0;
840 this->live_intervals_valid
= false;
844 fs_visitor::remove_dead_constants()
846 if (c
->dispatch_width
== 8) {
847 this->params_remap
= ralloc_array(mem_ctx
, int, c
->prog_data
.nr_params
);
849 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++)
850 this->params_remap
[i
] = -1;
852 /* Find which params are still in use. */
853 foreach_list(node
, &this->instructions
) {
854 fs_inst
*inst
= (fs_inst
*)node
;
856 for (int i
= 0; i
< 3; i
++) {
857 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
859 if (inst
->src
[i
].file
!= UNIFORM
)
862 assert(constant_nr
< (int)c
->prog_data
.nr_params
);
864 /* For now, set this to non-negative. We'll give it the
865 * actual new number in a moment, in order to keep the
866 * register numbers nicely ordered.
868 this->params_remap
[constant_nr
] = 0;
872 /* Figure out what the new numbers for the params will be. At some
873 * point when we're doing uniform array access, we're going to want
874 * to keep the distinction between .reg and .reg_offset, but for
877 unsigned int new_nr_params
= 0;
878 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
879 if (this->params_remap
[i
] != -1) {
880 this->params_remap
[i
] = new_nr_params
++;
884 /* Update the list of params to be uploaded to match our new numbering. */
885 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
886 int remapped
= this->params_remap
[i
];
891 /* We've already done setup_paramvalues_refs() so no need to worry
892 * about param_index and param_offset.
894 c
->prog_data
.param
[remapped
] = c
->prog_data
.param
[i
];
895 c
->prog_data
.param_convert
[remapped
] = c
->prog_data
.param_convert
[i
];
898 c
->prog_data
.nr_params
= new_nr_params
;
900 /* This should have been generated in the 8-wide pass already. */
901 assert(this->params_remap
);
904 /* Now do the renumbering of the shader to remove unused params. */
905 foreach_list(node
, &this->instructions
) {
906 fs_inst
*inst
= (fs_inst
*)node
;
908 for (int i
= 0; i
< 3; i
++) {
909 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
911 if (inst
->src
[i
].file
!= UNIFORM
)
914 assert(this->params_remap
[constant_nr
] != -1);
915 inst
->src
[i
].reg
= this->params_remap
[constant_nr
];
916 inst
->src
[i
].reg_offset
= 0;
924 * Choose accesses from the UNIFORM file to demote to using the pull
927 * We allow a fragment shader to have more than the specified minimum
928 * maximum number of fragment shader uniform components (64). If
929 * there are too many of these, they'd fill up all of register space.
930 * So, this will push some of them out to the pull constant buffer and
931 * update the program to load them.
934 fs_visitor::setup_pull_constants()
936 /* Only allow 16 registers (128 uniform components) as push constants. */
937 unsigned int max_uniform_components
= 16 * 8;
938 if (c
->prog_data
.nr_params
<= max_uniform_components
)
941 if (c
->dispatch_width
== 16) {
942 fail("Pull constants not supported in 16-wide\n");
946 /* Just demote the end of the list. We could probably do better
947 * here, demoting things that are rarely used in the program first.
949 int pull_uniform_base
= max_uniform_components
;
950 int pull_uniform_count
= c
->prog_data
.nr_params
- pull_uniform_base
;
952 foreach_list(node
, &this->instructions
) {
953 fs_inst
*inst
= (fs_inst
*)node
;
955 for (int i
= 0; i
< 3; i
++) {
956 if (inst
->src
[i
].file
!= UNIFORM
)
959 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
960 if (uniform_nr
< pull_uniform_base
)
963 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
964 fs_inst
*pull
= new(mem_ctx
) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
966 pull
->offset
= ((uniform_nr
- pull_uniform_base
) * 4) & ~15;
968 pull
->annotation
= inst
->annotation
;
972 inst
->insert_before(pull
);
974 inst
->src
[i
].file
= GRF
;
975 inst
->src
[i
].reg
= dst
.reg
;
976 inst
->src
[i
].reg_offset
= 0;
977 inst
->src
[i
].smear
= (uniform_nr
- pull_uniform_base
) & 3;
981 for (int i
= 0; i
< pull_uniform_count
; i
++) {
982 c
->prog_data
.pull_param
[i
] = c
->prog_data
.param
[pull_uniform_base
+ i
];
983 c
->prog_data
.pull_param_convert
[i
] =
984 c
->prog_data
.param_convert
[pull_uniform_base
+ i
];
986 c
->prog_data
.nr_params
-= pull_uniform_count
;
987 c
->prog_data
.nr_pull_params
= pull_uniform_count
;
991 * Attempts to move immediate constants into the immediate
992 * constant slot of following instructions.
994 * Immediate constants are a bit tricky -- they have to be in the last
995 * operand slot, you can't do abs/negate on them,
999 fs_visitor::propagate_constants()
1001 bool progress
= false;
1003 calculate_live_intervals();
1005 foreach_list(node
, &this->instructions
) {
1006 fs_inst
*inst
= (fs_inst
*)node
;
1008 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1010 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
1011 inst
->dst
.type
!= inst
->src
[0].type
||
1012 (c
->dispatch_width
== 16 &&
1013 (inst
->force_uncompressed
|| inst
->force_sechalf
)))
1016 /* Don't bother with cases where we should have had the
1017 * operation on the constant folded in GLSL already.
1022 /* Found a move of a constant to a GRF. Find anything else using the GRF
1023 * before it's written, and replace it with the constant if we can.
1025 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->next
;
1026 !scan_inst
->is_tail_sentinel();
1027 scan_inst
= (fs_inst
*)scan_inst
->next
) {
1028 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
1029 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
1030 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
1031 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
1035 for (int i
= 2; i
>= 0; i
--) {
1036 if (scan_inst
->src
[i
].file
!= GRF
||
1037 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
1038 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
1041 /* Don't bother with cases where we should have had the
1042 * operation on the constant folded in GLSL already.
1044 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
1047 switch (scan_inst
->opcode
) {
1048 case BRW_OPCODE_MOV
:
1049 scan_inst
->src
[i
] = inst
->src
[0];
1053 case BRW_OPCODE_MUL
:
1054 case BRW_OPCODE_ADD
:
1056 scan_inst
->src
[i
] = inst
->src
[0];
1058 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
1059 /* Fit this constant in by commuting the operands.
1060 * Exception: we can't do this for 32-bit integer MUL
1061 * because it's asymmetric.
1063 if (scan_inst
->opcode
== BRW_OPCODE_MUL
&&
1064 (scan_inst
->src
[1].type
== BRW_REGISTER_TYPE_D
||
1065 scan_inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
))
1067 scan_inst
->src
[0] = scan_inst
->src
[1];
1068 scan_inst
->src
[1] = inst
->src
[0];
1073 case BRW_OPCODE_CMP
:
1076 scan_inst
->src
[i
] = inst
->src
[0];
1078 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
1081 new_cmod
= brw_swap_cmod(scan_inst
->conditional_mod
);
1082 if (new_cmod
!= ~0u) {
1083 /* Fit this constant in by swapping the operands and
1086 scan_inst
->src
[0] = scan_inst
->src
[1];
1087 scan_inst
->src
[1] = inst
->src
[0];
1088 scan_inst
->conditional_mod
= new_cmod
;
1094 case BRW_OPCODE_SEL
:
1096 scan_inst
->src
[i
] = inst
->src
[0];
1098 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
1099 scan_inst
->src
[0] = scan_inst
->src
[1];
1100 scan_inst
->src
[1] = inst
->src
[0];
1102 /* If this was predicated, flipping operands means
1103 * we also need to flip the predicate.
1105 if (scan_inst
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
1106 scan_inst
->predicate_inverse
=
1107 !scan_inst
->predicate_inverse
;
1113 case SHADER_OPCODE_RCP
:
1114 /* The hardware doesn't do math on immediate values
1115 * (because why are you doing that, seriously?), but
1116 * the correct answer is to just constant fold it
1120 if (inst
->src
[0].imm
.f
!= 0.0f
) {
1121 scan_inst
->opcode
= BRW_OPCODE_MOV
;
1122 scan_inst
->src
[0] = inst
->src
[0];
1123 scan_inst
->src
[0].imm
.f
= 1.0f
/ scan_inst
->src
[0].imm
.f
;
1133 if (scan_inst
->dst
.file
== GRF
&&
1134 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
1135 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
1136 scan_inst
->is_tex())) {
1143 this->live_intervals_valid
= false;
1150 * Attempts to move immediate constants into the immediate
1151 * constant slot of following instructions.
1153 * Immediate constants are a bit tricky -- they have to be in the last
1154 * operand slot, you can't do abs/negate on them,
1158 fs_visitor::opt_algebraic()
1160 bool progress
= false;
1162 calculate_live_intervals();
1164 foreach_list(node
, &this->instructions
) {
1165 fs_inst
*inst
= (fs_inst
*)node
;
1167 switch (inst
->opcode
) {
1168 case BRW_OPCODE_MUL
:
1169 if (inst
->src
[1].file
!= IMM
)
1173 if (inst
->src
[1].type
== BRW_REGISTER_TYPE_F
&&
1174 inst
->src
[1].imm
.f
== 1.0) {
1175 inst
->opcode
= BRW_OPCODE_MOV
;
1176 inst
->src
[1] = reg_undef
;
1191 * Must be called after calculate_live_intervales() to remove unused
1192 * writes to registers -- register allocation will fail otherwise
1193 * because something deffed but not used won't be considered to
1194 * interfere with other regs.
1197 fs_visitor::dead_code_eliminate()
1199 bool progress
= false;
1202 calculate_live_intervals();
1204 foreach_list_safe(node
, &this->instructions
) {
1205 fs_inst
*inst
= (fs_inst
*)node
;
1207 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
1216 live_intervals_valid
= false;
1222 fs_visitor::register_coalesce()
1224 bool progress
= false;
1228 foreach_list_safe(node
, &this->instructions
) {
1229 fs_inst
*inst
= (fs_inst
*)node
;
1231 /* Make sure that we dominate the instructions we're going to
1232 * scan for interfering with our coalescing, or we won't have
1233 * scanned enough to see if anything interferes with our
1234 * coalescing. We don't dominate the following instructions if
1235 * we're in a loop or an if block.
1237 switch (inst
->opcode
) {
1241 case BRW_OPCODE_WHILE
:
1247 case BRW_OPCODE_ENDIF
:
1253 if (loop_depth
|| if_depth
)
1256 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1259 inst
->dst
.file
!= GRF
|| (inst
->src
[0].file
!= GRF
&&
1260 inst
->src
[0].file
!= UNIFORM
)||
1261 inst
->dst
.type
!= inst
->src
[0].type
)
1264 bool has_source_modifiers
= inst
->src
[0].abs
|| inst
->src
[0].negate
;
1266 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
1267 * them: check for no writes to either one until the exit of the
1270 bool interfered
= false;
1272 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->next
;
1273 !scan_inst
->is_tail_sentinel();
1274 scan_inst
= (fs_inst
*)scan_inst
->next
) {
1275 if (scan_inst
->dst
.file
== GRF
) {
1276 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
1277 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
1278 scan_inst
->is_tex())) {
1282 if (inst
->src
[0].file
== GRF
&&
1283 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1284 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
1285 scan_inst
->is_tex())) {
1291 /* The gen6 MATH instruction can't handle source modifiers or
1292 * unusual register regions, so avoid coalescing those for
1293 * now. We should do something more specific.
1295 if (intel
->gen
>= 6 &&
1296 scan_inst
->is_math() &&
1297 (has_source_modifiers
|| inst
->src
[0].file
== UNIFORM
)) {
1302 /* The accumulator result appears to get used for the
1303 * conditional modifier generation. When negating a UD
1304 * value, there is a 33rd bit generated for the sign in the
1305 * accumulator value, so now you can't check, for example,
1306 * equality with a 32-bit value. See piglit fs-op-neg-uint.
1308 if (scan_inst
->conditional_mod
&&
1309 inst
->src
[0].negate
&&
1310 inst
->src
[0].type
== BRW_REGISTER_TYPE_UD
) {
1319 /* Rewrite the later usage to point at the source of the move to
1322 for (fs_inst
*scan_inst
= inst
;
1323 !scan_inst
->is_tail_sentinel();
1324 scan_inst
= (fs_inst
*)scan_inst
->next
) {
1325 for (int i
= 0; i
< 3; i
++) {
1326 if (scan_inst
->src
[i
].file
== GRF
&&
1327 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
1328 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
1329 fs_reg new_src
= inst
->src
[0];
1330 if (scan_inst
->src
[i
].abs
) {
1334 new_src
.negate
^= scan_inst
->src
[i
].negate
;
1335 scan_inst
->src
[i
] = new_src
;
1345 live_intervals_valid
= false;
1352 fs_visitor::compute_to_mrf()
1354 bool progress
= false;
1357 calculate_live_intervals();
1359 foreach_list_safe(node
, &this->instructions
) {
1360 fs_inst
*inst
= (fs_inst
*)node
;
1365 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1367 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
1368 inst
->dst
.type
!= inst
->src
[0].type
||
1369 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
1372 /* Work out which hardware MRF registers are written by this
1375 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
1377 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
1378 mrf_high
= mrf_low
+ 4;
1379 } else if (c
->dispatch_width
== 16 &&
1380 (!inst
->force_uncompressed
&& !inst
->force_sechalf
)) {
1381 mrf_high
= mrf_low
+ 1;
1386 /* Can't compute-to-MRF this GRF if someone else was going to
1389 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
1392 /* Found a move of a GRF to a MRF. Let's see if we can go
1393 * rewrite the thing that made this GRF to write into the MRF.
1396 for (scan_inst
= (fs_inst
*)inst
->prev
;
1397 scan_inst
->prev
!= NULL
;
1398 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
1399 if (scan_inst
->dst
.file
== GRF
&&
1400 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
1401 /* Found the last thing to write our reg we want to turn
1402 * into a compute-to-MRF.
1405 if (scan_inst
->is_tex()) {
1406 /* texturing writes several continuous regs, so we can't
1407 * compute-to-mrf that.
1412 /* If it's predicated, it (probably) didn't populate all
1413 * the channels. We might be able to rewrite everything
1414 * that writes that reg, but it would require smarter
1415 * tracking to delay the rewriting until complete success.
1417 if (scan_inst
->predicated
)
1420 /* If it's half of register setup and not the same half as
1421 * our MOV we're trying to remove, bail for now.
1423 if (scan_inst
->force_uncompressed
!= inst
->force_uncompressed
||
1424 scan_inst
->force_sechalf
!= inst
->force_sechalf
) {
1428 /* SEND instructions can't have MRF as a destination. */
1429 if (scan_inst
->mlen
)
1432 if (intel
->gen
>= 6) {
1433 /* gen6 math instructions must have the destination be
1434 * GRF, so no compute-to-MRF for them.
1436 if (scan_inst
->is_math()) {
1441 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1442 /* Found the creator of our MRF's source value. */
1443 scan_inst
->dst
.file
= MRF
;
1444 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1445 scan_inst
->saturate
|= inst
->saturate
;
1452 /* We don't handle flow control here. Most computation of
1453 * values that end up in MRFs are shortly before the MRF
1456 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
1457 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
1458 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
1459 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
1463 /* You can't read from an MRF, so if someone else reads our
1464 * MRF's source GRF that we wanted to rewrite, that stops us.
1466 bool interfered
= false;
1467 for (int i
= 0; i
< 3; i
++) {
1468 if (scan_inst
->src
[i
].file
== GRF
&&
1469 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
1470 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1477 if (scan_inst
->dst
.file
== MRF
) {
1478 /* If somebody else writes our MRF here, we can't
1479 * compute-to-MRF before that.
1481 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
1484 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
1485 scan_mrf_high
= scan_mrf_low
+ 4;
1486 } else if (c
->dispatch_width
== 16 &&
1487 (!scan_inst
->force_uncompressed
&&
1488 !scan_inst
->force_sechalf
)) {
1489 scan_mrf_high
= scan_mrf_low
+ 1;
1491 scan_mrf_high
= scan_mrf_low
;
1494 if (mrf_low
== scan_mrf_low
||
1495 mrf_low
== scan_mrf_high
||
1496 mrf_high
== scan_mrf_low
||
1497 mrf_high
== scan_mrf_high
) {
1502 if (scan_inst
->mlen
> 0) {
1503 /* Found a SEND instruction, which means that there are
1504 * live values in MRFs from base_mrf to base_mrf +
1505 * scan_inst->mlen - 1. Don't go pushing our MRF write up
1508 if (mrf_low
>= scan_inst
->base_mrf
&&
1509 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1512 if (mrf_high
>= scan_inst
->base_mrf
&&
1513 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1524 * Walks through basic blocks, looking for repeated MRF writes and
1525 * removing the later ones.
1528 fs_visitor::remove_duplicate_mrf_writes()
1530 fs_inst
*last_mrf_move
[16];
1531 bool progress
= false;
1533 /* Need to update the MRF tracking for compressed instructions. */
1534 if (c
->dispatch_width
== 16)
1537 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
1539 foreach_list_safe(node
, &this->instructions
) {
1540 fs_inst
*inst
= (fs_inst
*)node
;
1542 switch (inst
->opcode
) {
1544 case BRW_OPCODE_WHILE
:
1546 case BRW_OPCODE_ELSE
:
1547 case BRW_OPCODE_ENDIF
:
1548 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
1554 if (inst
->opcode
== BRW_OPCODE_MOV
&&
1555 inst
->dst
.file
== MRF
) {
1556 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
1557 if (prev_inst
&& inst
->equals(prev_inst
)) {
1564 /* Clear out the last-write records for MRFs that were overwritten. */
1565 if (inst
->dst
.file
== MRF
) {
1566 last_mrf_move
[inst
->dst
.reg
] = NULL
;
1569 if (inst
->mlen
> 0) {
1570 /* Found a SEND instruction, which will include two or fewer
1571 * implied MRF writes. We could do better here.
1573 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
1574 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
1578 /* Clear out any MRF move records whose sources got overwritten. */
1579 if (inst
->dst
.file
== GRF
) {
1580 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
1581 if (last_mrf_move
[i
] &&
1582 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
1583 last_mrf_move
[i
] = NULL
;
1588 if (inst
->opcode
== BRW_OPCODE_MOV
&&
1589 inst
->dst
.file
== MRF
&&
1590 inst
->src
[0].file
== GRF
&&
1591 !inst
->predicated
) {
1592 last_mrf_move
[inst
->dst
.reg
] = inst
;
1600 * Possibly returns an instruction that set up @param reg.
1602 * Sometimes we want to take the result of some expression/variable
1603 * dereference tree and rewrite the instruction generating the result
1604 * of the tree. When processing the tree, we know that the
1605 * instructions generated are all writing temporaries that are dead
1606 * outside of this tree. So, if we have some instructions that write
1607 * a temporary, we're free to point that temp write somewhere else.
1609 * Note that this doesn't guarantee that the instruction generated
1610 * only reg -- it might be the size=4 destination of a texture instruction.
1613 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
1619 end
->force_uncompressed
||
1620 end
->force_sechalf
||
1621 !reg
.equals(end
->dst
)) {
1631 uint32_t prog_offset_16
= 0;
1632 uint32_t orig_nr_params
= c
->prog_data
.nr_params
;
1634 brw_wm_payload_setup(brw
, c
);
1636 if (c
->dispatch_width
== 16) {
1637 /* align to 64 byte boundary. */
1638 while ((c
->func
.nr_insn
* sizeof(struct brw_instruction
)) % 64) {
1642 /* Save off the start of this 16-wide program in case we succeed. */
1643 prog_offset_16
= c
->func
.nr_insn
* sizeof(struct brw_instruction
);
1645 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1651 calculate_urb_setup();
1653 emit_interpolation_setup_gen4();
1655 emit_interpolation_setup_gen6();
1657 /* Generate FS IR for main(). (the visitor only descends into
1658 * functions called "main").
1660 foreach_list(node
, &*shader
->ir
) {
1661 ir_instruction
*ir
= (ir_instruction
*)node
;
1663 this->result
= reg_undef
;
1671 split_virtual_grfs();
1673 setup_paramvalues_refs();
1674 setup_pull_constants();
1680 progress
= remove_duplicate_mrf_writes() || progress
;
1682 progress
= propagate_constants() || progress
;
1683 progress
= opt_algebraic() || progress
;
1684 progress
= register_coalesce() || progress
;
1685 progress
= compute_to_mrf() || progress
;
1686 progress
= dead_code_eliminate() || progress
;
1689 remove_dead_constants();
1691 schedule_instructions();
1693 assign_curb_setup();
1697 /* Debug of register spilling: Go spill everything. */
1698 int virtual_grf_count
= virtual_grf_next
;
1699 for (int i
= 0; i
< virtual_grf_count
; i
++) {
1705 assign_regs_trivial();
1707 while (!assign_regs()) {
1713 assert(force_uncompressed_stack
== 0);
1714 assert(force_sechalf_stack
== 0);
1721 if (c
->dispatch_width
== 8) {
1722 c
->prog_data
.reg_blocks
= brw_register_blocks(grf_used
);
1724 c
->prog_data
.reg_blocks_16
= brw_register_blocks(grf_used
);
1725 c
->prog_data
.prog_offset_16
= prog_offset_16
;
1727 /* Make sure we didn't try to sneak in an extra uniform */
1728 assert(orig_nr_params
== c
->prog_data
.nr_params
);
1729 (void) orig_nr_params
;
1736 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
,
1737 struct gl_shader_program
*prog
)
1739 struct intel_context
*intel
= &brw
->intel
;
1744 struct brw_shader
*shader
=
1745 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
1749 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1750 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
1751 _mesa_print_ir(shader
->ir
, NULL
);
1755 /* Now the main event: Visit the shader IR and generate our FS IR for it.
1757 c
->dispatch_width
= 8;
1759 fs_visitor
v(c
, prog
, shader
);
1761 prog
->LinkStatus
= false;
1762 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1764 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
1770 if (intel
->gen
>= 5 && c
->prog_data
.nr_pull_params
== 0) {
1771 c
->dispatch_width
= 16;
1772 fs_visitor
v2(c
, prog
, shader
);
1773 v2
.import_uniforms(&v
);
1777 c
->prog_data
.dispatch_width
= 8;
1783 brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
1785 struct brw_context
*brw
= brw_context(ctx
);
1786 struct brw_wm_prog_key key
;
1788 if (!prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
])
1791 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)
1792 prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
]->Program
;
1793 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
1795 memset(&key
, 0, sizeof(key
));
1798 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
1800 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
1801 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
1803 /* Just assume depth testing. */
1804 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
1805 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
1807 key
.vp_outputs_written
|= BITFIELD64_BIT(FRAG_ATTRIB_WPOS
);
1808 for (int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
1809 if (!(fp
->Base
.InputsRead
& BITFIELD64_BIT(i
)))
1812 key
.proj_attrib_mask
|= 1 << i
;
1814 int vp_index
= _mesa_vert_result_to_frag_attrib((gl_vert_result
) i
);
1817 key
.vp_outputs_written
|= BITFIELD64_BIT(vp_index
);
1820 key
.clamp_fragment_color
= true;
1822 for (int i
= 0; i
< BRW_MAX_TEX_UNIT
; i
++) {
1823 if (fp
->Base
.ShadowSamplers
& (1 << i
))
1824 key
.tex
.compare_funcs
[i
] = GL_LESS
;
1826 /* FINISHME: depth compares might use (0,0,0,W) for example */
1827 key
.tex
.swizzles
[i
] = SWIZZLE_XYZW
;
1830 if (fp
->Base
.InputsRead
& FRAG_BIT_WPOS
) {
1831 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
1832 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
1835 key
.nr_color_regions
= 1;
1837 key
.program_string_id
= bfp
->id
;
1839 uint32_t old_prog_offset
= brw
->wm
.prog_offset
;
1840 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
1842 bool success
= do_wm_prog(brw
, prog
, bfp
, &key
);
1844 brw
->wm
.prog_offset
= old_prog_offset
;
1845 brw
->wm
.prog_data
= old_prog_data
;