2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "../glsl/glsl_types.h"
47 #include "../glsl/ir_optimization.h"
48 #include "../glsl/ir_print_visitor.h"
51 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
52 GRF
= BRW_GENERAL_REGISTER_FILE
,
53 MRF
= BRW_MESSAGE_REGISTER_FILE
,
54 IMM
= BRW_IMMEDIATE_VALUE
,
55 FIXED_HW_REG
, /* a struct brw_reg */
56 UNIFORM
, /* prog_data->params[hw_reg] */
61 FS_OPCODE_FB_WRITE
= 256,
79 static int using_new_fs
= -1;
80 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
83 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
85 struct brw_shader
*shader
;
87 shader
= talloc_zero(NULL
, struct brw_shader
);
89 shader
->base
.Type
= type
;
90 shader
->base
.Name
= name
;
91 _mesa_init_shader(ctx
, &shader
->base
);
97 struct gl_shader_program
*
98 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
100 struct brw_shader_program
*prog
;
101 prog
= talloc_zero(NULL
, struct brw_shader_program
);
103 prog
->base
.Name
= name
;
104 _mesa_init_shader_program(ctx
, &prog
->base
);
110 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
112 if (!_mesa_ir_compile_shader(ctx
, shader
))
119 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
121 if (using_new_fs
== -1)
122 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
124 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
125 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
127 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
128 void *mem_ctx
= talloc_new(NULL
);
132 talloc_free(shader
->ir
);
133 shader
->ir
= new(shader
) exec_list
;
134 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
136 do_mat_op_to_vec(shader
->ir
);
137 do_mod_to_fract(shader
->ir
);
138 do_div_to_mul_rcp(shader
->ir
);
139 do_sub_to_add_neg(shader
->ir
);
140 do_explog_to_explog2(shader
->ir
);
141 do_lower_texture_projection(shader
->ir
);
146 brw_do_channel_expressions(shader
->ir
);
147 brw_do_vector_splitting(shader
->ir
);
149 progress
= do_lower_jumps(shader
->ir
, true, true,
150 true, /* main return */
151 false, /* continue */
155 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
157 progress
= lower_noise(shader
->ir
) || progress
;
159 lower_variable_index_to_cond_assign(shader
->ir
,
161 GL_TRUE
, /* output */
163 GL_TRUE
/* uniform */
167 validate_ir_tree(shader
->ir
);
169 reparent_ir(shader
->ir
, shader
->ir
);
170 talloc_free(mem_ctx
);
174 if (!_mesa_ir_link_shader(ctx
, prog
))
181 type_size(const struct glsl_type
*type
)
183 unsigned int size
, i
;
185 switch (type
->base_type
) {
188 case GLSL_TYPE_FLOAT
:
190 return type
->components();
191 case GLSL_TYPE_ARRAY
:
192 return type_size(type
->fields
.array
) * type
->length
;
193 case GLSL_TYPE_STRUCT
:
195 for (i
= 0; i
< type
->length
; i
++) {
196 size
+= type_size(type
->fields
.structure
[i
].type
);
199 case GLSL_TYPE_SAMPLER
:
200 /* Samplers take up no register space, since they're baked in at
205 assert(!"not reached");
212 /* Callers of this talloc-based new need not call delete. It's
213 * easier to just talloc_free 'ctx' (or any of its ancestors). */
214 static void* operator new(size_t size
, void *ctx
)
218 node
= talloc_size(ctx
, size
);
219 assert(node
!= NULL
);
227 this->reg_offset
= 0;
233 /** Generic unset register constructor. */
237 this->file
= BAD_FILE
;
240 /** Immediate value constructor. */
245 this->type
= BRW_REGISTER_TYPE_F
;
249 /** Immediate value constructor. */
254 this->type
= BRW_REGISTER_TYPE_D
;
258 /** Immediate value constructor. */
263 this->type
= BRW_REGISTER_TYPE_UD
;
267 /** Fixed brw_reg Immediate value constructor. */
268 fs_reg(struct brw_reg fixed_hw_reg
)
271 this->file
= FIXED_HW_REG
;
272 this->fixed_hw_reg
= fixed_hw_reg
;
273 this->type
= fixed_hw_reg
.type
;
276 fs_reg(enum register_file file
, int hw_reg
);
277 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
279 /** Register file: ARF, GRF, MRF, IMM. */
280 enum register_file file
;
281 /** virtual register number. 0 = fixed hw reg */
283 /** Offset within the virtual register. */
285 /** HW register number. Generally unset until register allocation. */
287 /** Register type. BRW_REGISTER_TYPE_* */
291 struct brw_reg fixed_hw_reg
;
293 /** Value for file == BRW_IMMMEDIATE_FILE */
301 static const fs_reg reg_undef
;
302 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
304 class fs_inst
: public exec_node
{
306 /* Callers of this talloc-based new need not call delete. It's
307 * easier to just talloc_free 'ctx' (or any of its ancestors). */
308 static void* operator new(size_t size
, void *ctx
)
312 node
= talloc_zero_size(ctx
, size
);
313 assert(node
!= NULL
);
320 this->opcode
= BRW_OPCODE_NOP
;
321 this->saturate
= false;
322 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
323 this->predicated
= false;
327 this->header_present
= false;
328 this->shadow_compare
= false;
339 this->opcode
= opcode
;
342 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
)
345 this->opcode
= opcode
;
350 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
353 this->opcode
= opcode
;
359 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg src2
)
362 this->opcode
= opcode
;
369 int opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
374 int conditional_mod
; /**< BRW_CONDITIONAL_* */
376 int mlen
; /**< SEND message length */
378 int target
; /**< MRT target. */
384 * Annotation for the generated IR. One of the two can be set.
387 const char *annotation
;
391 class fs_visitor
: public ir_visitor
395 fs_visitor(struct brw_wm_compile
*c
, struct brw_shader
*shader
)
400 this->fp
= brw
->fragment_program
;
401 this->intel
= &brw
->intel
;
402 this->ctx
= &intel
->ctx
;
403 this->mem_ctx
= talloc_new(NULL
);
404 this->shader
= shader
;
406 this->variable_ht
= hash_table_ctor(0,
407 hash_table_pointer_hash
,
408 hash_table_pointer_compare
);
410 this->frag_color
= NULL
;
411 this->frag_data
= NULL
;
412 this->frag_depth
= NULL
;
413 this->first_non_payload_grf
= 0;
415 this->current_annotation
= NULL
;
416 this->annotation_string
= NULL
;
417 this->annotation_ir
= NULL
;
418 this->base_ir
= NULL
;
420 this->virtual_grf_sizes
= NULL
;
421 this->virtual_grf_next
= 1;
422 this->virtual_grf_array_size
= 0;
423 this->virtual_grf_def
= NULL
;
424 this->virtual_grf_use
= NULL
;
426 this->kill_emitted
= false;
431 talloc_free(this->mem_ctx
);
432 hash_table_dtor(this->variable_ht
);
435 fs_reg
*variable_storage(ir_variable
*var
);
436 int virtual_grf_alloc(int size
);
438 void visit(ir_variable
*ir
);
439 void visit(ir_assignment
*ir
);
440 void visit(ir_dereference_variable
*ir
);
441 void visit(ir_dereference_record
*ir
);
442 void visit(ir_dereference_array
*ir
);
443 void visit(ir_expression
*ir
);
444 void visit(ir_texture
*ir
);
445 void visit(ir_if
*ir
);
446 void visit(ir_constant
*ir
);
447 void visit(ir_swizzle
*ir
);
448 void visit(ir_return
*ir
);
449 void visit(ir_loop
*ir
);
450 void visit(ir_loop_jump
*ir
);
451 void visit(ir_discard
*ir
);
452 void visit(ir_call
*ir
);
453 void visit(ir_function
*ir
);
454 void visit(ir_function_signature
*ir
);
456 fs_inst
*emit(fs_inst inst
);
457 void assign_curb_setup();
458 void calculate_urb_setup();
459 void assign_urb_setup();
461 void assign_regs_trivial();
462 void calculate_live_intervals();
463 bool propagate_constants();
464 bool dead_code_eliminate();
465 bool virtual_grf_interferes(int a
, int b
);
466 void generate_code();
467 void generate_fb_write(fs_inst
*inst
);
468 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
469 struct brw_reg
*src
);
470 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
471 void generate_math(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg
*src
);
472 void generate_discard(fs_inst
*inst
, struct brw_reg temp
);
473 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
474 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
476 void emit_dummy_fs();
477 fs_reg
*emit_fragcoord_interpolation(ir_variable
*ir
);
478 fs_reg
*emit_frontfacing_interpolation(ir_variable
*ir
);
479 fs_reg
*emit_general_interpolation(ir_variable
*ir
);
480 void emit_interpolation_setup_gen4();
481 void emit_interpolation_setup_gen6();
482 fs_inst
*emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
);
483 fs_inst
*emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
);
484 void emit_fb_writes();
485 void emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
486 const glsl_type
*type
, bool predicated
);
488 struct brw_reg
interp_reg(int location
, int channel
);
489 int setup_uniform_values(int loc
, const glsl_type
*type
);
490 void setup_builtin_uniform_values(ir_variable
*ir
);
492 struct brw_context
*brw
;
493 const struct gl_fragment_program
*fp
;
494 struct intel_context
*intel
;
496 struct brw_wm_compile
*c
;
497 struct brw_compile
*p
;
498 struct brw_shader
*shader
;
500 exec_list instructions
;
502 int *virtual_grf_sizes
;
503 int virtual_grf_next
;
504 int virtual_grf_array_size
;
505 int *virtual_grf_def
;
506 int *virtual_grf_use
;
508 struct hash_table
*variable_ht
;
509 ir_variable
*frag_color
, *frag_data
, *frag_depth
;
510 int first_non_payload_grf
;
511 int urb_setup
[FRAG_ATTRIB_MAX
];
514 /** @{ debug annotation info */
515 const char *current_annotation
;
516 ir_instruction
*base_ir
;
517 const char **annotation_string
;
518 ir_instruction
**annotation_ir
;
523 /* Result of last visit() method. */
538 fs_visitor::virtual_grf_alloc(int size
)
540 if (virtual_grf_array_size
<= virtual_grf_next
) {
541 if (virtual_grf_array_size
== 0)
542 virtual_grf_array_size
= 16;
544 virtual_grf_array_size
*= 2;
545 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
546 int, virtual_grf_array_size
);
548 /* This slot is always unused. */
549 virtual_grf_sizes
[0] = 0;
551 virtual_grf_sizes
[virtual_grf_next
] = size
;
552 return virtual_grf_next
++;
555 /** Fixed HW reg constructor. */
556 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
560 this->hw_reg
= hw_reg
;
561 this->type
= BRW_REGISTER_TYPE_F
;
565 brw_type_for_base_type(const struct glsl_type
*type
)
567 switch (type
->base_type
) {
568 case GLSL_TYPE_FLOAT
:
569 return BRW_REGISTER_TYPE_F
;
572 return BRW_REGISTER_TYPE_D
;
574 return BRW_REGISTER_TYPE_UD
;
575 case GLSL_TYPE_ARRAY
:
576 case GLSL_TYPE_STRUCT
:
577 /* These should be overridden with the type of the member when
578 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
579 * way to trip up if we don't.
581 return BRW_REGISTER_TYPE_UD
;
583 assert(!"not reached");
584 return BRW_REGISTER_TYPE_F
;
588 /** Automatic reg constructor. */
589 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
594 this->reg
= v
->virtual_grf_alloc(type_size(type
));
595 this->reg_offset
= 0;
596 this->type
= brw_type_for_base_type(type
);
600 fs_visitor::variable_storage(ir_variable
*var
)
602 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
605 /* Our support for uniforms is piggy-backed on the struct
606 * gl_fragment_program, because that's where the values actually
607 * get stored, rather than in some global gl_shader_program uniform
611 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
613 unsigned int offset
= 0;
616 if (type
->is_matrix()) {
617 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
618 type
->vector_elements
,
621 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
622 offset
+= setup_uniform_values(loc
+ offset
, column
);
628 switch (type
->base_type
) {
629 case GLSL_TYPE_FLOAT
:
633 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
634 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
635 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
639 case GLSL_TYPE_STRUCT
:
640 for (unsigned int i
= 0; i
< type
->length
; i
++) {
641 offset
+= setup_uniform_values(loc
+ offset
,
642 type
->fields
.structure
[i
].type
);
646 case GLSL_TYPE_ARRAY
:
647 for (unsigned int i
= 0; i
< type
->length
; i
++) {
648 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
652 case GLSL_TYPE_SAMPLER
:
653 /* The sampler takes up a slot, but we don't use any values from it. */
657 assert(!"not reached");
663 /* Our support for builtin uniforms is even scarier than non-builtin.
664 * It sits on top of the PROG_STATE_VAR parameters that are
665 * automatically updated from GL context state.
668 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
670 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
672 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
673 statevar
= &_mesa_builtin_uniform_desc
[i
];
674 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
678 if (!statevar
->name
) {
680 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
685 if (ir
->type
->is_array()) {
686 array_count
= ir
->type
->length
;
691 for (int a
= 0; a
< array_count
; a
++) {
692 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
693 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
694 int tokens
[STATE_LENGTH
];
696 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
697 if (ir
->type
->is_array()) {
701 /* This state reference has already been setup by ir_to_mesa,
702 * but we'll get the same index back here.
704 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
705 (gl_state_index
*)tokens
);
706 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
708 /* Add each of the unique swizzles of the element as a
709 * parameter. This'll end up matching the expected layout of
710 * the array/matrix/structure we're trying to fill in.
713 for (unsigned int i
= 0; i
< 4; i
++) {
714 int swiz
= GET_SWZ(element
->swizzle
, i
);
715 if (swiz
== last_swiz
)
719 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
726 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
728 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
730 fs_reg neg_y
= this->pixel_y
;
734 if (ir
->pixel_center_integer
) {
735 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
737 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
742 if (ir
->origin_upper_left
&& ir
->pixel_center_integer
) {
743 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
745 fs_reg pixel_y
= this->pixel_y
;
746 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
748 if (!ir
->origin_upper_left
) {
749 pixel_y
.negate
= true;
750 offset
+= c
->key
.drawable_height
- 1.0;
753 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
758 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
759 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
762 /* gl_FragCoord.w: Already set up in emit_interpolation */
763 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
769 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
771 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
772 /* Interpolation is always in floating point regs. */
773 reg
->type
= BRW_REGISTER_TYPE_F
;
776 unsigned int array_elements
;
777 const glsl_type
*type
;
779 if (ir
->type
->is_array()) {
780 array_elements
= ir
->type
->length
;
781 if (array_elements
== 0) {
784 type
= ir
->type
->fields
.array
;
790 int location
= ir
->location
;
791 for (unsigned int i
= 0; i
< array_elements
; i
++) {
792 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
793 if (urb_setup
[location
] == -1) {
794 /* If there's no incoming setup data for this slot, don't
795 * emit interpolation for it.
797 attr
.reg_offset
+= type
->vector_elements
;
802 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
803 struct brw_reg interp
= interp_reg(location
, c
);
804 emit(fs_inst(FS_OPCODE_LINTERP
,
811 attr
.reg_offset
-= type
->vector_elements
;
813 if (intel
->gen
< 6) {
814 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
815 emit(fs_inst(BRW_OPCODE_MUL
,
830 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
832 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
833 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
834 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
837 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
841 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
842 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
848 fs_visitor::visit(ir_variable
*ir
)
852 if (variable_storage(ir
))
855 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
856 this->frag_color
= ir
;
857 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
858 this->frag_data
= ir
;
859 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
860 this->frag_depth
= ir
;
863 if (ir
->mode
== ir_var_in
) {
864 if (!strcmp(ir
->name
, "gl_FragCoord")) {
865 reg
= emit_fragcoord_interpolation(ir
);
866 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
867 reg
= emit_frontfacing_interpolation(ir
);
869 reg
= emit_general_interpolation(ir
);
872 hash_table_insert(this->variable_ht
, reg
, ir
);
876 if (ir
->mode
== ir_var_uniform
) {
877 int param_index
= c
->prog_data
.nr_params
;
879 if (!strncmp(ir
->name
, "gl_", 3)) {
880 setup_builtin_uniform_values(ir
);
882 setup_uniform_values(ir
->location
, ir
->type
);
885 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
889 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
891 hash_table_insert(this->variable_ht
, reg
, ir
);
895 fs_visitor::visit(ir_dereference_variable
*ir
)
897 fs_reg
*reg
= variable_storage(ir
->var
);
902 fs_visitor::visit(ir_dereference_record
*ir
)
904 const glsl_type
*struct_type
= ir
->record
->type
;
906 ir
->record
->accept(this);
908 unsigned int offset
= 0;
909 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
910 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
912 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
914 this->result
.reg_offset
+= offset
;
915 this->result
.type
= brw_type_for_base_type(ir
->type
);
919 fs_visitor::visit(ir_dereference_array
*ir
)
924 ir
->array
->accept(this);
925 index
= ir
->array_index
->as_constant();
927 element_size
= type_size(ir
->type
);
928 this->result
.type
= brw_type_for_base_type(ir
->type
);
931 assert(this->result
.file
== UNIFORM
||
932 (this->result
.file
== GRF
&&
933 this->result
.reg
!= 0));
934 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
936 assert(!"FINISHME: non-constant array element");
941 fs_visitor::visit(ir_expression
*ir
)
943 unsigned int operand
;
948 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
949 ir
->operands
[operand
]->accept(this);
950 if (this->result
.file
== BAD_FILE
) {
952 printf("Failed to get tree for expression operand:\n");
953 ir
->operands
[operand
]->accept(&v
);
956 op
[operand
] = this->result
;
958 /* Matrix expression operands should have been broken down to vector
959 * operations already.
961 assert(!ir
->operands
[operand
]->type
->is_matrix());
962 /* And then those vector operands should have been broken down to scalar.
964 assert(!ir
->operands
[operand
]->type
->is_vector());
967 /* Storage for our result. If our result goes into an assignment, it will
968 * just get copy-propagated out, so no worries.
970 this->result
= fs_reg(this, ir
->type
);
972 switch (ir
->operation
) {
973 case ir_unop_logic_not
:
974 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
977 op
[0].negate
= !op
[0].negate
;
978 this->result
= op
[0];
982 this->result
= op
[0];
985 temp
= fs_reg(this, ir
->type
);
987 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
989 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
990 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
991 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
992 inst
->predicated
= true;
994 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
995 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
996 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
997 inst
->predicated
= true;
1001 emit(fs_inst(FS_OPCODE_RCP
, this->result
, op
[0]));
1005 emit(fs_inst(FS_OPCODE_EXP2
, this->result
, op
[0]));
1008 emit(fs_inst(FS_OPCODE_LOG2
, this->result
, op
[0]));
1012 assert(!"not reached: should be handled by ir_explog_to_explog2");
1015 emit(fs_inst(FS_OPCODE_SIN
, this->result
, op
[0]));
1018 emit(fs_inst(FS_OPCODE_COS
, this->result
, op
[0]));
1022 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
1025 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
1029 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
1032 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1036 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
1039 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1042 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1046 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1047 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1048 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1050 case ir_binop_greater
:
1051 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1052 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1053 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1055 case ir_binop_lequal
:
1056 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1057 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1058 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1060 case ir_binop_gequal
:
1061 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1062 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1063 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1065 case ir_binop_equal
:
1066 case ir_binop_all_equal
: /* same as nequal for scalars */
1067 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1068 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1069 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1071 case ir_binop_nequal
:
1072 case ir_binop_any_nequal
: /* same as nequal for scalars */
1073 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1074 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1075 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1078 case ir_binop_logic_xor
:
1079 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
1082 case ir_binop_logic_or
:
1083 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
1086 case ir_binop_logic_and
:
1087 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
1091 case ir_binop_cross
:
1093 assert(!"not reached: should be handled by brw_fs_channel_expressions");
1097 assert(!"not reached: should be handled by lower_noise");
1101 emit(fs_inst(FS_OPCODE_SQRT
, this->result
, op
[0]));
1105 emit(fs_inst(FS_OPCODE_RSQ
, this->result
, op
[0]));
1111 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1114 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1118 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
1119 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1122 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1125 op
[0].negate
= ~op
[0].negate
;
1126 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1127 this->result
.negate
= true;
1130 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1133 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
1137 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1138 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1140 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1141 inst
->predicated
= true;
1144 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1145 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1147 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1148 inst
->predicated
= true;
1152 inst
= emit(fs_inst(FS_OPCODE_POW
, this->result
, op
[0], op
[1]));
1155 case ir_unop_bit_not
:
1157 case ir_binop_lshift
:
1158 case ir_binop_rshift
:
1159 case ir_binop_bit_and
:
1160 case ir_binop_bit_xor
:
1161 case ir_binop_bit_or
:
1162 assert(!"GLSL 1.30 features unsupported");
1168 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1169 const glsl_type
*type
, bool predicated
)
1171 switch (type
->base_type
) {
1172 case GLSL_TYPE_FLOAT
:
1173 case GLSL_TYPE_UINT
:
1175 case GLSL_TYPE_BOOL
:
1176 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1177 l
.type
= brw_type_for_base_type(type
);
1178 r
.type
= brw_type_for_base_type(type
);
1180 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1181 inst
->predicated
= predicated
;
1187 case GLSL_TYPE_ARRAY
:
1188 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1189 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1192 case GLSL_TYPE_STRUCT
:
1193 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1194 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1199 case GLSL_TYPE_SAMPLER
:
1203 assert(!"not reached");
1209 fs_visitor::visit(ir_assignment
*ir
)
1214 /* FINISHME: arrays on the lhs */
1215 ir
->lhs
->accept(this);
1218 ir
->rhs
->accept(this);
1221 assert(l
.file
!= BAD_FILE
);
1222 assert(r
.file
!= BAD_FILE
);
1224 if (ir
->condition
) {
1225 /* Get the condition bool into the predicate. */
1226 ir
->condition
->accept(this);
1227 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, this->result
, fs_reg(0)));
1228 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1231 if (ir
->lhs
->type
->is_scalar() ||
1232 ir
->lhs
->type
->is_vector()) {
1233 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1234 if (ir
->write_mask
& (1 << i
)) {
1235 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1237 inst
->predicated
= true;
1243 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1248 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1252 bool simd16
= false;
1255 if (ir
->shadow_comparitor
) {
1256 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1257 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1259 coordinate
.reg_offset
++;
1261 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1264 if (ir
->op
== ir_tex
) {
1265 /* There's no plain shadow compare message, so we use shadow
1266 * compare with a bias of 0.0.
1268 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1271 } else if (ir
->op
== ir_txb
) {
1272 ir
->lod_info
.bias
->accept(this);
1273 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1277 assert(ir
->op
== ir_txl
);
1278 ir
->lod_info
.lod
->accept(this);
1279 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1284 ir
->shadow_comparitor
->accept(this);
1285 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1287 } else if (ir
->op
== ir_tex
) {
1288 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1289 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1291 coordinate
.reg_offset
++;
1293 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1296 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1297 * instructions. We'll need to do SIMD16 here.
1299 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1301 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
* 2;) {
1302 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1304 coordinate
.reg_offset
++;
1307 /* The unused upper half. */
1311 /* lod/bias appears after u/v/r. */
1314 if (ir
->op
== ir_txb
) {
1315 ir
->lod_info
.bias
->accept(this);
1316 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1320 ir
->lod_info
.lod
->accept(this);
1321 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1326 /* The unused upper half. */
1329 /* Now, since we're doing simd16, the return is 2 interleaved
1330 * vec4s where the odd-indexed ones are junk. We'll need to move
1331 * this weirdness around to the expected layout.
1335 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1337 dst
.type
= BRW_REGISTER_TYPE_F
;
1340 fs_inst
*inst
= NULL
;
1343 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
1346 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
1349 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
1353 assert(!"GLSL 1.30 features unsupported");
1359 for (int i
= 0; i
< 4; i
++) {
1360 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1361 orig_dst
.reg_offset
++;
1362 dst
.reg_offset
+= 2;
1370 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1372 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1373 * optional parameters like shadow comparitor or LOD bias. If
1374 * optional parameters aren't present, those base slots are
1375 * optional and don't need to be included in the message.
1377 * We don't fill in the unnecessary slots regardless, which may
1378 * look surprising in the disassembly.
1383 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1384 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1385 coordinate
.reg_offset
++;
1388 if (ir
->shadow_comparitor
) {
1389 mlen
= MAX2(mlen
, 4);
1391 ir
->shadow_comparitor
->accept(this);
1392 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1396 fs_inst
*inst
= NULL
;
1399 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
1402 ir
->lod_info
.bias
->accept(this);
1403 mlen
= MAX2(mlen
, 4);
1404 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1407 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
1410 ir
->lod_info
.lod
->accept(this);
1411 mlen
= MAX2(mlen
, 4);
1412 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1415 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
1419 assert(!"GLSL 1.30 features unsupported");
1428 fs_visitor::visit(ir_texture
*ir
)
1430 fs_inst
*inst
= NULL
;
1432 ir
->coordinate
->accept(this);
1433 fs_reg coordinate
= this->result
;
1435 /* Should be lowered by do_lower_texture_projection */
1436 assert(!ir
->projector
);
1438 /* Writemasking doesn't eliminate channels on SIMD8 texture
1439 * samples, so don't worry about them.
1441 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1443 if (intel
->gen
< 5) {
1444 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1446 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1450 _mesa_get_sampler_uniform_value(ir
->sampler
,
1451 ctx
->Shader
.CurrentProgram
,
1452 &brw
->fragment_program
->Base
);
1453 inst
->sampler
= c
->fp
->program
.Base
.SamplerUnits
[inst
->sampler
];
1457 if (ir
->shadow_comparitor
)
1458 inst
->shadow_compare
= true;
1460 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1461 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1463 for (int i
= 0; i
< 4; i
++) {
1464 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1465 fs_reg l
= swizzle_dst
;
1468 if (swiz
== SWIZZLE_ZERO
) {
1469 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1470 } else if (swiz
== SWIZZLE_ONE
) {
1471 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1474 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1475 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1478 this->result
= swizzle_dst
;
1483 fs_visitor::visit(ir_swizzle
*ir
)
1485 ir
->val
->accept(this);
1486 fs_reg val
= this->result
;
1488 if (ir
->type
->vector_elements
== 1) {
1489 this->result
.reg_offset
+= ir
->mask
.x
;
1493 fs_reg result
= fs_reg(this, ir
->type
);
1494 this->result
= result
;
1496 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1497 fs_reg channel
= val
;
1515 channel
.reg_offset
+= swiz
;
1516 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1517 result
.reg_offset
++;
1522 fs_visitor::visit(ir_discard
*ir
)
1524 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1526 assert(ir
->condition
== NULL
); /* FINISHME */
1528 emit(fs_inst(FS_OPCODE_DISCARD
, temp
, temp
));
1529 kill_emitted
= true;
1533 fs_visitor::visit(ir_constant
*ir
)
1535 fs_reg
reg(this, ir
->type
);
1538 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1539 switch (ir
->type
->base_type
) {
1540 case GLSL_TYPE_FLOAT
:
1541 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1543 case GLSL_TYPE_UINT
:
1544 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1547 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1549 case GLSL_TYPE_BOOL
:
1550 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1553 assert(!"Non-float/uint/int/bool constant");
1560 fs_visitor::visit(ir_if
*ir
)
1564 /* Don't point the annotation at the if statement, because then it plus
1565 * the then and else blocks get printed.
1567 this->base_ir
= ir
->condition
;
1569 /* Generate the condition into the condition code. */
1570 ir
->condition
->accept(this);
1571 inst
= emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(brw_null_reg()), this->result
));
1572 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1574 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1575 inst
->predicated
= true;
1577 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1578 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1584 if (!ir
->else_instructions
.is_empty()) {
1585 emit(fs_inst(BRW_OPCODE_ELSE
));
1587 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1588 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1595 emit(fs_inst(BRW_OPCODE_ENDIF
));
1599 fs_visitor::visit(ir_loop
*ir
)
1601 fs_reg counter
= reg_undef
;
1604 this->base_ir
= ir
->counter
;
1605 ir
->counter
->accept(this);
1606 counter
= *(variable_storage(ir
->counter
));
1609 this->base_ir
= ir
->from
;
1610 ir
->from
->accept(this);
1612 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1616 emit(fs_inst(BRW_OPCODE_DO
));
1619 this->base_ir
= ir
->to
;
1620 ir
->to
->accept(this);
1622 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
,
1623 counter
, this->result
));
1625 case ir_binop_equal
:
1626 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1628 case ir_binop_nequal
:
1629 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1631 case ir_binop_gequal
:
1632 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1634 case ir_binop_lequal
:
1635 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1637 case ir_binop_greater
:
1638 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1641 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1644 assert(!"not reached: unknown loop condition");
1649 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1650 inst
->predicated
= true;
1653 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1654 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1660 if (ir
->increment
) {
1661 this->base_ir
= ir
->increment
;
1662 ir
->increment
->accept(this);
1663 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1666 emit(fs_inst(BRW_OPCODE_WHILE
));
1670 fs_visitor::visit(ir_loop_jump
*ir
)
1673 case ir_loop_jump::jump_break
:
1674 emit(fs_inst(BRW_OPCODE_BREAK
));
1676 case ir_loop_jump::jump_continue
:
1677 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1683 fs_visitor::visit(ir_call
*ir
)
1685 assert(!"FINISHME");
1689 fs_visitor::visit(ir_return
*ir
)
1691 assert(!"FINISHME");
1695 fs_visitor::visit(ir_function
*ir
)
1697 /* Ignore function bodies other than main() -- we shouldn't see calls to
1698 * them since they should all be inlined before we get to ir_to_mesa.
1700 if (strcmp(ir
->name
, "main") == 0) {
1701 const ir_function_signature
*sig
;
1704 sig
= ir
->matching_signature(&empty
);
1708 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1709 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1718 fs_visitor::visit(ir_function_signature
*ir
)
1720 assert(!"not reached");
1725 fs_visitor::emit(fs_inst inst
)
1727 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1730 list_inst
->annotation
= this->current_annotation
;
1731 list_inst
->ir
= this->base_ir
;
1733 this->instructions
.push_tail(list_inst
);
1738 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1740 fs_visitor::emit_dummy_fs()
1742 /* Everyone's favorite color. */
1743 emit(fs_inst(BRW_OPCODE_MOV
,
1746 emit(fs_inst(BRW_OPCODE_MOV
,
1749 emit(fs_inst(BRW_OPCODE_MOV
,
1752 emit(fs_inst(BRW_OPCODE_MOV
,
1757 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1762 /* The register location here is relative to the start of the URB
1763 * data. It will get adjusted to be a real location before
1764 * generate_code() time.
1767 fs_visitor::interp_reg(int location
, int channel
)
1769 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1770 int stride
= (channel
& 1) * 4;
1772 assert(urb_setup
[location
] != -1);
1774 return brw_vec1_grf(regnr
, stride
);
1777 /** Emits the interpolation for the varying inputs. */
1779 fs_visitor::emit_interpolation_setup_gen4()
1781 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1783 this->current_annotation
= "compute pixel centers";
1784 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1785 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1786 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1787 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1788 emit(fs_inst(BRW_OPCODE_ADD
,
1790 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1791 fs_reg(brw_imm_v(0x10101010))));
1792 emit(fs_inst(BRW_OPCODE_ADD
,
1794 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1795 fs_reg(brw_imm_v(0x11001100))));
1797 this->current_annotation
= "compute pixel deltas from v0";
1799 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1800 this->delta_y
= this->delta_x
;
1801 this->delta_y
.reg_offset
++;
1803 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1804 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1806 emit(fs_inst(BRW_OPCODE_ADD
,
1809 fs_reg(negate(brw_vec1_grf(1, 0)))));
1810 emit(fs_inst(BRW_OPCODE_ADD
,
1813 fs_reg(negate(brw_vec1_grf(1, 1)))));
1815 this->current_annotation
= "compute pos.w and 1/pos.w";
1816 /* Compute wpos.w. It's always in our setup, since it's needed to
1817 * interpolate the other attributes.
1819 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1820 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1821 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1822 /* Compute the pixel 1/W value from wpos.w. */
1823 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1824 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
));
1825 this->current_annotation
= NULL
;
1828 /** Emits the interpolation for the varying inputs. */
1830 fs_visitor::emit_interpolation_setup_gen6()
1832 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1834 /* If the pixel centers end up used, the setup is the same as for gen4. */
1835 this->current_annotation
= "compute pixel centers";
1836 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1837 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1838 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1839 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1840 emit(fs_inst(BRW_OPCODE_ADD
,
1842 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1843 fs_reg(brw_imm_v(0x10101010))));
1844 emit(fs_inst(BRW_OPCODE_ADD
,
1846 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1847 fs_reg(brw_imm_v(0x11001100))));
1849 this->current_annotation
= "compute 1/pos.w";
1850 this->wpos_w
= fs_reg(brw_vec8_grf(c
->key
.source_w_reg
, 0));
1851 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1852 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
));
1854 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1855 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1857 this->current_annotation
= NULL
;
1861 fs_visitor::emit_fb_writes()
1863 this->current_annotation
= "FB write header";
1864 GLboolean header_present
= GL_TRUE
;
1867 if (intel
->gen
>= 6 &&
1868 !this->kill_emitted
&&
1869 c
->key
.nr_color_regions
== 1) {
1870 header_present
= false;
1873 if (header_present
) {
1878 if (c
->key
.aa_dest_stencil_reg
) {
1879 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1880 fs_reg(brw_vec8_grf(c
->key
.aa_dest_stencil_reg
, 0))));
1883 /* Reserve space for color. It'll be filled in per MRT below. */
1887 if (c
->key
.source_depth_to_render_target
) {
1888 if (c
->key
.computes_depth
) {
1889 /* Hand over gl_FragDepth. */
1890 assert(this->frag_depth
);
1891 fs_reg depth
= *(variable_storage(this->frag_depth
));
1893 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
1895 /* Pass through the payload depth. */
1896 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1897 fs_reg(brw_vec8_grf(c
->key
.source_depth_reg
, 0))));
1901 if (c
->key
.dest_depth_reg
) {
1902 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1903 fs_reg(brw_vec8_grf(c
->key
.dest_depth_reg
, 0))));
1906 fs_reg color
= reg_undef
;
1907 if (this->frag_color
)
1908 color
= *(variable_storage(this->frag_color
));
1909 else if (this->frag_data
)
1910 color
= *(variable_storage(this->frag_data
));
1912 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1913 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1914 "FB write target %d",
1916 if (this->frag_color
|| this->frag_data
) {
1917 for (int i
= 0; i
< 4; i
++) {
1918 emit(fs_inst(BRW_OPCODE_MOV
,
1919 fs_reg(MRF
, color_mrf
+ i
),
1925 if (this->frag_color
)
1926 color
.reg_offset
-= 4;
1928 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1929 reg_undef
, reg_undef
));
1930 inst
->target
= target
;
1932 if (target
== c
->key
.nr_color_regions
- 1)
1934 inst
->header_present
= header_present
;
1937 if (c
->key
.nr_color_regions
== 0) {
1938 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1939 reg_undef
, reg_undef
));
1942 inst
->header_present
= header_present
;
1945 this->current_annotation
= NULL
;
1949 fs_visitor::generate_fb_write(fs_inst
*inst
)
1951 GLboolean eot
= inst
->eot
;
1952 struct brw_reg implied_header
;
1954 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1957 brw_push_insn_state(p
);
1958 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1959 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1961 if (inst
->header_present
) {
1962 if (intel
->gen
>= 6) {
1965 brw_vec8_grf(0, 0));
1966 implied_header
= brw_null_reg();
1968 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1973 brw_vec8_grf(1, 0));
1975 implied_header
= brw_null_reg();
1978 brw_pop_insn_state(p
);
1981 8, /* dispatch_width */
1982 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
1992 fs_visitor::generate_linterp(fs_inst
*inst
,
1993 struct brw_reg dst
, struct brw_reg
*src
)
1995 struct brw_reg delta_x
= src
[0];
1996 struct brw_reg delta_y
= src
[1];
1997 struct brw_reg interp
= src
[2];
2000 delta_y
.nr
== delta_x
.nr
+ 1 &&
2001 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2002 brw_PLN(p
, dst
, interp
, delta_x
);
2004 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2005 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2010 fs_visitor::generate_math(fs_inst
*inst
,
2011 struct brw_reg dst
, struct brw_reg
*src
)
2015 switch (inst
->opcode
) {
2017 op
= BRW_MATH_FUNCTION_INV
;
2020 op
= BRW_MATH_FUNCTION_RSQ
;
2022 case FS_OPCODE_SQRT
:
2023 op
= BRW_MATH_FUNCTION_SQRT
;
2025 case FS_OPCODE_EXP2
:
2026 op
= BRW_MATH_FUNCTION_EXP
;
2028 case FS_OPCODE_LOG2
:
2029 op
= BRW_MATH_FUNCTION_LOG
;
2032 op
= BRW_MATH_FUNCTION_POW
;
2035 op
= BRW_MATH_FUNCTION_SIN
;
2038 op
= BRW_MATH_FUNCTION_COS
;
2041 assert(!"not reached: unknown math function");
2046 if (inst
->opcode
== FS_OPCODE_POW
) {
2047 brw_MOV(p
, brw_message_reg(3), src
[1]);
2052 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2053 BRW_MATH_SATURATE_NONE
,
2055 BRW_MATH_DATA_VECTOR
,
2056 BRW_MATH_PRECISION_FULL
);
2060 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2064 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2066 if (intel
->gen
>= 5) {
2067 switch (inst
->opcode
) {
2069 if (inst
->shadow_compare
) {
2070 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2072 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2076 if (inst
->shadow_compare
) {
2077 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2079 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2084 switch (inst
->opcode
) {
2086 /* Note that G45 and older determines shadow compare and dispatch width
2087 * from message length for most messages.
2089 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2090 if (inst
->shadow_compare
) {
2091 assert(inst
->mlen
== 5);
2093 assert(inst
->mlen
<= 6);
2097 if (inst
->shadow_compare
) {
2098 assert(inst
->mlen
== 5);
2099 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2101 assert(inst
->mlen
== 8);
2102 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2103 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2108 assert(msg_type
!= -1);
2110 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2119 retype(dst
, BRW_REGISTER_TYPE_UW
),
2121 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2122 SURF_INDEX_TEXTURE(inst
->sampler
),
2134 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2137 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2139 * and we're trying to produce:
2142 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2143 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2144 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2145 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2146 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2147 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2148 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2149 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2151 * and add another set of two more subspans if in 16-pixel dispatch mode.
2153 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2154 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2155 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2156 * between each other. We could probably do it like ddx and swizzle the right
2157 * order later, but bail for now and just produce
2158 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2161 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2163 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2164 BRW_REGISTER_TYPE_F
,
2165 BRW_VERTICAL_STRIDE_2
,
2167 BRW_HORIZONTAL_STRIDE_0
,
2168 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2169 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2170 BRW_REGISTER_TYPE_F
,
2171 BRW_VERTICAL_STRIDE_2
,
2173 BRW_HORIZONTAL_STRIDE_0
,
2174 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2175 brw_ADD(p
, dst
, src0
, negate(src1
));
2179 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2181 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2182 BRW_REGISTER_TYPE_F
,
2183 BRW_VERTICAL_STRIDE_4
,
2185 BRW_HORIZONTAL_STRIDE_0
,
2186 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2187 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2188 BRW_REGISTER_TYPE_F
,
2189 BRW_VERTICAL_STRIDE_4
,
2191 BRW_HORIZONTAL_STRIDE_0
,
2192 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2193 brw_ADD(p
, dst
, src0
, negate(src1
));
2197 fs_visitor::generate_discard(fs_inst
*inst
, struct brw_reg temp
)
2199 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2200 temp
= brw_uw1_reg(temp
.file
, temp
.nr
, 0);
2202 brw_push_insn_state(p
);
2203 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2204 brw_NOT(p
, temp
, brw_mask_reg(1)); /* IMASK */
2205 brw_AND(p
, g0
, temp
, g0
);
2206 brw_pop_insn_state(p
);
2210 fs_visitor::assign_curb_setup()
2212 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
2213 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2215 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2216 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2217 fs_inst
*inst
= (fs_inst
*)iter
.get();
2219 for (unsigned int i
= 0; i
< 3; i
++) {
2220 if (inst
->src
[i
].file
== UNIFORM
) {
2221 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2222 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2226 inst
->src
[i
].file
= FIXED_HW_REG
;
2227 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
2234 fs_visitor::calculate_urb_setup()
2236 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2241 /* Figure out where each of the incoming setup attributes lands. */
2242 if (intel
->gen
>= 6) {
2243 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2244 if (i
== FRAG_ATTRIB_WPOS
||
2245 (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
))) {
2246 urb_setup
[i
] = urb_next
++;
2250 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2251 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2252 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2255 if (i
>= VERT_RESULT_VAR0
)
2256 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2257 else if (i
<= VERT_RESULT_TEX7
)
2263 urb_setup
[fp_index
] = urb_next
++;
2268 /* Each attribute is 4 setup channels, each of which is half a reg. */
2269 c
->prog_data
.urb_read_length
= urb_next
* 2;
2273 fs_visitor::assign_urb_setup()
2275 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2277 /* Offset all the urb_setup[] index by the actual position of the
2278 * setup regs, now that the location of the constants has been chosen.
2280 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2281 fs_inst
*inst
= (fs_inst
*)iter
.get();
2283 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2286 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2288 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2291 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2295 assign_reg(int *reg_hw_locations
, fs_reg
*reg
)
2297 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
2298 reg
->hw_reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
;
2304 fs_visitor::assign_regs_trivial()
2307 int hw_reg_mapping
[this->virtual_grf_next
];
2310 hw_reg_mapping
[0] = 0;
2311 hw_reg_mapping
[1] = this->first_non_payload_grf
;
2312 for (i
= 2; i
< this->virtual_grf_next
; i
++) {
2313 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
2314 this->virtual_grf_sizes
[i
- 1]);
2316 last_grf
= hw_reg_mapping
[i
- 1] + this->virtual_grf_sizes
[i
- 1];
2318 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2319 fs_inst
*inst
= (fs_inst
*)iter
.get();
2321 assign_reg(hw_reg_mapping
, &inst
->dst
);
2322 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2323 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2326 this->grf_used
= last_grf
+ 1;
2330 fs_visitor::assign_regs()
2333 int hw_reg_mapping
[this->virtual_grf_next
+ 1];
2334 int base_reg_count
= BRW_MAX_GRF
- this->first_non_payload_grf
;
2335 int class_sizes
[base_reg_count
];
2336 int class_count
= 0;
2337 int aligned_pair_class
= -1;
2339 /* Set up the register classes.
2341 * The base registers store a scalar value. For texture samples,
2342 * we get virtual GRFs composed of 4 contiguous hw register. For
2343 * structures and arrays, we store them as contiguous larger things
2344 * than that, though we should be able to do better most of the
2347 class_sizes
[class_count
++] = 1;
2348 if (brw
->has_pln
&& intel
->gen
< 6) {
2349 /* Always set up the (unaligned) pairs for gen5, so we can find
2350 * them for making the aligned pair class.
2352 class_sizes
[class_count
++] = 2;
2354 for (int r
= 1; r
< this->virtual_grf_next
; r
++) {
2357 for (i
= 0; i
< class_count
; i
++) {
2358 if (class_sizes
[i
] == this->virtual_grf_sizes
[r
])
2361 if (i
== class_count
) {
2362 if (this->virtual_grf_sizes
[r
] >= base_reg_count
) {
2363 fprintf(stderr
, "Object too large to register allocate.\n");
2367 class_sizes
[class_count
++] = this->virtual_grf_sizes
[r
];
2371 int ra_reg_count
= 0;
2372 int class_base_reg
[class_count
];
2373 int class_reg_count
[class_count
];
2374 int classes
[class_count
+ 1];
2376 for (int i
= 0; i
< class_count
; i
++) {
2377 class_base_reg
[i
] = ra_reg_count
;
2378 class_reg_count
[i
] = base_reg_count
- (class_sizes
[i
] - 1);
2379 ra_reg_count
+= class_reg_count
[i
];
2382 struct ra_regs
*regs
= ra_alloc_reg_set(ra_reg_count
);
2383 for (int i
= 0; i
< class_count
; i
++) {
2384 classes
[i
] = ra_alloc_reg_class(regs
);
2386 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2387 ra_class_add_reg(regs
, classes
[i
], class_base_reg
[i
] + i_r
);
2390 /* Add conflicts between our contiguous registers aliasing
2391 * base regs and other register classes' contiguous registers
2392 * that alias base regs, or the base regs themselves for classes[0].
2394 for (int c
= 0; c
<= i
; c
++) {
2395 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2396 for (int c_r
= MAX2(0, i_r
- (class_sizes
[c
] - 1));
2397 c_r
< MIN2(class_reg_count
[c
], i_r
+ class_sizes
[i
]);
2401 printf("%d/%d conflicts %d/%d\n",
2402 class_sizes
[i
], this->first_non_payload_grf
+ i_r
,
2403 class_sizes
[c
], this->first_non_payload_grf
+ c_r
);
2406 ra_add_reg_conflict(regs
,
2407 class_base_reg
[i
] + i_r
,
2408 class_base_reg
[c
] + c_r
);
2414 /* Add a special class for aligned pairs, which we'll put delta_x/y
2415 * in on gen5 so that we can do PLN.
2417 if (brw
->has_pln
&& intel
->gen
< 6) {
2418 int reg_count
= (base_reg_count
- 1) / 2;
2419 int unaligned_pair_class
= 1;
2420 assert(class_sizes
[unaligned_pair_class
] == 2);
2422 aligned_pair_class
= class_count
;
2423 classes
[aligned_pair_class
] = ra_alloc_reg_class(regs
);
2424 class_base_reg
[aligned_pair_class
] = 0;
2425 class_reg_count
[aligned_pair_class
] = 0;
2426 int start
= (this->first_non_payload_grf
& 1) ? 1 : 0;
2428 for (int i
= 0; i
< reg_count
; i
++) {
2429 ra_class_add_reg(regs
, classes
[aligned_pair_class
],
2430 class_base_reg
[unaligned_pair_class
] + i
* 2 + start
);
2435 ra_set_finalize(regs
);
2437 struct ra_graph
*g
= ra_alloc_interference_graph(regs
,
2438 this->virtual_grf_next
);
2439 /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
2442 ra_set_node_class(g
, 0, classes
[0]);
2444 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2445 for (int c
= 0; c
< class_count
; c
++) {
2446 if (class_sizes
[c
] == this->virtual_grf_sizes
[i
]) {
2447 if (aligned_pair_class
>= 0 &&
2448 this->delta_x
.reg
== i
) {
2449 ra_set_node_class(g
, i
, classes
[aligned_pair_class
]);
2451 ra_set_node_class(g
, i
, classes
[c
]);
2457 for (int j
= 1; j
< i
; j
++) {
2458 if (virtual_grf_interferes(i
, j
)) {
2459 ra_add_node_interference(g
, i
, j
);
2464 /* FINISHME: Handle spilling */
2465 if (!ra_allocate_no_spills(g
)) {
2466 fprintf(stderr
, "Failed to allocate registers.\n");
2471 /* Get the chosen virtual registers for each node, and map virtual
2472 * regs in the register classes back down to real hardware reg
2475 hw_reg_mapping
[0] = 0; /* unused */
2476 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2477 int reg
= ra_get_node_reg(g
, i
);
2480 for (int c
= 0; c
< class_count
; c
++) {
2481 if (reg
>= class_base_reg
[c
] &&
2482 reg
< class_base_reg
[c
] + class_reg_count
[c
]) {
2483 hw_reg
= reg
- class_base_reg
[c
];
2488 assert(hw_reg
!= -1);
2489 hw_reg_mapping
[i
] = this->first_non_payload_grf
+ hw_reg
;
2490 last_grf
= MAX2(last_grf
,
2491 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
] - 1);
2494 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2495 fs_inst
*inst
= (fs_inst
*)iter
.get();
2497 assign_reg(hw_reg_mapping
, &inst
->dst
);
2498 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2499 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2502 this->grf_used
= last_grf
+ 1;
2509 fs_visitor::calculate_live_intervals()
2511 int num_vars
= this->virtual_grf_next
;
2512 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2513 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2517 for (int i
= 0; i
< num_vars
; i
++) {
2523 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2524 fs_inst
*inst
= (fs_inst
*)iter
.get();
2526 if (inst
->opcode
== BRW_OPCODE_DO
) {
2527 if (loop_depth
++ == 0)
2529 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2532 if (loop_depth
== 0) {
2535 * Patches up any vars marked for use within the loop as
2536 * live until the end. This is conservative, as there
2537 * will often be variables defined and used inside the
2538 * loop but dead at the end of the loop body.
2540 for (int i
= 0; i
< num_vars
; i
++) {
2541 if (use
[i
] == loop_start
) {
2552 for (unsigned int i
= 0; i
< 3; i
++) {
2553 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2554 use
[inst
->src
[i
].reg
] = MAX2(use
[inst
->src
[i
].reg
], eip
);
2557 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2558 def
[inst
->dst
.reg
] = MIN2(def
[inst
->dst
.reg
], eip
);
2565 talloc_free(this->virtual_grf_def
);
2566 talloc_free(this->virtual_grf_use
);
2567 this->virtual_grf_def
= def
;
2568 this->virtual_grf_use
= use
;
2572 * Attempts to move immediate constants into the immediate
2573 * constant slot of following instructions.
2575 * Immediate constants are a bit tricky -- they have to be in the last
2576 * operand slot, you can't do abs/negate on them,
2580 fs_visitor::propagate_constants()
2582 bool progress
= false;
2584 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2585 fs_inst
*inst
= (fs_inst
*)iter
.get();
2587 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2589 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2590 inst
->dst
.type
!= inst
->src
[0].type
)
2593 /* Don't bother with cases where we should have had the
2594 * operation on the constant folded in GLSL already.
2599 /* Found a move of a constant to a GRF. Find anything else using the GRF
2600 * before it's written, and replace it with the constant if we can.
2602 exec_list_iterator scan_iter
= iter
;
2604 for (; scan_iter
.has_next(); scan_iter
.next()) {
2605 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2607 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2608 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2609 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2610 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2614 for (int i
= 2; i
>= 0; i
--) {
2615 if (scan_inst
->src
[i
].file
!= GRF
||
2616 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2617 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2620 /* Don't bother with cases where we should have had the
2621 * operation on the constant folded in GLSL already.
2623 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2626 switch (scan_inst
->opcode
) {
2627 case BRW_OPCODE_MOV
:
2628 scan_inst
->src
[i
] = inst
->src
[0];
2632 case BRW_OPCODE_MUL
:
2633 case BRW_OPCODE_ADD
:
2635 scan_inst
->src
[i
] = inst
->src
[0];
2637 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2638 /* Fit this constant in by commuting the operands */
2639 scan_inst
->src
[0] = scan_inst
->src
[1];
2640 scan_inst
->src
[1] = inst
->src
[0];
2643 case BRW_OPCODE_CMP
:
2645 scan_inst
->src
[i
] = inst
->src
[0];
2651 if (scan_inst
->dst
.file
== GRF
&&
2652 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2653 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2654 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2663 * Must be called after calculate_live_intervales() to remove unused
2664 * writes to registers -- register allocation will fail otherwise
2665 * because something deffed but not used won't be considered to
2666 * interfere with other regs.
2669 fs_visitor::dead_code_eliminate()
2671 bool progress
= false;
2672 int num_vars
= this->virtual_grf_next
;
2673 bool dead
[num_vars
];
2675 for (int i
= 0; i
< num_vars
; i
++) {
2676 /* This would be ">=", but FS_OPCODE_DISCARD has a src == dst where
2677 * it writes dst then reads it as src.
2679 dead
[i
] = this->virtual_grf_def
[i
] > this->virtual_grf_use
[i
];
2682 /* Mark off its interval so it won't interfere with anything. */
2683 this->virtual_grf_def
[i
] = -1;
2684 this->virtual_grf_use
[i
] = -1;
2688 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2689 fs_inst
*inst
= (fs_inst
*)iter
.get();
2691 if (inst
->dst
.file
== GRF
&& dead
[inst
->dst
.reg
]) {
2701 fs_visitor::virtual_grf_interferes(int a
, int b
)
2703 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
2704 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
2706 /* For dead code, just check if the def interferes with the other range. */
2707 if (this->virtual_grf_use
[a
] == -1) {
2708 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
2709 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
2711 if (this->virtual_grf_use
[b
] == -1) {
2712 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
2713 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
2716 return start
<= end
;
2719 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
2721 struct brw_reg brw_reg
;
2723 switch (reg
->file
) {
2727 brw_reg
= brw_vec8_reg(reg
->file
,
2729 brw_reg
= retype(brw_reg
, reg
->type
);
2732 switch (reg
->type
) {
2733 case BRW_REGISTER_TYPE_F
:
2734 brw_reg
= brw_imm_f(reg
->imm
.f
);
2736 case BRW_REGISTER_TYPE_D
:
2737 brw_reg
= brw_imm_d(reg
->imm
.i
);
2739 case BRW_REGISTER_TYPE_UD
:
2740 brw_reg
= brw_imm_ud(reg
->imm
.u
);
2743 assert(!"not reached");
2748 brw_reg
= reg
->fixed_hw_reg
;
2751 /* Probably unused. */
2752 brw_reg
= brw_null_reg();
2755 assert(!"not reached");
2756 brw_reg
= brw_null_reg();
2760 brw_reg
= brw_abs(brw_reg
);
2762 brw_reg
= negate(brw_reg
);
2768 fs_visitor::generate_code()
2770 unsigned int annotation_len
= 0;
2771 int last_native_inst
= 0;
2772 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
2773 int if_stack_depth
= 0, loop_stack_depth
= 0;
2774 int if_depth_in_loop
[16];
2776 if_depth_in_loop
[loop_stack_depth
] = 0;
2778 memset(&if_stack
, 0, sizeof(if_stack
));
2779 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2780 fs_inst
*inst
= (fs_inst
*)iter
.get();
2781 struct brw_reg src
[3], dst
;
2783 for (unsigned int i
= 0; i
< 3; i
++) {
2784 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
2786 dst
= brw_reg_from_fs_reg(&inst
->dst
);
2788 brw_set_conditionalmod(p
, inst
->conditional_mod
);
2789 brw_set_predicate_control(p
, inst
->predicated
);
2791 switch (inst
->opcode
) {
2792 case BRW_OPCODE_MOV
:
2793 brw_MOV(p
, dst
, src
[0]);
2795 case BRW_OPCODE_ADD
:
2796 brw_ADD(p
, dst
, src
[0], src
[1]);
2798 case BRW_OPCODE_MUL
:
2799 brw_MUL(p
, dst
, src
[0], src
[1]);
2802 case BRW_OPCODE_FRC
:
2803 brw_FRC(p
, dst
, src
[0]);
2805 case BRW_OPCODE_RNDD
:
2806 brw_RNDD(p
, dst
, src
[0]);
2808 case BRW_OPCODE_RNDZ
:
2809 brw_RNDZ(p
, dst
, src
[0]);
2812 case BRW_OPCODE_AND
:
2813 brw_AND(p
, dst
, src
[0], src
[1]);
2816 brw_OR(p
, dst
, src
[0], src
[1]);
2818 case BRW_OPCODE_XOR
:
2819 brw_XOR(p
, dst
, src
[0], src
[1]);
2822 case BRW_OPCODE_CMP
:
2823 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
2825 case BRW_OPCODE_SEL
:
2826 brw_SEL(p
, dst
, src
[0], src
[1]);
2830 assert(if_stack_depth
< 16);
2831 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
2832 if_depth_in_loop
[loop_stack_depth
]++;
2835 case BRW_OPCODE_ELSE
:
2836 if_stack
[if_stack_depth
- 1] =
2837 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
2839 case BRW_OPCODE_ENDIF
:
2841 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
2842 if_depth_in_loop
[loop_stack_depth
]--;
2846 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
2847 if_depth_in_loop
[loop_stack_depth
] = 0;
2850 case BRW_OPCODE_BREAK
:
2851 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
2852 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2854 case BRW_OPCODE_CONTINUE
:
2855 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
2856 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2859 case BRW_OPCODE_WHILE
: {
2860 struct brw_instruction
*inst0
, *inst1
;
2863 if (intel
->gen
>= 5)
2866 assert(loop_stack_depth
> 0);
2868 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
2869 /* patch all the BREAK/CONT instructions from last BGNLOOP */
2870 while (inst0
> loop_stack
[loop_stack_depth
]) {
2872 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
2873 inst0
->bits3
.if_else
.jump_count
== 0) {
2874 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
2876 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
2877 inst0
->bits3
.if_else
.jump_count
== 0) {
2878 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
2886 case FS_OPCODE_SQRT
:
2887 case FS_OPCODE_EXP2
:
2888 case FS_OPCODE_LOG2
:
2892 generate_math(inst
, dst
, src
);
2894 case FS_OPCODE_LINTERP
:
2895 generate_linterp(inst
, dst
, src
);
2900 generate_tex(inst
, dst
, src
[0]);
2902 case FS_OPCODE_DISCARD
:
2903 generate_discard(inst
, dst
/* src0 == dst */);
2906 generate_ddx(inst
, dst
, src
[0]);
2909 generate_ddy(inst
, dst
, src
[0]);
2911 case FS_OPCODE_FB_WRITE
:
2912 generate_fb_write(inst
);
2915 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
2916 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
2917 brw_opcodes
[inst
->opcode
].name
);
2919 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
2924 if (annotation_len
< p
->nr_insn
) {
2925 annotation_len
*= 2;
2926 if (annotation_len
< 16)
2927 annotation_len
= 16;
2929 this->annotation_string
= talloc_realloc(this->mem_ctx
,
2933 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
2939 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
2940 this->annotation_string
[i
] = inst
->annotation
;
2941 this->annotation_ir
[i
] = inst
->ir
;
2943 last_native_inst
= p
->nr_insn
;
2948 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
2950 struct brw_compile
*p
= &c
->func
;
2951 struct intel_context
*intel
= &brw
->intel
;
2952 GLcontext
*ctx
= &intel
->ctx
;
2953 struct brw_shader
*shader
= NULL
;
2954 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
2962 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
2963 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
2964 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
2971 /* We always use 8-wide mode, at least for now. For one, flow
2972 * control only works in 8-wide. Also, when we're fragment shader
2973 * bound, we're almost always under register pressure as well, so
2974 * 8-wide would save us from the performance cliff of spilling
2977 c
->dispatch_width
= 8;
2979 if (INTEL_DEBUG
& DEBUG_WM
) {
2980 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
2981 _mesa_print_ir(shader
->ir
, NULL
);
2985 /* Now the main event: Visit the shader IR and generate our FS IR for it.
2987 fs_visitor
v(c
, shader
);
2992 v
.calculate_urb_setup();
2994 v
.emit_interpolation_setup_gen4();
2996 v
.emit_interpolation_setup_gen6();
2998 /* Generate FS IR for main(). (the visitor only descends into
2999 * functions called "main").
3001 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3002 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3008 v
.assign_curb_setup();
3009 v
.assign_urb_setup();
3015 v
.calculate_live_intervals();
3016 progress
= v
.propagate_constants() || progress
;
3017 progress
= v
.dead_code_eliminate() || progress
;
3021 v
.assign_regs_trivial();
3029 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3034 if (INTEL_DEBUG
& DEBUG_WM
) {
3035 const char *last_annotation_string
= NULL
;
3036 ir_instruction
*last_annotation_ir
= NULL
;
3038 printf("Native code for fragment shader %d:\n", prog
->Name
);
3039 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3040 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
3041 last_annotation_ir
= v
.annotation_ir
[i
];
3042 if (last_annotation_ir
) {
3044 last_annotation_ir
->print();
3048 if (last_annotation_string
!= v
.annotation_string
[i
]) {
3049 last_annotation_string
= v
.annotation_string
[i
];
3050 if (last_annotation_string
)
3051 printf(" %s\n", last_annotation_string
);
3053 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3058 c
->prog_data
.total_grf
= v
.grf_used
;
3059 c
->prog_data
.total_scratch
= 0;