2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "../glsl/glsl_types.h"
47 #include "../glsl/ir_optimization.h"
48 #include "../glsl/ir_print_visitor.h"
50 #define MAX_INSTRUCTION (1 << 30)
51 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
54 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
56 struct brw_shader
*shader
;
58 shader
= rzalloc(NULL
, struct brw_shader
);
60 shader
->base
.Type
= type
;
61 shader
->base
.Name
= name
;
62 _mesa_init_shader(ctx
, &shader
->base
);
68 struct gl_shader_program
*
69 brw_new_shader_program(struct gl_context
*ctx
, GLuint name
)
71 struct brw_shader_program
*prog
;
72 prog
= rzalloc(NULL
, struct brw_shader_program
);
74 prog
->base
.Name
= name
;
75 _mesa_init_shader_program(ctx
, &prog
->base
);
81 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
83 struct brw_context
*brw
= brw_context(ctx
);
84 struct intel_context
*intel
= &brw
->intel
;
86 struct brw_shader
*shader
=
87 (struct brw_shader
*)prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
89 void *mem_ctx
= ralloc_context(NULL
);
93 ralloc_free(shader
->ir
);
94 shader
->ir
= new(shader
) exec_list
;
95 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
97 do_mat_op_to_vec(shader
->ir
);
98 lower_instructions(shader
->ir
,
105 /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
106 * if-statements need to be flattened.
109 lower_if_to_cond_assign(shader
->ir
, 16);
111 do_lower_texture_projection(shader
->ir
);
112 do_vec_index_to_cond_assign(shader
->ir
);
113 brw_do_cubemap_normalize(shader
->ir
);
114 lower_noise(shader
->ir
);
115 lower_quadop_vector(shader
->ir
, false);
116 lower_variable_index_to_cond_assign(shader
->ir
,
118 GL_TRUE
, /* output */
120 GL_TRUE
/* uniform */
126 brw_do_channel_expressions(shader
->ir
);
127 brw_do_vector_splitting(shader
->ir
);
129 progress
= do_lower_jumps(shader
->ir
, true, true,
130 true, /* main return */
131 false, /* continue */
135 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
138 validate_ir_tree(shader
->ir
);
140 reparent_ir(shader
->ir
, shader
->ir
);
141 ralloc_free(mem_ctx
);
144 if (!_mesa_ir_link_shader(ctx
, prog
))
151 type_size(const struct glsl_type
*type
)
153 unsigned int size
, i
;
155 switch (type
->base_type
) {
158 case GLSL_TYPE_FLOAT
:
160 return type
->components();
161 case GLSL_TYPE_ARRAY
:
162 return type_size(type
->fields
.array
) * type
->length
;
163 case GLSL_TYPE_STRUCT
:
165 for (i
= 0; i
< type
->length
; i
++) {
166 size
+= type_size(type
->fields
.structure
[i
].type
);
169 case GLSL_TYPE_SAMPLER
:
170 /* Samplers take up no register space, since they're baked in at
175 assert(!"not reached");
181 * Returns how many MRFs an FS opcode will write over.
183 * Note that this is not the 0 or 1 implied writes in an actual gen
184 * instruction -- the FS opcodes often generate MOVs in addition.
187 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
192 switch (inst
->opcode
) {
208 case FS_OPCODE_FB_WRITE
:
210 case FS_OPCODE_PULL_CONSTANT_LOAD
:
211 case FS_OPCODE_UNSPILL
:
213 case FS_OPCODE_SPILL
:
216 assert(!"not reached");
222 fs_visitor::virtual_grf_alloc(int size
)
224 if (virtual_grf_array_size
<= virtual_grf_next
) {
225 if (virtual_grf_array_size
== 0)
226 virtual_grf_array_size
= 16;
228 virtual_grf_array_size
*= 2;
229 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
230 virtual_grf_array_size
);
232 /* This slot is always unused. */
233 virtual_grf_sizes
[0] = 0;
235 virtual_grf_sizes
[virtual_grf_next
] = size
;
236 return virtual_grf_next
++;
239 /** Fixed HW reg constructor. */
240 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
244 this->hw_reg
= hw_reg
;
245 this->type
= BRW_REGISTER_TYPE_F
;
248 /** Fixed HW reg constructor. */
249 fs_reg::fs_reg(enum register_file file
, int hw_reg
, uint32_t type
)
253 this->hw_reg
= hw_reg
;
258 brw_type_for_base_type(const struct glsl_type
*type
)
260 switch (type
->base_type
) {
261 case GLSL_TYPE_FLOAT
:
262 return BRW_REGISTER_TYPE_F
;
265 return BRW_REGISTER_TYPE_D
;
267 return BRW_REGISTER_TYPE_UD
;
268 case GLSL_TYPE_ARRAY
:
269 case GLSL_TYPE_STRUCT
:
270 case GLSL_TYPE_SAMPLER
:
271 /* These should be overridden with the type of the member when
272 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
273 * way to trip up if we don't.
275 return BRW_REGISTER_TYPE_UD
;
277 assert(!"not reached");
278 return BRW_REGISTER_TYPE_F
;
282 /** Automatic reg constructor. */
283 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
288 this->reg
= v
->virtual_grf_alloc(type_size(type
));
289 this->reg_offset
= 0;
290 this->type
= brw_type_for_base_type(type
);
294 fs_visitor::variable_storage(ir_variable
*var
)
296 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
299 /* Our support for uniforms is piggy-backed on the struct
300 * gl_fragment_program, because that's where the values actually
301 * get stored, rather than in some global gl_shader_program uniform
305 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
307 unsigned int offset
= 0;
309 if (type
->is_matrix()) {
310 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
311 type
->vector_elements
,
314 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
315 offset
+= setup_uniform_values(loc
+ offset
, column
);
321 switch (type
->base_type
) {
322 case GLSL_TYPE_FLOAT
:
326 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
327 unsigned int param
= c
->prog_data
.nr_params
++;
329 assert(param
< ARRAY_SIZE(c
->prog_data
.param
));
331 switch (type
->base_type
) {
332 case GLSL_TYPE_FLOAT
:
333 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
336 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2U
;
339 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2I
;
342 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2B
;
345 assert(!"not reached");
346 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
349 this->param_index
[param
] = loc
;
350 this->param_offset
[param
] = i
;
354 case GLSL_TYPE_STRUCT
:
355 for (unsigned int i
= 0; i
< type
->length
; i
++) {
356 offset
+= setup_uniform_values(loc
+ offset
,
357 type
->fields
.structure
[i
].type
);
361 case GLSL_TYPE_ARRAY
:
362 for (unsigned int i
= 0; i
< type
->length
; i
++) {
363 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
367 case GLSL_TYPE_SAMPLER
:
368 /* The sampler takes up a slot, but we don't use any values from it. */
372 assert(!"not reached");
378 /* Our support for builtin uniforms is even scarier than non-builtin.
379 * It sits on top of the PROG_STATE_VAR parameters that are
380 * automatically updated from GL context state.
383 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
385 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
387 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
388 statevar
= &_mesa_builtin_uniform_desc
[i
];
389 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
393 if (!statevar
->name
) {
395 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
400 if (ir
->type
->is_array()) {
401 array_count
= ir
->type
->length
;
406 for (int a
= 0; a
< array_count
; a
++) {
407 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
408 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
409 int tokens
[STATE_LENGTH
];
411 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
412 if (ir
->type
->is_array()) {
416 /* This state reference has already been setup by ir_to_mesa,
417 * but we'll get the same index back here.
419 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
420 (gl_state_index
*)tokens
);
422 /* Add each of the unique swizzles of the element as a
423 * parameter. This'll end up matching the expected layout of
424 * the array/matrix/structure we're trying to fill in.
427 for (unsigned int i
= 0; i
< 4; i
++) {
428 int swiz
= GET_SWZ(element
->swizzle
, i
);
429 if (swiz
== last_swiz
)
433 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
435 this->param_index
[c
->prog_data
.nr_params
] = index
;
436 this->param_offset
[c
->prog_data
.nr_params
] = swiz
;
437 c
->prog_data
.nr_params
++;
444 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
446 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
448 fs_reg neg_y
= this->pixel_y
;
450 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
453 if (ir
->pixel_center_integer
) {
454 emit(BRW_OPCODE_MOV
, wpos
, this->pixel_x
);
456 emit(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
));
461 if (!flip
&& ir
->pixel_center_integer
) {
462 emit(BRW_OPCODE_MOV
, wpos
, this->pixel_y
);
464 fs_reg pixel_y
= this->pixel_y
;
465 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
468 pixel_y
.negate
= true;
469 offset
+= c
->key
.drawable_height
- 1.0;
472 emit(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
));
477 if (intel
->gen
>= 6) {
478 emit(BRW_OPCODE_MOV
, wpos
,
479 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0)));
481 emit(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
482 interp_reg(FRAG_ATTRIB_WPOS
, 2));
486 /* gl_FragCoord.w: Already set up in emit_interpolation */
487 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
493 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
495 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
496 /* Interpolation is always in floating point regs. */
497 reg
->type
= BRW_REGISTER_TYPE_F
;
500 unsigned int array_elements
;
501 const glsl_type
*type
;
503 if (ir
->type
->is_array()) {
504 array_elements
= ir
->type
->length
;
505 if (array_elements
== 0) {
508 type
= ir
->type
->fields
.array
;
514 int location
= ir
->location
;
515 for (unsigned int i
= 0; i
< array_elements
; i
++) {
516 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
517 if (urb_setup
[location
] == -1) {
518 /* If there's no incoming setup data for this slot, don't
519 * emit interpolation for it.
521 attr
.reg_offset
+= type
->vector_elements
;
526 if (c
->key
.flat_shade
&& (location
== FRAG_ATTRIB_COL0
||
527 location
== FRAG_ATTRIB_COL1
)) {
528 /* Constant interpolation (flat shading) case. The SF has
529 * handed us defined values in only the constant offset
530 * field of the setup reg.
532 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
533 struct brw_reg interp
= interp_reg(location
, c
);
534 interp
= suboffset(interp
, 3);
535 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
539 /* Perspective interpolation case. */
540 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
541 struct brw_reg interp
= interp_reg(location
, c
);
542 emit(FS_OPCODE_LINTERP
, attr
,
543 this->delta_x
, this->delta_y
, fs_reg(interp
));
547 if (intel
->gen
< 6) {
548 attr
.reg_offset
-= type
->vector_elements
;
549 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
550 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
563 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
565 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
567 /* The frontfacing comes in as a bit in the thread payload. */
568 if (intel
->gen
>= 6) {
569 emit(BRW_OPCODE_ASR
, *reg
,
570 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
572 emit(BRW_OPCODE_NOT
, *reg
, *reg
);
573 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1));
575 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
576 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
579 fs_inst
*inst
= emit(BRW_OPCODE_CMP
, *reg
,
582 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
583 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u));
590 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src
)
602 assert(!"not reached: bad math opcode");
606 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
607 * might be able to do better by doing execsize = 1 math and then
608 * expanding that result out, but we would need to be careful with
611 * The hardware ignores source modifiers (negate and abs) on math
612 * instructions, so we also move to a temp to set those up.
614 if (intel
->gen
>= 6 && (src
.file
== UNIFORM
||
617 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
618 emit(BRW_OPCODE_MOV
, expanded
, src
);
622 fs_inst
*inst
= emit(opcode
, dst
, src
);
624 if (intel
->gen
< 6) {
633 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
638 assert(opcode
== FS_OPCODE_POW
);
640 if (intel
->gen
>= 6) {
641 /* Can't do hstride == 0 args to gen6 math, so expand it out.
643 * The hardware ignores source modifiers (negate and abs) on math
644 * instructions, so we also move to a temp to set those up.
646 if (src0
.file
== UNIFORM
|| src0
.abs
|| src0
.negate
) {
647 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
648 emit(BRW_OPCODE_MOV
, expanded
, src0
);
652 if (src1
.file
== UNIFORM
|| src1
.abs
|| src1
.negate
) {
653 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
654 emit(BRW_OPCODE_MOV
, expanded
, src1
);
658 inst
= emit(opcode
, dst
, src0
, src1
);
660 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1), src1
);
661 inst
= emit(opcode
, dst
, src0
, reg_null_f
);
663 inst
->base_mrf
= base_mrf
;
670 fs_visitor::visit(ir_variable
*ir
)
674 if (variable_storage(ir
))
677 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
678 this->frag_color
= ir
;
679 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
680 this->frag_data
= ir
;
681 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
682 this->frag_depth
= ir
;
685 if (ir
->mode
== ir_var_in
) {
686 if (!strcmp(ir
->name
, "gl_FragCoord")) {
687 reg
= emit_fragcoord_interpolation(ir
);
688 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
689 reg
= emit_frontfacing_interpolation(ir
);
691 reg
= emit_general_interpolation(ir
);
694 hash_table_insert(this->variable_ht
, reg
, ir
);
698 if (ir
->mode
== ir_var_uniform
) {
699 int param_index
= c
->prog_data
.nr_params
;
701 if (!strncmp(ir
->name
, "gl_", 3)) {
702 setup_builtin_uniform_values(ir
);
704 setup_uniform_values(ir
->location
, ir
->type
);
707 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
708 reg
->type
= brw_type_for_base_type(ir
->type
);
712 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
714 hash_table_insert(this->variable_ht
, reg
, ir
);
718 fs_visitor::visit(ir_dereference_variable
*ir
)
720 fs_reg
*reg
= variable_storage(ir
->var
);
725 fs_visitor::visit(ir_dereference_record
*ir
)
727 const glsl_type
*struct_type
= ir
->record
->type
;
729 ir
->record
->accept(this);
731 unsigned int offset
= 0;
732 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
733 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
735 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
737 this->result
.reg_offset
+= offset
;
738 this->result
.type
= brw_type_for_base_type(ir
->type
);
742 fs_visitor::visit(ir_dereference_array
*ir
)
747 ir
->array
->accept(this);
748 index
= ir
->array_index
->as_constant();
750 element_size
= type_size(ir
->type
);
751 this->result
.type
= brw_type_for_base_type(ir
->type
);
754 assert(this->result
.file
== UNIFORM
||
755 (this->result
.file
== GRF
&&
756 this->result
.reg
!= 0));
757 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
759 assert(!"FINISHME: non-constant array element");
763 /* Instruction selection: Produce a MOV.sat instead of
764 * MIN(MAX(val, 0), 1) when possible.
767 fs_visitor::try_emit_saturate(ir_expression
*ir
)
769 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
774 sat_val
->accept(this);
775 fs_reg src
= this->result
;
777 this->result
= fs_reg(this, ir
->type
);
778 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, this->result
, src
);
779 inst
->saturate
= true;
785 brw_conditional_for_comparison(unsigned int op
)
789 return BRW_CONDITIONAL_L
;
790 case ir_binop_greater
:
791 return BRW_CONDITIONAL_G
;
792 case ir_binop_lequal
:
793 return BRW_CONDITIONAL_LE
;
794 case ir_binop_gequal
:
795 return BRW_CONDITIONAL_GE
;
797 case ir_binop_all_equal
: /* same as equal for scalars */
798 return BRW_CONDITIONAL_Z
;
799 case ir_binop_nequal
:
800 case ir_binop_any_nequal
: /* same as nequal for scalars */
801 return BRW_CONDITIONAL_NZ
;
803 assert(!"not reached: bad operation for comparison");
804 return BRW_CONDITIONAL_NZ
;
809 fs_visitor::visit(ir_expression
*ir
)
811 unsigned int operand
;
815 assert(ir
->get_num_operands() <= 2);
817 if (try_emit_saturate(ir
))
820 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
821 ir
->operands
[operand
]->accept(this);
822 if (this->result
.file
== BAD_FILE
) {
824 printf("Failed to get tree for expression operand:\n");
825 ir
->operands
[operand
]->accept(&v
);
828 op
[operand
] = this->result
;
830 /* Matrix expression operands should have been broken down to vector
831 * operations already.
833 assert(!ir
->operands
[operand
]->type
->is_matrix());
834 /* And then those vector operands should have been broken down to scalar.
836 assert(!ir
->operands
[operand
]->type
->is_vector());
839 /* Storage for our result. If our result goes into an assignment, it will
840 * just get copy-propagated out, so no worries.
842 this->result
= fs_reg(this, ir
->type
);
844 switch (ir
->operation
) {
845 case ir_unop_logic_not
:
846 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
847 * ones complement of the whole register, not just bit 0.
849 emit(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1));
852 op
[0].negate
= !op
[0].negate
;
853 this->result
= op
[0];
857 op
[0].negate
= false;
858 this->result
= op
[0];
861 temp
= fs_reg(this, ir
->type
);
863 emit(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
));
865 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
866 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
867 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
));
868 inst
->predicated
= true;
870 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
871 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
872 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
));
873 inst
->predicated
= true;
877 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
881 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
884 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
888 assert(!"not reached: should be handled by ir_explog_to_explog2");
891 case ir_unop_sin_reduced
:
892 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
895 case ir_unop_cos_reduced
:
896 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
900 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
903 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
907 emit(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]);
910 assert(!"not reached: should be handled by ir_sub_to_add_neg");
914 emit(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]);
917 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
920 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
924 case ir_binop_greater
:
925 case ir_binop_lequal
:
926 case ir_binop_gequal
:
928 case ir_binop_all_equal
:
929 case ir_binop_nequal
:
930 case ir_binop_any_nequal
:
932 /* original gen4 does implicit conversion before comparison. */
934 temp
.type
= op
[0].type
;
936 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
937 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
938 emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1));
941 case ir_binop_logic_xor
:
942 emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
945 case ir_binop_logic_or
:
946 emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
949 case ir_binop_logic_and
:
950 emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
955 assert(!"not reached: should be handled by brw_fs_channel_expressions");
959 assert(!"not reached: should be handled by lower_noise");
962 case ir_quadop_vector
:
963 assert(!"not reached: should be handled by lower_quadop_vector");
967 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
971 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
978 emit(BRW_OPCODE_MOV
, this->result
, op
[0]);
983 /* original gen4 does implicit conversion before comparison. */
985 temp
.type
= op
[0].type
;
987 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], fs_reg(0.0f
));
988 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
989 inst
= emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(1));
993 emit(BRW_OPCODE_RNDZ
, this->result
, op
[0]);
996 op
[0].negate
= !op
[0].negate
;
997 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
998 this->result
.negate
= true;
1001 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
1004 inst
= emit(BRW_OPCODE_FRC
, this->result
, op
[0]);
1006 case ir_unop_round_even
:
1007 emit(BRW_OPCODE_RNDE
, this->result
, op
[0]);
1011 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
1012 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1014 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
1015 inst
->predicated
= true;
1018 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
1019 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1021 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
1022 inst
->predicated
= true;
1026 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
1029 case ir_unop_bit_not
:
1030 inst
= emit(BRW_OPCODE_NOT
, this->result
, op
[0]);
1032 case ir_binop_bit_and
:
1033 inst
= emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
1035 case ir_binop_bit_xor
:
1036 inst
= emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
1038 case ir_binop_bit_or
:
1039 inst
= emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
1043 case ir_binop_lshift
:
1044 case ir_binop_rshift
:
1045 assert(!"GLSL 1.30 features unsupported");
1051 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1052 const glsl_type
*type
, bool predicated
)
1054 switch (type
->base_type
) {
1055 case GLSL_TYPE_FLOAT
:
1056 case GLSL_TYPE_UINT
:
1058 case GLSL_TYPE_BOOL
:
1059 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1060 l
.type
= brw_type_for_base_type(type
);
1061 r
.type
= brw_type_for_base_type(type
);
1063 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, l
, r
);
1064 inst
->predicated
= predicated
;
1070 case GLSL_TYPE_ARRAY
:
1071 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1072 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1076 case GLSL_TYPE_STRUCT
:
1077 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1078 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1083 case GLSL_TYPE_SAMPLER
:
1087 assert(!"not reached");
1093 fs_visitor::visit(ir_assignment
*ir
)
1098 /* FINISHME: arrays on the lhs */
1099 ir
->lhs
->accept(this);
1102 ir
->rhs
->accept(this);
1105 assert(l
.file
!= BAD_FILE
);
1106 assert(r
.file
!= BAD_FILE
);
1108 if (ir
->condition
) {
1109 emit_bool_to_cond_code(ir
->condition
);
1112 if (ir
->lhs
->type
->is_scalar() ||
1113 ir
->lhs
->type
->is_vector()) {
1114 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1115 if (ir
->write_mask
& (1 << i
)) {
1116 inst
= emit(BRW_OPCODE_MOV
, l
, r
);
1118 inst
->predicated
= true;
1124 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1129 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1133 bool simd16
= false;
1139 if (ir
->shadow_comparitor
) {
1140 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1141 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
1142 coordinate
.reg_offset
++;
1144 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1147 if (ir
->op
== ir_tex
) {
1148 /* There's no plain shadow compare message, so we use shadow
1149 * compare with a bias of 0.0.
1151 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
));
1153 } else if (ir
->op
== ir_txb
) {
1154 ir
->lod_info
.bias
->accept(this);
1155 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1158 assert(ir
->op
== ir_txl
);
1159 ir
->lod_info
.lod
->accept(this);
1160 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1164 ir
->shadow_comparitor
->accept(this);
1165 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1167 } else if (ir
->op
== ir_tex
) {
1168 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1169 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
1170 coordinate
.reg_offset
++;
1172 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1174 } else if (ir
->op
== ir_txd
) {
1175 assert(!"TXD isn't supported on gen4 yet.");
1177 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1178 * instructions. We'll need to do SIMD16 here.
1180 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1182 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1183 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), coordinate
);
1184 coordinate
.reg_offset
++;
1187 /* lod/bias appears after u/v/r. */
1190 if (ir
->op
== ir_txb
) {
1191 ir
->lod_info
.bias
->accept(this);
1192 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1195 ir
->lod_info
.lod
->accept(this);
1196 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1200 /* The unused upper half. */
1203 /* Now, since we're doing simd16, the return is 2 interleaved
1204 * vec4s where the odd-indexed ones are junk. We'll need to move
1205 * this weirdness around to the expected layout.
1209 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1211 dst
.type
= BRW_REGISTER_TYPE_F
;
1214 fs_inst
*inst
= NULL
;
1217 inst
= emit(FS_OPCODE_TEX
, dst
);
1220 inst
= emit(FS_OPCODE_TXB
, dst
);
1223 inst
= emit(FS_OPCODE_TXL
, dst
);
1226 inst
= emit(FS_OPCODE_TXD
, dst
);
1229 assert(!"GLSL 1.30 features unsupported");
1232 inst
->base_mrf
= base_mrf
;
1236 for (int i
= 0; i
< 4; i
++) {
1237 emit(BRW_OPCODE_MOV
, orig_dst
, dst
);
1238 orig_dst
.reg_offset
++;
1239 dst
.reg_offset
+= 2;
1247 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1249 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1250 * optional parameters like shadow comparitor or LOD bias. If
1251 * optional parameters aren't present, those base slots are
1252 * optional and don't need to be included in the message.
1254 * We don't fill in the unnecessary slots regardless, which may
1255 * look surprising in the disassembly.
1257 int mlen
= 1; /* g0 header always present. */
1260 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1261 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
1262 coordinate
.reg_offset
++;
1264 mlen
+= ir
->coordinate
->type
->vector_elements
;
1266 if (ir
->shadow_comparitor
) {
1267 mlen
= MAX2(mlen
, 5);
1269 ir
->shadow_comparitor
->accept(this);
1270 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1274 fs_inst
*inst
= NULL
;
1277 inst
= emit(FS_OPCODE_TEX
, dst
);
1280 ir
->lod_info
.bias
->accept(this);
1281 mlen
= MAX2(mlen
, 5);
1282 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1285 inst
= emit(FS_OPCODE_TXB
, dst
);
1288 ir
->lod_info
.lod
->accept(this);
1289 mlen
= MAX2(mlen
, 5);
1290 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1293 inst
= emit(FS_OPCODE_TXL
, dst
);
1297 assert(!"GLSL 1.30 features unsupported");
1300 inst
->base_mrf
= base_mrf
;
1307 fs_visitor::visit(ir_texture
*ir
)
1310 fs_inst
*inst
= NULL
;
1312 ir
->coordinate
->accept(this);
1313 fs_reg coordinate
= this->result
;
1315 if (ir
->offset
!= NULL
) {
1316 ir_constant
*offset
= ir
->offset
->as_constant();
1317 assert(offset
!= NULL
);
1319 signed char offsets
[3];
1320 for (unsigned i
= 0; i
< ir
->offset
->type
->vector_elements
; i
++)
1321 offsets
[i
] = (signed char) offset
->value
.i
[i
];
1323 /* Combine all three offsets into a single unsigned dword:
1325 * bits 11:8 - U Offset (X component)
1326 * bits 7:4 - V Offset (Y component)
1327 * bits 3:0 - R Offset (Z component)
1329 unsigned offset_bits
= 0;
1330 for (unsigned i
= 0; i
< ir
->offset
->type
->vector_elements
; i
++) {
1331 const unsigned shift
= 4 * (2 - i
);
1332 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
1335 /* Explicitly set up the message header by copying g0 to msg reg m1. */
1336 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 1, BRW_REGISTER_TYPE_UD
),
1337 fs_reg(GRF
, 0, BRW_REGISTER_TYPE_UD
));
1339 /* Then set the offset bits in DWord 2 of the message header. */
1340 emit(BRW_OPCODE_MOV
,
1341 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 1, 2),
1342 BRW_REGISTER_TYPE_UD
)),
1343 fs_reg(brw_imm_uw(offset_bits
)));
1346 /* Should be lowered by do_lower_texture_projection */
1347 assert(!ir
->projector
);
1349 sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
1350 ctx
->Shader
.CurrentFragmentProgram
,
1351 &brw
->fragment_program
->Base
);
1352 sampler
= c
->fp
->program
.Base
.SamplerUnits
[sampler
];
1354 /* The 965 requires the EU to do the normalization of GL rectangle
1355 * texture coordinates. We use the program parameter state
1356 * tracking to get the scaling factor.
1358 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1359 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1360 int tokens
[STATE_LENGTH
] = {
1362 STATE_TEXRECT_SCALE
,
1368 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
1370 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
+ 1] =
1373 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1374 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1375 GLuint index
= _mesa_add_state_reference(params
,
1376 (gl_state_index
*)tokens
);
1378 this->param_index
[c
->prog_data
.nr_params
] = index
;
1379 this->param_offset
[c
->prog_data
.nr_params
] = 0;
1380 c
->prog_data
.nr_params
++;
1381 this->param_index
[c
->prog_data
.nr_params
] = index
;
1382 this->param_offset
[c
->prog_data
.nr_params
] = 1;
1383 c
->prog_data
.nr_params
++;
1385 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1386 fs_reg src
= coordinate
;
1389 emit(BRW_OPCODE_MUL
, dst
, src
, scale_x
);
1392 emit(BRW_OPCODE_MUL
, dst
, src
, scale_y
);
1395 /* Writemasking doesn't eliminate channels on SIMD8 texture
1396 * samples, so don't worry about them.
1398 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1400 if (intel
->gen
< 5) {
1401 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1403 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1406 /* If there's an offset, we already set up m1. To avoid the implied move,
1407 * use the null register. Otherwise, we want an implied move from g0.
1409 if (ir
->offset
!= NULL
)
1410 inst
->src
[0] = fs_reg(brw_null_reg());
1412 inst
->src
[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
));
1414 inst
->sampler
= sampler
;
1418 if (ir
->shadow_comparitor
)
1419 inst
->shadow_compare
= true;
1421 if (ir
->type
== glsl_type::float_type
) {
1422 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1423 assert(ir
->sampler
->type
->sampler_shadow
);
1424 } else if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1425 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1427 for (int i
= 0; i
< 4; i
++) {
1428 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1429 fs_reg l
= swizzle_dst
;
1432 if (swiz
== SWIZZLE_ZERO
) {
1433 emit(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
));
1434 } else if (swiz
== SWIZZLE_ONE
) {
1435 emit(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
));
1438 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1439 emit(BRW_OPCODE_MOV
, l
, r
);
1442 this->result
= swizzle_dst
;
1447 fs_visitor::visit(ir_swizzle
*ir
)
1449 ir
->val
->accept(this);
1450 fs_reg val
= this->result
;
1452 if (ir
->type
->vector_elements
== 1) {
1453 this->result
.reg_offset
+= ir
->mask
.x
;
1457 fs_reg result
= fs_reg(this, ir
->type
);
1458 this->result
= result
;
1460 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1461 fs_reg channel
= val
;
1479 channel
.reg_offset
+= swiz
;
1480 emit(BRW_OPCODE_MOV
, result
, channel
);
1481 result
.reg_offset
++;
1486 fs_visitor::visit(ir_discard
*ir
)
1488 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1490 assert(ir
->condition
== NULL
); /* FINISHME */
1492 emit(FS_OPCODE_DISCARD_NOT
, temp
, reg_null_d
);
1493 emit(FS_OPCODE_DISCARD_AND
, reg_null_d
, temp
);
1494 kill_emitted
= true;
1498 fs_visitor::visit(ir_constant
*ir
)
1500 /* Set this->result to reg at the bottom of the function because some code
1501 * paths will cause this visitor to be applied to other fields. This will
1502 * cause the value stored in this->result to be modified.
1504 * Make reg constant so that it doesn't get accidentally modified along the
1505 * way. Yes, I actually had this problem. :(
1507 const fs_reg
reg(this, ir
->type
);
1508 fs_reg dst_reg
= reg
;
1510 if (ir
->type
->is_array()) {
1511 const unsigned size
= type_size(ir
->type
->fields
.array
);
1513 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1514 ir
->array_elements
[i
]->accept(this);
1515 fs_reg src_reg
= this->result
;
1517 dst_reg
.type
= src_reg
.type
;
1518 for (unsigned j
= 0; j
< size
; j
++) {
1519 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1520 src_reg
.reg_offset
++;
1521 dst_reg
.reg_offset
++;
1524 } else if (ir
->type
->is_record()) {
1525 foreach_list(node
, &ir
->components
) {
1526 ir_instruction
*const field
= (ir_instruction
*) node
;
1527 const unsigned size
= type_size(field
->type
);
1529 field
->accept(this);
1530 fs_reg src_reg
= this->result
;
1532 dst_reg
.type
= src_reg
.type
;
1533 for (unsigned j
= 0; j
< size
; j
++) {
1534 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1535 src_reg
.reg_offset
++;
1536 dst_reg
.reg_offset
++;
1540 const unsigned size
= type_size(ir
->type
);
1542 for (unsigned i
= 0; i
< size
; i
++) {
1543 switch (ir
->type
->base_type
) {
1544 case GLSL_TYPE_FLOAT
:
1545 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.f
[i
]));
1547 case GLSL_TYPE_UINT
:
1548 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.u
[i
]));
1551 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.i
[i
]));
1553 case GLSL_TYPE_BOOL
:
1554 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg((int)ir
->value
.b
[i
]));
1557 assert(!"Non-float/uint/int/bool constant");
1559 dst_reg
.reg_offset
++;
1567 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1569 ir_expression
*expr
= ir
->as_expression();
1575 assert(expr
->get_num_operands() <= 2);
1576 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1577 assert(expr
->operands
[i
]->type
->is_scalar());
1579 expr
->operands
[i
]->accept(this);
1580 op
[i
] = this->result
;
1583 switch (expr
->operation
) {
1584 case ir_unop_logic_not
:
1585 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1));
1586 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1589 case ir_binop_logic_xor
:
1590 inst
= emit(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]);
1591 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1594 case ir_binop_logic_or
:
1595 inst
= emit(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]);
1596 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1599 case ir_binop_logic_and
:
1600 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]);
1601 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1605 if (intel
->gen
>= 6) {
1606 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0.0f
));
1608 inst
= emit(BRW_OPCODE_MOV
, reg_null_f
, op
[0]);
1610 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1614 if (intel
->gen
>= 6) {
1615 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0));
1617 inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, op
[0]);
1619 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1622 case ir_binop_greater
:
1623 case ir_binop_gequal
:
1625 case ir_binop_lequal
:
1626 case ir_binop_equal
:
1627 case ir_binop_all_equal
:
1628 case ir_binop_nequal
:
1629 case ir_binop_any_nequal
:
1630 inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, op
[0], op
[1]);
1631 inst
->conditional_mod
=
1632 brw_conditional_for_comparison(expr
->operation
);
1636 assert(!"not reached");
1645 if (intel
->gen
>= 6) {
1646 fs_inst
*inst
= emit(BRW_OPCODE_AND
, reg_null_d
, this->result
, fs_reg(1));
1647 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1649 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, this->result
);
1650 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1655 * Emit a gen6 IF statement with the comparison folded into the IF
1659 fs_visitor::emit_if_gen6(ir_if
*ir
)
1661 ir_expression
*expr
= ir
->condition
->as_expression();
1668 assert(expr
->get_num_operands() <= 2);
1669 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1670 assert(expr
->operands
[i
]->type
->is_scalar());
1672 expr
->operands
[i
]->accept(this);
1673 op
[i
] = this->result
;
1676 switch (expr
->operation
) {
1677 case ir_unop_logic_not
:
1678 inst
= emit(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(0));
1679 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1682 case ir_binop_logic_xor
:
1683 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1684 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1687 case ir_binop_logic_or
:
1688 temp
= fs_reg(this, glsl_type::bool_type
);
1689 emit(BRW_OPCODE_OR
, temp
, op
[0], op
[1]);
1690 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1691 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1694 case ir_binop_logic_and
:
1695 temp
= fs_reg(this, glsl_type::bool_type
);
1696 emit(BRW_OPCODE_AND
, temp
, op
[0], op
[1]);
1697 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1698 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1702 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1703 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1707 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1708 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1711 case ir_binop_greater
:
1712 case ir_binop_gequal
:
1714 case ir_binop_lequal
:
1715 case ir_binop_equal
:
1716 case ir_binop_all_equal
:
1717 case ir_binop_nequal
:
1718 case ir_binop_any_nequal
:
1719 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1720 inst
->conditional_mod
=
1721 brw_conditional_for_comparison(expr
->operation
);
1724 assert(!"not reached");
1725 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1726 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1733 ir
->condition
->accept(this);
1735 fs_inst
*inst
= emit(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0));
1736 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1740 fs_visitor::visit(ir_if
*ir
)
1744 /* Don't point the annotation at the if statement, because then it plus
1745 * the then and else blocks get printed.
1747 this->base_ir
= ir
->condition
;
1749 if (intel
->gen
>= 6) {
1752 emit_bool_to_cond_code(ir
->condition
);
1754 inst
= emit(BRW_OPCODE_IF
);
1755 inst
->predicated
= true;
1758 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1759 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1765 if (!ir
->else_instructions
.is_empty()) {
1766 emit(BRW_OPCODE_ELSE
);
1768 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1769 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1776 emit(BRW_OPCODE_ENDIF
);
1780 fs_visitor::visit(ir_loop
*ir
)
1782 fs_reg counter
= reg_undef
;
1785 this->base_ir
= ir
->counter
;
1786 ir
->counter
->accept(this);
1787 counter
= *(variable_storage(ir
->counter
));
1790 this->base_ir
= ir
->from
;
1791 ir
->from
->accept(this);
1793 emit(BRW_OPCODE_MOV
, counter
, this->result
);
1797 emit(BRW_OPCODE_DO
);
1800 this->base_ir
= ir
->to
;
1801 ir
->to
->accept(this);
1803 fs_inst
*inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, counter
, this->result
);
1804 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->cmp
);
1806 inst
= emit(BRW_OPCODE_BREAK
);
1807 inst
->predicated
= true;
1810 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1811 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1817 if (ir
->increment
) {
1818 this->base_ir
= ir
->increment
;
1819 ir
->increment
->accept(this);
1820 emit(BRW_OPCODE_ADD
, counter
, counter
, this->result
);
1823 emit(BRW_OPCODE_WHILE
);
1827 fs_visitor::visit(ir_loop_jump
*ir
)
1830 case ir_loop_jump::jump_break
:
1831 emit(BRW_OPCODE_BREAK
);
1833 case ir_loop_jump::jump_continue
:
1834 emit(BRW_OPCODE_CONTINUE
);
1840 fs_visitor::visit(ir_call
*ir
)
1842 assert(!"FINISHME");
1846 fs_visitor::visit(ir_return
*ir
)
1848 assert(!"FINISHME");
1852 fs_visitor::visit(ir_function
*ir
)
1854 /* Ignore function bodies other than main() -- we shouldn't see calls to
1855 * them since they should all be inlined before we get to ir_to_mesa.
1857 if (strcmp(ir
->name
, "main") == 0) {
1858 const ir_function_signature
*sig
;
1861 sig
= ir
->matching_signature(&empty
);
1865 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1866 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1875 fs_visitor::visit(ir_function_signature
*ir
)
1877 assert(!"not reached");
1882 fs_visitor::emit(fs_inst inst
)
1884 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1887 list_inst
->annotation
= this->current_annotation
;
1888 list_inst
->ir
= this->base_ir
;
1890 this->instructions
.push_tail(list_inst
);
1895 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1897 fs_visitor::emit_dummy_fs()
1899 /* Everyone's favorite color. */
1900 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 2), fs_reg(1.0f
));
1901 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 3), fs_reg(0.0f
));
1902 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 4), fs_reg(1.0f
));
1903 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 5), fs_reg(0.0f
));
1906 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
1907 write
->base_mrf
= 0;
1910 /* The register location here is relative to the start of the URB
1911 * data. It will get adjusted to be a real location before
1912 * generate_code() time.
1915 fs_visitor::interp_reg(int location
, int channel
)
1917 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1918 int stride
= (channel
& 1) * 4;
1920 assert(urb_setup
[location
] != -1);
1922 return brw_vec1_grf(regnr
, stride
);
1925 /** Emits the interpolation for the varying inputs. */
1927 fs_visitor::emit_interpolation_setup_gen4()
1929 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1931 this->current_annotation
= "compute pixel centers";
1932 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1933 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1934 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1935 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1936 emit(BRW_OPCODE_ADD
,
1938 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1939 fs_reg(brw_imm_v(0x10101010)));
1940 emit(BRW_OPCODE_ADD
,
1942 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1943 fs_reg(brw_imm_v(0x11001100)));
1945 this->current_annotation
= "compute pixel deltas from v0";
1947 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1948 this->delta_y
= this->delta_x
;
1949 this->delta_y
.reg_offset
++;
1951 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1952 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1954 emit(BRW_OPCODE_ADD
, this->delta_x
,
1955 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0))));
1956 emit(BRW_OPCODE_ADD
, this->delta_y
,
1957 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1))));
1959 this->current_annotation
= "compute pos.w and 1/pos.w";
1960 /* Compute wpos.w. It's always in our setup, since it's needed to
1961 * interpolate the other attributes.
1963 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1964 emit(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1965 interp_reg(FRAG_ATTRIB_WPOS
, 3));
1966 /* Compute the pixel 1/W value from wpos.w. */
1967 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1968 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1969 this->current_annotation
= NULL
;
1972 /** Emits the interpolation for the varying inputs. */
1974 fs_visitor::emit_interpolation_setup_gen6()
1976 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1978 /* If the pixel centers end up used, the setup is the same as for gen4. */
1979 this->current_annotation
= "compute pixel centers";
1980 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1981 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1982 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1983 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1984 emit(BRW_OPCODE_ADD
,
1986 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1987 fs_reg(brw_imm_v(0x10101010)));
1988 emit(BRW_OPCODE_ADD
,
1990 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1991 fs_reg(brw_imm_v(0x11001100)));
1993 /* As of gen6, we can no longer mix float and int sources. We have
1994 * to turn the integer pixel centers into floats for their actual
1997 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1998 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1999 emit(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
);
2000 emit(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
);
2002 this->current_annotation
= "compute 1/pos.w";
2003 this->wpos_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
2004 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
2005 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
2007 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
2008 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
2010 this->current_annotation
= NULL
;
2014 fs_visitor::emit_fb_writes()
2016 this->current_annotation
= "FB write header";
2017 GLboolean header_present
= GL_TRUE
;
2020 if (intel
->gen
>= 6 &&
2021 !this->kill_emitted
&&
2022 c
->key
.nr_color_regions
== 1) {
2023 header_present
= false;
2026 if (header_present
) {
2031 if (c
->aa_dest_stencil_reg
) {
2032 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2033 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0)));
2036 /* Reserve space for color. It'll be filled in per MRT below. */
2040 if (c
->source_depth_to_render_target
) {
2041 if (c
->computes_depth
) {
2042 /* Hand over gl_FragDepth. */
2043 assert(this->frag_depth
);
2044 fs_reg depth
= *(variable_storage(this->frag_depth
));
2046 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
);
2048 /* Pass through the payload depth. */
2049 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2050 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0)));
2054 if (c
->dest_depth_reg
) {
2055 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2056 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0)));
2059 fs_reg color
= reg_undef
;
2060 if (this->frag_color
)
2061 color
= *(variable_storage(this->frag_color
));
2062 else if (this->frag_data
) {
2063 color
= *(variable_storage(this->frag_data
));
2064 color
.type
= BRW_REGISTER_TYPE_F
;
2067 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2068 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2069 "FB write target %d",
2071 if (this->frag_color
|| this->frag_data
) {
2072 for (int i
= 0; i
< 4; i
++) {
2073 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, color_mrf
+ i
), color
);
2078 if (this->frag_color
)
2079 color
.reg_offset
-= 4;
2081 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2082 inst
->target
= target
;
2085 if (target
== c
->key
.nr_color_regions
- 1)
2087 inst
->header_present
= header_present
;
2090 if (c
->key
.nr_color_regions
== 0) {
2091 if (c
->key
.alpha_test
&& (this->frag_color
|| this->frag_data
)) {
2092 /* If the alpha test is enabled but there's no color buffer,
2093 * we still need to send alpha out the pipeline to our null
2096 color
.reg_offset
+= 3;
2097 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, color_mrf
+ 3), color
);
2100 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2104 inst
->header_present
= header_present
;
2107 this->current_annotation
= NULL
;
2111 fs_visitor::generate_fb_write(fs_inst
*inst
)
2113 GLboolean eot
= inst
->eot
;
2114 struct brw_reg implied_header
;
2116 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
2119 brw_push_insn_state(p
);
2120 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2121 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2123 if (inst
->header_present
) {
2124 if (intel
->gen
>= 6) {
2126 brw_message_reg(inst
->base_mrf
),
2127 brw_vec8_grf(0, 0));
2129 if (inst
->target
> 0) {
2130 /* Set the render target index for choosing BLEND_STATE. */
2131 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 2),
2132 BRW_REGISTER_TYPE_UD
),
2133 brw_imm_ud(inst
->target
));
2136 /* Clear viewport index, render target array index. */
2137 brw_AND(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 0),
2138 BRW_REGISTER_TYPE_UD
),
2139 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2140 brw_imm_ud(0xf7ff));
2142 implied_header
= brw_null_reg();
2144 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2148 brw_message_reg(inst
->base_mrf
+ 1),
2149 brw_vec8_grf(1, 0));
2151 implied_header
= brw_null_reg();
2154 brw_pop_insn_state(p
);
2157 8, /* dispatch_width */
2158 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
2165 inst
->header_present
);
2169 fs_visitor::generate_linterp(fs_inst
*inst
,
2170 struct brw_reg dst
, struct brw_reg
*src
)
2172 struct brw_reg delta_x
= src
[0];
2173 struct brw_reg delta_y
= src
[1];
2174 struct brw_reg interp
= src
[2];
2177 delta_y
.nr
== delta_x
.nr
+ 1 &&
2178 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2179 brw_PLN(p
, dst
, interp
, delta_x
);
2181 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2182 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2187 fs_visitor::generate_math(fs_inst
*inst
,
2188 struct brw_reg dst
, struct brw_reg
*src
)
2192 switch (inst
->opcode
) {
2194 op
= BRW_MATH_FUNCTION_INV
;
2197 op
= BRW_MATH_FUNCTION_RSQ
;
2199 case FS_OPCODE_SQRT
:
2200 op
= BRW_MATH_FUNCTION_SQRT
;
2202 case FS_OPCODE_EXP2
:
2203 op
= BRW_MATH_FUNCTION_EXP
;
2205 case FS_OPCODE_LOG2
:
2206 op
= BRW_MATH_FUNCTION_LOG
;
2209 op
= BRW_MATH_FUNCTION_POW
;
2212 op
= BRW_MATH_FUNCTION_SIN
;
2215 op
= BRW_MATH_FUNCTION_COS
;
2218 assert(!"not reached: unknown math function");
2223 if (intel
->gen
>= 6) {
2224 assert(inst
->mlen
== 0);
2226 if (inst
->opcode
== FS_OPCODE_POW
) {
2227 brw_math2(p
, dst
, op
, src
[0], src
[1]);
2231 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2232 BRW_MATH_SATURATE_NONE
,
2234 BRW_MATH_DATA_VECTOR
,
2235 BRW_MATH_PRECISION_FULL
);
2238 assert(inst
->mlen
>= 1);
2242 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2243 BRW_MATH_SATURATE_NONE
,
2244 inst
->base_mrf
, src
[0],
2245 BRW_MATH_DATA_VECTOR
,
2246 BRW_MATH_PRECISION_FULL
);
2251 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2255 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2257 if (intel
->gen
>= 5) {
2258 switch (inst
->opcode
) {
2260 if (inst
->shadow_compare
) {
2261 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
2263 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
2267 if (inst
->shadow_compare
) {
2268 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
2270 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
2274 if (inst
->shadow_compare
) {
2275 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
2277 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
2281 assert(!"TXD isn't supported on gen5+ yet.");
2285 switch (inst
->opcode
) {
2287 /* Note that G45 and older determines shadow compare and dispatch width
2288 * from message length for most messages.
2290 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2291 if (inst
->shadow_compare
) {
2292 assert(inst
->mlen
== 6);
2294 assert(inst
->mlen
<= 4);
2298 if (inst
->shadow_compare
) {
2299 assert(inst
->mlen
== 6);
2300 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
2302 assert(inst
->mlen
== 9);
2303 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2304 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2308 if (inst
->shadow_compare
) {
2309 assert(inst
->mlen
== 6);
2310 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
2312 assert(inst
->mlen
== 9);
2313 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
2314 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2318 assert(!"TXD isn't supported on gen4 yet.");
2322 assert(msg_type
!= -1);
2324 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2330 retype(dst
, BRW_REGISTER_TYPE_UW
),
2333 SURF_INDEX_TEXTURE(inst
->sampler
),
2345 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2348 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2350 * and we're trying to produce:
2353 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2354 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2355 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2356 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2357 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2358 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2359 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2360 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2362 * and add another set of two more subspans if in 16-pixel dispatch mode.
2364 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2365 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2366 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2367 * between each other. We could probably do it like ddx and swizzle the right
2368 * order later, but bail for now and just produce
2369 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2372 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2374 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2375 BRW_REGISTER_TYPE_F
,
2376 BRW_VERTICAL_STRIDE_2
,
2378 BRW_HORIZONTAL_STRIDE_0
,
2379 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2380 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2381 BRW_REGISTER_TYPE_F
,
2382 BRW_VERTICAL_STRIDE_2
,
2384 BRW_HORIZONTAL_STRIDE_0
,
2385 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2386 brw_ADD(p
, dst
, src0
, negate(src1
));
2390 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2392 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2393 BRW_REGISTER_TYPE_F
,
2394 BRW_VERTICAL_STRIDE_4
,
2396 BRW_HORIZONTAL_STRIDE_0
,
2397 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2398 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2399 BRW_REGISTER_TYPE_F
,
2400 BRW_VERTICAL_STRIDE_4
,
2402 BRW_HORIZONTAL_STRIDE_0
,
2403 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2404 brw_ADD(p
, dst
, src0
, negate(src1
));
2408 fs_visitor::generate_discard_not(fs_inst
*inst
, struct brw_reg mask
)
2410 if (intel
->gen
>= 6) {
2411 /* Gen6 no longer has the mask reg for us to just read the
2412 * active channels from. However, cmp updates just the channels
2413 * of the flag reg that are enabled, so we can get at the
2414 * channel enables that way. In this step, make a reg of ones
2417 brw_MOV(p
, mask
, brw_imm_ud(1));
2419 brw_push_insn_state(p
);
2420 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2421 brw_NOT(p
, mask
, brw_mask_reg(1)); /* IMASK */
2422 brw_pop_insn_state(p
);
2427 fs_visitor::generate_discard_and(fs_inst
*inst
, struct brw_reg mask
)
2429 if (intel
->gen
>= 6) {
2430 struct brw_reg f0
= brw_flag_reg();
2431 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
2433 brw_push_insn_state(p
);
2434 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2435 brw_MOV(p
, f0
, brw_imm_uw(0xffff)); /* inactive channels undiscarded */
2436 brw_pop_insn_state(p
);
2438 brw_CMP(p
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
2439 BRW_CONDITIONAL_Z
, mask
, brw_imm_ud(0)); /* active channels fail test */
2440 /* Undo CMP's whacking of predication*/
2441 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2443 brw_push_insn_state(p
);
2444 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2445 brw_AND(p
, g1
, f0
, g1
);
2446 brw_pop_insn_state(p
);
2448 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2450 mask
= brw_uw1_reg(mask
.file
, mask
.nr
, 0);
2452 brw_push_insn_state(p
);
2453 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2454 brw_AND(p
, g0
, mask
, g0
);
2455 brw_pop_insn_state(p
);
2460 fs_visitor::generate_spill(fs_inst
*inst
, struct brw_reg src
)
2462 assert(inst
->mlen
!= 0);
2465 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
2466 retype(src
, BRW_REGISTER_TYPE_UD
));
2467 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
), 1,
2472 fs_visitor::generate_unspill(fs_inst
*inst
, struct brw_reg dst
)
2474 assert(inst
->mlen
!= 0);
2476 /* Clear any post destination dependencies that would be ignored by
2477 * the block read. See the B-Spec for pre-gen5 send instruction.
2479 * This could use a better solution, since texture sampling and
2480 * math reads could potentially run into it as well -- anywhere
2481 * that we have a SEND with a destination that is a register that
2482 * was written but not read within the last N instructions (what's
2483 * N? unsure). This is rare because of dead code elimination, but
2486 if (intel
->gen
== 4 && !intel
->is_g4x
)
2487 brw_MOV(p
, brw_null_reg(), dst
);
2489 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
), 1,
2492 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2493 /* gen4 errata: destination from a send can't be used as a
2494 * destination until it's been read. Just read it so we don't
2497 brw_MOV(p
, brw_null_reg(), dst
);
2503 fs_visitor::generate_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
)
2505 assert(inst
->mlen
!= 0);
2507 /* Clear any post destination dependencies that would be ignored by
2508 * the block read. See the B-Spec for pre-gen5 send instruction.
2510 * This could use a better solution, since texture sampling and
2511 * math reads could potentially run into it as well -- anywhere
2512 * that we have a SEND with a destination that is a register that
2513 * was written but not read within the last N instructions (what's
2514 * N? unsure). This is rare because of dead code elimination, but
2517 if (intel
->gen
== 4 && !intel
->is_g4x
)
2518 brw_MOV(p
, brw_null_reg(), dst
);
2520 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
2521 inst
->offset
, SURF_INDEX_FRAG_CONST_BUFFER
);
2523 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2524 /* gen4 errata: destination from a send can't be used as a
2525 * destination until it's been read. Just read it so we don't
2528 brw_MOV(p
, brw_null_reg(), dst
);
2533 * To be called after the last _mesa_add_state_reference() call, to
2534 * set up prog_data.param[] for assign_curb_setup() and
2535 * setup_pull_constants().
2538 fs_visitor::setup_paramvalues_refs()
2540 /* Set up the pointers to ParamValues now that that array is finalized. */
2541 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
2542 c
->prog_data
.param
[i
] =
2543 fp
->Base
.Parameters
->ParameterValues
[this->param_index
[i
]] +
2544 this->param_offset
[i
];
2549 fs_visitor::assign_curb_setup()
2551 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
2552 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2554 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2555 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2556 fs_inst
*inst
= (fs_inst
*)iter
.get();
2558 for (unsigned int i
= 0; i
< 3; i
++) {
2559 if (inst
->src
[i
].file
== UNIFORM
) {
2560 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2561 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2565 inst
->src
[i
].file
= FIXED_HW_REG
;
2566 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
2573 fs_visitor::calculate_urb_setup()
2575 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2580 /* Figure out where each of the incoming setup attributes lands. */
2581 if (intel
->gen
>= 6) {
2582 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2583 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2584 urb_setup
[i
] = urb_next
++;
2588 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2589 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2590 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2593 if (i
>= VERT_RESULT_VAR0
)
2594 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2595 else if (i
<= VERT_RESULT_TEX7
)
2601 urb_setup
[fp_index
] = urb_next
++;
2606 /* Each attribute is 4 setup channels, each of which is half a reg. */
2607 c
->prog_data
.urb_read_length
= urb_next
* 2;
2611 fs_visitor::assign_urb_setup()
2613 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2615 /* Offset all the urb_setup[] index by the actual position of the
2616 * setup regs, now that the location of the constants has been chosen.
2618 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2619 fs_inst
*inst
= (fs_inst
*)iter
.get();
2621 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
2622 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2623 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2626 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
2627 assert(inst
->src
[0].file
== FIXED_HW_REG
);
2628 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
2632 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2636 * Split large virtual GRFs into separate components if we can.
2638 * This is mostly duplicated with what brw_fs_vector_splitting does,
2639 * but that's really conservative because it's afraid of doing
2640 * splitting that doesn't result in real progress after the rest of
2641 * the optimization phases, which would cause infinite looping in
2642 * optimization. We can do it once here, safely. This also has the
2643 * opportunity to split interpolated values, or maybe even uniforms,
2644 * which we don't have at the IR level.
2646 * We want to split, because virtual GRFs are what we register
2647 * allocate and spill (due to contiguousness requirements for some
2648 * instructions), and they're what we naturally generate in the
2649 * codegen process, but most virtual GRFs don't actually need to be
2650 * contiguous sets of GRFs. If we split, we'll end up with reduced
2651 * live intervals and better dead code elimination and coalescing.
2654 fs_visitor::split_virtual_grfs()
2656 int num_vars
= this->virtual_grf_next
;
2657 bool split_grf
[num_vars
];
2658 int new_virtual_grf
[num_vars
];
2660 /* Try to split anything > 0 sized. */
2661 for (int i
= 0; i
< num_vars
; i
++) {
2662 if (this->virtual_grf_sizes
[i
] != 1)
2663 split_grf
[i
] = true;
2665 split_grf
[i
] = false;
2669 /* PLN opcodes rely on the delta_xy being contiguous. */
2670 split_grf
[this->delta_x
.reg
] = false;
2673 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2674 fs_inst
*inst
= (fs_inst
*)iter
.get();
2676 /* Texturing produces 4 contiguous registers, so no splitting. */
2677 if (inst
->is_tex()) {
2678 split_grf
[inst
->dst
.reg
] = false;
2682 /* Allocate new space for split regs. Note that the virtual
2683 * numbers will be contiguous.
2685 for (int i
= 0; i
< num_vars
; i
++) {
2687 new_virtual_grf
[i
] = virtual_grf_alloc(1);
2688 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
2689 int reg
= virtual_grf_alloc(1);
2690 assert(reg
== new_virtual_grf
[i
] + j
- 1);
2693 this->virtual_grf_sizes
[i
] = 1;
2697 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2698 fs_inst
*inst
= (fs_inst
*)iter
.get();
2700 if (inst
->dst
.file
== GRF
&&
2701 split_grf
[inst
->dst
.reg
] &&
2702 inst
->dst
.reg_offset
!= 0) {
2703 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
2704 inst
->dst
.reg_offset
- 1);
2705 inst
->dst
.reg_offset
= 0;
2707 for (int i
= 0; i
< 3; i
++) {
2708 if (inst
->src
[i
].file
== GRF
&&
2709 split_grf
[inst
->src
[i
].reg
] &&
2710 inst
->src
[i
].reg_offset
!= 0) {
2711 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
2712 inst
->src
[i
].reg_offset
- 1);
2713 inst
->src
[i
].reg_offset
= 0;
2717 this->live_intervals_valid
= false;
2721 * Choose accesses from the UNIFORM file to demote to using the pull
2724 * We allow a fragment shader to have more than the specified minimum
2725 * maximum number of fragment shader uniform components (64). If
2726 * there are too many of these, they'd fill up all of register space.
2727 * So, this will push some of them out to the pull constant buffer and
2728 * update the program to load them.
2731 fs_visitor::setup_pull_constants()
2733 /* Only allow 16 registers (128 uniform components) as push constants. */
2734 unsigned int max_uniform_components
= 16 * 8;
2735 if (c
->prog_data
.nr_params
<= max_uniform_components
)
2738 /* Just demote the end of the list. We could probably do better
2739 * here, demoting things that are rarely used in the program first.
2741 int pull_uniform_base
= max_uniform_components
;
2742 int pull_uniform_count
= c
->prog_data
.nr_params
- pull_uniform_base
;
2744 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2745 fs_inst
*inst
= (fs_inst
*)iter
.get();
2747 for (int i
= 0; i
< 3; i
++) {
2748 if (inst
->src
[i
].file
!= UNIFORM
)
2751 int uniform_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2752 if (uniform_nr
< pull_uniform_base
)
2755 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
2756 fs_inst
*pull
= new(mem_ctx
) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
2758 pull
->offset
= ((uniform_nr
- pull_uniform_base
) * 4) & ~15;
2759 pull
->ir
= inst
->ir
;
2760 pull
->annotation
= inst
->annotation
;
2761 pull
->base_mrf
= 14;
2764 inst
->insert_before(pull
);
2766 inst
->src
[i
].file
= GRF
;
2767 inst
->src
[i
].reg
= dst
.reg
;
2768 inst
->src
[i
].reg_offset
= 0;
2769 inst
->src
[i
].smear
= (uniform_nr
- pull_uniform_base
) & 3;
2773 for (int i
= 0; i
< pull_uniform_count
; i
++) {
2774 c
->prog_data
.pull_param
[i
] = c
->prog_data
.param
[pull_uniform_base
+ i
];
2775 c
->prog_data
.pull_param_convert
[i
] =
2776 c
->prog_data
.param_convert
[pull_uniform_base
+ i
];
2778 c
->prog_data
.nr_params
-= pull_uniform_count
;
2779 c
->prog_data
.nr_pull_params
= pull_uniform_count
;
2783 fs_visitor::calculate_live_intervals()
2785 int num_vars
= this->virtual_grf_next
;
2786 int *def
= ralloc_array(mem_ctx
, int, num_vars
);
2787 int *use
= ralloc_array(mem_ctx
, int, num_vars
);
2790 int bb_header_ip
= 0;
2792 if (this->live_intervals_valid
)
2795 for (int i
= 0; i
< num_vars
; i
++) {
2796 def
[i
] = MAX_INSTRUCTION
;
2801 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2802 fs_inst
*inst
= (fs_inst
*)iter
.get();
2804 if (inst
->opcode
== BRW_OPCODE_DO
) {
2805 if (loop_depth
++ == 0)
2807 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2810 if (loop_depth
== 0) {
2811 /* Patches up the use of vars marked for being live across
2814 for (int i
= 0; i
< num_vars
; i
++) {
2815 if (use
[i
] == loop_start
) {
2821 for (unsigned int i
= 0; i
< 3; i
++) {
2822 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2823 int reg
= inst
->src
[i
].reg
;
2825 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2826 def
[reg
] >= bb_header_ip
)) {
2829 def
[reg
] = MIN2(loop_start
, def
[reg
]);
2830 use
[reg
] = loop_start
;
2832 /* Nobody else is going to go smash our start to
2833 * later in the loop now, because def[reg] now
2834 * points before the bb header.
2839 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2840 int reg
= inst
->dst
.reg
;
2842 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2843 !inst
->predicated
)) {
2844 def
[reg
] = MIN2(def
[reg
], ip
);
2846 def
[reg
] = MIN2(def
[reg
], loop_start
);
2853 /* Set the basic block header IP. This is used for determining
2854 * if a complete def of single-register virtual GRF in a loop
2855 * dominates a use in the same basic block. It's a quick way to
2856 * reduce the live interval range of most register used in a
2859 if (inst
->opcode
== BRW_OPCODE_IF
||
2860 inst
->opcode
== BRW_OPCODE_ELSE
||
2861 inst
->opcode
== BRW_OPCODE_ENDIF
||
2862 inst
->opcode
== BRW_OPCODE_DO
||
2863 inst
->opcode
== BRW_OPCODE_WHILE
||
2864 inst
->opcode
== BRW_OPCODE_BREAK
||
2865 inst
->opcode
== BRW_OPCODE_CONTINUE
) {
2870 ralloc_free(this->virtual_grf_def
);
2871 ralloc_free(this->virtual_grf_use
);
2872 this->virtual_grf_def
= def
;
2873 this->virtual_grf_use
= use
;
2875 this->live_intervals_valid
= true;
2879 * Attempts to move immediate constants into the immediate
2880 * constant slot of following instructions.
2882 * Immediate constants are a bit tricky -- they have to be in the last
2883 * operand slot, you can't do abs/negate on them,
2887 fs_visitor::propagate_constants()
2889 bool progress
= false;
2891 calculate_live_intervals();
2893 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2894 fs_inst
*inst
= (fs_inst
*)iter
.get();
2896 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2898 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2899 inst
->dst
.type
!= inst
->src
[0].type
)
2902 /* Don't bother with cases where we should have had the
2903 * operation on the constant folded in GLSL already.
2908 /* Found a move of a constant to a GRF. Find anything else using the GRF
2909 * before it's written, and replace it with the constant if we can.
2911 exec_list_iterator scan_iter
= iter
;
2913 for (; scan_iter
.has_next(); scan_iter
.next()) {
2914 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2916 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2917 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2918 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2919 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2923 for (int i
= 2; i
>= 0; i
--) {
2924 if (scan_inst
->src
[i
].file
!= GRF
||
2925 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2926 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2929 /* Don't bother with cases where we should have had the
2930 * operation on the constant folded in GLSL already.
2932 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2935 switch (scan_inst
->opcode
) {
2936 case BRW_OPCODE_MOV
:
2937 scan_inst
->src
[i
] = inst
->src
[0];
2941 case BRW_OPCODE_MUL
:
2942 case BRW_OPCODE_ADD
:
2944 scan_inst
->src
[i
] = inst
->src
[0];
2946 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2947 /* Fit this constant in by commuting the operands */
2948 scan_inst
->src
[0] = scan_inst
->src
[1];
2949 scan_inst
->src
[1] = inst
->src
[0];
2953 case BRW_OPCODE_CMP
:
2954 case BRW_OPCODE_SEL
:
2956 scan_inst
->src
[i
] = inst
->src
[0];
2962 if (scan_inst
->dst
.file
== GRF
&&
2963 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2964 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2965 scan_inst
->is_tex())) {
2972 this->live_intervals_valid
= false;
2977 * Must be called after calculate_live_intervales() to remove unused
2978 * writes to registers -- register allocation will fail otherwise
2979 * because something deffed but not used won't be considered to
2980 * interfere with other regs.
2983 fs_visitor::dead_code_eliminate()
2985 bool progress
= false;
2988 calculate_live_intervals();
2990 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2991 fs_inst
*inst
= (fs_inst
*)iter
.get();
2993 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
3002 live_intervals_valid
= false;
3008 fs_visitor::register_coalesce()
3010 bool progress
= false;
3014 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3015 fs_inst
*inst
= (fs_inst
*)iter
.get();
3017 /* Make sure that we dominate the instructions we're going to
3018 * scan for interfering with our coalescing, or we won't have
3019 * scanned enough to see if anything interferes with our
3020 * coalescing. We don't dominate the following instructions if
3021 * we're in a loop or an if block.
3023 switch (inst
->opcode
) {
3027 case BRW_OPCODE_WHILE
:
3033 case BRW_OPCODE_ENDIF
:
3037 if (loop_depth
|| if_depth
)
3040 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3043 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
3044 inst
->dst
.type
!= inst
->src
[0].type
)
3047 bool has_source_modifiers
= inst
->src
[0].abs
|| inst
->src
[0].negate
;
3049 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
3050 * them: check for no writes to either one until the exit of the
3053 bool interfered
= false;
3054 exec_list_iterator scan_iter
= iter
;
3056 for (; scan_iter
.has_next(); scan_iter
.next()) {
3057 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
3059 if (scan_inst
->dst
.file
== GRF
) {
3060 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
3061 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
3062 scan_inst
->is_tex())) {
3066 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
3067 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
3068 scan_inst
->is_tex())) {
3074 /* The gen6 MATH instruction can't handle source modifiers, so avoid
3075 * coalescing those for now. We should do something more specific.
3077 if (intel
->gen
== 6 && scan_inst
->is_math() && has_source_modifiers
) {
3086 /* Rewrite the later usage to point at the source of the move to
3089 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
3091 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
3093 for (int i
= 0; i
< 3; i
++) {
3094 if (scan_inst
->src
[i
].file
== GRF
&&
3095 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
3096 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
3097 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
3098 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
3099 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
3100 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
3101 scan_inst
->src
[i
].smear
= inst
->src
[0].smear
;
3111 live_intervals_valid
= false;
3118 fs_visitor::compute_to_mrf()
3120 bool progress
= false;
3123 calculate_live_intervals();
3125 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3126 fs_inst
*inst
= (fs_inst
*)iter
.get();
3131 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3133 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
3134 inst
->dst
.type
!= inst
->src
[0].type
||
3135 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
3138 /* Can't compute-to-MRF this GRF if someone else was going to
3141 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
3144 /* Found a move of a GRF to a MRF. Let's see if we can go
3145 * rewrite the thing that made this GRF to write into the MRF.
3148 for (scan_inst
= (fs_inst
*)inst
->prev
;
3149 scan_inst
->prev
!= NULL
;
3150 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
3151 if (scan_inst
->dst
.file
== GRF
&&
3152 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
3153 /* Found the last thing to write our reg we want to turn
3154 * into a compute-to-MRF.
3157 if (scan_inst
->is_tex()) {
3158 /* texturing writes several continuous regs, so we can't
3159 * compute-to-mrf that.
3164 /* If it's predicated, it (probably) didn't populate all
3167 if (scan_inst
->predicated
)
3170 /* SEND instructions can't have MRF as a destination. */
3171 if (scan_inst
->mlen
)
3174 if (intel
->gen
>= 6) {
3175 /* gen6 math instructions must have the destination be
3176 * GRF, so no compute-to-MRF for them.
3178 if (scan_inst
->is_math()) {
3183 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
3184 /* Found the creator of our MRF's source value. */
3185 scan_inst
->dst
.file
= MRF
;
3186 scan_inst
->dst
.hw_reg
= inst
->dst
.hw_reg
;
3187 scan_inst
->saturate
|= inst
->saturate
;
3194 /* We don't handle flow control here. Most computation of
3195 * values that end up in MRFs are shortly before the MRF
3198 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
3199 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
3200 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
3201 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
3205 /* You can't read from an MRF, so if someone else reads our
3206 * MRF's source GRF that we wanted to rewrite, that stops us.
3208 bool interfered
= false;
3209 for (int i
= 0; i
< 3; i
++) {
3210 if (scan_inst
->src
[i
].file
== GRF
&&
3211 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
3212 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
3219 if (scan_inst
->dst
.file
== MRF
&&
3220 scan_inst
->dst
.hw_reg
== inst
->dst
.hw_reg
) {
3221 /* Somebody else wrote our MRF here, so we can't can't
3222 * compute-to-MRF before that.
3227 if (scan_inst
->mlen
> 0) {
3228 /* Found a SEND instruction, which means that there are
3229 * live values in MRFs from base_mrf to base_mrf +
3230 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3233 if (inst
->dst
.hw_reg
>= scan_inst
->base_mrf
&&
3234 inst
->dst
.hw_reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
3245 * Walks through basic blocks, locking for repeated MRF writes and
3246 * removing the later ones.
3249 fs_visitor::remove_duplicate_mrf_writes()
3251 fs_inst
*last_mrf_move
[16];
3252 bool progress
= false;
3254 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3256 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3257 fs_inst
*inst
= (fs_inst
*)iter
.get();
3259 switch (inst
->opcode
) {
3261 case BRW_OPCODE_WHILE
:
3263 case BRW_OPCODE_ELSE
:
3264 case BRW_OPCODE_ENDIF
:
3265 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3271 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3272 inst
->dst
.file
== MRF
) {
3273 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.hw_reg
];
3274 if (prev_inst
&& inst
->equals(prev_inst
)) {
3281 /* Clear out the last-write records for MRFs that were overwritten. */
3282 if (inst
->dst
.file
== MRF
) {
3283 last_mrf_move
[inst
->dst
.hw_reg
] = NULL
;
3286 if (inst
->mlen
> 0) {
3287 /* Found a SEND instruction, which will include two or fewer
3288 * implied MRF writes. We could do better here.
3290 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3291 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3295 /* Clear out any MRF move records whose sources got overwritten. */
3296 if (inst
->dst
.file
== GRF
) {
3297 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
3298 if (last_mrf_move
[i
] &&
3299 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
3300 last_mrf_move
[i
] = NULL
;
3305 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3306 inst
->dst
.file
== MRF
&&
3307 inst
->src
[0].file
== GRF
&&
3308 !inst
->predicated
) {
3309 last_mrf_move
[inst
->dst
.hw_reg
] = inst
;
3317 fs_visitor::virtual_grf_interferes(int a
, int b
)
3319 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
3320 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
3322 /* We can't handle dead register writes here, without iterating
3323 * over the whole instruction stream to find every single dead
3324 * write to that register to compare to the live interval of the
3325 * other register. Just assert that dead_code_eliminate() has been
3328 assert((this->virtual_grf_use
[a
] != -1 ||
3329 this->virtual_grf_def
[a
] == MAX_INSTRUCTION
) &&
3330 (this->virtual_grf_use
[b
] != -1 ||
3331 this->virtual_grf_def
[b
] == MAX_INSTRUCTION
));
3336 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
3338 struct brw_reg brw_reg
;
3340 switch (reg
->file
) {
3344 if (reg
->smear
== -1) {
3345 brw_reg
= brw_vec8_reg(reg
->file
,
3348 brw_reg
= brw_vec1_reg(reg
->file
,
3349 reg
->hw_reg
, reg
->smear
);
3351 brw_reg
= retype(brw_reg
, reg
->type
);
3354 switch (reg
->type
) {
3355 case BRW_REGISTER_TYPE_F
:
3356 brw_reg
= brw_imm_f(reg
->imm
.f
);
3358 case BRW_REGISTER_TYPE_D
:
3359 brw_reg
= brw_imm_d(reg
->imm
.i
);
3361 case BRW_REGISTER_TYPE_UD
:
3362 brw_reg
= brw_imm_ud(reg
->imm
.u
);
3365 assert(!"not reached");
3366 brw_reg
= brw_null_reg();
3371 brw_reg
= reg
->fixed_hw_reg
;
3374 /* Probably unused. */
3375 brw_reg
= brw_null_reg();
3378 assert(!"not reached");
3379 brw_reg
= brw_null_reg();
3382 assert(!"not reached");
3383 brw_reg
= brw_null_reg();
3387 brw_reg
= brw_abs(brw_reg
);
3389 brw_reg
= negate(brw_reg
);
3395 fs_visitor::generate_code()
3397 int last_native_inst
= 0;
3398 const char *last_annotation_string
= NULL
;
3399 ir_instruction
*last_annotation_ir
= NULL
;
3401 int if_stack_array_size
= 16;
3402 int loop_stack_array_size
= 16;
3403 int if_stack_depth
= 0, loop_stack_depth
= 0;
3404 brw_instruction
**if_stack
=
3405 rzalloc_array(this->mem_ctx
, brw_instruction
*, if_stack_array_size
);
3406 brw_instruction
**loop_stack
=
3407 rzalloc_array(this->mem_ctx
, brw_instruction
*, loop_stack_array_size
);
3408 int *if_depth_in_loop
=
3409 rzalloc_array(this->mem_ctx
, int, loop_stack_array_size
);
3412 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3413 printf("Native code for fragment shader %d:\n",
3414 ctx
->Shader
.CurrentFragmentProgram
->Name
);
3417 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3418 fs_inst
*inst
= (fs_inst
*)iter
.get();
3419 struct brw_reg src
[3], dst
;
3421 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3422 if (last_annotation_ir
!= inst
->ir
) {
3423 last_annotation_ir
= inst
->ir
;
3424 if (last_annotation_ir
) {
3426 last_annotation_ir
->print();
3430 if (last_annotation_string
!= inst
->annotation
) {
3431 last_annotation_string
= inst
->annotation
;
3432 if (last_annotation_string
)
3433 printf(" %s\n", last_annotation_string
);
3437 for (unsigned int i
= 0; i
< 3; i
++) {
3438 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
3440 dst
= brw_reg_from_fs_reg(&inst
->dst
);
3442 brw_set_conditionalmod(p
, inst
->conditional_mod
);
3443 brw_set_predicate_control(p
, inst
->predicated
);
3444 brw_set_saturate(p
, inst
->saturate
);
3446 switch (inst
->opcode
) {
3447 case BRW_OPCODE_MOV
:
3448 brw_MOV(p
, dst
, src
[0]);
3450 case BRW_OPCODE_ADD
:
3451 brw_ADD(p
, dst
, src
[0], src
[1]);
3453 case BRW_OPCODE_MUL
:
3454 brw_MUL(p
, dst
, src
[0], src
[1]);
3457 case BRW_OPCODE_FRC
:
3458 brw_FRC(p
, dst
, src
[0]);
3460 case BRW_OPCODE_RNDD
:
3461 brw_RNDD(p
, dst
, src
[0]);
3463 case BRW_OPCODE_RNDE
:
3464 brw_RNDE(p
, dst
, src
[0]);
3466 case BRW_OPCODE_RNDZ
:
3467 brw_RNDZ(p
, dst
, src
[0]);
3470 case BRW_OPCODE_AND
:
3471 brw_AND(p
, dst
, src
[0], src
[1]);
3474 brw_OR(p
, dst
, src
[0], src
[1]);
3476 case BRW_OPCODE_XOR
:
3477 brw_XOR(p
, dst
, src
[0], src
[1]);
3479 case BRW_OPCODE_NOT
:
3480 brw_NOT(p
, dst
, src
[0]);
3482 case BRW_OPCODE_ASR
:
3483 brw_ASR(p
, dst
, src
[0], src
[1]);
3485 case BRW_OPCODE_SHR
:
3486 brw_SHR(p
, dst
, src
[0], src
[1]);
3488 case BRW_OPCODE_SHL
:
3489 brw_SHL(p
, dst
, src
[0], src
[1]);
3492 case BRW_OPCODE_CMP
:
3493 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
3495 case BRW_OPCODE_SEL
:
3496 brw_SEL(p
, dst
, src
[0], src
[1]);
3500 if (inst
->src
[0].file
!= BAD_FILE
) {
3501 assert(intel
->gen
>= 6);
3502 if_stack
[if_stack_depth
] = gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
3504 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
3506 if_depth_in_loop
[loop_stack_depth
]++;
3508 if (if_stack_array_size
<= if_stack_depth
) {
3509 if_stack_array_size
*= 2;
3510 if_stack
= reralloc(this->mem_ctx
, if_stack
, brw_instruction
*,
3511 if_stack_array_size
);
3515 case BRW_OPCODE_ELSE
:
3516 if_stack
[if_stack_depth
- 1] =
3517 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
3519 case BRW_OPCODE_ENDIF
:
3521 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
3522 if_depth_in_loop
[loop_stack_depth
]--;
3526 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
3527 if (loop_stack_array_size
<= loop_stack_depth
) {
3528 loop_stack_array_size
*= 2;
3529 loop_stack
= reralloc(this->mem_ctx
, loop_stack
, brw_instruction
*,
3530 loop_stack_array_size
);
3531 if_depth_in_loop
= reralloc(this->mem_ctx
, if_depth_in_loop
, int,
3532 loop_stack_array_size
);
3534 if_depth_in_loop
[loop_stack_depth
] = 0;
3537 case BRW_OPCODE_BREAK
:
3538 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
3539 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3541 case BRW_OPCODE_CONTINUE
:
3542 /* FINISHME: We need to write the loop instruction support still. */
3543 if (intel
->gen
>= 6)
3544 gen6_CONT(p
, loop_stack
[loop_stack_depth
- 1]);
3546 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
3547 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3550 case BRW_OPCODE_WHILE
: {
3551 struct brw_instruction
*inst0
, *inst1
;
3554 if (intel
->gen
>= 5)
3557 assert(loop_stack_depth
> 0);
3559 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
3560 if (intel
->gen
< 6) {
3561 /* patch all the BREAK/CONT instructions from last BGNLOOP */
3562 while (inst0
> loop_stack
[loop_stack_depth
]) {
3564 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
3565 inst0
->bits3
.if_else
.jump_count
== 0) {
3566 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
3568 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
3569 inst0
->bits3
.if_else
.jump_count
== 0) {
3570 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
3579 case FS_OPCODE_SQRT
:
3580 case FS_OPCODE_EXP2
:
3581 case FS_OPCODE_LOG2
:
3585 generate_math(inst
, dst
, src
);
3587 case FS_OPCODE_CINTERP
:
3588 brw_MOV(p
, dst
, src
[0]);
3590 case FS_OPCODE_LINTERP
:
3591 generate_linterp(inst
, dst
, src
);
3597 generate_tex(inst
, dst
, src
[0]);
3599 case FS_OPCODE_DISCARD_NOT
:
3600 generate_discard_not(inst
, dst
);
3602 case FS_OPCODE_DISCARD_AND
:
3603 generate_discard_and(inst
, src
[0]);
3606 generate_ddx(inst
, dst
, src
[0]);
3609 generate_ddy(inst
, dst
, src
[0]);
3612 case FS_OPCODE_SPILL
:
3613 generate_spill(inst
, src
[0]);
3616 case FS_OPCODE_UNSPILL
:
3617 generate_unspill(inst
, dst
);
3620 case FS_OPCODE_PULL_CONSTANT_LOAD
:
3621 generate_pull_constant_load(inst
, dst
);
3624 case FS_OPCODE_FB_WRITE
:
3625 generate_fb_write(inst
);
3628 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
3629 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
3630 brw_opcodes
[inst
->opcode
].name
);
3632 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
3637 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3638 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
3640 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3641 ((uint32_t *)&p
->store
[i
])[3],
3642 ((uint32_t *)&p
->store
[i
])[2],
3643 ((uint32_t *)&p
->store
[i
])[1],
3644 ((uint32_t *)&p
->store
[i
])[0]);
3646 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3650 last_native_inst
= p
->nr_insn
;
3653 ralloc_free(if_stack
);
3654 ralloc_free(loop_stack
);
3655 ralloc_free(if_depth_in_loop
);
3659 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
3660 * emit issues, it doesn't get the jump distances into the output,
3661 * which is often something we want to debug. So this is here in
3662 * case you're doing that.
3665 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3666 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3667 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3668 ((uint32_t *)&p
->store
[i
])[3],
3669 ((uint32_t *)&p
->store
[i
])[2],
3670 ((uint32_t *)&p
->store
[i
])[1],
3671 ((uint32_t *)&p
->store
[i
])[0]);
3672 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3679 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
3681 struct intel_context
*intel
= &brw
->intel
;
3682 struct gl_context
*ctx
= &intel
->ctx
;
3683 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentFragmentProgram
;
3688 struct brw_shader
*shader
=
3689 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3693 /* We always use 8-wide mode, at least for now. For one, flow
3694 * control only works in 8-wide. Also, when we're fragment shader
3695 * bound, we're almost always under register pressure as well, so
3696 * 8-wide would save us from the performance cliff of spilling
3699 c
->dispatch_width
= 8;
3701 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3702 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3703 _mesa_print_ir(shader
->ir
, NULL
);
3707 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3709 fs_visitor
v(c
, shader
);
3714 v
.calculate_urb_setup();
3716 v
.emit_interpolation_setup_gen4();
3718 v
.emit_interpolation_setup_gen6();
3720 /* Generate FS IR for main(). (the visitor only descends into
3721 * functions called "main").
3723 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3724 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3731 v
.split_virtual_grfs();
3733 v
.setup_paramvalues_refs();
3734 v
.setup_pull_constants();
3740 progress
= v
.remove_duplicate_mrf_writes() || progress
;
3742 progress
= v
.propagate_constants() || progress
;
3743 progress
= v
.register_coalesce() || progress
;
3744 progress
= v
.compute_to_mrf() || progress
;
3745 progress
= v
.dead_code_eliminate() || progress
;
3748 v
.schedule_instructions();
3750 v
.assign_curb_setup();
3751 v
.assign_urb_setup();
3754 /* Debug of register spilling: Go spill everything. */
3755 int virtual_grf_count
= v
.virtual_grf_next
;
3756 for (int i
= 1; i
< virtual_grf_count
; i
++) {
3762 v
.assign_regs_trivial();
3764 while (!v
.assign_regs()) {
3774 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3779 c
->prog_data
.total_grf
= v
.grf_used
;