2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "brw_dead_control_flow.h"
47 #include "main/uniforms.h"
48 #include "brw_fs_live_variables.h"
49 #include "glsl/glsl_types.h"
50 #include "program/sampler.h"
53 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
54 const fs_reg
*src
, unsigned sources
)
56 memset(this, 0, sizeof(*this));
58 this->src
= new fs_reg
[MAX2(sources
, 3)];
59 for (unsigned i
= 0; i
< sources
; i
++)
60 this->src
[i
] = src
[i
];
62 this->opcode
= opcode
;
64 this->sources
= sources
;
65 this->exec_size
= exec_size
;
67 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
69 /* If exec_size == 0, try to guess it from the registers. Since all
70 * manner of things may use hardware registers, we first try to guess
71 * based on GRF registers. If this fails, we will go ahead and take the
72 * width from the destination register.
74 if (this->exec_size
== 0) {
75 if (dst
.file
== GRF
) {
76 this->exec_size
= dst
.width
;
78 for (unsigned i
= 0; i
< sources
; ++i
) {
79 if (src
[i
].file
!= GRF
&& src
[i
].file
!= ATTR
)
82 if (this->exec_size
<= 1)
83 this->exec_size
= src
[i
].width
;
84 assert(src
[i
].width
== 1 || src
[i
].width
== this->exec_size
);
88 if (this->exec_size
== 0 && dst
.file
!= BAD_FILE
)
89 this->exec_size
= dst
.width
;
91 assert(this->exec_size
!= 0);
93 for (unsigned i
= 0; i
< sources
; ++i
) {
94 switch (this->src
[i
].file
) {
96 this->src
[i
].effective_width
= 8;
101 assert(this->src
[i
].width
> 0);
102 if (this->src
[i
].width
== 1) {
103 this->src
[i
].effective_width
= this->exec_size
;
105 this->src
[i
].effective_width
= this->src
[i
].width
;
110 this->src
[i
].effective_width
= this->exec_size
;
113 unreachable("Invalid source register file");
116 this->dst
.effective_width
= this->exec_size
;
118 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
120 /* This will be the case for almost all instructions. */
127 DIV_ROUND_UP(MAX2(dst
.width
* dst
.stride
, 1) * type_sz(dst
.type
), 32);
130 this->regs_written
= 0;
134 unreachable("Invalid destination register file");
136 unreachable("Invalid register file");
139 this->writes_accumulator
= false;
144 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
147 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
149 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
152 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
)
154 init(opcode
, 0, dst
, NULL
, 0);
157 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
160 const fs_reg src
[1] = { src0
};
161 init(opcode
, exec_size
, dst
, src
, 1);
164 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
)
166 const fs_reg src
[1] = { src0
};
167 init(opcode
, 0, dst
, src
, 1);
170 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
171 const fs_reg
&src0
, const fs_reg
&src1
)
173 const fs_reg src
[2] = { src0
, src1
};
174 init(opcode
, exec_size
, dst
, src
, 2);
177 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
180 const fs_reg src
[2] = { src0
, src1
};
181 init(opcode
, 0, dst
, src
, 2);
184 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
185 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
187 const fs_reg src
[3] = { src0
, src1
, src2
};
188 init(opcode
, exec_size
, dst
, src
, 3);
191 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
192 const fs_reg
&src1
, const fs_reg
&src2
)
194 const fs_reg src
[3] = { src0
, src1
, src2
};
195 init(opcode
, 0, dst
, src
, 3);
198 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
,
199 const fs_reg src
[], unsigned sources
)
201 init(opcode
, 0, dst
, src
, sources
);
204 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
205 const fs_reg src
[], unsigned sources
)
207 init(opcode
, exec_width
, dst
, src
, sources
);
210 fs_inst::fs_inst(const fs_inst
&that
)
212 memcpy(this, &that
, sizeof(that
));
214 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
216 for (unsigned i
= 0; i
< that
.sources
; i
++)
217 this->src
[i
] = that
.src
[i
];
226 fs_inst::resize_sources(uint8_t num_sources
)
228 if (this->sources
!= num_sources
) {
229 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
231 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
232 src
[i
] = this->src
[i
];
236 this->sources
= num_sources
;
242 fs_visitor::op(const fs_reg &dst, const fs_reg &src0) \
244 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0); \
249 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
250 const fs_reg &src1) \
252 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
255 #define ALU2_ACC(op) \
257 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
258 const fs_reg &src1) \
260 fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1);\
261 inst->writes_accumulator = true; \
267 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
268 const fs_reg &src1, const fs_reg &src2) \
270 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2);\
302 /** Gen4 predicated IF. */
304 fs_visitor::IF(enum brw_predicate predicate
)
306 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
, dispatch_width
);
307 inst
->predicate
= predicate
;
311 /** Gen6 IF with embedded comparison. */
313 fs_visitor::IF(const fs_reg
&src0
, const fs_reg
&src1
,
314 enum brw_conditional_mod condition
)
316 assert(brw
->gen
== 6);
317 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
, dispatch_width
,
318 reg_null_d
, src0
, src1
);
319 inst
->conditional_mod
= condition
;
324 * CMP: Sets the low bit of the destination channels with the result
325 * of the comparison, while the upper bits are undefined, and updates
326 * the flag register with the packed 16 bits of the result.
329 fs_visitor::CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
,
330 enum brw_conditional_mod condition
)
334 /* Take the instruction:
336 * CMP null<d> src0<f> src1<f>
338 * Original gen4 does type conversion to the destination type before
339 * comparison, producing garbage results for floating point comparisons.
341 * The destination type doesn't matter on newer generations, so we set the
342 * type to match src0 so we can compact the instruction.
344 dst
.type
= src0
.type
;
345 if (dst
.file
== HW_REG
)
346 dst
.fixed_hw_reg
.type
= dst
.type
;
348 resolve_ud_negate(&src0
);
349 resolve_ud_negate(&src1
);
351 inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_CMP
, dst
, src0
, src1
);
352 inst
->conditional_mod
= condition
;
358 fs_visitor::LOAD_PAYLOAD(const fs_reg
&dst
, fs_reg
*src
, int sources
)
360 uint8_t exec_size
= dst
.width
;
361 for (int i
= 0; i
< sources
; ++i
) {
362 assert(src
[i
].width
% dst
.width
== 0);
363 if (src
[i
].width
> exec_size
)
364 exec_size
= src
[i
].width
;
367 fs_inst
*inst
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
, exec_size
,
369 inst
->regs_written
= 0;
370 for (int i
= 0; i
< sources
; ++i
) {
371 /* The LOAD_PAYLOAD instruction only really makes sense if we are
372 * dealing with whole registers. If this ever changes, we can deal
375 int size
= inst
->src
[i
].effective_width
* type_sz(src
[i
].type
);
376 assert(size
% 32 == 0);
377 inst
->regs_written
+= (size
+ 31) / 32;
384 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_reg
&dst
,
385 const fs_reg
&surf_index
,
386 const fs_reg
&varying_offset
,
387 uint32_t const_offset
)
389 exec_list instructions
;
392 /* We have our constant surface use a pitch of 4 bytes, so our index can
393 * be any component of a vector, and then we load 4 contiguous
394 * components starting from that.
396 * We break down the const_offset to a portion added to the variable
397 * offset and a portion done using reg_offset, which means that if you
398 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
399 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
400 * CSE can later notice that those loads are all the same and eliminate
401 * the redundant ones.
403 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
404 instructions
.push_tail(ADD(vec4_offset
,
405 varying_offset
, fs_reg(const_offset
& ~3)));
408 if (brw
->gen
== 4 && dst
.width
== 8) {
409 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
410 * u, v, r) as parameters, or we can just use the SIMD16 message
411 * consisting of (header, u). We choose the second, at the cost of a
412 * longer return length.
419 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
421 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
423 assert(dst
.width
% 8 == 0);
424 int regs_written
= 4 * (dst
.width
/ 8) * scale
;
425 fs_reg vec4_result
= fs_reg(GRF
, alloc
.allocate(regs_written
),
426 dst
.type
, dst
.width
);
427 inst
= new(mem_ctx
) fs_inst(op
, vec4_result
, surf_index
, vec4_offset
);
428 inst
->regs_written
= regs_written
;
429 instructions
.push_tail(inst
);
433 inst
->header_present
= true;
437 inst
->mlen
= 1 + dispatch_width
/ 8;
440 fs_reg result
= offset(vec4_result
, (const_offset
& 3) * scale
);
441 instructions
.push_tail(MOV(dst
, result
));
447 * A helper for MOV generation for fixing up broken hardware SEND dependency
451 fs_visitor::DEP_RESOLVE_MOV(int grf
)
453 fs_inst
*inst
= MOV(brw_null_reg(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
456 inst
->annotation
= "send dependency resolve";
458 /* The caller always wants uncompressed to emit the minimal extra
459 * dependencies, and to avoid having to deal with aligning its regs to 2.
467 fs_inst::equals(fs_inst
*inst
) const
469 return (opcode
== inst
->opcode
&&
470 dst
.equals(inst
->dst
) &&
471 src
[0].equals(inst
->src
[0]) &&
472 src
[1].equals(inst
->src
[1]) &&
473 src
[2].equals(inst
->src
[2]) &&
474 saturate
== inst
->saturate
&&
475 predicate
== inst
->predicate
&&
476 conditional_mod
== inst
->conditional_mod
&&
477 mlen
== inst
->mlen
&&
478 base_mrf
== inst
->base_mrf
&&
479 target
== inst
->target
&&
481 header_present
== inst
->header_present
&&
482 shadow_compare
== inst
->shadow_compare
&&
483 exec_size
== inst
->exec_size
&&
484 offset
== inst
->offset
);
488 fs_inst::overwrites_reg(const fs_reg
®
) const
490 return reg
.in_range(dst
, regs_written
);
494 fs_inst::is_send_from_grf() const
497 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
498 case SHADER_OPCODE_SHADER_TIME_ADD
:
499 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
500 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
501 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
502 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
503 case SHADER_OPCODE_UNTYPED_ATOMIC
:
504 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
505 case SHADER_OPCODE_URB_WRITE_SIMD8
:
507 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
508 return src
[1].file
== GRF
;
509 case FS_OPCODE_FB_WRITE
:
510 return src
[0].file
== GRF
;
513 return src
[0].file
== GRF
;
520 fs_inst::can_do_source_mods(struct brw_context
*brw
)
522 if (brw
->gen
== 6 && is_math())
525 if (is_send_from_grf())
528 if (!backend_instruction::can_do_source_mods())
535 fs_inst::has_side_effects() const
537 return this->eot
|| backend_instruction::has_side_effects();
543 memset(this, 0, sizeof(*this));
547 /** Generic unset register constructor. */
551 this->file
= BAD_FILE
;
554 /** Immediate value constructor. */
555 fs_reg::fs_reg(float f
)
559 this->type
= BRW_REGISTER_TYPE_F
;
560 this->fixed_hw_reg
.dw1
.f
= f
;
564 /** Immediate value constructor. */
565 fs_reg::fs_reg(int32_t i
)
569 this->type
= BRW_REGISTER_TYPE_D
;
570 this->fixed_hw_reg
.dw1
.d
= i
;
574 /** Immediate value constructor. */
575 fs_reg::fs_reg(uint32_t u
)
579 this->type
= BRW_REGISTER_TYPE_UD
;
580 this->fixed_hw_reg
.dw1
.ud
= u
;
584 /** Vector float immediate value constructor. */
585 fs_reg::fs_reg(uint8_t vf
[4])
589 this->type
= BRW_REGISTER_TYPE_VF
;
590 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
593 /** Vector float immediate value constructor. */
594 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
598 this->type
= BRW_REGISTER_TYPE_VF
;
599 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
605 /** Fixed brw_reg. */
606 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
610 this->fixed_hw_reg
= fixed_hw_reg
;
611 this->type
= fixed_hw_reg
.type
;
612 this->width
= 1 << fixed_hw_reg
.width
;
616 fs_reg::equals(const fs_reg
&r
) const
618 return (file
== r
.file
&&
620 reg_offset
== r
.reg_offset
&&
621 subreg_offset
== r
.subreg_offset
&&
623 negate
== r
.negate
&&
625 !reladdr
&& !r
.reladdr
&&
626 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
, sizeof(fixed_hw_reg
)) == 0 &&
632 fs_reg::set_smear(unsigned subreg
)
634 assert(file
!= HW_REG
&& file
!= IMM
);
635 subreg_offset
= subreg
* type_sz(type
);
641 fs_reg::is_contiguous() const
647 fs_visitor::type_size(const struct glsl_type
*type
)
649 unsigned int size
, i
;
651 switch (type
->base_type
) {
654 case GLSL_TYPE_FLOAT
:
656 return type
->components();
657 case GLSL_TYPE_ARRAY
:
658 return type_size(type
->fields
.array
) * type
->length
;
659 case GLSL_TYPE_STRUCT
:
661 for (i
= 0; i
< type
->length
; i
++) {
662 size
+= type_size(type
->fields
.structure
[i
].type
);
665 case GLSL_TYPE_SAMPLER
:
666 /* Samplers take up no register space, since they're baked in at
670 case GLSL_TYPE_ATOMIC_UINT
:
672 case GLSL_TYPE_IMAGE
:
674 case GLSL_TYPE_ERROR
:
675 case GLSL_TYPE_INTERFACE
:
676 case GLSL_TYPE_DOUBLE
:
677 unreachable("not reached");
684 * Create a MOV to read the timestamp register.
686 * The caller is responsible for emitting the MOV. The return value is
687 * the destination of the MOV, with extra parameters set.
690 fs_visitor::get_timestamp(fs_inst
**out_mov
)
692 assert(brw
->gen
>= 7);
694 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
697 BRW_REGISTER_TYPE_UD
));
699 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
, 4);
701 fs_inst
*mov
= MOV(dst
, ts
);
702 /* We want to read the 3 fields we care about even if it's not enabled in
705 mov
->force_writemask_all
= true;
707 /* The caller wants the low 32 bits of the timestamp. Since it's running
708 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
709 * which is plenty of time for our purposes. It is identical across the
710 * EUs, but since it's tracking GPU core speed it will increment at a
711 * varying rate as render P-states change.
713 * The caller could also check if render P-states have changed (or anything
714 * else that might disrupt timing) by setting smear to 2 and checking if
715 * that field is != 0.
724 fs_visitor::emit_shader_time_begin()
726 current_annotation
= "shader time start";
728 shader_start_time
= get_timestamp(&mov
);
733 fs_visitor::emit_shader_time_end()
735 current_annotation
= "shader time end";
737 enum shader_time_shader_type type
, written_type
, reset_type
;
739 case MESA_SHADER_VERTEX
:
741 written_type
= ST_VS_WRITTEN
;
742 reset_type
= ST_VS_RESET
;
744 case MESA_SHADER_GEOMETRY
:
746 written_type
= ST_GS_WRITTEN
;
747 reset_type
= ST_GS_RESET
;
749 case MESA_SHADER_FRAGMENT
:
750 if (dispatch_width
== 8) {
752 written_type
= ST_FS8_WRITTEN
;
753 reset_type
= ST_FS8_RESET
;
755 assert(dispatch_width
== 16);
757 written_type
= ST_FS16_WRITTEN
;
758 reset_type
= ST_FS16_RESET
;
762 unreachable("fs_visitor::emit_shader_time_end missing code");
765 /* Insert our code just before the final SEND with EOT. */
766 exec_node
*end
= this->instructions
.get_tail();
767 assert(end
&& ((fs_inst
*) end
)->eot
);
770 fs_reg shader_end_time
= get_timestamp(&tm_read
);
771 end
->insert_before(tm_read
);
773 /* Check that there weren't any timestamp reset events (assuming these
774 * were the only two timestamp reads that happened).
776 fs_reg reset
= shader_end_time
;
778 fs_inst
*test
= AND(reg_null_d
, reset
, fs_reg(1u));
779 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
780 test
->force_writemask_all
= true;
781 end
->insert_before(test
);
782 end
->insert_before(IF(BRW_PREDICATE_NORMAL
));
784 fs_reg start
= shader_start_time
;
786 fs_reg diff
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
, 1);
788 fs_inst
*add
= ADD(diff
, start
, shader_end_time
);
789 add
->force_writemask_all
= true;
790 end
->insert_before(add
);
792 /* If there were no instructions between the two timestamp gets, the diff
793 * is 2 cycles. Remove that overhead, so I can forget about that when
794 * trying to determine the time taken for single instructions.
796 add
= ADD(diff
, diff
, fs_reg(-2u));
797 add
->force_writemask_all
= true;
798 end
->insert_before(add
);
800 end
->insert_before(SHADER_TIME_ADD(type
, diff
));
801 end
->insert_before(SHADER_TIME_ADD(written_type
, fs_reg(1u)));
802 end
->insert_before(new(mem_ctx
) fs_inst(BRW_OPCODE_ELSE
, dispatch_width
));
803 end
->insert_before(SHADER_TIME_ADD(reset_type
, fs_reg(1u)));
804 end
->insert_before(new(mem_ctx
) fs_inst(BRW_OPCODE_ENDIF
, dispatch_width
));
808 fs_visitor::SHADER_TIME_ADD(enum shader_time_shader_type type
, fs_reg value
)
810 int shader_time_index
=
811 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
812 fs_reg offset
= fs_reg(shader_time_index
* SHADER_TIME_STRIDE
);
815 if (dispatch_width
== 8)
816 payload
= vgrf(glsl_type::uvec2_type
);
818 payload
= vgrf(glsl_type::uint_type
);
820 return new(mem_ctx
) fs_inst(SHADER_OPCODE_SHADER_TIME_ADD
,
821 fs_reg(), payload
, offset
, value
);
825 fs_visitor::vfail(const char *format
, va_list va
)
834 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
835 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
837 this->fail_msg
= msg
;
840 fprintf(stderr
, "%s", msg
);
845 fs_visitor::fail(const char *format
, ...)
849 va_start(va
, format
);
855 * Mark this program as impossible to compile in SIMD16 mode.
857 * During the SIMD8 compile (which happens first), we can detect and flag
858 * things that are unsupported in SIMD16 mode, so the compiler can skip
859 * the SIMD16 compile altogether.
861 * During a SIMD16 compile (if one happens anyway), this just calls fail().
864 fs_visitor::no16(const char *format
, ...)
868 va_start(va
, format
);
870 if (dispatch_width
== 16) {
873 simd16_unsupported
= true;
875 if (brw
->perf_debug
) {
877 ralloc_vasprintf_append(&no16_msg
, format
, va
);
879 no16_msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
887 fs_visitor::emit(enum opcode opcode
)
889 return emit(new(mem_ctx
) fs_inst(opcode
, dispatch_width
));
893 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
)
895 return emit(new(mem_ctx
) fs_inst(opcode
, dst
));
899 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
)
901 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
));
905 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
908 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
, src1
));
912 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
913 const fs_reg
&src1
, const fs_reg
&src2
)
915 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
, src1
, src2
));
919 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
,
920 fs_reg src
[], int sources
)
922 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src
, sources
));
926 * Returns true if the instruction has a flag that means it won't
927 * update an entire destination register.
929 * For example, dead code elimination and live variable analysis want to know
930 * when a write to a variable screens off any preceding values that were in
934 fs_inst::is_partial_write() const
936 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
937 (this->dst
.width
* type_sz(this->dst
.type
)) < 32 ||
938 !this->dst
.is_contiguous());
942 fs_inst::regs_read(int arg
) const
944 if (is_tex() && arg
== 0 && src
[0].file
== GRF
) {
946 } else if (opcode
== FS_OPCODE_FB_WRITE
&& arg
== 0) {
948 } else if (opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
&& arg
== 0) {
950 } else if (opcode
== SHADER_OPCODE_UNTYPED_ATOMIC
&& arg
== 0) {
952 } else if (opcode
== SHADER_OPCODE_UNTYPED_SURFACE_READ
&& arg
== 0) {
954 } else if (opcode
== FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
&& arg
== 0) {
956 } else if (opcode
== FS_OPCODE_LINTERP
&& arg
== 0) {
957 return exec_size
/ 4;
960 switch (src
[arg
].file
) {
967 if (src
[arg
].stride
== 0) {
970 int size
= src
[arg
].width
* src
[arg
].stride
* type_sz(src
[arg
].type
);
971 return (size
+ 31) / 32;
974 unreachable("MRF registers are not allowed as sources");
976 unreachable("Invalid register file");
981 fs_inst::reads_flag() const
987 fs_inst::writes_flag() const
989 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
990 opcode
!= BRW_OPCODE_IF
&&
991 opcode
!= BRW_OPCODE_WHILE
)) ||
992 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
996 * Returns how many MRFs an FS opcode will write over.
998 * Note that this is not the 0 or 1 implied writes in an actual gen
999 * instruction -- the FS opcodes often generate MOVs in addition.
1002 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
1004 if (inst
->mlen
== 0)
1007 if (inst
->base_mrf
== -1)
1010 switch (inst
->opcode
) {
1011 case SHADER_OPCODE_RCP
:
1012 case SHADER_OPCODE_RSQ
:
1013 case SHADER_OPCODE_SQRT
:
1014 case SHADER_OPCODE_EXP2
:
1015 case SHADER_OPCODE_LOG2
:
1016 case SHADER_OPCODE_SIN
:
1017 case SHADER_OPCODE_COS
:
1018 return 1 * dispatch_width
/ 8;
1019 case SHADER_OPCODE_POW
:
1020 case SHADER_OPCODE_INT_QUOTIENT
:
1021 case SHADER_OPCODE_INT_REMAINDER
:
1022 return 2 * dispatch_width
/ 8;
1023 case SHADER_OPCODE_TEX
:
1025 case SHADER_OPCODE_TXD
:
1026 case SHADER_OPCODE_TXF
:
1027 case SHADER_OPCODE_TXF_CMS
:
1028 case SHADER_OPCODE_TXF_MCS
:
1029 case SHADER_OPCODE_TG4
:
1030 case SHADER_OPCODE_TG4_OFFSET
:
1031 case SHADER_OPCODE_TXL
:
1032 case SHADER_OPCODE_TXS
:
1033 case SHADER_OPCODE_LOD
:
1035 case FS_OPCODE_FB_WRITE
:
1037 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1038 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1040 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
1042 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1044 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1045 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1046 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1047 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
1048 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
1049 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
1050 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
1053 unreachable("not reached");
1058 fs_visitor::vgrf(const glsl_type
*const type
)
1060 int reg_width
= dispatch_width
/ 8;
1061 return fs_reg(GRF
, alloc
.allocate(type_size(type
) * reg_width
),
1062 brw_type_for_base_type(type
), dispatch_width
);
1066 fs_visitor::vgrf(int num_components
)
1068 int reg_width
= dispatch_width
/ 8;
1069 return fs_reg(GRF
, alloc
.allocate(num_components
* reg_width
),
1070 BRW_REGISTER_TYPE_F
, dispatch_width
);
1073 /** Fixed HW reg constructor. */
1074 fs_reg::fs_reg(enum register_file file
, int reg
)
1079 this->type
= BRW_REGISTER_TYPE_F
;
1090 /** Fixed HW reg constructor. */
1091 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
)
1107 /** Fixed HW reg constructor. */
1108 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
,
1115 this->width
= width
;
1119 fs_visitor::variable_storage(ir_variable
*var
)
1121 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
1125 import_uniforms_callback(const void *key
,
1129 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
1130 const fs_reg
*reg
= (const fs_reg
*)data
;
1132 if (reg
->file
!= UNIFORM
)
1135 hash_table_insert(dst_ht
, data
, key
);
1138 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1139 * This brings in those uniform definitions
1142 fs_visitor::import_uniforms(fs_visitor
*v
)
1144 hash_table_call_foreach(v
->variable_ht
,
1145 import_uniforms_callback
,
1147 this->push_constant_loc
= v
->push_constant_loc
;
1148 this->pull_constant_loc
= v
->pull_constant_loc
;
1149 this->uniforms
= v
->uniforms
;
1150 this->param_size
= v
->param_size
;
1153 /* Our support for uniforms is piggy-backed on the struct
1154 * gl_fragment_program, because that's where the values actually
1155 * get stored, rather than in some global gl_shader_program uniform
1159 fs_visitor::setup_uniform_values(ir_variable
*ir
)
1161 int namelen
= strlen(ir
->name
);
1163 /* The data for our (non-builtin) uniforms is stored in a series of
1164 * gl_uniform_driver_storage structs for each subcomponent that
1165 * glGetUniformLocation() could name. We know it's been set up in the same
1166 * order we'd walk the type, so walk the list of storage and find anything
1167 * with our name, or the prefix of a component that starts with our name.
1169 unsigned params_before
= uniforms
;
1170 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
1171 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
1173 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
1174 (storage
->name
[namelen
] != 0 &&
1175 storage
->name
[namelen
] != '.' &&
1176 storage
->name
[namelen
] != '[')) {
1180 unsigned slots
= storage
->type
->component_slots();
1181 if (storage
->array_elements
)
1182 slots
*= storage
->array_elements
;
1184 for (unsigned i
= 0; i
< slots
; i
++) {
1185 stage_prog_data
->param
[uniforms
++] = &storage
->storage
[i
];
1189 /* Make sure we actually initialized the right amount of stuff here. */
1190 assert(params_before
+ ir
->type
->component_slots() == uniforms
);
1191 (void)params_before
;
1195 /* Our support for builtin uniforms is even scarier than non-builtin.
1196 * It sits on top of the PROG_STATE_VAR parameters that are
1197 * automatically updated from GL context state.
1200 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
1202 const ir_state_slot
*const slots
= ir
->get_state_slots();
1203 assert(slots
!= NULL
);
1205 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1206 /* This state reference has already been setup by ir_to_mesa, but we'll
1207 * get the same index back here.
1209 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1210 (gl_state_index
*)slots
[i
].tokens
);
1212 /* Add each of the unique swizzles of the element as a parameter.
1213 * This'll end up matching the expected layout of the
1214 * array/matrix/structure we're trying to fill in.
1217 for (unsigned int j
= 0; j
< 4; j
++) {
1218 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
1219 if (swiz
== last_swiz
)
1223 stage_prog_data
->param
[uniforms
++] =
1224 &prog
->Parameters
->ParameterValues
[index
][swiz
];
1230 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
1231 bool origin_upper_left
)
1233 assert(stage
== MESA_SHADER_FRAGMENT
);
1234 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1235 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1237 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
1239 /* gl_FragCoord.x */
1240 if (pixel_center_integer
) {
1241 emit(MOV(wpos
, this->pixel_x
));
1243 emit(ADD(wpos
, this->pixel_x
, fs_reg(0.5f
)));
1245 wpos
= offset(wpos
, 1);
1247 /* gl_FragCoord.y */
1248 if (!flip
&& pixel_center_integer
) {
1249 emit(MOV(wpos
, this->pixel_y
));
1251 fs_reg pixel_y
= this->pixel_y
;
1252 float offset
= (pixel_center_integer
? 0.0 : 0.5);
1255 pixel_y
.negate
= true;
1256 offset
+= key
->drawable_height
- 1.0;
1259 emit(ADD(wpos
, pixel_y
, fs_reg(offset
)));
1261 wpos
= offset(wpos
, 1);
1263 /* gl_FragCoord.z */
1264 if (brw
->gen
>= 6) {
1265 emit(MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0))));
1267 emit(FS_OPCODE_LINTERP
, wpos
,
1268 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1269 interp_reg(VARYING_SLOT_POS
, 2));
1271 wpos
= offset(wpos
, 1);
1273 /* gl_FragCoord.w: Already set up in emit_interpolation */
1274 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
1280 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1281 glsl_interp_qualifier interpolation_mode
,
1282 bool is_centroid
, bool is_sample
)
1284 brw_wm_barycentric_interp_mode barycoord_mode
;
1285 if (brw
->gen
>= 6) {
1287 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1288 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1290 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1291 } else if (is_sample
) {
1292 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1293 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1295 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1297 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1298 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1300 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1303 /* On Ironlake and below, there is only one interpolation mode.
1304 * Centroid interpolation doesn't mean anything on this hardware --
1305 * there is no multisampling.
1307 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1309 return emit(FS_OPCODE_LINTERP
, attr
,
1310 this->delta_xy
[barycoord_mode
], interp
);
1314 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1315 const glsl_type
*type
,
1316 glsl_interp_qualifier interpolation_mode
,
1317 int location
, bool mod_centroid
,
1320 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1322 assert(stage
== MESA_SHADER_FRAGMENT
);
1323 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1324 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1326 unsigned int array_elements
;
1328 if (type
->is_array()) {
1329 array_elements
= type
->length
;
1330 if (array_elements
== 0) {
1331 fail("dereferenced array '%s' has length 0\n", name
);
1333 type
= type
->fields
.array
;
1338 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1340 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1341 if (key
->flat_shade
&& is_gl_Color
) {
1342 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1344 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1348 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1349 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1350 if (prog_data
->urb_setup
[location
] == -1) {
1351 /* If there's no incoming setup data for this slot, don't
1352 * emit interpolation for it.
1354 attr
= offset(attr
, type
->vector_elements
);
1359 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1360 /* Constant interpolation (flat shading) case. The SF has
1361 * handed us defined values in only the constant offset
1362 * field of the setup reg.
1364 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1365 struct brw_reg interp
= interp_reg(location
, k
);
1366 interp
= suboffset(interp
, 3);
1367 interp
.type
= attr
.type
;
1368 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1369 attr
= offset(attr
, 1);
1372 /* Smooth/noperspective interpolation case. */
1373 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1374 struct brw_reg interp
= interp_reg(location
, k
);
1375 if (brw
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1376 /* Get the pixel/sample mask into f0 so that we know
1377 * which pixels are lit. Then, for each channel that is
1378 * unlit, replace the centroid data with non-centroid
1381 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1384 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1386 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1387 inst
->predicate_inverse
= true;
1389 inst
->no_dd_clear
= true;
1391 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1392 mod_centroid
&& !key
->persample_shading
,
1393 mod_sample
|| key
->persample_shading
);
1394 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1395 inst
->predicate_inverse
= false;
1397 inst
->no_dd_check
= true;
1400 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1401 mod_centroid
&& !key
->persample_shading
,
1402 mod_sample
|| key
->persample_shading
);
1404 if (brw
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1405 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
1407 attr
= offset(attr
, 1);
1417 fs_visitor::emit_frontfacing_interpolation()
1419 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1421 if (brw
->gen
>= 6) {
1422 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1423 * a boolean result from this (~0/true or 0/false).
1425 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1426 * this task in only one instruction:
1427 * - a negation source modifier will flip the bit; and
1428 * - a W -> D type conversion will sign extend the bit into the high
1429 * word of the destination.
1431 * An ASR 15 fills the low word of the destination.
1433 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1436 emit(ASR(*reg
, g0
, fs_reg(15)));
1438 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1439 * a boolean result from this (1/true or 0/false).
1441 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1442 * the negation source modifier to flip it. Unfortunately the SHR
1443 * instruction only operates on UD (or D with an abs source modifier)
1444 * sources without negation.
1446 * Instead, use ASR (which will give ~0/true or 0/false).
1448 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1451 emit(ASR(*reg
, g1_6
, fs_reg(31)));
1458 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1460 assert(stage
== MESA_SHADER_FRAGMENT
);
1461 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1462 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1464 if (key
->compute_pos_offset
) {
1465 /* Convert int_sample_pos to floating point */
1466 emit(MOV(dst
, int_sample_pos
));
1467 /* Scale to the range [0, 1] */
1468 emit(MUL(dst
, dst
, fs_reg(1 / 16.0f
)));
1471 /* From ARB_sample_shading specification:
1472 * "When rendering to a non-multisample buffer, or if multisample
1473 * rasterization is disabled, gl_SamplePosition will always be
1476 emit(MOV(dst
, fs_reg(0.5f
)));
1481 fs_visitor::emit_samplepos_setup()
1483 assert(brw
->gen
>= 6);
1485 this->current_annotation
= "compute sample position";
1486 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1488 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1489 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1491 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1492 * mode will be enabled.
1494 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1495 * R31.1:0 Position Offset X/Y for Slot[3:0]
1496 * R31.3:2 Position Offset X/Y for Slot[7:4]
1499 * The X, Y sample positions come in as bytes in thread payload. So, read
1500 * the positions using vstride=16, width=8, hstride=2.
1502 struct brw_reg sample_pos_reg
=
1503 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1504 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1506 if (dispatch_width
== 8) {
1507 emit(MOV(int_sample_x
, fs_reg(sample_pos_reg
)));
1509 emit(MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
)));
1510 emit(MOV(half(int_sample_x
, 1), fs_reg(suboffset(sample_pos_reg
, 16))))
1511 ->force_sechalf
= true;
1513 /* Compute gl_SamplePosition.x */
1514 compute_sample_position(pos
, int_sample_x
);
1515 pos
= offset(pos
, 1);
1516 if (dispatch_width
== 8) {
1517 emit(MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1))));
1519 emit(MOV(half(int_sample_y
, 0),
1520 fs_reg(suboffset(sample_pos_reg
, 1))));
1521 emit(MOV(half(int_sample_y
, 1), fs_reg(suboffset(sample_pos_reg
, 17))))
1522 ->force_sechalf
= true;
1524 /* Compute gl_SamplePosition.y */
1525 compute_sample_position(pos
, int_sample_y
);
1530 fs_visitor::emit_sampleid_setup()
1532 assert(stage
== MESA_SHADER_FRAGMENT
);
1533 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1534 assert(brw
->gen
>= 6);
1536 this->current_annotation
= "compute sample id";
1537 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1539 if (key
->compute_sample_id
) {
1540 fs_reg t1
= vgrf(glsl_type::int_type
);
1541 fs_reg t2
= vgrf(glsl_type::int_type
);
1542 t2
.type
= BRW_REGISTER_TYPE_UW
;
1544 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1545 * 8x multisampling, subspan 0 will represent sample N (where N
1546 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1547 * 7. We can find the value of N by looking at R0.0 bits 7:6
1548 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1549 * (since samples are always delivered in pairs). That is, we
1550 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1551 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1552 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1553 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1554 * populating a temporary variable with the sequence (0, 1, 2, 3),
1555 * and then reading from it using vstride=1, width=4, hstride=0.
1556 * These computations hold good for 4x multisampling as well.
1558 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1559 * the first four slots are sample 0 of subspan 0; the next four
1560 * are sample 1 of subspan 0; the third group is sample 0 of
1561 * subspan 1, and finally sample 1 of subspan 1.
1564 inst
= emit(BRW_OPCODE_AND
, t1
,
1565 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1567 inst
->force_writemask_all
= true;
1568 inst
= emit(BRW_OPCODE_SHR
, t1
, t1
, fs_reg(5));
1569 inst
->force_writemask_all
= true;
1570 /* This works for both SIMD8 and SIMD16 */
1571 inst
= emit(MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210)));
1572 inst
->force_writemask_all
= true;
1573 /* This special instruction takes care of setting vstride=1,
1574 * width=4, hstride=0 of t2 during an ADD instruction.
1576 emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1578 /* As per GL_ARB_sample_shading specification:
1579 * "When rendering to a non-multisample buffer, or if multisample
1580 * rasterization is disabled, gl_SampleID will always be zero."
1582 emit(BRW_OPCODE_MOV
, *reg
, fs_reg(0));
1589 fs_visitor::resolve_source_modifiers(fs_reg
*src
)
1591 if (!src
->abs
&& !src
->negate
)
1594 fs_reg temp
= retype(vgrf(1), src
->type
);
1595 emit(MOV(temp
, *src
));
1600 fs_visitor::fix_math_operand(fs_reg src
)
1602 /* Can't do hstride == 0 args on gen6 math, so expand it out. We
1603 * might be able to do better by doing execsize = 1 math and then
1604 * expanding that result out, but we would need to be careful with
1607 * The hardware ignores source modifiers (negate and abs) on math
1608 * instructions, so we also move to a temp to set those up.
1610 if (brw
->gen
== 6 && src
.file
!= UNIFORM
&& src
.file
!= IMM
&&
1611 !src
.abs
&& !src
.negate
)
1614 /* Gen7 relaxes most of the above restrictions, but still can't use IMM
1617 if (brw
->gen
>= 7 && src
.file
!= IMM
)
1620 fs_reg expanded
= vgrf(glsl_type::float_type
);
1621 expanded
.type
= src
.type
;
1622 emit(BRW_OPCODE_MOV
, expanded
, src
);
1627 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src
)
1630 case SHADER_OPCODE_RCP
:
1631 case SHADER_OPCODE_RSQ
:
1632 case SHADER_OPCODE_SQRT
:
1633 case SHADER_OPCODE_EXP2
:
1634 case SHADER_OPCODE_LOG2
:
1635 case SHADER_OPCODE_SIN
:
1636 case SHADER_OPCODE_COS
:
1639 unreachable("not reached: bad math opcode");
1642 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
1643 * might be able to do better by doing execsize = 1 math and then
1644 * expanding that result out, but we would need to be careful with
1647 * Gen 6 hardware ignores source modifiers (negate and abs) on math
1648 * instructions, so we also move to a temp to set those up.
1650 if (brw
->gen
== 6 || brw
->gen
== 7)
1651 src
= fix_math_operand(src
);
1653 fs_inst
*inst
= emit(opcode
, dst
, src
);
1657 inst
->mlen
= dispatch_width
/ 8;
1664 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
1669 if (brw
->gen
>= 8) {
1670 inst
= emit(opcode
, dst
, src0
, src1
);
1671 } else if (brw
->gen
>= 6) {
1672 src0
= fix_math_operand(src0
);
1673 src1
= fix_math_operand(src1
);
1675 inst
= emit(opcode
, dst
, src0
, src1
);
1677 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
1678 * "Message Payload":
1680 * "Operand0[7]. For the INT DIV functions, this operand is the
1683 * "Operand1[7]. For the INT DIV functions, this operand is the
1686 bool is_int_div
= opcode
!= SHADER_OPCODE_POW
;
1687 fs_reg
&op0
= is_int_div
? src1
: src0
;
1688 fs_reg
&op1
= is_int_div
? src0
: src1
;
1690 emit(MOV(fs_reg(MRF
, base_mrf
+ 1, op1
.type
, dispatch_width
), op1
));
1691 inst
= emit(opcode
, dst
, op0
, reg_null_f
);
1693 inst
->base_mrf
= base_mrf
;
1694 inst
->mlen
= 2 * dispatch_width
/ 8;
1700 fs_visitor::emit_discard_jump()
1702 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1704 /* For performance, after a discard, jump to the end of the
1705 * shader if all relevant channels have been discarded.
1707 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1708 discard_jump
->flag_subreg
= 1;
1710 discard_jump
->predicate
= (dispatch_width
== 8)
1711 ? BRW_PREDICATE_ALIGN1_ANY8H
1712 : BRW_PREDICATE_ALIGN1_ANY16H
;
1713 discard_jump
->predicate_inverse
= true;
1717 fs_visitor::assign_curb_setup()
1719 if (dispatch_width
== 8) {
1720 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1722 assert(stage
== MESA_SHADER_FRAGMENT
);
1723 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1724 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1727 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1729 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1730 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1731 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1732 if (inst
->src
[i
].file
== UNIFORM
) {
1733 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1735 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1736 constant_nr
= push_constant_loc
[uniform_nr
];
1738 /* Section 5.11 of the OpenGL 4.1 spec says:
1739 * "Out-of-bounds reads return undefined values, which include
1740 * values from other variables of the active program or zero."
1741 * Just return the first push constant.
1746 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1750 inst
->src
[i
].file
= HW_REG
;
1751 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1752 retype(brw_reg
, inst
->src
[i
].type
),
1753 inst
->src
[i
].subreg_offset
);
1760 fs_visitor::calculate_urb_setup()
1762 assert(stage
== MESA_SHADER_FRAGMENT
);
1763 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1764 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1766 memset(prog_data
->urb_setup
, -1,
1767 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1770 /* Figure out where each of the incoming setup attributes lands. */
1771 if (brw
->gen
>= 6) {
1772 if (_mesa_bitcount_64(prog
->InputsRead
&
1773 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1774 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1775 * first 16 varying inputs, so we can put them wherever we want.
1776 * Just put them in order.
1778 * This is useful because it means that (a) inputs not used by the
1779 * fragment shader won't take up valuable register space, and (b) we
1780 * won't have to recompile the fragment shader if it gets paired with
1781 * a different vertex (or geometry) shader.
1783 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1784 if (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1785 BITFIELD64_BIT(i
)) {
1786 prog_data
->urb_setup
[i
] = urb_next
++;
1790 /* We have enough input varyings that the SF/SBE pipeline stage can't
1791 * arbitrarily rearrange them to suit our whim; we have to put them
1792 * in an order that matches the output of the previous pipeline stage
1793 * (geometry or vertex shader).
1795 struct brw_vue_map prev_stage_vue_map
;
1796 brw_compute_vue_map(brw
, &prev_stage_vue_map
,
1797 key
->input_slots_valid
);
1798 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1799 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1800 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1802 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1803 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1806 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1807 (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1808 BITFIELD64_BIT(varying
))) {
1809 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1812 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1815 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1816 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1817 /* Point size is packed into the header, not as a general attribute */
1818 if (i
== VARYING_SLOT_PSIZ
)
1821 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1822 /* The back color slot is skipped when the front color is
1823 * also written to. In addition, some slots can be
1824 * written in the vertex shader and not read in the
1825 * fragment shader. So the register number must always be
1826 * incremented, mapped or not.
1828 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1829 prog_data
->urb_setup
[i
] = urb_next
;
1835 * It's a FS only attribute, and we did interpolation for this attribute
1836 * in SF thread. So, count it here, too.
1838 * See compile_sf_prog() for more info.
1840 if (prog
->InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1841 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1844 prog_data
->num_varying_inputs
= urb_next
;
1848 fs_visitor::assign_urb_setup()
1850 assert(stage
== MESA_SHADER_FRAGMENT
);
1851 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1853 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1855 /* Offset all the urb_setup[] index by the actual position of the
1856 * setup regs, now that the location of the constants has been chosen.
1858 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1859 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1860 assert(inst
->src
[1].file
== HW_REG
);
1861 inst
->src
[1].fixed_hw_reg
.nr
+= urb_start
;
1864 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1865 assert(inst
->src
[0].file
== HW_REG
);
1866 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1870 /* Each attribute is 4 setup channels, each of which is half a reg. */
1871 this->first_non_payload_grf
=
1872 urb_start
+ prog_data
->num_varying_inputs
* 2;
1876 fs_visitor::assign_vs_urb_setup()
1878 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1879 int grf
, count
, slot
, channel
, attr
;
1881 assert(stage
== MESA_SHADER_VERTEX
);
1882 count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1883 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1886 /* Each attribute is 4 regs. */
1887 this->first_non_payload_grf
=
1888 payload
.num_regs
+ prog_data
->curb_read_length
+ count
* 4;
1890 unsigned vue_entries
=
1891 MAX2(count
, vs_prog_data
->base
.vue_map
.num_slots
);
1893 vs_prog_data
->base
.urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1894 vs_prog_data
->base
.urb_read_length
= (count
+ 1) / 2;
1896 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1898 /* Rewrite all ATTR file references to the hw grf that they land in. */
1899 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1900 for (int i
= 0; i
< inst
->sources
; i
++) {
1901 if (inst
->src
[i
].file
== ATTR
) {
1903 if (inst
->src
[i
].reg
== VERT_ATTRIB_MAX
) {
1906 /* Attributes come in in a contiguous block, ordered by their
1907 * gl_vert_attrib value. That means we can compute the slot
1908 * number for an attribute by masking out the enabled
1909 * attributes before it and counting the bits.
1911 attr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
/ 4;
1912 slot
= _mesa_bitcount_64(vs_prog_data
->inputs_read
&
1913 BITFIELD64_MASK(attr
));
1916 channel
= inst
->src
[i
].reg_offset
& 3;
1918 grf
= payload
.num_regs
+
1919 prog_data
->curb_read_length
+
1922 inst
->src
[i
].file
= HW_REG
;
1923 inst
->src
[i
].fixed_hw_reg
=
1924 retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
);
1931 * Split large virtual GRFs into separate components if we can.
1933 * This is mostly duplicated with what brw_fs_vector_splitting does,
1934 * but that's really conservative because it's afraid of doing
1935 * splitting that doesn't result in real progress after the rest of
1936 * the optimization phases, which would cause infinite looping in
1937 * optimization. We can do it once here, safely. This also has the
1938 * opportunity to split interpolated values, or maybe even uniforms,
1939 * which we don't have at the IR level.
1941 * We want to split, because virtual GRFs are what we register
1942 * allocate and spill (due to contiguousness requirements for some
1943 * instructions), and they're what we naturally generate in the
1944 * codegen process, but most virtual GRFs don't actually need to be
1945 * contiguous sets of GRFs. If we split, we'll end up with reduced
1946 * live intervals and better dead code elimination and coalescing.
1949 fs_visitor::split_virtual_grfs()
1951 int num_vars
= this->alloc
.count
;
1953 /* Count the total number of registers */
1955 int vgrf_to_reg
[num_vars
];
1956 for (int i
= 0; i
< num_vars
; i
++) {
1957 vgrf_to_reg
[i
] = reg_count
;
1958 reg_count
+= alloc
.sizes
[i
];
1961 /* An array of "split points". For each register slot, this indicates
1962 * if this slot can be separated from the previous slot. Every time an
1963 * instruction uses multiple elements of a register (as a source or
1964 * destination), we mark the used slots as inseparable. Then we go
1965 * through and split the registers into the smallest pieces we can.
1967 bool split_points
[reg_count
];
1968 memset(split_points
, 0, sizeof(split_points
));
1970 /* Mark all used registers as fully splittable */
1971 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1972 if (inst
->dst
.file
== GRF
) {
1973 int reg
= vgrf_to_reg
[inst
->dst
.reg
];
1974 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.reg
]; j
++)
1975 split_points
[reg
+ j
] = true;
1978 for (int i
= 0; i
< inst
->sources
; i
++) {
1979 if (inst
->src
[i
].file
== GRF
) {
1980 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
];
1981 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].reg
]; j
++)
1982 split_points
[reg
+ j
] = true;
1987 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1988 if (inst
->dst
.file
== GRF
) {
1989 int reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1990 for (int j
= 1; j
< inst
->regs_written
; j
++)
1991 split_points
[reg
+ j
] = false;
1993 for (int i
= 0; i
< inst
->sources
; i
++) {
1994 if (inst
->src
[i
].file
== GRF
) {
1995 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1996 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1997 split_points
[reg
+ j
] = false;
2002 int new_virtual_grf
[reg_count
];
2003 int new_reg_offset
[reg_count
];
2006 for (int i
= 0; i
< num_vars
; i
++) {
2007 /* The first one should always be 0 as a quick sanity check. */
2008 assert(split_points
[reg
] == false);
2011 new_reg_offset
[reg
] = 0;
2016 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
2017 /* If this is a split point, reset the offset to 0 and allocate a
2018 * new virtual GRF for the previous offset many registers
2020 if (split_points
[reg
]) {
2021 assert(offset
<= MAX_VGRF_SIZE
);
2022 int grf
= alloc
.allocate(offset
);
2023 for (int k
= reg
- offset
; k
< reg
; k
++)
2024 new_virtual_grf
[k
] = grf
;
2027 new_reg_offset
[reg
] = offset
;
2032 /* The last one gets the original register number */
2033 assert(offset
<= MAX_VGRF_SIZE
);
2034 alloc
.sizes
[i
] = offset
;
2035 for (int k
= reg
- offset
; k
< reg
; k
++)
2036 new_virtual_grf
[k
] = i
;
2038 assert(reg
== reg_count
);
2040 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2041 if (inst
->dst
.file
== GRF
) {
2042 reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
2043 inst
->dst
.reg
= new_virtual_grf
[reg
];
2044 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
2045 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2047 for (int i
= 0; i
< inst
->sources
; i
++) {
2048 if (inst
->src
[i
].file
== GRF
) {
2049 reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
2050 inst
->src
[i
].reg
= new_virtual_grf
[reg
];
2051 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
2052 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2056 invalidate_live_intervals();
2060 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
2062 * During code generation, we create tons of temporary variables, many of
2063 * which get immediately killed and are never used again. Yet, in later
2064 * optimization and analysis passes, such as compute_live_intervals, we need
2065 * to loop over all the virtual GRFs. Compacting them can save a lot of
2069 fs_visitor::compact_virtual_grfs()
2071 bool progress
= false;
2072 int remap_table
[this->alloc
.count
];
2073 memset(remap_table
, -1, sizeof(remap_table
));
2075 /* Mark which virtual GRFs are used. */
2076 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
2077 if (inst
->dst
.file
== GRF
)
2078 remap_table
[inst
->dst
.reg
] = 0;
2080 for (int i
= 0; i
< inst
->sources
; i
++) {
2081 if (inst
->src
[i
].file
== GRF
)
2082 remap_table
[inst
->src
[i
].reg
] = 0;
2086 /* Compact the GRF arrays. */
2088 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
2089 if (remap_table
[i
] == -1) {
2090 /* We just found an unused register. This means that we are
2091 * actually going to compact something.
2095 remap_table
[i
] = new_index
;
2096 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
2097 invalidate_live_intervals();
2102 this->alloc
.count
= new_index
;
2104 /* Patch all the instructions to use the newly renumbered registers */
2105 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2106 if (inst
->dst
.file
== GRF
)
2107 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
2109 for (int i
= 0; i
< inst
->sources
; i
++) {
2110 if (inst
->src
[i
].file
== GRF
)
2111 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
2115 /* Patch all the references to delta_xy, since they're used in register
2116 * allocation. If they're unused, switch them to BAD_FILE so we don't
2117 * think some random VGRF is delta_xy.
2119 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2120 if (delta_xy
[i
].file
== GRF
) {
2121 if (remap_table
[delta_xy
[i
].reg
] != -1) {
2122 delta_xy
[i
].reg
= remap_table
[delta_xy
[i
].reg
];
2124 delta_xy
[i
].file
= BAD_FILE
;
2133 * Implements array access of uniforms by inserting a
2134 * PULL_CONSTANT_LOAD instruction.
2136 * Unlike temporary GRF array access (where we don't support it due to
2137 * the difficulty of doing relative addressing on instruction
2138 * destinations), we could potentially do array access of uniforms
2139 * that were loaded in GRF space as push constants. In real-world
2140 * usage we've seen, though, the arrays being used are always larger
2141 * than we could load as push constants, so just always move all
2142 * uniform array access out to a pull constant buffer.
2145 fs_visitor::move_uniform_array_access_to_pull_constants()
2147 if (dispatch_width
!= 8)
2150 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2151 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
2153 /* Walk through and find array access of uniforms. Put a copy of that
2154 * uniform in the pull constant buffer.
2156 * Note that we don't move constant-indexed accesses to arrays. No
2157 * testing has been done of the performance impact of this choice.
2159 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2160 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2161 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
2164 int uniform
= inst
->src
[i
].reg
;
2166 /* If this array isn't already present in the pull constant buffer,
2169 if (pull_constant_loc
[uniform
] == -1) {
2170 const gl_constant_value
**values
= &stage_prog_data
->param
[uniform
];
2172 assert(param_size
[uniform
]);
2174 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
2175 pull_constant_loc
[uniform
+ j
] = stage_prog_data
->nr_pull_params
;
2177 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
2186 * Assign UNIFORM file registers to either push constants or pull constants.
2188 * We allow a fragment shader to have more than the specified minimum
2189 * maximum number of fragment shader uniform components (64). If
2190 * there are too many of these, they'd fill up all of register space.
2191 * So, this will push some of them out to the pull constant buffer and
2192 * update the program to load them.
2195 fs_visitor::assign_constant_locations()
2197 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
2198 if (dispatch_width
!= 8)
2201 /* Find which UNIFORM registers are still in use. */
2202 bool is_live
[uniforms
];
2203 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2207 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2208 for (int i
= 0; i
< inst
->sources
; i
++) {
2209 if (inst
->src
[i
].file
!= UNIFORM
)
2212 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
2213 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
2214 is_live
[constant_nr
] = true;
2218 /* Only allow 16 registers (128 uniform components) as push constants.
2220 * Just demote the end of the list. We could probably do better
2221 * here, demoting things that are rarely used in the program first.
2223 * If changing this value, note the limitation about total_regs in
2226 unsigned int max_push_components
= 16 * 8;
2227 unsigned int num_push_constants
= 0;
2229 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2231 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2232 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
2233 /* This UNIFORM register is either dead, or has already been demoted
2234 * to a pull const. Mark it as no longer living in the param[] array.
2236 push_constant_loc
[i
] = -1;
2240 if (num_push_constants
< max_push_components
) {
2241 /* Retain as a push constant. Record the location in the params[]
2244 push_constant_loc
[i
] = num_push_constants
++;
2246 /* Demote to a pull constant. */
2247 push_constant_loc
[i
] = -1;
2249 int pull_index
= stage_prog_data
->nr_pull_params
++;
2250 stage_prog_data
->pull_param
[pull_index
] = stage_prog_data
->param
[i
];
2251 pull_constant_loc
[i
] = pull_index
;
2255 stage_prog_data
->nr_params
= num_push_constants
;
2257 /* Up until now, the param[] array has been indexed by reg + reg_offset
2258 * of UNIFORM registers. Condense it to only contain the uniforms we
2259 * chose to upload as push constants.
2261 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2262 int remapped
= push_constant_loc
[i
];
2267 assert(remapped
<= (int)i
);
2268 stage_prog_data
->param
[remapped
] = stage_prog_data
->param
[i
];
2273 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2274 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2277 fs_visitor::demote_pull_constants()
2279 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2280 for (int i
= 0; i
< inst
->sources
; i
++) {
2281 if (inst
->src
[i
].file
!= UNIFORM
)
2285 unsigned location
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
2286 if (location
>= uniforms
) /* Out of bounds access */
2289 pull_index
= pull_constant_loc
[location
];
2291 if (pull_index
== -1)
2294 /* Set up the annotation tracking for new generated instructions. */
2296 current_annotation
= inst
->annotation
;
2298 fs_reg
surf_index(stage_prog_data
->binding_table
.pull_constants_start
);
2299 fs_reg dst
= vgrf(glsl_type::float_type
);
2301 /* Generate a pull load into dst. */
2302 if (inst
->src
[i
].reladdr
) {
2303 exec_list list
= VARYING_PULL_CONSTANT_LOAD(dst
,
2305 *inst
->src
[i
].reladdr
,
2307 inst
->insert_before(block
, &list
);
2308 inst
->src
[i
].reladdr
= NULL
;
2310 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
2312 new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, 8,
2313 dst
, surf_index
, offset
);
2314 inst
->insert_before(block
, pull
);
2315 inst
->src
[i
].set_smear(pull_index
& 3);
2318 /* Rewrite the instruction to use the temporary VGRF. */
2319 inst
->src
[i
].file
= GRF
;
2320 inst
->src
[i
].reg
= dst
.reg
;
2321 inst
->src
[i
].reg_offset
= 0;
2322 inst
->src
[i
].width
= dispatch_width
;
2325 invalidate_live_intervals();
2329 fs_visitor::opt_algebraic()
2331 bool progress
= false;
2333 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2334 switch (inst
->opcode
) {
2335 case BRW_OPCODE_MOV
:
2336 if (inst
->src
[0].file
!= IMM
)
2339 if (inst
->saturate
) {
2340 if (inst
->dst
.type
!= inst
->src
[0].type
)
2341 assert(!"unimplemented: saturate mixed types");
2343 if (brw_saturate_immediate(inst
->dst
.type
,
2344 &inst
->src
[0].fixed_hw_reg
)) {
2345 inst
->saturate
= false;
2351 case BRW_OPCODE_MUL
:
2352 if (inst
->src
[1].file
!= IMM
)
2356 if (inst
->src
[1].is_one()) {
2357 inst
->opcode
= BRW_OPCODE_MOV
;
2358 inst
->src
[1] = reg_undef
;
2364 if (inst
->src
[1].is_negative_one()) {
2365 inst
->opcode
= BRW_OPCODE_MOV
;
2366 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2367 inst
->src
[1] = reg_undef
;
2373 if (inst
->src
[1].is_zero()) {
2374 inst
->opcode
= BRW_OPCODE_MOV
;
2375 inst
->src
[0] = inst
->src
[1];
2376 inst
->src
[1] = reg_undef
;
2381 if (inst
->src
[0].file
== IMM
) {
2382 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2383 inst
->opcode
= BRW_OPCODE_MOV
;
2384 inst
->src
[0].fixed_hw_reg
.dw1
.f
*= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2385 inst
->src
[1] = reg_undef
;
2390 case BRW_OPCODE_ADD
:
2391 if (inst
->src
[1].file
!= IMM
)
2395 if (inst
->src
[1].is_zero()) {
2396 inst
->opcode
= BRW_OPCODE_MOV
;
2397 inst
->src
[1] = reg_undef
;
2402 if (inst
->src
[0].file
== IMM
) {
2403 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2404 inst
->opcode
= BRW_OPCODE_MOV
;
2405 inst
->src
[0].fixed_hw_reg
.dw1
.f
+= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2406 inst
->src
[1] = reg_undef
;
2412 if (inst
->src
[0].equals(inst
->src
[1])) {
2413 inst
->opcode
= BRW_OPCODE_MOV
;
2414 inst
->src
[1] = reg_undef
;
2419 case BRW_OPCODE_LRP
:
2420 if (inst
->src
[1].equals(inst
->src
[2])) {
2421 inst
->opcode
= BRW_OPCODE_MOV
;
2422 inst
->src
[0] = inst
->src
[1];
2423 inst
->src
[1] = reg_undef
;
2424 inst
->src
[2] = reg_undef
;
2429 case BRW_OPCODE_CMP
:
2430 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2432 inst
->src
[0].negate
&&
2433 inst
->src
[1].is_zero()) {
2434 inst
->src
[0].abs
= false;
2435 inst
->src
[0].negate
= false;
2436 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2441 case BRW_OPCODE_SEL
:
2442 if (inst
->src
[0].equals(inst
->src
[1])) {
2443 inst
->opcode
= BRW_OPCODE_MOV
;
2444 inst
->src
[1] = reg_undef
;
2445 inst
->predicate
= BRW_PREDICATE_NONE
;
2446 inst
->predicate_inverse
= false;
2448 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2449 switch (inst
->conditional_mod
) {
2450 case BRW_CONDITIONAL_LE
:
2451 case BRW_CONDITIONAL_L
:
2452 switch (inst
->src
[1].type
) {
2453 case BRW_REGISTER_TYPE_F
:
2454 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
>= 1.0f
) {
2455 inst
->opcode
= BRW_OPCODE_MOV
;
2456 inst
->src
[1] = reg_undef
;
2457 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2465 case BRW_CONDITIONAL_GE
:
2466 case BRW_CONDITIONAL_G
:
2467 switch (inst
->src
[1].type
) {
2468 case BRW_REGISTER_TYPE_F
:
2469 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
<= 0.0f
) {
2470 inst
->opcode
= BRW_OPCODE_MOV
;
2471 inst
->src
[1] = reg_undef
;
2472 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2484 case BRW_OPCODE_MAD
:
2485 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2486 inst
->opcode
= BRW_OPCODE_MOV
;
2487 inst
->src
[1] = reg_undef
;
2488 inst
->src
[2] = reg_undef
;
2490 } else if (inst
->src
[0].is_zero()) {
2491 inst
->opcode
= BRW_OPCODE_MUL
;
2492 inst
->src
[0] = inst
->src
[2];
2493 inst
->src
[2] = reg_undef
;
2495 } else if (inst
->src
[1].is_one()) {
2496 inst
->opcode
= BRW_OPCODE_ADD
;
2497 inst
->src
[1] = inst
->src
[2];
2498 inst
->src
[2] = reg_undef
;
2500 } else if (inst
->src
[2].is_one()) {
2501 inst
->opcode
= BRW_OPCODE_ADD
;
2502 inst
->src
[2] = reg_undef
;
2504 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2505 inst
->opcode
= BRW_OPCODE_ADD
;
2506 inst
->src
[1].fixed_hw_reg
.dw1
.f
*= inst
->src
[2].fixed_hw_reg
.dw1
.f
;
2507 inst
->src
[2] = reg_undef
;
2511 case SHADER_OPCODE_RCP
: {
2512 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2513 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2514 if (inst
->src
[0].equals(prev
->dst
)) {
2515 inst
->opcode
= SHADER_OPCODE_RSQ
;
2516 inst
->src
[0] = prev
->src
[0];
2526 /* Swap if src[0] is immediate. */
2527 if (progress
&& inst
->is_commutative()) {
2528 if (inst
->src
[0].file
== IMM
) {
2529 fs_reg tmp
= inst
->src
[1];
2530 inst
->src
[1] = inst
->src
[0];
2539 * Optimize sample messages which are followed by the final RT write.
2541 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2542 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2543 * final texturing results copied to the framebuffer write payload and modify
2544 * them to write to the framebuffer directly.
2547 fs_visitor::opt_sampler_eot()
2549 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2551 if (brw
->gen
< 9 && !brw
->is_cherryview
)
2554 /* FINISHME: It should be possible to implement this optimization when there
2555 * are multiple drawbuffers.
2557 if (key
->nr_color_regions
!= 1)
2560 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2561 fs_inst
*fb_write
= (fs_inst
*) cfg
->blocks
[cfg
->num_blocks
- 1]->end();
2562 assert(fb_write
->eot
);
2563 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2565 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2567 /* There wasn't one; nothing to do. */
2568 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2571 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2572 * It's very likely to be the previous instruction.
2574 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2575 if (load_payload
->is_head_sentinel() ||
2576 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2579 assert(!tex_inst
->eot
); /* We can't get here twice */
2580 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2582 tex_inst
->offset
|= fb_write
->target
<< 24;
2583 tex_inst
->eot
= true;
2584 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2586 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2587 * to create a new LOAD_PAYLOAD command with the same sources and a space
2588 * saved for the header. Using a new destination register not only makes sure
2589 * we have enough space, but it will make sure the dead code eliminator kills
2590 * the instruction that this will replace.
2592 if (tex_inst
->header_present
)
2595 fs_reg send_header
= vgrf(load_payload
->sources
+ 1);
2596 fs_reg
*new_sources
=
2597 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2599 new_sources
[0] = fs_reg();
2600 for (int i
= 0; i
< load_payload
->sources
; i
++)
2601 new_sources
[i
+1] = load_payload
->src
[i
];
2603 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2604 * requires a lot of information about the sources to appropriately figure
2605 * out the number of registers needed to be used. Given this stage in our
2606 * optimization, we may not have the appropriate GRFs required by
2607 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2608 * manually emit the instruction.
2610 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2611 load_payload
->exec_size
,
2614 load_payload
->sources
+ 1);
2616 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2618 tex_inst
->header_present
= true;
2619 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2620 tex_inst
->src
[0] = send_header
;
2621 tex_inst
->dst
= reg_null_ud
;
2627 fs_visitor::opt_register_renaming()
2629 bool progress
= false;
2632 int remap
[alloc
.count
];
2633 memset(remap
, -1, sizeof(int) * alloc
.count
);
2635 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2636 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2638 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2639 inst
->opcode
== BRW_OPCODE_WHILE
) {
2643 /* Rewrite instruction sources. */
2644 for (int i
= 0; i
< inst
->sources
; i
++) {
2645 if (inst
->src
[i
].file
== GRF
&&
2646 remap
[inst
->src
[i
].reg
] != -1 &&
2647 remap
[inst
->src
[i
].reg
] != inst
->src
[i
].reg
) {
2648 inst
->src
[i
].reg
= remap
[inst
->src
[i
].reg
];
2653 const int dst
= inst
->dst
.reg
;
2656 inst
->dst
.file
== GRF
&&
2657 alloc
.sizes
[inst
->dst
.reg
] == inst
->dst
.width
/ 8 &&
2658 !inst
->is_partial_write()) {
2659 if (remap
[dst
] == -1) {
2662 remap
[dst
] = alloc
.allocate(inst
->dst
.width
/ 8);
2663 inst
->dst
.reg
= remap
[dst
];
2666 } else if (inst
->dst
.file
== GRF
&&
2668 remap
[dst
] != dst
) {
2669 inst
->dst
.reg
= remap
[dst
];
2675 invalidate_live_intervals();
2677 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2678 if (delta_xy
[i
].file
== GRF
&& remap
[delta_xy
[i
].reg
] != -1) {
2679 delta_xy
[i
].reg
= remap
[delta_xy
[i
].reg
];
2688 * Remove redundant or useless discard jumps.
2690 * For example, we can eliminate jumps in the following sequence:
2692 * discard-jump (redundant with the next jump)
2693 * discard-jump (useless; jumps to the next instruction)
2697 fs_visitor::opt_redundant_discard_jumps()
2699 bool progress
= false;
2701 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2703 fs_inst
*placeholder_halt
= NULL
;
2704 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2705 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2706 placeholder_halt
= inst
;
2711 if (!placeholder_halt
)
2714 /* Delete any HALTs immediately before the placeholder halt. */
2715 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2716 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2717 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2718 prev
->remove(last_bblock
);
2723 invalidate_live_intervals();
2729 fs_visitor::compute_to_mrf()
2731 bool progress
= false;
2734 /* No MRFs on Gen >= 7. */
2738 calculate_live_intervals();
2740 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2744 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2745 inst
->is_partial_write() ||
2746 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2747 inst
->dst
.type
!= inst
->src
[0].type
||
2748 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2749 !inst
->src
[0].is_contiguous() ||
2750 inst
->src
[0].subreg_offset
)
2753 /* Work out which hardware MRF registers are written by this
2756 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2758 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2759 mrf_high
= mrf_low
+ 4;
2760 } else if (inst
->exec_size
== 16) {
2761 mrf_high
= mrf_low
+ 1;
2766 /* Can't compute-to-MRF this GRF if someone else was going to
2769 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2772 /* Found a move of a GRF to a MRF. Let's see if we can go
2773 * rewrite the thing that made this GRF to write into the MRF.
2775 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2776 if (scan_inst
->dst
.file
== GRF
&&
2777 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2778 /* Found the last thing to write our reg we want to turn
2779 * into a compute-to-MRF.
2782 /* If this one instruction didn't populate all the
2783 * channels, bail. We might be able to rewrite everything
2784 * that writes that reg, but it would require smarter
2785 * tracking to delay the rewriting until complete success.
2787 if (scan_inst
->is_partial_write())
2790 /* Things returning more than one register would need us to
2791 * understand coalescing out more than one MOV at a time.
2793 if (scan_inst
->regs_written
> scan_inst
->dst
.width
/ 8)
2796 /* SEND instructions can't have MRF as a destination. */
2797 if (scan_inst
->mlen
)
2800 if (brw
->gen
== 6) {
2801 /* gen6 math instructions must have the destination be
2802 * GRF, so no compute-to-MRF for them.
2804 if (scan_inst
->is_math()) {
2809 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2810 /* Found the creator of our MRF's source value. */
2811 scan_inst
->dst
.file
= MRF
;
2812 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2813 scan_inst
->saturate
|= inst
->saturate
;
2814 inst
->remove(block
);
2820 /* We don't handle control flow here. Most computation of
2821 * values that end up in MRFs are shortly before the MRF
2824 if (block
->start() == scan_inst
)
2827 /* You can't read from an MRF, so if someone else reads our
2828 * MRF's source GRF that we wanted to rewrite, that stops us.
2830 bool interfered
= false;
2831 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2832 if (scan_inst
->src
[i
].file
== GRF
&&
2833 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2834 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2841 if (scan_inst
->dst
.file
== MRF
) {
2842 /* If somebody else writes our MRF here, we can't
2843 * compute-to-MRF before that.
2845 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2848 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2849 scan_mrf_high
= scan_mrf_low
+ 4;
2850 } else if (scan_inst
->exec_size
== 16) {
2851 scan_mrf_high
= scan_mrf_low
+ 1;
2853 scan_mrf_high
= scan_mrf_low
;
2856 if (mrf_low
== scan_mrf_low
||
2857 mrf_low
== scan_mrf_high
||
2858 mrf_high
== scan_mrf_low
||
2859 mrf_high
== scan_mrf_high
) {
2864 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2865 /* Found a SEND instruction, which means that there are
2866 * live values in MRFs from base_mrf to base_mrf +
2867 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2870 if (mrf_low
>= scan_inst
->base_mrf
&&
2871 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2874 if (mrf_high
>= scan_inst
->base_mrf
&&
2875 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2883 invalidate_live_intervals();
2889 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2890 * instructions to FS_OPCODE_REP_FB_WRITE.
2893 fs_visitor::emit_repclear_shader()
2895 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2897 int color_mrf
= base_mrf
+ 2;
2899 fs_inst
*mov
= emit(MOV(vec4(brw_message_reg(color_mrf
)),
2900 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
)));
2901 mov
->force_writemask_all
= true;
2904 if (key
->nr_color_regions
== 1) {
2905 write
= emit(FS_OPCODE_REP_FB_WRITE
);
2906 write
->saturate
= key
->clamp_fragment_color
;
2907 write
->base_mrf
= color_mrf
;
2909 write
->header_present
= false;
2912 assume(key
->nr_color_regions
> 0);
2913 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2914 write
= emit(FS_OPCODE_REP_FB_WRITE
);
2915 write
->saturate
= key
->clamp_fragment_color
;
2916 write
->base_mrf
= base_mrf
;
2918 write
->header_present
= true;
2926 assign_constant_locations();
2927 assign_curb_setup();
2929 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2930 assert(mov
->src
[0].file
== HW_REG
);
2931 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].fixed_hw_reg
.nr
, 0);
2935 * Walks through basic blocks, looking for repeated MRF writes and
2936 * removing the later ones.
2939 fs_visitor::remove_duplicate_mrf_writes()
2941 fs_inst
*last_mrf_move
[16];
2942 bool progress
= false;
2944 /* Need to update the MRF tracking for compressed instructions. */
2945 if (dispatch_width
== 16)
2948 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2950 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2951 if (inst
->is_control_flow()) {
2952 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2955 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2956 inst
->dst
.file
== MRF
) {
2957 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2958 if (prev_inst
&& inst
->equals(prev_inst
)) {
2959 inst
->remove(block
);
2965 /* Clear out the last-write records for MRFs that were overwritten. */
2966 if (inst
->dst
.file
== MRF
) {
2967 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2970 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2971 /* Found a SEND instruction, which will include two or fewer
2972 * implied MRF writes. We could do better here.
2974 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2975 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2979 /* Clear out any MRF move records whose sources got overwritten. */
2980 if (inst
->dst
.file
== GRF
) {
2981 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2982 if (last_mrf_move
[i
] &&
2983 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2984 last_mrf_move
[i
] = NULL
;
2989 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2990 inst
->dst
.file
== MRF
&&
2991 inst
->src
[0].file
== GRF
&&
2992 !inst
->is_partial_write()) {
2993 last_mrf_move
[inst
->dst
.reg
] = inst
;
2998 invalidate_live_intervals();
3004 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3006 /* Clear the flag for registers that actually got read (as expected). */
3007 for (int i
= 0; i
< inst
->sources
; i
++) {
3009 if (inst
->src
[i
].file
== GRF
) {
3010 grf
= inst
->src
[i
].reg
;
3011 } else if (inst
->src
[i
].file
== HW_REG
&&
3012 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
3013 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
3018 if (grf
>= first_grf
&&
3019 grf
< first_grf
+ grf_len
) {
3020 deps
[grf
- first_grf
] = false;
3021 if (inst
->exec_size
== 16)
3022 deps
[grf
- first_grf
+ 1] = false;
3028 * Implements this workaround for the original 965:
3030 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3031 * check for post destination dependencies on this instruction, software
3032 * must ensure that there is no destination hazard for the case of ‘write
3033 * followed by a posted write’ shown in the following example.
3036 * 2. send r3.xy <rest of send instruction>
3039 * Due to no post-destination dependency check on the ‘send’, the above
3040 * code sequence could have two instructions (1 and 2) in flight at the
3041 * same time that both consider ‘r3’ as the target of their final writes.
3044 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3047 int write_len
= inst
->regs_written
;
3048 int first_write_grf
= inst
->dst
.reg
;
3049 bool needs_dep
[BRW_MAX_MRF
];
3050 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3052 memset(needs_dep
, false, sizeof(needs_dep
));
3053 memset(needs_dep
, true, write_len
);
3055 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3057 /* Walk backwards looking for writes to registers we're writing which
3058 * aren't read since being written. If we hit the start of the program,
3059 * we assume that there are no outstanding dependencies on entry to the
3062 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
3063 /* If we hit control flow, assume that there *are* outstanding
3064 * dependencies, and force their cleanup before our instruction.
3066 if (block
->start() == scan_inst
) {
3067 for (int i
= 0; i
< write_len
; i
++) {
3069 inst
->insert_before(block
, DEP_RESOLVE_MOV(first_write_grf
+ i
));
3075 /* We insert our reads as late as possible on the assumption that any
3076 * instruction but a MOV that might have left us an outstanding
3077 * dependency has more latency than a MOV.
3079 if (scan_inst
->dst
.file
== GRF
) {
3080 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
3081 int reg
= scan_inst
->dst
.reg
+ i
;
3083 if (reg
>= first_write_grf
&&
3084 reg
< first_write_grf
+ write_len
&&
3085 needs_dep
[reg
- first_write_grf
]) {
3086 inst
->insert_before(block
, DEP_RESOLVE_MOV(reg
));
3087 needs_dep
[reg
- first_write_grf
] = false;
3088 if (scan_inst
->exec_size
== 16)
3089 needs_dep
[reg
- first_write_grf
+ 1] = false;
3094 /* Clear the flag for registers that actually got read (as expected). */
3095 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3097 /* Continue the loop only if we haven't resolved all the dependencies */
3099 for (i
= 0; i
< write_len
; i
++) {
3109 * Implements this workaround for the original 965:
3111 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3112 * used as a destination register until after it has been sourced by an
3113 * instruction with a different destination register.
3116 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3118 int write_len
= inst
->regs_written
;
3119 int first_write_grf
= inst
->dst
.reg
;
3120 bool needs_dep
[BRW_MAX_MRF
];
3121 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3123 memset(needs_dep
, false, sizeof(needs_dep
));
3124 memset(needs_dep
, true, write_len
);
3125 /* Walk forwards looking for writes to registers we're writing which aren't
3126 * read before being written.
3128 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
, block
) {
3129 /* If we hit control flow, force resolve all remaining dependencies. */
3130 if (block
->end() == scan_inst
) {
3131 for (int i
= 0; i
< write_len
; i
++) {
3133 scan_inst
->insert_before(block
,
3134 DEP_RESOLVE_MOV(first_write_grf
+ i
));
3139 /* Clear the flag for registers that actually got read (as expected). */
3140 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3142 /* We insert our reads as late as possible since they're reading the
3143 * result of a SEND, which has massive latency.
3145 if (scan_inst
->dst
.file
== GRF
&&
3146 scan_inst
->dst
.reg
>= first_write_grf
&&
3147 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
3148 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
3149 scan_inst
->insert_before(block
, DEP_RESOLVE_MOV(scan_inst
->dst
.reg
));
3150 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
3153 /* Continue the loop only if we haven't resolved all the dependencies */
3155 for (i
= 0; i
< write_len
; i
++) {
3165 fs_visitor::insert_gen4_send_dependency_workarounds()
3167 if (brw
->gen
!= 4 || brw
->is_g4x
)
3170 bool progress
= false;
3172 /* Note that we're done with register allocation, so GRF fs_regs always
3173 * have a .reg_offset of 0.
3176 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3177 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
3178 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3179 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3185 invalidate_live_intervals();
3189 * Turns the generic expression-style uniform pull constant load instruction
3190 * into a hardware-specific series of instructions for loading a pull
3193 * The expression style allows the CSE pass before this to optimize out
3194 * repeated loads from the same offset, and gives the pre-register-allocation
3195 * scheduling full flexibility, while the conversion to native instructions
3196 * allows the post-register-allocation scheduler the best information
3199 * Note that execution masking for setting up pull constant loads is special:
3200 * the channels that need to be written are unrelated to the current execution
3201 * mask, since a later instruction will use one of the result channels as a
3202 * source operand for all 8 or 16 of its channels.
3205 fs_visitor::lower_uniform_pull_constant_loads()
3207 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3208 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3211 if (brw
->gen
>= 7) {
3212 /* The offset arg before was a vec4-aligned byte offset. We need to
3213 * turn it into a dword offset.
3215 fs_reg const_offset_reg
= inst
->src
[1];
3216 assert(const_offset_reg
.file
== IMM
&&
3217 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3218 const_offset_reg
.fixed_hw_reg
.dw1
.ud
/= 4;
3219 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1));
3221 /* We have to use a message header on Skylake to get SIMD4x2 mode.
3222 * Reserve space for the register.
3224 if (brw
->gen
>= 9) {
3225 payload
.reg_offset
++;
3226 alloc
.sizes
[payload
.reg
] = 2;
3229 /* This is actually going to be a MOV, but since only the first dword
3230 * is accessed, we have a special opcode to do just that one. Note
3231 * that this needs to be an operation that will be considered a def
3232 * by live variable analysis, or register allocation will explode.
3234 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3235 8, payload
, const_offset_reg
);
3236 setup
->force_writemask_all
= true;
3238 setup
->ir
= inst
->ir
;
3239 setup
->annotation
= inst
->annotation
;
3240 inst
->insert_before(block
, setup
);
3242 /* Similarly, this will only populate the first 4 channels of the
3243 * result register (since we only use smear values from 0-3), but we
3244 * don't tell the optimizer.
3246 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3247 inst
->src
[1] = payload
;
3249 invalidate_live_intervals();
3251 /* Before register allocation, we didn't tell the scheduler about the
3252 * MRF we use. We know it's safe to use this MRF because nothing
3253 * else does except for register spill/unspill, which generates and
3254 * uses its MRF within a single IR instruction.
3256 inst
->base_mrf
= 14;
3263 fs_visitor::lower_load_payload()
3265 bool progress
= false;
3267 int vgrf_to_reg
[alloc
.count
];
3269 for (unsigned i
= 0; i
< alloc
.count
; ++i
) {
3270 vgrf_to_reg
[i
] = reg_count
;
3271 reg_count
+= alloc
.sizes
[i
];
3275 bool written
:1; /* Whether this register has ever been written */
3276 bool force_writemask_all
:1;
3277 bool force_sechalf
:1;
3278 } metadata
[reg_count
];
3279 memset(metadata
, 0, sizeof(metadata
));
3281 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3282 if (inst
->dst
.file
== GRF
) {
3283 const int dst_reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
3284 bool force_sechalf
= inst
->force_sechalf
&&
3285 !inst
->force_writemask_all
;
3286 bool toggle_sechalf
= inst
->dst
.width
== 16 &&
3287 type_sz(inst
->dst
.type
) == 4 &&
3288 !inst
->force_writemask_all
;
3289 for (int i
= 0; i
< inst
->regs_written
; ++i
) {
3290 metadata
[dst_reg
+ i
].written
= true;
3291 metadata
[dst_reg
+ i
].force_sechalf
= force_sechalf
;
3292 metadata
[dst_reg
+ i
].force_writemask_all
= inst
->force_writemask_all
;
3293 force_sechalf
= (toggle_sechalf
!= force_sechalf
);
3297 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
3298 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== GRF
);
3299 fs_reg dst
= inst
->dst
;
3301 for (int i
= 0; i
< inst
->sources
; i
++) {
3302 dst
.width
= inst
->src
[i
].effective_width
;
3303 dst
.type
= inst
->src
[i
].type
;
3305 if (inst
->src
[i
].file
== BAD_FILE
) {
3306 /* Do nothing but otherwise increment as normal */
3307 } else if (dst
.file
== MRF
&&
3310 i
+ 4 < inst
->sources
&&
3311 inst
->src
[i
+ 4].equals(horiz_offset(inst
->src
[i
], 8))) {
3312 fs_reg compr4_dst
= dst
;
3313 compr4_dst
.reg
+= BRW_MRF_COMPR4
;
3314 compr4_dst
.width
= 16;
3315 fs_reg compr4_src
= inst
->src
[i
];
3316 compr4_src
.width
= 16;
3317 fs_inst
*mov
= MOV(compr4_dst
, compr4_src
);
3318 mov
->force_writemask_all
= true;
3319 inst
->insert_before(block
, mov
);
3320 /* Mark i+4 as BAD_FILE so we don't emit a MOV for it */
3321 inst
->src
[i
+ 4].file
= BAD_FILE
;
3323 fs_inst
*mov
= MOV(dst
, inst
->src
[i
]);
3324 if (inst
->src
[i
].file
== GRF
) {
3325 int src_reg
= vgrf_to_reg
[inst
->src
[i
].reg
] +
3326 inst
->src
[i
].reg_offset
;
3327 mov
->force_sechalf
= metadata
[src_reg
].force_sechalf
;
3328 mov
->force_writemask_all
= metadata
[src_reg
].force_writemask_all
;
3330 /* We don't have any useful metadata for immediates or
3331 * uniforms. Assume that any of the channels of the
3332 * destination may be used.
3334 assert(inst
->src
[i
].file
== IMM
||
3335 inst
->src
[i
].file
== UNIFORM
);
3336 mov
->force_writemask_all
= true;
3339 if (dst
.file
== GRF
) {
3340 const int dst_reg
= vgrf_to_reg
[dst
.reg
] + dst
.reg_offset
;
3341 const bool force_writemask
= mov
->force_writemask_all
;
3342 metadata
[dst_reg
].force_writemask_all
= force_writemask
;
3343 metadata
[dst_reg
].force_sechalf
= mov
->force_sechalf
;
3344 if (dst
.width
* type_sz(dst
.type
) > 32) {
3345 assert(!mov
->force_sechalf
);
3346 metadata
[dst_reg
+ 1].force_writemask_all
= force_writemask
;
3347 metadata
[dst_reg
+ 1].force_sechalf
= !force_writemask
;
3351 inst
->insert_before(block
, mov
);
3354 dst
= offset(dst
, 1);
3357 inst
->remove(block
);
3363 invalidate_live_intervals();
3369 fs_visitor::dump_instructions()
3371 dump_instructions(NULL
);
3375 fs_visitor::dump_instructions(const char *name
)
3377 FILE *file
= stderr
;
3378 if (name
&& geteuid() != 0) {
3379 file
= fopen(name
, "w");
3385 calculate_register_pressure();
3386 int ip
= 0, max_pressure
= 0;
3387 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
3388 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
3389 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
3390 dump_instruction(inst
, file
);
3393 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
3396 foreach_in_list(backend_instruction
, inst
, &instructions
) {
3397 fprintf(file
, "%4d: ", ip
++);
3398 dump_instruction(inst
, file
);
3402 if (file
!= stderr
) {
3408 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
3410 dump_instruction(be_inst
, stderr
);
3414 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
3416 fs_inst
*inst
= (fs_inst
*)be_inst
;
3418 if (inst
->predicate
) {
3419 fprintf(file
, "(%cf0.%d) ",
3420 inst
->predicate_inverse
? '-' : '+',
3424 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
3426 fprintf(file
, ".sat");
3427 if (inst
->conditional_mod
) {
3428 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
3429 if (!inst
->predicate
&&
3430 (brw
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
3431 inst
->opcode
!= BRW_OPCODE_IF
&&
3432 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
3433 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
3436 fprintf(file
, "(%d) ", inst
->exec_size
);
3439 switch (inst
->dst
.file
) {
3441 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
3442 if (inst
->dst
.width
!= dispatch_width
)
3443 fprintf(file
, "@%d", inst
->dst
.width
);
3444 if (alloc
.sizes
[inst
->dst
.reg
] != inst
->dst
.width
/ 8 ||
3445 inst
->dst
.subreg_offset
)
3446 fprintf(file
, "+%d.%d",
3447 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
3450 fprintf(file
, "m%d", inst
->dst
.reg
);
3453 fprintf(file
, "(null)");
3456 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
3459 fprintf(file
, "***attr%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
3462 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3463 switch (inst
->dst
.fixed_hw_reg
.nr
) {
3465 fprintf(file
, "null");
3467 case BRW_ARF_ADDRESS
:
3468 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
3470 case BRW_ARF_ACCUMULATOR
:
3471 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
3474 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3475 inst
->dst
.fixed_hw_reg
.subnr
);
3478 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3479 inst
->dst
.fixed_hw_reg
.subnr
);
3483 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
3485 if (inst
->dst
.fixed_hw_reg
.subnr
)
3486 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
3489 fprintf(file
, "???");
3492 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
3494 for (int i
= 0; i
< inst
->sources
; i
++) {
3495 if (inst
->src
[i
].negate
)
3497 if (inst
->src
[i
].abs
)
3499 switch (inst
->src
[i
].file
) {
3501 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
3502 if (inst
->src
[i
].width
!= dispatch_width
)
3503 fprintf(file
, "@%d", inst
->src
[i
].width
);
3504 if (alloc
.sizes
[inst
->src
[i
].reg
] != inst
->src
[i
].width
/ 8 ||
3505 inst
->src
[i
].subreg_offset
)
3506 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
3507 inst
->src
[i
].subreg_offset
);
3510 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
3513 fprintf(file
, "attr%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
3516 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
3517 if (inst
->src
[i
].reladdr
) {
3518 fprintf(file
, "+reladdr");
3519 } else if (inst
->src
[i
].subreg_offset
) {
3520 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
3521 inst
->src
[i
].subreg_offset
);
3525 fprintf(file
, "(null)");
3528 switch (inst
->src
[i
].type
) {
3529 case BRW_REGISTER_TYPE_F
:
3530 fprintf(file
, "%ff", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
3532 case BRW_REGISTER_TYPE_W
:
3533 case BRW_REGISTER_TYPE_D
:
3534 fprintf(file
, "%dd", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
3536 case BRW_REGISTER_TYPE_UW
:
3537 case BRW_REGISTER_TYPE_UD
:
3538 fprintf(file
, "%uu", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
3540 case BRW_REGISTER_TYPE_VF
:
3541 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
3542 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
3543 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
3544 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
3545 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
3548 fprintf(file
, "???");
3553 if (inst
->src
[i
].fixed_hw_reg
.negate
)
3555 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3557 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3558 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
3560 fprintf(file
, "null");
3562 case BRW_ARF_ADDRESS
:
3563 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3565 case BRW_ARF_ACCUMULATOR
:
3566 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3569 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3570 inst
->src
[i
].fixed_hw_reg
.subnr
);
3573 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3574 inst
->src
[i
].fixed_hw_reg
.subnr
);
3578 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
3580 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
3581 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3582 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3586 fprintf(file
, "???");
3589 if (inst
->src
[i
].abs
)
3592 if (inst
->src
[i
].file
!= IMM
) {
3593 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
3596 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
3597 fprintf(file
, ", ");
3602 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
3603 if (inst
->force_sechalf
)
3604 fprintf(file
, "2ndhalf ");
3606 fprintf(file
, "1sthalf ");
3609 fprintf(file
, "\n");
3613 * Possibly returns an instruction that set up @param reg.
3615 * Sometimes we want to take the result of some expression/variable
3616 * dereference tree and rewrite the instruction generating the result
3617 * of the tree. When processing the tree, we know that the
3618 * instructions generated are all writing temporaries that are dead
3619 * outside of this tree. So, if we have some instructions that write
3620 * a temporary, we're free to point that temp write somewhere else.
3622 * Note that this doesn't guarantee that the instruction generated
3623 * only reg -- it might be the size=4 destination of a texture instruction.
3626 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
3631 end
->is_partial_write() ||
3633 !reg
.equals(end
->dst
)) {
3641 fs_visitor::setup_payload_gen6()
3644 (prog
->InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
3645 unsigned barycentric_interp_modes
=
3646 (stage
== MESA_SHADER_FRAGMENT
) ?
3647 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
3649 assert(brw
->gen
>= 6);
3651 /* R0-1: masks, pixel X/Y coordinates. */
3652 payload
.num_regs
= 2;
3653 /* R2: only for 32-pixel dispatch.*/
3655 /* R3-26: barycentric interpolation coordinates. These appear in the
3656 * same order that they appear in the brw_wm_barycentric_interp_mode
3657 * enum. Each set of coordinates occupies 2 registers if dispatch width
3658 * == 8 and 4 registers if dispatch width == 16. Coordinates only
3659 * appear if they were enabled using the "Barycentric Interpolation
3660 * Mode" bits in WM_STATE.
3662 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
3663 if (barycentric_interp_modes
& (1 << i
)) {
3664 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
3665 payload
.num_regs
+= 2;
3666 if (dispatch_width
== 16) {
3667 payload
.num_regs
+= 2;
3672 /* R27: interpolated depth if uses source depth */
3674 payload
.source_depth_reg
= payload
.num_regs
;
3676 if (dispatch_width
== 16) {
3677 /* R28: interpolated depth if not SIMD8. */
3681 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
3683 payload
.source_w_reg
= payload
.num_regs
;
3685 if (dispatch_width
== 16) {
3686 /* R30: interpolated W if not SIMD8. */
3691 if (stage
== MESA_SHADER_FRAGMENT
) {
3692 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3693 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3694 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
3695 /* R31: MSAA position offsets. */
3696 if (prog_data
->uses_pos_offset
) {
3697 payload
.sample_pos_reg
= payload
.num_regs
;
3702 /* R32: MSAA input coverage mask */
3703 if (prog
->SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
3704 assert(brw
->gen
>= 7);
3705 payload
.sample_mask_in_reg
= payload
.num_regs
;
3707 if (dispatch_width
== 16) {
3708 /* R33: input coverage mask if not SIMD8. */
3713 /* R34-: bary for 32-pixel. */
3714 /* R58-59: interp W for 32-pixel. */
3716 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3717 source_depth_to_render_target
= true;
3722 fs_visitor::setup_vs_payload()
3724 /* R0: thread header, R1: urb handles */
3725 payload
.num_regs
= 2;
3729 fs_visitor::assign_binding_table_offsets()
3731 assert(stage
== MESA_SHADER_FRAGMENT
);
3732 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3733 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3734 uint32_t next_binding_table_offset
= 0;
3736 /* If there are no color regions, we still perform an FB write to a null
3737 * renderbuffer, which we place at surface index 0.
3739 prog_data
->binding_table
.render_target_start
= next_binding_table_offset
;
3740 next_binding_table_offset
+= MAX2(key
->nr_color_regions
, 1);
3742 assign_common_binding_table_offsets(next_binding_table_offset
);
3746 fs_visitor::calculate_register_pressure()
3748 invalidate_live_intervals();
3749 calculate_live_intervals();
3751 unsigned num_instructions
= 0;
3752 foreach_block(block
, cfg
)
3753 num_instructions
+= block
->instructions
.length();
3755 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
3757 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
3758 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
3759 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
3764 fs_visitor::optimize()
3766 const char *stage_name
= stage
== MESA_SHADER_VERTEX
? "vs" : "fs";
3768 split_virtual_grfs();
3770 move_uniform_array_access_to_pull_constants();
3771 assign_constant_locations();
3772 demote_pull_constants();
3774 #define OPT(pass, args...) ({ \
3776 bool this_progress = pass(args); \
3778 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
3779 char filename[64]; \
3780 snprintf(filename, 64, "%s%d-%04d-%02d-%02d-" #pass, \
3781 stage_name, dispatch_width, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
3783 backend_visitor::dump_instructions(filename); \
3786 progress = progress || this_progress; \
3790 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
3792 snprintf(filename
, 64, "%s%d-%04d-00-start",
3793 stage_name
, dispatch_width
, shader_prog
? shader_prog
->Name
: 0);
3795 backend_visitor::dump_instructions(filename
);
3806 OPT(remove_duplicate_mrf_writes
);
3810 OPT(opt_copy_propagate
);
3811 OPT(opt_peephole_predicated_break
);
3812 OPT(opt_cmod_propagation
);
3813 OPT(dead_code_eliminate
);
3814 OPT(opt_peephole_sel
);
3815 OPT(dead_control_flow_eliminate
, this);
3816 OPT(opt_register_renaming
);
3817 OPT(opt_redundant_discard_jumps
);
3818 OPT(opt_saturate_propagation
);
3819 OPT(register_coalesce
);
3820 OPT(compute_to_mrf
);
3822 OPT(compact_virtual_grfs
);
3827 OPT(opt_sampler_eot
);
3829 if (OPT(lower_load_payload
)) {
3830 split_virtual_grfs();
3831 OPT(register_coalesce
);
3832 OPT(compute_to_mrf
);
3833 OPT(dead_code_eliminate
);
3836 OPT(opt_combine_constants
);
3838 lower_uniform_pull_constant_loads();
3842 * Three source instruction must have a GRF/MRF destination register.
3843 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
3846 fs_visitor::fixup_3src_null_dest()
3848 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3849 if (inst
->is_3src() && inst
->dst
.is_null()) {
3850 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
3857 fs_visitor::allocate_registers()
3859 bool allocated_without_spills
;
3861 static const enum instruction_scheduler_mode pre_modes
[] = {
3863 SCHEDULE_PRE_NON_LIFO
,
3867 /* Try each scheduling heuristic to see if it can successfully register
3868 * allocate without spilling. They should be ordered by decreasing
3869 * performance but increasing likelihood of allocating.
3871 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
3872 schedule_instructions(pre_modes
[i
]);
3875 assign_regs_trivial();
3876 allocated_without_spills
= true;
3878 allocated_without_spills
= assign_regs(false);
3880 if (allocated_without_spills
)
3884 if (!allocated_without_spills
) {
3885 const char *stage_name
= stage
== MESA_SHADER_VERTEX
?
3886 "Vertex" : "Fragment";
3888 /* We assume that any spilling is worse than just dropping back to
3889 * SIMD8. There's probably actually some intermediate point where
3890 * SIMD16 with a couple of spills is still better.
3892 if (dispatch_width
== 16) {
3893 fail("Failure to register allocate. Reduce number of "
3894 "live scalar values to avoid this.");
3896 perf_debug("%s shader triggered register spilling. "
3897 "Try reducing the number of live scalar values to "
3898 "improve performance.\n", stage_name
);
3901 /* Since we're out of heuristics, just go spill registers until we
3902 * get an allocation.
3904 while (!assign_regs(true)) {
3910 /* This must come after all optimization and register allocation, since
3911 * it inserts dead code that happens to have side effects, and it does
3912 * so based on the actual physical registers in use.
3914 insert_gen4_send_dependency_workarounds();
3919 if (!allocated_without_spills
)
3920 schedule_instructions(SCHEDULE_POST
);
3922 if (last_scratch
> 0)
3923 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
3927 fs_visitor::run_vs()
3929 assert(stage
== MESA_SHADER_VERTEX
);
3931 assign_common_binding_table_offsets(0);
3934 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3935 emit_shader_time_begin();
3937 if (brw
->ctx
.Const
.ShaderCompilerOptions
[MESA_SHADER_VERTEX
].NirOptions
) {
3940 foreach_in_list(ir_instruction
, ir
, shader
->base
.ir
) {
3942 this->result
= reg_undef
;
3953 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3954 emit_shader_time_end();
3960 assign_curb_setup();
3961 assign_vs_urb_setup();
3963 fixup_3src_null_dest();
3964 allocate_registers();
3970 fs_visitor::run_fs()
3972 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3973 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
3975 assert(stage
== MESA_SHADER_FRAGMENT
);
3977 sanity_param_count
= prog
->Parameters
->NumParameters
;
3979 assign_binding_table_offsets();
3982 setup_payload_gen6();
3984 setup_payload_gen4();
3988 } else if (brw
->use_rep_send
&& dispatch_width
== 16) {
3989 emit_repclear_shader();
3991 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3992 emit_shader_time_begin();
3994 calculate_urb_setup();
3995 if (prog
->InputsRead
> 0) {
3997 emit_interpolation_setup_gen4();
3999 emit_interpolation_setup_gen6();
4002 /* We handle discards by keeping track of the still-live pixels in f0.1.
4003 * Initialize it with the dispatched pixels.
4005 if (wm_prog_data
->uses_kill
) {
4006 fs_inst
*discard_init
= emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
4007 discard_init
->flag_subreg
= 1;
4010 /* Generate FS IR for main(). (the visitor only descends into
4011 * functions called "main").
4013 if (brw
->ctx
.Const
.ShaderCompilerOptions
[MESA_SHADER_FRAGMENT
].NirOptions
) {
4015 } else if (shader
) {
4016 foreach_in_list(ir_instruction
, ir
, shader
->base
.ir
) {
4018 this->result
= reg_undef
;
4022 emit_fragment_program_code();
4028 if (wm_prog_data
->uses_kill
)
4029 emit(FS_OPCODE_PLACEHOLDER_HALT
);
4031 if (wm_key
->alpha_test_func
)
4036 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
4037 emit_shader_time_end();
4043 assign_curb_setup();
4046 fixup_3src_null_dest();
4047 allocate_registers();
4053 if (dispatch_width
== 8)
4054 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
4056 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
4058 /* If any state parameters were appended, then ParameterValues could have
4059 * been realloced, in which case the driver uniform storage set up by
4060 * _mesa_associate_uniform_storage() would point to freed memory. Make
4061 * sure that didn't happen.
4063 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
4069 brw_wm_fs_emit(struct brw_context
*brw
,
4071 const struct brw_wm_prog_key
*key
,
4072 struct brw_wm_prog_data
*prog_data
,
4073 struct gl_fragment_program
*fp
,
4074 struct gl_shader_program
*prog
,
4075 unsigned *final_assembly_size
)
4077 bool start_busy
= false;
4078 double start_time
= 0;
4080 if (unlikely(brw
->perf_debug
)) {
4081 start_busy
= (brw
->batch
.last_bo
&&
4082 drm_intel_bo_busy(brw
->batch
.last_bo
));
4083 start_time
= get_time();
4086 struct brw_shader
*shader
= NULL
;
4088 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
4090 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
4091 brw_dump_ir("fragment", prog
, &shader
->base
, &fp
->Base
);
4093 /* Now the main event: Visit the shader IR and generate our FS IR for it.
4095 fs_visitor
v(brw
, mem_ctx
, key
, prog_data
, prog
, fp
, 8);
4098 prog
->LinkStatus
= false;
4099 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
4102 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
4108 cfg_t
*simd16_cfg
= NULL
;
4109 fs_visitor
v2(brw
, mem_ctx
, key
, prog_data
, prog
, fp
, 16);
4110 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || brw
->use_rep_send
)) {
4111 if (!v
.simd16_unsupported
) {
4112 /* Try a SIMD16 compile */
4113 v2
.import_uniforms(&v
);
4115 perf_debug("SIMD16 shader failed to compile, falling back to "
4116 "SIMD8 at a 10-20%% performance cost: %s", v2
.fail_msg
);
4118 simd16_cfg
= v2
.cfg
;
4121 perf_debug("SIMD16 shader unsupported, falling back to "
4122 "SIMD8 at a 10-20%% performance cost: %s", v
.no16_msg
);
4127 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || brw
->no_simd8
;
4128 if ((no_simd8
|| brw
->gen
< 5) && simd16_cfg
) {
4130 prog_data
->no_8
= true;
4133 prog_data
->no_8
= false;
4136 fs_generator
g(brw
, mem_ctx
, (void *) key
, &prog_data
->base
,
4137 &fp
->Base
, v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
4139 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
4142 name
= ralloc_asprintf(mem_ctx
, "%s fragment shader %d",
4143 prog
->Label
? prog
->Label
: "unnamed",
4146 name
= ralloc_asprintf(mem_ctx
, "fragment program %d", fp
->Base
.Id
);
4148 g
.enable_debug(name
);
4152 g
.generate_code(simd8_cfg
, 8);
4154 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
4156 if (unlikely(brw
->perf_debug
) && shader
) {
4157 if (shader
->compiled_once
)
4158 brw_wm_debug_recompile(brw
, prog
, key
);
4159 shader
->compiled_once
= true;
4161 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
4162 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
4163 (get_time() - start_time
) * 1000);
4167 return g
.get_assembly(final_assembly_size
);
4171 brw_fs_precompile(struct gl_context
*ctx
,
4172 struct gl_shader_program
*shader_prog
,
4173 struct gl_program
*prog
)
4175 struct brw_context
*brw
= brw_context(ctx
);
4176 struct brw_wm_prog_key key
;
4178 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*) prog
;
4179 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
4180 bool program_uses_dfdy
= fp
->UsesDFdy
;
4182 memset(&key
, 0, sizeof(key
));
4186 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
4188 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
4189 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
4191 /* Just assume depth testing. */
4192 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
4193 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
4196 if (brw
->gen
< 6 || _mesa_bitcount_64(fp
->Base
.InputsRead
&
4197 BRW_FS_VARYING_INPUT_MASK
) > 16)
4198 key
.input_slots_valid
= fp
->Base
.InputsRead
| VARYING_BIT_POS
;
4200 const bool has_shader_channel_select
= brw
->is_haswell
|| brw
->gen
>= 8;
4201 unsigned sampler_count
= _mesa_fls(fp
->Base
.SamplersUsed
);
4202 for (unsigned i
= 0; i
< sampler_count
; i
++) {
4203 if (!has_shader_channel_select
&& (fp
->Base
.ShadowSamplers
& (1 << i
))) {
4204 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
4205 key
.tex
.swizzles
[i
] =
4206 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
4208 /* Color sampler: assume no swizzling. */
4209 key
.tex
.swizzles
[i
] = SWIZZLE_XYZW
;
4213 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
) {
4214 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
4217 key
.nr_color_regions
= _mesa_bitcount_64(fp
->Base
.OutputsWritten
&
4218 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
4219 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
)));
4221 if ((fp
->Base
.InputsRead
& VARYING_BIT_POS
) || program_uses_dfdy
) {
4222 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
) ||
4223 key
.nr_color_regions
> 1;
4226 key
.program_string_id
= bfp
->id
;
4228 uint32_t old_prog_offset
= brw
->wm
.base
.prog_offset
;
4229 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
4231 bool success
= brw_compile_wm_prog(brw
, shader_prog
, bfp
, &key
);
4233 brw
->wm
.base
.prog_offset
= old_prog_offset
;
4234 brw
->wm
.prog_data
= old_prog_data
;