2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "../glsl/glsl_types.h"
47 #include "../glsl/ir_optimization.h"
48 #include "../glsl/ir_print_visitor.h"
50 #define MAX_INSTRUCTION (1 << 30)
51 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
54 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
56 struct brw_shader
*shader
;
58 shader
= talloc_zero(NULL
, struct brw_shader
);
60 shader
->base
.Type
= type
;
61 shader
->base
.Name
= name
;
62 _mesa_init_shader(ctx
, &shader
->base
);
68 struct gl_shader_program
*
69 brw_new_shader_program(struct gl_context
*ctx
, GLuint name
)
71 struct brw_shader_program
*prog
;
72 prog
= talloc_zero(NULL
, struct brw_shader_program
);
74 prog
->base
.Name
= name
;
75 _mesa_init_shader_program(ctx
, &prog
->base
);
81 brw_compile_shader(struct gl_context
*ctx
, struct gl_shader
*shader
)
83 if (!_mesa_ir_compile_shader(ctx
, shader
))
90 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
92 struct brw_context
*brw
= brw_context(ctx
);
93 struct intel_context
*intel
= &brw
->intel
;
95 struct brw_shader
*shader
=
96 (struct brw_shader
*)prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
98 void *mem_ctx
= talloc_new(NULL
);
102 talloc_free(shader
->ir
);
103 shader
->ir
= new(shader
) exec_list
;
104 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
106 do_mat_op_to_vec(shader
->ir
);
107 lower_instructions(shader
->ir
,
114 /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
115 * if-statements need to be flattened.
118 lower_if_to_cond_assign(shader
->ir
, 16);
120 do_lower_texture_projection(shader
->ir
);
121 do_vec_index_to_cond_assign(shader
->ir
);
122 brw_do_cubemap_normalize(shader
->ir
);
127 brw_do_channel_expressions(shader
->ir
);
128 brw_do_vector_splitting(shader
->ir
);
130 progress
= do_lower_jumps(shader
->ir
, true, true,
131 true, /* main return */
132 false, /* continue */
136 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
138 progress
= lower_noise(shader
->ir
) || progress
;
140 lower_variable_index_to_cond_assign(shader
->ir
,
142 GL_TRUE
, /* output */
144 GL_TRUE
/* uniform */
146 progress
= lower_quadop_vector(shader
->ir
, false) || progress
;
149 validate_ir_tree(shader
->ir
);
151 reparent_ir(shader
->ir
, shader
->ir
);
152 talloc_free(mem_ctx
);
155 if (!_mesa_ir_link_shader(ctx
, prog
))
162 type_size(const struct glsl_type
*type
)
164 unsigned int size
, i
;
166 switch (type
->base_type
) {
169 case GLSL_TYPE_FLOAT
:
171 return type
->components();
172 case GLSL_TYPE_ARRAY
:
173 return type_size(type
->fields
.array
) * type
->length
;
174 case GLSL_TYPE_STRUCT
:
176 for (i
= 0; i
< type
->length
; i
++) {
177 size
+= type_size(type
->fields
.structure
[i
].type
);
180 case GLSL_TYPE_SAMPLER
:
181 /* Samplers take up no register space, since they're baked in at
186 assert(!"not reached");
192 * Returns how many MRFs an FS opcode will write over.
194 * Note that this is not the 0 or 1 implied writes in an actual gen
195 * instruction -- the FS opcodes often generate MOVs in addition.
198 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
203 switch (inst
->opcode
) {
218 case FS_OPCODE_FB_WRITE
:
220 case FS_OPCODE_PULL_CONSTANT_LOAD
:
221 case FS_OPCODE_UNSPILL
:
223 case FS_OPCODE_SPILL
:
226 assert(!"not reached");
232 fs_visitor::virtual_grf_alloc(int size
)
234 if (virtual_grf_array_size
<= virtual_grf_next
) {
235 if (virtual_grf_array_size
== 0)
236 virtual_grf_array_size
= 16;
238 virtual_grf_array_size
*= 2;
239 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
240 int, virtual_grf_array_size
);
242 /* This slot is always unused. */
243 virtual_grf_sizes
[0] = 0;
245 virtual_grf_sizes
[virtual_grf_next
] = size
;
246 return virtual_grf_next
++;
249 /** Fixed HW reg constructor. */
250 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
254 this->hw_reg
= hw_reg
;
255 this->type
= BRW_REGISTER_TYPE_F
;
258 /** Fixed HW reg constructor. */
259 fs_reg::fs_reg(enum register_file file
, int hw_reg
, uint32_t type
)
263 this->hw_reg
= hw_reg
;
268 brw_type_for_base_type(const struct glsl_type
*type
)
270 switch (type
->base_type
) {
271 case GLSL_TYPE_FLOAT
:
272 return BRW_REGISTER_TYPE_F
;
275 return BRW_REGISTER_TYPE_D
;
277 return BRW_REGISTER_TYPE_UD
;
278 case GLSL_TYPE_ARRAY
:
279 case GLSL_TYPE_STRUCT
:
280 case GLSL_TYPE_SAMPLER
:
281 /* These should be overridden with the type of the member when
282 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
283 * way to trip up if we don't.
285 return BRW_REGISTER_TYPE_UD
;
287 assert(!"not reached");
288 return BRW_REGISTER_TYPE_F
;
292 /** Automatic reg constructor. */
293 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
298 this->reg
= v
->virtual_grf_alloc(type_size(type
));
299 this->reg_offset
= 0;
300 this->type
= brw_type_for_base_type(type
);
304 fs_visitor::variable_storage(ir_variable
*var
)
306 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
309 /* Our support for uniforms is piggy-backed on the struct
310 * gl_fragment_program, because that's where the values actually
311 * get stored, rather than in some global gl_shader_program uniform
315 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
317 unsigned int offset
= 0;
319 if (type
->is_matrix()) {
320 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
321 type
->vector_elements
,
324 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
325 offset
+= setup_uniform_values(loc
+ offset
, column
);
331 switch (type
->base_type
) {
332 case GLSL_TYPE_FLOAT
:
336 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
337 unsigned int param
= c
->prog_data
.nr_params
++;
339 assert(param
< ARRAY_SIZE(c
->prog_data
.param
));
341 switch (type
->base_type
) {
342 case GLSL_TYPE_FLOAT
:
343 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
346 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2U
;
349 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2I
;
352 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2B
;
355 assert(!"not reached");
356 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
359 this->param_index
[param
] = loc
;
360 this->param_offset
[param
] = i
;
364 case GLSL_TYPE_STRUCT
:
365 for (unsigned int i
= 0; i
< type
->length
; i
++) {
366 offset
+= setup_uniform_values(loc
+ offset
,
367 type
->fields
.structure
[i
].type
);
371 case GLSL_TYPE_ARRAY
:
372 for (unsigned int i
= 0; i
< type
->length
; i
++) {
373 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
377 case GLSL_TYPE_SAMPLER
:
378 /* The sampler takes up a slot, but we don't use any values from it. */
382 assert(!"not reached");
388 /* Our support for builtin uniforms is even scarier than non-builtin.
389 * It sits on top of the PROG_STATE_VAR parameters that are
390 * automatically updated from GL context state.
393 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
395 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
397 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
398 statevar
= &_mesa_builtin_uniform_desc
[i
];
399 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
403 if (!statevar
->name
) {
405 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
410 if (ir
->type
->is_array()) {
411 array_count
= ir
->type
->length
;
416 for (int a
= 0; a
< array_count
; a
++) {
417 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
418 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
419 int tokens
[STATE_LENGTH
];
421 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
422 if (ir
->type
->is_array()) {
426 /* This state reference has already been setup by ir_to_mesa,
427 * but we'll get the same index back here.
429 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
430 (gl_state_index
*)tokens
);
432 /* Add each of the unique swizzles of the element as a
433 * parameter. This'll end up matching the expected layout of
434 * the array/matrix/structure we're trying to fill in.
437 for (unsigned int i
= 0; i
< 4; i
++) {
438 int swiz
= GET_SWZ(element
->swizzle
, i
);
439 if (swiz
== last_swiz
)
443 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
445 this->param_index
[c
->prog_data
.nr_params
] = index
;
446 this->param_offset
[c
->prog_data
.nr_params
] = swiz
;
447 c
->prog_data
.nr_params
++;
454 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
456 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
458 fs_reg neg_y
= this->pixel_y
;
460 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
463 if (ir
->pixel_center_integer
) {
464 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
466 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
471 if (!flip
&& ir
->pixel_center_integer
) {
472 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
474 fs_reg pixel_y
= this->pixel_y
;
475 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
478 pixel_y
.negate
= true;
479 offset
+= c
->key
.drawable_height
- 1.0;
482 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
487 if (intel
->gen
>= 6) {
488 emit(fs_inst(BRW_OPCODE_MOV
, wpos
,
489 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
491 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
492 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
496 /* gl_FragCoord.w: Already set up in emit_interpolation */
497 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
503 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
505 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
506 /* Interpolation is always in floating point regs. */
507 reg
->type
= BRW_REGISTER_TYPE_F
;
510 unsigned int array_elements
;
511 const glsl_type
*type
;
513 if (ir
->type
->is_array()) {
514 array_elements
= ir
->type
->length
;
515 if (array_elements
== 0) {
518 type
= ir
->type
->fields
.array
;
524 int location
= ir
->location
;
525 for (unsigned int i
= 0; i
< array_elements
; i
++) {
526 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
527 if (urb_setup
[location
] == -1) {
528 /* If there's no incoming setup data for this slot, don't
529 * emit interpolation for it.
531 attr
.reg_offset
+= type
->vector_elements
;
536 if (c
->key
.flat_shade
&& (location
== FRAG_ATTRIB_COL0
||
537 location
== FRAG_ATTRIB_COL1
)) {
538 /* Constant interpolation (flat shading) case. The SF has
539 * handed us defined values in only the constant offset
540 * field of the setup reg.
542 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
543 struct brw_reg interp
= interp_reg(location
, c
);
544 interp
= suboffset(interp
, 3);
545 emit(fs_inst(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
)));
549 /* Perspective interpolation case. */
550 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
551 struct brw_reg interp
= interp_reg(location
, c
);
552 emit(fs_inst(FS_OPCODE_LINTERP
,
560 if (intel
->gen
< 6) {
561 attr
.reg_offset
-= type
->vector_elements
;
562 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
563 emit(fs_inst(BRW_OPCODE_MUL
,
579 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
581 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
583 /* The frontfacing comes in as a bit in the thread payload. */
584 if (intel
->gen
>= 6) {
585 emit(fs_inst(BRW_OPCODE_ASR
,
587 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
589 emit(fs_inst(BRW_OPCODE_NOT
,
592 emit(fs_inst(BRW_OPCODE_AND
,
597 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
598 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
601 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
605 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
606 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
613 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src
)
625 assert(!"not reached: bad math opcode");
629 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
630 * might be able to do better by doing execsize = 1 math and then
631 * expanding that result out, but we would need to be careful with
634 * The hardware ignores source modifiers (negate and abs) on math
635 * instructions, so we also move to a temp to set those up.
637 if (intel
->gen
>= 6 && (src
.file
== UNIFORM
||
640 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
641 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src
));
645 fs_inst
*inst
= emit(fs_inst(opcode
, dst
, src
));
647 if (intel
->gen
< 6) {
656 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
661 assert(opcode
== FS_OPCODE_POW
);
663 if (intel
->gen
>= 6) {
664 /* Can't do hstride == 0 args to gen6 math, so expand it out. */
665 if (src0
.file
== UNIFORM
) {
666 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
667 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src0
));
671 if (src1
.file
== UNIFORM
) {
672 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
673 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src1
));
677 inst
= emit(fs_inst(opcode
, dst
, src0
, src1
));
679 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1), src1
));
680 inst
= emit(fs_inst(opcode
, dst
, src0
, reg_null_f
));
682 inst
->base_mrf
= base_mrf
;
689 fs_visitor::visit(ir_variable
*ir
)
693 if (variable_storage(ir
))
696 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
697 this->frag_color
= ir
;
698 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
699 this->frag_data
= ir
;
700 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
701 this->frag_depth
= ir
;
704 if (ir
->mode
== ir_var_in
) {
705 if (!strcmp(ir
->name
, "gl_FragCoord")) {
706 reg
= emit_fragcoord_interpolation(ir
);
707 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
708 reg
= emit_frontfacing_interpolation(ir
);
710 reg
= emit_general_interpolation(ir
);
713 hash_table_insert(this->variable_ht
, reg
, ir
);
717 if (ir
->mode
== ir_var_uniform
) {
718 int param_index
= c
->prog_data
.nr_params
;
720 if (!strncmp(ir
->name
, "gl_", 3)) {
721 setup_builtin_uniform_values(ir
);
723 setup_uniform_values(ir
->location
, ir
->type
);
726 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
727 reg
->type
= brw_type_for_base_type(ir
->type
);
731 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
733 hash_table_insert(this->variable_ht
, reg
, ir
);
737 fs_visitor::visit(ir_dereference_variable
*ir
)
739 fs_reg
*reg
= variable_storage(ir
->var
);
744 fs_visitor::visit(ir_dereference_record
*ir
)
746 const glsl_type
*struct_type
= ir
->record
->type
;
748 ir
->record
->accept(this);
750 unsigned int offset
= 0;
751 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
752 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
754 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
756 this->result
.reg_offset
+= offset
;
757 this->result
.type
= brw_type_for_base_type(ir
->type
);
761 fs_visitor::visit(ir_dereference_array
*ir
)
766 ir
->array
->accept(this);
767 index
= ir
->array_index
->as_constant();
769 element_size
= type_size(ir
->type
);
770 this->result
.type
= brw_type_for_base_type(ir
->type
);
773 assert(this->result
.file
== UNIFORM
||
774 (this->result
.file
== GRF
&&
775 this->result
.reg
!= 0));
776 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
778 assert(!"FINISHME: non-constant array element");
782 /* Instruction selection: Produce a MOV.sat instead of
783 * MIN(MAX(val, 0), 1) when possible.
786 fs_visitor::try_emit_saturate(ir_expression
*ir
)
788 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
793 sat_val
->accept(this);
794 fs_reg src
= this->result
;
796 this->result
= fs_reg(this, ir
->type
);
797 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, src
));
798 inst
->saturate
= true;
804 brw_conditional_for_comparison(unsigned int op
)
808 return BRW_CONDITIONAL_L
;
809 case ir_binop_greater
:
810 return BRW_CONDITIONAL_G
;
811 case ir_binop_lequal
:
812 return BRW_CONDITIONAL_LE
;
813 case ir_binop_gequal
:
814 return BRW_CONDITIONAL_GE
;
816 case ir_binop_all_equal
: /* same as equal for scalars */
817 return BRW_CONDITIONAL_Z
;
818 case ir_binop_nequal
:
819 case ir_binop_any_nequal
: /* same as nequal for scalars */
820 return BRW_CONDITIONAL_NZ
;
822 assert(!"not reached: bad operation for comparison");
823 return BRW_CONDITIONAL_NZ
;
828 fs_visitor::visit(ir_expression
*ir
)
830 unsigned int operand
;
834 assert(ir
->get_num_operands() <= 2);
836 if (try_emit_saturate(ir
))
839 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
840 ir
->operands
[operand
]->accept(this);
841 if (this->result
.file
== BAD_FILE
) {
843 printf("Failed to get tree for expression operand:\n");
844 ir
->operands
[operand
]->accept(&v
);
847 op
[operand
] = this->result
;
849 /* Matrix expression operands should have been broken down to vector
850 * operations already.
852 assert(!ir
->operands
[operand
]->type
->is_matrix());
853 /* And then those vector operands should have been broken down to scalar.
855 assert(!ir
->operands
[operand
]->type
->is_vector());
858 /* Storage for our result. If our result goes into an assignment, it will
859 * just get copy-propagated out, so no worries.
861 this->result
= fs_reg(this, ir
->type
);
863 switch (ir
->operation
) {
864 case ir_unop_logic_not
:
865 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
866 * ones complement of the whole register, not just bit 0.
868 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1)));
871 op
[0].negate
= !op
[0].negate
;
872 this->result
= op
[0];
876 op
[0].negate
= false;
877 this->result
= op
[0];
880 temp
= fs_reg(this, ir
->type
);
882 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
884 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
885 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
886 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
887 inst
->predicated
= true;
889 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
890 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
891 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
892 inst
->predicated
= true;
896 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
900 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
903 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
907 assert(!"not reached: should be handled by ir_explog_to_explog2");
910 case ir_unop_sin_reduced
:
911 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
914 case ir_unop_cos_reduced
:
915 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
919 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
922 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
926 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
929 assert(!"not reached: should be handled by ir_sub_to_add_neg");
933 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
936 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
939 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
943 case ir_binop_greater
:
944 case ir_binop_lequal
:
945 case ir_binop_gequal
:
947 case ir_binop_all_equal
:
948 case ir_binop_nequal
:
949 case ir_binop_any_nequal
:
951 /* original gen4 does implicit conversion before comparison. */
953 temp
.type
= op
[0].type
;
955 inst
= emit(fs_inst(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]));
956 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
957 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
960 case ir_binop_logic_xor
:
961 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
964 case ir_binop_logic_or
:
965 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
968 case ir_binop_logic_and
:
969 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
974 assert(!"not reached: should be handled by brw_fs_channel_expressions");
978 assert(!"not reached: should be handled by lower_noise");
981 case ir_quadop_vector
:
982 assert(!"not reached: should be handled by lower_quadop_vector");
986 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
990 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
997 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1001 temp
= this->result
;
1002 /* original gen4 does implicit conversion before comparison. */
1004 temp
.type
= op
[0].type
;
1006 inst
= emit(fs_inst(BRW_OPCODE_CMP
, temp
, op
[0], fs_reg(0.0f
)));
1007 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1008 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
,
1009 this->result
, fs_reg(1)));
1013 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
1016 op
[0].negate
= !op
[0].negate
;
1017 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1018 this->result
.negate
= true;
1021 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1024 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
1026 case ir_unop_round_even
:
1027 emit(fs_inst(BRW_OPCODE_RNDE
, this->result
, op
[0]));
1031 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1032 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1034 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1035 inst
->predicated
= true;
1038 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1039 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1041 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1042 inst
->predicated
= true;
1046 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
1049 case ir_unop_bit_not
:
1050 inst
= emit(fs_inst(BRW_OPCODE_NOT
, this->result
, op
[0]));
1052 case ir_binop_bit_and
:
1053 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
1055 case ir_binop_bit_xor
:
1056 inst
= emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
1058 case ir_binop_bit_or
:
1059 inst
= emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
1063 case ir_binop_lshift
:
1064 case ir_binop_rshift
:
1065 assert(!"GLSL 1.30 features unsupported");
1071 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1072 const glsl_type
*type
, bool predicated
)
1074 switch (type
->base_type
) {
1075 case GLSL_TYPE_FLOAT
:
1076 case GLSL_TYPE_UINT
:
1078 case GLSL_TYPE_BOOL
:
1079 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1080 l
.type
= brw_type_for_base_type(type
);
1081 r
.type
= brw_type_for_base_type(type
);
1083 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1084 inst
->predicated
= predicated
;
1090 case GLSL_TYPE_ARRAY
:
1091 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1092 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1096 case GLSL_TYPE_STRUCT
:
1097 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1098 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1103 case GLSL_TYPE_SAMPLER
:
1107 assert(!"not reached");
1113 fs_visitor::visit(ir_assignment
*ir
)
1118 /* FINISHME: arrays on the lhs */
1119 ir
->lhs
->accept(this);
1122 ir
->rhs
->accept(this);
1125 assert(l
.file
!= BAD_FILE
);
1126 assert(r
.file
!= BAD_FILE
);
1128 if (ir
->condition
) {
1129 emit_bool_to_cond_code(ir
->condition
);
1132 if (ir
->lhs
->type
->is_scalar() ||
1133 ir
->lhs
->type
->is_vector()) {
1134 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1135 if (ir
->write_mask
& (1 << i
)) {
1136 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1138 inst
->predicated
= true;
1144 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1149 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1153 bool simd16
= false;
1159 if (ir
->shadow_comparitor
) {
1160 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1161 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1163 coordinate
.reg_offset
++;
1165 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1168 if (ir
->op
== ir_tex
) {
1169 /* There's no plain shadow compare message, so we use shadow
1170 * compare with a bias of 0.0.
1172 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1175 } else if (ir
->op
== ir_txb
) {
1176 ir
->lod_info
.bias
->accept(this);
1177 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1181 assert(ir
->op
== ir_txl
);
1182 ir
->lod_info
.lod
->accept(this);
1183 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1188 ir
->shadow_comparitor
->accept(this);
1189 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1191 } else if (ir
->op
== ir_tex
) {
1192 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1193 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1195 coordinate
.reg_offset
++;
1197 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1200 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1201 * instructions. We'll need to do SIMD16 here.
1203 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1205 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1206 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2),
1208 coordinate
.reg_offset
++;
1211 /* lod/bias appears after u/v/r. */
1214 if (ir
->op
== ir_txb
) {
1215 ir
->lod_info
.bias
->accept(this);
1216 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1220 ir
->lod_info
.lod
->accept(this);
1221 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1226 /* The unused upper half. */
1229 /* Now, since we're doing simd16, the return is 2 interleaved
1230 * vec4s where the odd-indexed ones are junk. We'll need to move
1231 * this weirdness around to the expected layout.
1235 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1237 dst
.type
= BRW_REGISTER_TYPE_F
;
1240 fs_inst
*inst
= NULL
;
1243 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1246 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1249 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1253 assert(!"GLSL 1.30 features unsupported");
1256 inst
->base_mrf
= base_mrf
;
1260 for (int i
= 0; i
< 4; i
++) {
1261 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1262 orig_dst
.reg_offset
++;
1263 dst
.reg_offset
+= 2;
1271 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1273 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1274 * optional parameters like shadow comparitor or LOD bias. If
1275 * optional parameters aren't present, those base slots are
1276 * optional and don't need to be included in the message.
1278 * We don't fill in the unnecessary slots regardless, which may
1279 * look surprising in the disassembly.
1281 int mlen
= 1; /* g0 header always present. */
1284 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1285 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1287 coordinate
.reg_offset
++;
1289 mlen
+= ir
->coordinate
->type
->vector_elements
;
1291 if (ir
->shadow_comparitor
) {
1292 mlen
= MAX2(mlen
, 5);
1294 ir
->shadow_comparitor
->accept(this);
1295 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1299 fs_inst
*inst
= NULL
;
1302 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1305 ir
->lod_info
.bias
->accept(this);
1306 mlen
= MAX2(mlen
, 5);
1307 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1310 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1313 ir
->lod_info
.lod
->accept(this);
1314 mlen
= MAX2(mlen
, 5);
1315 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1318 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1322 assert(!"GLSL 1.30 features unsupported");
1325 inst
->base_mrf
= base_mrf
;
1332 fs_visitor::visit(ir_texture
*ir
)
1335 fs_inst
*inst
= NULL
;
1337 ir
->coordinate
->accept(this);
1338 fs_reg coordinate
= this->result
;
1340 /* Should be lowered by do_lower_texture_projection */
1341 assert(!ir
->projector
);
1343 sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
1344 ctx
->Shader
.CurrentFragmentProgram
,
1345 &brw
->fragment_program
->Base
);
1346 sampler
= c
->fp
->program
.Base
.SamplerUnits
[sampler
];
1348 /* The 965 requires the EU to do the normalization of GL rectangle
1349 * texture coordinates. We use the program parameter state
1350 * tracking to get the scaling factor.
1352 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1353 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1354 int tokens
[STATE_LENGTH
] = {
1356 STATE_TEXRECT_SCALE
,
1362 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
1364 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
+ 1] =
1367 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1368 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1369 GLuint index
= _mesa_add_state_reference(params
,
1370 (gl_state_index
*)tokens
);
1372 this->param_index
[c
->prog_data
.nr_params
] = index
;
1373 this->param_offset
[c
->prog_data
.nr_params
] = 0;
1374 c
->prog_data
.nr_params
++;
1375 this->param_index
[c
->prog_data
.nr_params
] = index
;
1376 this->param_offset
[c
->prog_data
.nr_params
] = 1;
1377 c
->prog_data
.nr_params
++;
1379 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1380 fs_reg src
= coordinate
;
1383 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_x
));
1386 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_y
));
1389 /* Writemasking doesn't eliminate channels on SIMD8 texture
1390 * samples, so don't worry about them.
1392 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1394 if (intel
->gen
< 5) {
1395 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1397 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1400 inst
->sampler
= sampler
;
1404 if (ir
->shadow_comparitor
)
1405 inst
->shadow_compare
= true;
1407 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1408 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1410 for (int i
= 0; i
< 4; i
++) {
1411 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1412 fs_reg l
= swizzle_dst
;
1415 if (swiz
== SWIZZLE_ZERO
) {
1416 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1417 } else if (swiz
== SWIZZLE_ONE
) {
1418 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1421 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1422 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1425 this->result
= swizzle_dst
;
1430 fs_visitor::visit(ir_swizzle
*ir
)
1432 ir
->val
->accept(this);
1433 fs_reg val
= this->result
;
1435 if (ir
->type
->vector_elements
== 1) {
1436 this->result
.reg_offset
+= ir
->mask
.x
;
1440 fs_reg result
= fs_reg(this, ir
->type
);
1441 this->result
= result
;
1443 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1444 fs_reg channel
= val
;
1462 channel
.reg_offset
+= swiz
;
1463 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1464 result
.reg_offset
++;
1469 fs_visitor::visit(ir_discard
*ir
)
1471 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1473 assert(ir
->condition
== NULL
); /* FINISHME */
1475 emit(fs_inst(FS_OPCODE_DISCARD_NOT
, temp
, reg_null_d
));
1476 emit(fs_inst(FS_OPCODE_DISCARD_AND
, reg_null_d
, temp
));
1477 kill_emitted
= true;
1481 fs_visitor::visit(ir_constant
*ir
)
1483 /* Set this->result to reg at the bottom of the function because some code
1484 * paths will cause this visitor to be applied to other fields. This will
1485 * cause the value stored in this->result to be modified.
1487 * Make reg constant so that it doesn't get accidentally modified along the
1488 * way. Yes, I actually had this problem. :(
1490 const fs_reg
reg(this, ir
->type
);
1491 fs_reg dst_reg
= reg
;
1493 if (ir
->type
->is_array()) {
1494 const unsigned size
= type_size(ir
->type
->fields
.array
);
1496 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1497 ir
->array_elements
[i
]->accept(this);
1498 fs_reg src_reg
= this->result
;
1500 dst_reg
.type
= src_reg
.type
;
1501 for (unsigned j
= 0; j
< size
; j
++) {
1502 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, src_reg
));
1503 src_reg
.reg_offset
++;
1504 dst_reg
.reg_offset
++;
1507 } else if (ir
->type
->is_record()) {
1508 foreach_list(node
, &ir
->components
) {
1509 ir_instruction
*const field
= (ir_instruction
*) node
;
1510 const unsigned size
= type_size(field
->type
);
1512 field
->accept(this);
1513 fs_reg src_reg
= this->result
;
1515 dst_reg
.type
= src_reg
.type
;
1516 for (unsigned j
= 0; j
< size
; j
++) {
1517 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, src_reg
));
1518 src_reg
.reg_offset
++;
1519 dst_reg
.reg_offset
++;
1523 const unsigned size
= type_size(ir
->type
);
1525 for (unsigned i
= 0; i
< size
; i
++) {
1526 switch (ir
->type
->base_type
) {
1527 case GLSL_TYPE_FLOAT
:
1528 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.f
[i
])));
1530 case GLSL_TYPE_UINT
:
1531 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.u
[i
])));
1534 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.i
[i
])));
1536 case GLSL_TYPE_BOOL
:
1537 emit(fs_inst(BRW_OPCODE_MOV
, dst_reg
, fs_reg((int)ir
->value
.b
[i
])));
1540 assert(!"Non-float/uint/int/bool constant");
1542 dst_reg
.reg_offset
++;
1550 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1552 ir_expression
*expr
= ir
->as_expression();
1558 assert(expr
->get_num_operands() <= 2);
1559 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1560 assert(expr
->operands
[i
]->type
->is_scalar());
1562 expr
->operands
[i
]->accept(this);
1563 op
[i
] = this->result
;
1566 switch (expr
->operation
) {
1567 case ir_unop_logic_not
:
1568 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1)));
1569 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1572 case ir_binop_logic_xor
:
1573 inst
= emit(fs_inst(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]));
1574 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1577 case ir_binop_logic_or
:
1578 inst
= emit(fs_inst(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]));
1579 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1582 case ir_binop_logic_and
:
1583 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]));
1584 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1588 if (intel
->gen
>= 6) {
1589 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1590 op
[0], fs_reg(0.0f
)));
1592 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_f
, op
[0]));
1594 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1598 if (intel
->gen
>= 6) {
1599 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0)));
1601 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1603 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1606 case ir_binop_greater
:
1607 case ir_binop_gequal
:
1609 case ir_binop_lequal
:
1610 case ir_binop_equal
:
1611 case ir_binop_all_equal
:
1612 case ir_binop_nequal
:
1613 case ir_binop_any_nequal
:
1614 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_cmp
, op
[0], op
[1]));
1615 inst
->conditional_mod
=
1616 brw_conditional_for_comparison(expr
->operation
);
1620 assert(!"not reached");
1629 if (intel
->gen
>= 6) {
1630 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
,
1631 this->result
, fs_reg(1)));
1632 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1634 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, this->result
));
1635 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1640 * Emit a gen6 IF statement with the comparison folded into the IF
1644 fs_visitor::emit_if_gen6(ir_if
*ir
)
1646 ir_expression
*expr
= ir
->condition
->as_expression();
1653 assert(expr
->get_num_operands() <= 2);
1654 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1655 assert(expr
->operands
[i
]->type
->is_scalar());
1657 expr
->operands
[i
]->accept(this);
1658 op
[i
] = this->result
;
1661 switch (expr
->operation
) {
1662 case ir_unop_logic_not
:
1663 inst
= emit(fs_inst(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(0)));
1664 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1667 case ir_binop_logic_xor
:
1668 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1669 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1672 case ir_binop_logic_or
:
1673 temp
= fs_reg(this, glsl_type::bool_type
);
1674 emit(fs_inst(BRW_OPCODE_OR
, temp
, op
[0], op
[1]));
1675 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1676 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1679 case ir_binop_logic_and
:
1680 temp
= fs_reg(this, glsl_type::bool_type
);
1681 emit(fs_inst(BRW_OPCODE_AND
, temp
, op
[0], op
[1]));
1682 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1683 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1687 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0)));
1688 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1692 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1693 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1696 case ir_binop_greater
:
1697 case ir_binop_gequal
:
1699 case ir_binop_lequal
:
1700 case ir_binop_equal
:
1701 case ir_binop_all_equal
:
1702 case ir_binop_nequal
:
1703 case ir_binop_any_nequal
:
1704 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1705 inst
->conditional_mod
=
1706 brw_conditional_for_comparison(expr
->operation
);
1709 assert(!"not reached");
1710 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1711 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1718 ir
->condition
->accept(this);
1720 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0)));
1721 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1725 fs_visitor::visit(ir_if
*ir
)
1729 /* Don't point the annotation at the if statement, because then it plus
1730 * the then and else blocks get printed.
1732 this->base_ir
= ir
->condition
;
1734 if (intel
->gen
>= 6) {
1737 emit_bool_to_cond_code(ir
->condition
);
1739 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1740 inst
->predicated
= true;
1743 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1744 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1750 if (!ir
->else_instructions
.is_empty()) {
1751 emit(fs_inst(BRW_OPCODE_ELSE
));
1753 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1754 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1761 emit(fs_inst(BRW_OPCODE_ENDIF
));
1765 fs_visitor::visit(ir_loop
*ir
)
1767 fs_reg counter
= reg_undef
;
1770 this->base_ir
= ir
->counter
;
1771 ir
->counter
->accept(this);
1772 counter
= *(variable_storage(ir
->counter
));
1775 this->base_ir
= ir
->from
;
1776 ir
->from
->accept(this);
1778 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1782 emit(fs_inst(BRW_OPCODE_DO
));
1785 this->base_ir
= ir
->to
;
1786 ir
->to
->accept(this);
1788 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_cmp
,
1789 counter
, this->result
));
1790 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->cmp
);
1792 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1793 inst
->predicated
= true;
1796 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1797 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1803 if (ir
->increment
) {
1804 this->base_ir
= ir
->increment
;
1805 ir
->increment
->accept(this);
1806 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1809 emit(fs_inst(BRW_OPCODE_WHILE
));
1813 fs_visitor::visit(ir_loop_jump
*ir
)
1816 case ir_loop_jump::jump_break
:
1817 emit(fs_inst(BRW_OPCODE_BREAK
));
1819 case ir_loop_jump::jump_continue
:
1820 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1826 fs_visitor::visit(ir_call
*ir
)
1828 assert(!"FINISHME");
1832 fs_visitor::visit(ir_return
*ir
)
1834 assert(!"FINISHME");
1838 fs_visitor::visit(ir_function
*ir
)
1840 /* Ignore function bodies other than main() -- we shouldn't see calls to
1841 * them since they should all be inlined before we get to ir_to_mesa.
1843 if (strcmp(ir
->name
, "main") == 0) {
1844 const ir_function_signature
*sig
;
1847 sig
= ir
->matching_signature(&empty
);
1851 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1852 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1861 fs_visitor::visit(ir_function_signature
*ir
)
1863 assert(!"not reached");
1868 fs_visitor::emit(fs_inst inst
)
1870 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1873 list_inst
->annotation
= this->current_annotation
;
1874 list_inst
->ir
= this->base_ir
;
1876 this->instructions
.push_tail(list_inst
);
1881 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1883 fs_visitor::emit_dummy_fs()
1885 /* Everyone's favorite color. */
1886 emit(fs_inst(BRW_OPCODE_MOV
,
1889 emit(fs_inst(BRW_OPCODE_MOV
,
1892 emit(fs_inst(BRW_OPCODE_MOV
,
1895 emit(fs_inst(BRW_OPCODE_MOV
,
1900 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1903 write
->base_mrf
= 0;
1906 /* The register location here is relative to the start of the URB
1907 * data. It will get adjusted to be a real location before
1908 * generate_code() time.
1911 fs_visitor::interp_reg(int location
, int channel
)
1913 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1914 int stride
= (channel
& 1) * 4;
1916 assert(urb_setup
[location
] != -1);
1918 return brw_vec1_grf(regnr
, stride
);
1921 /** Emits the interpolation for the varying inputs. */
1923 fs_visitor::emit_interpolation_setup_gen4()
1925 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1927 this->current_annotation
= "compute pixel centers";
1928 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1929 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1930 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1931 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1932 emit(fs_inst(BRW_OPCODE_ADD
,
1934 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1935 fs_reg(brw_imm_v(0x10101010))));
1936 emit(fs_inst(BRW_OPCODE_ADD
,
1938 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1939 fs_reg(brw_imm_v(0x11001100))));
1941 this->current_annotation
= "compute pixel deltas from v0";
1943 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1944 this->delta_y
= this->delta_x
;
1945 this->delta_y
.reg_offset
++;
1947 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1948 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1950 emit(fs_inst(BRW_OPCODE_ADD
,
1953 fs_reg(negate(brw_vec1_grf(1, 0)))));
1954 emit(fs_inst(BRW_OPCODE_ADD
,
1957 fs_reg(negate(brw_vec1_grf(1, 1)))));
1959 this->current_annotation
= "compute pos.w and 1/pos.w";
1960 /* Compute wpos.w. It's always in our setup, since it's needed to
1961 * interpolate the other attributes.
1963 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1964 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1965 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1966 /* Compute the pixel 1/W value from wpos.w. */
1967 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1968 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1969 this->current_annotation
= NULL
;
1972 /** Emits the interpolation for the varying inputs. */
1974 fs_visitor::emit_interpolation_setup_gen6()
1976 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1978 /* If the pixel centers end up used, the setup is the same as for gen4. */
1979 this->current_annotation
= "compute pixel centers";
1980 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1981 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1982 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1983 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1984 emit(fs_inst(BRW_OPCODE_ADD
,
1986 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1987 fs_reg(brw_imm_v(0x10101010))));
1988 emit(fs_inst(BRW_OPCODE_ADD
,
1990 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1991 fs_reg(brw_imm_v(0x11001100))));
1993 /* As of gen6, we can no longer mix float and int sources. We have
1994 * to turn the integer pixel centers into floats for their actual
1997 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1998 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1999 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
));
2000 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
));
2002 this->current_annotation
= "compute 1/pos.w";
2003 this->wpos_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
2004 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
2005 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
2007 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
2008 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
2010 this->current_annotation
= NULL
;
2014 fs_visitor::emit_fb_writes()
2016 this->current_annotation
= "FB write header";
2017 GLboolean header_present
= GL_TRUE
;
2020 if (intel
->gen
>= 6 &&
2021 !this->kill_emitted
&&
2022 c
->key
.nr_color_regions
== 1) {
2023 header_present
= false;
2026 if (header_present
) {
2031 if (c
->aa_dest_stencil_reg
) {
2032 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2033 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0))));
2036 /* Reserve space for color. It'll be filled in per MRT below. */
2040 if (c
->source_depth_to_render_target
) {
2041 if (c
->computes_depth
) {
2042 /* Hand over gl_FragDepth. */
2043 assert(this->frag_depth
);
2044 fs_reg depth
= *(variable_storage(this->frag_depth
));
2046 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
2048 /* Pass through the payload depth. */
2049 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2050 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0))));
2054 if (c
->dest_depth_reg
) {
2055 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2056 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0))));
2059 fs_reg color
= reg_undef
;
2060 if (this->frag_color
)
2061 color
= *(variable_storage(this->frag_color
));
2062 else if (this->frag_data
) {
2063 color
= *(variable_storage(this->frag_data
));
2064 color
.type
= BRW_REGISTER_TYPE_F
;
2067 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2068 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
2069 "FB write target %d",
2071 if (this->frag_color
|| this->frag_data
) {
2072 for (int i
= 0; i
< 4; i
++) {
2073 emit(fs_inst(BRW_OPCODE_MOV
,
2074 fs_reg(MRF
, color_mrf
+ i
),
2080 if (this->frag_color
)
2081 color
.reg_offset
-= 4;
2083 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
2084 reg_undef
, reg_undef
));
2085 inst
->target
= target
;
2088 if (target
== c
->key
.nr_color_regions
- 1)
2090 inst
->header_present
= header_present
;
2093 if (c
->key
.nr_color_regions
== 0) {
2094 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
2095 reg_undef
, reg_undef
));
2099 inst
->header_present
= header_present
;
2102 this->current_annotation
= NULL
;
2106 fs_visitor::generate_fb_write(fs_inst
*inst
)
2108 GLboolean eot
= inst
->eot
;
2109 struct brw_reg implied_header
;
2111 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
2114 brw_push_insn_state(p
);
2115 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2116 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2118 if (inst
->header_present
) {
2119 if (intel
->gen
>= 6) {
2121 brw_message_reg(inst
->base_mrf
),
2122 brw_vec8_grf(0, 0));
2124 if (inst
->target
> 0) {
2125 /* Set the render target index for choosing BLEND_STATE. */
2126 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 2),
2127 BRW_REGISTER_TYPE_UD
),
2128 brw_imm_ud(inst
->target
));
2131 /* Clear viewport index, render target array index. */
2132 brw_AND(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 0),
2133 BRW_REGISTER_TYPE_UD
),
2134 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2135 brw_imm_ud(0xf7ff));
2137 implied_header
= brw_null_reg();
2139 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2143 brw_message_reg(inst
->base_mrf
+ 1),
2144 brw_vec8_grf(1, 0));
2146 implied_header
= brw_null_reg();
2149 brw_pop_insn_state(p
);
2152 8, /* dispatch_width */
2153 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
2160 inst
->header_present
);
2164 fs_visitor::generate_linterp(fs_inst
*inst
,
2165 struct brw_reg dst
, struct brw_reg
*src
)
2167 struct brw_reg delta_x
= src
[0];
2168 struct brw_reg delta_y
= src
[1];
2169 struct brw_reg interp
= src
[2];
2172 delta_y
.nr
== delta_x
.nr
+ 1 &&
2173 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2174 brw_PLN(p
, dst
, interp
, delta_x
);
2176 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2177 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2182 fs_visitor::generate_math(fs_inst
*inst
,
2183 struct brw_reg dst
, struct brw_reg
*src
)
2187 switch (inst
->opcode
) {
2189 op
= BRW_MATH_FUNCTION_INV
;
2192 op
= BRW_MATH_FUNCTION_RSQ
;
2194 case FS_OPCODE_SQRT
:
2195 op
= BRW_MATH_FUNCTION_SQRT
;
2197 case FS_OPCODE_EXP2
:
2198 op
= BRW_MATH_FUNCTION_EXP
;
2200 case FS_OPCODE_LOG2
:
2201 op
= BRW_MATH_FUNCTION_LOG
;
2204 op
= BRW_MATH_FUNCTION_POW
;
2207 op
= BRW_MATH_FUNCTION_SIN
;
2210 op
= BRW_MATH_FUNCTION_COS
;
2213 assert(!"not reached: unknown math function");
2218 if (intel
->gen
>= 6) {
2219 assert(inst
->mlen
== 0);
2221 if (inst
->opcode
== FS_OPCODE_POW
) {
2222 brw_math2(p
, dst
, op
, src
[0], src
[1]);
2226 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2227 BRW_MATH_SATURATE_NONE
,
2229 BRW_MATH_DATA_VECTOR
,
2230 BRW_MATH_PRECISION_FULL
);
2233 assert(inst
->mlen
>= 1);
2237 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2238 BRW_MATH_SATURATE_NONE
,
2239 inst
->base_mrf
, src
[0],
2240 BRW_MATH_DATA_VECTOR
,
2241 BRW_MATH_PRECISION_FULL
);
2246 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
)
2250 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2252 if (intel
->gen
>= 5) {
2253 switch (inst
->opcode
) {
2255 if (inst
->shadow_compare
) {
2256 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2258 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2262 if (inst
->shadow_compare
) {
2263 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2265 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2270 switch (inst
->opcode
) {
2272 /* Note that G45 and older determines shadow compare and dispatch width
2273 * from message length for most messages.
2275 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2276 if (inst
->shadow_compare
) {
2277 assert(inst
->mlen
== 6);
2279 assert(inst
->mlen
<= 4);
2283 if (inst
->shadow_compare
) {
2284 assert(inst
->mlen
== 6);
2285 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2287 assert(inst
->mlen
== 9);
2288 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2289 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2294 assert(msg_type
!= -1);
2296 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2302 retype(dst
, BRW_REGISTER_TYPE_UW
),
2304 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2305 SURF_INDEX_TEXTURE(inst
->sampler
),
2317 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2320 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2322 * and we're trying to produce:
2325 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2326 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2327 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2328 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2329 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2330 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2331 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2332 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2334 * and add another set of two more subspans if in 16-pixel dispatch mode.
2336 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2337 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2338 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2339 * between each other. We could probably do it like ddx and swizzle the right
2340 * order later, but bail for now and just produce
2341 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2344 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2346 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2347 BRW_REGISTER_TYPE_F
,
2348 BRW_VERTICAL_STRIDE_2
,
2350 BRW_HORIZONTAL_STRIDE_0
,
2351 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2352 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2353 BRW_REGISTER_TYPE_F
,
2354 BRW_VERTICAL_STRIDE_2
,
2356 BRW_HORIZONTAL_STRIDE_0
,
2357 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2358 brw_ADD(p
, dst
, src0
, negate(src1
));
2362 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2364 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2365 BRW_REGISTER_TYPE_F
,
2366 BRW_VERTICAL_STRIDE_4
,
2368 BRW_HORIZONTAL_STRIDE_0
,
2369 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2370 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2371 BRW_REGISTER_TYPE_F
,
2372 BRW_VERTICAL_STRIDE_4
,
2374 BRW_HORIZONTAL_STRIDE_0
,
2375 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2376 brw_ADD(p
, dst
, src0
, negate(src1
));
2380 fs_visitor::generate_discard_not(fs_inst
*inst
, struct brw_reg mask
)
2382 if (intel
->gen
>= 6) {
2383 /* Gen6 no longer has the mask reg for us to just read the
2384 * active channels from. However, cmp updates just the channels
2385 * of the flag reg that are enabled, so we can get at the
2386 * channel enables that way. In this step, make a reg of ones
2389 brw_MOV(p
, mask
, brw_imm_ud(1));
2391 brw_push_insn_state(p
);
2392 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2393 brw_NOT(p
, mask
, brw_mask_reg(1)); /* IMASK */
2394 brw_pop_insn_state(p
);
2399 fs_visitor::generate_discard_and(fs_inst
*inst
, struct brw_reg mask
)
2401 if (intel
->gen
>= 6) {
2402 struct brw_reg f0
= brw_flag_reg();
2403 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
2405 brw_push_insn_state(p
);
2406 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2407 brw_MOV(p
, f0
, brw_imm_uw(0xffff)); /* inactive channels undiscarded */
2408 brw_pop_insn_state(p
);
2410 brw_CMP(p
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
2411 BRW_CONDITIONAL_Z
, mask
, brw_imm_ud(0)); /* active channels fail test */
2412 /* Undo CMP's whacking of predication*/
2413 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2415 brw_push_insn_state(p
);
2416 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2417 brw_AND(p
, g1
, f0
, g1
);
2418 brw_pop_insn_state(p
);
2420 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2422 mask
= brw_uw1_reg(mask
.file
, mask
.nr
, 0);
2424 brw_push_insn_state(p
);
2425 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2426 brw_AND(p
, g0
, mask
, g0
);
2427 brw_pop_insn_state(p
);
2432 fs_visitor::generate_spill(fs_inst
*inst
, struct brw_reg src
)
2434 assert(inst
->mlen
!= 0);
2437 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
2438 retype(src
, BRW_REGISTER_TYPE_UD
));
2439 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
), 1,
2444 fs_visitor::generate_unspill(fs_inst
*inst
, struct brw_reg dst
)
2446 assert(inst
->mlen
!= 0);
2448 /* Clear any post destination dependencies that would be ignored by
2449 * the block read. See the B-Spec for pre-gen5 send instruction.
2451 * This could use a better solution, since texture sampling and
2452 * math reads could potentially run into it as well -- anywhere
2453 * that we have a SEND with a destination that is a register that
2454 * was written but not read within the last N instructions (what's
2455 * N? unsure). This is rare because of dead code elimination, but
2458 if (intel
->gen
== 4 && !intel
->is_g4x
)
2459 brw_MOV(p
, brw_null_reg(), dst
);
2461 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
), 1,
2464 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2465 /* gen4 errata: destination from a send can't be used as a
2466 * destination until it's been read. Just read it so we don't
2469 brw_MOV(p
, brw_null_reg(), dst
);
2475 fs_visitor::generate_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
)
2477 assert(inst
->mlen
!= 0);
2479 /* Clear any post destination dependencies that would be ignored by
2480 * the block read. See the B-Spec for pre-gen5 send instruction.
2482 * This could use a better solution, since texture sampling and
2483 * math reads could potentially run into it as well -- anywhere
2484 * that we have a SEND with a destination that is a register that
2485 * was written but not read within the last N instructions (what's
2486 * N? unsure). This is rare because of dead code elimination, but
2489 if (intel
->gen
== 4 && !intel
->is_g4x
)
2490 brw_MOV(p
, brw_null_reg(), dst
);
2492 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
2493 inst
->offset
, SURF_INDEX_FRAG_CONST_BUFFER
);
2495 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2496 /* gen4 errata: destination from a send can't be used as a
2497 * destination until it's been read. Just read it so we don't
2500 brw_MOV(p
, brw_null_reg(), dst
);
2505 * To be called after the last _mesa_add_state_reference() call, to
2506 * set up prog_data.param[] for assign_curb_setup() and
2507 * setup_pull_constants().
2510 fs_visitor::setup_paramvalues_refs()
2512 /* Set up the pointers to ParamValues now that that array is finalized. */
2513 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
2514 c
->prog_data
.param
[i
] =
2515 fp
->Base
.Parameters
->ParameterValues
[this->param_index
[i
]] +
2516 this->param_offset
[i
];
2521 fs_visitor::assign_curb_setup()
2523 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
2524 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2526 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2527 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2528 fs_inst
*inst
= (fs_inst
*)iter
.get();
2530 for (unsigned int i
= 0; i
< 3; i
++) {
2531 if (inst
->src
[i
].file
== UNIFORM
) {
2532 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2533 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2537 inst
->src
[i
].file
= FIXED_HW_REG
;
2538 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
2545 fs_visitor::calculate_urb_setup()
2547 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2552 /* Figure out where each of the incoming setup attributes lands. */
2553 if (intel
->gen
>= 6) {
2554 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2555 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2556 urb_setup
[i
] = urb_next
++;
2560 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2561 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2562 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2565 if (i
>= VERT_RESULT_VAR0
)
2566 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2567 else if (i
<= VERT_RESULT_TEX7
)
2573 urb_setup
[fp_index
] = urb_next
++;
2578 /* Each attribute is 4 setup channels, each of which is half a reg. */
2579 c
->prog_data
.urb_read_length
= urb_next
* 2;
2583 fs_visitor::assign_urb_setup()
2585 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2587 /* Offset all the urb_setup[] index by the actual position of the
2588 * setup regs, now that the location of the constants has been chosen.
2590 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2591 fs_inst
*inst
= (fs_inst
*)iter
.get();
2593 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
2594 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2595 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2598 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
2599 assert(inst
->src
[0].file
== FIXED_HW_REG
);
2600 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
2604 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2608 * Split large virtual GRFs into separate components if we can.
2610 * This is mostly duplicated with what brw_fs_vector_splitting does,
2611 * but that's really conservative because it's afraid of doing
2612 * splitting that doesn't result in real progress after the rest of
2613 * the optimization phases, which would cause infinite looping in
2614 * optimization. We can do it once here, safely. This also has the
2615 * opportunity to split interpolated values, or maybe even uniforms,
2616 * which we don't have at the IR level.
2618 * We want to split, because virtual GRFs are what we register
2619 * allocate and spill (due to contiguousness requirements for some
2620 * instructions), and they're what we naturally generate in the
2621 * codegen process, but most virtual GRFs don't actually need to be
2622 * contiguous sets of GRFs. If we split, we'll end up with reduced
2623 * live intervals and better dead code elimination and coalescing.
2626 fs_visitor::split_virtual_grfs()
2628 int num_vars
= this->virtual_grf_next
;
2629 bool split_grf
[num_vars
];
2630 int new_virtual_grf
[num_vars
];
2632 /* Try to split anything > 0 sized. */
2633 for (int i
= 0; i
< num_vars
; i
++) {
2634 if (this->virtual_grf_sizes
[i
] != 1)
2635 split_grf
[i
] = true;
2637 split_grf
[i
] = false;
2641 /* PLN opcodes rely on the delta_xy being contiguous. */
2642 split_grf
[this->delta_x
.reg
] = false;
2645 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2646 fs_inst
*inst
= (fs_inst
*)iter
.get();
2648 /* Texturing produces 4 contiguous registers, so no splitting. */
2649 if (inst
->is_tex()) {
2650 split_grf
[inst
->dst
.reg
] = false;
2654 /* Allocate new space for split regs. Note that the virtual
2655 * numbers will be contiguous.
2657 for (int i
= 0; i
< num_vars
; i
++) {
2659 new_virtual_grf
[i
] = virtual_grf_alloc(1);
2660 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
2661 int reg
= virtual_grf_alloc(1);
2662 assert(reg
== new_virtual_grf
[i
] + j
- 1);
2665 this->virtual_grf_sizes
[i
] = 1;
2669 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2670 fs_inst
*inst
= (fs_inst
*)iter
.get();
2672 if (inst
->dst
.file
== GRF
&&
2673 split_grf
[inst
->dst
.reg
] &&
2674 inst
->dst
.reg_offset
!= 0) {
2675 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
2676 inst
->dst
.reg_offset
- 1);
2677 inst
->dst
.reg_offset
= 0;
2679 for (int i
= 0; i
< 3; i
++) {
2680 if (inst
->src
[i
].file
== GRF
&&
2681 split_grf
[inst
->src
[i
].reg
] &&
2682 inst
->src
[i
].reg_offset
!= 0) {
2683 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
2684 inst
->src
[i
].reg_offset
- 1);
2685 inst
->src
[i
].reg_offset
= 0;
2689 this->live_intervals_valid
= false;
2693 * Choose accesses from the UNIFORM file to demote to using the pull
2696 * We allow a fragment shader to have more than the specified minimum
2697 * maximum number of fragment shader uniform components (64). If
2698 * there are too many of these, they'd fill up all of register space.
2699 * So, this will push some of them out to the pull constant buffer and
2700 * update the program to load them.
2703 fs_visitor::setup_pull_constants()
2705 /* Only allow 16 registers (128 uniform components) as push constants. */
2706 unsigned int max_uniform_components
= 16 * 8;
2707 if (c
->prog_data
.nr_params
<= max_uniform_components
)
2710 /* Just demote the end of the list. We could probably do better
2711 * here, demoting things that are rarely used in the program first.
2713 int pull_uniform_base
= max_uniform_components
;
2714 int pull_uniform_count
= c
->prog_data
.nr_params
- pull_uniform_base
;
2716 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2717 fs_inst
*inst
= (fs_inst
*)iter
.get();
2719 for (int i
= 0; i
< 3; i
++) {
2720 if (inst
->src
[i
].file
!= UNIFORM
)
2723 int uniform_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2724 if (uniform_nr
< pull_uniform_base
)
2727 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
2728 fs_inst
*pull
= new(mem_ctx
) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
2730 pull
->offset
= ((uniform_nr
- pull_uniform_base
) * 4) & ~15;
2731 pull
->ir
= inst
->ir
;
2732 pull
->annotation
= inst
->annotation
;
2733 pull
->base_mrf
= 14;
2736 inst
->insert_before(pull
);
2738 inst
->src
[i
].file
= GRF
;
2739 inst
->src
[i
].reg
= dst
.reg
;
2740 inst
->src
[i
].reg_offset
= 0;
2741 inst
->src
[i
].smear
= (uniform_nr
- pull_uniform_base
) & 3;
2745 for (int i
= 0; i
< pull_uniform_count
; i
++) {
2746 c
->prog_data
.pull_param
[i
] = c
->prog_data
.param
[pull_uniform_base
+ i
];
2747 c
->prog_data
.pull_param_convert
[i
] =
2748 c
->prog_data
.param_convert
[pull_uniform_base
+ i
];
2750 c
->prog_data
.nr_params
-= pull_uniform_count
;
2751 c
->prog_data
.nr_pull_params
= pull_uniform_count
;
2755 fs_visitor::calculate_live_intervals()
2757 int num_vars
= this->virtual_grf_next
;
2758 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2759 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2762 int bb_header_ip
= 0;
2764 if (this->live_intervals_valid
)
2767 for (int i
= 0; i
< num_vars
; i
++) {
2768 def
[i
] = MAX_INSTRUCTION
;
2773 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2774 fs_inst
*inst
= (fs_inst
*)iter
.get();
2776 if (inst
->opcode
== BRW_OPCODE_DO
) {
2777 if (loop_depth
++ == 0)
2779 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2782 if (loop_depth
== 0) {
2783 /* Patches up the use of vars marked for being live across
2786 for (int i
= 0; i
< num_vars
; i
++) {
2787 if (use
[i
] == loop_start
) {
2793 for (unsigned int i
= 0; i
< 3; i
++) {
2794 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2795 int reg
= inst
->src
[i
].reg
;
2797 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2798 def
[reg
] >= bb_header_ip
)) {
2801 def
[reg
] = MIN2(loop_start
, def
[reg
]);
2802 use
[reg
] = loop_start
;
2804 /* Nobody else is going to go smash our start to
2805 * later in the loop now, because def[reg] now
2806 * points before the bb header.
2811 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2812 int reg
= inst
->dst
.reg
;
2814 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2815 !inst
->predicated
)) {
2816 def
[reg
] = MIN2(def
[reg
], ip
);
2818 def
[reg
] = MIN2(def
[reg
], loop_start
);
2825 /* Set the basic block header IP. This is used for determining
2826 * if a complete def of single-register virtual GRF in a loop
2827 * dominates a use in the same basic block. It's a quick way to
2828 * reduce the live interval range of most register used in a
2831 if (inst
->opcode
== BRW_OPCODE_IF
||
2832 inst
->opcode
== BRW_OPCODE_ELSE
||
2833 inst
->opcode
== BRW_OPCODE_ENDIF
||
2834 inst
->opcode
== BRW_OPCODE_DO
||
2835 inst
->opcode
== BRW_OPCODE_WHILE
||
2836 inst
->opcode
== BRW_OPCODE_BREAK
||
2837 inst
->opcode
== BRW_OPCODE_CONTINUE
) {
2842 talloc_free(this->virtual_grf_def
);
2843 talloc_free(this->virtual_grf_use
);
2844 this->virtual_grf_def
= def
;
2845 this->virtual_grf_use
= use
;
2847 this->live_intervals_valid
= true;
2851 * Attempts to move immediate constants into the immediate
2852 * constant slot of following instructions.
2854 * Immediate constants are a bit tricky -- they have to be in the last
2855 * operand slot, you can't do abs/negate on them,
2859 fs_visitor::propagate_constants()
2861 bool progress
= false;
2863 calculate_live_intervals();
2865 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2866 fs_inst
*inst
= (fs_inst
*)iter
.get();
2868 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2870 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2871 inst
->dst
.type
!= inst
->src
[0].type
)
2874 /* Don't bother with cases where we should have had the
2875 * operation on the constant folded in GLSL already.
2880 /* Found a move of a constant to a GRF. Find anything else using the GRF
2881 * before it's written, and replace it with the constant if we can.
2883 exec_list_iterator scan_iter
= iter
;
2885 for (; scan_iter
.has_next(); scan_iter
.next()) {
2886 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2888 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2889 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2890 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2891 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2895 for (int i
= 2; i
>= 0; i
--) {
2896 if (scan_inst
->src
[i
].file
!= GRF
||
2897 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2898 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2901 /* Don't bother with cases where we should have had the
2902 * operation on the constant folded in GLSL already.
2904 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2907 switch (scan_inst
->opcode
) {
2908 case BRW_OPCODE_MOV
:
2909 scan_inst
->src
[i
] = inst
->src
[0];
2913 case BRW_OPCODE_MUL
:
2914 case BRW_OPCODE_ADD
:
2916 scan_inst
->src
[i
] = inst
->src
[0];
2918 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2919 /* Fit this constant in by commuting the operands */
2920 scan_inst
->src
[0] = scan_inst
->src
[1];
2921 scan_inst
->src
[1] = inst
->src
[0];
2925 case BRW_OPCODE_CMP
:
2926 case BRW_OPCODE_SEL
:
2928 scan_inst
->src
[i
] = inst
->src
[0];
2934 if (scan_inst
->dst
.file
== GRF
&&
2935 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2936 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2937 scan_inst
->is_tex())) {
2944 this->live_intervals_valid
= false;
2949 * Must be called after calculate_live_intervales() to remove unused
2950 * writes to registers -- register allocation will fail otherwise
2951 * because something deffed but not used won't be considered to
2952 * interfere with other regs.
2955 fs_visitor::dead_code_eliminate()
2957 bool progress
= false;
2960 calculate_live_intervals();
2962 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2963 fs_inst
*inst
= (fs_inst
*)iter
.get();
2965 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
2974 live_intervals_valid
= false;
2980 fs_visitor::register_coalesce()
2982 bool progress
= false;
2986 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2987 fs_inst
*inst
= (fs_inst
*)iter
.get();
2989 /* Make sure that we dominate the instructions we're going to
2990 * scan for interfering with our coalescing, or we won't have
2991 * scanned enough to see if anything interferes with our
2992 * coalescing. We don't dominate the following instructions if
2993 * we're in a loop or an if block.
2995 switch (inst
->opcode
) {
2999 case BRW_OPCODE_WHILE
:
3005 case BRW_OPCODE_ENDIF
:
3009 if (loop_depth
|| if_depth
)
3012 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3015 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
3016 inst
->dst
.type
!= inst
->src
[0].type
)
3019 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
3020 * them: check for no writes to either one until the exit of the
3023 bool interfered
= false;
3024 exec_list_iterator scan_iter
= iter
;
3026 for (; scan_iter
.has_next(); scan_iter
.next()) {
3027 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
3029 if (scan_inst
->dst
.file
== GRF
) {
3030 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
3031 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
3032 scan_inst
->is_tex())) {
3036 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
3037 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
3038 scan_inst
->is_tex())) {
3048 /* Rewrite the later usage to point at the source of the move to
3051 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
3053 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
3055 for (int i
= 0; i
< 3; i
++) {
3056 if (scan_inst
->src
[i
].file
== GRF
&&
3057 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
3058 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
3059 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
3060 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
3061 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
3062 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
3063 scan_inst
->src
[i
].smear
= inst
->src
[0].smear
;
3073 live_intervals_valid
= false;
3080 fs_visitor::compute_to_mrf()
3082 bool progress
= false;
3085 calculate_live_intervals();
3087 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3088 fs_inst
*inst
= (fs_inst
*)iter
.get();
3093 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3095 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
3096 inst
->dst
.type
!= inst
->src
[0].type
||
3097 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
3100 /* Can't compute-to-MRF this GRF if someone else was going to
3103 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
3106 /* Found a move of a GRF to a MRF. Let's see if we can go
3107 * rewrite the thing that made this GRF to write into the MRF.
3110 for (scan_inst
= (fs_inst
*)inst
->prev
;
3111 scan_inst
->prev
!= NULL
;
3112 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
3113 if (scan_inst
->dst
.file
== GRF
&&
3114 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
3115 /* Found the last thing to write our reg we want to turn
3116 * into a compute-to-MRF.
3119 if (scan_inst
->is_tex()) {
3120 /* texturing writes several continuous regs, so we can't
3121 * compute-to-mrf that.
3126 /* If it's predicated, it (probably) didn't populate all
3129 if (scan_inst
->predicated
)
3132 /* SEND instructions can't have MRF as a destination. */
3133 if (scan_inst
->mlen
)
3136 if (intel
->gen
>= 6) {
3137 /* gen6 math instructions must have the destination be
3138 * GRF, so no compute-to-MRF for them.
3140 if (scan_inst
->is_math()) {
3145 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
3146 /* Found the creator of our MRF's source value. */
3147 scan_inst
->dst
.file
= MRF
;
3148 scan_inst
->dst
.hw_reg
= inst
->dst
.hw_reg
;
3149 scan_inst
->saturate
|= inst
->saturate
;
3156 /* We don't handle flow control here. Most computation of
3157 * values that end up in MRFs are shortly before the MRF
3160 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
3161 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
3162 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
3163 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
3167 /* You can't read from an MRF, so if someone else reads our
3168 * MRF's source GRF that we wanted to rewrite, that stops us.
3170 bool interfered
= false;
3171 for (int i
= 0; i
< 3; i
++) {
3172 if (scan_inst
->src
[i
].file
== GRF
&&
3173 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
3174 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
3181 if (scan_inst
->dst
.file
== MRF
&&
3182 scan_inst
->dst
.hw_reg
== inst
->dst
.hw_reg
) {
3183 /* Somebody else wrote our MRF here, so we can't can't
3184 * compute-to-MRF before that.
3189 if (scan_inst
->mlen
> 0) {
3190 /* Found a SEND instruction, which means that there are
3191 * live values in MRFs from base_mrf to base_mrf +
3192 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3195 if (inst
->dst
.hw_reg
>= scan_inst
->base_mrf
&&
3196 inst
->dst
.hw_reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
3207 * Walks through basic blocks, locking for repeated MRF writes and
3208 * removing the later ones.
3211 fs_visitor::remove_duplicate_mrf_writes()
3213 fs_inst
*last_mrf_move
[16];
3214 bool progress
= false;
3216 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3218 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3219 fs_inst
*inst
= (fs_inst
*)iter
.get();
3221 switch (inst
->opcode
) {
3223 case BRW_OPCODE_WHILE
:
3225 case BRW_OPCODE_ELSE
:
3226 case BRW_OPCODE_ENDIF
:
3227 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3233 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3234 inst
->dst
.file
== MRF
) {
3235 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.hw_reg
];
3236 if (prev_inst
&& inst
->equals(prev_inst
)) {
3243 /* Clear out the last-write records for MRFs that were overwritten. */
3244 if (inst
->dst
.file
== MRF
) {
3245 last_mrf_move
[inst
->dst
.hw_reg
] = NULL
;
3248 if (inst
->mlen
> 0) {
3249 /* Found a SEND instruction, which will include two or fewer
3250 * implied MRF writes. We could do better here.
3252 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3253 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3257 /* Clear out any MRF move records whose sources got overwritten. */
3258 if (inst
->dst
.file
== GRF
) {
3259 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
3260 if (last_mrf_move
[i
] &&
3261 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
3262 last_mrf_move
[i
] = NULL
;
3267 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3268 inst
->dst
.file
== MRF
&&
3269 inst
->src
[0].file
== GRF
&&
3270 !inst
->predicated
) {
3271 last_mrf_move
[inst
->dst
.hw_reg
] = inst
;
3279 fs_visitor::virtual_grf_interferes(int a
, int b
)
3281 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
3282 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
3284 /* We can't handle dead register writes here, without iterating
3285 * over the whole instruction stream to find every single dead
3286 * write to that register to compare to the live interval of the
3287 * other register. Just assert that dead_code_eliminate() has been
3290 assert((this->virtual_grf_use
[a
] != -1 ||
3291 this->virtual_grf_def
[a
] == MAX_INSTRUCTION
) &&
3292 (this->virtual_grf_use
[b
] != -1 ||
3293 this->virtual_grf_def
[b
] == MAX_INSTRUCTION
));
3298 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
3300 struct brw_reg brw_reg
;
3302 switch (reg
->file
) {
3306 if (reg
->smear
== -1) {
3307 brw_reg
= brw_vec8_reg(reg
->file
,
3310 brw_reg
= brw_vec1_reg(reg
->file
,
3311 reg
->hw_reg
, reg
->smear
);
3313 brw_reg
= retype(brw_reg
, reg
->type
);
3316 switch (reg
->type
) {
3317 case BRW_REGISTER_TYPE_F
:
3318 brw_reg
= brw_imm_f(reg
->imm
.f
);
3320 case BRW_REGISTER_TYPE_D
:
3321 brw_reg
= brw_imm_d(reg
->imm
.i
);
3323 case BRW_REGISTER_TYPE_UD
:
3324 brw_reg
= brw_imm_ud(reg
->imm
.u
);
3327 assert(!"not reached");
3328 brw_reg
= brw_null_reg();
3333 brw_reg
= reg
->fixed_hw_reg
;
3336 /* Probably unused. */
3337 brw_reg
= brw_null_reg();
3340 assert(!"not reached");
3341 brw_reg
= brw_null_reg();
3344 assert(!"not reached");
3345 brw_reg
= brw_null_reg();
3349 brw_reg
= brw_abs(brw_reg
);
3351 brw_reg
= negate(brw_reg
);
3357 fs_visitor::generate_code()
3359 int last_native_inst
= 0;
3360 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
3361 int if_stack_depth
= 0, loop_stack_depth
= 0;
3362 int if_depth_in_loop
[16];
3363 const char *last_annotation_string
= NULL
;
3364 ir_instruction
*last_annotation_ir
= NULL
;
3366 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3367 printf("Native code for fragment shader %d:\n",
3368 ctx
->Shader
.CurrentFragmentProgram
->Name
);
3371 if_depth_in_loop
[loop_stack_depth
] = 0;
3373 memset(&if_stack
, 0, sizeof(if_stack
));
3374 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3375 fs_inst
*inst
= (fs_inst
*)iter
.get();
3376 struct brw_reg src
[3], dst
;
3378 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3379 if (last_annotation_ir
!= inst
->ir
) {
3380 last_annotation_ir
= inst
->ir
;
3381 if (last_annotation_ir
) {
3383 last_annotation_ir
->print();
3387 if (last_annotation_string
!= inst
->annotation
) {
3388 last_annotation_string
= inst
->annotation
;
3389 if (last_annotation_string
)
3390 printf(" %s\n", last_annotation_string
);
3394 for (unsigned int i
= 0; i
< 3; i
++) {
3395 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
3397 dst
= brw_reg_from_fs_reg(&inst
->dst
);
3399 brw_set_conditionalmod(p
, inst
->conditional_mod
);
3400 brw_set_predicate_control(p
, inst
->predicated
);
3401 brw_set_saturate(p
, inst
->saturate
);
3403 switch (inst
->opcode
) {
3404 case BRW_OPCODE_MOV
:
3405 brw_MOV(p
, dst
, src
[0]);
3407 case BRW_OPCODE_ADD
:
3408 brw_ADD(p
, dst
, src
[0], src
[1]);
3410 case BRW_OPCODE_MUL
:
3411 brw_MUL(p
, dst
, src
[0], src
[1]);
3414 case BRW_OPCODE_FRC
:
3415 brw_FRC(p
, dst
, src
[0]);
3417 case BRW_OPCODE_RNDD
:
3418 brw_RNDD(p
, dst
, src
[0]);
3420 case BRW_OPCODE_RNDE
:
3421 brw_RNDE(p
, dst
, src
[0]);
3423 case BRW_OPCODE_RNDZ
:
3424 brw_RNDZ(p
, dst
, src
[0]);
3427 case BRW_OPCODE_AND
:
3428 brw_AND(p
, dst
, src
[0], src
[1]);
3431 brw_OR(p
, dst
, src
[0], src
[1]);
3433 case BRW_OPCODE_XOR
:
3434 brw_XOR(p
, dst
, src
[0], src
[1]);
3436 case BRW_OPCODE_NOT
:
3437 brw_NOT(p
, dst
, src
[0]);
3439 case BRW_OPCODE_ASR
:
3440 brw_ASR(p
, dst
, src
[0], src
[1]);
3442 case BRW_OPCODE_SHR
:
3443 brw_SHR(p
, dst
, src
[0], src
[1]);
3445 case BRW_OPCODE_SHL
:
3446 brw_SHL(p
, dst
, src
[0], src
[1]);
3449 case BRW_OPCODE_CMP
:
3450 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
3452 case BRW_OPCODE_SEL
:
3453 brw_SEL(p
, dst
, src
[0], src
[1]);
3457 assert(if_stack_depth
< 16);
3458 if (inst
->src
[0].file
!= BAD_FILE
) {
3459 assert(intel
->gen
>= 6);
3460 if_stack
[if_stack_depth
] = brw_IF_gen6(p
, inst
->conditional_mod
, src
[0], src
[1]);
3462 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
3464 if_depth_in_loop
[loop_stack_depth
]++;
3468 case BRW_OPCODE_ELSE
:
3469 if_stack
[if_stack_depth
- 1] =
3470 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
3472 case BRW_OPCODE_ENDIF
:
3474 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
3475 if_depth_in_loop
[loop_stack_depth
]--;
3479 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
3480 if_depth_in_loop
[loop_stack_depth
] = 0;
3483 case BRW_OPCODE_BREAK
:
3484 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
3485 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3487 case BRW_OPCODE_CONTINUE
:
3488 /* FINISHME: We need to write the loop instruction support still. */
3489 if (intel
->gen
>= 6)
3490 brw_CONT_gen6(p
, loop_stack
[loop_stack_depth
- 1]);
3492 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
3493 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3496 case BRW_OPCODE_WHILE
: {
3497 struct brw_instruction
*inst0
, *inst1
;
3500 if (intel
->gen
>= 5)
3503 assert(loop_stack_depth
> 0);
3505 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
3506 if (intel
->gen
< 6) {
3507 /* patch all the BREAK/CONT instructions from last BGNLOOP */
3508 while (inst0
> loop_stack
[loop_stack_depth
]) {
3510 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
3511 inst0
->bits3
.if_else
.jump_count
== 0) {
3512 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
3514 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
3515 inst0
->bits3
.if_else
.jump_count
== 0) {
3516 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
3525 case FS_OPCODE_SQRT
:
3526 case FS_OPCODE_EXP2
:
3527 case FS_OPCODE_LOG2
:
3531 generate_math(inst
, dst
, src
);
3533 case FS_OPCODE_CINTERP
:
3534 brw_MOV(p
, dst
, src
[0]);
3536 case FS_OPCODE_LINTERP
:
3537 generate_linterp(inst
, dst
, src
);
3542 generate_tex(inst
, dst
);
3544 case FS_OPCODE_DISCARD_NOT
:
3545 generate_discard_not(inst
, dst
);
3547 case FS_OPCODE_DISCARD_AND
:
3548 generate_discard_and(inst
, src
[0]);
3551 generate_ddx(inst
, dst
, src
[0]);
3554 generate_ddy(inst
, dst
, src
[0]);
3557 case FS_OPCODE_SPILL
:
3558 generate_spill(inst
, src
[0]);
3561 case FS_OPCODE_UNSPILL
:
3562 generate_unspill(inst
, dst
);
3565 case FS_OPCODE_PULL_CONSTANT_LOAD
:
3566 generate_pull_constant_load(inst
, dst
);
3569 case FS_OPCODE_FB_WRITE
:
3570 generate_fb_write(inst
);
3573 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
3574 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
3575 brw_opcodes
[inst
->opcode
].name
);
3577 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
3582 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3583 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
3585 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3586 ((uint32_t *)&p
->store
[i
])[3],
3587 ((uint32_t *)&p
->store
[i
])[2],
3588 ((uint32_t *)&p
->store
[i
])[1],
3589 ((uint32_t *)&p
->store
[i
])[0]);
3591 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3595 last_native_inst
= p
->nr_insn
;
3600 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
3601 * emit issues, it doesn't get the jump distances into the output,
3602 * which is often something we want to debug. So this is here in
3603 * case you're doing that.
3606 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3607 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3608 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3609 ((uint32_t *)&p
->store
[i
])[3],
3610 ((uint32_t *)&p
->store
[i
])[2],
3611 ((uint32_t *)&p
->store
[i
])[1],
3612 ((uint32_t *)&p
->store
[i
])[0]);
3613 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3620 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
3622 struct intel_context
*intel
= &brw
->intel
;
3623 struct gl_context
*ctx
= &intel
->ctx
;
3624 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentFragmentProgram
;
3629 struct brw_shader
*shader
=
3630 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3634 /* We always use 8-wide mode, at least for now. For one, flow
3635 * control only works in 8-wide. Also, when we're fragment shader
3636 * bound, we're almost always under register pressure as well, so
3637 * 8-wide would save us from the performance cliff of spilling
3640 c
->dispatch_width
= 8;
3642 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3643 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3644 _mesa_print_ir(shader
->ir
, NULL
);
3648 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3650 fs_visitor
v(c
, shader
);
3655 v
.calculate_urb_setup();
3657 v
.emit_interpolation_setup_gen4();
3659 v
.emit_interpolation_setup_gen6();
3661 /* Generate FS IR for main(). (the visitor only descends into
3662 * functions called "main").
3664 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3665 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3672 v
.split_virtual_grfs();
3674 v
.setup_paramvalues_refs();
3675 v
.setup_pull_constants();
3681 progress
= v
.remove_duplicate_mrf_writes() || progress
;
3683 progress
= v
.propagate_constants() || progress
;
3684 progress
= v
.register_coalesce() || progress
;
3685 progress
= v
.compute_to_mrf() || progress
;
3686 progress
= v
.dead_code_eliminate() || progress
;
3689 v
.schedule_instructions();
3691 v
.assign_curb_setup();
3692 v
.assign_urb_setup();
3695 /* Debug of register spilling: Go spill everything. */
3696 int virtual_grf_count
= v
.virtual_grf_next
;
3697 for (int i
= 1; i
< virtual_grf_count
; i
++) {
3703 v
.assign_regs_trivial();
3705 while (!v
.assign_regs()) {
3715 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3720 c
->prog_data
.total_grf
= v
.grf_used
;