2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "brw_vec4_gs_visitor.h"
48 #include "brw_dead_control_flow.h"
49 #include "main/uniforms.h"
50 #include "brw_fs_live_variables.h"
51 #include "glsl/nir/glsl_types.h"
52 #include "program/sampler.h"
57 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
58 const fs_reg
*src
, unsigned sources
)
60 memset(this, 0, sizeof(*this));
62 this->src
= new fs_reg
[MAX2(sources
, 3)];
63 for (unsigned i
= 0; i
< sources
; i
++)
64 this->src
[i
] = src
[i
];
66 this->opcode
= opcode
;
68 this->sources
= sources
;
69 this->exec_size
= exec_size
;
71 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
73 assert(this->exec_size
!= 0);
75 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
77 /* This will be the case for almost all instructions. */
84 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
88 this->regs_written
= 0;
92 unreachable("Invalid destination register file");
95 this->writes_accumulator
= false;
100 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
103 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
105 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
108 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
110 init(opcode
, exec_size
, dst
, NULL
, 0);
113 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
116 const fs_reg src
[1] = { src0
};
117 init(opcode
, exec_size
, dst
, src
, 1);
120 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
121 const fs_reg
&src0
, const fs_reg
&src1
)
123 const fs_reg src
[2] = { src0
, src1
};
124 init(opcode
, exec_size
, dst
, src
, 2);
127 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
128 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
130 const fs_reg src
[3] = { src0
, src1
, src2
};
131 init(opcode
, exec_size
, dst
, src
, 3);
134 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
135 const fs_reg src
[], unsigned sources
)
137 init(opcode
, exec_width
, dst
, src
, sources
);
140 fs_inst::fs_inst(const fs_inst
&that
)
142 memcpy(this, &that
, sizeof(that
));
144 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
146 for (unsigned i
= 0; i
< that
.sources
; i
++)
147 this->src
[i
] = that
.src
[i
];
156 fs_inst::resize_sources(uint8_t num_sources
)
158 if (this->sources
!= num_sources
) {
159 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
161 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
162 src
[i
] = this->src
[i
];
166 this->sources
= num_sources
;
171 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
173 const fs_reg
&surf_index
,
174 const fs_reg
&varying_offset
,
175 uint32_t const_offset
)
177 /* We have our constant surface use a pitch of 4 bytes, so our index can
178 * be any component of a vector, and then we load 4 contiguous
179 * components starting from that.
181 * We break down the const_offset to a portion added to the variable
182 * offset and a portion done using reg_offset, which means that if you
183 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
184 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
185 * CSE can later notice that those loads are all the same and eliminate
186 * the redundant ones.
188 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
189 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~3));
192 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
193 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
194 * u, v, r) as parameters, or we can just use the SIMD16 message
195 * consisting of (header, u). We choose the second, at the cost of a
196 * longer return length.
202 if (devinfo
->gen
>= 7)
203 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
205 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
207 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
208 fs_reg vec4_result
= fs_reg(VGRF
, alloc
.allocate(regs_written
), dst
.type
);
209 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
210 inst
->regs_written
= regs_written
;
212 if (devinfo
->gen
< 7) {
213 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
214 inst
->header_size
= 1;
215 if (devinfo
->gen
== 4)
218 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
221 bld
.MOV(dst
, offset(vec4_result
, bld
, (const_offset
& 3) * scale
));
225 * A helper for MOV generation for fixing up broken hardware SEND dependency
229 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
231 /* The caller always wants uncompressed to emit the minimal extra
232 * dependencies, and to avoid having to deal with aligning its regs to 2.
234 const fs_builder ubld
= bld
.annotate("send dependency resolve")
237 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
241 fs_inst::equals(fs_inst
*inst
) const
243 return (opcode
== inst
->opcode
&&
244 dst
.equals(inst
->dst
) &&
245 src
[0].equals(inst
->src
[0]) &&
246 src
[1].equals(inst
->src
[1]) &&
247 src
[2].equals(inst
->src
[2]) &&
248 saturate
== inst
->saturate
&&
249 predicate
== inst
->predicate
&&
250 conditional_mod
== inst
->conditional_mod
&&
251 mlen
== inst
->mlen
&&
252 base_mrf
== inst
->base_mrf
&&
253 target
== inst
->target
&&
255 header_size
== inst
->header_size
&&
256 shadow_compare
== inst
->shadow_compare
&&
257 exec_size
== inst
->exec_size
&&
258 offset
== inst
->offset
);
262 fs_inst::overwrites_reg(const fs_reg
®
) const
264 return reg
.in_range(dst
, regs_written
);
268 fs_inst::is_send_from_grf() const
271 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
272 case SHADER_OPCODE_SHADER_TIME_ADD
:
273 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
274 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
275 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
276 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
277 case SHADER_OPCODE_UNTYPED_ATOMIC
:
278 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
279 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
280 case SHADER_OPCODE_TYPED_ATOMIC
:
281 case SHADER_OPCODE_TYPED_SURFACE_READ
:
282 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
283 case SHADER_OPCODE_URB_WRITE_SIMD8
:
284 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
285 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
286 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
287 case SHADER_OPCODE_URB_READ_SIMD8
:
288 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
290 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
291 return src
[1].file
== VGRF
;
292 case FS_OPCODE_FB_WRITE
:
293 return src
[0].file
== VGRF
;
296 return src
[0].file
== VGRF
;
303 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
305 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
308 fs_reg reg
= this->src
[0];
309 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
312 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
315 for (int i
= 0; i
< this->sources
; i
++) {
316 reg
.type
= this->src
[i
].type
;
317 if (!this->src
[i
].equals(reg
))
320 if (i
< this->header_size
) {
323 reg
.reg_offset
+= this->exec_size
/ 8;
331 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
333 if (devinfo
->gen
== 6 && is_math())
336 if (is_send_from_grf())
339 if (!backend_instruction::can_do_source_mods())
346 fs_inst::can_change_types() const
348 return dst
.type
== src
[0].type
&&
349 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
350 (opcode
== BRW_OPCODE_MOV
||
351 (opcode
== BRW_OPCODE_SEL
&&
352 dst
.type
== src
[1].type
&&
353 predicate
!= BRW_PREDICATE_NONE
&&
354 !src
[1].abs
&& !src
[1].negate
));
358 fs_inst::has_side_effects() const
360 return this->eot
|| backend_instruction::has_side_effects();
366 memset(this, 0, sizeof(*this));
370 /** Generic unset register constructor. */
374 this->file
= BAD_FILE
;
377 fs_reg::fs_reg(struct brw_reg reg
) :
380 this->reg_offset
= 0;
381 this->subreg_offset
= 0;
382 this->reladdr
= NULL
;
384 if (this->file
== IMM
&&
385 (this->type
!= BRW_REGISTER_TYPE_V
&&
386 this->type
!= BRW_REGISTER_TYPE_UV
&&
387 this->type
!= BRW_REGISTER_TYPE_VF
)) {
393 fs_reg::equals(const fs_reg
&r
) const
395 return (memcmp((brw_reg
*)this, (brw_reg
*)&r
, sizeof(brw_reg
)) == 0 &&
396 reg_offset
== r
.reg_offset
&&
397 subreg_offset
== r
.subreg_offset
&&
398 !reladdr
&& !r
.reladdr
&&
403 fs_reg::set_smear(unsigned subreg
)
405 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
406 subreg_offset
= subreg
* type_sz(type
);
412 fs_reg::is_contiguous() const
418 fs_reg::component_size(unsigned width
) const
420 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
423 return MAX2(width
* stride
, 1) * type_sz(type
);
427 type_size_scalar(const struct glsl_type
*type
)
429 unsigned int size
, i
;
431 switch (type
->base_type
) {
434 case GLSL_TYPE_FLOAT
:
436 return type
->components();
437 case GLSL_TYPE_ARRAY
:
438 return type_size_scalar(type
->fields
.array
) * type
->length
;
439 case GLSL_TYPE_STRUCT
:
441 for (i
= 0; i
< type
->length
; i
++) {
442 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
445 case GLSL_TYPE_SAMPLER
:
446 /* Samplers take up no register space, since they're baked in at
450 case GLSL_TYPE_ATOMIC_UINT
:
452 case GLSL_TYPE_SUBROUTINE
:
454 case GLSL_TYPE_IMAGE
:
455 return BRW_IMAGE_PARAM_SIZE
;
457 case GLSL_TYPE_ERROR
:
458 case GLSL_TYPE_INTERFACE
:
459 case GLSL_TYPE_DOUBLE
:
460 unreachable("not reached");
467 * Returns the number of scalar components needed to store type, assuming
468 * that vectors are padded out to vec4.
470 * This has the packing rules of type_size_vec4(), but counts components
471 * similar to type_size_scalar().
474 type_size_vec4_times_4(const struct glsl_type
*type
)
476 return 4 * type_size_vec4(type
);
480 * Create a MOV to read the timestamp register.
482 * The caller is responsible for emitting the MOV. The return value is
483 * the destination of the MOV, with extra parameters set.
486 fs_visitor::get_timestamp(const fs_builder
&bld
)
488 assert(devinfo
->gen
>= 7);
490 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
493 BRW_REGISTER_TYPE_UD
));
495 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
497 /* We want to read the 3 fields we care about even if it's not enabled in
500 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
506 fs_visitor::emit_shader_time_begin()
508 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
510 /* We want only the low 32 bits of the timestamp. Since it's running
511 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
512 * which is plenty of time for our purposes. It is identical across the
513 * EUs, but since it's tracking GPU core speed it will increment at a
514 * varying rate as render P-states change.
516 shader_start_time
.set_smear(0);
520 fs_visitor::emit_shader_time_end()
522 /* Insert our code just before the final SEND with EOT. */
523 exec_node
*end
= this->instructions
.get_tail();
524 assert(end
&& ((fs_inst
*) end
)->eot
);
525 const fs_builder ibld
= bld
.annotate("shader time end")
526 .exec_all().at(NULL
, end
);
528 fs_reg shader_end_time
= get_timestamp(ibld
);
530 /* We only use the low 32 bits of the timestamp - see
531 * emit_shader_time_begin()).
533 * We could also check if render P-states have changed (or anything
534 * else that might disrupt timing) by setting smear to 2 and checking if
535 * that field is != 0.
537 shader_end_time
.set_smear(0);
539 /* Check that there weren't any timestamp reset events (assuming these
540 * were the only two timestamp reads that happened).
542 fs_reg reset
= shader_end_time
;
544 set_condmod(BRW_CONDITIONAL_Z
,
545 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
546 ibld
.IF(BRW_PREDICATE_NORMAL
);
548 fs_reg start
= shader_start_time
;
550 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
553 const fs_builder cbld
= ibld
.group(1, 0);
554 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
556 /* If there were no instructions between the two timestamp gets, the diff
557 * is 2 cycles. Remove that overhead, so I can forget about that when
558 * trying to determine the time taken for single instructions.
560 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
561 SHADER_TIME_ADD(cbld
, 0, diff
);
562 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
563 ibld
.emit(BRW_OPCODE_ELSE
);
564 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
565 ibld
.emit(BRW_OPCODE_ENDIF
);
569 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
570 int shader_time_subindex
,
573 int index
= shader_time_index
* 3 + shader_time_subindex
;
574 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
577 if (dispatch_width
== 8)
578 payload
= vgrf(glsl_type::uvec2_type
);
580 payload
= vgrf(glsl_type::uint_type
);
582 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
586 fs_visitor::vfail(const char *format
, va_list va
)
595 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
596 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
598 this->fail_msg
= msg
;
601 fprintf(stderr
, "%s", msg
);
606 fs_visitor::fail(const char *format
, ...)
610 va_start(va
, format
);
616 * Mark this program as impossible to compile in SIMD16 mode.
618 * During the SIMD8 compile (which happens first), we can detect and flag
619 * things that are unsupported in SIMD16 mode, so the compiler can skip
620 * the SIMD16 compile altogether.
622 * During a SIMD16 compile (if one happens anyway), this just calls fail().
625 fs_visitor::no16(const char *msg
)
627 if (dispatch_width
== 16) {
630 simd16_unsupported
= true;
632 compiler
->shader_perf_log(log_data
,
633 "SIMD16 shader failed to compile: %s", msg
);
638 * Returns true if the instruction has a flag that means it won't
639 * update an entire destination register.
641 * For example, dead code elimination and live variable analysis want to know
642 * when a write to a variable screens off any preceding values that were in
646 fs_inst::is_partial_write() const
648 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
649 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
650 !this->dst
.is_contiguous());
654 fs_inst::components_read(unsigned i
) const
657 case FS_OPCODE_LINTERP
:
663 case FS_OPCODE_PIXEL_X
:
664 case FS_OPCODE_PIXEL_Y
:
668 case FS_OPCODE_FB_WRITE_LOGICAL
:
669 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
670 /* First/second FB write color. */
672 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
676 case SHADER_OPCODE_TEX_LOGICAL
:
677 case SHADER_OPCODE_TXD_LOGICAL
:
678 case SHADER_OPCODE_TXF_LOGICAL
:
679 case SHADER_OPCODE_TXL_LOGICAL
:
680 case SHADER_OPCODE_TXS_LOGICAL
:
681 case FS_OPCODE_TXB_LOGICAL
:
682 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
683 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
684 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
685 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
686 case SHADER_OPCODE_LOD_LOGICAL
:
687 case SHADER_OPCODE_TG4_LOGICAL
:
688 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
689 assert(src
[8].file
== IMM
&& src
[9].file
== IMM
);
690 /* Texture coordinates. */
693 /* Texture derivatives. */
694 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
696 /* Texture offset. */
700 else if (i
== 5 && opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
705 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
706 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
707 assert(src
[3].file
== IMM
);
708 /* Surface coordinates. */
711 /* Surface operation source (ignored for reads). */
717 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
718 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
719 assert(src
[3].file
== IMM
&&
721 /* Surface coordinates. */
724 /* Surface operation source. */
730 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
731 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
732 assert(src
[3].file
== IMM
&&
734 const unsigned op
= src
[4].ud
;
735 /* Surface coordinates. */
738 /* Surface operation source. */
739 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
741 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
742 op
== BRW_AOP_PREDEC
))
754 fs_inst::regs_read(int arg
) const
757 case FS_OPCODE_FB_WRITE
:
758 case SHADER_OPCODE_URB_WRITE_SIMD8
:
759 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
760 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
761 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
762 case SHADER_OPCODE_URB_READ_SIMD8
:
763 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
764 case SHADER_OPCODE_UNTYPED_ATOMIC
:
765 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
766 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
767 case SHADER_OPCODE_TYPED_ATOMIC
:
768 case SHADER_OPCODE_TYPED_SURFACE_READ
:
769 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
770 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
775 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
776 /* The payload is actually stored in src1 */
781 case FS_OPCODE_LINTERP
:
786 case SHADER_OPCODE_LOAD_PAYLOAD
:
787 if (arg
< this->header_size
)
791 case CS_OPCODE_CS_TERMINATE
:
792 case SHADER_OPCODE_BARRIER
:
795 case SHADER_OPCODE_MOV_INDIRECT
:
797 assert(src
[2].file
== IMM
);
798 unsigned region_length
= src
[2].ud
;
800 if (src
[0].file
== FIXED_GRF
) {
801 /* If the start of the region is not register aligned, then
802 * there's some portion of the register that's technically
803 * unread at the beginning.
805 * However, the register allocator works in terms of whole
806 * registers, and does not use subnr. It assumes that the
807 * read starts at the beginning of the register, and extends
808 * regs_read() whole registers beyond that.
810 * To compensate, we extend the region length to include this
811 * unread portion at the beginning.
814 region_length
+= src
[0].subnr
* type_sz(src
[0].type
);
816 return DIV_ROUND_UP(region_length
, REG_SIZE
);
818 assert(!"Invalid register file");
824 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
829 switch (src
[arg
].file
) {
839 return DIV_ROUND_UP(components_read(arg
) *
840 src
[arg
].component_size(exec_size
),
843 unreachable("MRF registers are not allowed as sources");
849 fs_inst::reads_flag() const
855 fs_inst::writes_flag() const
857 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
858 opcode
!= BRW_OPCODE_IF
&&
859 opcode
!= BRW_OPCODE_WHILE
)) ||
860 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
864 * Returns how many MRFs an FS opcode will write over.
866 * Note that this is not the 0 or 1 implied writes in an actual gen
867 * instruction -- the FS opcodes often generate MOVs in addition.
870 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
875 if (inst
->base_mrf
== -1)
878 switch (inst
->opcode
) {
879 case SHADER_OPCODE_RCP
:
880 case SHADER_OPCODE_RSQ
:
881 case SHADER_OPCODE_SQRT
:
882 case SHADER_OPCODE_EXP2
:
883 case SHADER_OPCODE_LOG2
:
884 case SHADER_OPCODE_SIN
:
885 case SHADER_OPCODE_COS
:
886 return 1 * dispatch_width
/ 8;
887 case SHADER_OPCODE_POW
:
888 case SHADER_OPCODE_INT_QUOTIENT
:
889 case SHADER_OPCODE_INT_REMAINDER
:
890 return 2 * dispatch_width
/ 8;
891 case SHADER_OPCODE_TEX
:
893 case SHADER_OPCODE_TXD
:
894 case SHADER_OPCODE_TXF
:
895 case SHADER_OPCODE_TXF_CMS
:
896 case SHADER_OPCODE_TXF_CMS_W
:
897 case SHADER_OPCODE_TXF_MCS
:
898 case SHADER_OPCODE_TG4
:
899 case SHADER_OPCODE_TG4_OFFSET
:
900 case SHADER_OPCODE_TXL
:
901 case SHADER_OPCODE_TXS
:
902 case SHADER_OPCODE_LOD
:
903 case SHADER_OPCODE_SAMPLEINFO
:
905 case FS_OPCODE_FB_WRITE
:
907 case FS_OPCODE_GET_BUFFER_SIZE
:
908 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
909 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
911 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
913 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
915 case SHADER_OPCODE_UNTYPED_ATOMIC
:
916 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
917 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
918 case SHADER_OPCODE_TYPED_ATOMIC
:
919 case SHADER_OPCODE_TYPED_SURFACE_READ
:
920 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
921 case SHADER_OPCODE_URB_WRITE_SIMD8
:
922 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
923 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
924 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
925 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
926 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
927 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
928 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
931 unreachable("not reached");
936 fs_visitor::vgrf(const glsl_type
*const type
)
938 int reg_width
= dispatch_width
/ 8;
939 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
940 brw_type_for_base_type(type
));
943 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
948 this->type
= BRW_REGISTER_TYPE_F
;
949 this->stride
= (file
== UNIFORM
? 0 : 1);
952 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
958 this->stride
= (file
== UNIFORM
? 0 : 1);
961 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
962 * This brings in those uniform definitions
965 fs_visitor::import_uniforms(fs_visitor
*v
)
967 this->push_constant_loc
= v
->push_constant_loc
;
968 this->pull_constant_loc
= v
->pull_constant_loc
;
969 this->uniforms
= v
->uniforms
;
970 this->param_size
= v
->param_size
;
974 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
975 bool origin_upper_left
)
977 assert(stage
== MESA_SHADER_FRAGMENT
);
978 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
979 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
981 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
984 if (pixel_center_integer
) {
985 bld
.MOV(wpos
, this->pixel_x
);
987 bld
.ADD(wpos
, this->pixel_x
, brw_imm_f(0.5f
));
989 wpos
= offset(wpos
, bld
, 1);
992 if (!flip
&& pixel_center_integer
) {
993 bld
.MOV(wpos
, this->pixel_y
);
995 fs_reg pixel_y
= this->pixel_y
;
996 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
999 pixel_y
.negate
= true;
1000 offset
+= key
->drawable_height
- 1.0f
;
1003 bld
.ADD(wpos
, pixel_y
, brw_imm_f(offset
));
1005 wpos
= offset(wpos
, bld
, 1);
1007 /* gl_FragCoord.z */
1008 if (devinfo
->gen
>= 6) {
1009 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1011 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1012 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1013 interp_reg(VARYING_SLOT_POS
, 2));
1015 wpos
= offset(wpos
, bld
, 1);
1017 /* gl_FragCoord.w: Already set up in emit_interpolation */
1018 bld
.MOV(wpos
, this->wpos_w
);
1024 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1025 glsl_interp_qualifier interpolation_mode
,
1026 bool is_centroid
, bool is_sample
)
1028 brw_wm_barycentric_interp_mode barycoord_mode
;
1029 if (devinfo
->gen
>= 6) {
1031 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1032 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1034 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1035 } else if (is_sample
) {
1036 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1037 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1039 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1041 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1042 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1044 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1047 /* On Ironlake and below, there is only one interpolation mode.
1048 * Centroid interpolation doesn't mean anything on this hardware --
1049 * there is no multisampling.
1051 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1053 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1054 this->delta_xy
[barycoord_mode
], interp
);
1058 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1059 const glsl_type
*type
,
1060 glsl_interp_qualifier interpolation_mode
,
1061 int location
, bool mod_centroid
,
1064 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1066 assert(stage
== MESA_SHADER_FRAGMENT
);
1067 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1068 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1070 unsigned int array_elements
;
1072 if (type
->is_array()) {
1073 array_elements
= type
->arrays_of_arrays_size();
1074 if (array_elements
== 0) {
1075 fail("dereferenced array '%s' has length 0\n", name
);
1077 type
= type
->without_array();
1082 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1084 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1085 if (key
->flat_shade
&& is_gl_Color
) {
1086 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1088 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1092 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1093 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1094 if (prog_data
->urb_setup
[location
] == -1) {
1095 /* If there's no incoming setup data for this slot, don't
1096 * emit interpolation for it.
1098 attr
= offset(attr
, bld
, type
->vector_elements
);
1103 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1104 /* Constant interpolation (flat shading) case. The SF has
1105 * handed us defined values in only the constant offset
1106 * field of the setup reg.
1108 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1109 struct brw_reg interp
= interp_reg(location
, k
);
1110 interp
= suboffset(interp
, 3);
1111 interp
.type
= attr
.type
;
1112 bld
.emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1113 attr
= offset(attr
, bld
, 1);
1116 /* Smooth/noperspective interpolation case. */
1117 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1118 struct brw_reg interp
= interp_reg(location
, k
);
1119 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1120 /* Get the pixel/sample mask into f0 so that we know
1121 * which pixels are lit. Then, for each channel that is
1122 * unlit, replace the centroid data with non-centroid
1125 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1128 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1130 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1131 inst
->predicate_inverse
= true;
1132 if (devinfo
->has_pln
)
1133 inst
->no_dd_clear
= true;
1135 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1136 mod_centroid
&& !key
->persample_shading
,
1137 mod_sample
|| key
->persample_shading
);
1138 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1139 inst
->predicate_inverse
= false;
1140 if (devinfo
->has_pln
)
1141 inst
->no_dd_check
= true;
1144 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1145 mod_centroid
&& !key
->persample_shading
,
1146 mod_sample
|| key
->persample_shading
);
1148 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1149 bld
.MUL(attr
, attr
, this->pixel_w
);
1151 attr
= offset(attr
, bld
, 1);
1161 fs_visitor::emit_frontfacing_interpolation()
1163 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1165 if (devinfo
->gen
>= 6) {
1166 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1167 * a boolean result from this (~0/true or 0/false).
1169 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1170 * this task in only one instruction:
1171 * - a negation source modifier will flip the bit; and
1172 * - a W -> D type conversion will sign extend the bit into the high
1173 * word of the destination.
1175 * An ASR 15 fills the low word of the destination.
1177 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1180 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1182 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1183 * a boolean result from this (1/true or 0/false).
1185 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1186 * the negation source modifier to flip it. Unfortunately the SHR
1187 * instruction only operates on UD (or D with an abs source modifier)
1188 * sources without negation.
1190 * Instead, use ASR (which will give ~0/true or 0/false).
1192 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1195 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1202 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1204 assert(stage
== MESA_SHADER_FRAGMENT
);
1205 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1206 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1208 if (key
->compute_pos_offset
) {
1209 /* Convert int_sample_pos to floating point */
1210 bld
.MOV(dst
, int_sample_pos
);
1211 /* Scale to the range [0, 1] */
1212 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1215 /* From ARB_sample_shading specification:
1216 * "When rendering to a non-multisample buffer, or if multisample
1217 * rasterization is disabled, gl_SamplePosition will always be
1220 bld
.MOV(dst
, brw_imm_f(0.5f
));
1225 fs_visitor::emit_samplepos_setup()
1227 assert(devinfo
->gen
>= 6);
1229 const fs_builder abld
= bld
.annotate("compute sample position");
1230 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1232 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1233 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1235 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1236 * mode will be enabled.
1238 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1239 * R31.1:0 Position Offset X/Y for Slot[3:0]
1240 * R31.3:2 Position Offset X/Y for Slot[7:4]
1243 * The X, Y sample positions come in as bytes in thread payload. So, read
1244 * the positions using vstride=16, width=8, hstride=2.
1246 struct brw_reg sample_pos_reg
=
1247 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1248 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1250 if (dispatch_width
== 8) {
1251 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1253 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1254 abld
.half(1).MOV(half(int_sample_x
, 1),
1255 fs_reg(suboffset(sample_pos_reg
, 16)));
1257 /* Compute gl_SamplePosition.x */
1258 compute_sample_position(pos
, int_sample_x
);
1259 pos
= offset(pos
, abld
, 1);
1260 if (dispatch_width
== 8) {
1261 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1263 abld
.half(0).MOV(half(int_sample_y
, 0),
1264 fs_reg(suboffset(sample_pos_reg
, 1)));
1265 abld
.half(1).MOV(half(int_sample_y
, 1),
1266 fs_reg(suboffset(sample_pos_reg
, 17)));
1268 /* Compute gl_SamplePosition.y */
1269 compute_sample_position(pos
, int_sample_y
);
1274 fs_visitor::emit_sampleid_setup()
1276 assert(stage
== MESA_SHADER_FRAGMENT
);
1277 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1278 assert(devinfo
->gen
>= 6);
1280 const fs_builder abld
= bld
.annotate("compute sample id");
1281 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1283 if (key
->compute_sample_id
) {
1284 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1286 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1288 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1289 * 8x multisampling, subspan 0 will represent sample N (where N
1290 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1291 * 7. We can find the value of N by looking at R0.0 bits 7:6
1292 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1293 * (since samples are always delivered in pairs). That is, we
1294 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1295 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1296 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1297 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1298 * populating a temporary variable with the sequence (0, 1, 2, 3),
1299 * and then reading from it using vstride=1, width=4, hstride=0.
1300 * These computations hold good for 4x multisampling as well.
1302 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1303 * the first four slots are sample 0 of subspan 0; the next four
1304 * are sample 1 of subspan 0; the third group is sample 0 of
1305 * subspan 1, and finally sample 1 of subspan 1.
1308 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1309 * accomodate 16x MSAA.
1311 unsigned sspi_mask
= devinfo
->gen
>= 9 ? 0x1c0 : 0xc0;
1313 abld
.exec_all().group(1, 0)
1314 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1315 brw_imm_ud(sspi_mask
));
1316 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1318 /* This works for both SIMD8 and SIMD16 */
1319 abld
.exec_all().group(4, 0)
1320 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1322 /* This special instruction takes care of setting vstride=1,
1323 * width=4, hstride=0 of t2 during an ADD instruction.
1325 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1327 /* As per GL_ARB_sample_shading specification:
1328 * "When rendering to a non-multisample buffer, or if multisample
1329 * rasterization is disabled, gl_SampleID will always be zero."
1331 abld
.MOV(*reg
, brw_imm_d(0));
1338 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1340 if (!src
.abs
&& !src
.negate
)
1343 fs_reg temp
= bld
.vgrf(src
.type
);
1350 fs_visitor::emit_discard_jump()
1352 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1354 /* For performance, after a discard, jump to the end of the
1355 * shader if all relevant channels have been discarded.
1357 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1358 discard_jump
->flag_subreg
= 1;
1360 discard_jump
->predicate
= (dispatch_width
== 8)
1361 ? BRW_PREDICATE_ALIGN1_ANY8H
1362 : BRW_PREDICATE_ALIGN1_ANY16H
;
1363 discard_jump
->predicate_inverse
= true;
1367 fs_visitor::emit_gs_thread_end()
1369 assert(stage
== MESA_SHADER_GEOMETRY
);
1371 struct brw_gs_prog_data
*gs_prog_data
=
1372 (struct brw_gs_prog_data
*) prog_data
;
1374 if (gs_compile
->control_data_header_size_bits
> 0) {
1375 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1378 const fs_builder abld
= bld
.annotate("thread end");
1381 if (gs_prog_data
->static_vertex_count
!= -1) {
1382 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1383 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1384 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1385 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1386 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1389 /* Delete now dead instructions. */
1390 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1396 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1400 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1401 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1402 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1405 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1406 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1407 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1408 sources
[1] = this->final_gs_vertex_count
;
1409 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1410 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1418 fs_visitor::assign_curb_setup()
1420 if (dispatch_width
== 8) {
1421 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1423 if (stage
== MESA_SHADER_FRAGMENT
) {
1424 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1425 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1426 } else if (stage
== MESA_SHADER_COMPUTE
) {
1427 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1428 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1430 unreachable("Unsupported shader type!");
1434 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1436 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1437 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1438 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1439 if (inst
->src
[i
].file
== UNIFORM
) {
1440 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1442 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1443 constant_nr
= push_constant_loc
[uniform_nr
];
1445 /* Section 5.11 of the OpenGL 4.1 spec says:
1446 * "Out-of-bounds reads return undefined values, which include
1447 * values from other variables of the active program or zero."
1448 * Just return the first push constant.
1453 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1456 brw_reg
.abs
= inst
->src
[i
].abs
;
1457 brw_reg
.negate
= inst
->src
[i
].negate
;
1459 assert(inst
->src
[i
].stride
== 0);
1460 inst
->src
[i
] = byte_offset(
1461 retype(brw_reg
, inst
->src
[i
].type
),
1462 inst
->src
[i
].subreg_offset
);
1467 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1468 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1472 fs_visitor::calculate_urb_setup()
1474 assert(stage
== MESA_SHADER_FRAGMENT
);
1475 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1476 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1478 memset(prog_data
->urb_setup
, -1,
1479 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1482 /* Figure out where each of the incoming setup attributes lands. */
1483 if (devinfo
->gen
>= 6) {
1484 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1485 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1486 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1487 * first 16 varying inputs, so we can put them wherever we want.
1488 * Just put them in order.
1490 * This is useful because it means that (a) inputs not used by the
1491 * fragment shader won't take up valuable register space, and (b) we
1492 * won't have to recompile the fragment shader if it gets paired with
1493 * a different vertex (or geometry) shader.
1495 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1496 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1497 BITFIELD64_BIT(i
)) {
1498 prog_data
->urb_setup
[i
] = urb_next
++;
1502 bool include_vue_header
=
1503 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1505 /* We have enough input varyings that the SF/SBE pipeline stage can't
1506 * arbitrarily rearrange them to suit our whim; we have to put them
1507 * in an order that matches the output of the previous pipeline stage
1508 * (geometry or vertex shader).
1510 struct brw_vue_map prev_stage_vue_map
;
1511 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1512 key
->input_slots_valid
,
1513 nir
->info
.separate_shader
);
1515 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1517 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1518 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1520 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1521 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1522 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1523 BITFIELD64_BIT(varying
))) {
1524 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1527 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1530 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1531 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1532 /* Point size is packed into the header, not as a general attribute */
1533 if (i
== VARYING_SLOT_PSIZ
)
1536 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1537 /* The back color slot is skipped when the front color is
1538 * also written to. In addition, some slots can be
1539 * written in the vertex shader and not read in the
1540 * fragment shader. So the register number must always be
1541 * incremented, mapped or not.
1543 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1544 prog_data
->urb_setup
[i
] = urb_next
;
1550 * It's a FS only attribute, and we did interpolation for this attribute
1551 * in SF thread. So, count it here, too.
1553 * See compile_sf_prog() for more info.
1555 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1556 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1559 prog_data
->num_varying_inputs
= urb_next
;
1563 fs_visitor::assign_urb_setup()
1565 assert(stage
== MESA_SHADER_FRAGMENT
);
1566 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1568 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1570 /* Offset all the urb_setup[] index by the actual position of the
1571 * setup regs, now that the location of the constants has been chosen.
1573 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1574 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1575 assert(inst
->src
[1].file
== FIXED_GRF
);
1576 inst
->src
[1].nr
+= urb_start
;
1579 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1580 assert(inst
->src
[0].file
== FIXED_GRF
);
1581 inst
->src
[0].nr
+= urb_start
;
1585 /* Each attribute is 4 setup channels, each of which is half a reg. */
1586 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1590 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1592 for (int i
= 0; i
< inst
->sources
; i
++) {
1593 if (inst
->src
[i
].file
== ATTR
) {
1594 int grf
= payload
.num_regs
+
1595 prog_data
->curb_read_length
+
1597 inst
->src
[i
].reg_offset
;
1599 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : inst
->exec_size
;
1600 struct brw_reg reg
=
1601 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1602 inst
->src
[i
].subreg_offset
),
1603 inst
->exec_size
* inst
->src
[i
].stride
,
1604 width
, inst
->src
[i
].stride
);
1605 reg
.abs
= inst
->src
[i
].abs
;
1606 reg
.negate
= inst
->src
[i
].negate
;
1614 fs_visitor::assign_vs_urb_setup()
1616 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1618 assert(stage
== MESA_SHADER_VERTEX
);
1619 int count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1620 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1623 /* Each attribute is 4 regs. */
1624 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1626 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1628 /* Rewrite all ATTR file references to the hw grf that they land in. */
1629 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1630 convert_attr_sources_to_hw_regs(inst
);
1635 fs_visitor::assign_gs_urb_setup()
1637 assert(stage
== MESA_SHADER_GEOMETRY
);
1639 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1641 first_non_payload_grf
+=
1642 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1644 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1645 /* Rewrite all ATTR file references to GRFs. */
1646 convert_attr_sources_to_hw_regs(inst
);
1652 * Split large virtual GRFs into separate components if we can.
1654 * This is mostly duplicated with what brw_fs_vector_splitting does,
1655 * but that's really conservative because it's afraid of doing
1656 * splitting that doesn't result in real progress after the rest of
1657 * the optimization phases, which would cause infinite looping in
1658 * optimization. We can do it once here, safely. This also has the
1659 * opportunity to split interpolated values, or maybe even uniforms,
1660 * which we don't have at the IR level.
1662 * We want to split, because virtual GRFs are what we register
1663 * allocate and spill (due to contiguousness requirements for some
1664 * instructions), and they're what we naturally generate in the
1665 * codegen process, but most virtual GRFs don't actually need to be
1666 * contiguous sets of GRFs. If we split, we'll end up with reduced
1667 * live intervals and better dead code elimination and coalescing.
1670 fs_visitor::split_virtual_grfs()
1672 int num_vars
= this->alloc
.count
;
1674 /* Count the total number of registers */
1676 int vgrf_to_reg
[num_vars
];
1677 for (int i
= 0; i
< num_vars
; i
++) {
1678 vgrf_to_reg
[i
] = reg_count
;
1679 reg_count
+= alloc
.sizes
[i
];
1682 /* An array of "split points". For each register slot, this indicates
1683 * if this slot can be separated from the previous slot. Every time an
1684 * instruction uses multiple elements of a register (as a source or
1685 * destination), we mark the used slots as inseparable. Then we go
1686 * through and split the registers into the smallest pieces we can.
1688 bool split_points
[reg_count
];
1689 memset(split_points
, 0, sizeof(split_points
));
1691 /* Mark all used registers as fully splittable */
1692 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1693 if (inst
->dst
.file
== VGRF
) {
1694 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1695 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1696 split_points
[reg
+ j
] = true;
1699 for (int i
= 0; i
< inst
->sources
; i
++) {
1700 if (inst
->src
[i
].file
== VGRF
) {
1701 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1702 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1703 split_points
[reg
+ j
] = true;
1708 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1709 if (inst
->dst
.file
== VGRF
) {
1710 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1711 for (int j
= 1; j
< inst
->regs_written
; j
++)
1712 split_points
[reg
+ j
] = false;
1714 for (int i
= 0; i
< inst
->sources
; i
++) {
1715 if (inst
->src
[i
].file
== VGRF
) {
1716 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1717 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1718 split_points
[reg
+ j
] = false;
1723 int new_virtual_grf
[reg_count
];
1724 int new_reg_offset
[reg_count
];
1727 for (int i
= 0; i
< num_vars
; i
++) {
1728 /* The first one should always be 0 as a quick sanity check. */
1729 assert(split_points
[reg
] == false);
1732 new_reg_offset
[reg
] = 0;
1737 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1738 /* If this is a split point, reset the offset to 0 and allocate a
1739 * new virtual GRF for the previous offset many registers
1741 if (split_points
[reg
]) {
1742 assert(offset
<= MAX_VGRF_SIZE
);
1743 int grf
= alloc
.allocate(offset
);
1744 for (int k
= reg
- offset
; k
< reg
; k
++)
1745 new_virtual_grf
[k
] = grf
;
1748 new_reg_offset
[reg
] = offset
;
1753 /* The last one gets the original register number */
1754 assert(offset
<= MAX_VGRF_SIZE
);
1755 alloc
.sizes
[i
] = offset
;
1756 for (int k
= reg
- offset
; k
< reg
; k
++)
1757 new_virtual_grf
[k
] = i
;
1759 assert(reg
== reg_count
);
1761 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1762 if (inst
->dst
.file
== VGRF
) {
1763 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1764 inst
->dst
.nr
= new_virtual_grf
[reg
];
1765 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1766 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1768 for (int i
= 0; i
< inst
->sources
; i
++) {
1769 if (inst
->src
[i
].file
== VGRF
) {
1770 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1771 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1772 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1773 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1777 invalidate_live_intervals();
1781 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1783 * During code generation, we create tons of temporary variables, many of
1784 * which get immediately killed and are never used again. Yet, in later
1785 * optimization and analysis passes, such as compute_live_intervals, we need
1786 * to loop over all the virtual GRFs. Compacting them can save a lot of
1790 fs_visitor::compact_virtual_grfs()
1792 bool progress
= false;
1793 int remap_table
[this->alloc
.count
];
1794 memset(remap_table
, -1, sizeof(remap_table
));
1796 /* Mark which virtual GRFs are used. */
1797 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1798 if (inst
->dst
.file
== VGRF
)
1799 remap_table
[inst
->dst
.nr
] = 0;
1801 for (int i
= 0; i
< inst
->sources
; i
++) {
1802 if (inst
->src
[i
].file
== VGRF
)
1803 remap_table
[inst
->src
[i
].nr
] = 0;
1807 /* Compact the GRF arrays. */
1809 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1810 if (remap_table
[i
] == -1) {
1811 /* We just found an unused register. This means that we are
1812 * actually going to compact something.
1816 remap_table
[i
] = new_index
;
1817 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1818 invalidate_live_intervals();
1823 this->alloc
.count
= new_index
;
1825 /* Patch all the instructions to use the newly renumbered registers */
1826 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1827 if (inst
->dst
.file
== VGRF
)
1828 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1830 for (int i
= 0; i
< inst
->sources
; i
++) {
1831 if (inst
->src
[i
].file
== VGRF
)
1832 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1836 /* Patch all the references to delta_xy, since they're used in register
1837 * allocation. If they're unused, switch them to BAD_FILE so we don't
1838 * think some random VGRF is delta_xy.
1840 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1841 if (delta_xy
[i
].file
== VGRF
) {
1842 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1843 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1845 delta_xy
[i
].file
= BAD_FILE
;
1854 * Assign UNIFORM file registers to either push constants or pull constants.
1856 * We allow a fragment shader to have more than the specified minimum
1857 * maximum number of fragment shader uniform components (64). If
1858 * there are too many of these, they'd fill up all of register space.
1859 * So, this will push some of them out to the pull constant buffer and
1860 * update the program to load them. We also use pull constants for all
1861 * indirect constant loads because we don't support indirect accesses in
1865 fs_visitor::assign_constant_locations()
1867 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1868 if (dispatch_width
!= 8)
1871 unsigned int num_pull_constants
= 0;
1873 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1874 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1876 bool is_live
[uniforms
];
1877 memset(is_live
, 0, sizeof(is_live
));
1879 /* First, we walk through the instructions and do two things:
1881 * 1) Figure out which uniforms are live.
1883 * 2) Find all indirect access of uniform arrays and flag them as needing
1884 * to go into the pull constant buffer.
1886 * Note that we don't move constant-indexed accesses to arrays. No
1887 * testing has been done of the performance impact of this choice.
1889 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1890 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1891 if (inst
->src
[i
].file
!= UNIFORM
)
1894 if (inst
->src
[i
].reladdr
) {
1895 int uniform
= inst
->src
[i
].nr
;
1897 /* If this array isn't already present in the pull constant buffer,
1900 if (pull_constant_loc
[uniform
] == -1) {
1901 assert(param_size
[uniform
]);
1902 for (int j
= 0; j
< param_size
[uniform
]; j
++)
1903 pull_constant_loc
[uniform
+ j
] = num_pull_constants
++;
1906 /* Mark the the one accessed uniform as live */
1907 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1908 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1909 is_live
[constant_nr
] = true;
1914 /* Only allow 16 registers (128 uniform components) as push constants.
1916 * Just demote the end of the list. We could probably do better
1917 * here, demoting things that are rarely used in the program first.
1919 * If changing this value, note the limitation about total_regs in
1922 unsigned int max_push_components
= 16 * 8;
1923 unsigned int num_push_constants
= 0;
1925 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1927 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1928 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1929 /* This UNIFORM register is either dead, or has already been demoted
1930 * to a pull const. Mark it as no longer living in the param[] array.
1932 push_constant_loc
[i
] = -1;
1936 if (num_push_constants
< max_push_components
) {
1937 /* Retain as a push constant. Record the location in the params[]
1940 push_constant_loc
[i
] = num_push_constants
++;
1942 /* Demote to a pull constant. */
1943 push_constant_loc
[i
] = -1;
1944 pull_constant_loc
[i
] = num_pull_constants
++;
1948 stage_prog_data
->nr_params
= num_push_constants
;
1949 stage_prog_data
->nr_pull_params
= num_pull_constants
;
1951 /* Up until now, the param[] array has been indexed by reg + reg_offset
1952 * of UNIFORM registers. Move pull constants into pull_param[] and
1953 * condense param[] to only contain the uniforms we chose to push.
1955 * NOTE: Because we are condensing the params[] array, we know that
1956 * push_constant_loc[i] <= i and we can do it in one smooth loop without
1957 * having to make a copy.
1959 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1960 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
1962 if (pull_constant_loc
[i
] != -1) {
1963 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
1964 } else if (push_constant_loc
[i
] != -1) {
1965 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
1971 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
1972 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
1975 fs_visitor::demote_pull_constants()
1977 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1978 for (int i
= 0; i
< inst
->sources
; i
++) {
1979 if (inst
->src
[i
].file
!= UNIFORM
)
1983 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1984 if (location
>= uniforms
) /* Out of bounds access */
1987 pull_index
= pull_constant_loc
[location
];
1989 if (pull_index
== -1)
1992 /* Set up the annotation tracking for new generated instructions. */
1993 const fs_builder
ibld(this, block
, inst
);
1994 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
1995 fs_reg dst
= vgrf(glsl_type::float_type
);
1997 assert(inst
->src
[i
].stride
== 0);
1999 /* Generate a pull load into dst. */
2000 if (inst
->src
[i
].reladdr
) {
2001 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
2003 *inst
->src
[i
].reladdr
,
2005 inst
->src
[i
].reladdr
= NULL
;
2006 inst
->src
[i
].stride
= 1;
2008 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2009 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2010 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2011 dst
, brw_imm_ud(index
), offset
);
2012 inst
->src
[i
].set_smear(pull_index
& 3);
2014 brw_mark_surface_used(prog_data
, index
);
2016 /* Rewrite the instruction to use the temporary VGRF. */
2017 inst
->src
[i
].file
= VGRF
;
2018 inst
->src
[i
].nr
= dst
.nr
;
2019 inst
->src
[i
].reg_offset
= 0;
2022 invalidate_live_intervals();
2026 fs_visitor::opt_algebraic()
2028 bool progress
= false;
2030 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2031 switch (inst
->opcode
) {
2032 case BRW_OPCODE_MOV
:
2033 if (inst
->src
[0].file
!= IMM
)
2036 if (inst
->saturate
) {
2037 if (inst
->dst
.type
!= inst
->src
[0].type
)
2038 assert(!"unimplemented: saturate mixed types");
2040 if (brw_saturate_immediate(inst
->dst
.type
, &inst
->src
[0])) {
2041 inst
->saturate
= false;
2047 case BRW_OPCODE_MUL
:
2048 if (inst
->src
[1].file
!= IMM
)
2052 if (inst
->src
[1].is_one()) {
2053 inst
->opcode
= BRW_OPCODE_MOV
;
2054 inst
->src
[1] = reg_undef
;
2060 if (inst
->src
[1].is_negative_one()) {
2061 inst
->opcode
= BRW_OPCODE_MOV
;
2062 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2063 inst
->src
[1] = reg_undef
;
2069 if (inst
->src
[1].is_zero()) {
2070 inst
->opcode
= BRW_OPCODE_MOV
;
2071 inst
->src
[0] = inst
->src
[1];
2072 inst
->src
[1] = reg_undef
;
2077 if (inst
->src
[0].file
== IMM
) {
2078 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2079 inst
->opcode
= BRW_OPCODE_MOV
;
2080 inst
->src
[0].f
*= inst
->src
[1].f
;
2081 inst
->src
[1] = reg_undef
;
2086 case BRW_OPCODE_ADD
:
2087 if (inst
->src
[1].file
!= IMM
)
2091 if (inst
->src
[1].is_zero()) {
2092 inst
->opcode
= BRW_OPCODE_MOV
;
2093 inst
->src
[1] = reg_undef
;
2098 if (inst
->src
[0].file
== IMM
) {
2099 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2100 inst
->opcode
= BRW_OPCODE_MOV
;
2101 inst
->src
[0].f
+= inst
->src
[1].f
;
2102 inst
->src
[1] = reg_undef
;
2108 if (inst
->src
[0].equals(inst
->src
[1])) {
2109 inst
->opcode
= BRW_OPCODE_MOV
;
2110 inst
->src
[1] = reg_undef
;
2115 case BRW_OPCODE_LRP
:
2116 if (inst
->src
[1].equals(inst
->src
[2])) {
2117 inst
->opcode
= BRW_OPCODE_MOV
;
2118 inst
->src
[0] = inst
->src
[1];
2119 inst
->src
[1] = reg_undef
;
2120 inst
->src
[2] = reg_undef
;
2125 case BRW_OPCODE_CMP
:
2126 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2128 inst
->src
[0].negate
&&
2129 inst
->src
[1].is_zero()) {
2130 inst
->src
[0].abs
= false;
2131 inst
->src
[0].negate
= false;
2132 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2137 case BRW_OPCODE_SEL
:
2138 if (inst
->src
[0].equals(inst
->src
[1])) {
2139 inst
->opcode
= BRW_OPCODE_MOV
;
2140 inst
->src
[1] = reg_undef
;
2141 inst
->predicate
= BRW_PREDICATE_NONE
;
2142 inst
->predicate_inverse
= false;
2144 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2145 switch (inst
->conditional_mod
) {
2146 case BRW_CONDITIONAL_LE
:
2147 case BRW_CONDITIONAL_L
:
2148 switch (inst
->src
[1].type
) {
2149 case BRW_REGISTER_TYPE_F
:
2150 if (inst
->src
[1].f
>= 1.0f
) {
2151 inst
->opcode
= BRW_OPCODE_MOV
;
2152 inst
->src
[1] = reg_undef
;
2153 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2161 case BRW_CONDITIONAL_GE
:
2162 case BRW_CONDITIONAL_G
:
2163 switch (inst
->src
[1].type
) {
2164 case BRW_REGISTER_TYPE_F
:
2165 if (inst
->src
[1].f
<= 0.0f
) {
2166 inst
->opcode
= BRW_OPCODE_MOV
;
2167 inst
->src
[1] = reg_undef
;
2168 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2180 case BRW_OPCODE_MAD
:
2181 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2182 inst
->opcode
= BRW_OPCODE_MOV
;
2183 inst
->src
[1] = reg_undef
;
2184 inst
->src
[2] = reg_undef
;
2186 } else if (inst
->src
[0].is_zero()) {
2187 inst
->opcode
= BRW_OPCODE_MUL
;
2188 inst
->src
[0] = inst
->src
[2];
2189 inst
->src
[2] = reg_undef
;
2191 } else if (inst
->src
[1].is_one()) {
2192 inst
->opcode
= BRW_OPCODE_ADD
;
2193 inst
->src
[1] = inst
->src
[2];
2194 inst
->src
[2] = reg_undef
;
2196 } else if (inst
->src
[2].is_one()) {
2197 inst
->opcode
= BRW_OPCODE_ADD
;
2198 inst
->src
[2] = reg_undef
;
2200 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2201 inst
->opcode
= BRW_OPCODE_ADD
;
2202 inst
->src
[1].f
*= inst
->src
[2].f
;
2203 inst
->src
[2] = reg_undef
;
2207 case SHADER_OPCODE_RCP
: {
2208 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2209 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2210 if (inst
->src
[0].equals(prev
->dst
)) {
2211 inst
->opcode
= SHADER_OPCODE_RSQ
;
2212 inst
->src
[0] = prev
->src
[0];
2218 case SHADER_OPCODE_BROADCAST
:
2219 if (is_uniform(inst
->src
[0])) {
2220 inst
->opcode
= BRW_OPCODE_MOV
;
2222 inst
->force_writemask_all
= true;
2224 } else if (inst
->src
[1].file
== IMM
) {
2225 inst
->opcode
= BRW_OPCODE_MOV
;
2226 inst
->src
[0] = component(inst
->src
[0],
2229 inst
->force_writemask_all
= true;
2238 /* Swap if src[0] is immediate. */
2239 if (progress
&& inst
->is_commutative()) {
2240 if (inst
->src
[0].file
== IMM
) {
2241 fs_reg tmp
= inst
->src
[1];
2242 inst
->src
[1] = inst
->src
[0];
2251 * Optimize sample messages that have constant zero values for the trailing
2252 * texture coordinates. We can just reduce the message length for these
2253 * instructions instead of reserving a register for it. Trailing parameters
2254 * that aren't sent default to zero anyway. This will cause the dead code
2255 * eliminator to remove the MOV instruction that would otherwise be emitted to
2256 * set up the zero value.
2259 fs_visitor::opt_zero_samples()
2261 /* Gen4 infers the texturing opcode based on the message length so we can't
2264 if (devinfo
->gen
< 5)
2267 bool progress
= false;
2269 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2270 if (!inst
->is_tex())
2273 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2275 if (load_payload
->is_head_sentinel() ||
2276 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2279 /* We don't want to remove the message header or the first parameter.
2280 * Removing the first parameter is not allowed, see the Haswell PRM
2281 * volume 7, page 149:
2283 * "Parameter 0 is required except for the sampleinfo message, which
2284 * has no parameter 0"
2286 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2287 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2288 (inst
->exec_size
/ 8) +
2289 inst
->header_size
- 1].is_zero()) {
2290 inst
->mlen
-= inst
->exec_size
/ 8;
2296 invalidate_live_intervals();
2302 * Optimize sample messages which are followed by the final RT write.
2304 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2305 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2306 * final texturing results copied to the framebuffer write payload and modify
2307 * them to write to the framebuffer directly.
2310 fs_visitor::opt_sampler_eot()
2312 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2314 if (stage
!= MESA_SHADER_FRAGMENT
)
2317 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2320 /* FINISHME: It should be possible to implement this optimization when there
2321 * are multiple drawbuffers.
2323 if (key
->nr_color_regions
!= 1)
2326 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2327 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2328 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2329 assert(fb_write
->eot
);
2330 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2332 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2334 /* There wasn't one; nothing to do. */
2335 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2338 /* 3D Sampler » Messages » Message Format
2340 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2341 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2343 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2344 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2345 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2346 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2347 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2350 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2351 * It's very likely to be the previous instruction.
2353 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2354 if (load_payload
->is_head_sentinel() ||
2355 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2358 assert(!tex_inst
->eot
); /* We can't get here twice */
2359 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2361 const fs_builder
ibld(this, block
, tex_inst
);
2363 tex_inst
->offset
|= fb_write
->target
<< 24;
2364 tex_inst
->eot
= true;
2365 tex_inst
->dst
= ibld
.null_reg_ud();
2366 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2368 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2369 * to create a new LOAD_PAYLOAD command with the same sources and a space
2370 * saved for the header. Using a new destination register not only makes sure
2371 * we have enough space, but it will make sure the dead code eliminator kills
2372 * the instruction that this will replace.
2374 if (tex_inst
->header_size
!= 0)
2377 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2378 load_payload
->sources
+ 1);
2379 fs_reg
*new_sources
=
2380 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2382 new_sources
[0] = fs_reg();
2383 for (int i
= 0; i
< load_payload
->sources
; i
++)
2384 new_sources
[i
+1] = load_payload
->src
[i
];
2386 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2387 * requires a lot of information about the sources to appropriately figure
2388 * out the number of registers needed to be used. Given this stage in our
2389 * optimization, we may not have the appropriate GRFs required by
2390 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2391 * manually emit the instruction.
2393 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2394 load_payload
->exec_size
,
2397 load_payload
->sources
+ 1);
2399 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2400 new_load_payload
->header_size
= 1;
2402 tex_inst
->header_size
= 1;
2403 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2404 tex_inst
->src
[0] = send_header
;
2410 fs_visitor::opt_register_renaming()
2412 bool progress
= false;
2415 int remap
[alloc
.count
];
2416 memset(remap
, -1, sizeof(int) * alloc
.count
);
2418 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2419 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2421 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2422 inst
->opcode
== BRW_OPCODE_WHILE
) {
2426 /* Rewrite instruction sources. */
2427 for (int i
= 0; i
< inst
->sources
; i
++) {
2428 if (inst
->src
[i
].file
== VGRF
&&
2429 remap
[inst
->src
[i
].nr
] != -1 &&
2430 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2431 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2436 const int dst
= inst
->dst
.nr
;
2439 inst
->dst
.file
== VGRF
&&
2440 alloc
.sizes
[inst
->dst
.nr
] == inst
->exec_size
/ 8 &&
2441 !inst
->is_partial_write()) {
2442 if (remap
[dst
] == -1) {
2445 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2446 inst
->dst
.nr
= remap
[dst
];
2449 } else if (inst
->dst
.file
== VGRF
&&
2451 remap
[dst
] != dst
) {
2452 inst
->dst
.nr
= remap
[dst
];
2458 invalidate_live_intervals();
2460 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2461 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2462 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2471 * Remove redundant or useless discard jumps.
2473 * For example, we can eliminate jumps in the following sequence:
2475 * discard-jump (redundant with the next jump)
2476 * discard-jump (useless; jumps to the next instruction)
2480 fs_visitor::opt_redundant_discard_jumps()
2482 bool progress
= false;
2484 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2486 fs_inst
*placeholder_halt
= NULL
;
2487 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2488 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2489 placeholder_halt
= inst
;
2494 if (!placeholder_halt
)
2497 /* Delete any HALTs immediately before the placeholder halt. */
2498 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2499 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2500 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2501 prev
->remove(last_bblock
);
2506 invalidate_live_intervals();
2512 fs_visitor::compute_to_mrf()
2514 bool progress
= false;
2517 /* No MRFs on Gen >= 7. */
2518 if (devinfo
->gen
>= 7)
2521 calculate_live_intervals();
2523 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2527 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2528 inst
->is_partial_write() ||
2529 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2530 inst
->dst
.type
!= inst
->src
[0].type
||
2531 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2532 !inst
->src
[0].is_contiguous() ||
2533 inst
->src
[0].subreg_offset
)
2536 /* Work out which hardware MRF registers are written by this
2539 int mrf_low
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2541 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2542 mrf_high
= mrf_low
+ 4;
2543 } else if (inst
->exec_size
== 16) {
2544 mrf_high
= mrf_low
+ 1;
2549 /* Can't compute-to-MRF this GRF if someone else was going to
2552 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2555 /* Found a move of a GRF to a MRF. Let's see if we can go
2556 * rewrite the thing that made this GRF to write into the MRF.
2558 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2559 if (scan_inst
->dst
.file
== VGRF
&&
2560 scan_inst
->dst
.nr
== inst
->src
[0].nr
) {
2561 /* Found the last thing to write our reg we want to turn
2562 * into a compute-to-MRF.
2565 /* If this one instruction didn't populate all the
2566 * channels, bail. We might be able to rewrite everything
2567 * that writes that reg, but it would require smarter
2568 * tracking to delay the rewriting until complete success.
2570 if (scan_inst
->is_partial_write())
2573 /* Things returning more than one register would need us to
2574 * understand coalescing out more than one MOV at a time.
2576 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2579 /* SEND instructions can't have MRF as a destination. */
2580 if (scan_inst
->mlen
)
2583 if (devinfo
->gen
== 6) {
2584 /* gen6 math instructions must have the destination be
2585 * GRF, so no compute-to-MRF for them.
2587 if (scan_inst
->is_math()) {
2592 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2593 /* Found the creator of our MRF's source value. */
2594 scan_inst
->dst
.file
= MRF
;
2595 scan_inst
->dst
.nr
= inst
->dst
.nr
;
2596 scan_inst
->saturate
|= inst
->saturate
;
2597 inst
->remove(block
);
2603 /* We don't handle control flow here. Most computation of
2604 * values that end up in MRFs are shortly before the MRF
2607 if (block
->start() == scan_inst
)
2610 /* You can't read from an MRF, so if someone else reads our
2611 * MRF's source GRF that we wanted to rewrite, that stops us.
2613 bool interfered
= false;
2614 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2615 if (scan_inst
->src
[i
].file
== VGRF
&&
2616 scan_inst
->src
[i
].nr
== inst
->src
[0].nr
&&
2617 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2624 if (scan_inst
->dst
.file
== MRF
) {
2625 /* If somebody else writes our MRF here, we can't
2626 * compute-to-MRF before that.
2628 int scan_mrf_low
= scan_inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2631 if (scan_inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2632 scan_mrf_high
= scan_mrf_low
+ 4;
2633 } else if (scan_inst
->exec_size
== 16) {
2634 scan_mrf_high
= scan_mrf_low
+ 1;
2636 scan_mrf_high
= scan_mrf_low
;
2639 if (mrf_low
== scan_mrf_low
||
2640 mrf_low
== scan_mrf_high
||
2641 mrf_high
== scan_mrf_low
||
2642 mrf_high
== scan_mrf_high
) {
2647 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2648 /* Found a SEND instruction, which means that there are
2649 * live values in MRFs from base_mrf to base_mrf +
2650 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2653 if (mrf_low
>= scan_inst
->base_mrf
&&
2654 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2657 if (mrf_high
>= scan_inst
->base_mrf
&&
2658 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2666 invalidate_live_intervals();
2672 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2673 * flow. We could probably do better here with some form of divergence
2677 fs_visitor::eliminate_find_live_channel()
2679 bool progress
= false;
2682 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2683 switch (inst
->opcode
) {
2689 case BRW_OPCODE_ENDIF
:
2690 case BRW_OPCODE_WHILE
:
2694 case FS_OPCODE_DISCARD_JUMP
:
2695 /* This can potentially make control flow non-uniform until the end
2700 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2702 inst
->opcode
= BRW_OPCODE_MOV
;
2703 inst
->src
[0] = brw_imm_ud(0u);
2705 inst
->force_writemask_all
= true;
2719 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2720 * instructions to FS_OPCODE_REP_FB_WRITE.
2723 fs_visitor::emit_repclear_shader()
2725 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2727 int color_mrf
= base_mrf
+ 2;
2729 fs_inst
*mov
= bld
.exec_all().group(4, 0)
2730 .MOV(brw_message_reg(color_mrf
),
2731 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2734 if (key
->nr_color_regions
== 1) {
2735 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2736 write
->saturate
= key
->clamp_fragment_color
;
2737 write
->base_mrf
= color_mrf
;
2739 write
->header_size
= 0;
2742 assume(key
->nr_color_regions
> 0);
2743 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2744 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2745 write
->saturate
= key
->clamp_fragment_color
;
2746 write
->base_mrf
= base_mrf
;
2748 write
->header_size
= 2;
2756 assign_constant_locations();
2757 assign_curb_setup();
2759 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2760 assert(mov
->src
[0].file
== FIXED_GRF
);
2761 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2765 * Walks through basic blocks, looking for repeated MRF writes and
2766 * removing the later ones.
2769 fs_visitor::remove_duplicate_mrf_writes()
2771 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2772 bool progress
= false;
2774 /* Need to update the MRF tracking for compressed instructions. */
2775 if (dispatch_width
== 16)
2778 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2780 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2781 if (inst
->is_control_flow()) {
2782 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2785 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2786 inst
->dst
.file
== MRF
) {
2787 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2788 if (prev_inst
&& inst
->equals(prev_inst
)) {
2789 inst
->remove(block
);
2795 /* Clear out the last-write records for MRFs that were overwritten. */
2796 if (inst
->dst
.file
== MRF
) {
2797 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2800 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2801 /* Found a SEND instruction, which will include two or fewer
2802 * implied MRF writes. We could do better here.
2804 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2805 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2809 /* Clear out any MRF move records whose sources got overwritten. */
2810 if (inst
->dst
.file
== VGRF
) {
2811 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2812 if (last_mrf_move
[i
] &&
2813 last_mrf_move
[i
]->src
[0].nr
== inst
->dst
.nr
) {
2814 last_mrf_move
[i
] = NULL
;
2819 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2820 inst
->dst
.file
== MRF
&&
2821 inst
->src
[0].file
== VGRF
&&
2822 !inst
->is_partial_write()) {
2823 last_mrf_move
[inst
->dst
.nr
] = inst
;
2828 invalidate_live_intervals();
2834 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2836 /* Clear the flag for registers that actually got read (as expected). */
2837 for (int i
= 0; i
< inst
->sources
; i
++) {
2839 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
2840 grf
= inst
->src
[i
].nr
;
2845 if (grf
>= first_grf
&&
2846 grf
< first_grf
+ grf_len
) {
2847 deps
[grf
- first_grf
] = false;
2848 if (inst
->exec_size
== 16)
2849 deps
[grf
- first_grf
+ 1] = false;
2855 * Implements this workaround for the original 965:
2857 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2858 * check for post destination dependencies on this instruction, software
2859 * must ensure that there is no destination hazard for the case of ‘write
2860 * followed by a posted write’ shown in the following example.
2863 * 2. send r3.xy <rest of send instruction>
2866 * Due to no post-destination dependency check on the ‘send’, the above
2867 * code sequence could have two instructions (1 and 2) in flight at the
2868 * same time that both consider ‘r3’ as the target of their final writes.
2871 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2874 int write_len
= inst
->regs_written
;
2875 int first_write_grf
= inst
->dst
.nr
;
2876 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2877 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2879 memset(needs_dep
, false, sizeof(needs_dep
));
2880 memset(needs_dep
, true, write_len
);
2882 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2884 /* Walk backwards looking for writes to registers we're writing which
2885 * aren't read since being written. If we hit the start of the program,
2886 * we assume that there are no outstanding dependencies on entry to the
2889 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2890 /* If we hit control flow, assume that there *are* outstanding
2891 * dependencies, and force their cleanup before our instruction.
2893 if (block
->start() == scan_inst
) {
2894 for (int i
= 0; i
< write_len
; i
++) {
2896 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
2897 first_write_grf
+ i
);
2902 /* We insert our reads as late as possible on the assumption that any
2903 * instruction but a MOV that might have left us an outstanding
2904 * dependency has more latency than a MOV.
2906 if (scan_inst
->dst
.file
== VGRF
) {
2907 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2908 int reg
= scan_inst
->dst
.nr
+ i
;
2910 if (reg
>= first_write_grf
&&
2911 reg
< first_write_grf
+ write_len
&&
2912 needs_dep
[reg
- first_write_grf
]) {
2913 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
2914 needs_dep
[reg
- first_write_grf
] = false;
2915 if (scan_inst
->exec_size
== 16)
2916 needs_dep
[reg
- first_write_grf
+ 1] = false;
2921 /* Clear the flag for registers that actually got read (as expected). */
2922 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2924 /* Continue the loop only if we haven't resolved all the dependencies */
2926 for (i
= 0; i
< write_len
; i
++) {
2936 * Implements this workaround for the original 965:
2938 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2939 * used as a destination register until after it has been sourced by an
2940 * instruction with a different destination register.
2943 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2945 int write_len
= inst
->regs_written
;
2946 int first_write_grf
= inst
->dst
.nr
;
2947 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2948 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2950 memset(needs_dep
, false, sizeof(needs_dep
));
2951 memset(needs_dep
, true, write_len
);
2952 /* Walk forwards looking for writes to registers we're writing which aren't
2953 * read before being written.
2955 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
2956 /* If we hit control flow, force resolve all remaining dependencies. */
2957 if (block
->end() == scan_inst
) {
2958 for (int i
= 0; i
< write_len
; i
++) {
2960 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2961 first_write_grf
+ i
);
2966 /* Clear the flag for registers that actually got read (as expected). */
2967 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2969 /* We insert our reads as late as possible since they're reading the
2970 * result of a SEND, which has massive latency.
2972 if (scan_inst
->dst
.file
== VGRF
&&
2973 scan_inst
->dst
.nr
>= first_write_grf
&&
2974 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
2975 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
2976 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2978 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
2981 /* Continue the loop only if we haven't resolved all the dependencies */
2983 for (i
= 0; i
< write_len
; i
++) {
2993 fs_visitor::insert_gen4_send_dependency_workarounds()
2995 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
2998 bool progress
= false;
3000 /* Note that we're done with register allocation, so GRF fs_regs always
3001 * have a .reg_offset of 0.
3004 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3005 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3006 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3007 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3013 invalidate_live_intervals();
3017 * Turns the generic expression-style uniform pull constant load instruction
3018 * into a hardware-specific series of instructions for loading a pull
3021 * The expression style allows the CSE pass before this to optimize out
3022 * repeated loads from the same offset, and gives the pre-register-allocation
3023 * scheduling full flexibility, while the conversion to native instructions
3024 * allows the post-register-allocation scheduler the best information
3027 * Note that execution masking for setting up pull constant loads is special:
3028 * the channels that need to be written are unrelated to the current execution
3029 * mask, since a later instruction will use one of the result channels as a
3030 * source operand for all 8 or 16 of its channels.
3033 fs_visitor::lower_uniform_pull_constant_loads()
3035 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3036 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3039 if (devinfo
->gen
>= 7) {
3040 /* The offset arg before was a vec4-aligned byte offset. We need to
3041 * turn it into a dword offset.
3043 fs_reg const_offset_reg
= inst
->src
[1];
3044 assert(const_offset_reg
.file
== IMM
&&
3045 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3046 const_offset_reg
.ud
/= 4;
3048 fs_reg payload
, offset
;
3049 if (devinfo
->gen
>= 9) {
3050 /* We have to use a message header on Skylake to get SIMD4x2
3051 * mode. Reserve space for the register.
3053 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3054 offset
.reg_offset
++;
3057 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3061 /* This is actually going to be a MOV, but since only the first dword
3062 * is accessed, we have a special opcode to do just that one. Note
3063 * that this needs to be an operation that will be considered a def
3064 * by live variable analysis, or register allocation will explode.
3066 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3067 8, offset
, const_offset_reg
);
3068 setup
->force_writemask_all
= true;
3070 setup
->ir
= inst
->ir
;
3071 setup
->annotation
= inst
->annotation
;
3072 inst
->insert_before(block
, setup
);
3074 /* Similarly, this will only populate the first 4 channels of the
3075 * result register (since we only use smear values from 0-3), but we
3076 * don't tell the optimizer.
3078 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3079 inst
->src
[1] = payload
;
3080 inst
->base_mrf
= -1;
3082 invalidate_live_intervals();
3084 /* Before register allocation, we didn't tell the scheduler about the
3085 * MRF we use. We know it's safe to use this MRF because nothing
3086 * else does except for register spill/unspill, which generates and
3087 * uses its MRF within a single IR instruction.
3089 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3096 fs_visitor::lower_load_payload()
3098 bool progress
= false;
3100 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3101 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3104 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3105 assert(inst
->saturate
== false);
3106 fs_reg dst
= inst
->dst
;
3108 /* Get rid of COMPR4. We'll add it back in if we need it */
3109 if (dst
.file
== MRF
)
3110 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3112 const fs_builder
ibld(this, block
, inst
);
3113 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3115 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3116 if (inst
->src
[i
].file
!= BAD_FILE
) {
3117 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3118 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3119 hbld
.MOV(mov_dst
, mov_src
);
3121 dst
= offset(dst
, hbld
, 1);
3124 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3125 inst
->exec_size
> 8) {
3126 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3127 * a straightforward copy. Instead, the result of the
3128 * LOAD_PAYLOAD is treated as interleaved and the first four
3129 * non-header sources are unpacked as:
3140 * This is used for gen <= 5 fb writes.
3142 assert(inst
->exec_size
== 16);
3143 assert(inst
->header_size
+ 4 <= inst
->sources
);
3144 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3145 if (inst
->src
[i
].file
!= BAD_FILE
) {
3146 if (devinfo
->has_compr4
) {
3147 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3148 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3149 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3151 /* Platform doesn't have COMPR4. We have to fake it */
3152 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3153 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3155 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3162 /* The loop above only ever incremented us through the first set
3163 * of 4 registers. However, thanks to the magic of COMPR4, we
3164 * actually wrote to the first 8 registers, so we need to take
3165 * that into account now.
3169 /* The COMPR4 code took care of the first 4 sources. We'll let
3170 * the regular path handle any remaining sources. Yes, we are
3171 * modifying the instruction but we're about to delete it so
3172 * this really doesn't hurt anything.
3174 inst
->header_size
+= 4;
3177 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3178 if (inst
->src
[i
].file
!= BAD_FILE
)
3179 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3180 dst
= offset(dst
, ibld
, 1);
3183 inst
->remove(block
);
3188 invalidate_live_intervals();
3194 fs_visitor::lower_integer_multiplication()
3196 bool progress
= false;
3198 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3199 const fs_builder
ibld(this, block
, inst
);
3201 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3202 if (inst
->dst
.is_accumulator() ||
3203 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3204 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3207 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3208 * operation directly, but CHV/BXT cannot.
3210 if (devinfo
->gen
>= 8 &&
3211 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3214 if (inst
->src
[1].file
== IMM
&&
3215 inst
->src
[1].ud
< (1 << 16)) {
3216 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3217 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3220 * If multiplying by an immediate value that fits in 16-bits, do a
3221 * single MUL instruction with that value in the proper location.
3223 if (devinfo
->gen
< 7) {
3224 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3226 ibld
.MOV(imm
, inst
->src
[1]);
3227 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3229 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3232 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3233 * do 32-bit integer multiplication in one instruction, but instead
3234 * must do a sequence (which actually calculates a 64-bit result):
3236 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3237 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3238 * mov(8) g2<1>D acc0<8,8,1>D
3240 * But on Gen > 6, the ability to use second accumulator register
3241 * (acc1) for non-float data types was removed, preventing a simple
3242 * implementation in SIMD16. A 16-channel result can be calculated by
3243 * executing the three instructions twice in SIMD8, once with quarter
3244 * control of 1Q for the first eight channels and again with 2Q for
3245 * the second eight channels.
3247 * Which accumulator register is implicitly accessed (by AccWrEnable
3248 * for instance) is determined by the quarter control. Unfortunately
3249 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3250 * implicit accumulator access by an instruction with 2Q will access
3251 * acc1 regardless of whether the data type is usable in acc1.
3253 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3254 * integer data types.
3256 * Since we only want the low 32-bits of the result, we can do two
3257 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3258 * adjust the high result and add them (like the mach is doing):
3260 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3261 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3262 * shl(8) g9<1>D g8<8,8,1>D 16D
3263 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3265 * We avoid the shl instruction by realizing that we only want to add
3266 * the low 16-bits of the "high" result to the high 16-bits of the
3267 * "low" result and using proper regioning on the add:
3269 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3270 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3271 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3273 * Since it does not use the (single) accumulator register, we can
3274 * schedule multi-component multiplications much better.
3277 fs_reg orig_dst
= inst
->dst
;
3278 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3279 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3282 fs_reg low
= inst
->dst
;
3283 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3286 if (devinfo
->gen
>= 7) {
3287 fs_reg src1_0_w
= inst
->src
[1];
3288 fs_reg src1_1_w
= inst
->src
[1];
3290 if (inst
->src
[1].file
== IMM
) {
3291 src1_0_w
.ud
&= 0xffff;
3294 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3295 if (src1_0_w
.stride
!= 0) {
3296 assert(src1_0_w
.stride
== 1);
3297 src1_0_w
.stride
= 2;
3300 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3301 if (src1_1_w
.stride
!= 0) {
3302 assert(src1_1_w
.stride
== 1);
3303 src1_1_w
.stride
= 2;
3305 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3307 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3308 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3310 fs_reg src0_0_w
= inst
->src
[0];
3311 fs_reg src0_1_w
= inst
->src
[0];
3313 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3314 if (src0_0_w
.stride
!= 0) {
3315 assert(src0_0_w
.stride
== 1);
3316 src0_0_w
.stride
= 2;
3319 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3320 if (src0_1_w
.stride
!= 0) {
3321 assert(src0_1_w
.stride
== 1);
3322 src0_1_w
.stride
= 2;
3324 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3326 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3327 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3330 fs_reg dst
= inst
->dst
;
3331 dst
.type
= BRW_REGISTER_TYPE_UW
;
3332 dst
.subreg_offset
= 2;
3335 high
.type
= BRW_REGISTER_TYPE_UW
;
3338 low
.type
= BRW_REGISTER_TYPE_UW
;
3339 low
.subreg_offset
= 2;
3342 ibld
.ADD(dst
, low
, high
);
3344 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3345 set_condmod(inst
->conditional_mod
,
3346 ibld
.MOV(orig_dst
, inst
->dst
));
3350 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3351 /* Should have been lowered to 8-wide. */
3352 assert(inst
->exec_size
<= 8);
3353 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3355 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3356 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3358 if (devinfo
->gen
>= 8) {
3359 /* Until Gen8, integer multiplies read 32-bits from one source,
3360 * and 16-bits from the other, and relying on the MACH instruction
3361 * to generate the high bits of the result.
3363 * On Gen8, the multiply instruction does a full 32x32-bit
3364 * multiply, but in order to do a 64-bit multiply we can simulate
3365 * the previous behavior and then use a MACH instruction.
3367 * FINISHME: Don't use source modifiers on src1.
3369 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3370 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3371 mul
->src
[1].type
= (type_is_signed(mul
->src
[1].type
) ?
3372 BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
3373 mul
->src
[1].stride
*= 2;
3375 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3376 inst
->force_sechalf
) {
3377 /* Among other things the quarter control bits influence which
3378 * accumulator register is used by the hardware for instructions
3379 * that access the accumulator implicitly (e.g. MACH). A
3380 * second-half instruction would normally map to acc1, which
3381 * doesn't exist on Gen7 and up (the hardware does emulate it for
3382 * floating-point instructions *only* by taking advantage of the
3383 * extra precision of acc0 not normally used for floating point
3386 * HSW and up are careful enough not to try to access an
3387 * accumulator register that doesn't exist, but on earlier Gen7
3388 * hardware we need to make sure that the quarter control bits are
3389 * zero to avoid non-deterministic behaviour and emit an extra MOV
3390 * to get the result masked correctly according to the current
3393 mach
->force_sechalf
= false;
3394 mach
->force_writemask_all
= true;
3395 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3396 ibld
.MOV(inst
->dst
, mach
->dst
);
3402 inst
->remove(block
);
3407 invalidate_live_intervals();
3413 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3414 fs_reg
*dst
, fs_reg color
, unsigned components
)
3416 if (key
->clamp_fragment_color
) {
3417 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3418 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3420 for (unsigned i
= 0; i
< components
; i
++)
3422 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3427 for (unsigned i
= 0; i
< components
; i
++)
3428 dst
[i
] = offset(color
, bld
, i
);
3432 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3433 const brw_wm_prog_data
*prog_data
,
3434 const brw_wm_prog_key
*key
,
3435 const fs_visitor::thread_payload
&payload
)
3437 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3438 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3439 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3440 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3441 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3442 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3443 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3444 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3445 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3446 const unsigned components
=
3447 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3449 /* We can potentially have a message length of up to 15, so we have to set
3450 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3453 int header_size
= 2, payload_header_size
;
3454 unsigned length
= 0;
3456 /* From the Sandy Bridge PRM, volume 4, page 198:
3458 * "Dispatched Pixel Enables. One bit per pixel indicating
3459 * which pixels were originally enabled when the thread was
3460 * dispatched. This field is only required for the end-of-
3461 * thread message and on all dual-source messages."
3463 if (devinfo
->gen
>= 6 &&
3464 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3465 color1
.file
== BAD_FILE
&&
3466 key
->nr_color_regions
== 1) {
3470 if (header_size
!= 0) {
3471 assert(header_size
== 2);
3472 /* Allocate 2 registers for a header */
3476 if (payload
.aa_dest_stencil_reg
) {
3477 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3478 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3479 .MOV(sources
[length
],
3480 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3484 if (prog_data
->uses_omask
) {
3485 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3486 BRW_REGISTER_TYPE_UD
);
3488 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3489 * relevant. Since it's unsigned single words one vgrf is always
3490 * 16-wide, but only the lower or higher 8 channels will be used by the
3491 * hardware when doing a SIMD8 write depending on whether we have
3492 * selected the subspans for the first or second half respectively.
3494 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3495 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3496 sample_mask
.stride
*= 2;
3498 bld
.exec_all().annotate("FB write oMask")
3499 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3500 inst
->force_sechalf
),
3505 payload_header_size
= length
;
3507 if (src0_alpha
.file
!= BAD_FILE
) {
3508 /* FIXME: This is being passed at the wrong location in the payload and
3509 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3510 * It's supposed to be immediately before oMask but there seems to be no
3511 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3512 * requires header sources to form a contiguous segment at the beginning
3513 * of the message and src0_alpha has per-channel semantics.
3515 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3519 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3522 if (color1
.file
!= BAD_FILE
) {
3523 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3527 if (src_depth
.file
!= BAD_FILE
) {
3528 sources
[length
] = src_depth
;
3532 if (dst_depth
.file
!= BAD_FILE
) {
3533 sources
[length
] = dst_depth
;
3537 if (src_stencil
.file
!= BAD_FILE
) {
3538 assert(devinfo
->gen
>= 9);
3539 assert(bld
.dispatch_width() != 16);
3541 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3542 * available on gen9+. As such it's impossible to have both enabled at the
3543 * same time and therefore length cannot overrun the array.
3545 assert(length
< 15);
3547 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3548 bld
.exec_all().annotate("FB write OS")
3549 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3550 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3555 if (devinfo
->gen
>= 7) {
3556 /* Send from the GRF */
3557 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3558 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3559 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3560 load
->dst
= payload
;
3562 inst
->src
[0] = payload
;
3563 inst
->resize_sources(1);
3564 inst
->base_mrf
= -1;
3566 /* Send from the MRF */
3567 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3568 sources
, length
, payload_header_size
);
3570 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3571 * will do this for us if we just give it a COMPR4 destination.
3573 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3574 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3576 inst
->resize_sources(0);
3580 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3581 inst
->mlen
= load
->regs_written
;
3582 inst
->header_size
= header_size
;
3586 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3587 const fs_reg
&coordinate
,
3588 const fs_reg
&shadow_c
,
3589 const fs_reg
&lod
, const fs_reg
&lod2
,
3590 const fs_reg
&sampler
,
3591 unsigned coord_components
,
3592 unsigned grad_components
)
3594 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3595 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3596 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3597 fs_reg msg_end
= msg_begin
;
3600 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3602 for (unsigned i
= 0; i
< coord_components
; i
++)
3603 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3604 offset(coordinate
, bld
, i
));
3606 msg_end
= offset(msg_end
, bld
, coord_components
);
3608 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3609 * require all three components to be present and zero if they are unused.
3611 if (coord_components
> 0 &&
3612 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3613 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3614 for (unsigned i
= coord_components
; i
< 3; i
++)
3615 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3617 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3620 if (op
== SHADER_OPCODE_TXD
) {
3621 /* TXD unsupported in SIMD16 mode. */
3622 assert(bld
.dispatch_width() == 8);
3624 /* the slots for u and v are always present, but r is optional */
3625 if (coord_components
< 2)
3626 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3629 * dPdx = dudx, dvdx, drdx
3630 * dPdy = dudy, dvdy, drdy
3632 * 1-arg: Does not exist.
3634 * 2-arg: dudx dvdx dudy dvdy
3635 * dPdx.x dPdx.y dPdy.x dPdy.y
3638 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3639 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3640 * m5 m6 m7 m8 m9 m10
3642 for (unsigned i
= 0; i
< grad_components
; i
++)
3643 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3645 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3647 for (unsigned i
= 0; i
< grad_components
; i
++)
3648 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3650 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3654 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3655 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3657 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3658 bld
.dispatch_width() == 16);
3660 const brw_reg_type type
=
3661 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3662 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3663 bld
.MOV(retype(msg_end
, type
), lod
);
3664 msg_end
= offset(msg_end
, bld
, 1);
3667 if (shadow_c
.file
!= BAD_FILE
) {
3668 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3669 /* There's no plain shadow compare message, so we use shadow
3670 * compare with a bias of 0.0.
3672 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3673 msg_end
= offset(msg_end
, bld
, 1);
3676 bld
.MOV(msg_end
, shadow_c
);
3677 msg_end
= offset(msg_end
, bld
, 1);
3681 inst
->src
[0] = reg_undef
;
3682 inst
->src
[1] = sampler
;
3683 inst
->resize_sources(2);
3684 inst
->base_mrf
= msg_begin
.nr
;
3685 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3686 inst
->header_size
= 1;
3690 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3692 const fs_reg
&shadow_c
,
3693 fs_reg lod
, fs_reg lod2
,
3694 const fs_reg
&sample_index
,
3695 const fs_reg
&sampler
,
3696 const fs_reg
&offset_value
,
3697 unsigned coord_components
,
3698 unsigned grad_components
)
3700 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3701 fs_reg msg_coords
= message
;
3702 unsigned header_size
= 0;
3704 if (offset_value
.file
!= BAD_FILE
) {
3705 /* The offsets set up by the visitor are in the m1 header, so we can't
3712 for (unsigned i
= 0; i
< coord_components
; i
++) {
3713 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3714 coordinate
= offset(coordinate
, bld
, 1);
3716 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3717 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3719 if (shadow_c
.file
!= BAD_FILE
) {
3720 fs_reg msg_shadow
= msg_lod
;
3721 bld
.MOV(msg_shadow
, shadow_c
);
3722 msg_lod
= offset(msg_shadow
, bld
, 1);
3727 case SHADER_OPCODE_TXL
:
3729 bld
.MOV(msg_lod
, lod
);
3730 msg_end
= offset(msg_lod
, bld
, 1);
3732 case SHADER_OPCODE_TXD
:
3735 * dPdx = dudx, dvdx, drdx
3736 * dPdy = dudy, dvdy, drdy
3738 * Load up these values:
3739 * - dudx dudy dvdx dvdy drdx drdy
3740 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3743 for (unsigned i
= 0; i
< grad_components
; i
++) {
3744 bld
.MOV(msg_end
, lod
);
3745 lod
= offset(lod
, bld
, 1);
3746 msg_end
= offset(msg_end
, bld
, 1);
3748 bld
.MOV(msg_end
, lod2
);
3749 lod2
= offset(lod2
, bld
, 1);
3750 msg_end
= offset(msg_end
, bld
, 1);
3753 case SHADER_OPCODE_TXS
:
3754 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3755 bld
.MOV(msg_lod
, lod
);
3756 msg_end
= offset(msg_lod
, bld
, 1);
3758 case SHADER_OPCODE_TXF
:
3759 msg_lod
= offset(msg_coords
, bld
, 3);
3760 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3761 msg_end
= offset(msg_lod
, bld
, 1);
3763 case SHADER_OPCODE_TXF_CMS
:
3764 msg_lod
= offset(msg_coords
, bld
, 3);
3766 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3768 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3769 msg_end
= offset(msg_lod
, bld
, 2);
3776 inst
->src
[0] = reg_undef
;
3777 inst
->src
[1] = sampler
;
3778 inst
->resize_sources(2);
3779 inst
->base_mrf
= message
.nr
;
3780 inst
->mlen
= msg_end
.nr
- message
.nr
;
3781 inst
->header_size
= header_size
;
3783 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3784 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3788 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3790 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3793 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
3797 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3799 const fs_reg
&shadow_c
,
3800 fs_reg lod
, fs_reg lod2
,
3801 const fs_reg
&sample_index
,
3802 const fs_reg
&mcs
, const fs_reg
&sampler
,
3803 fs_reg offset_value
,
3804 unsigned coord_components
,
3805 unsigned grad_components
)
3807 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3808 int reg_width
= bld
.dispatch_width() / 8;
3809 unsigned header_size
= 0, length
= 0;
3810 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3811 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3812 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3814 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3815 offset_value
.file
!= BAD_FILE
||
3816 is_high_sampler(devinfo
, sampler
)) {
3817 /* For general texture offsets (no txf workaround), we need a header to
3818 * put them in. Note that we're only reserving space for it in the
3819 * message payload as it will be initialized implicitly by the
3822 * TG4 needs to place its channel select in the header, for interaction
3823 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3824 * larger sampler numbers we need to offset the Sampler State Pointer in
3828 sources
[0] = fs_reg();
3832 if (shadow_c
.file
!= BAD_FILE
) {
3833 bld
.MOV(sources
[length
], shadow_c
);
3837 bool coordinate_done
= false;
3839 /* The sampler can only meaningfully compute LOD for fragment shader
3840 * messages. For all other stages, we change the opcode to TXL and
3841 * hardcode the LOD to 0.
3843 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3844 op
== SHADER_OPCODE_TEX
) {
3845 op
= SHADER_OPCODE_TXL
;
3846 lod
= brw_imm_f(0.0f
);
3849 /* Set up the LOD info */
3852 case SHADER_OPCODE_TXL
:
3853 bld
.MOV(sources
[length
], lod
);
3856 case SHADER_OPCODE_TXD
:
3857 /* TXD should have been lowered in SIMD16 mode. */
3858 assert(bld
.dispatch_width() == 8);
3860 /* Load dPdx and the coordinate together:
3861 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3863 for (unsigned i
= 0; i
< coord_components
; i
++) {
3864 bld
.MOV(sources
[length
], coordinate
);
3865 coordinate
= offset(coordinate
, bld
, 1);
3868 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3869 * only derivatives for (u, v, r).
3871 if (i
< grad_components
) {
3872 bld
.MOV(sources
[length
], lod
);
3873 lod
= offset(lod
, bld
, 1);
3876 bld
.MOV(sources
[length
], lod2
);
3877 lod2
= offset(lod2
, bld
, 1);
3882 coordinate_done
= true;
3884 case SHADER_OPCODE_TXS
:
3885 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3888 case SHADER_OPCODE_TXF
:
3889 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3890 * On Gen9 they are u, v, lod, r
3892 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3893 coordinate
= offset(coordinate
, bld
, 1);
3896 if (devinfo
->gen
>= 9) {
3897 if (coord_components
>= 2) {
3898 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3899 coordinate
= offset(coordinate
, bld
, 1);
3904 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
3907 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
3908 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3909 coordinate
= offset(coordinate
, bld
, 1);
3913 coordinate_done
= true;
3915 case SHADER_OPCODE_TXF_CMS
:
3916 case SHADER_OPCODE_TXF_CMS_W
:
3917 case SHADER_OPCODE_TXF_UMS
:
3918 case SHADER_OPCODE_TXF_MCS
:
3919 if (op
== SHADER_OPCODE_TXF_UMS
||
3920 op
== SHADER_OPCODE_TXF_CMS
||
3921 op
== SHADER_OPCODE_TXF_CMS_W
) {
3922 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
3926 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
3927 /* Data from the multisample control surface. */
3928 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
3931 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
3934 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
3935 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
3938 offset(mcs
, bld
, 1));
3943 /* There is no offsetting for this message; just copy in the integer
3944 * texture coordinates.
3946 for (unsigned i
= 0; i
< coord_components
; i
++) {
3947 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3948 coordinate
= offset(coordinate
, bld
, 1);
3952 coordinate_done
= true;
3954 case SHADER_OPCODE_TG4_OFFSET
:
3955 /* gather4_po_c should have been lowered in SIMD16 mode. */
3956 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
3958 /* More crazy intermixing */
3959 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
3960 bld
.MOV(sources
[length
], coordinate
);
3961 coordinate
= offset(coordinate
, bld
, 1);
3965 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
3966 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
3967 offset_value
= offset(offset_value
, bld
, 1);
3971 if (coord_components
== 3) { /* r if present */
3972 bld
.MOV(sources
[length
], coordinate
);
3973 coordinate
= offset(coordinate
, bld
, 1);
3977 coordinate_done
= true;
3983 /* Set up the coordinate (except for cases where it was done above) */
3984 if (!coordinate_done
) {
3985 for (unsigned i
= 0; i
< coord_components
; i
++) {
3986 bld
.MOV(sources
[length
], coordinate
);
3987 coordinate
= offset(coordinate
, bld
, 1);
3994 mlen
= length
* reg_width
- header_size
;
3996 mlen
= length
* reg_width
;
3998 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
3999 BRW_REGISTER_TYPE_F
);
4000 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4002 /* Generate the SEND. */
4004 inst
->src
[0] = src_payload
;
4005 inst
->src
[1] = sampler
;
4006 inst
->resize_sources(2);
4007 inst
->base_mrf
= -1;
4009 inst
->header_size
= header_size
;
4011 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4012 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4016 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4018 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4019 const fs_reg
&coordinate
= inst
->src
[0];
4020 const fs_reg
&shadow_c
= inst
->src
[1];
4021 const fs_reg
&lod
= inst
->src
[2];
4022 const fs_reg
&lod2
= inst
->src
[3];
4023 const fs_reg
&sample_index
= inst
->src
[4];
4024 const fs_reg
&mcs
= inst
->src
[5];
4025 const fs_reg
&sampler
= inst
->src
[6];
4026 const fs_reg
&offset_value
= inst
->src
[7];
4027 assert(inst
->src
[8].file
== IMM
&& inst
->src
[9].file
== IMM
);
4028 const unsigned coord_components
= inst
->src
[8].ud
;
4029 const unsigned grad_components
= inst
->src
[9].ud
;
4031 if (devinfo
->gen
>= 7) {
4032 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4033 shadow_c
, lod
, lod2
, sample_index
,
4034 mcs
, sampler
, offset_value
,
4035 coord_components
, grad_components
);
4036 } else if (devinfo
->gen
>= 5) {
4037 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4038 shadow_c
, lod
, lod2
, sample_index
,
4039 sampler
, offset_value
,
4040 coord_components
, grad_components
);
4042 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4043 shadow_c
, lod
, lod2
, sampler
,
4044 coord_components
, grad_components
);
4049 * Initialize the header present in some typed and untyped surface
4053 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4055 fs_builder ubld
= bld
.exec_all().group(8, 0);
4056 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4057 ubld
.MOV(dst
, brw_imm_d(0));
4058 ubld
.MOV(component(dst
, 7), sample_mask
);
4063 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4064 const fs_reg
&sample_mask
)
4066 /* Get the logical send arguments. */
4067 const fs_reg
&addr
= inst
->src
[0];
4068 const fs_reg
&src
= inst
->src
[1];
4069 const fs_reg
&surface
= inst
->src
[2];
4070 const UNUSED fs_reg
&dims
= inst
->src
[3];
4071 const fs_reg
&arg
= inst
->src
[4];
4073 /* Calculate the total number of components of the payload. */
4074 const unsigned addr_sz
= inst
->components_read(0);
4075 const unsigned src_sz
= inst
->components_read(1);
4076 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4077 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4079 /* Allocate space for the payload. */
4080 fs_reg
*const components
= new fs_reg
[sz
];
4081 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4084 /* Construct the payload. */
4086 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4088 for (unsigned i
= 0; i
< addr_sz
; i
++)
4089 components
[n
++] = offset(addr
, bld
, i
);
4091 for (unsigned i
= 0; i
< src_sz
; i
++)
4092 components
[n
++] = offset(src
, bld
, i
);
4094 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4096 /* Update the original instruction. */
4098 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4099 inst
->header_size
= header_sz
;
4101 inst
->src
[0] = payload
;
4102 inst
->src
[1] = surface
;
4104 inst
->resize_sources(3);
4106 delete[] components
;
4110 fs_visitor::lower_logical_sends()
4112 bool progress
= false;
4114 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4115 const fs_builder
ibld(this, block
, inst
);
4117 switch (inst
->opcode
) {
4118 case FS_OPCODE_FB_WRITE_LOGICAL
:
4119 assert(stage
== MESA_SHADER_FRAGMENT
);
4120 lower_fb_write_logical_send(ibld
, inst
,
4121 (const brw_wm_prog_data
*)prog_data
,
4122 (const brw_wm_prog_key
*)key
,
4126 case SHADER_OPCODE_TEX_LOGICAL
:
4127 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4130 case SHADER_OPCODE_TXD_LOGICAL
:
4131 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4134 case SHADER_OPCODE_TXF_LOGICAL
:
4135 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4138 case SHADER_OPCODE_TXL_LOGICAL
:
4139 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4142 case SHADER_OPCODE_TXS_LOGICAL
:
4143 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4146 case FS_OPCODE_TXB_LOGICAL
:
4147 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4150 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4151 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4154 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4155 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4158 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4159 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4162 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4163 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4166 case SHADER_OPCODE_LOD_LOGICAL
:
4167 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4170 case SHADER_OPCODE_TG4_LOGICAL
:
4171 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4174 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4175 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4178 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4179 lower_surface_logical_send(ibld
, inst
,
4180 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4184 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4185 lower_surface_logical_send(ibld
, inst
,
4186 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4187 ibld
.sample_mask_reg());
4190 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4191 lower_surface_logical_send(ibld
, inst
,
4192 SHADER_OPCODE_UNTYPED_ATOMIC
,
4193 ibld
.sample_mask_reg());
4196 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4197 lower_surface_logical_send(ibld
, inst
,
4198 SHADER_OPCODE_TYPED_SURFACE_READ
,
4202 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4203 lower_surface_logical_send(ibld
, inst
,
4204 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4205 ibld
.sample_mask_reg());
4208 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4209 lower_surface_logical_send(ibld
, inst
,
4210 SHADER_OPCODE_TYPED_ATOMIC
,
4211 ibld
.sample_mask_reg());
4222 invalidate_live_intervals();
4228 * Get the closest native SIMD width supported by the hardware for instruction
4229 * \p inst. The instruction will be left untouched by
4230 * fs_visitor::lower_simd_width() if the returned value is equal to the
4231 * original execution size.
4234 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4235 const fs_inst
*inst
)
4237 switch (inst
->opcode
) {
4238 case BRW_OPCODE_MOV
:
4239 case BRW_OPCODE_SEL
:
4240 case BRW_OPCODE_NOT
:
4241 case BRW_OPCODE_AND
:
4243 case BRW_OPCODE_XOR
:
4244 case BRW_OPCODE_SHR
:
4245 case BRW_OPCODE_SHL
:
4246 case BRW_OPCODE_ASR
:
4247 case BRW_OPCODE_CMP
:
4248 case BRW_OPCODE_CMPN
:
4249 case BRW_OPCODE_CSEL
:
4250 case BRW_OPCODE_F32TO16
:
4251 case BRW_OPCODE_F16TO32
:
4252 case BRW_OPCODE_BFREV
:
4253 case BRW_OPCODE_BFE
:
4254 case BRW_OPCODE_BFI1
:
4255 case BRW_OPCODE_BFI2
:
4256 case BRW_OPCODE_ADD
:
4257 case BRW_OPCODE_MUL
:
4258 case BRW_OPCODE_AVG
:
4259 case BRW_OPCODE_FRC
:
4260 case BRW_OPCODE_RNDU
:
4261 case BRW_OPCODE_RNDD
:
4262 case BRW_OPCODE_RNDE
:
4263 case BRW_OPCODE_RNDZ
:
4264 case BRW_OPCODE_LZD
:
4265 case BRW_OPCODE_FBH
:
4266 case BRW_OPCODE_FBL
:
4267 case BRW_OPCODE_CBIT
:
4268 case BRW_OPCODE_SAD2
:
4269 case BRW_OPCODE_MAD
:
4270 case BRW_OPCODE_LRP
:
4271 case SHADER_OPCODE_RCP
:
4272 case SHADER_OPCODE_RSQ
:
4273 case SHADER_OPCODE_SQRT
:
4274 case SHADER_OPCODE_EXP2
:
4275 case SHADER_OPCODE_LOG2
:
4276 case SHADER_OPCODE_POW
:
4277 case SHADER_OPCODE_INT_QUOTIENT
:
4278 case SHADER_OPCODE_INT_REMAINDER
:
4279 case SHADER_OPCODE_SIN
:
4280 case SHADER_OPCODE_COS
: {
4281 /* According to the PRMs:
4282 * "A. In Direct Addressing mode, a source cannot span more than 2
4283 * adjacent GRF registers.
4284 * B. A destination cannot span more than 2 adjacent GRF registers."
4286 * Look for the source or destination with the largest register region
4287 * which is the one that is going to limit the overal execution size of
4288 * the instruction due to this rule.
4290 unsigned reg_count
= inst
->regs_written
;
4292 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4293 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4295 /* Calculate the maximum execution size of the instruction based on the
4296 * factor by which it goes over the hardware limit of 2 GRFs.
4298 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4300 case SHADER_OPCODE_MULH
:
4301 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4302 * is 8-wide on Gen7+.
4304 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4306 case FS_OPCODE_FB_WRITE_LOGICAL
:
4307 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4310 assert(devinfo
->gen
!= 6 ||
4311 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4312 inst
->exec_size
== 8);
4313 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4314 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4315 8 : inst
->exec_size
);
4317 case SHADER_OPCODE_TXD_LOGICAL
:
4318 /* TXD is unsupported in SIMD16 mode. */
4321 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4322 /* gather4_po_c is unsupported in SIMD16 mode. */
4323 const fs_reg
&shadow_c
= inst
->src
[1];
4324 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4326 case SHADER_OPCODE_TXL_LOGICAL
:
4327 case FS_OPCODE_TXB_LOGICAL
: {
4328 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4329 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4330 * mode because the message exceeds the maximum length of 11.
4332 const fs_reg
&shadow_c
= inst
->src
[1];
4333 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4335 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4338 return inst
->exec_size
;
4340 case SHADER_OPCODE_TXF_LOGICAL
:
4341 case SHADER_OPCODE_TXS_LOGICAL
:
4342 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4343 * messages. Use SIMD16 instead.
4345 if (devinfo
->gen
== 4)
4348 return inst
->exec_size
;
4350 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4351 /* This opcode can take up to 6 arguments which means that in some
4352 * circumstances it can end up with a message that is too long in SIMD16
4355 const unsigned coord_components
= inst
->src
[8].ud
;
4356 /* First three arguments are the sample index and the two arguments for
4359 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4362 return inst
->exec_size
;
4365 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4366 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4367 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4371 return inst
->exec_size
;
4376 * The \p rows array of registers represents a \p num_rows by \p num_columns
4377 * matrix in row-major order, write it in column-major order into the register
4378 * passed as destination. \p stride gives the separation between matrix
4379 * elements in the input in fs_builder::dispatch_width() units.
4382 emit_transpose(const fs_builder
&bld
,
4383 const fs_reg
&dst
, const fs_reg
*rows
,
4384 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4386 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4388 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4389 for (unsigned j
= 0; j
< num_rows
; ++j
)
4390 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4393 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4395 delete[] components
;
4399 fs_visitor::lower_simd_width()
4401 bool progress
= false;
4403 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4404 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4406 if (lower_width
!= inst
->exec_size
) {
4407 /* Builder matching the original instruction. We may also need to
4408 * emit an instruction of width larger than the original, set the
4409 * execution size of the builder to the highest of both for now so
4410 * we're sure that both cases can be handled.
4412 const fs_builder ibld
= bld
.at(block
, inst
)
4413 .exec_all(inst
->force_writemask_all
)
4414 .group(MAX2(inst
->exec_size
, lower_width
),
4415 inst
->force_sechalf
);
4417 /* Split the copies in chunks of the execution width of either the
4418 * original or the lowered instruction, whichever is lower.
4420 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4421 const unsigned n
= inst
->exec_size
/ copy_width
;
4422 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4423 inst
->dst
.component_size(inst
->exec_size
);
4426 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4427 !inst
->writes_accumulator
&& !inst
->mlen
);
4429 for (unsigned i
= 0; i
< n
; i
++) {
4430 /* Emit a copy of the original instruction with the lowered width.
4431 * If the EOT flag was set throw it away except for the last
4432 * instruction to avoid killing the thread prematurely.
4434 fs_inst split_inst
= *inst
;
4435 split_inst
.exec_size
= lower_width
;
4436 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4438 /* Select the correct channel enables for the i-th group, then
4439 * transform the sources and destination and emit the lowered
4442 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4444 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4445 if (inst
->src
[j
].file
!= BAD_FILE
&&
4446 !is_uniform(inst
->src
[j
])) {
4447 /* Get the i-th copy_width-wide chunk of the source. */
4448 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4449 const unsigned src_size
= inst
->components_read(j
);
4451 /* Use a trivial transposition to copy one every n
4452 * copy_width-wide components of the register into a
4453 * temporary passed as source to the lowered instruction.
4455 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4456 emit_transpose(lbld
.group(copy_width
, 0),
4457 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4461 if (inst
->regs_written
) {
4462 /* Allocate enough space to hold the result of the lowered
4463 * instruction and fix up the number of registers written.
4465 split_inst
.dst
= dsts
[i
] =
4466 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4467 split_inst
.regs_written
=
4468 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4472 lbld
.emit(split_inst
);
4475 if (inst
->regs_written
) {
4476 /* Distance between useful channels in the temporaries, skipping
4477 * garbage if the lowered instruction is wider than the original.
4479 const unsigned m
= lower_width
/ copy_width
;
4481 /* Interleave the components of the result from the lowered
4482 * instructions. We need to set exec_all() when copying more than
4483 * one half per component, because LOAD_PAYLOAD (in terms of which
4484 * emit_transpose is implemented) can only use the same channel
4485 * enable signals for all of its non-header sources.
4487 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4488 .group(copy_width
, 0),
4489 inst
->dst
, dsts
, n
, dst_size
, m
);
4492 inst
->remove(block
);
4498 invalidate_live_intervals();
4504 fs_visitor::dump_instructions()
4506 dump_instructions(NULL
);
4510 fs_visitor::dump_instructions(const char *name
)
4512 FILE *file
= stderr
;
4513 if (name
&& geteuid() != 0) {
4514 file
= fopen(name
, "w");
4520 calculate_register_pressure();
4521 int ip
= 0, max_pressure
= 0;
4522 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4523 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4524 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4525 dump_instruction(inst
, file
);
4528 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4531 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4532 fprintf(file
, "%4d: ", ip
++);
4533 dump_instruction(inst
, file
);
4537 if (file
!= stderr
) {
4543 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4545 dump_instruction(be_inst
, stderr
);
4549 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4551 fs_inst
*inst
= (fs_inst
*)be_inst
;
4553 if (inst
->predicate
) {
4554 fprintf(file
, "(%cf0.%d) ",
4555 inst
->predicate_inverse
? '-' : '+',
4559 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4561 fprintf(file
, ".sat");
4562 if (inst
->conditional_mod
) {
4563 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4564 if (!inst
->predicate
&&
4565 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4566 inst
->opcode
!= BRW_OPCODE_IF
&&
4567 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4568 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4571 fprintf(file
, "(%d) ", inst
->exec_size
);
4574 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4577 switch (inst
->dst
.file
) {
4579 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
4580 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
4581 inst
->dst
.subreg_offset
)
4582 fprintf(file
, "+%d.%d",
4583 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4586 fprintf(file
, "g%d", inst
->dst
.nr
);
4589 fprintf(file
, "m%d", inst
->dst
.nr
);
4592 fprintf(file
, "(null)");
4595 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4598 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4601 switch (inst
->dst
.nr
) {
4603 fprintf(file
, "null");
4605 case BRW_ARF_ADDRESS
:
4606 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
4608 case BRW_ARF_ACCUMULATOR
:
4609 fprintf(file
, "acc%d", inst
->dst
.subnr
);
4612 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4615 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4618 if (inst
->dst
.subnr
)
4619 fprintf(file
, "+%d", inst
->dst
.subnr
);
4622 unreachable("not reached");
4624 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4626 for (int i
= 0; i
< inst
->sources
; i
++) {
4627 if (inst
->src
[i
].negate
)
4629 if (inst
->src
[i
].abs
)
4631 switch (inst
->src
[i
].file
) {
4633 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
4634 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
4635 inst
->src
[i
].subreg_offset
)
4636 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4637 inst
->src
[i
].subreg_offset
);
4640 fprintf(file
, "g%d", inst
->src
[i
].nr
);
4643 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
4646 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
4649 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
4650 if (inst
->src
[i
].reladdr
) {
4651 fprintf(file
, "+reladdr");
4652 } else if (inst
->src
[i
].subreg_offset
) {
4653 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4654 inst
->src
[i
].subreg_offset
);
4658 fprintf(file
, "(null)");
4661 switch (inst
->src
[i
].type
) {
4662 case BRW_REGISTER_TYPE_F
:
4663 fprintf(file
, "%ff", inst
->src
[i
].f
);
4665 case BRW_REGISTER_TYPE_W
:
4666 case BRW_REGISTER_TYPE_D
:
4667 fprintf(file
, "%dd", inst
->src
[i
].d
);
4669 case BRW_REGISTER_TYPE_UW
:
4670 case BRW_REGISTER_TYPE_UD
:
4671 fprintf(file
, "%uu", inst
->src
[i
].ud
);
4673 case BRW_REGISTER_TYPE_VF
:
4674 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4675 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
4676 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
4677 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
4678 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
4681 fprintf(file
, "???");
4686 switch (inst
->src
[i
].nr
) {
4688 fprintf(file
, "null");
4690 case BRW_ARF_ADDRESS
:
4691 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
4693 case BRW_ARF_ACCUMULATOR
:
4694 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
4697 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4700 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4703 if (inst
->src
[i
].subnr
)
4704 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
4707 if (inst
->src
[i
].abs
)
4710 if (inst
->src
[i
].file
!= IMM
) {
4711 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4714 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4715 fprintf(file
, ", ");
4720 if (inst
->force_writemask_all
)
4721 fprintf(file
, "NoMask ");
4723 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4724 if (inst
->force_sechalf
)
4725 fprintf(file
, "2ndhalf ");
4727 fprintf(file
, "1sthalf ");
4730 fprintf(file
, "\n");
4734 * Possibly returns an instruction that set up @param reg.
4736 * Sometimes we want to take the result of some expression/variable
4737 * dereference tree and rewrite the instruction generating the result
4738 * of the tree. When processing the tree, we know that the
4739 * instructions generated are all writing temporaries that are dead
4740 * outside of this tree. So, if we have some instructions that write
4741 * a temporary, we're free to point that temp write somewhere else.
4743 * Note that this doesn't guarantee that the instruction generated
4744 * only reg -- it might be the size=4 destination of a texture instruction.
4747 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4752 end
->is_partial_write() ||
4754 !reg
.equals(end
->dst
)) {
4762 fs_visitor::setup_payload_gen6()
4765 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4766 unsigned barycentric_interp_modes
=
4767 (stage
== MESA_SHADER_FRAGMENT
) ?
4768 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4770 assert(devinfo
->gen
>= 6);
4772 /* R0-1: masks, pixel X/Y coordinates. */
4773 payload
.num_regs
= 2;
4774 /* R2: only for 32-pixel dispatch.*/
4776 /* R3-26: barycentric interpolation coordinates. These appear in the
4777 * same order that they appear in the brw_wm_barycentric_interp_mode
4778 * enum. Each set of coordinates occupies 2 registers if dispatch width
4779 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4780 * appear if they were enabled using the "Barycentric Interpolation
4781 * Mode" bits in WM_STATE.
4783 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4784 if (barycentric_interp_modes
& (1 << i
)) {
4785 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4786 payload
.num_regs
+= 2;
4787 if (dispatch_width
== 16) {
4788 payload
.num_regs
+= 2;
4793 /* R27: interpolated depth if uses source depth */
4795 payload
.source_depth_reg
= payload
.num_regs
;
4797 if (dispatch_width
== 16) {
4798 /* R28: interpolated depth if not SIMD8. */
4802 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4804 payload
.source_w_reg
= payload
.num_regs
;
4806 if (dispatch_width
== 16) {
4807 /* R30: interpolated W if not SIMD8. */
4812 if (stage
== MESA_SHADER_FRAGMENT
) {
4813 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4814 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4815 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4816 /* R31: MSAA position offsets. */
4817 if (prog_data
->uses_pos_offset
) {
4818 payload
.sample_pos_reg
= payload
.num_regs
;
4823 /* R32: MSAA input coverage mask */
4824 if (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4825 assert(devinfo
->gen
>= 7);
4826 payload
.sample_mask_in_reg
= payload
.num_regs
;
4828 if (dispatch_width
== 16) {
4829 /* R33: input coverage mask if not SIMD8. */
4834 /* R34-: bary for 32-pixel. */
4835 /* R58-59: interp W for 32-pixel. */
4837 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4838 source_depth_to_render_target
= true;
4843 fs_visitor::setup_vs_payload()
4845 /* R0: thread header, R1: urb handles */
4846 payload
.num_regs
= 2;
4850 * We are building the local ID push constant data using the simplest possible
4851 * method. We simply push the local IDs directly as they should appear in the
4852 * registers for the uvec3 gl_LocalInvocationID variable.
4854 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4855 * registers worth of push constant space.
4857 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
4858 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
4861 * FINISHME: There are a few easy optimizations to consider.
4863 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
4864 * no need for using push constant space for that dimension.
4866 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
4867 * easily use 16-bit words rather than 32-bit dwords in the push constant
4870 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
4871 * conveying the data, and thereby reduce push constant usage.
4875 fs_visitor::setup_gs_payload()
4877 assert(stage
== MESA_SHADER_GEOMETRY
);
4879 struct brw_gs_prog_data
*gs_prog_data
=
4880 (struct brw_gs_prog_data
*) prog_data
;
4881 struct brw_vue_prog_data
*vue_prog_data
=
4882 (struct brw_vue_prog_data
*) prog_data
;
4884 /* R0: thread header, R1: output URB handles */
4885 payload
.num_regs
= 2;
4887 if (gs_prog_data
->include_primitive_id
) {
4888 /* R2: Primitive ID 0..7 */
4892 /* Use a maximum of 32 registers for push-model inputs. */
4893 const unsigned max_push_components
= 32;
4895 /* If pushing our inputs would take too many registers, reduce the URB read
4896 * length (which is in HWords, or 8 registers), and resort to pulling.
4898 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
4899 * have to multiply by VerticesIn to obtain the total storage requirement.
4901 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
4902 max_push_components
) {
4903 gs_prog_data
->base
.include_vue_handles
= true;
4905 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
4906 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
4908 vue_prog_data
->urb_read_length
=
4909 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
4914 fs_visitor::setup_cs_payload()
4916 assert(devinfo
->gen
>= 7);
4917 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
4919 payload
.num_regs
= 1;
4921 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
4922 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
4923 payload
.local_invocation_id_reg
= payload
.num_regs
;
4924 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
4929 fs_visitor::calculate_register_pressure()
4931 invalidate_live_intervals();
4932 calculate_live_intervals();
4934 unsigned num_instructions
= 0;
4935 foreach_block(block
, cfg
)
4936 num_instructions
+= block
->instructions
.length();
4938 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
4940 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
4941 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
4942 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
4947 fs_visitor::optimize()
4949 /* Start by validating the shader we currently have. */
4952 /* bld is the common builder object pointing at the end of the program we
4953 * used to translate it into i965 IR. For the optimization and lowering
4954 * passes coming next, any code added after the end of the program without
4955 * having explicitly called fs_builder::at() clearly points at a mistake.
4956 * Ideally optimization passes wouldn't be part of the visitor so they
4957 * wouldn't have access to bld at all, but they do, so just in case some
4958 * pass forgets to ask for a location explicitly set it to NULL here to
4959 * make it trip. The dispatch width is initialized to a bogus value to
4960 * make sure that optimizations set the execution controls explicitly to
4961 * match the code they are manipulating instead of relying on the defaults.
4963 bld
= fs_builder(this, 64);
4965 assign_constant_locations();
4966 demote_pull_constants();
4970 split_virtual_grfs();
4973 #define OPT(pass, args...) ({ \
4975 bool this_progress = pass(args); \
4977 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
4978 char filename[64]; \
4979 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
4980 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
4982 backend_shader::dump_instructions(filename); \
4987 progress = progress || this_progress; \
4991 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
4993 snprintf(filename
, 64, "%s%d-%s-00-start",
4994 stage_abbrev
, dispatch_width
, nir
->info
.name
);
4996 backend_shader::dump_instructions(filename
);
4999 bool progress
= false;
5003 OPT(lower_simd_width
);
5004 OPT(lower_logical_sends
);
5011 OPT(remove_duplicate_mrf_writes
);
5015 OPT(opt_copy_propagate
);
5016 OPT(opt_predicated_break
, this);
5017 OPT(opt_cmod_propagation
);
5018 OPT(dead_code_eliminate
);
5019 OPT(opt_peephole_sel
);
5020 OPT(dead_control_flow_eliminate
, this);
5021 OPT(opt_register_renaming
);
5022 OPT(opt_redundant_discard_jumps
);
5023 OPT(opt_saturate_propagation
);
5024 OPT(opt_zero_samples
);
5025 OPT(register_coalesce
);
5026 OPT(compute_to_mrf
);
5027 OPT(eliminate_find_live_channel
);
5029 OPT(compact_virtual_grfs
);
5034 OPT(opt_sampler_eot
);
5036 if (OPT(lower_load_payload
)) {
5037 split_virtual_grfs();
5038 OPT(register_coalesce
);
5039 OPT(compute_to_mrf
);
5040 OPT(dead_code_eliminate
);
5043 OPT(opt_combine_constants
);
5044 OPT(lower_integer_multiplication
);
5046 lower_uniform_pull_constant_loads();
5052 * Three source instruction must have a GRF/MRF destination register.
5053 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5056 fs_visitor::fixup_3src_null_dest()
5058 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5059 if (inst
->is_3src() && inst
->dst
.is_null()) {
5060 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5067 fs_visitor::allocate_registers()
5069 bool allocated_without_spills
;
5071 static const enum instruction_scheduler_mode pre_modes
[] = {
5073 SCHEDULE_PRE_NON_LIFO
,
5077 /* Try each scheduling heuristic to see if it can successfully register
5078 * allocate without spilling. They should be ordered by decreasing
5079 * performance but increasing likelihood of allocating.
5081 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5082 schedule_instructions(pre_modes
[i
]);
5085 assign_regs_trivial();
5086 allocated_without_spills
= true;
5088 allocated_without_spills
= assign_regs(false);
5090 if (allocated_without_spills
)
5094 if (!allocated_without_spills
) {
5095 /* We assume that any spilling is worse than just dropping back to
5096 * SIMD8. There's probably actually some intermediate point where
5097 * SIMD16 with a couple of spills is still better.
5099 if (dispatch_width
== 16) {
5100 fail("Failure to register allocate. Reduce number of "
5101 "live scalar values to avoid this.");
5103 compiler
->shader_perf_log(log_data
,
5104 "%s shader triggered register spilling. "
5105 "Try reducing the number of live scalar "
5106 "values to improve performance.\n",
5110 /* Since we're out of heuristics, just go spill registers until we
5111 * get an allocation.
5113 while (!assign_regs(true)) {
5119 /* This must come after all optimization and register allocation, since
5120 * it inserts dead code that happens to have side effects, and it does
5121 * so based on the actual physical registers in use.
5123 insert_gen4_send_dependency_workarounds();
5128 schedule_instructions(SCHEDULE_POST
);
5130 if (last_scratch
> 0)
5131 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5135 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5137 assert(stage
== MESA_SHADER_VERTEX
);
5141 if (shader_time_index
>= 0)
5142 emit_shader_time_begin();
5149 compute_clip_distance(clip_planes
);
5153 if (shader_time_index
>= 0)
5154 emit_shader_time_end();
5160 assign_curb_setup();
5161 assign_vs_urb_setup();
5163 fixup_3src_null_dest();
5164 allocate_registers();
5170 fs_visitor::run_gs()
5172 assert(stage
== MESA_SHADER_GEOMETRY
);
5176 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
5178 if (gs_compile
->control_data_header_size_bits
> 0) {
5179 /* Create a VGRF to store accumulated control data bits. */
5180 this->control_data_bits
= vgrf(glsl_type::uint_type
);
5182 /* If we're outputting more than 32 control data bits, then EmitVertex()
5183 * will set control_data_bits to 0 after emitting the first vertex.
5184 * Otherwise, we need to initialize it to 0 here.
5186 if (gs_compile
->control_data_header_size_bits
<= 32) {
5187 const fs_builder abld
= bld
.annotate("initialize control data bits");
5188 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
5192 if (shader_time_index
>= 0)
5193 emit_shader_time_begin();
5197 emit_gs_thread_end();
5199 if (shader_time_index
>= 0)
5200 emit_shader_time_end();
5209 assign_curb_setup();
5210 assign_gs_urb_setup();
5212 fixup_3src_null_dest();
5213 allocate_registers();
5219 fs_visitor::run_fs(bool do_rep_send
)
5221 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5222 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5224 assert(stage
== MESA_SHADER_FRAGMENT
);
5226 if (devinfo
->gen
>= 6)
5227 setup_payload_gen6();
5229 setup_payload_gen4();
5233 } else if (do_rep_send
) {
5234 assert(dispatch_width
== 16);
5235 emit_repclear_shader();
5237 if (shader_time_index
>= 0)
5238 emit_shader_time_begin();
5240 calculate_urb_setup();
5241 if (nir
->info
.inputs_read
> 0) {
5242 if (devinfo
->gen
< 6)
5243 emit_interpolation_setup_gen4();
5245 emit_interpolation_setup_gen6();
5248 /* We handle discards by keeping track of the still-live pixels in f0.1.
5249 * Initialize it with the dispatched pixels.
5251 if (wm_prog_data
->uses_kill
) {
5252 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5253 discard_init
->flag_subreg
= 1;
5256 /* Generate FS IR for main(). (the visitor only descends into
5257 * functions called "main").
5264 if (wm_prog_data
->uses_kill
)
5265 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5267 if (wm_key
->alpha_test_func
)
5272 if (shader_time_index
>= 0)
5273 emit_shader_time_end();
5279 assign_curb_setup();
5282 fixup_3src_null_dest();
5283 allocate_registers();
5289 if (dispatch_width
== 8)
5290 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5292 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5298 fs_visitor::run_cs()
5300 assert(stage
== MESA_SHADER_COMPUTE
);
5304 if (shader_time_index
>= 0)
5305 emit_shader_time_begin();
5312 emit_cs_terminate();
5314 if (shader_time_index
>= 0)
5315 emit_shader_time_end();
5321 assign_curb_setup();
5323 fixup_3src_null_dest();
5324 allocate_registers();
5333 * Return a bitfield where bit n is set if barycentric interpolation mode n
5334 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5337 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5338 bool shade_model_flat
,
5339 bool persample_shading
,
5340 const nir_shader
*shader
)
5342 unsigned barycentric_interp_modes
= 0;
5344 nir_foreach_variable(var
, &shader
->inputs
) {
5345 enum glsl_interp_qualifier interp_qualifier
=
5346 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5347 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5348 bool is_sample
= var
->data
.sample
|| persample_shading
;
5349 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5350 (var
->data
.location
== VARYING_SLOT_COL1
);
5352 /* Ignore WPOS and FACE, because they don't require interpolation. */
5353 if (var
->data
.location
== VARYING_SLOT_POS
||
5354 var
->data
.location
== VARYING_SLOT_FACE
)
5357 /* Determine the set (or sets) of barycentric coordinates needed to
5358 * interpolate this variable. Note that when
5359 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5360 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5361 * for lit pixels, so we need both sets of barycentric coordinates.
5363 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5365 barycentric_interp_modes
|=
5366 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5367 } else if (is_sample
) {
5368 barycentric_interp_modes
|=
5369 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5371 if ((!is_centroid
&& !is_sample
) ||
5372 devinfo
->needs_unlit_centroid_workaround
) {
5373 barycentric_interp_modes
|=
5374 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5376 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5377 (!(shade_model_flat
&& is_gl_Color
) &&
5378 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5380 barycentric_interp_modes
|=
5381 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5382 } else if (is_sample
) {
5383 barycentric_interp_modes
|=
5384 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5386 if ((!is_centroid
&& !is_sample
) ||
5387 devinfo
->needs_unlit_centroid_workaround
) {
5388 barycentric_interp_modes
|=
5389 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5394 return barycentric_interp_modes
;
5398 computed_depth_mode(const nir_shader
*shader
)
5400 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5401 switch (shader
->info
.fs
.depth_layout
) {
5402 case FRAG_DEPTH_LAYOUT_NONE
:
5403 case FRAG_DEPTH_LAYOUT_ANY
:
5404 return BRW_PSCDEPTH_ON
;
5405 case FRAG_DEPTH_LAYOUT_GREATER
:
5406 return BRW_PSCDEPTH_ON_GE
;
5407 case FRAG_DEPTH_LAYOUT_LESS
:
5408 return BRW_PSCDEPTH_ON_LE
;
5409 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5410 return BRW_PSCDEPTH_OFF
;
5413 return BRW_PSCDEPTH_OFF
;
5417 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5419 const struct brw_wm_prog_key
*key
,
5420 struct brw_wm_prog_data
*prog_data
,
5421 const nir_shader
*shader
,
5422 struct gl_program
*prog
,
5423 int shader_time_index8
, int shader_time_index16
,
5425 unsigned *final_assembly_size
,
5428 /* key->alpha_test_func means simulating alpha testing via discards,
5429 * so the shader definitely kills pixels.
5431 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5432 prog_data
->uses_omask
=
5433 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5434 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5435 prog_data
->computed_stencil
=
5436 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5438 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5440 prog_data
->barycentric_interp_modes
=
5441 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5443 key
->persample_shading
,
5446 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5447 &prog_data
->base
, prog
, shader
, 8,
5448 shader_time_index8
);
5449 if (!v
.run_fs(false /* do_rep_send */)) {
5451 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5456 cfg_t
*simd16_cfg
= NULL
;
5457 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5458 &prog_data
->base
, prog
, shader
, 16,
5459 shader_time_index16
);
5460 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5461 if (!v
.simd16_unsupported
) {
5462 /* Try a SIMD16 compile */
5463 v2
.import_uniforms(&v
);
5464 if (!v2
.run_fs(use_rep_send
)) {
5465 compiler
->shader_perf_log(log_data
,
5466 "SIMD16 shader failed to compile: %s",
5469 simd16_cfg
= v2
.cfg
;
5475 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5476 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5478 prog_data
->no_8
= true;
5481 prog_data
->no_8
= false;
5484 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5485 v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
5487 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5488 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5489 shader
->info
.label
? shader
->info
.label
:
5491 shader
->info
.name
));
5495 g
.generate_code(simd8_cfg
, 8);
5497 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5499 return g
.get_assembly(final_assembly_size
);
5503 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
5504 void *buffer
, uint32_t threads
, uint32_t stride
)
5506 if (prog_data
->local_invocation_id_regs
== 0)
5509 /* 'stride' should be an integer number of registers, that is, a multiple
5512 assert(stride
% 32 == 0);
5514 unsigned x
= 0, y
= 0, z
= 0;
5515 for (unsigned t
= 0; t
< threads
; t
++) {
5516 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
5518 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
5519 param
[0 * prog_data
->simd_size
+ i
] = x
;
5520 param
[1 * prog_data
->simd_size
+ i
] = y
;
5521 param
[2 * prog_data
->simd_size
+ i
] = z
;
5524 if (x
== prog_data
->local_size
[0]) {
5527 if (y
== prog_data
->local_size
[1]) {
5530 if (z
== prog_data
->local_size
[2])
5539 fs_visitor::emit_cs_local_invocation_id_setup()
5541 assert(stage
== MESA_SHADER_COMPUTE
);
5543 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5545 struct brw_reg src
=
5546 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5547 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5549 src
.nr
+= dispatch_width
/ 8;
5550 bld
.MOV(offset(*reg
, bld
, 1), src
);
5551 src
.nr
+= dispatch_width
/ 8;
5552 bld
.MOV(offset(*reg
, bld
, 2), src
);
5558 fs_visitor::emit_cs_work_group_id_setup()
5560 assert(stage
== MESA_SHADER_COMPUTE
);
5562 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5564 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5565 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5566 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5568 bld
.MOV(*reg
, r0_1
);
5569 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5570 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5576 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5578 const struct brw_cs_prog_key
*key
,
5579 struct brw_cs_prog_data
*prog_data
,
5580 const nir_shader
*shader
,
5581 int shader_time_index
,
5582 unsigned *final_assembly_size
,
5585 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5586 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5587 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5588 unsigned local_workgroup_size
=
5589 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5590 shader
->info
.cs
.local_size
[2];
5592 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5595 const char *fail_msg
= NULL
;
5597 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5599 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5600 NULL
, /* Never used in core profile */
5601 shader
, 8, shader_time_index
);
5603 fail_msg
= v8
.fail_msg
;
5604 } else if (local_workgroup_size
<= 8 * max_cs_threads
) {
5606 prog_data
->simd_size
= 8;
5609 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5610 NULL
, /* Never used in core profile */
5611 shader
, 16, shader_time_index
);
5612 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5613 !fail_msg
&& !v8
.simd16_unsupported
&&
5614 local_workgroup_size
<= 16 * max_cs_threads
) {
5615 /* Try a SIMD16 compile */
5616 v16
.import_uniforms(&v8
);
5617 if (!v16
.run_cs()) {
5618 compiler
->shader_perf_log(log_data
,
5619 "SIMD16 shader failed to compile: %s",
5623 "Couldn't generate SIMD16 program and not "
5624 "enough threads for SIMD8";
5628 prog_data
->simd_size
= 16;
5632 if (unlikely(cfg
== NULL
)) {
5635 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5640 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5641 v8
.promoted_constants
, v8
.runtime_check_aads_emit
, "CS");
5642 if (INTEL_DEBUG
& DEBUG_CS
) {
5643 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5644 shader
->info
.label
? shader
->info
.label
:
5647 g
.enable_debug(name
);
5650 g
.generate_code(cfg
, prog_data
->simd_size
);
5652 return g
.get_assembly(final_assembly_size
);