2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_optimize.h"
37 #include "program/hash_table.h"
38 #include "brw_context.h"
43 #include "../glsl/glsl_types.h"
44 #include "../glsl/ir_optimization.h"
45 #include "../glsl/ir_print_visitor.h"
48 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
49 GRF
= BRW_GENERAL_REGISTER_FILE
,
50 MRF
= BRW_MESSAGE_REGISTER_FILE
,
51 IMM
= BRW_IMMEDIATE_VALUE
,
52 FIXED_HW_REG
, /* a struct brw_reg */
53 UNIFORM
, /* prog_data->params[hw_reg] */
58 FS_OPCODE_FB_WRITE
= 256,
72 static int using_new_fs
= -1;
75 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
77 struct brw_shader
*shader
;
79 shader
= talloc_zero(NULL
, struct brw_shader
);
81 shader
->base
.Type
= type
;
82 shader
->base
.Name
= name
;
83 _mesa_init_shader(ctx
, &shader
->base
);
89 struct gl_shader_program
*
90 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
92 struct brw_shader_program
*prog
;
93 prog
= talloc_zero(NULL
, struct brw_shader_program
);
95 prog
->base
.Name
= name
;
96 _mesa_init_shader_program(ctx
, &prog
->base
);
102 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
104 if (!_mesa_ir_compile_shader(ctx
, shader
))
111 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
113 if (using_new_fs
== -1)
114 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
116 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
117 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
119 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
120 void *mem_ctx
= talloc_new(NULL
);
124 talloc_free(shader
->ir
);
125 shader
->ir
= new(shader
) exec_list
;
126 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
128 do_mat_op_to_vec(shader
->ir
);
129 do_mod_to_fract(shader
->ir
);
130 do_div_to_mul_rcp(shader
->ir
);
131 do_sub_to_add_neg(shader
->ir
);
132 do_explog_to_explog2(shader
->ir
);
134 brw_do_channel_expressions(shader
->ir
);
135 brw_do_vector_splitting(shader
->ir
);
140 progress
= do_common_optimization(shader
->ir
, true) || progress
;
143 validate_ir_tree(shader
->ir
);
145 reparent_ir(shader
->ir
, shader
->ir
);
146 talloc_free(mem_ctx
);
150 if (!_mesa_ir_link_shader(ctx
, prog
))
157 type_size(const struct glsl_type
*type
)
159 unsigned int size
, i
;
161 switch (type
->base_type
) {
164 case GLSL_TYPE_FLOAT
:
166 return type
->components();
167 case GLSL_TYPE_ARRAY
:
168 /* FINISHME: uniform/varying arrays. */
169 return type_size(type
->fields
.array
) * type
->length
;
170 case GLSL_TYPE_STRUCT
:
172 for (i
= 0; i
< type
->length
; i
++) {
173 size
+= type_size(type
->fields
.structure
[i
].type
);
176 case GLSL_TYPE_SAMPLER
:
177 /* Samplers take up no register space, since they're baked in at
182 assert(!"not reached");
189 /* Callers of this talloc-based new need not call delete. It's
190 * easier to just talloc_free 'ctx' (or any of its ancestors). */
191 static void* operator new(size_t size
, void *ctx
)
195 node
= talloc_size(ctx
, size
);
196 assert(node
!= NULL
);
201 /** Generic unset register constructor. */
204 this->file
= BAD_FILE
;
206 this->reg_offset
= 0;
212 /** Immediate value constructor. */
218 this->type
= BRW_REGISTER_TYPE_F
;
224 /** Immediate value constructor. */
230 this->type
= BRW_REGISTER_TYPE_D
;
236 /** Immediate value constructor. */
242 this->type
= BRW_REGISTER_TYPE_UD
;
248 /** Fixed brw_reg Immediate value constructor. */
249 fs_reg(struct brw_reg fixed_hw_reg
)
251 this->file
= FIXED_HW_REG
;
252 this->fixed_hw_reg
= fixed_hw_reg
;
255 this->type
= fixed_hw_reg
.type
;
260 fs_reg(enum register_file file
, int hw_reg
);
261 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
263 /** Register file: ARF, GRF, MRF, IMM. */
264 enum register_file file
;
265 /** Abstract register number. 0 = fixed hw reg */
267 /** Offset within the abstract register. */
269 /** HW register number. Generally unset until register allocation. */
271 /** Register type. BRW_REGISTER_TYPE_* */
275 struct brw_reg fixed_hw_reg
;
277 /** Value for file == BRW_IMMMEDIATE_FILE */
285 static const fs_reg reg_undef
;
286 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
288 class fs_inst
: public exec_node
{
290 /* Callers of this talloc-based new need not call delete. It's
291 * easier to just talloc_free 'ctx' (or any of its ancestors). */
292 static void* operator new(size_t size
, void *ctx
)
296 node
= talloc_zero_size(ctx
, size
);
297 assert(node
!= NULL
);
304 this->opcode
= BRW_OPCODE_NOP
;
305 this->saturate
= false;
306 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
307 this->predicated
= false;
312 this->opcode
= opcode
;
313 this->saturate
= false;
314 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
315 this->predicated
= false;
318 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
)
320 this->opcode
= opcode
;
323 this->saturate
= false;
324 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
325 this->predicated
= false;
328 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
330 this->opcode
= opcode
;
334 this->saturate
= false;
335 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
336 this->predicated
= false;
339 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg src2
)
341 this->opcode
= opcode
;
346 this->saturate
= false;
347 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
348 this->predicated
= false;
351 int opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
356 int conditional_mod
; /**< BRW_CONDITIONAL_* */
359 * Annotation for the generated IR. One of the two can be set.
362 const char *annotation
;
366 class fs_visitor
: public ir_visitor
370 fs_visitor(struct brw_wm_compile
*c
, struct brw_shader
*shader
)
375 this->intel
= &brw
->intel
;
376 this->ctx
= &intel
->ctx
;
377 this->mem_ctx
= talloc_new(NULL
);
378 this->shader
= shader
;
380 this->next_abstract_grf
= 1;
381 this->variable_ht
= hash_table_ctor(0,
382 hash_table_pointer_hash
,
383 hash_table_pointer_compare
);
385 this->frag_color
= NULL
;
386 this->frag_data
= NULL
;
387 this->frag_depth
= NULL
;
388 this->first_non_payload_grf
= 0;
390 this->current_annotation
= NULL
;
391 this->annotation_string
= NULL
;
392 this->annotation_ir
= NULL
;
396 talloc_free(this->mem_ctx
);
397 hash_table_dtor(this->variable_ht
);
400 fs_reg
*variable_storage(ir_variable
*var
);
402 void visit(ir_variable
*ir
);
403 void visit(ir_assignment
*ir
);
404 void visit(ir_dereference_variable
*ir
);
405 void visit(ir_dereference_record
*ir
);
406 void visit(ir_dereference_array
*ir
);
407 void visit(ir_expression
*ir
);
408 void visit(ir_texture
*ir
);
409 void visit(ir_if
*ir
);
410 void visit(ir_constant
*ir
);
411 void visit(ir_swizzle
*ir
);
412 void visit(ir_return
*ir
);
413 void visit(ir_loop
*ir
);
414 void visit(ir_loop_jump
*ir
);
415 void visit(ir_discard
*ir
);
416 void visit(ir_call
*ir
);
417 void visit(ir_function
*ir
);
418 void visit(ir_function_signature
*ir
);
420 fs_inst
*emit(fs_inst inst
);
421 void assign_curb_setup();
422 void assign_urb_setup();
424 void generate_code();
425 void generate_fb_write(fs_inst
*inst
);
426 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
427 struct brw_reg
*src
);
428 void generate_math(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg
*src
);
430 void emit_dummy_fs();
431 void emit_interpolation();
432 void emit_pinterp(int location
);
433 void emit_fb_writes();
435 struct brw_reg
interp_reg(int location
, int channel
);
437 struct brw_context
*brw
;
438 struct intel_context
*intel
;
440 struct brw_wm_compile
*c
;
441 struct brw_compile
*p
;
442 struct brw_shader
*shader
;
444 exec_list instructions
;
445 int next_abstract_grf
;
446 struct hash_table
*variable_ht
;
447 ir_variable
*frag_color
, *frag_data
, *frag_depth
;
448 int first_non_payload_grf
;
450 /** @{ debug annotation info */
451 const char *current_annotation
;
452 ir_instruction
*base_ir
;
453 const char **annotation_string
;
454 ir_instruction
**annotation_ir
;
459 /* Result of last visit() method. */
467 fs_reg interp_attrs
[64];
473 /** Fixed HW reg constructor. */
474 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
478 this->reg_offset
= 0;
479 this->hw_reg
= hw_reg
;
480 this->type
= BRW_REGISTER_TYPE_F
;
485 /** Automatic reg constructor. */
486 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
489 this->reg
= v
->next_abstract_grf
;
490 this->reg_offset
= 0;
491 v
->next_abstract_grf
+= type_size(type
);
496 switch (type
->base_type
) {
497 case GLSL_TYPE_FLOAT
:
498 this->type
= BRW_REGISTER_TYPE_F
;
502 this->type
= BRW_REGISTER_TYPE_D
;
505 this->type
= BRW_REGISTER_TYPE_UD
;
508 assert(!"not reached");
509 this->type
= BRW_REGISTER_TYPE_F
;
515 fs_visitor::variable_storage(ir_variable
*var
)
517 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
521 fs_visitor::visit(ir_variable
*ir
)
525 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
526 this->frag_color
= ir
;
527 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
528 this->frag_data
= ir
;
529 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
530 this->frag_depth
= ir
;
531 assert(!"FINISHME: this hangs currently.");
534 if (ir
->mode
== ir_var_in
) {
535 reg
= &this->interp_attrs
[ir
->location
];
538 if (ir
->mode
== ir_var_uniform
) {
539 const float *vec_values
;
540 int param_index
= c
->prog_data
.nr_params
;
542 /* FINISHME: This is wildly incomplete. */
543 assert(ir
->type
->is_scalar() || ir
->type
->is_vector());
545 const struct gl_program
*fp
= &this->brw
->fragment_program
->Base
;
546 /* Our support for uniforms is piggy-backed on the struct
547 * gl_fragment_program, because that's where the values actually
548 * get stored, rather than in some global gl_shader_program uniform
551 vec_values
= fp
->Parameters
->ParameterValues
[ir
->location
];
552 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
553 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
556 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
560 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
562 hash_table_insert(this->variable_ht
, reg
, ir
);
566 fs_visitor::visit(ir_dereference_variable
*ir
)
568 fs_reg
*reg
= variable_storage(ir
->var
);
573 fs_visitor::visit(ir_dereference_record
*ir
)
579 fs_visitor::visit(ir_dereference_array
*ir
)
584 ir
->array
->accept(this);
585 index
= ir
->array_index
->as_constant();
587 if (ir
->type
->is_matrix()) {
588 element_size
= ir
->type
->vector_elements
;
590 element_size
= type_size(ir
->type
);
594 assert(this->result
.file
== UNIFORM
||
595 (this->result
.file
== GRF
&&
596 this->result
.reg
!= 0));
597 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
599 assert(!"FINISHME: non-constant matrix column");
604 fs_visitor::visit(ir_expression
*ir
)
606 unsigned int operand
;
611 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
612 ir
->operands
[operand
]->accept(this);
613 if (this->result
.file
== BAD_FILE
) {
615 printf("Failed to get tree for expression operand:\n");
616 ir
->operands
[operand
]->accept(&v
);
619 op
[operand
] = this->result
;
621 /* Matrix expression operands should have been broken down to vector
622 * operations already.
624 assert(!ir
->operands
[operand
]->type
->is_matrix());
625 /* And then those vector operands should have been broken down to scalar.
627 assert(!ir
->operands
[operand
]->type
->is_vector());
630 /* Storage for our result. If our result goes into an assignment, it will
631 * just get copy-propagated out, so no worries.
633 this->result
= fs_reg(this, ir
->type
);
635 switch (ir
->operation
) {
636 case ir_unop_logic_not
:
637 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
640 op
[0].negate
= ~op
[0].negate
;
641 this->result
= op
[0];
645 this->result
= op
[0];
648 temp
= fs_reg(this, ir
->type
);
650 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
651 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
653 inst
= emit(fs_inst(BRW_OPCODE_CMP
, temp
, op
[0], fs_reg(0.0f
)));
654 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
657 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, this->result
, temp
));
661 emit(fs_inst(FS_OPCODE_RCP
, this->result
, op
[0]));
665 emit(fs_inst(FS_OPCODE_EXP2
, this->result
, op
[0]));
668 emit(fs_inst(FS_OPCODE_LOG2
, this->result
, op
[0]));
672 assert(!"not reached: should be handled by ir_explog_to_explog2");
675 emit(fs_inst(FS_OPCODE_SIN
, this->result
, op
[0]));
678 emit(fs_inst(FS_OPCODE_COS
, this->result
, op
[0]));
682 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
685 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
689 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
692 assert(!"not reached: should be handled by ir_sub_to_add_neg");
696 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
699 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
702 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
706 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
707 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
708 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
710 case ir_binop_greater
:
711 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
712 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
713 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
715 case ir_binop_lequal
:
716 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
717 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
718 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
720 case ir_binop_gequal
:
721 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
722 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
723 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
726 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
727 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
728 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
730 case ir_binop_nequal
:
731 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
732 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
733 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
736 case ir_binop_logic_xor
:
737 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
740 case ir_binop_logic_or
:
741 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
744 case ir_binop_logic_and
:
745 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
751 assert(!"not reached: should be handled by brw_channel_expressions");
755 emit(fs_inst(FS_OPCODE_SQRT
, this->result
, op
[0]));
759 emit(fs_inst(FS_OPCODE_RSQ
, this->result
, op
[0]));
765 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
768 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
772 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
773 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
776 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
779 op
[0].negate
= ~op
[0].negate
;
780 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
781 this->result
.negate
= true;
784 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
787 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
791 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
792 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
794 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
795 inst
->predicated
= true;
798 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
799 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
801 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
802 inst
->predicated
= true;
806 inst
= emit(fs_inst(FS_OPCODE_POW
, this->result
, op
[0], op
[1]));
809 case ir_unop_bit_not
:
811 case ir_binop_lshift
:
812 case ir_binop_rshift
:
813 case ir_binop_bit_and
:
814 case ir_binop_bit_xor
:
815 case ir_binop_bit_or
:
816 assert(!"GLSL 1.30 features unsupported");
822 fs_visitor::visit(ir_assignment
*ir
)
829 /* FINISHME: arrays on the lhs */
830 ir
->lhs
->accept(this);
833 ir
->rhs
->accept(this);
836 /* FINISHME: This should really set to the correct maximal writemask for each
837 * FINISHME: component written (in the loops below). This case can only
838 * FINISHME: occur for matrices, arrays, and structures.
840 if (ir
->write_mask
== 0) {
841 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
842 write_mask
= WRITEMASK_XYZW
;
844 assert(ir
->lhs
->type
->is_vector() || ir
->lhs
->type
->is_scalar());
845 write_mask
= ir
->write_mask
;
848 assert(l
.file
!= BAD_FILE
);
849 assert(r
.file
!= BAD_FILE
);
852 /* Get the condition bool into the predicate. */
853 ir
->condition
->accept(this);
854 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, fs_reg(0)));
855 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
858 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
859 if (i
>= 4 || (write_mask
& (1 << i
))) {
860 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
862 inst
->predicated
= true;
870 fs_visitor::visit(ir_texture
*ir
)
876 fs_visitor::visit(ir_swizzle
*ir
)
878 ir
->val
->accept(this);
879 fs_reg val
= this->result
;
881 fs_reg result
= fs_reg(this, ir
->type
);
882 this->result
= result
;
884 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
885 fs_reg channel
= val
;
903 channel
.reg_offset
+= swiz
;
904 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
910 fs_visitor::visit(ir_discard
*ir
)
916 fs_visitor::visit(ir_constant
*ir
)
918 fs_reg
reg(this, ir
->type
);
921 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
922 switch (ir
->type
->base_type
) {
923 case GLSL_TYPE_FLOAT
:
924 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
927 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
930 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
933 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
936 assert(!"Non-float/uint/int/bool constant");
943 fs_visitor::visit(ir_if
*ir
)
947 /* Don't point the annotation at the if statement, because then it plus
948 * the then and else blocks get printed.
950 this->base_ir
= ir
->condition
;
952 /* Generate the condition into the condition code. */
953 ir
->condition
->accept(this);
954 inst
= emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(brw_null_reg()), this->result
));
955 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
957 inst
= emit(fs_inst(BRW_OPCODE_IF
));
958 inst
->predicated
= true;
960 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
961 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
967 if (!ir
->else_instructions
.is_empty()) {
968 emit(fs_inst(BRW_OPCODE_ELSE
));
970 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
971 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
978 emit(fs_inst(BRW_OPCODE_ENDIF
));
982 fs_visitor::visit(ir_loop
*ir
)
988 fs_visitor::visit(ir_loop_jump
*ir
)
994 fs_visitor::visit(ir_call
*ir
)
1000 fs_visitor::visit(ir_return
*ir
)
1002 assert(!"FINISHME");
1006 fs_visitor::visit(ir_function
*ir
)
1008 /* Ignore function bodies other than main() -- we shouldn't see calls to
1009 * them since they should all be inlined before we get to ir_to_mesa.
1011 if (strcmp(ir
->name
, "main") == 0) {
1012 const ir_function_signature
*sig
;
1015 sig
= ir
->matching_signature(&empty
);
1019 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1020 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1029 fs_visitor::visit(ir_function_signature
*ir
)
1031 assert(!"not reached");
1036 fs_visitor::emit(fs_inst inst
)
1038 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1041 list_inst
->annotation
= this->current_annotation
;
1042 list_inst
->ir
= this->base_ir
;
1044 this->instructions
.push_tail(list_inst
);
1049 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1051 fs_visitor::emit_dummy_fs()
1053 /* Everyone's favorite color. */
1054 emit(fs_inst(BRW_OPCODE_MOV
,
1057 emit(fs_inst(BRW_OPCODE_MOV
,
1060 emit(fs_inst(BRW_OPCODE_MOV
,
1063 emit(fs_inst(BRW_OPCODE_MOV
,
1068 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1073 /* The register location here is relative to the start of the URB
1074 * data. It will get adjusted to be a real location before
1075 * generate_code() time.
1078 fs_visitor::interp_reg(int location
, int channel
)
1080 int regnr
= location
* 2 + channel
/ 2;
1081 int stride
= (channel
& 1) * 4;
1083 return brw_vec1_grf(regnr
, stride
);
1086 /** Emits the interpolation for the varying inputs. */
1088 fs_visitor::emit_interpolation()
1090 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1091 /* For now, the source regs for the setup URB data will be unset,
1092 * since we don't know until codegen how many push constants we'll
1093 * use, and therefore what the setup URB offset is.
1095 fs_reg src_reg
= reg_undef
;
1097 this->current_annotation
= "compute pixel centers";
1098 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1099 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1100 emit(fs_inst(BRW_OPCODE_ADD
,
1102 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1103 fs_reg(brw_imm_v(0x10101010))));
1104 emit(fs_inst(BRW_OPCODE_ADD
,
1106 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1107 fs_reg(brw_imm_v(0x11001100))));
1109 this->current_annotation
= "compute pixel deltas from v0";
1110 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1111 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1112 emit(fs_inst(BRW_OPCODE_ADD
,
1115 fs_reg(negate(brw_vec1_grf(1, 0)))));
1116 emit(fs_inst(BRW_OPCODE_ADD
,
1119 fs_reg(brw_vec1_grf(1, 1))));
1121 this->current_annotation
= "compute pos.w and 1/pos.w";
1122 /* Compute wpos. Unlike many other varying inputs, we usually need it
1123 * to produce 1/w, and the varying variable wouldn't show up.
1125 fs_reg wpos
= fs_reg(this, glsl_type::vec4_type
);
1126 this->interp_attrs
[FRAG_ATTRIB_WPOS
] = wpos
;
1127 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
)); /* FINISHME: ARB_fcc */
1129 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
)); /* FINISHME: ARB_fcc */
1131 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
1132 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
1134 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
1135 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1136 /* Compute the pixel W value from wpos.w. */
1137 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1138 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos
));
1140 /* FINISHME: gl_FrontFacing */
1142 foreach_iter(exec_list_iterator
, iter
, *this->shader
->ir
) {
1143 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1144 ir_variable
*var
= ir
->as_variable();
1149 if (var
->mode
!= ir_var_in
)
1152 /* If it's already set up (WPOS), skip. */
1153 if (var
->location
== 0)
1156 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1158 "(FRAG_ATTRIB[%d])",
1161 emit_pinterp(var
->location
);
1163 this->current_annotation
= NULL
;
1167 fs_visitor::emit_pinterp(int location
)
1169 fs_reg interp_attr
= fs_reg(this, glsl_type::vec4_type
);
1170 this->interp_attrs
[location
] = interp_attr
;
1172 for (unsigned int i
= 0; i
< 4; i
++) {
1173 struct brw_reg interp
= interp_reg(location
, i
);
1174 emit(fs_inst(FS_OPCODE_LINTERP
,
1179 interp_attr
.reg_offset
++;
1181 interp_attr
.reg_offset
-= 4;
1183 for (unsigned int i
= 0; i
< 4; i
++) {
1184 emit(fs_inst(BRW_OPCODE_MUL
,
1188 interp_attr
.reg_offset
++;
1193 fs_visitor::emit_fb_writes()
1195 this->current_annotation
= "FB write";
1197 assert(this->frag_color
|| !"FINISHME: MRT");
1198 fs_reg color
= *(variable_storage(this->frag_color
));
1200 for (int i
= 0; i
< 4; i
++) {
1201 emit(fs_inst(BRW_OPCODE_MOV
,
1207 emit(fs_inst(FS_OPCODE_FB_WRITE
,
1211 this->current_annotation
= NULL
;
1215 fs_visitor::generate_fb_write(fs_inst
*inst
)
1217 GLboolean eot
= 1; /* FINISHME: MRT */
1218 /* FINISHME: AADS */
1220 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1223 brw_push_insn_state(p
);
1224 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1225 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1228 brw_vec8_grf(1, 0));
1229 brw_pop_insn_state(p
);
1234 8, /* dispatch_width */
1235 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
1237 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
1238 0, /* FINISHME: MRT target */
1245 fs_visitor::generate_linterp(fs_inst
*inst
,
1246 struct brw_reg dst
, struct brw_reg
*src
)
1248 struct brw_reg delta_x
= src
[0];
1249 struct brw_reg delta_y
= src
[1];
1250 struct brw_reg interp
= src
[2];
1253 delta_y
.nr
== delta_x
.nr
+ 1 &&
1254 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
1255 brw_PLN(p
, dst
, interp
, delta_x
);
1257 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
1258 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
1263 fs_visitor::generate_math(fs_inst
*inst
,
1264 struct brw_reg dst
, struct brw_reg
*src
)
1268 switch (inst
->opcode
) {
1270 op
= BRW_MATH_FUNCTION_INV
;
1273 op
= BRW_MATH_FUNCTION_RSQ
;
1275 case FS_OPCODE_SQRT
:
1276 op
= BRW_MATH_FUNCTION_SQRT
;
1278 case FS_OPCODE_EXP2
:
1279 op
= BRW_MATH_FUNCTION_EXP
;
1281 case FS_OPCODE_LOG2
:
1282 op
= BRW_MATH_FUNCTION_LOG
;
1285 op
= BRW_MATH_FUNCTION_POW
;
1288 op
= BRW_MATH_FUNCTION_SIN
;
1291 op
= BRW_MATH_FUNCTION_COS
;
1294 assert(!"not reached: unknown math function");
1299 if (inst
->opcode
== FS_OPCODE_POW
) {
1300 brw_MOV(p
, brw_message_reg(3), src
[1]);
1305 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
1306 BRW_MATH_SATURATE_NONE
,
1308 BRW_MATH_DATA_VECTOR
,
1309 BRW_MATH_PRECISION_FULL
);
1313 trivial_assign_reg(int header_size
, fs_reg
*reg
)
1315 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
1316 reg
->hw_reg
= header_size
+ reg
->reg
- 1 + reg
->reg_offset
;
1322 fs_visitor::assign_curb_setup()
1324 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
1325 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
1327 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1328 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1329 fs_inst
*inst
= (fs_inst
*)iter
.get();
1331 for (unsigned int i
= 0; i
< 3; i
++) {
1332 if (inst
->src
[i
].file
== UNIFORM
) {
1333 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
1334 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
1338 inst
->src
[i
].file
= FIXED_HW_REG
;
1339 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
1346 fs_visitor::assign_urb_setup()
1348 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
1349 int interp_reg_nr
[FRAG_ATTRIB_MAX
];
1351 c
->prog_data
.urb_read_length
= 0;
1353 /* Figure out where each of the incoming setup attributes lands. */
1354 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
1355 interp_reg_nr
[i
] = -1;
1357 if (i
!= FRAG_ATTRIB_WPOS
&&
1358 !(brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)))
1361 /* Each attribute is 4 setup channels, each of which is half a reg. */
1362 interp_reg_nr
[i
] = urb_start
+ c
->prog_data
.urb_read_length
;
1363 c
->prog_data
.urb_read_length
+= 2;
1366 /* Map the register numbers for FS_OPCODE_LINTERP so that it uses
1367 * the correct setup input.
1369 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1370 fs_inst
*inst
= (fs_inst
*)iter
.get();
1372 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
1375 assert(inst
->src
[2].file
== FIXED_HW_REG
);
1377 int location
= inst
->src
[2].fixed_hw_reg
.nr
/ 2;
1378 assert(interp_reg_nr
[location
] != -1);
1379 inst
->src
[2].fixed_hw_reg
.nr
= (interp_reg_nr
[location
] +
1380 (inst
->src
[2].fixed_hw_reg
.nr
& 1));
1383 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
1387 fs_visitor::assign_regs()
1389 int header_size
= this->first_non_payload_grf
;
1392 /* FINISHME: trivial assignment of register numbers */
1393 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1394 fs_inst
*inst
= (fs_inst
*)iter
.get();
1396 trivial_assign_reg(header_size
, &inst
->dst
);
1397 trivial_assign_reg(header_size
, &inst
->src
[0]);
1398 trivial_assign_reg(header_size
, &inst
->src
[1]);
1400 last_grf
= MAX2(last_grf
, inst
->dst
.hw_reg
);
1401 last_grf
= MAX2(last_grf
, inst
->src
[0].hw_reg
);
1402 last_grf
= MAX2(last_grf
, inst
->src
[1].hw_reg
);
1405 this->grf_used
= last_grf
+ 1;
1408 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
1410 struct brw_reg brw_reg
;
1412 switch (reg
->file
) {
1416 brw_reg
= brw_vec8_reg(reg
->file
,
1418 brw_reg
= retype(brw_reg
, reg
->type
);
1421 switch (reg
->type
) {
1422 case BRW_REGISTER_TYPE_F
:
1423 brw_reg
= brw_imm_f(reg
->imm
.f
);
1425 case BRW_REGISTER_TYPE_D
:
1426 brw_reg
= brw_imm_d(reg
->imm
.i
);
1428 case BRW_REGISTER_TYPE_UD
:
1429 brw_reg
= brw_imm_ud(reg
->imm
.u
);
1432 assert(!"not reached");
1437 brw_reg
= reg
->fixed_hw_reg
;
1440 /* Probably unused. */
1441 brw_reg
= brw_null_reg();
1444 assert(!"not reached");
1445 brw_reg
= brw_null_reg();
1449 brw_reg
= brw_abs(brw_reg
);
1451 brw_reg
= negate(brw_reg
);
1457 fs_visitor::generate_code()
1459 unsigned int annotation_len
= 0;
1460 int last_native_inst
= 0;
1461 struct brw_instruction
*if_stack
[16];
1462 int if_stack_depth
= 0;
1464 memset(&if_stack
, 0, sizeof(if_stack
));
1465 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1466 fs_inst
*inst
= (fs_inst
*)iter
.get();
1467 struct brw_reg src
[3], dst
;
1469 for (unsigned int i
= 0; i
< 3; i
++) {
1470 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
1472 dst
= brw_reg_from_fs_reg(&inst
->dst
);
1474 brw_set_conditionalmod(p
, inst
->conditional_mod
);
1475 brw_set_predicate_control(p
, inst
->predicated
);
1477 switch (inst
->opcode
) {
1478 case BRW_OPCODE_MOV
:
1479 brw_MOV(p
, dst
, src
[0]);
1481 case BRW_OPCODE_ADD
:
1482 brw_ADD(p
, dst
, src
[0], src
[1]);
1484 case BRW_OPCODE_MUL
:
1485 brw_MUL(p
, dst
, src
[0], src
[1]);
1488 case BRW_OPCODE_FRC
:
1489 brw_FRC(p
, dst
, src
[0]);
1491 case BRW_OPCODE_RNDD
:
1492 brw_RNDD(p
, dst
, src
[0]);
1494 case BRW_OPCODE_RNDZ
:
1495 brw_RNDZ(p
, dst
, src
[0]);
1498 case BRW_OPCODE_AND
:
1499 brw_AND(p
, dst
, src
[0], src
[1]);
1502 brw_OR(p
, dst
, src
[0], src
[1]);
1504 case BRW_OPCODE_XOR
:
1505 brw_XOR(p
, dst
, src
[0], src
[1]);
1508 case BRW_OPCODE_CMP
:
1509 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1511 case BRW_OPCODE_SEL
:
1512 brw_SEL(p
, dst
, src
[0], src
[1]);
1516 assert(if_stack_depth
< 16);
1517 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
1520 case BRW_OPCODE_ELSE
:
1521 if_stack
[if_stack_depth
- 1] =
1522 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
1524 case BRW_OPCODE_ENDIF
:
1526 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
1530 case FS_OPCODE_SQRT
:
1531 case FS_OPCODE_EXP2
:
1532 case FS_OPCODE_LOG2
:
1536 generate_math(inst
, dst
, src
);
1538 case FS_OPCODE_LINTERP
:
1539 generate_linterp(inst
, dst
, src
);
1541 case FS_OPCODE_FB_WRITE
:
1542 generate_fb_write(inst
);
1545 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
1546 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
1547 brw_opcodes
[inst
->opcode
].name
);
1549 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
1554 if (annotation_len
< p
->nr_insn
) {
1555 annotation_len
*= 2;
1556 if (annotation_len
< 16)
1557 annotation_len
= 16;
1559 this->annotation_string
= talloc_realloc(this->mem_ctx
,
1563 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
1569 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
1570 this->annotation_string
[i
] = inst
->annotation
;
1571 this->annotation_ir
[i
] = inst
->ir
;
1573 last_native_inst
= p
->nr_insn
;
1578 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
1580 struct brw_compile
*p
= &c
->func
;
1581 struct intel_context
*intel
= &brw
->intel
;
1582 GLcontext
*ctx
= &intel
->ctx
;
1583 struct brw_shader
*shader
= NULL
;
1584 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
1592 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
1593 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
1594 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
1601 /* We always use 8-wide mode, at least for now. For one, flow
1602 * control only works in 8-wide. Also, when we're fragment shader
1603 * bound, we're almost always under register pressure as well, so
1604 * 8-wide would save us from the performance cliff of spilling
1607 c
->dispatch_width
= 8;
1609 if (INTEL_DEBUG
& DEBUG_WM
) {
1610 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
1611 _mesa_print_ir(shader
->ir
, NULL
);
1615 /* Now the main event: Visit the shader IR and generate our FS IR for it.
1617 fs_visitor
v(c
, shader
);
1622 v
.emit_interpolation();
1624 /* Generate FS IR for main(). (the visitor only descends into
1625 * functions called "main").
1627 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
1628 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1637 v
.assign_curb_setup();
1638 v
.assign_urb_setup();
1644 if (INTEL_DEBUG
& DEBUG_WM
) {
1645 const char *last_annotation_string
= NULL
;
1646 ir_instruction
*last_annotation_ir
= NULL
;
1648 printf("Native code for fragment shader %d:\n", prog
->Name
);
1649 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
1650 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
1651 last_annotation_ir
= v
.annotation_ir
[i
];
1652 if (last_annotation_ir
) {
1654 last_annotation_ir
->print();
1658 if (last_annotation_string
!= v
.annotation_string
[i
]) {
1659 last_annotation_string
= v
.annotation_string
[i
];
1660 if (last_annotation_string
)
1661 printf(" %s\n", last_annotation_string
);
1663 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
1668 c
->prog_data
.total_grf
= v
.grf_used
;
1669 c
->prog_data
.total_scratch
= 0;