2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
36 #include "brw_vec4_gs_visitor.h"
38 #include "brw_program.h"
39 #include "brw_dead_control_flow.h"
40 #include "intel_debug.h"
41 #include "compiler/glsl_types.h"
42 #include "compiler/nir/nir_builder.h"
43 #include "program/prog_parameter.h"
47 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
51 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
52 const fs_reg
*src
, unsigned sources
)
54 memset(this, 0, sizeof(*this));
56 this->src
= new fs_reg
[MAX2(sources
, 3)];
57 for (unsigned i
= 0; i
< sources
; i
++)
58 this->src
[i
] = src
[i
];
60 this->opcode
= opcode
;
62 this->sources
= sources
;
63 this->exec_size
= exec_size
;
66 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
68 assert(this->exec_size
!= 0);
70 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
72 /* This will be the case for almost all instructions. */
79 this->size_written
= dst
.component_size(exec_size
);
82 this->size_written
= 0;
86 unreachable("Invalid destination register file");
89 this->writes_accumulator
= false;
94 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
99 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
104 init(opcode
, exec_size
, dst
, NULL
, 0);
107 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg src
[1] = { src0
};
111 init(opcode
, exec_size
, dst
, src
, 1);
114 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
115 const fs_reg
&src0
, const fs_reg
&src1
)
117 const fs_reg src
[2] = { src0
, src1
};
118 init(opcode
, exec_size
, dst
, src
, 2);
121 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
122 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
124 const fs_reg src
[3] = { src0
, src1
, src2
};
125 init(opcode
, exec_size
, dst
, src
, 3);
128 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
129 const fs_reg src
[], unsigned sources
)
131 init(opcode
, exec_width
, dst
, src
, sources
);
134 fs_inst::fs_inst(const fs_inst
&that
)
136 memcpy(this, &that
, sizeof(that
));
138 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
140 for (unsigned i
= 0; i
< that
.sources
; i
++)
141 this->src
[i
] = that
.src
[i
];
150 fs_inst::resize_sources(uint8_t num_sources
)
152 if (this->sources
!= num_sources
) {
153 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
155 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
156 src
[i
] = this->src
[i
];
160 this->sources
= num_sources
;
165 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
167 const fs_reg
&surf_index
,
168 const fs_reg
&varying_offset
,
169 uint32_t const_offset
)
171 /* We have our constant surface use a pitch of 4 bytes, so our index can
172 * be any component of a vector, and then we load 4 contiguous
173 * components starting from that.
175 * We break down the const_offset to a portion added to the variable offset
176 * and a portion done using fs_reg::offset, which means that if you have
177 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
178 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
179 * later notice that those loads are all the same and eliminate the
182 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
183 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
185 /* The pull load message will load a vec4 (16 bytes). If we are loading
186 * a double this means we are only loading 2 elements worth of data.
187 * We also want to use a 32-bit data type for the dst of the load operation
188 * so other parts of the driver don't get confused about the size of the
191 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
192 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
193 vec4_result
, surf_index
, vec4_offset
);
194 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
196 if (type_sz(dst
.type
) == 8) {
197 shuffle_32bit_load_result_to_64bit_data(
198 bld
, retype(vec4_result
, dst
.type
), vec4_result
, 2);
201 vec4_result
.type
= dst
.type
;
202 bld
.MOV(dst
, offset(vec4_result
, bld
,
203 (const_offset
& 0xf) / type_sz(vec4_result
.type
)));
207 * A helper for MOV generation for fixing up broken hardware SEND dependency
211 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
213 /* The caller always wants uncompressed to emit the minimal extra
214 * dependencies, and to avoid having to deal with aligning its regs to 2.
216 const fs_builder ubld
= bld
.annotate("send dependency resolve")
219 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
223 fs_inst::equals(fs_inst
*inst
) const
225 return (opcode
== inst
->opcode
&&
226 dst
.equals(inst
->dst
) &&
227 src
[0].equals(inst
->src
[0]) &&
228 src
[1].equals(inst
->src
[1]) &&
229 src
[2].equals(inst
->src
[2]) &&
230 saturate
== inst
->saturate
&&
231 predicate
== inst
->predicate
&&
232 conditional_mod
== inst
->conditional_mod
&&
233 mlen
== inst
->mlen
&&
234 base_mrf
== inst
->base_mrf
&&
235 target
== inst
->target
&&
237 header_size
== inst
->header_size
&&
238 shadow_compare
== inst
->shadow_compare
&&
239 exec_size
== inst
->exec_size
&&
240 offset
== inst
->offset
);
244 fs_inst::is_send_from_grf() const
247 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
248 case SHADER_OPCODE_SHADER_TIME_ADD
:
249 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
250 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
251 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
252 case SHADER_OPCODE_UNTYPED_ATOMIC
:
253 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
254 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
255 case SHADER_OPCODE_TYPED_ATOMIC
:
256 case SHADER_OPCODE_TYPED_SURFACE_READ
:
257 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
258 case SHADER_OPCODE_URB_WRITE_SIMD8
:
259 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
260 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
261 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
262 case SHADER_OPCODE_URB_READ_SIMD8
:
263 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
265 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
266 return src
[1].file
== VGRF
;
267 case FS_OPCODE_FB_WRITE
:
268 case FS_OPCODE_FB_READ
:
269 return src
[0].file
== VGRF
;
272 return src
[0].file
== VGRF
;
279 * Returns true if this instruction's sources and destinations cannot
280 * safely be the same register.
282 * In most cases, a register can be written over safely by the same
283 * instruction that is its last use. For a single instruction, the
284 * sources are dereferenced before writing of the destination starts
287 * However, there are a few cases where this can be problematic:
289 * - Virtual opcodes that translate to multiple instructions in the
290 * code generator: if src == dst and one instruction writes the
291 * destination before a later instruction reads the source, then
292 * src will have been clobbered.
294 * - SIMD16 compressed instructions with certain regioning (see below).
296 * The register allocator uses this information to set up conflicts between
297 * GRF sources and the destination.
300 fs_inst::has_source_and_destination_hazard() const
303 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
304 /* Multiple partial writes to the destination */
307 /* The SIMD16 compressed instruction
309 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
311 * is actually decoded in hardware as:
313 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
314 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
316 * Which is safe. However, if we have uniform accesses
317 * happening, we get into trouble:
319 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
320 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
322 * Now our destination for the first instruction overwrote the
323 * second instruction's src0, and we get garbage for those 8
324 * pixels. There's a similar issue for the pre-gen6
325 * pixel_x/pixel_y, which are registers of 16-bit values and thus
326 * would get stomped by the first decode as well.
328 if (exec_size
== 16) {
329 for (int i
= 0; i
< sources
; i
++) {
330 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
331 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
332 src
[i
].type
== BRW_REGISTER_TYPE_W
||
333 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
334 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
344 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
346 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
349 fs_reg reg
= this->src
[0];
350 if (reg
.file
!= VGRF
|| reg
.offset
!= 0 || reg
.stride
!= 1)
353 if (grf_alloc
.sizes
[reg
.nr
] * REG_SIZE
!= this->size_written
)
356 for (int i
= 0; i
< this->sources
; i
++) {
357 reg
.type
= this->src
[i
].type
;
358 if (!this->src
[i
].equals(reg
))
361 if (i
< this->header_size
) {
362 reg
.offset
+= REG_SIZE
;
364 reg
= horiz_offset(reg
, this->exec_size
);
372 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
)
374 if (devinfo
->gen
== 6 && is_math())
377 if (is_send_from_grf())
380 if (!backend_instruction::can_do_source_mods())
387 fs_inst::can_change_types() const
389 return dst
.type
== src
[0].type
&&
390 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
391 (opcode
== BRW_OPCODE_MOV
||
392 (opcode
== BRW_OPCODE_SEL
&&
393 dst
.type
== src
[1].type
&&
394 predicate
!= BRW_PREDICATE_NONE
&&
395 !src
[1].abs
&& !src
[1].negate
));
399 fs_inst::has_side_effects() const
401 return this->eot
|| backend_instruction::has_side_effects();
407 memset(this, 0, sizeof(*this));
411 /** Generic unset register constructor. */
415 this->file
= BAD_FILE
;
418 fs_reg::fs_reg(struct ::brw_reg reg
) :
423 if (this->file
== IMM
&&
424 (this->type
!= BRW_REGISTER_TYPE_V
&&
425 this->type
!= BRW_REGISTER_TYPE_UV
&&
426 this->type
!= BRW_REGISTER_TYPE_VF
)) {
432 fs_reg::equals(const fs_reg
&r
) const
434 return (this->backend_reg::equals(r
) &&
439 fs_reg::is_contiguous() const
445 fs_reg::component_size(unsigned width
) const
447 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
450 return MAX2(width
* stride
, 1) * type_sz(type
);
454 type_size_scalar(const struct glsl_type
*type
)
456 unsigned int size
, i
;
458 switch (type
->base_type
) {
461 case GLSL_TYPE_FLOAT
:
463 return type
->components();
464 case GLSL_TYPE_DOUBLE
:
465 case GLSL_TYPE_UINT64
:
466 case GLSL_TYPE_INT64
:
467 return type
->components() * 2;
468 case GLSL_TYPE_ARRAY
:
469 return type_size_scalar(type
->fields
.array
) * type
->length
;
470 case GLSL_TYPE_STRUCT
:
472 for (i
= 0; i
< type
->length
; i
++) {
473 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
476 case GLSL_TYPE_SAMPLER
:
477 /* Samplers take up no register space, since they're baked in at
481 case GLSL_TYPE_ATOMIC_UINT
:
483 case GLSL_TYPE_SUBROUTINE
:
485 case GLSL_TYPE_IMAGE
:
486 return BRW_IMAGE_PARAM_SIZE
;
488 case GLSL_TYPE_ERROR
:
489 case GLSL_TYPE_INTERFACE
:
490 case GLSL_TYPE_FUNCTION
:
491 unreachable("not reached");
498 * Create a MOV to read the timestamp register.
500 * The caller is responsible for emitting the MOV. The return value is
501 * the destination of the MOV, with extra parameters set.
504 fs_visitor::get_timestamp(const fs_builder
&bld
)
506 assert(devinfo
->gen
>= 7);
508 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
511 BRW_REGISTER_TYPE_UD
));
513 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
515 /* We want to read the 3 fields we care about even if it's not enabled in
518 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
524 fs_visitor::emit_shader_time_begin()
526 /* We want only the low 32 bits of the timestamp. Since it's running
527 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
528 * which is plenty of time for our purposes. It is identical across the
529 * EUs, but since it's tracking GPU core speed it will increment at a
530 * varying rate as render P-states change.
532 shader_start_time
= component(
533 get_timestamp(bld
.annotate("shader time start")), 0);
537 fs_visitor::emit_shader_time_end()
539 /* Insert our code just before the final SEND with EOT. */
540 exec_node
*end
= this->instructions
.get_tail();
541 assert(end
&& ((fs_inst
*) end
)->eot
);
542 const fs_builder ibld
= bld
.annotate("shader time end")
543 .exec_all().at(NULL
, end
);
544 const fs_reg timestamp
= get_timestamp(ibld
);
546 /* We only use the low 32 bits of the timestamp - see
547 * emit_shader_time_begin()).
549 * We could also check if render P-states have changed (or anything
550 * else that might disrupt timing) by setting smear to 2 and checking if
551 * that field is != 0.
553 const fs_reg shader_end_time
= component(timestamp
, 0);
555 /* Check that there weren't any timestamp reset events (assuming these
556 * were the only two timestamp reads that happened).
558 const fs_reg reset
= component(timestamp
, 2);
559 set_condmod(BRW_CONDITIONAL_Z
,
560 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
561 ibld
.IF(BRW_PREDICATE_NORMAL
);
563 fs_reg start
= shader_start_time
;
565 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
566 BRW_REGISTER_TYPE_UD
),
568 const fs_builder cbld
= ibld
.group(1, 0);
569 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
571 /* If there were no instructions between the two timestamp gets, the diff
572 * is 2 cycles. Remove that overhead, so I can forget about that when
573 * trying to determine the time taken for single instructions.
575 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
576 SHADER_TIME_ADD(cbld
, 0, diff
);
577 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
578 ibld
.emit(BRW_OPCODE_ELSE
);
579 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
580 ibld
.emit(BRW_OPCODE_ENDIF
);
584 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
585 int shader_time_subindex
,
588 int index
= shader_time_index
* 3 + shader_time_subindex
;
589 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
592 if (dispatch_width
== 8)
593 payload
= vgrf(glsl_type::uvec2_type
);
595 payload
= vgrf(glsl_type::uint_type
);
597 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
601 fs_visitor::vfail(const char *format
, va_list va
)
610 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
611 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
613 this->fail_msg
= msg
;
616 fprintf(stderr
, "%s", msg
);
621 fs_visitor::fail(const char *format
, ...)
625 va_start(va
, format
);
631 * Mark this program as impossible to compile with dispatch width greater
634 * During the SIMD8 compile (which happens first), we can detect and flag
635 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
636 * SIMD16+ compile altogether.
638 * During a compile of dispatch width greater than n (if one happens anyway),
639 * this just calls fail().
642 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
644 if (dispatch_width
> n
) {
647 max_dispatch_width
= n
;
648 compiler
->shader_perf_log(log_data
,
649 "Shader dispatch width limited to SIMD%d: %s",
655 * Returns true if the instruction has a flag that means it won't
656 * update an entire destination register.
658 * For example, dead code elimination and live variable analysis want to know
659 * when a write to a variable screens off any preceding values that were in
663 fs_inst::is_partial_write() const
665 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
666 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
667 !this->dst
.is_contiguous() ||
668 this->dst
.offset
% REG_SIZE
!= 0);
672 fs_inst::components_read(unsigned i
) const
674 /* Return zero if the source is not present. */
675 if (src
[i
].file
== BAD_FILE
)
679 case FS_OPCODE_LINTERP
:
685 case FS_OPCODE_PIXEL_X
:
686 case FS_OPCODE_PIXEL_Y
:
690 case FS_OPCODE_FB_WRITE_LOGICAL
:
691 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
692 /* First/second FB write color. */
694 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
698 case SHADER_OPCODE_TEX_LOGICAL
:
699 case SHADER_OPCODE_TXD_LOGICAL
:
700 case SHADER_OPCODE_TXF_LOGICAL
:
701 case SHADER_OPCODE_TXL_LOGICAL
:
702 case SHADER_OPCODE_TXS_LOGICAL
:
703 case FS_OPCODE_TXB_LOGICAL
:
704 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
705 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
706 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
707 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
708 case SHADER_OPCODE_LOD_LOGICAL
:
709 case SHADER_OPCODE_TG4_LOGICAL
:
710 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
711 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
712 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
713 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
714 /* Texture coordinates. */
715 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
716 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
717 /* Texture derivatives. */
718 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
719 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
720 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
721 /* Texture offset. */
722 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
725 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
730 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
731 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
732 assert(src
[3].file
== IMM
);
733 /* Surface coordinates. */
736 /* Surface operation source (ignored for reads). */
742 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
743 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
744 assert(src
[3].file
== IMM
&&
746 /* Surface coordinates. */
749 /* Surface operation source. */
755 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
756 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
757 assert(src
[3].file
== IMM
&&
759 const unsigned op
= src
[4].ud
;
760 /* Surface coordinates. */
763 /* Surface operation source. */
764 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
766 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
767 op
== BRW_AOP_PREDEC
))
779 fs_inst::size_read(int arg
) const
782 case FS_OPCODE_FB_WRITE
:
783 case FS_OPCODE_FB_READ
:
784 case SHADER_OPCODE_URB_WRITE_SIMD8
:
785 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
786 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
787 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
788 case SHADER_OPCODE_URB_READ_SIMD8
:
789 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
790 case SHADER_OPCODE_UNTYPED_ATOMIC
:
791 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
792 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
793 case SHADER_OPCODE_TYPED_ATOMIC
:
794 case SHADER_OPCODE_TYPED_SURFACE_READ
:
795 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
796 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
798 return mlen
* REG_SIZE
;
801 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
802 /* The payload is actually stored in src1 */
804 return mlen
* REG_SIZE
;
807 case FS_OPCODE_LINTERP
:
812 case SHADER_OPCODE_LOAD_PAYLOAD
:
813 if (arg
< this->header_size
)
817 case CS_OPCODE_CS_TERMINATE
:
818 case SHADER_OPCODE_BARRIER
:
821 case SHADER_OPCODE_MOV_INDIRECT
:
823 assert(src
[2].file
== IMM
);
829 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
830 return mlen
* REG_SIZE
;
834 switch (src
[arg
].file
) {
837 return components_read(arg
) * type_sz(src
[arg
].type
);
843 return components_read(arg
) * src
[arg
].component_size(exec_size
);
845 unreachable("MRF registers are not allowed as sources");
851 /* Return the subset of flag registers that an instruction could
852 * potentially read or write based on the execution controls and flag
853 * subregister number of the instruction.
856 flag_mask(const fs_inst
*inst
)
858 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
859 const unsigned end
= start
+ inst
->exec_size
;
860 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
865 fs_inst::flags_read(const gen_device_info
*devinfo
) const
867 /* XXX - This doesn't consider explicit uses of the flag register as source
870 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
871 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
872 /* The vertical predication modes combine corresponding bits from
873 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
875 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
876 return flag_mask(this) << shift
| flag_mask(this);
877 } else if (predicate
) {
878 return flag_mask(this);
885 fs_inst::flags_written() const
887 /* XXX - This doesn't consider explicit uses of the flag register as
888 * destination region.
890 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
891 opcode
!= BRW_OPCODE_IF
&&
892 opcode
!= BRW_OPCODE_WHILE
)) ||
893 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
894 return flag_mask(this);
901 * Returns how many MRFs an FS opcode will write over.
903 * Note that this is not the 0 or 1 implied writes in an actual gen
904 * instruction -- the FS opcodes often generate MOVs in addition.
907 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
912 if (inst
->base_mrf
== -1)
915 switch (inst
->opcode
) {
916 case SHADER_OPCODE_RCP
:
917 case SHADER_OPCODE_RSQ
:
918 case SHADER_OPCODE_SQRT
:
919 case SHADER_OPCODE_EXP2
:
920 case SHADER_OPCODE_LOG2
:
921 case SHADER_OPCODE_SIN
:
922 case SHADER_OPCODE_COS
:
923 return 1 * dispatch_width
/ 8;
924 case SHADER_OPCODE_POW
:
925 case SHADER_OPCODE_INT_QUOTIENT
:
926 case SHADER_OPCODE_INT_REMAINDER
:
927 return 2 * dispatch_width
/ 8;
928 case SHADER_OPCODE_TEX
:
930 case SHADER_OPCODE_TXD
:
931 case SHADER_OPCODE_TXF
:
932 case SHADER_OPCODE_TXF_CMS
:
933 case SHADER_OPCODE_TXF_MCS
:
934 case SHADER_OPCODE_TG4
:
935 case SHADER_OPCODE_TG4_OFFSET
:
936 case SHADER_OPCODE_TXL
:
937 case SHADER_OPCODE_TXS
:
938 case SHADER_OPCODE_LOD
:
939 case SHADER_OPCODE_SAMPLEINFO
:
941 case FS_OPCODE_FB_WRITE
:
943 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
944 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
946 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
948 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
951 unreachable("not reached");
956 fs_visitor::vgrf(const glsl_type
*const type
)
958 int reg_width
= dispatch_width
/ 8;
959 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
960 brw_type_for_base_type(type
));
963 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
968 this->type
= BRW_REGISTER_TYPE_F
;
969 this->stride
= (file
== UNIFORM
? 0 : 1);
972 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
978 this->stride
= (file
== UNIFORM
? 0 : 1);
981 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
982 * This brings in those uniform definitions
985 fs_visitor::import_uniforms(fs_visitor
*v
)
987 this->push_constant_loc
= v
->push_constant_loc
;
988 this->pull_constant_loc
= v
->pull_constant_loc
;
989 this->uniforms
= v
->uniforms
;
993 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
995 assert(stage
== MESA_SHADER_FRAGMENT
);
998 bld
.MOV(wpos
, this->pixel_x
);
999 wpos
= offset(wpos
, bld
, 1);
1001 /* gl_FragCoord.y */
1002 bld
.MOV(wpos
, this->pixel_y
);
1003 wpos
= offset(wpos
, bld
, 1);
1005 /* gl_FragCoord.z */
1006 if (devinfo
->gen
>= 6) {
1007 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1009 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1010 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1011 interp_reg(VARYING_SLOT_POS
, 2));
1013 wpos
= offset(wpos
, bld
, 1);
1015 /* gl_FragCoord.w: Already set up in emit_interpolation */
1016 bld
.MOV(wpos
, this->wpos_w
);
1019 enum brw_barycentric_mode
1020 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1022 /* Barycentric modes don't make sense for flat inputs. */
1023 assert(mode
!= INTERP_MODE_FLAT
);
1027 case nir_intrinsic_load_barycentric_pixel
:
1028 case nir_intrinsic_load_barycentric_at_offset
:
1029 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1031 case nir_intrinsic_load_barycentric_centroid
:
1032 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1034 case nir_intrinsic_load_barycentric_sample
:
1035 case nir_intrinsic_load_barycentric_at_sample
:
1036 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1039 unreachable("invalid intrinsic");
1042 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1045 return (enum brw_barycentric_mode
) bary
;
1049 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1051 static enum brw_barycentric_mode
1052 centroid_to_pixel(enum brw_barycentric_mode bary
)
1054 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1055 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1056 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1060 fs_visitor::emit_frontfacing_interpolation()
1062 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1064 if (devinfo
->gen
>= 6) {
1065 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1066 * a boolean result from this (~0/true or 0/false).
1068 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1069 * this task in only one instruction:
1070 * - a negation source modifier will flip the bit; and
1071 * - a W -> D type conversion will sign extend the bit into the high
1072 * word of the destination.
1074 * An ASR 15 fills the low word of the destination.
1076 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1079 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1081 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1082 * a boolean result from this (1/true or 0/false).
1084 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1085 * the negation source modifier to flip it. Unfortunately the SHR
1086 * instruction only operates on UD (or D with an abs source modifier)
1087 * sources without negation.
1089 * Instead, use ASR (which will give ~0/true or 0/false).
1091 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1094 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1101 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1103 assert(stage
== MESA_SHADER_FRAGMENT
);
1104 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1105 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1107 if (wm_prog_data
->persample_dispatch
) {
1108 /* Convert int_sample_pos to floating point */
1109 bld
.MOV(dst
, int_sample_pos
);
1110 /* Scale to the range [0, 1] */
1111 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1114 /* From ARB_sample_shading specification:
1115 * "When rendering to a non-multisample buffer, or if multisample
1116 * rasterization is disabled, gl_SamplePosition will always be
1119 bld
.MOV(dst
, brw_imm_f(0.5f
));
1124 fs_visitor::emit_samplepos_setup()
1126 assert(devinfo
->gen
>= 6);
1128 const fs_builder abld
= bld
.annotate("compute sample position");
1129 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1131 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1132 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1134 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1135 * mode will be enabled.
1137 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1138 * R31.1:0 Position Offset X/Y for Slot[3:0]
1139 * R31.3:2 Position Offset X/Y for Slot[7:4]
1142 * The X, Y sample positions come in as bytes in thread payload. So, read
1143 * the positions using vstride=16, width=8, hstride=2.
1145 struct brw_reg sample_pos_reg
=
1146 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1147 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1149 if (dispatch_width
== 8) {
1150 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1152 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1153 abld
.half(1).MOV(half(int_sample_x
, 1),
1154 fs_reg(suboffset(sample_pos_reg
, 16)));
1156 /* Compute gl_SamplePosition.x */
1157 compute_sample_position(pos
, int_sample_x
);
1158 pos
= offset(pos
, abld
, 1);
1159 if (dispatch_width
== 8) {
1160 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1162 abld
.half(0).MOV(half(int_sample_y
, 0),
1163 fs_reg(suboffset(sample_pos_reg
, 1)));
1164 abld
.half(1).MOV(half(int_sample_y
, 1),
1165 fs_reg(suboffset(sample_pos_reg
, 17)));
1167 /* Compute gl_SamplePosition.y */
1168 compute_sample_position(pos
, int_sample_y
);
1173 fs_visitor::emit_sampleid_setup()
1175 assert(stage
== MESA_SHADER_FRAGMENT
);
1176 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1177 assert(devinfo
->gen
>= 6);
1179 const fs_builder abld
= bld
.annotate("compute sample id");
1180 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1182 if (!key
->multisample_fbo
) {
1183 /* As per GL_ARB_sample_shading specification:
1184 * "When rendering to a non-multisample buffer, or if multisample
1185 * rasterization is disabled, gl_SampleID will always be zero."
1187 abld
.MOV(*reg
, brw_imm_d(0));
1188 } else if (devinfo
->gen
>= 8) {
1189 /* Sample ID comes in as 4-bit numbers in g1.0:
1191 * 15:12 Slot 3 SampleID (only used in SIMD16)
1192 * 11:8 Slot 2 SampleID (only used in SIMD16)
1193 * 7:4 Slot 1 SampleID
1194 * 3:0 Slot 0 SampleID
1196 * Each slot corresponds to four channels, so we want to replicate each
1197 * half-byte value to 4 channels in a row:
1199 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1200 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1202 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1203 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1205 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1206 * channels to read the first byte (7:0), and the second group of 8
1207 * channels to read the second byte (15:8). Then, we shift right by
1208 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1209 * values into place. Finally, we AND with 0xf to keep the low nibble.
1211 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1212 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1214 * TODO: These payload bits exist on Gen7 too, but they appear to always
1215 * be zero, so this code fails to work. We should find out why.
1217 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1219 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1220 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1221 brw_imm_v(0x44440000));
1222 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1224 const fs_reg t1
= component(fs_reg(VGRF
, alloc
.allocate(1),
1225 BRW_REGISTER_TYPE_D
), 0);
1226 const fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1228 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1229 * 8x multisampling, subspan 0 will represent sample N (where N
1230 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1231 * 7. We can find the value of N by looking at R0.0 bits 7:6
1232 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1233 * (since samples are always delivered in pairs). That is, we
1234 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1235 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1236 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1237 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1238 * populating a temporary variable with the sequence (0, 1, 2, 3),
1239 * and then reading from it using vstride=1, width=4, hstride=0.
1240 * These computations hold good for 4x multisampling as well.
1242 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1243 * the first four slots are sample 0 of subspan 0; the next four
1244 * are sample 1 of subspan 0; the third group is sample 0 of
1245 * subspan 1, and finally sample 1 of subspan 1.
1248 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1249 * accomodate 16x MSAA.
1251 abld
.exec_all().group(1, 0)
1252 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1254 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1256 /* This works for both SIMD8 and SIMD16 */
1257 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1259 /* This special instruction takes care of setting vstride=1,
1260 * width=4, hstride=0 of t2 during an ADD instruction.
1262 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1269 fs_visitor::emit_samplemaskin_setup()
1271 assert(stage
== MESA_SHADER_FRAGMENT
);
1272 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1273 assert(devinfo
->gen
>= 6);
1275 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1277 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1278 BRW_REGISTER_TYPE_D
));
1280 if (wm_prog_data
->persample_dispatch
) {
1281 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1282 * and a mask representing which sample is being processed by the
1283 * current shader invocation.
1285 * From the OES_sample_variables specification:
1286 * "When per-sample shading is active due to the use of a fragment input
1287 * qualified by "sample" or due to the use of the gl_SampleID or
1288 * gl_SamplePosition variables, only the bit for the current sample is
1289 * set in gl_SampleMaskIn."
1291 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1293 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1294 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1296 fs_reg one
= vgrf(glsl_type::int_type
);
1297 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1298 abld
.MOV(one
, brw_imm_d(1));
1299 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1300 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1302 /* In per-pixel mode, the coverage mask is sufficient. */
1303 *reg
= coverage_mask
;
1309 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1311 if (!src
.abs
&& !src
.negate
)
1314 fs_reg temp
= bld
.vgrf(src
.type
);
1321 fs_visitor::emit_discard_jump()
1323 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1325 /* For performance, after a discard, jump to the end of the
1326 * shader if all relevant channels have been discarded.
1328 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1329 discard_jump
->flag_subreg
= 1;
1331 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1332 discard_jump
->predicate_inverse
= true;
1336 fs_visitor::emit_gs_thread_end()
1338 assert(stage
== MESA_SHADER_GEOMETRY
);
1340 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1342 if (gs_compile
->control_data_header_size_bits
> 0) {
1343 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1346 const fs_builder abld
= bld
.annotate("thread end");
1349 if (gs_prog_data
->static_vertex_count
!= -1) {
1350 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1351 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1352 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1353 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1354 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1357 /* Delete now dead instructions. */
1358 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1364 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1368 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1369 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1370 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1373 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1374 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1375 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1376 sources
[1] = this->final_gs_vertex_count
;
1377 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1378 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1386 fs_visitor::assign_curb_setup()
1388 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1390 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1391 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1392 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1393 if (inst
->src
[i
].file
== UNIFORM
) {
1394 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1396 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1397 constant_nr
= push_constant_loc
[uniform_nr
];
1399 /* Section 5.11 of the OpenGL 4.1 spec says:
1400 * "Out-of-bounds reads return undefined values, which include
1401 * values from other variables of the active program or zero."
1402 * Just return the first push constant.
1407 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1410 brw_reg
.abs
= inst
->src
[i
].abs
;
1411 brw_reg
.negate
= inst
->src
[i
].negate
;
1413 assert(inst
->src
[i
].stride
== 0);
1414 inst
->src
[i
] = byte_offset(
1415 retype(brw_reg
, inst
->src
[i
].type
),
1416 inst
->src
[i
].offset
% 4);
1421 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1422 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1426 fs_visitor::calculate_urb_setup()
1428 assert(stage
== MESA_SHADER_FRAGMENT
);
1429 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1430 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1432 memset(prog_data
->urb_setup
, -1,
1433 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1436 /* Figure out where each of the incoming setup attributes lands. */
1437 if (devinfo
->gen
>= 6) {
1438 if (_mesa_bitcount_64(nir
->info
->inputs_read
&
1439 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1440 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1441 * first 16 varying inputs, so we can put them wherever we want.
1442 * Just put them in order.
1444 * This is useful because it means that (a) inputs not used by the
1445 * fragment shader won't take up valuable register space, and (b) we
1446 * won't have to recompile the fragment shader if it gets paired with
1447 * a different vertex (or geometry) shader.
1449 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1450 if (nir
->info
->inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1451 BITFIELD64_BIT(i
)) {
1452 prog_data
->urb_setup
[i
] = urb_next
++;
1456 bool include_vue_header
=
1457 nir
->info
->inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1459 /* We have enough input varyings that the SF/SBE pipeline stage can't
1460 * arbitrarily rearrange them to suit our whim; we have to put them
1461 * in an order that matches the output of the previous pipeline stage
1462 * (geometry or vertex shader).
1464 struct brw_vue_map prev_stage_vue_map
;
1465 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1466 key
->input_slots_valid
,
1467 nir
->info
->separate_shader
);
1469 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1471 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1472 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1474 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1475 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1476 (nir
->info
->inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1477 BITFIELD64_BIT(varying
))) {
1478 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1481 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1484 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1485 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1486 /* Point size is packed into the header, not as a general attribute */
1487 if (i
== VARYING_SLOT_PSIZ
)
1490 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1491 /* The back color slot is skipped when the front color is
1492 * also written to. In addition, some slots can be
1493 * written in the vertex shader and not read in the
1494 * fragment shader. So the register number must always be
1495 * incremented, mapped or not.
1497 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1498 prog_data
->urb_setup
[i
] = urb_next
;
1504 * It's a FS only attribute, and we did interpolation for this attribute
1505 * in SF thread. So, count it here, too.
1507 * See compile_sf_prog() for more info.
1509 if (nir
->info
->inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1510 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1513 prog_data
->num_varying_inputs
= urb_next
;
1517 fs_visitor::assign_urb_setup()
1519 assert(stage
== MESA_SHADER_FRAGMENT
);
1520 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1522 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1524 /* Offset all the urb_setup[] index by the actual position of the
1525 * setup regs, now that the location of the constants has been chosen.
1527 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1528 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1529 assert(inst
->src
[1].file
== FIXED_GRF
);
1530 inst
->src
[1].nr
+= urb_start
;
1533 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1534 assert(inst
->src
[0].file
== FIXED_GRF
);
1535 inst
->src
[0].nr
+= urb_start
;
1539 /* Each attribute is 4 setup channels, each of which is half a reg. */
1540 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1544 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1546 for (int i
= 0; i
< inst
->sources
; i
++) {
1547 if (inst
->src
[i
].file
== ATTR
) {
1548 int grf
= payload
.num_regs
+
1549 prog_data
->curb_read_length
+
1551 inst
->src
[i
].offset
/ REG_SIZE
;
1553 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1555 * VertStride must be used to cross GRF register boundaries. This
1556 * rule implies that elements within a 'Width' cannot cross GRF
1559 * So, for registers that are large enough, we have to split the exec
1560 * size in two and trust the compression state to sort it out.
1562 unsigned total_size
= inst
->exec_size
*
1563 inst
->src
[i
].stride
*
1564 type_sz(inst
->src
[i
].type
);
1566 assert(total_size
<= 2 * REG_SIZE
);
1567 const unsigned exec_size
=
1568 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1570 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1571 struct brw_reg reg
=
1572 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1573 inst
->src
[i
].offset
% REG_SIZE
),
1574 exec_size
* inst
->src
[i
].stride
,
1575 width
, inst
->src
[i
].stride
);
1576 reg
.abs
= inst
->src
[i
].abs
;
1577 reg
.negate
= inst
->src
[i
].negate
;
1585 fs_visitor::assign_vs_urb_setup()
1587 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1589 assert(stage
== MESA_SHADER_VERTEX
);
1591 /* Each attribute is 4 regs. */
1592 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1594 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1596 /* Rewrite all ATTR file references to the hw grf that they land in. */
1597 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1598 convert_attr_sources_to_hw_regs(inst
);
1603 fs_visitor::assign_tcs_single_patch_urb_setup()
1605 assert(stage
== MESA_SHADER_TESS_CTRL
);
1607 /* Rewrite all ATTR file references to HW_REGs. */
1608 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1609 convert_attr_sources_to_hw_regs(inst
);
1614 fs_visitor::assign_tes_urb_setup()
1616 assert(stage
== MESA_SHADER_TESS_EVAL
);
1618 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1620 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1622 /* Rewrite all ATTR file references to HW_REGs. */
1623 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1624 convert_attr_sources_to_hw_regs(inst
);
1629 fs_visitor::assign_gs_urb_setup()
1631 assert(stage
== MESA_SHADER_GEOMETRY
);
1633 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1635 first_non_payload_grf
+=
1636 8 * vue_prog_data
->urb_read_length
* nir
->info
->gs
.vertices_in
;
1638 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1639 /* Rewrite all ATTR file references to GRFs. */
1640 convert_attr_sources_to_hw_regs(inst
);
1646 * Split large virtual GRFs into separate components if we can.
1648 * This is mostly duplicated with what brw_fs_vector_splitting does,
1649 * but that's really conservative because it's afraid of doing
1650 * splitting that doesn't result in real progress after the rest of
1651 * the optimization phases, which would cause infinite looping in
1652 * optimization. We can do it once here, safely. This also has the
1653 * opportunity to split interpolated values, or maybe even uniforms,
1654 * which we don't have at the IR level.
1656 * We want to split, because virtual GRFs are what we register
1657 * allocate and spill (due to contiguousness requirements for some
1658 * instructions), and they're what we naturally generate in the
1659 * codegen process, but most virtual GRFs don't actually need to be
1660 * contiguous sets of GRFs. If we split, we'll end up with reduced
1661 * live intervals and better dead code elimination and coalescing.
1664 fs_visitor::split_virtual_grfs()
1666 /* Compact the register file so we eliminate dead vgrfs. This
1667 * only defines split points for live registers, so if we have
1668 * too large dead registers they will hit assertions later.
1670 compact_virtual_grfs();
1672 int num_vars
= this->alloc
.count
;
1674 /* Count the total number of registers */
1676 int vgrf_to_reg
[num_vars
];
1677 for (int i
= 0; i
< num_vars
; i
++) {
1678 vgrf_to_reg
[i
] = reg_count
;
1679 reg_count
+= alloc
.sizes
[i
];
1682 /* An array of "split points". For each register slot, this indicates
1683 * if this slot can be separated from the previous slot. Every time an
1684 * instruction uses multiple elements of a register (as a source or
1685 * destination), we mark the used slots as inseparable. Then we go
1686 * through and split the registers into the smallest pieces we can.
1688 bool split_points
[reg_count
];
1689 memset(split_points
, 0, sizeof(split_points
));
1691 /* Mark all used registers as fully splittable */
1692 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1693 if (inst
->dst
.file
== VGRF
) {
1694 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1695 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1696 split_points
[reg
+ j
] = true;
1699 for (int i
= 0; i
< inst
->sources
; i
++) {
1700 if (inst
->src
[i
].file
== VGRF
) {
1701 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1702 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1703 split_points
[reg
+ j
] = true;
1708 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1709 if (inst
->dst
.file
== VGRF
) {
1710 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1711 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1712 split_points
[reg
+ j
] = false;
1714 for (int i
= 0; i
< inst
->sources
; i
++) {
1715 if (inst
->src
[i
].file
== VGRF
) {
1716 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1717 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1718 split_points
[reg
+ j
] = false;
1723 int new_virtual_grf
[reg_count
];
1724 int new_reg_offset
[reg_count
];
1727 for (int i
= 0; i
< num_vars
; i
++) {
1728 /* The first one should always be 0 as a quick sanity check. */
1729 assert(split_points
[reg
] == false);
1732 new_reg_offset
[reg
] = 0;
1737 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1738 /* If this is a split point, reset the offset to 0 and allocate a
1739 * new virtual GRF for the previous offset many registers
1741 if (split_points
[reg
]) {
1742 assert(offset
<= MAX_VGRF_SIZE
);
1743 int grf
= alloc
.allocate(offset
);
1744 for (int k
= reg
- offset
; k
< reg
; k
++)
1745 new_virtual_grf
[k
] = grf
;
1748 new_reg_offset
[reg
] = offset
;
1753 /* The last one gets the original register number */
1754 assert(offset
<= MAX_VGRF_SIZE
);
1755 alloc
.sizes
[i
] = offset
;
1756 for (int k
= reg
- offset
; k
< reg
; k
++)
1757 new_virtual_grf
[k
] = i
;
1759 assert(reg
== reg_count
);
1761 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1762 if (inst
->dst
.file
== VGRF
) {
1763 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1764 inst
->dst
.nr
= new_virtual_grf
[reg
];
1765 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
1766 inst
->dst
.offset
% REG_SIZE
;
1767 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1769 for (int i
= 0; i
< inst
->sources
; i
++) {
1770 if (inst
->src
[i
].file
== VGRF
) {
1771 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1772 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1773 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
1774 inst
->src
[i
].offset
% REG_SIZE
;
1775 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1779 invalidate_live_intervals();
1783 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1785 * During code generation, we create tons of temporary variables, many of
1786 * which get immediately killed and are never used again. Yet, in later
1787 * optimization and analysis passes, such as compute_live_intervals, we need
1788 * to loop over all the virtual GRFs. Compacting them can save a lot of
1792 fs_visitor::compact_virtual_grfs()
1794 bool progress
= false;
1795 int remap_table
[this->alloc
.count
];
1796 memset(remap_table
, -1, sizeof(remap_table
));
1798 /* Mark which virtual GRFs are used. */
1799 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1800 if (inst
->dst
.file
== VGRF
)
1801 remap_table
[inst
->dst
.nr
] = 0;
1803 for (int i
= 0; i
< inst
->sources
; i
++) {
1804 if (inst
->src
[i
].file
== VGRF
)
1805 remap_table
[inst
->src
[i
].nr
] = 0;
1809 /* Compact the GRF arrays. */
1811 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1812 if (remap_table
[i
] == -1) {
1813 /* We just found an unused register. This means that we are
1814 * actually going to compact something.
1818 remap_table
[i
] = new_index
;
1819 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1820 invalidate_live_intervals();
1825 this->alloc
.count
= new_index
;
1827 /* Patch all the instructions to use the newly renumbered registers */
1828 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1829 if (inst
->dst
.file
== VGRF
)
1830 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1832 for (int i
= 0; i
< inst
->sources
; i
++) {
1833 if (inst
->src
[i
].file
== VGRF
)
1834 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1838 /* Patch all the references to delta_xy, since they're used in register
1839 * allocation. If they're unused, switch them to BAD_FILE so we don't
1840 * think some random VGRF is delta_xy.
1842 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1843 if (delta_xy
[i
].file
== VGRF
) {
1844 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1845 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1847 delta_xy
[i
].file
= BAD_FILE
;
1856 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
,
1857 unsigned *max_chunk_bitsize
,
1858 bool contiguous
, unsigned bitsize
,
1859 const unsigned target_bitsize
,
1860 int *push_constant_loc
, int *pull_constant_loc
,
1861 unsigned *num_push_constants
,
1862 unsigned *num_pull_constants
,
1863 const unsigned max_push_components
,
1864 const unsigned max_chunk_size
,
1865 struct brw_stage_prog_data
*stage_prog_data
)
1867 /* This is the first live uniform in the chunk */
1868 if (*chunk_start
< 0)
1869 *chunk_start
= uniform
;
1871 /* Keep track of the maximum bit size access in contiguous uniforms */
1872 *max_chunk_bitsize
= MAX2(*max_chunk_bitsize
, bitsize
);
1874 /* If this element does not need to be contiguous with the next, we
1875 * split at this point and everything between chunk_start and u forms a
1879 /* If bitsize doesn't match the target one, skip it */
1880 if (*max_chunk_bitsize
!= target_bitsize
) {
1881 /* FIXME: right now we only support 32 and 64-bit accesses */
1882 assert(*max_chunk_bitsize
== 4 || *max_chunk_bitsize
== 8);
1883 *max_chunk_bitsize
= 0;
1888 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
1890 /* Decide whether we should push or pull this parameter. In the
1891 * Vulkan driver, push constants are explicitly exposed via the API
1892 * so we push everything. In GL, we only push small arrays.
1894 if (stage_prog_data
->pull_param
== NULL
||
1895 (*num_push_constants
+ chunk_size
<= max_push_components
&&
1896 chunk_size
<= max_chunk_size
)) {
1897 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
1898 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1899 push_constant_loc
[j
] = (*num_push_constants
)++;
1901 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1902 pull_constant_loc
[j
] = (*num_pull_constants
)++;
1905 *max_chunk_bitsize
= 0;
1911 * Assign UNIFORM file registers to either push constants or pull constants.
1913 * We allow a fragment shader to have more than the specified minimum
1914 * maximum number of fragment shader uniform components (64). If
1915 * there are too many of these, they'd fill up all of register space.
1916 * So, this will push some of them out to the pull constant buffer and
1917 * update the program to load them.
1920 fs_visitor::assign_constant_locations()
1922 /* Only the first compile gets to decide on locations. */
1923 if (dispatch_width
!= min_dispatch_width
)
1926 bool is_live
[uniforms
];
1927 memset(is_live
, 0, sizeof(is_live
));
1928 unsigned bitsize_access
[uniforms
];
1929 memset(bitsize_access
, 0, sizeof(bitsize_access
));
1931 /* For each uniform slot, a value of true indicates that the given slot and
1932 * the next slot must remain contiguous. This is used to keep us from
1933 * splitting arrays apart.
1935 bool contiguous
[uniforms
];
1936 memset(contiguous
, 0, sizeof(contiguous
));
1938 int thread_local_id_index
=
1939 (stage
== MESA_SHADER_COMPUTE
) ?
1940 brw_cs_prog_data(stage_prog_data
)->thread_local_id_index
: -1;
1942 /* First, we walk through the instructions and do two things:
1944 * 1) Figure out which uniforms are live.
1946 * 2) Mark any indirectly used ranges of registers as contiguous.
1948 * Note that we don't move constant-indexed accesses to arrays. No
1949 * testing has been done of the performance impact of this choice.
1951 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1952 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1953 if (inst
->src
[i
].file
!= UNIFORM
)
1956 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1958 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
1959 assert(inst
->src
[2].ud
% 4 == 0);
1960 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
1961 assert(last
< uniforms
);
1963 for (unsigned j
= constant_nr
; j
< last
; j
++) {
1965 contiguous
[j
] = true;
1966 bitsize_access
[j
] = MAX2(bitsize_access
[j
], type_sz(inst
->src
[i
].type
));
1968 is_live
[last
] = true;
1969 bitsize_access
[last
] = MAX2(bitsize_access
[last
], type_sz(inst
->src
[i
].type
));
1971 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
1972 int regs_read
= inst
->components_read(i
) *
1973 type_sz(inst
->src
[i
].type
) / 4;
1974 for (int j
= 0; j
< regs_read
; j
++) {
1975 is_live
[constant_nr
+ j
] = true;
1976 bitsize_access
[constant_nr
+ j
] =
1977 MAX2(bitsize_access
[constant_nr
+ j
], type_sz(inst
->src
[i
].type
));
1984 if (thread_local_id_index
>= 0 && !is_live
[thread_local_id_index
])
1985 thread_local_id_index
= -1;
1987 /* Only allow 16 registers (128 uniform components) as push constants.
1989 * Just demote the end of the list. We could probably do better
1990 * here, demoting things that are rarely used in the program first.
1992 * If changing this value, note the limitation about total_regs in
1995 unsigned int max_push_components
= 16 * 8;
1996 if (thread_local_id_index
>= 0)
1997 max_push_components
--; /* Save a slot for the thread ID */
1999 /* We push small arrays, but no bigger than 16 floats. This is big enough
2000 * for a vec4 but hopefully not large enough to push out other stuff. We
2001 * should probably use a better heuristic at some point.
2003 const unsigned int max_chunk_size
= 16;
2005 unsigned int num_push_constants
= 0;
2006 unsigned int num_pull_constants
= 0;
2008 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2009 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2011 /* Default to -1 meaning no location */
2012 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2013 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2015 int chunk_start
= -1;
2016 unsigned max_chunk_bitsize
= 0;
2018 /* First push 64-bit uniforms to ensure they are properly aligned */
2019 const unsigned uniform_64_bit_size
= type_sz(BRW_REGISTER_TYPE_DF
);
2020 for (unsigned u
= 0; u
< uniforms
; u
++) {
2024 set_push_pull_constant_loc(u
, &chunk_start
, &max_chunk_bitsize
,
2025 contiguous
[u
], bitsize_access
[u
],
2026 uniform_64_bit_size
,
2027 push_constant_loc
, pull_constant_loc
,
2028 &num_push_constants
, &num_pull_constants
,
2029 max_push_components
, max_chunk_size
,
2034 /* Then push the rest of uniforms */
2035 const unsigned uniform_32_bit_size
= type_sz(BRW_REGISTER_TYPE_F
);
2036 for (unsigned u
= 0; u
< uniforms
; u
++) {
2040 /* Skip thread_local_id_index to put it in the last push register. */
2041 if (thread_local_id_index
== (int)u
)
2044 set_push_pull_constant_loc(u
, &chunk_start
, &max_chunk_bitsize
,
2045 contiguous
[u
], bitsize_access
[u
],
2046 uniform_32_bit_size
,
2047 push_constant_loc
, pull_constant_loc
,
2048 &num_push_constants
, &num_pull_constants
,
2049 max_push_components
, max_chunk_size
,
2053 /* Add the CS local thread ID uniform at the end of the push constants */
2054 if (thread_local_id_index
>= 0)
2055 push_constant_loc
[thread_local_id_index
] = num_push_constants
++;
2057 /* As the uniforms are going to be reordered, take the data from a temporary
2058 * copy of the original param[].
2060 gl_constant_value
**param
= ralloc_array(NULL
, gl_constant_value
*,
2061 stage_prog_data
->nr_params
);
2062 memcpy(param
, stage_prog_data
->param
,
2063 sizeof(gl_constant_value
*) * stage_prog_data
->nr_params
);
2064 stage_prog_data
->nr_params
= num_push_constants
;
2065 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2067 /* Up until now, the param[] array has been indexed by reg + offset
2068 * of UNIFORM registers. Move pull constants into pull_param[] and
2069 * condense param[] to only contain the uniforms we chose to push.
2071 * NOTE: Because we are condensing the params[] array, we know that
2072 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2073 * having to make a copy.
2075 int new_thread_local_id_index
= -1;
2076 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2077 const gl_constant_value
*value
= param
[i
];
2079 if (pull_constant_loc
[i
] != -1) {
2080 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2081 } else if (push_constant_loc
[i
] != -1) {
2082 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2083 if (thread_local_id_index
== (int)i
)
2084 new_thread_local_id_index
= push_constant_loc
[i
];
2089 if (stage
== MESA_SHADER_COMPUTE
)
2090 brw_cs_prog_data(stage_prog_data
)->thread_local_id_index
=
2091 new_thread_local_id_index
;
2095 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2096 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2099 fs_visitor::lower_constant_loads()
2101 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2103 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2104 /* Set up the annotation tracking for new generated instructions. */
2105 const fs_builder
ibld(this, block
, inst
);
2107 for (int i
= 0; i
< inst
->sources
; i
++) {
2108 if (inst
->src
[i
].file
!= UNIFORM
)
2111 /* We'll handle this case later */
2112 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2115 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
2116 if (location
>= uniforms
)
2117 continue; /* Out of bounds access */
2119 int pull_index
= pull_constant_loc
[location
];
2121 if (pull_index
== -1)
2124 assert(inst
->src
[i
].stride
== 0);
2126 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2127 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2128 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2129 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2130 const unsigned base
= pull_index
* 4;
2132 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2133 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2135 /* Rewrite the instruction to use the temporary VGRF. */
2136 inst
->src
[i
].file
= VGRF
;
2137 inst
->src
[i
].nr
= dst
.nr
;
2138 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2139 inst
->src
[i
].offset
% 4;
2141 brw_mark_surface_used(prog_data
, index
);
2144 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2145 inst
->src
[0].file
== UNIFORM
) {
2147 unsigned location
= inst
->src
[0].nr
+ inst
->src
[0].offset
/ 4;
2148 if (location
>= uniforms
)
2149 continue; /* Out of bounds access */
2151 int pull_index
= pull_constant_loc
[location
];
2153 if (pull_index
== -1)
2156 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2160 inst
->remove(block
);
2162 brw_mark_surface_used(prog_data
, index
);
2165 invalidate_live_intervals();
2169 fs_visitor::opt_algebraic()
2171 bool progress
= false;
2173 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2174 switch (inst
->opcode
) {
2175 case BRW_OPCODE_MOV
:
2176 if (inst
->src
[0].file
!= IMM
)
2179 if (inst
->saturate
) {
2180 if (inst
->dst
.type
!= inst
->src
[0].type
)
2181 assert(!"unimplemented: saturate mixed types");
2183 if (brw_saturate_immediate(inst
->dst
.type
,
2184 &inst
->src
[0].as_brw_reg())) {
2185 inst
->saturate
= false;
2191 case BRW_OPCODE_MUL
:
2192 if (inst
->src
[1].file
!= IMM
)
2196 if (inst
->src
[1].is_one()) {
2197 inst
->opcode
= BRW_OPCODE_MOV
;
2198 inst
->src
[1] = reg_undef
;
2204 if (inst
->src
[1].is_negative_one()) {
2205 inst
->opcode
= BRW_OPCODE_MOV
;
2206 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2207 inst
->src
[1] = reg_undef
;
2213 if (inst
->src
[1].is_zero()) {
2214 inst
->opcode
= BRW_OPCODE_MOV
;
2215 inst
->src
[0] = inst
->src
[1];
2216 inst
->src
[1] = reg_undef
;
2221 if (inst
->src
[0].file
== IMM
) {
2222 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2223 inst
->opcode
= BRW_OPCODE_MOV
;
2224 inst
->src
[0].f
*= inst
->src
[1].f
;
2225 inst
->src
[1] = reg_undef
;
2230 case BRW_OPCODE_ADD
:
2231 if (inst
->src
[1].file
!= IMM
)
2235 if (inst
->src
[1].is_zero()) {
2236 inst
->opcode
= BRW_OPCODE_MOV
;
2237 inst
->src
[1] = reg_undef
;
2242 if (inst
->src
[0].file
== IMM
) {
2243 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2244 inst
->opcode
= BRW_OPCODE_MOV
;
2245 inst
->src
[0].f
+= inst
->src
[1].f
;
2246 inst
->src
[1] = reg_undef
;
2252 if (inst
->src
[0].equals(inst
->src
[1])) {
2253 inst
->opcode
= BRW_OPCODE_MOV
;
2254 inst
->src
[1] = reg_undef
;
2259 case BRW_OPCODE_LRP
:
2260 if (inst
->src
[1].equals(inst
->src
[2])) {
2261 inst
->opcode
= BRW_OPCODE_MOV
;
2262 inst
->src
[0] = inst
->src
[1];
2263 inst
->src
[1] = reg_undef
;
2264 inst
->src
[2] = reg_undef
;
2269 case BRW_OPCODE_CMP
:
2270 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2272 inst
->src
[0].negate
&&
2273 inst
->src
[1].is_zero()) {
2274 inst
->src
[0].abs
= false;
2275 inst
->src
[0].negate
= false;
2276 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2281 case BRW_OPCODE_SEL
:
2282 if (inst
->src
[0].equals(inst
->src
[1])) {
2283 inst
->opcode
= BRW_OPCODE_MOV
;
2284 inst
->src
[1] = reg_undef
;
2285 inst
->predicate
= BRW_PREDICATE_NONE
;
2286 inst
->predicate_inverse
= false;
2288 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2289 switch (inst
->conditional_mod
) {
2290 case BRW_CONDITIONAL_LE
:
2291 case BRW_CONDITIONAL_L
:
2292 switch (inst
->src
[1].type
) {
2293 case BRW_REGISTER_TYPE_F
:
2294 if (inst
->src
[1].f
>= 1.0f
) {
2295 inst
->opcode
= BRW_OPCODE_MOV
;
2296 inst
->src
[1] = reg_undef
;
2297 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2305 case BRW_CONDITIONAL_GE
:
2306 case BRW_CONDITIONAL_G
:
2307 switch (inst
->src
[1].type
) {
2308 case BRW_REGISTER_TYPE_F
:
2309 if (inst
->src
[1].f
<= 0.0f
) {
2310 inst
->opcode
= BRW_OPCODE_MOV
;
2311 inst
->src
[1] = reg_undef
;
2312 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2324 case BRW_OPCODE_MAD
:
2325 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2326 inst
->opcode
= BRW_OPCODE_MOV
;
2327 inst
->src
[1] = reg_undef
;
2328 inst
->src
[2] = reg_undef
;
2330 } else if (inst
->src
[0].is_zero()) {
2331 inst
->opcode
= BRW_OPCODE_MUL
;
2332 inst
->src
[0] = inst
->src
[2];
2333 inst
->src
[2] = reg_undef
;
2335 } else if (inst
->src
[1].is_one()) {
2336 inst
->opcode
= BRW_OPCODE_ADD
;
2337 inst
->src
[1] = inst
->src
[2];
2338 inst
->src
[2] = reg_undef
;
2340 } else if (inst
->src
[2].is_one()) {
2341 inst
->opcode
= BRW_OPCODE_ADD
;
2342 inst
->src
[2] = reg_undef
;
2344 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2345 inst
->opcode
= BRW_OPCODE_ADD
;
2346 inst
->src
[1].f
*= inst
->src
[2].f
;
2347 inst
->src
[2] = reg_undef
;
2351 case SHADER_OPCODE_BROADCAST
:
2352 if (is_uniform(inst
->src
[0])) {
2353 inst
->opcode
= BRW_OPCODE_MOV
;
2355 inst
->force_writemask_all
= true;
2357 } else if (inst
->src
[1].file
== IMM
) {
2358 inst
->opcode
= BRW_OPCODE_MOV
;
2359 inst
->src
[0] = component(inst
->src
[0],
2362 inst
->force_writemask_all
= true;
2371 /* Swap if src[0] is immediate. */
2372 if (progress
&& inst
->is_commutative()) {
2373 if (inst
->src
[0].file
== IMM
) {
2374 fs_reg tmp
= inst
->src
[1];
2375 inst
->src
[1] = inst
->src
[0];
2384 * Optimize sample messages that have constant zero values for the trailing
2385 * texture coordinates. We can just reduce the message length for these
2386 * instructions instead of reserving a register for it. Trailing parameters
2387 * that aren't sent default to zero anyway. This will cause the dead code
2388 * eliminator to remove the MOV instruction that would otherwise be emitted to
2389 * set up the zero value.
2392 fs_visitor::opt_zero_samples()
2394 /* Gen4 infers the texturing opcode based on the message length so we can't
2397 if (devinfo
->gen
< 5)
2400 bool progress
= false;
2402 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2403 if (!inst
->is_tex())
2406 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2408 if (load_payload
->is_head_sentinel() ||
2409 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2412 /* We don't want to remove the message header or the first parameter.
2413 * Removing the first parameter is not allowed, see the Haswell PRM
2414 * volume 7, page 149:
2416 * "Parameter 0 is required except for the sampleinfo message, which
2417 * has no parameter 0"
2419 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2420 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2421 (inst
->exec_size
/ 8) +
2422 inst
->header_size
- 1].is_zero()) {
2423 inst
->mlen
-= inst
->exec_size
/ 8;
2429 invalidate_live_intervals();
2435 * Optimize sample messages which are followed by the final RT write.
2437 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2438 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2439 * final texturing results copied to the framebuffer write payload and modify
2440 * them to write to the framebuffer directly.
2443 fs_visitor::opt_sampler_eot()
2445 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2447 if (stage
!= MESA_SHADER_FRAGMENT
)
2450 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2453 /* FINISHME: It should be possible to implement this optimization when there
2454 * are multiple drawbuffers.
2456 if (key
->nr_color_regions
!= 1)
2459 /* Requires emitting a bunch of saturating MOV instructions during logical
2460 * send lowering to clamp the color payload, which the sampler unit isn't
2461 * going to do for us.
2463 if (key
->clamp_fragment_color
)
2466 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2467 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2468 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2469 assert(fb_write
->eot
);
2470 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2472 /* There wasn't one; nothing to do. */
2473 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2476 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2478 /* 3D Sampler » Messages » Message Format
2480 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2481 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2483 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2484 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2485 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2486 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2487 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2488 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2489 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2490 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2493 /* XXX - This shouldn't be necessary. */
2494 if (tex_inst
->prev
->is_head_sentinel())
2497 /* Check that the FB write sources are fully initialized by the single
2498 * texturing instruction.
2500 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2501 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2502 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2503 fb_write
->size_read(i
) != tex_inst
->size_written
)
2505 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2506 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2511 assert(!tex_inst
->eot
); /* We can't get here twice */
2512 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2514 const fs_builder
ibld(this, block
, tex_inst
);
2516 tex_inst
->offset
|= fb_write
->target
<< 24;
2517 tex_inst
->eot
= true;
2518 tex_inst
->dst
= ibld
.null_reg_ud();
2519 tex_inst
->size_written
= 0;
2520 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2522 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2523 * flag and submit a header together with the sampler message as required
2526 invalidate_live_intervals();
2531 fs_visitor::opt_register_renaming()
2533 bool progress
= false;
2536 int remap
[alloc
.count
];
2537 memset(remap
, -1, sizeof(int) * alloc
.count
);
2539 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2540 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2542 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2543 inst
->opcode
== BRW_OPCODE_WHILE
) {
2547 /* Rewrite instruction sources. */
2548 for (int i
= 0; i
< inst
->sources
; i
++) {
2549 if (inst
->src
[i
].file
== VGRF
&&
2550 remap
[inst
->src
[i
].nr
] != -1 &&
2551 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2552 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2557 const int dst
= inst
->dst
.nr
;
2560 inst
->dst
.file
== VGRF
&&
2561 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
2562 !inst
->is_partial_write()) {
2563 if (remap
[dst
] == -1) {
2566 remap
[dst
] = alloc
.allocate(regs_written(inst
));
2567 inst
->dst
.nr
= remap
[dst
];
2570 } else if (inst
->dst
.file
== VGRF
&&
2572 remap
[dst
] != dst
) {
2573 inst
->dst
.nr
= remap
[dst
];
2579 invalidate_live_intervals();
2581 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2582 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2583 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2592 * Remove redundant or useless discard jumps.
2594 * For example, we can eliminate jumps in the following sequence:
2596 * discard-jump (redundant with the next jump)
2597 * discard-jump (useless; jumps to the next instruction)
2601 fs_visitor::opt_redundant_discard_jumps()
2603 bool progress
= false;
2605 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2607 fs_inst
*placeholder_halt
= NULL
;
2608 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2609 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2610 placeholder_halt
= inst
;
2615 if (!placeholder_halt
)
2618 /* Delete any HALTs immediately before the placeholder halt. */
2619 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2620 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2621 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2622 prev
->remove(last_bblock
);
2627 invalidate_live_intervals();
2633 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2634 * from \p r.offset which overlaps the region starting at \p s.offset and
2635 * spanning \p ds bytes.
2637 static inline unsigned
2638 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
2640 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
2641 const int shift
= rel_offset
/ REG_SIZE
;
2642 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
2643 assert(reg_space(r
) == reg_space(s
) &&
2644 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
2645 return ((1 << n
) - 1) << shift
;
2649 fs_visitor::compute_to_mrf()
2651 bool progress
= false;
2654 /* No MRFs on Gen >= 7. */
2655 if (devinfo
->gen
>= 7)
2658 calculate_live_intervals();
2660 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2664 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2665 inst
->is_partial_write() ||
2666 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2667 inst
->dst
.type
!= inst
->src
[0].type
||
2668 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2669 !inst
->src
[0].is_contiguous() ||
2670 inst
->src
[0].offset
% REG_SIZE
!= 0)
2673 /* Can't compute-to-MRF this GRF if someone else was going to
2676 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2679 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2680 * things that computed the value of all GRFs of the source region. The
2681 * regs_left bitset keeps track of the registers we haven't yet found a
2682 * generating instruction for.
2684 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
2686 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2687 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2688 inst
->src
[0], inst
->size_read(0))) {
2689 /* Found the last thing to write our reg we want to turn
2690 * into a compute-to-MRF.
2693 /* If this one instruction didn't populate all the
2694 * channels, bail. We might be able to rewrite everything
2695 * that writes that reg, but it would require smarter
2698 if (scan_inst
->is_partial_write())
2701 /* Handling things not fully contained in the source of the copy
2702 * would need us to understand coalescing out more than one MOV at
2705 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
2706 inst
->src
[0], inst
->size_read(0)))
2709 /* SEND instructions can't have MRF as a destination. */
2710 if (scan_inst
->mlen
)
2713 if (devinfo
->gen
== 6) {
2714 /* gen6 math instructions must have the destination be
2715 * GRF, so no compute-to-MRF for them.
2717 if (scan_inst
->is_math()) {
2722 /* Clear the bits for any registers this instruction overwrites. */
2723 regs_left
&= ~mask_relative_to(
2724 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2729 /* We don't handle control flow here. Most computation of
2730 * values that end up in MRFs are shortly before the MRF
2733 if (block
->start() == scan_inst
)
2736 /* You can't read from an MRF, so if someone else reads our
2737 * MRF's source GRF that we wanted to rewrite, that stops us.
2739 bool interfered
= false;
2740 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2741 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
2742 inst
->src
[0], inst
->size_read(0))) {
2749 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2750 inst
->dst
, inst
->size_written
)) {
2751 /* If somebody else writes our MRF here, we can't
2752 * compute-to-MRF before that.
2757 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2758 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2759 inst
->dst
, inst
->size_written
)) {
2760 /* Found a SEND instruction, which means that there are
2761 * live values in MRFs from base_mrf to base_mrf +
2762 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2772 /* Found all generating instructions of our MRF's source value, so it
2773 * should be safe to rewrite them to point to the MRF directly.
2775 regs_left
= (1 << regs_read(inst
, 0)) - 1;
2777 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2778 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2779 inst
->src
[0], inst
->size_read(0))) {
2780 /* Clear the bits for any registers this instruction overwrites. */
2781 regs_left
&= ~mask_relative_to(
2782 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2784 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
2785 reg_offset(inst
->src
[0]);
2787 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2788 /* Apply the same address transformation done by the hardware
2789 * for COMPR4 MRF writes.
2791 assert(rel_offset
< 2 * REG_SIZE
);
2792 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
2794 /* Clear the COMPR4 bit if the generating instruction is not
2797 if (scan_inst
->size_written
< 2 * REG_SIZE
)
2798 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2801 /* Calculate the MRF number the result of this instruction is
2802 * ultimately written to.
2804 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
2807 scan_inst
->dst
.file
= MRF
;
2808 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
2809 scan_inst
->saturate
|= inst
->saturate
;
2816 inst
->remove(block
);
2821 invalidate_live_intervals();
2827 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2828 * flow. We could probably do better here with some form of divergence
2832 fs_visitor::eliminate_find_live_channel()
2834 bool progress
= false;
2837 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
2838 /* The optimization below assumes that channel zero is live on thread
2839 * dispatch, which may not be the case if the fixed function dispatches
2845 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2846 switch (inst
->opcode
) {
2852 case BRW_OPCODE_ENDIF
:
2853 case BRW_OPCODE_WHILE
:
2857 case FS_OPCODE_DISCARD_JUMP
:
2858 /* This can potentially make control flow non-uniform until the end
2863 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2865 inst
->opcode
= BRW_OPCODE_MOV
;
2866 inst
->src
[0] = brw_imm_ud(0u);
2868 inst
->force_writemask_all
= true;
2882 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2883 * instructions to FS_OPCODE_REP_FB_WRITE.
2886 fs_visitor::emit_repclear_shader()
2888 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2890 int color_mrf
= base_mrf
+ 2;
2894 mov
= bld
.exec_all().group(4, 0)
2895 .MOV(brw_message_reg(color_mrf
),
2896 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2898 struct brw_reg reg
=
2899 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2900 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
2901 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2903 mov
= bld
.exec_all().group(4, 0)
2904 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2908 if (key
->nr_color_regions
== 1) {
2909 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2910 write
->saturate
= key
->clamp_fragment_color
;
2911 write
->base_mrf
= color_mrf
;
2913 write
->header_size
= 0;
2916 assume(key
->nr_color_regions
> 0);
2917 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2918 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2919 write
->saturate
= key
->clamp_fragment_color
;
2920 write
->base_mrf
= base_mrf
;
2922 write
->header_size
= 2;
2930 assign_constant_locations();
2931 assign_curb_setup();
2933 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2935 assert(mov
->src
[0].file
== FIXED_GRF
);
2936 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2941 * Walks through basic blocks, looking for repeated MRF writes and
2942 * removing the later ones.
2945 fs_visitor::remove_duplicate_mrf_writes()
2947 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2948 bool progress
= false;
2950 /* Need to update the MRF tracking for compressed instructions. */
2951 if (dispatch_width
>= 16)
2954 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2956 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2957 if (inst
->is_control_flow()) {
2958 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2961 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2962 inst
->dst
.file
== MRF
) {
2963 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2964 if (prev_inst
&& inst
->equals(prev_inst
)) {
2965 inst
->remove(block
);
2971 /* Clear out the last-write records for MRFs that were overwritten. */
2972 if (inst
->dst
.file
== MRF
) {
2973 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2976 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2977 /* Found a SEND instruction, which will include two or fewer
2978 * implied MRF writes. We could do better here.
2980 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2981 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2985 /* Clear out any MRF move records whose sources got overwritten. */
2986 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2987 if (last_mrf_move
[i
] &&
2988 regions_overlap(inst
->dst
, inst
->size_written
,
2989 last_mrf_move
[i
]->src
[0],
2990 last_mrf_move
[i
]->size_read(0))) {
2991 last_mrf_move
[i
] = NULL
;
2995 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2996 inst
->dst
.file
== MRF
&&
2997 inst
->src
[0].file
!= ARF
&&
2998 !inst
->is_partial_write()) {
2999 last_mrf_move
[inst
->dst
.nr
] = inst
;
3004 invalidate_live_intervals();
3010 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3012 /* Clear the flag for registers that actually got read (as expected). */
3013 for (int i
= 0; i
< inst
->sources
; i
++) {
3015 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3016 grf
= inst
->src
[i
].nr
;
3021 if (grf
>= first_grf
&&
3022 grf
< first_grf
+ grf_len
) {
3023 deps
[grf
- first_grf
] = false;
3024 if (inst
->exec_size
== 16)
3025 deps
[grf
- first_grf
+ 1] = false;
3031 * Implements this workaround for the original 965:
3033 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3034 * check for post destination dependencies on this instruction, software
3035 * must ensure that there is no destination hazard for the case of ‘write
3036 * followed by a posted write’ shown in the following example.
3039 * 2. send r3.xy <rest of send instruction>
3042 * Due to no post-destination dependency check on the ‘send’, the above
3043 * code sequence could have two instructions (1 and 2) in flight at the
3044 * same time that both consider ‘r3’ as the target of their final writes.
3047 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3050 int write_len
= regs_written(inst
);
3051 int first_write_grf
= inst
->dst
.nr
;
3052 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3053 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3055 memset(needs_dep
, false, sizeof(needs_dep
));
3056 memset(needs_dep
, true, write_len
);
3058 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3060 /* Walk backwards looking for writes to registers we're writing which
3061 * aren't read since being written. If we hit the start of the program,
3062 * we assume that there are no outstanding dependencies on entry to the
3065 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3066 /* If we hit control flow, assume that there *are* outstanding
3067 * dependencies, and force their cleanup before our instruction.
3069 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3070 for (int i
= 0; i
< write_len
; i
++) {
3072 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3073 first_write_grf
+ i
);
3078 /* We insert our reads as late as possible on the assumption that any
3079 * instruction but a MOV that might have left us an outstanding
3080 * dependency has more latency than a MOV.
3082 if (scan_inst
->dst
.file
== VGRF
) {
3083 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3084 int reg
= scan_inst
->dst
.nr
+ i
;
3086 if (reg
>= first_write_grf
&&
3087 reg
< first_write_grf
+ write_len
&&
3088 needs_dep
[reg
- first_write_grf
]) {
3089 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3090 needs_dep
[reg
- first_write_grf
] = false;
3091 if (scan_inst
->exec_size
== 16)
3092 needs_dep
[reg
- first_write_grf
+ 1] = false;
3097 /* Clear the flag for registers that actually got read (as expected). */
3098 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3100 /* Continue the loop only if we haven't resolved all the dependencies */
3102 for (i
= 0; i
< write_len
; i
++) {
3112 * Implements this workaround for the original 965:
3114 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3115 * used as a destination register until after it has been sourced by an
3116 * instruction with a different destination register.
3119 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3121 int write_len
= regs_written(inst
);
3122 int first_write_grf
= inst
->dst
.nr
;
3123 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3124 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3126 memset(needs_dep
, false, sizeof(needs_dep
));
3127 memset(needs_dep
, true, write_len
);
3128 /* Walk forwards looking for writes to registers we're writing which aren't
3129 * read before being written.
3131 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3132 /* If we hit control flow, force resolve all remaining dependencies. */
3133 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3134 for (int i
= 0; i
< write_len
; i
++) {
3136 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3137 first_write_grf
+ i
);
3142 /* Clear the flag for registers that actually got read (as expected). */
3143 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3145 /* We insert our reads as late as possible since they're reading the
3146 * result of a SEND, which has massive latency.
3148 if (scan_inst
->dst
.file
== VGRF
&&
3149 scan_inst
->dst
.nr
>= first_write_grf
&&
3150 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3151 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3152 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3154 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3157 /* Continue the loop only if we haven't resolved all the dependencies */
3159 for (i
= 0; i
< write_len
; i
++) {
3169 fs_visitor::insert_gen4_send_dependency_workarounds()
3171 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3174 bool progress
= false;
3176 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3177 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3178 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3179 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3185 invalidate_live_intervals();
3189 * Turns the generic expression-style uniform pull constant load instruction
3190 * into a hardware-specific series of instructions for loading a pull
3193 * The expression style allows the CSE pass before this to optimize out
3194 * repeated loads from the same offset, and gives the pre-register-allocation
3195 * scheduling full flexibility, while the conversion to native instructions
3196 * allows the post-register-allocation scheduler the best information
3199 * Note that execution masking for setting up pull constant loads is special:
3200 * the channels that need to be written are unrelated to the current execution
3201 * mask, since a later instruction will use one of the result channels as a
3202 * source operand for all 8 or 16 of its channels.
3205 fs_visitor::lower_uniform_pull_constant_loads()
3207 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3208 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3211 if (devinfo
->gen
>= 7) {
3212 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3213 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3215 ubld
.group(8, 0).MOV(payload
,
3216 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3217 ubld
.group(1, 0).MOV(component(payload
, 2),
3218 brw_imm_ud(inst
->src
[1].ud
/ 16));
3220 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3221 inst
->src
[1] = payload
;
3222 inst
->header_size
= 1;
3225 invalidate_live_intervals();
3227 /* Before register allocation, we didn't tell the scheduler about the
3228 * MRF we use. We know it's safe to use this MRF because nothing
3229 * else does except for register spill/unspill, which generates and
3230 * uses its MRF within a single IR instruction.
3232 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3239 fs_visitor::lower_load_payload()
3241 bool progress
= false;
3243 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3244 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3247 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3248 assert(inst
->saturate
== false);
3249 fs_reg dst
= inst
->dst
;
3251 /* Get rid of COMPR4. We'll add it back in if we need it */
3252 if (dst
.file
== MRF
)
3253 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3255 const fs_builder
ibld(this, block
, inst
);
3256 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3258 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3259 if (inst
->src
[i
].file
!= BAD_FILE
) {
3260 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3261 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3262 hbld
.MOV(mov_dst
, mov_src
);
3264 dst
= offset(dst
, hbld
, 1);
3267 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3268 inst
->exec_size
> 8) {
3269 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3270 * a straightforward copy. Instead, the result of the
3271 * LOAD_PAYLOAD is treated as interleaved and the first four
3272 * non-header sources are unpacked as:
3283 * This is used for gen <= 5 fb writes.
3285 assert(inst
->exec_size
== 16);
3286 assert(inst
->header_size
+ 4 <= inst
->sources
);
3287 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3288 if (inst
->src
[i
].file
!= BAD_FILE
) {
3289 if (devinfo
->has_compr4
) {
3290 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3291 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3292 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3294 /* Platform doesn't have COMPR4. We have to fake it */
3295 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3296 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3298 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3305 /* The loop above only ever incremented us through the first set
3306 * of 4 registers. However, thanks to the magic of COMPR4, we
3307 * actually wrote to the first 8 registers, so we need to take
3308 * that into account now.
3312 /* The COMPR4 code took care of the first 4 sources. We'll let
3313 * the regular path handle any remaining sources. Yes, we are
3314 * modifying the instruction but we're about to delete it so
3315 * this really doesn't hurt anything.
3317 inst
->header_size
+= 4;
3320 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3321 if (inst
->src
[i
].file
!= BAD_FILE
)
3322 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3323 dst
= offset(dst
, ibld
, 1);
3326 inst
->remove(block
);
3331 invalidate_live_intervals();
3337 fs_visitor::lower_integer_multiplication()
3339 bool progress
= false;
3341 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3342 const fs_builder
ibld(this, block
, inst
);
3344 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3345 if (inst
->dst
.is_accumulator() ||
3346 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3347 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3350 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3351 * operation directly, but CHV/BXT cannot.
3353 if (devinfo
->gen
>= 8 &&
3354 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3357 if (inst
->src
[1].file
== IMM
&&
3358 inst
->src
[1].ud
< (1 << 16)) {
3359 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3360 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3363 * If multiplying by an immediate value that fits in 16-bits, do a
3364 * single MUL instruction with that value in the proper location.
3366 if (devinfo
->gen
< 7) {
3367 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3369 ibld
.MOV(imm
, inst
->src
[1]);
3370 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3372 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3373 ibld
.MUL(inst
->dst
, inst
->src
[0],
3374 ud
? brw_imm_uw(inst
->src
[1].ud
)
3375 : brw_imm_w(inst
->src
[1].d
));
3378 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3379 * do 32-bit integer multiplication in one instruction, but instead
3380 * must do a sequence (which actually calculates a 64-bit result):
3382 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3383 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3384 * mov(8) g2<1>D acc0<8,8,1>D
3386 * But on Gen > 6, the ability to use second accumulator register
3387 * (acc1) for non-float data types was removed, preventing a simple
3388 * implementation in SIMD16. A 16-channel result can be calculated by
3389 * executing the three instructions twice in SIMD8, once with quarter
3390 * control of 1Q for the first eight channels and again with 2Q for
3391 * the second eight channels.
3393 * Which accumulator register is implicitly accessed (by AccWrEnable
3394 * for instance) is determined by the quarter control. Unfortunately
3395 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3396 * implicit accumulator access by an instruction with 2Q will access
3397 * acc1 regardless of whether the data type is usable in acc1.
3399 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3400 * integer data types.
3402 * Since we only want the low 32-bits of the result, we can do two
3403 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3404 * adjust the high result and add them (like the mach is doing):
3406 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3407 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3408 * shl(8) g9<1>D g8<8,8,1>D 16D
3409 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3411 * We avoid the shl instruction by realizing that we only want to add
3412 * the low 16-bits of the "high" result to the high 16-bits of the
3413 * "low" result and using proper regioning on the add:
3415 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3416 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3417 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3419 * Since it does not use the (single) accumulator register, we can
3420 * schedule multi-component multiplications much better.
3423 fs_reg orig_dst
= inst
->dst
;
3424 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3425 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3428 fs_reg low
= inst
->dst
;
3429 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3432 if (devinfo
->gen
>= 7) {
3433 if (inst
->src
[1].file
== IMM
) {
3434 ibld
.MUL(low
, inst
->src
[0],
3435 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3436 ibld
.MUL(high
, inst
->src
[0],
3437 brw_imm_uw(inst
->src
[1].ud
>> 16));
3439 ibld
.MUL(low
, inst
->src
[0],
3440 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3441 ibld
.MUL(high
, inst
->src
[0],
3442 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3445 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
3447 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
3451 ibld
.ADD(subscript(inst
->dst
, BRW_REGISTER_TYPE_UW
, 1),
3452 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3453 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
3455 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3456 set_condmod(inst
->conditional_mod
,
3457 ibld
.MOV(orig_dst
, inst
->dst
));
3461 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3462 /* Should have been lowered to 8-wide. */
3463 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3464 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3466 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3467 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3469 if (devinfo
->gen
>= 8) {
3470 /* Until Gen8, integer multiplies read 32-bits from one source,
3471 * and 16-bits from the other, and relying on the MACH instruction
3472 * to generate the high bits of the result.
3474 * On Gen8, the multiply instruction does a full 32x32-bit
3475 * multiply, but in order to do a 64-bit multiply we can simulate
3476 * the previous behavior and then use a MACH instruction.
3478 * FINISHME: Don't use source modifiers on src1.
3480 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3481 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3482 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3483 mul
->src
[1].stride
*= 2;
3485 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3487 /* Among other things the quarter control bits influence which
3488 * accumulator register is used by the hardware for instructions
3489 * that access the accumulator implicitly (e.g. MACH). A
3490 * second-half instruction would normally map to acc1, which
3491 * doesn't exist on Gen7 and up (the hardware does emulate it for
3492 * floating-point instructions *only* by taking advantage of the
3493 * extra precision of acc0 not normally used for floating point
3496 * HSW and up are careful enough not to try to access an
3497 * accumulator register that doesn't exist, but on earlier Gen7
3498 * hardware we need to make sure that the quarter control bits are
3499 * zero to avoid non-deterministic behaviour and emit an extra MOV
3500 * to get the result masked correctly according to the current
3504 mach
->force_writemask_all
= true;
3505 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3506 ibld
.MOV(inst
->dst
, mach
->dst
);
3512 inst
->remove(block
);
3517 invalidate_live_intervals();
3523 fs_visitor::lower_minmax()
3525 assert(devinfo
->gen
< 6);
3527 bool progress
= false;
3529 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3530 const fs_builder
ibld(this, block
, inst
);
3532 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3533 inst
->predicate
== BRW_PREDICATE_NONE
) {
3534 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3535 * the original SEL.L/GE instruction
3537 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3538 inst
->conditional_mod
);
3539 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3540 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3547 invalidate_live_intervals();
3553 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3554 fs_reg
*dst
, fs_reg color
, unsigned components
)
3556 if (key
->clamp_fragment_color
) {
3557 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3558 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3560 for (unsigned i
= 0; i
< components
; i
++)
3562 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3567 for (unsigned i
= 0; i
< components
; i
++)
3568 dst
[i
] = offset(color
, bld
, i
);
3572 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3573 const struct brw_wm_prog_data
*prog_data
,
3574 const brw_wm_prog_key
*key
,
3575 const fs_visitor::thread_payload
&payload
)
3577 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3578 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3579 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3580 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3581 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3582 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3583 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3584 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3585 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3586 const unsigned components
=
3587 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3589 /* We can potentially have a message length of up to 15, so we have to set
3590 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3593 int header_size
= 2, payload_header_size
;
3594 unsigned length
= 0;
3596 /* From the Sandy Bridge PRM, volume 4, page 198:
3598 * "Dispatched Pixel Enables. One bit per pixel indicating
3599 * which pixels were originally enabled when the thread was
3600 * dispatched. This field is only required for the end-of-
3601 * thread message and on all dual-source messages."
3603 if (devinfo
->gen
>= 6 &&
3604 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3605 color1
.file
== BAD_FILE
&&
3606 key
->nr_color_regions
== 1) {
3610 if (header_size
!= 0) {
3611 assert(header_size
== 2);
3612 /* Allocate 2 registers for a header */
3616 if (payload
.aa_dest_stencil_reg
) {
3617 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3618 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3619 .MOV(sources
[length
],
3620 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3624 if (sample_mask
.file
!= BAD_FILE
) {
3625 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3626 BRW_REGISTER_TYPE_UD
);
3628 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3629 * relevant. Since it's unsigned single words one vgrf is always
3630 * 16-wide, but only the lower or higher 8 channels will be used by the
3631 * hardware when doing a SIMD8 write depending on whether we have
3632 * selected the subspans for the first or second half respectively.
3634 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3635 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3636 sample_mask
.stride
*= 2;
3638 bld
.exec_all().annotate("FB write oMask")
3639 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3645 payload_header_size
= length
;
3647 if (src0_alpha
.file
!= BAD_FILE
) {
3648 /* FIXME: This is being passed at the wrong location in the payload and
3649 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3650 * It's supposed to be immediately before oMask but there seems to be no
3651 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3652 * requires header sources to form a contiguous segment at the beginning
3653 * of the message and src0_alpha has per-channel semantics.
3655 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3657 } else if (key
->replicate_alpha
&& inst
->target
!= 0) {
3658 /* Handle the case when fragment shader doesn't write to draw buffer
3659 * zero. No need to call setup_color_payload() for src0_alpha because
3660 * alpha value will be undefined.
3665 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3668 if (color1
.file
!= BAD_FILE
) {
3669 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3673 if (src_depth
.file
!= BAD_FILE
) {
3674 sources
[length
] = src_depth
;
3678 if (dst_depth
.file
!= BAD_FILE
) {
3679 sources
[length
] = dst_depth
;
3683 if (src_stencil
.file
!= BAD_FILE
) {
3684 assert(devinfo
->gen
>= 9);
3685 assert(bld
.dispatch_width() != 16);
3687 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3688 * available on gen9+. As such it's impossible to have both enabled at the
3689 * same time and therefore length cannot overrun the array.
3691 assert(length
< 15);
3693 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3694 bld
.exec_all().annotate("FB write OS")
3695 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3696 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3701 if (devinfo
->gen
>= 7) {
3702 /* Send from the GRF */
3703 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3704 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3705 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
3706 load
->dst
= payload
;
3708 inst
->src
[0] = payload
;
3709 inst
->resize_sources(1);
3711 /* Send from the MRF */
3712 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3713 sources
, length
, payload_header_size
);
3715 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3716 * will do this for us if we just give it a COMPR4 destination.
3718 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3719 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3721 inst
->resize_sources(0);
3725 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3726 inst
->mlen
= regs_written(load
);
3727 inst
->header_size
= header_size
;
3731 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
3733 const fs_builder
&ubld
= bld
.exec_all();
3734 const unsigned length
= 2;
3735 const fs_reg header
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
, length
);
3738 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3740 inst
->resize_sources(1);
3741 inst
->src
[0] = header
;
3742 inst
->opcode
= FS_OPCODE_FB_READ
;
3743 inst
->mlen
= length
;
3744 inst
->header_size
= length
;
3748 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3749 const fs_reg
&coordinate
,
3750 const fs_reg
&shadow_c
,
3751 const fs_reg
&lod
, const fs_reg
&lod2
,
3752 const fs_reg
&surface
,
3753 const fs_reg
&sampler
,
3754 unsigned coord_components
,
3755 unsigned grad_components
)
3757 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3758 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3759 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3760 fs_reg msg_end
= msg_begin
;
3763 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3765 for (unsigned i
= 0; i
< coord_components
; i
++)
3766 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3767 offset(coordinate
, bld
, i
));
3769 msg_end
= offset(msg_end
, bld
, coord_components
);
3771 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3772 * require all three components to be present and zero if they are unused.
3774 if (coord_components
> 0 &&
3775 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3776 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3777 for (unsigned i
= coord_components
; i
< 3; i
++)
3778 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3780 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3783 if (op
== SHADER_OPCODE_TXD
) {
3784 /* TXD unsupported in SIMD16 mode. */
3785 assert(bld
.dispatch_width() == 8);
3787 /* the slots for u and v are always present, but r is optional */
3788 if (coord_components
< 2)
3789 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3792 * dPdx = dudx, dvdx, drdx
3793 * dPdy = dudy, dvdy, drdy
3795 * 1-arg: Does not exist.
3797 * 2-arg: dudx dvdx dudy dvdy
3798 * dPdx.x dPdx.y dPdy.x dPdy.y
3801 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3802 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3803 * m5 m6 m7 m8 m9 m10
3805 for (unsigned i
= 0; i
< grad_components
; i
++)
3806 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3808 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3810 for (unsigned i
= 0; i
< grad_components
; i
++)
3811 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3813 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3817 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
3818 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
3820 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3821 bld
.dispatch_width() == 16);
3823 const brw_reg_type type
=
3824 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3825 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3826 bld
.MOV(retype(msg_end
, type
), lod
);
3827 msg_end
= offset(msg_end
, bld
, 1);
3830 if (shadow_c
.file
!= BAD_FILE
) {
3831 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3832 /* There's no plain shadow compare message, so we use shadow
3833 * compare with a bias of 0.0.
3835 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3836 msg_end
= offset(msg_end
, bld
, 1);
3839 bld
.MOV(msg_end
, shadow_c
);
3840 msg_end
= offset(msg_end
, bld
, 1);
3844 inst
->src
[0] = reg_undef
;
3845 inst
->src
[1] = surface
;
3846 inst
->src
[2] = sampler
;
3847 inst
->resize_sources(3);
3848 inst
->base_mrf
= msg_begin
.nr
;
3849 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3850 inst
->header_size
= 1;
3854 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3855 const fs_reg
&coordinate
,
3856 const fs_reg
&shadow_c
,
3857 const fs_reg
&lod
, const fs_reg
&lod2
,
3858 const fs_reg
&sample_index
,
3859 const fs_reg
&surface
,
3860 const fs_reg
&sampler
,
3861 unsigned coord_components
,
3862 unsigned grad_components
)
3864 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3865 fs_reg msg_coords
= message
;
3866 unsigned header_size
= 0;
3868 if (inst
->offset
!= 0) {
3869 /* The offsets set up by the visitor are in the m1 header, so we can't
3876 for (unsigned i
= 0; i
< coord_components
; i
++)
3877 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
3878 offset(coordinate
, bld
, i
));
3880 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3881 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3883 if (shadow_c
.file
!= BAD_FILE
) {
3884 fs_reg msg_shadow
= msg_lod
;
3885 bld
.MOV(msg_shadow
, shadow_c
);
3886 msg_lod
= offset(msg_shadow
, bld
, 1);
3891 case SHADER_OPCODE_TXL
:
3893 bld
.MOV(msg_lod
, lod
);
3894 msg_end
= offset(msg_lod
, bld
, 1);
3896 case SHADER_OPCODE_TXD
:
3899 * dPdx = dudx, dvdx, drdx
3900 * dPdy = dudy, dvdy, drdy
3902 * Load up these values:
3903 * - dudx dudy dvdx dvdy drdx drdy
3904 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3907 for (unsigned i
= 0; i
< grad_components
; i
++) {
3908 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
3909 msg_end
= offset(msg_end
, bld
, 1);
3911 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
3912 msg_end
= offset(msg_end
, bld
, 1);
3915 case SHADER_OPCODE_TXS
:
3916 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3917 bld
.MOV(msg_lod
, lod
);
3918 msg_end
= offset(msg_lod
, bld
, 1);
3920 case SHADER_OPCODE_TXF
:
3921 msg_lod
= offset(msg_coords
, bld
, 3);
3922 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3923 msg_end
= offset(msg_lod
, bld
, 1);
3925 case SHADER_OPCODE_TXF_CMS
:
3926 msg_lod
= offset(msg_coords
, bld
, 3);
3928 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3930 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3931 msg_end
= offset(msg_lod
, bld
, 2);
3938 inst
->src
[0] = reg_undef
;
3939 inst
->src
[1] = surface
;
3940 inst
->src
[2] = sampler
;
3941 inst
->resize_sources(3);
3942 inst
->base_mrf
= message
.nr
;
3943 inst
->mlen
= msg_end
.nr
- message
.nr
;
3944 inst
->header_size
= header_size
;
3946 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3947 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3951 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
3953 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3956 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
3960 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3961 const fs_reg
&coordinate
,
3962 const fs_reg
&shadow_c
,
3963 fs_reg lod
, const fs_reg
&lod2
,
3964 const fs_reg
&sample_index
,
3966 const fs_reg
&surface
,
3967 const fs_reg
&sampler
,
3968 const fs_reg
&tg4_offset
,
3969 unsigned coord_components
,
3970 unsigned grad_components
)
3972 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3973 unsigned reg_width
= bld
.dispatch_width() / 8;
3974 unsigned header_size
= 0, length
= 0;
3975 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3976 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3977 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3979 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3980 inst
->offset
!= 0 || inst
->eot
||
3981 op
== SHADER_OPCODE_SAMPLEINFO
||
3982 is_high_sampler(devinfo
, sampler
)) {
3983 /* For general texture offsets (no txf workaround), we need a header to
3984 * put them in. Note that we're only reserving space for it in the
3985 * message payload as it will be initialized implicitly by the
3988 * TG4 needs to place its channel select in the header, for interaction
3989 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3990 * larger sampler numbers we need to offset the Sampler State Pointer in
3994 sources
[0] = fs_reg();
3997 /* If we're requesting fewer than four channels worth of response,
3998 * and we have an explicit header, we need to set up the sampler
3999 * writemask. It's reversed from normal: 1 means "don't write".
4001 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4002 assert(regs_written(inst
) % reg_width
== 0);
4003 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4004 inst
->offset
|= mask
<< 12;
4008 if (shadow_c
.file
!= BAD_FILE
) {
4009 bld
.MOV(sources
[length
], shadow_c
);
4013 bool coordinate_done
= false;
4015 /* Set up the LOD info */
4018 case SHADER_OPCODE_TXL
:
4019 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4020 op
= SHADER_OPCODE_TXL_LZ
;
4023 bld
.MOV(sources
[length
], lod
);
4026 case SHADER_OPCODE_TXD
:
4027 /* TXD should have been lowered in SIMD16 mode. */
4028 assert(bld
.dispatch_width() == 8);
4030 /* Load dPdx and the coordinate together:
4031 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4033 for (unsigned i
= 0; i
< coord_components
; i
++) {
4034 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4036 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4037 * only derivatives for (u, v, r).
4039 if (i
< grad_components
) {
4040 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4041 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4045 coordinate_done
= true;
4047 case SHADER_OPCODE_TXS
:
4048 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4051 case SHADER_OPCODE_TXF
:
4052 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4053 * On Gen9 they are u, v, lod, r
4055 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4057 if (devinfo
->gen
>= 9) {
4058 if (coord_components
>= 2) {
4059 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4060 offset(coordinate
, bld
, 1));
4062 sources
[length
] = brw_imm_d(0);
4067 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4068 op
= SHADER_OPCODE_TXF_LZ
;
4070 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4074 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4075 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4076 offset(coordinate
, bld
, i
));
4078 coordinate_done
= true;
4081 case SHADER_OPCODE_TXF_CMS
:
4082 case SHADER_OPCODE_TXF_CMS_W
:
4083 case SHADER_OPCODE_TXF_UMS
:
4084 case SHADER_OPCODE_TXF_MCS
:
4085 if (op
== SHADER_OPCODE_TXF_UMS
||
4086 op
== SHADER_OPCODE_TXF_CMS
||
4087 op
== SHADER_OPCODE_TXF_CMS_W
) {
4088 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4092 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4093 /* Data from the multisample control surface. */
4094 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4097 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4100 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4101 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4104 offset(mcs
, bld
, 1));
4109 /* There is no offsetting for this message; just copy in the integer
4110 * texture coordinates.
4112 for (unsigned i
= 0; i
< coord_components
; i
++)
4113 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4114 offset(coordinate
, bld
, i
));
4116 coordinate_done
= true;
4118 case SHADER_OPCODE_TG4_OFFSET
:
4119 /* More crazy intermixing */
4120 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4121 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4123 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4124 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4125 offset(tg4_offset
, bld
, i
));
4127 if (coord_components
== 3) /* r if present */
4128 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4130 coordinate_done
= true;
4136 /* Set up the coordinate (except for cases where it was done above) */
4137 if (!coordinate_done
) {
4138 for (unsigned i
= 0; i
< coord_components
; i
++)
4139 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4144 mlen
= length
* reg_width
- header_size
;
4146 mlen
= length
* reg_width
;
4148 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4149 BRW_REGISTER_TYPE_F
);
4150 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4152 /* Generate the SEND. */
4154 inst
->src
[0] = src_payload
;
4155 inst
->src
[1] = surface
;
4156 inst
->src
[2] = sampler
;
4157 inst
->resize_sources(3);
4159 inst
->header_size
= header_size
;
4161 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4162 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4166 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4168 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4169 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4170 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4171 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4172 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4173 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4174 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4175 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4176 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4177 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
4178 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4179 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4180 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4181 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4183 if (devinfo
->gen
>= 7) {
4184 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4185 shadow_c
, lod
, lod2
, sample_index
,
4186 mcs
, surface
, sampler
, tg4_offset
,
4187 coord_components
, grad_components
);
4188 } else if (devinfo
->gen
>= 5) {
4189 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4190 shadow_c
, lod
, lod2
, sample_index
,
4192 coord_components
, grad_components
);
4194 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4195 shadow_c
, lod
, lod2
,
4197 coord_components
, grad_components
);
4202 * Initialize the header present in some typed and untyped surface
4206 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4208 fs_builder ubld
= bld
.exec_all().group(8, 0);
4209 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4210 ubld
.MOV(dst
, brw_imm_d(0));
4211 ubld
.MOV(component(dst
, 7), sample_mask
);
4216 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4217 const fs_reg
&sample_mask
)
4219 /* Get the logical send arguments. */
4220 const fs_reg
&addr
= inst
->src
[0];
4221 const fs_reg
&src
= inst
->src
[1];
4222 const fs_reg
&surface
= inst
->src
[2];
4223 const UNUSED fs_reg
&dims
= inst
->src
[3];
4224 const fs_reg
&arg
= inst
->src
[4];
4226 /* Calculate the total number of components of the payload. */
4227 const unsigned addr_sz
= inst
->components_read(0);
4228 const unsigned src_sz
= inst
->components_read(1);
4229 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4230 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4232 /* Allocate space for the payload. */
4233 fs_reg
*const components
= new fs_reg
[sz
];
4234 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4237 /* Construct the payload. */
4239 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4241 for (unsigned i
= 0; i
< addr_sz
; i
++)
4242 components
[n
++] = offset(addr
, bld
, i
);
4244 for (unsigned i
= 0; i
< src_sz
; i
++)
4245 components
[n
++] = offset(src
, bld
, i
);
4247 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4249 /* Update the original instruction. */
4251 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4252 inst
->header_size
= header_sz
;
4254 inst
->src
[0] = payload
;
4255 inst
->src
[1] = surface
;
4257 inst
->resize_sources(3);
4259 delete[] components
;
4263 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4265 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4267 if (devinfo
->gen
>= 7) {
4268 /* We are switching the instruction from an ALU-like instruction to a
4269 * send-from-grf instruction. Since sends can't handle strides or
4270 * source modifiers, we have to make a copy of the offset source.
4272 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4273 bld
.MOV(tmp
, inst
->src
[1]);
4276 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4279 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4280 BRW_REGISTER_TYPE_UD
);
4282 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4284 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4285 inst
->resize_sources(1);
4286 inst
->base_mrf
= payload
.nr
;
4287 inst
->header_size
= 1;
4288 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4293 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4295 assert(bld
.shader
->devinfo
->gen
< 6);
4298 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4300 if (inst
->sources
> 1) {
4301 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4302 * "Message Payload":
4304 * "Operand0[7]. For the INT DIV functions, this operand is the
4307 * "Operand1[7]. For the INT DIV functions, this operand is the
4310 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4311 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4312 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4314 inst
->resize_sources(1);
4315 inst
->src
[0] = src0
;
4317 assert(inst
->exec_size
== 8);
4318 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4323 fs_visitor::lower_logical_sends()
4325 bool progress
= false;
4327 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4328 const fs_builder
ibld(this, block
, inst
);
4330 switch (inst
->opcode
) {
4331 case FS_OPCODE_FB_WRITE_LOGICAL
:
4332 assert(stage
== MESA_SHADER_FRAGMENT
);
4333 lower_fb_write_logical_send(ibld
, inst
,
4334 brw_wm_prog_data(prog_data
),
4335 (const brw_wm_prog_key
*)key
,
4339 case FS_OPCODE_FB_READ_LOGICAL
:
4340 lower_fb_read_logical_send(ibld
, inst
);
4343 case SHADER_OPCODE_TEX_LOGICAL
:
4344 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4347 case SHADER_OPCODE_TXD_LOGICAL
:
4348 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4351 case SHADER_OPCODE_TXF_LOGICAL
:
4352 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4355 case SHADER_OPCODE_TXL_LOGICAL
:
4356 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4359 case SHADER_OPCODE_TXS_LOGICAL
:
4360 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4363 case FS_OPCODE_TXB_LOGICAL
:
4364 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4367 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4368 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4371 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4372 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4375 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4376 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4379 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4380 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4383 case SHADER_OPCODE_LOD_LOGICAL
:
4384 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4387 case SHADER_OPCODE_TG4_LOGICAL
:
4388 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4391 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4392 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4395 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4396 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4399 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4400 lower_surface_logical_send(ibld
, inst
,
4401 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4405 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4406 lower_surface_logical_send(ibld
, inst
,
4407 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4408 ibld
.sample_mask_reg());
4411 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4412 lower_surface_logical_send(ibld
, inst
,
4413 SHADER_OPCODE_UNTYPED_ATOMIC
,
4414 ibld
.sample_mask_reg());
4417 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4418 lower_surface_logical_send(ibld
, inst
,
4419 SHADER_OPCODE_TYPED_SURFACE_READ
,
4423 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4424 lower_surface_logical_send(ibld
, inst
,
4425 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4426 ibld
.sample_mask_reg());
4429 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4430 lower_surface_logical_send(ibld
, inst
,
4431 SHADER_OPCODE_TYPED_ATOMIC
,
4432 ibld
.sample_mask_reg());
4435 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4436 lower_varying_pull_constant_logical_send(ibld
, inst
);
4439 case SHADER_OPCODE_RCP
:
4440 case SHADER_OPCODE_RSQ
:
4441 case SHADER_OPCODE_SQRT
:
4442 case SHADER_OPCODE_EXP2
:
4443 case SHADER_OPCODE_LOG2
:
4444 case SHADER_OPCODE_SIN
:
4445 case SHADER_OPCODE_COS
:
4446 case SHADER_OPCODE_POW
:
4447 case SHADER_OPCODE_INT_QUOTIENT
:
4448 case SHADER_OPCODE_INT_REMAINDER
:
4449 /* The math opcodes are overloaded for the send-like and
4450 * expression-like instructions which seems kind of icky. Gen6+ has
4451 * a native (but rather quirky) MATH instruction so we don't need to
4452 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4453 * logical instructions (which we can easily recognize because they
4454 * have mlen = 0) into send-like virtual instructions.
4456 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4457 lower_math_logical_send(ibld
, inst
);
4472 invalidate_live_intervals();
4478 * Get the closest allowed SIMD width for instruction \p inst accounting for
4479 * some common regioning and execution control restrictions that apply to FPU
4480 * instructions. These restrictions don't necessarily have any relevance to
4481 * instructions not executed by the FPU pipeline like extended math, control
4482 * flow or send message instructions.
4484 * For virtual opcodes it's really up to the instruction -- In some cases
4485 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4486 * instructions) it may simplify virtual instruction lowering if we can
4487 * enforce FPU-like regioning restrictions already on the virtual instruction,
4488 * in other cases (e.g. virtual send-like instructions) this may be
4489 * excessively restrictive.
4492 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
4493 const fs_inst
*inst
)
4495 /* Maximum execution size representable in the instruction controls. */
4496 unsigned max_width
= MIN2(32, inst
->exec_size
);
4498 /* According to the PRMs:
4499 * "A. In Direct Addressing mode, a source cannot span more than 2
4500 * adjacent GRF registers.
4501 * B. A destination cannot span more than 2 adjacent GRF registers."
4503 * Look for the source or destination with the largest register region
4504 * which is the one that is going to limit the overall execution size of
4505 * the instruction due to this rule.
4507 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4509 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4510 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
4512 /* Calculate the maximum execution size of the instruction based on the
4513 * factor by which it goes over the hardware limit of 2 GRFs.
4516 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4518 /* According to the IVB PRMs:
4519 * "When destination spans two registers, the source MUST span two
4520 * registers. The exception to the above rule:
4522 * - When source is scalar, the source registers are not incremented.
4523 * - When source is packed integer Word and destination is packed
4524 * integer DWord, the source register is not incremented but the
4525 * source sub register is incremented."
4527 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4528 * restrictions. The code below intentionally doesn't check whether the
4529 * destination type is integer because empirically the hardware doesn't
4530 * seem to care what the actual type is as long as it's dword-aligned.
4532 if (devinfo
->gen
< 8) {
4533 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4534 if (inst
->size_written
> REG_SIZE
&&
4535 inst
->size_read(i
) != 0 && inst
->size_read(i
) <= REG_SIZE
&&
4536 !is_uniform(inst
->src
[i
]) &&
4537 !(type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4538 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1)) {
4539 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4540 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4545 /* From the IVB PRMs:
4546 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4547 * are applied for both halves of the SIMD32 instruction. If different
4548 * execution mask channels are required, split the instruction into two
4549 * SIMD16 instructions."
4551 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4552 * 32-wide control flow support in hardware and will behave similarly.
4554 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4555 max_width
= MIN2(max_width
, 16);
4557 /* From the IVB PRMs (applies to HSW too):
4558 * "Instructions with condition modifiers must not use SIMD32."
4560 * From the BDW PRMs (applies to later hardware too):
4561 * "Ternary instruction with condition modifiers must not use SIMD32."
4563 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4564 max_width
= MIN2(max_width
, 16);
4566 /* From the IVB PRMs (applies to other devices that don't have the
4567 * gen_device_info::supports_simd16_3src flag set):
4568 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4569 * SIMD8 is not allowed for DF operations."
4571 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4572 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4574 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
4575 * the 8-bit quarter of the execution mask signals specified in the
4576 * instruction control fields) for the second compressed half of any
4577 * single-precision instruction (for double-precision instructions
4578 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
4579 * the EU will apply the wrong execution controls for the second
4580 * sequential GRF write if the number of channels per GRF is not exactly
4581 * eight in single-precision mode (or four in double-float mode).
4583 * In this situation we calculate the maximum size of the split
4584 * instructions so they only ever write to a single register.
4586 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
4587 !inst
->force_writemask_all
) {
4588 const unsigned channels_per_grf
= inst
->exec_size
/
4589 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4590 unsigned exec_type_size
= 0;
4591 for (int i
= 0; i
< inst
->sources
; i
++) {
4592 if (inst
->src
[i
].file
!= BAD_FILE
)
4593 exec_type_size
= MAX2(exec_type_size
, type_sz(inst
->src
[i
].type
));
4595 assert(exec_type_size
);
4597 /* The hardware shifts exactly 8 channels per compressed half of the
4598 * instruction in single-precision mode and exactly 4 in double-precision.
4600 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
4601 max_width
= MIN2(max_width
, channels_per_grf
);
4604 /* Only power-of-two execution sizes are representable in the instruction
4607 return 1 << _mesa_logbase2(max_width
);
4611 * Get the maximum allowed SIMD width for instruction \p inst accounting for
4612 * various payload size restrictions that apply to sampler message
4615 * This is only intended to provide a maximum theoretical bound for the
4616 * execution size of the message based on the number of argument components
4617 * alone, which in most cases will determine whether the SIMD8 or SIMD16
4618 * variant of the message can be used, though some messages may have
4619 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
4620 * the message length to determine the exact SIMD width and argument count,
4621 * which makes a number of sampler message combinations impossible to
4625 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
4626 const fs_inst
*inst
)
4628 /* Calculate the number of coordinate components that have to be present
4629 * assuming that additional arguments follow the texel coordinates in the
4630 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
4631 * need to pad to four or three components depending on the message,
4632 * pre-ILK we need to pad to at most three components.
4634 const unsigned req_coord_components
=
4635 (devinfo
->gen
>= 7 ||
4636 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
4637 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
4638 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
4641 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
4642 * variant of the TXL or TXF message.
4644 const bool implicit_lod
= devinfo
->gen
>= 9 &&
4645 (inst
->opcode
== SHADER_OPCODE_TXL
||
4646 inst
->opcode
== SHADER_OPCODE_TXF
) &&
4647 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
4649 /* Calculate the total number of argument components that need to be passed
4650 * to the sampler unit.
4652 const unsigned num_payload_components
=
4653 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
4654 req_coord_components
) +
4655 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
4656 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
4657 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
4658 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
4659 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
4660 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
4661 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
4663 /* SIMD16 messages with more than five arguments exceed the maximum message
4664 * size supported by the sampler, regardless of whether a header is
4667 return MIN2(inst
->exec_size
,
4668 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
4672 * Get the closest native SIMD width supported by the hardware for instruction
4673 * \p inst. The instruction will be left untouched by
4674 * fs_visitor::lower_simd_width() if the returned value is equal to the
4675 * original execution size.
4678 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
4679 const fs_inst
*inst
)
4681 switch (inst
->opcode
) {
4682 case BRW_OPCODE_MOV
:
4683 case BRW_OPCODE_SEL
:
4684 case BRW_OPCODE_NOT
:
4685 case BRW_OPCODE_AND
:
4687 case BRW_OPCODE_XOR
:
4688 case BRW_OPCODE_SHR
:
4689 case BRW_OPCODE_SHL
:
4690 case BRW_OPCODE_ASR
:
4691 case BRW_OPCODE_CMPN
:
4692 case BRW_OPCODE_CSEL
:
4693 case BRW_OPCODE_F32TO16
:
4694 case BRW_OPCODE_F16TO32
:
4695 case BRW_OPCODE_BFREV
:
4696 case BRW_OPCODE_BFE
:
4697 case BRW_OPCODE_ADD
:
4698 case BRW_OPCODE_MUL
:
4699 case BRW_OPCODE_AVG
:
4700 case BRW_OPCODE_FRC
:
4701 case BRW_OPCODE_RNDU
:
4702 case BRW_OPCODE_RNDD
:
4703 case BRW_OPCODE_RNDE
:
4704 case BRW_OPCODE_RNDZ
:
4705 case BRW_OPCODE_LZD
:
4706 case BRW_OPCODE_FBH
:
4707 case BRW_OPCODE_FBL
:
4708 case BRW_OPCODE_CBIT
:
4709 case BRW_OPCODE_SAD2
:
4710 case BRW_OPCODE_MAD
:
4711 case BRW_OPCODE_LRP
:
4712 case FS_OPCODE_PACK
:
4713 return get_fpu_lowered_simd_width(devinfo
, inst
);
4715 case BRW_OPCODE_CMP
: {
4716 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4717 * when the destination is a GRF the dependency-clear bit on the flag
4718 * register is cleared early.
4720 * Suggested workarounds are to disable coissuing CMP instructions
4721 * or to split CMP(16) instructions into two CMP(8) instructions.
4723 * We choose to split into CMP(8) instructions since disabling
4724 * coissuing would affect CMP instructions not otherwise affected by
4727 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4728 !inst
->dst
.is_null() ? 8 : ~0);
4729 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4731 case BRW_OPCODE_BFI1
:
4732 case BRW_OPCODE_BFI2
:
4733 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4735 * "Force BFI instructions to be executed always in SIMD8."
4737 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4738 get_fpu_lowered_simd_width(devinfo
, inst
));
4741 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4742 return inst
->exec_size
;
4744 case SHADER_OPCODE_RCP
:
4745 case SHADER_OPCODE_RSQ
:
4746 case SHADER_OPCODE_SQRT
:
4747 case SHADER_OPCODE_EXP2
:
4748 case SHADER_OPCODE_LOG2
:
4749 case SHADER_OPCODE_SIN
:
4750 case SHADER_OPCODE_COS
:
4751 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4754 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4755 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4756 MIN2(8, inst
->exec_size
));
4758 case SHADER_OPCODE_POW
:
4759 /* SIMD16 is only allowed on Gen7+. */
4760 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4761 MIN2(8, inst
->exec_size
));
4763 case SHADER_OPCODE_INT_QUOTIENT
:
4764 case SHADER_OPCODE_INT_REMAINDER
:
4765 /* Integer division is limited to SIMD8 on all generations. */
4766 return MIN2(8, inst
->exec_size
);
4768 case FS_OPCODE_LINTERP
:
4769 case FS_OPCODE_GET_BUFFER_SIZE
:
4770 case FS_OPCODE_DDX_COARSE
:
4771 case FS_OPCODE_DDX_FINE
:
4772 case FS_OPCODE_DDY_COARSE
:
4773 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4774 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4775 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4776 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4777 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4778 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4779 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4780 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4781 return MIN2(16, inst
->exec_size
);
4783 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4784 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4785 * message used to implement varying pull constant loads, so expand it
4786 * to SIMD16. An alternative with longer message payload length but
4787 * shorter return payload would be to use the SIMD8 sampler message that
4788 * takes (header, u, v, r) as parameters instead of (header, u).
4790 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4792 case FS_OPCODE_DDY_FINE
:
4793 /* The implementation of this virtual opcode may require emitting
4794 * compressed Align16 instructions, which are severely limited on some
4797 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4798 * Region Restrictions):
4800 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4801 * and SIMD8 is not allowed for DF operations."
4803 * In this context, "DW operations" means "operations acting on 32-bit
4804 * values", so it includes operations on floats.
4806 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4807 * (Instruction Compression -> Rules and Restrictions):
4809 * "A compressed instruction must be in Align1 access mode. Align16
4810 * mode instructions cannot be compressed."
4812 * Similar text exists in the g45 PRM.
4814 * Empirically, compressed align16 instructions using odd register
4815 * numbers don't appear to work on Sandybridge either.
4817 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4818 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4819 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
4821 case SHADER_OPCODE_MULH
:
4822 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4823 * is 8-wide on Gen7+.
4825 return (devinfo
->gen
>= 7 ? 8 :
4826 get_fpu_lowered_simd_width(devinfo
, inst
));
4828 case FS_OPCODE_FB_WRITE_LOGICAL
:
4829 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4832 assert(devinfo
->gen
!= 6 ||
4833 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4834 inst
->exec_size
== 8);
4835 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4836 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4837 8 : MIN2(16, inst
->exec_size
));
4839 case FS_OPCODE_FB_READ_LOGICAL
:
4840 return MIN2(16, inst
->exec_size
);
4842 case SHADER_OPCODE_TEX_LOGICAL
:
4843 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4844 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4845 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4846 case SHADER_OPCODE_LOD_LOGICAL
:
4847 case SHADER_OPCODE_TG4_LOGICAL
:
4848 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4849 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4850 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4851 return get_sampler_lowered_simd_width(devinfo
, inst
);
4853 case SHADER_OPCODE_TXD_LOGICAL
:
4854 /* TXD is unsupported in SIMD16 mode. */
4857 case SHADER_OPCODE_TXL_LOGICAL
:
4858 case FS_OPCODE_TXB_LOGICAL
:
4859 /* Only one execution size is representable pre-ILK depending on whether
4860 * the shadow reference argument is present.
4862 if (devinfo
->gen
== 4)
4863 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
4865 return get_sampler_lowered_simd_width(devinfo
, inst
);
4867 case SHADER_OPCODE_TXF_LOGICAL
:
4868 case SHADER_OPCODE_TXS_LOGICAL
:
4869 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4870 * messages. Use SIMD16 instead.
4872 if (devinfo
->gen
== 4)
4875 return get_sampler_lowered_simd_width(devinfo
, inst
);
4877 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4878 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4879 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4882 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4883 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4884 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4885 return MIN2(16, inst
->exec_size
);
4887 case SHADER_OPCODE_URB_READ_SIMD8
:
4888 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
4889 case SHADER_OPCODE_URB_WRITE_SIMD8
:
4890 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
4891 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
4892 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
4893 return MIN2(8, inst
->exec_size
);
4895 case SHADER_OPCODE_MOV_INDIRECT
:
4896 /* Prior to Broadwell, we only have 8 address subregisters */
4897 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
4898 2 * REG_SIZE
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
4901 case SHADER_OPCODE_LOAD_PAYLOAD
: {
4902 const unsigned reg_count
=
4903 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
4905 if (reg_count
> 2) {
4906 /* Only LOAD_PAYLOAD instructions with per-channel destination region
4907 * can be easily lowered (which excludes headers and heterogeneous
4910 assert(!inst
->header_size
);
4911 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4912 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
4913 inst
->src
[i
].file
== BAD_FILE
);
4915 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4917 return inst
->exec_size
;
4921 return inst
->exec_size
;
4926 * Return true if splitting out the group of channels of instruction \p inst
4927 * given by lbld.group() requires allocating a temporary for the i-th source
4928 * of the lowered instruction.
4931 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
4933 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
4934 (inst
->components_read(i
) == 1 &&
4935 lbld
.dispatch_width() <= inst
->exec_size
));
4939 * Extract the data that would be consumed by the channel group given by
4940 * lbld.group() from the i-th source region of instruction \p inst and return
4941 * it as result in packed form. If any copy instructions are required they
4942 * will be emitted before the given \p inst in \p block.
4945 emit_unzip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
,
4948 /* Specified channel group from the source region. */
4949 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
4951 if (needs_src_copy(lbld
, inst
, i
)) {
4952 /* Builder of the right width to perform the copy avoiding uninitialized
4953 * data if the lowered execution size is greater than the original
4954 * execution size of the instruction.
4956 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
4957 inst
->exec_size
), 0);
4958 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
4960 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
4961 cbld
.at(block
, inst
)
4962 .MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
4966 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
4967 /* The source is invariant for all dispatch_width-wide groups of the
4970 return inst
->src
[i
];
4973 /* We can just point the lowered instruction at the right channel group
4974 * from the original region.
4981 * Return true if splitting out the group of channels of instruction \p inst
4982 * given by lbld.group() requires allocating a temporary for the destination
4983 * of the lowered instruction and copying the data back to the original
4984 * destination region.
4987 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
4989 /* If the instruction writes more than one component we'll have to shuffle
4990 * the results of multiple lowered instructions in order to make sure that
4991 * they end up arranged correctly in the original destination region.
4993 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
4996 /* If the lowered execution size is larger than the original the result of
4997 * the instruction won't fit in the original destination, so we'll have to
4998 * allocate a temporary in any case.
5000 if (lbld
.dispatch_width() > inst
->exec_size
)
5003 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5004 /* If we already made a copy of the source for other reasons there won't
5005 * be any overlap with the destination.
5007 if (needs_src_copy(lbld
, inst
, i
))
5010 /* In order to keep the logic simple we emit a copy whenever the
5011 * destination region doesn't exactly match an overlapping source, which
5012 * may point at the source and destination not being aligned group by
5013 * group which could cause one of the lowered instructions to overwrite
5014 * the data read from the same source by other lowered instructions.
5016 if (regions_overlap(inst
->dst
, inst
->size_written
,
5017 inst
->src
[i
], inst
->size_read(i
)) &&
5018 !inst
->dst
.equals(inst
->src
[i
]))
5026 * Insert data from a packed temporary into the channel group given by
5027 * lbld.group() of the destination region of instruction \p inst and return
5028 * the temporary as result. If any copy instructions are required they will
5029 * be emitted around the given \p inst in \p block.
5032 emit_zip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
)
5034 /* Builder of the right width to perform the copy avoiding uninitialized
5035 * data if the lowered execution size is greater than the original
5036 * execution size of the instruction.
5038 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5039 inst
->exec_size
), 0);
5041 /* Specified channel group from the destination region. */
5042 const fs_reg dst
= horiz_offset(inst
->dst
, lbld
.group());
5043 const unsigned dst_size
= inst
->size_written
/
5044 inst
->dst
.component_size(inst
->exec_size
);
5046 if (needs_dst_copy(lbld
, inst
)) {
5047 const fs_reg tmp
= lbld
.vgrf(inst
->dst
.type
, dst_size
);
5049 if (inst
->predicate
) {
5050 /* Handle predication by copying the original contents of
5051 * the destination into the temporary before emitting the
5052 * lowered instruction.
5054 for (unsigned k
= 0; k
< dst_size
; ++k
)
5055 cbld
.at(block
, inst
)
5056 .MOV(offset(tmp
, lbld
, k
), offset(dst
, inst
->exec_size
, k
));
5059 for (unsigned k
= 0; k
< dst_size
; ++k
)
5060 cbld
.at(block
, inst
->next
)
5061 .MOV(offset(dst
, inst
->exec_size
, k
), offset(tmp
, lbld
, k
));
5066 /* No need to allocate a temporary for the lowered instruction, just
5067 * take the right group of channels from the original region.
5074 fs_visitor::lower_simd_width()
5076 bool progress
= false;
5078 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5079 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5081 if (lower_width
!= inst
->exec_size
) {
5082 /* Builder matching the original instruction. We may also need to
5083 * emit an instruction of width larger than the original, set the
5084 * execution size of the builder to the highest of both for now so
5085 * we're sure that both cases can be handled.
5087 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5088 const fs_builder ibld
= bld
.at(block
, inst
)
5089 .exec_all(inst
->force_writemask_all
)
5090 .group(max_width
, inst
->group
/ max_width
);
5092 /* Split the copies in chunks of the execution width of either the
5093 * original or the lowered instruction, whichever is lower.
5095 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5096 const unsigned dst_size
= inst
->size_written
/
5097 inst
->dst
.component_size(inst
->exec_size
);
5099 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5101 for (unsigned i
= 0; i
< n
; i
++) {
5102 /* Emit a copy of the original instruction with the lowered width.
5103 * If the EOT flag was set throw it away except for the last
5104 * instruction to avoid killing the thread prematurely.
5106 fs_inst split_inst
= *inst
;
5107 split_inst
.exec_size
= lower_width
;
5108 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
5110 /* Select the correct channel enables for the i-th group, then
5111 * transform the sources and destination and emit the lowered
5114 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5116 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5117 split_inst
.src
[j
] = emit_unzip(lbld
, block
, inst
, j
);
5119 split_inst
.dst
= emit_zip(lbld
, block
, inst
);
5120 split_inst
.size_written
=
5121 split_inst
.dst
.component_size(lower_width
) * dst_size
;
5123 lbld
.emit(split_inst
);
5126 inst
->remove(block
);
5132 invalidate_live_intervals();
5138 fs_visitor::dump_instructions()
5140 dump_instructions(NULL
);
5144 fs_visitor::dump_instructions(const char *name
)
5146 FILE *file
= stderr
;
5147 if (name
&& geteuid() != 0) {
5148 file
= fopen(name
, "w");
5154 calculate_register_pressure();
5155 int ip
= 0, max_pressure
= 0;
5156 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5157 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5158 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5159 dump_instruction(inst
, file
);
5162 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5165 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5166 fprintf(file
, "%4d: ", ip
++);
5167 dump_instruction(inst
, file
);
5171 if (file
!= stderr
) {
5177 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5179 dump_instruction(be_inst
, stderr
);
5183 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5185 fs_inst
*inst
= (fs_inst
*)be_inst
;
5187 if (inst
->predicate
) {
5188 fprintf(file
, "(%cf0.%d) ",
5189 inst
->predicate_inverse
? '-' : '+',
5193 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5195 fprintf(file
, ".sat");
5196 if (inst
->conditional_mod
) {
5197 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5198 if (!inst
->predicate
&&
5199 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5200 inst
->opcode
!= BRW_OPCODE_IF
&&
5201 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5202 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5205 fprintf(file
, "(%d) ", inst
->exec_size
);
5208 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5212 fprintf(file
, "(EOT) ");
5215 switch (inst
->dst
.file
) {
5217 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5220 fprintf(file
, "g%d", inst
->dst
.nr
);
5223 fprintf(file
, "m%d", inst
->dst
.nr
);
5226 fprintf(file
, "(null)");
5229 fprintf(file
, "***u%d***", inst
->dst
.nr
);
5232 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
5235 switch (inst
->dst
.nr
) {
5237 fprintf(file
, "null");
5239 case BRW_ARF_ADDRESS
:
5240 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5242 case BRW_ARF_ACCUMULATOR
:
5243 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5246 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5249 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5254 unreachable("not reached");
5257 if (inst
->dst
.offset
||
5258 (inst
->dst
.file
== VGRF
&&
5259 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
5260 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
5261 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
5262 inst
->dst
.offset
% reg_size
);
5265 if (inst
->dst
.stride
!= 1)
5266 fprintf(file
, "<%u>", inst
->dst
.stride
);
5267 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
5269 for (int i
= 0; i
< inst
->sources
; i
++) {
5270 if (inst
->src
[i
].negate
)
5272 if (inst
->src
[i
].abs
)
5274 switch (inst
->src
[i
].file
) {
5276 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5279 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5282 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5285 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
5288 fprintf(file
, "u%d", inst
->src
[i
].nr
);
5291 fprintf(file
, "(null)");
5294 switch (inst
->src
[i
].type
) {
5295 case BRW_REGISTER_TYPE_F
:
5296 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5298 case BRW_REGISTER_TYPE_DF
:
5299 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5301 case BRW_REGISTER_TYPE_W
:
5302 case BRW_REGISTER_TYPE_D
:
5303 fprintf(file
, "%dd", inst
->src
[i
].d
);
5305 case BRW_REGISTER_TYPE_UW
:
5306 case BRW_REGISTER_TYPE_UD
:
5307 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5309 case BRW_REGISTER_TYPE_VF
:
5310 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5311 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5312 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5313 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5314 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5317 fprintf(file
, "???");
5322 switch (inst
->src
[i
].nr
) {
5324 fprintf(file
, "null");
5326 case BRW_ARF_ADDRESS
:
5327 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5329 case BRW_ARF_ACCUMULATOR
:
5330 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5333 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5336 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5342 if (inst
->src
[i
].offset
||
5343 (inst
->src
[i
].file
== VGRF
&&
5344 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
5345 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
5346 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
5347 inst
->src
[i
].offset
% reg_size
);
5350 if (inst
->src
[i
].abs
)
5353 if (inst
->src
[i
].file
!= IMM
) {
5355 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5356 unsigned hstride
= inst
->src
[i
].hstride
;
5357 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5359 stride
= inst
->src
[i
].stride
;
5362 fprintf(file
, "<%u>", stride
);
5364 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
5367 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5368 fprintf(file
, ", ");
5373 if (inst
->force_writemask_all
)
5374 fprintf(file
, "NoMask ");
5376 if (inst
->exec_size
!= dispatch_width
)
5377 fprintf(file
, "group%d ", inst
->group
);
5379 fprintf(file
, "\n");
5383 * Possibly returns an instruction that set up @param reg.
5385 * Sometimes we want to take the result of some expression/variable
5386 * dereference tree and rewrite the instruction generating the result
5387 * of the tree. When processing the tree, we know that the
5388 * instructions generated are all writing temporaries that are dead
5389 * outside of this tree. So, if we have some instructions that write
5390 * a temporary, we're free to point that temp write somewhere else.
5392 * Note that this doesn't guarantee that the instruction generated
5393 * only reg -- it might be the size=4 destination of a texture instruction.
5396 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5401 end
->is_partial_write() ||
5402 !reg
.equals(end
->dst
)) {
5410 fs_visitor::setup_fs_payload_gen6()
5412 assert(stage
== MESA_SHADER_FRAGMENT
);
5413 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
5415 assert(devinfo
->gen
>= 6);
5417 /* R0-1: masks, pixel X/Y coordinates. */
5418 payload
.num_regs
= 2;
5419 /* R2: only for 32-pixel dispatch.*/
5421 /* R3-26: barycentric interpolation coordinates. These appear in the
5422 * same order that they appear in the brw_barycentric_mode
5423 * enum. Each set of coordinates occupies 2 registers if dispatch width
5424 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5425 * appear if they were enabled using the "Barycentric Interpolation
5426 * Mode" bits in WM_STATE.
5428 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5429 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
5430 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5431 payload
.num_regs
+= 2;
5432 if (dispatch_width
== 16) {
5433 payload
.num_regs
+= 2;
5438 /* R27: interpolated depth if uses source depth */
5439 prog_data
->uses_src_depth
=
5440 (nir
->info
->inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5441 if (prog_data
->uses_src_depth
) {
5442 payload
.source_depth_reg
= payload
.num_regs
;
5444 if (dispatch_width
== 16) {
5445 /* R28: interpolated depth if not SIMD8. */
5450 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5451 prog_data
->uses_src_w
=
5452 (nir
->info
->inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5453 if (prog_data
->uses_src_w
) {
5454 payload
.source_w_reg
= payload
.num_regs
;
5456 if (dispatch_width
== 16) {
5457 /* R30: interpolated W if not SIMD8. */
5462 /* R31: MSAA position offsets. */
5463 if (prog_data
->persample_dispatch
&&
5464 (nir
->info
->system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5465 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5467 * "MSDISPMODE_PERSAMPLE is required in order to select
5470 * So we can only really get sample positions if we are doing real
5471 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5472 * persample dispatch, we hard-code it to 0.5.
5474 prog_data
->uses_pos_offset
= true;
5475 payload
.sample_pos_reg
= payload
.num_regs
;
5479 /* R32: MSAA input coverage mask */
5480 prog_data
->uses_sample_mask
=
5481 (nir
->info
->system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5482 if (prog_data
->uses_sample_mask
) {
5483 assert(devinfo
->gen
>= 7);
5484 payload
.sample_mask_in_reg
= payload
.num_regs
;
5486 if (dispatch_width
== 16) {
5487 /* R33: input coverage mask if not SIMD8. */
5492 /* R34-: bary for 32-pixel. */
5493 /* R58-59: interp W for 32-pixel. */
5495 if (nir
->info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5496 source_depth_to_render_target
= true;
5501 fs_visitor::setup_vs_payload()
5503 /* R0: thread header, R1: urb handles */
5504 payload
.num_regs
= 2;
5508 fs_visitor::setup_gs_payload()
5510 assert(stage
== MESA_SHADER_GEOMETRY
);
5512 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
5513 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
5515 /* R0: thread header, R1: output URB handles */
5516 payload
.num_regs
= 2;
5518 if (gs_prog_data
->include_primitive_id
) {
5519 /* R2: Primitive ID 0..7 */
5523 /* Use a maximum of 24 registers for push-model inputs. */
5524 const unsigned max_push_components
= 24;
5526 /* If pushing our inputs would take too many registers, reduce the URB read
5527 * length (which is in HWords, or 8 registers), and resort to pulling.
5529 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5530 * have to multiply by VerticesIn to obtain the total storage requirement.
5532 if (8 * vue_prog_data
->urb_read_length
* nir
->info
->gs
.vertices_in
>
5533 max_push_components
|| gs_prog_data
->invocations
> 1) {
5534 gs_prog_data
->base
.include_vue_handles
= true;
5536 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5537 payload
.num_regs
+= nir
->info
->gs
.vertices_in
;
5539 vue_prog_data
->urb_read_length
=
5540 ROUND_DOWN_TO(max_push_components
/ nir
->info
->gs
.vertices_in
, 8) / 8;
5545 fs_visitor::setup_cs_payload()
5547 assert(devinfo
->gen
>= 7);
5548 payload
.num_regs
= 1;
5552 fs_visitor::calculate_register_pressure()
5554 invalidate_live_intervals();
5555 calculate_live_intervals();
5557 unsigned num_instructions
= 0;
5558 foreach_block(block
, cfg
)
5559 num_instructions
+= block
->instructions
.length();
5561 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5563 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5564 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5565 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5570 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5572 * The needs_unlit_centroid_workaround ends up producing one of these per
5573 * channel of centroid input, so it's good to clean them up.
5575 * An assumption here is that nothing ever modifies the dispatched pixels
5576 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5577 * dictates that anyway.
5580 fs_visitor::opt_drop_redundant_mov_to_flags()
5582 bool flag_mov_found
[2] = {false};
5583 bool progress
= false;
5585 /* Instructions removed by this pass can only be added if this were true */
5586 if (!devinfo
->needs_unlit_centroid_workaround
)
5589 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5590 if (inst
->is_control_flow()) {
5591 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5592 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5593 if (!flag_mov_found
[inst
->flag_subreg
]) {
5594 flag_mov_found
[inst
->flag_subreg
] = true;
5596 inst
->remove(block
);
5599 } else if (inst
->flags_written()) {
5600 flag_mov_found
[inst
->flag_subreg
] = false;
5608 fs_visitor::optimize()
5610 /* Start by validating the shader we currently have. */
5613 /* bld is the common builder object pointing at the end of the program we
5614 * used to translate it into i965 IR. For the optimization and lowering
5615 * passes coming next, any code added after the end of the program without
5616 * having explicitly called fs_builder::at() clearly points at a mistake.
5617 * Ideally optimization passes wouldn't be part of the visitor so they
5618 * wouldn't have access to bld at all, but they do, so just in case some
5619 * pass forgets to ask for a location explicitly set it to NULL here to
5620 * make it trip. The dispatch width is initialized to a bogus value to
5621 * make sure that optimizations set the execution controls explicitly to
5622 * match the code they are manipulating instead of relying on the defaults.
5624 bld
= fs_builder(this, 64);
5626 assign_constant_locations();
5627 lower_constant_loads();
5631 split_virtual_grfs();
5634 #define OPT(pass, args...) ({ \
5636 bool this_progress = pass(args); \
5638 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5639 char filename[64]; \
5640 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5641 stage_abbrev, dispatch_width, nir->info->name, iteration, pass_num); \
5643 backend_shader::dump_instructions(filename); \
5648 progress = progress || this_progress; \
5652 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5654 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5655 stage_abbrev
, dispatch_width
, nir
->info
->name
);
5657 backend_shader::dump_instructions(filename
);
5660 bool progress
= false;
5664 OPT(opt_drop_redundant_mov_to_flags
);
5671 OPT(remove_duplicate_mrf_writes
);
5675 OPT(opt_copy_propagation
);
5676 OPT(opt_predicated_break
, this);
5677 OPT(opt_cmod_propagation
);
5678 OPT(dead_code_eliminate
);
5679 OPT(opt_peephole_sel
);
5680 OPT(dead_control_flow_eliminate
, this);
5681 OPT(opt_register_renaming
);
5682 OPT(opt_saturate_propagation
);
5683 OPT(register_coalesce
);
5684 OPT(compute_to_mrf
);
5685 OPT(eliminate_find_live_channel
);
5687 OPT(compact_virtual_grfs
);
5693 if (OPT(lower_pack
)) {
5694 OPT(register_coalesce
);
5695 OPT(dead_code_eliminate
);
5698 if (OPT(lower_d2x
)) {
5699 OPT(opt_copy_propagation
);
5700 OPT(dead_code_eliminate
);
5703 OPT(lower_simd_width
);
5705 /* After SIMD lowering just in case we had to unroll the EOT send. */
5706 OPT(opt_sampler_eot
);
5708 OPT(lower_logical_sends
);
5711 OPT(opt_copy_propagation
);
5712 /* Only run after logical send lowering because it's easier to implement
5713 * in terms of physical sends.
5715 if (OPT(opt_zero_samples
))
5716 OPT(opt_copy_propagation
);
5717 /* Run after logical send lowering to give it a chance to CSE the
5718 * LOAD_PAYLOAD instructions created to construct the payloads of
5719 * e.g. texturing messages in cases where it wasn't possible to CSE the
5720 * whole logical instruction.
5723 OPT(register_coalesce
);
5724 OPT(compute_to_mrf
);
5725 OPT(dead_code_eliminate
);
5726 OPT(remove_duplicate_mrf_writes
);
5727 OPT(opt_peephole_sel
);
5730 OPT(opt_redundant_discard_jumps
);
5732 if (OPT(lower_load_payload
)) {
5733 split_virtual_grfs();
5734 OPT(register_coalesce
);
5735 OPT(compute_to_mrf
);
5736 OPT(dead_code_eliminate
);
5739 OPT(opt_combine_constants
);
5740 OPT(lower_integer_multiplication
);
5742 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5743 OPT(opt_cmod_propagation
);
5745 OPT(opt_copy_propagation
);
5746 OPT(dead_code_eliminate
);
5749 lower_uniform_pull_constant_loads();
5755 * Three source instruction must have a GRF/MRF destination register.
5756 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5759 fs_visitor::fixup_3src_null_dest()
5761 bool progress
= false;
5763 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5764 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5765 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5772 invalidate_live_intervals();
5776 fs_visitor::allocate_registers(bool allow_spilling
)
5778 bool allocated_without_spills
;
5780 static const enum instruction_scheduler_mode pre_modes
[] = {
5782 SCHEDULE_PRE_NON_LIFO
,
5786 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
5788 /* Try each scheduling heuristic to see if it can successfully register
5789 * allocate without spilling. They should be ordered by decreasing
5790 * performance but increasing likelihood of allocating.
5792 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5793 schedule_instructions(pre_modes
[i
]);
5796 assign_regs_trivial();
5797 allocated_without_spills
= true;
5799 allocated_without_spills
= assign_regs(false, spill_all
);
5801 if (allocated_without_spills
)
5805 if (!allocated_without_spills
) {
5806 if (!allow_spilling
)
5807 fail("Failure to register allocate and spilling is not allowed.");
5809 /* We assume that any spilling is worse than just dropping back to
5810 * SIMD8. There's probably actually some intermediate point where
5811 * SIMD16 with a couple of spills is still better.
5813 if (dispatch_width
> min_dispatch_width
) {
5814 fail("Failure to register allocate. Reduce number of "
5815 "live scalar values to avoid this.");
5817 compiler
->shader_perf_log(log_data
,
5818 "%s shader triggered register spilling. "
5819 "Try reducing the number of live scalar "
5820 "values to improve performance.\n",
5824 /* Since we're out of heuristics, just go spill registers until we
5825 * get an allocation.
5827 while (!assign_regs(true, spill_all
)) {
5833 /* This must come after all optimization and register allocation, since
5834 * it inserts dead code that happens to have side effects, and it does
5835 * so based on the actual physical registers in use.
5837 insert_gen4_send_dependency_workarounds();
5842 schedule_instructions(SCHEDULE_POST
);
5844 if (last_scratch
> 0) {
5845 MAYBE_UNUSED
unsigned max_scratch_size
= 2 * 1024 * 1024;
5847 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5849 if (stage
== MESA_SHADER_COMPUTE
) {
5850 if (devinfo
->is_haswell
) {
5851 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5852 * field documentation, Haswell supports a minimum of 2kB of
5853 * scratch space for compute shaders, unlike every other stage
5856 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
5857 } else if (devinfo
->gen
<= 7) {
5858 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5859 * field documentation, platforms prior to Haswell measure scratch
5860 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
5862 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
5863 max_scratch_size
= 12 * 1024;
5867 /* We currently only support up to 2MB of scratch space. If we
5868 * need to support more eventually, the documentation suggests
5869 * that we could allocate a larger buffer, and partition it out
5870 * ourselves. We'd just have to undo the hardware's address
5871 * calculation by subtracting (FFTID * Per Thread Scratch Space)
5872 * and then add FFTID * (Larger Per Thread Scratch Space).
5874 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
5875 * Thread Group Tracking > Local Memory/Scratch Space.
5877 assert(prog_data
->total_scratch
< max_scratch_size
);
5882 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5884 assert(stage
== MESA_SHADER_VERTEX
);
5888 if (shader_time_index
>= 0)
5889 emit_shader_time_begin();
5896 compute_clip_distance(clip_planes
);
5900 if (shader_time_index
>= 0)
5901 emit_shader_time_end();
5907 assign_curb_setup();
5908 assign_vs_urb_setup();
5910 fixup_3src_null_dest();
5911 allocate_registers(true);
5917 fs_visitor::run_tcs_single_patch()
5919 assert(stage
== MESA_SHADER_TESS_CTRL
);
5921 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
5923 /* r1-r4 contain the ICP handles. */
5924 payload
.num_regs
= 5;
5926 if (shader_time_index
>= 0)
5927 emit_shader_time_begin();
5929 /* Initialize gl_InvocationID */
5930 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
5931 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5932 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
5933 bld
.MOV(channels_ud
, channels_uw
);
5935 if (tcs_prog_data
->instances
== 1) {
5936 invocation_id
= channels_ud
;
5938 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5940 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
5941 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5942 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5943 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
5944 brw_imm_ud(INTEL_MASK(23, 17)));
5945 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
5947 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
5950 /* Fix the disptach mask */
5951 if (nir
->info
->tess
.tcs_vertices_out
% 8) {
5952 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
5953 brw_imm_ud(nir
->info
->tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
5954 bld
.IF(BRW_PREDICATE_NORMAL
);
5959 if (nir
->info
->tess
.tcs_vertices_out
% 8) {
5960 bld
.emit(BRW_OPCODE_ENDIF
);
5963 /* Emit EOT write; set TR DS Cache bit */
5965 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
5966 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
5967 fs_reg(brw_imm_ud(0)),
5969 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
5970 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
5972 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
5973 bld
.null_reg_ud(), payload
);
5977 if (shader_time_index
>= 0)
5978 emit_shader_time_end();
5987 assign_curb_setup();
5988 assign_tcs_single_patch_urb_setup();
5990 fixup_3src_null_dest();
5991 allocate_registers(true);
5997 fs_visitor::run_tes()
5999 assert(stage
== MESA_SHADER_TESS_EVAL
);
6001 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6002 payload
.num_regs
= 5;
6004 if (shader_time_index
>= 0)
6005 emit_shader_time_begin();
6014 if (shader_time_index
>= 0)
6015 emit_shader_time_end();
6021 assign_curb_setup();
6022 assign_tes_urb_setup();
6024 fixup_3src_null_dest();
6025 allocate_registers(true);
6031 fs_visitor::run_gs()
6033 assert(stage
== MESA_SHADER_GEOMETRY
);
6037 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6039 if (gs_compile
->control_data_header_size_bits
> 0) {
6040 /* Create a VGRF to store accumulated control data bits. */
6041 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6043 /* If we're outputting more than 32 control data bits, then EmitVertex()
6044 * will set control_data_bits to 0 after emitting the first vertex.
6045 * Otherwise, we need to initialize it to 0 here.
6047 if (gs_compile
->control_data_header_size_bits
<= 32) {
6048 const fs_builder abld
= bld
.annotate("initialize control data bits");
6049 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6053 if (shader_time_index
>= 0)
6054 emit_shader_time_begin();
6058 emit_gs_thread_end();
6060 if (shader_time_index
>= 0)
6061 emit_shader_time_end();
6070 assign_curb_setup();
6071 assign_gs_urb_setup();
6073 fixup_3src_null_dest();
6074 allocate_registers(true);
6080 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6082 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
6083 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6085 assert(stage
== MESA_SHADER_FRAGMENT
);
6087 if (devinfo
->gen
>= 6)
6088 setup_fs_payload_gen6();
6090 setup_fs_payload_gen4();
6094 } else if (do_rep_send
) {
6095 assert(dispatch_width
== 16);
6096 emit_repclear_shader();
6098 if (shader_time_index
>= 0)
6099 emit_shader_time_begin();
6101 calculate_urb_setup();
6102 if (nir
->info
->inputs_read
> 0 ||
6103 (nir
->info
->outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
6104 if (devinfo
->gen
< 6)
6105 emit_interpolation_setup_gen4();
6107 emit_interpolation_setup_gen6();
6110 /* We handle discards by keeping track of the still-live pixels in f0.1.
6111 * Initialize it with the dispatched pixels.
6113 if (wm_prog_data
->uses_kill
) {
6114 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6115 discard_init
->flag_subreg
= 1;
6118 /* Generate FS IR for main(). (the visitor only descends into
6119 * functions called "main").
6126 if (wm_prog_data
->uses_kill
)
6127 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6129 if (wm_key
->alpha_test_func
)
6134 if (shader_time_index
>= 0)
6135 emit_shader_time_end();
6141 assign_curb_setup();
6144 fixup_3src_null_dest();
6145 allocate_registers(allow_spilling
);
6155 fs_visitor::run_cs()
6157 assert(stage
== MESA_SHADER_COMPUTE
);
6161 if (shader_time_index
>= 0)
6162 emit_shader_time_begin();
6164 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6165 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6166 const fs_builder abld
= bld
.exec_all().group(1, 0);
6167 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
6168 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6176 emit_cs_terminate();
6178 if (shader_time_index
>= 0)
6179 emit_shader_time_end();
6185 assign_curb_setup();
6187 fixup_3src_null_dest();
6188 allocate_registers(true);
6197 * Return a bitfield where bit n is set if barycentric interpolation mode n
6198 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6200 * We examine the load_barycentric intrinsics rather than looking at input
6201 * variables so that we catch interpolateAtCentroid() messages too, which
6202 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6205 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
6206 const nir_shader
*shader
)
6208 unsigned barycentric_interp_modes
= 0;
6210 nir_foreach_function(f
, shader
) {
6214 nir_foreach_block(block
, f
->impl
) {
6215 nir_foreach_instr(instr
, block
) {
6216 if (instr
->type
!= nir_instr_type_intrinsic
)
6219 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6220 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6223 /* Ignore WPOS; it doesn't require interpolation. */
6224 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6227 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6228 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
6229 nir_intrinsic_interp_mode(intrin
);
6230 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
6231 enum brw_barycentric_mode bary
=
6232 brw_barycentric_mode(interp
, bary_op
);
6234 barycentric_interp_modes
|= 1 << bary
;
6236 if (devinfo
->needs_unlit_centroid_workaround
&&
6237 bary_op
== nir_intrinsic_load_barycentric_centroid
)
6238 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
6243 return barycentric_interp_modes
;
6247 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6248 const nir_shader
*shader
)
6250 prog_data
->flat_inputs
= 0;
6252 nir_foreach_variable(var
, &shader
->inputs
) {
6253 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6255 if (input_index
< 0)
6259 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6260 prog_data
->flat_inputs
|= (1 << input_index
);
6265 computed_depth_mode(const nir_shader
*shader
)
6267 if (shader
->info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6268 switch (shader
->info
->fs
.depth_layout
) {
6269 case FRAG_DEPTH_LAYOUT_NONE
:
6270 case FRAG_DEPTH_LAYOUT_ANY
:
6271 return BRW_PSCDEPTH_ON
;
6272 case FRAG_DEPTH_LAYOUT_GREATER
:
6273 return BRW_PSCDEPTH_ON_GE
;
6274 case FRAG_DEPTH_LAYOUT_LESS
:
6275 return BRW_PSCDEPTH_ON_LE
;
6276 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6277 return BRW_PSCDEPTH_OFF
;
6280 return BRW_PSCDEPTH_OFF
;
6284 * Move load_interpolated_input with simple (payload-based) barycentric modes
6285 * to the top of the program so we don't emit multiple PLNs for the same input.
6287 * This works around CSE not being able to handle non-dominating cases
6293 * interpolate the same exact input
6296 * This should be replaced by global value numbering someday.
6299 move_interpolation_to_top(nir_shader
*nir
)
6301 nir_foreach_function(f
, nir
) {
6305 nir_block
*top
= nir_start_block(f
->impl
);
6306 exec_node
*cursor_node
= NULL
;
6308 nir_foreach_block(block
, f
->impl
) {
6312 nir_foreach_instr_safe(instr
, block
) {
6313 if (instr
->type
!= nir_instr_type_intrinsic
)
6316 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6317 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6319 nir_intrinsic_instr
*bary_intrinsic
=
6320 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6321 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
6323 /* Leave interpolateAtSample/Offset() where they are. */
6324 if (op
== nir_intrinsic_load_barycentric_at_sample
||
6325 op
== nir_intrinsic_load_barycentric_at_offset
)
6328 nir_instr
*move
[3] = {
6329 &bary_intrinsic
->instr
,
6330 intrin
->src
[1].ssa
->parent_instr
,
6334 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
6335 if (move
[i
]->block
!= top
) {
6336 move
[i
]->block
= top
;
6337 exec_node_remove(&move
[i
]->node
);
6339 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
6341 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
6343 cursor_node
= &move
[i
]->node
;
6348 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6349 ((unsigned) nir_metadata_block_index
|
6350 (unsigned) nir_metadata_dominance
));
6355 * Demote per-sample barycentric intrinsics to centroid.
6357 * Useful when rendering to a non-multisampled buffer.
6360 demote_sample_qualifiers(nir_shader
*nir
)
6362 nir_foreach_function(f
, nir
) {
6367 nir_builder_init(&b
, f
->impl
);
6369 nir_foreach_block(block
, f
->impl
) {
6370 nir_foreach_instr_safe(instr
, block
) {
6371 if (instr
->type
!= nir_instr_type_intrinsic
)
6374 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6375 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
6376 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
6379 b
.cursor
= nir_before_instr(instr
);
6380 nir_ssa_def
*centroid
=
6381 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
6382 nir_intrinsic_interp_mode(intrin
));
6383 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
6384 nir_src_for_ssa(centroid
));
6385 nir_instr_remove(instr
);
6389 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6390 ((unsigned) nir_metadata_block_index
|
6391 (unsigned) nir_metadata_dominance
));
6396 * Pre-gen6, the register file of the EUs was shared between threads,
6397 * and each thread used some subset allocated on a 16-register block
6398 * granularity. The unit states wanted these block counts.
6401 brw_register_blocks(int reg_count
)
6403 return ALIGN(reg_count
, 16) / 16 - 1;
6407 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6409 const struct brw_wm_prog_key
*key
,
6410 struct brw_wm_prog_data
*prog_data
,
6411 const nir_shader
*src_shader
,
6412 struct gl_program
*prog
,
6413 int shader_time_index8
, int shader_time_index16
,
6414 bool allow_spilling
,
6415 bool use_rep_send
, struct brw_vue_map
*vue_map
,
6416 unsigned *final_assembly_size
,
6419 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
6421 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6422 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
6423 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
6424 brw_nir_lower_fs_outputs(shader
);
6426 if (devinfo
->gen
< 6) {
6427 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
, devinfo
);
6430 if (!key
->multisample_fbo
)
6431 NIR_PASS_V(shader
, demote_sample_qualifiers
);
6432 NIR_PASS_V(shader
, move_interpolation_to_top
);
6433 shader
= brw_postprocess_nir(shader
, compiler
, true);
6435 /* key->alpha_test_func means simulating alpha testing via discards,
6436 * so the shader definitely kills pixels.
6438 prog_data
->uses_kill
= shader
->info
->fs
.uses_discard
||
6439 key
->alpha_test_func
;
6440 prog_data
->uses_omask
= key
->multisample_fbo
&&
6441 shader
->info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6442 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6443 prog_data
->computed_stencil
=
6444 shader
->info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6446 prog_data
->persample_dispatch
=
6447 key
->multisample_fbo
&&
6448 (key
->persample_interp
||
6449 (shader
->info
->system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6450 SYSTEM_BIT_SAMPLE_POS
)) ||
6451 shader
->info
->fs
.uses_sample_qualifier
||
6452 shader
->info
->outputs_read
);
6454 prog_data
->early_fragment_tests
= shader
->info
->fs
.early_fragment_tests
;
6455 prog_data
->post_depth_coverage
= shader
->info
->fs
.post_depth_coverage
;
6456 prog_data
->inner_coverage
= shader
->info
->fs
.inner_coverage
;
6458 prog_data
->barycentric_interp_modes
=
6459 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
6461 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6462 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6463 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6465 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6466 &prog_data
->base
, prog
, shader
, 8,
6467 shader_time_index8
);
6468 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6470 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6473 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6475 simd8_grf_start
= v8
.payload
.num_regs
;
6476 simd8_grf_used
= v8
.grf_used
;
6479 if (v8
.max_dispatch_width
>= 16 &&
6480 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6481 /* Try a SIMD16 compile */
6482 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6483 &prog_data
->base
, prog
, shader
, 16,
6484 shader_time_index16
);
6485 v16
.import_uniforms(&v8
);
6486 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6487 compiler
->shader_perf_log(log_data
,
6488 "SIMD16 shader failed to compile: %s",
6491 simd16_cfg
= v16
.cfg
;
6492 simd16_grf_start
= v16
.payload
.num_regs
;
6493 simd16_grf_used
= v16
.grf_used
;
6497 /* When the caller requests a repclear shader, they want SIMD16-only */
6501 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6502 * at the top to select the shader. We've never implemented that.
6503 * Instead, we just give them exactly one shader and we pick the widest one
6506 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6509 if (prog_data
->persample_dispatch
) {
6510 /* Starting with SandyBridge (where we first get MSAA), the different
6511 * pixel dispatch combinations are grouped into classifications A
6512 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6513 * generations, the only configurations supporting persample dispatch
6514 * are are this in which only one dispatch width is enabled.
6516 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6517 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6519 if (compiler
->devinfo
->gen
== 6 &&
6520 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6522 } else if (simd16_cfg
) {
6527 /* We have to compute the flat inputs after the visitor is finished running
6528 * because it relies on prog_data->urb_setup which is computed in
6529 * fs_visitor::calculate_urb_setup().
6531 brw_compute_flat_inputs(prog_data
, shader
);
6533 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6534 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6535 MESA_SHADER_FRAGMENT
);
6537 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6538 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6539 shader
->info
->label
?
6540 shader
->info
->label
: "unnamed",
6541 shader
->info
->name
));
6545 prog_data
->dispatch_8
= true;
6546 g
.generate_code(simd8_cfg
, 8);
6547 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6548 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6551 prog_data
->dispatch_16
= true;
6552 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6553 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6554 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6556 } else if (simd16_cfg
) {
6557 prog_data
->dispatch_16
= true;
6558 g
.generate_code(simd16_cfg
, 16);
6559 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6560 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6563 return g
.get_assembly(final_assembly_size
);
6567 fs_visitor::emit_cs_work_group_id_setup()
6569 assert(stage
== MESA_SHADER_COMPUTE
);
6571 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6573 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6574 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6575 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6577 bld
.MOV(*reg
, r0_1
);
6578 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6579 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6585 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
6587 block
->dwords
= dwords
;
6588 block
->regs
= DIV_ROUND_UP(dwords
, 8);
6589 block
->size
= block
->regs
* 32;
6593 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
6594 struct brw_cs_prog_data
*cs_prog_data
)
6596 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
6597 bool fill_thread_id
=
6598 cs_prog_data
->thread_local_id_index
>= 0 &&
6599 cs_prog_data
->thread_local_id_index
< (int)prog_data
->nr_params
;
6600 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
6602 /* The thread ID should be stored in the last param dword */
6603 assert(prog_data
->nr_params
> 0 || !fill_thread_id
);
6604 assert(!fill_thread_id
||
6605 cs_prog_data
->thread_local_id_index
==
6606 (int)prog_data
->nr_params
- 1);
6608 unsigned cross_thread_dwords
, per_thread_dwords
;
6609 if (!cross_thread_supported
) {
6610 cross_thread_dwords
= 0u;
6611 per_thread_dwords
= prog_data
->nr_params
;
6612 } else if (fill_thread_id
) {
6613 /* Fill all but the last register with cross-thread payload */
6614 cross_thread_dwords
= 8 * (cs_prog_data
->thread_local_id_index
/ 8);
6615 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
6616 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
6618 /* Fill all data using cross-thread payload */
6619 cross_thread_dwords
= prog_data
->nr_params
;
6620 per_thread_dwords
= 0u;
6623 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
6624 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
6626 unsigned total_dwords
=
6627 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
6628 cs_prog_data
->push
.cross_thread
.size
) / 4;
6629 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
6631 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
6632 cs_prog_data
->push
.per_thread
.size
== 0);
6633 assert(cs_prog_data
->push
.cross_thread
.dwords
+
6634 cs_prog_data
->push
.per_thread
.dwords
==
6635 prog_data
->nr_params
);
6639 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
6641 cs_prog_data
->simd_size
= size
;
6642 unsigned group_size
= cs_prog_data
->local_size
[0] *
6643 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
6644 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
6648 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6650 const struct brw_cs_prog_key
*key
,
6651 struct brw_cs_prog_data
*prog_data
,
6652 const nir_shader
*src_shader
,
6653 int shader_time_index
,
6654 unsigned *final_assembly_size
,
6657 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6658 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
6659 brw_nir_lower_cs_shared(shader
);
6660 prog_data
->base
.total_shared
+= shader
->num_shared
;
6662 /* Now that we cloned the nir_shader, we can update num_uniforms based on
6663 * the thread_local_id_index.
6665 assert(prog_data
->thread_local_id_index
>= 0);
6666 shader
->num_uniforms
=
6667 MAX2(shader
->num_uniforms
,
6668 (unsigned)4 * (prog_data
->thread_local_id_index
+ 1));
6670 brw_nir_lower_intrinsics(shader
, &prog_data
->base
);
6671 shader
= brw_postprocess_nir(shader
, compiler
, true);
6673 prog_data
->local_size
[0] = shader
->info
->cs
.local_size
[0];
6674 prog_data
->local_size
[1] = shader
->info
->cs
.local_size
[1];
6675 prog_data
->local_size
[2] = shader
->info
->cs
.local_size
[2];
6676 unsigned local_workgroup_size
=
6677 shader
->info
->cs
.local_size
[0] * shader
->info
->cs
.local_size
[1] *
6678 shader
->info
->cs
.local_size
[2];
6680 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
6681 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
6684 const char *fail_msg
= NULL
;
6686 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6688 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6689 NULL
, /* Never used in core profile */
6690 shader
, 8, shader_time_index
);
6691 if (simd_required
<= 8) {
6693 fail_msg
= v8
.fail_msg
;
6696 cs_set_simd_size(prog_data
, 8);
6697 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6698 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
6702 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6703 NULL
, /* Never used in core profile */
6704 shader
, 16, shader_time_index
);
6705 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6706 !fail_msg
&& v8
.max_dispatch_width
>= 16 &&
6707 simd_required
<= 16) {
6708 /* Try a SIMD16 compile */
6709 if (simd_required
<= 8)
6710 v16
.import_uniforms(&v8
);
6711 if (!v16
.run_cs()) {
6712 compiler
->shader_perf_log(log_data
,
6713 "SIMD16 shader failed to compile: %s",
6717 "Couldn't generate SIMD16 program and not "
6718 "enough threads for SIMD8";
6722 cs_set_simd_size(prog_data
, 16);
6723 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6724 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
6728 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6729 NULL
, /* Never used in core profile */
6730 shader
, 32, shader_time_index
);
6731 if (!fail_msg
&& v8
.max_dispatch_width
>= 32 &&
6732 (simd_required
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
6733 /* Try a SIMD32 compile */
6734 if (simd_required
<= 8)
6735 v32
.import_uniforms(&v8
);
6736 else if (simd_required
<= 16)
6737 v32
.import_uniforms(&v16
);
6739 if (!v32
.run_cs()) {
6740 compiler
->shader_perf_log(log_data
,
6741 "SIMD32 shader failed to compile: %s",
6745 "Couldn't generate SIMD32 program and not "
6746 "enough threads for SIMD16";
6750 cs_set_simd_size(prog_data
, 32);
6751 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6755 if (unlikely(cfg
== NULL
)) {
6758 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6763 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6764 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6765 MESA_SHADER_COMPUTE
);
6766 if (INTEL_DEBUG
& DEBUG_CS
) {
6767 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6768 shader
->info
->label
? shader
->info
->label
:
6770 shader
->info
->name
);
6771 g
.enable_debug(name
);
6774 g
.generate_code(cfg
, prog_data
->simd_size
);
6776 return g
.get_assembly(final_assembly_size
);
6780 * Test the dispatch mask packing assumptions of
6781 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
6782 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
6783 * executed with an unexpected dispatch mask.
6786 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
6788 const gl_shader_stage stage
= bld
.shader
->stage
;
6790 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
6791 bld
.shader
->stage_prog_data
)) {
6792 const fs_builder ubld
= bld
.exec_all().group(1, 0);
6793 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
6794 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
6797 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
6798 ubld
.AND(tmp
, mask
, tmp
);
6800 /* This will loop forever if the dispatch mask doesn't have the expected
6801 * form '2^n-1', in which case tmp will be non-zero.
6803 bld
.emit(BRW_OPCODE_DO
);
6804 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
6805 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));