2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "main/macros.h"
36 #include "main/shaderobj.h"
37 #include "main/uniforms.h"
38 #include "main/fbobject.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/register_allocate.h"
42 #include "program/sampler.h"
43 #include "program/hash_table.h"
44 #include "brw_context.h"
48 #include "brw_shader.h"
50 #include "glsl/glsl_types.h"
51 #include "glsl/ir_print_visitor.h"
56 memset(this, 0, sizeof(*this));
57 this->opcode
= BRW_OPCODE_NOP
;
58 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
60 this->dst
= reg_undef
;
61 this->src
[0] = reg_undef
;
62 this->src
[1] = reg_undef
;
63 this->src
[2] = reg_undef
;
71 fs_inst::fs_inst(enum opcode opcode
)
74 this->opcode
= opcode
;
77 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
)
80 this->opcode
= opcode
;
84 assert(dst
.reg_offset
>= 0);
87 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
)
90 this->opcode
= opcode
;
95 assert(dst
.reg_offset
>= 0);
96 if (src
[0].file
== GRF
)
97 assert(src
[0].reg_offset
>= 0);
100 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
103 this->opcode
= opcode
;
109 assert(dst
.reg_offset
>= 0);
110 if (src
[0].file
== GRF
)
111 assert(src
[0].reg_offset
>= 0);
112 if (src
[1].file
== GRF
)
113 assert(src
[1].reg_offset
>= 0);
116 fs_inst::fs_inst(enum opcode opcode
, fs_reg dst
,
117 fs_reg src0
, fs_reg src1
, fs_reg src2
)
120 this->opcode
= opcode
;
127 assert(dst
.reg_offset
>= 0);
128 if (src
[0].file
== GRF
)
129 assert(src
[0].reg_offset
>= 0);
130 if (src
[1].file
== GRF
)
131 assert(src
[1].reg_offset
>= 0);
132 if (src
[2].file
== GRF
)
133 assert(src
[2].reg_offset
>= 0);
137 fs_inst::equals(fs_inst
*inst
)
139 return (opcode
== inst
->opcode
&&
140 dst
.equals(inst
->dst
) &&
141 src
[0].equals(inst
->src
[0]) &&
142 src
[1].equals(inst
->src
[1]) &&
143 src
[2].equals(inst
->src
[2]) &&
144 saturate
== inst
->saturate
&&
145 predicated
== inst
->predicated
&&
146 conditional_mod
== inst
->conditional_mod
&&
147 mlen
== inst
->mlen
&&
148 base_mrf
== inst
->base_mrf
&&
149 sampler
== inst
->sampler
&&
150 target
== inst
->target
&&
152 header_present
== inst
->header_present
&&
153 shadow_compare
== inst
->shadow_compare
&&
154 offset
== inst
->offset
);
158 fs_inst::regs_written()
163 /* The SINCOS and INT_DIV_QUOTIENT_AND_REMAINDER math functions return 2,
164 * but we don't currently use them...nor do we have an opcode for them.
171 fs_inst::overwrites_reg(const fs_reg
®
)
173 return (reg
.file
== dst
.file
&&
174 reg
.reg
== dst
.reg
&&
175 reg
.reg_offset
>= dst
.reg_offset
&&
176 reg
.reg_offset
< dst
.reg_offset
+ regs_written());
182 return (opcode
== SHADER_OPCODE_TEX
||
183 opcode
== FS_OPCODE_TXB
||
184 opcode
== SHADER_OPCODE_TXD
||
185 opcode
== SHADER_OPCODE_TXF
||
186 opcode
== SHADER_OPCODE_TXL
||
187 opcode
== SHADER_OPCODE_TXS
);
193 return (opcode
== SHADER_OPCODE_RCP
||
194 opcode
== SHADER_OPCODE_RSQ
||
195 opcode
== SHADER_OPCODE_SQRT
||
196 opcode
== SHADER_OPCODE_EXP2
||
197 opcode
== SHADER_OPCODE_LOG2
||
198 opcode
== SHADER_OPCODE_SIN
||
199 opcode
== SHADER_OPCODE_COS
||
200 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
201 opcode
== SHADER_OPCODE_INT_REMAINDER
||
202 opcode
== SHADER_OPCODE_POW
);
208 memset(this, 0, sizeof(*this));
212 /** Generic unset register constructor. */
216 this->file
= BAD_FILE
;
219 /** Immediate value constructor. */
220 fs_reg::fs_reg(float f
)
224 this->type
= BRW_REGISTER_TYPE_F
;
228 /** Immediate value constructor. */
229 fs_reg::fs_reg(int32_t i
)
233 this->type
= BRW_REGISTER_TYPE_D
;
237 /** Immediate value constructor. */
238 fs_reg::fs_reg(uint32_t u
)
242 this->type
= BRW_REGISTER_TYPE_UD
;
246 /** Fixed brw_reg Immediate value constructor. */
247 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
250 this->file
= FIXED_HW_REG
;
251 this->fixed_hw_reg
= fixed_hw_reg
;
252 this->type
= fixed_hw_reg
.type
;
256 fs_reg::equals(const fs_reg
&r
) const
258 return (file
== r
.file
&&
260 reg_offset
== r
.reg_offset
&&
262 negate
== r
.negate
&&
264 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
265 sizeof(fixed_hw_reg
)) == 0 &&
271 fs_visitor::type_size(const struct glsl_type
*type
)
273 unsigned int size
, i
;
275 switch (type
->base_type
) {
278 case GLSL_TYPE_FLOAT
:
280 return type
->components();
281 case GLSL_TYPE_ARRAY
:
282 return type_size(type
->fields
.array
) * type
->length
;
283 case GLSL_TYPE_STRUCT
:
285 for (i
= 0; i
< type
->length
; i
++) {
286 size
+= type_size(type
->fields
.structure
[i
].type
);
289 case GLSL_TYPE_SAMPLER
:
290 /* Samplers take up no register space, since they're baked in at
295 assert(!"not reached");
301 fs_visitor::fail(const char *format
, ...)
311 va_start(va
, format
);
312 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
314 msg
= ralloc_asprintf(mem_ctx
, "FS compile failed: %s\n", msg
);
316 this->fail_msg
= msg
;
318 if (INTEL_DEBUG
& DEBUG_WM
) {
319 fprintf(stderr
, "%s", msg
);
324 fs_visitor::emit(enum opcode opcode
)
326 return emit(fs_inst(opcode
));
330 fs_visitor::emit(enum opcode opcode
, fs_reg dst
)
332 return emit(fs_inst(opcode
, dst
));
336 fs_visitor::emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
)
338 return emit(fs_inst(opcode
, dst
, src0
));
342 fs_visitor::emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
344 return emit(fs_inst(opcode
, dst
, src0
, src1
));
348 fs_visitor::emit(enum opcode opcode
, fs_reg dst
,
349 fs_reg src0
, fs_reg src1
, fs_reg src2
)
351 return emit(fs_inst(opcode
, dst
, src0
, src1
, src2
));
355 fs_visitor::push_force_uncompressed()
357 force_uncompressed_stack
++;
361 fs_visitor::pop_force_uncompressed()
363 force_uncompressed_stack
--;
364 assert(force_uncompressed_stack
>= 0);
368 fs_visitor::push_force_sechalf()
370 force_sechalf_stack
++;
374 fs_visitor::pop_force_sechalf()
376 force_sechalf_stack
--;
377 assert(force_sechalf_stack
>= 0);
381 * Returns how many MRFs an FS opcode will write over.
383 * Note that this is not the 0 or 1 implied writes in an actual gen
384 * instruction -- the FS opcodes often generate MOVs in addition.
387 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
392 switch (inst
->opcode
) {
393 case SHADER_OPCODE_RCP
:
394 case SHADER_OPCODE_RSQ
:
395 case SHADER_OPCODE_SQRT
:
396 case SHADER_OPCODE_EXP2
:
397 case SHADER_OPCODE_LOG2
:
398 case SHADER_OPCODE_SIN
:
399 case SHADER_OPCODE_COS
:
400 return 1 * c
->dispatch_width
/ 8;
401 case SHADER_OPCODE_POW
:
402 case SHADER_OPCODE_INT_QUOTIENT
:
403 case SHADER_OPCODE_INT_REMAINDER
:
404 return 2 * c
->dispatch_width
/ 8;
405 case SHADER_OPCODE_TEX
:
407 case SHADER_OPCODE_TXD
:
408 case SHADER_OPCODE_TXF
:
409 case SHADER_OPCODE_TXL
:
410 case SHADER_OPCODE_TXS
:
412 case FS_OPCODE_FB_WRITE
:
414 case FS_OPCODE_PULL_CONSTANT_LOAD
:
415 case FS_OPCODE_UNSPILL
:
417 case FS_OPCODE_SPILL
:
420 assert(!"not reached");
426 fs_visitor::virtual_grf_alloc(int size
)
428 if (virtual_grf_array_size
<= virtual_grf_count
) {
429 if (virtual_grf_array_size
== 0)
430 virtual_grf_array_size
= 16;
432 virtual_grf_array_size
*= 2;
433 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
434 virtual_grf_array_size
);
436 virtual_grf_sizes
[virtual_grf_count
] = size
;
437 return virtual_grf_count
++;
440 /** Fixed HW reg constructor. */
441 fs_reg::fs_reg(enum register_file file
, int reg
)
446 this->type
= BRW_REGISTER_TYPE_F
;
449 /** Fixed HW reg constructor. */
450 fs_reg::fs_reg(enum register_file file
, int reg
, uint32_t type
)
458 /** Automatic reg constructor. */
459 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
464 this->reg
= v
->virtual_grf_alloc(v
->type_size(type
));
465 this->reg_offset
= 0;
466 this->type
= brw_type_for_base_type(type
);
470 fs_visitor::variable_storage(ir_variable
*var
)
472 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
476 import_uniforms_callback(const void *key
,
480 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
481 const fs_reg
*reg
= (const fs_reg
*)data
;
483 if (reg
->file
!= UNIFORM
)
486 hash_table_insert(dst_ht
, data
, key
);
489 /* For 16-wide, we need to follow from the uniform setup of 8-wide dispatch.
490 * This brings in those uniform definitions
493 fs_visitor::import_uniforms(fs_visitor
*v
)
495 hash_table_call_foreach(v
->variable_ht
,
496 import_uniforms_callback
,
498 this->params_remap
= v
->params_remap
;
501 /* Our support for uniforms is piggy-backed on the struct
502 * gl_fragment_program, because that's where the values actually
503 * get stored, rather than in some global gl_shader_program uniform
507 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
509 unsigned int offset
= 0;
511 if (type
->is_matrix()) {
512 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
513 type
->vector_elements
,
516 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
517 offset
+= setup_uniform_values(loc
+ offset
, column
);
523 switch (type
->base_type
) {
524 case GLSL_TYPE_FLOAT
:
528 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
529 unsigned int param
= c
->prog_data
.nr_params
++;
531 this->param_index
[param
] = loc
;
532 this->param_offset
[param
] = i
;
536 case GLSL_TYPE_STRUCT
:
537 for (unsigned int i
= 0; i
< type
->length
; i
++) {
538 offset
+= setup_uniform_values(loc
+ offset
,
539 type
->fields
.structure
[i
].type
);
543 case GLSL_TYPE_ARRAY
:
544 for (unsigned int i
= 0; i
< type
->length
; i
++) {
545 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
549 case GLSL_TYPE_SAMPLER
:
550 /* The sampler takes up a slot, but we don't use any values from it. */
554 assert(!"not reached");
560 /* Our support for builtin uniforms is even scarier than non-builtin.
561 * It sits on top of the PROG_STATE_VAR parameters that are
562 * automatically updated from GL context state.
565 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
567 const ir_state_slot
*const slots
= ir
->state_slots
;
568 assert(ir
->state_slots
!= NULL
);
570 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
571 /* This state reference has already been setup by ir_to_mesa, but we'll
572 * get the same index back here.
574 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
575 (gl_state_index
*)slots
[i
].tokens
);
577 /* Add each of the unique swizzles of the element as a parameter.
578 * This'll end up matching the expected layout of the
579 * array/matrix/structure we're trying to fill in.
582 for (unsigned int j
= 0; j
< 4; j
++) {
583 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
584 if (swiz
== last_swiz
)
588 this->param_index
[c
->prog_data
.nr_params
] = index
;
589 this->param_offset
[c
->prog_data
.nr_params
] = swiz
;
590 c
->prog_data
.nr_params
++;
596 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
598 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
600 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
603 if (ir
->pixel_center_integer
) {
604 emit(BRW_OPCODE_MOV
, wpos
, this->pixel_x
);
606 emit(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
));
611 if (!flip
&& ir
->pixel_center_integer
) {
612 emit(BRW_OPCODE_MOV
, wpos
, this->pixel_y
);
614 fs_reg pixel_y
= this->pixel_y
;
615 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
618 pixel_y
.negate
= true;
619 offset
+= c
->key
.drawable_height
- 1.0;
622 emit(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
));
627 if (intel
->gen
>= 6) {
628 emit(BRW_OPCODE_MOV
, wpos
,
629 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0)));
631 emit(FS_OPCODE_LINTERP
, wpos
,
632 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
633 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
634 interp_reg(FRAG_ATTRIB_WPOS
, 2));
638 /* gl_FragCoord.w: Already set up in emit_interpolation */
639 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
645 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
646 glsl_interp_qualifier interpolation_mode
,
649 brw_wm_barycentric_interp_mode barycoord_mode
;
651 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
652 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
654 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
656 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
657 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
659 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
661 return emit(FS_OPCODE_LINTERP
, attr
,
662 this->delta_x
[barycoord_mode
],
663 this->delta_y
[barycoord_mode
], interp
);
667 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
669 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
670 reg
->type
= brw_type_for_base_type(ir
->type
->get_scalar_type());
673 unsigned int array_elements
;
674 const glsl_type
*type
;
676 if (ir
->type
->is_array()) {
677 array_elements
= ir
->type
->length
;
678 if (array_elements
== 0) {
679 fail("dereferenced array '%s' has length 0\n", ir
->name
);
681 type
= ir
->type
->fields
.array
;
687 glsl_interp_qualifier interpolation_mode
=
688 ir
->determine_interpolation_mode(c
->key
.flat_shade
);
690 int location
= ir
->location
;
691 for (unsigned int i
= 0; i
< array_elements
; i
++) {
692 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
693 if (urb_setup
[location
] == -1) {
694 /* If there's no incoming setup data for this slot, don't
695 * emit interpolation for it.
697 attr
.reg_offset
+= type
->vector_elements
;
702 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
703 /* Constant interpolation (flat shading) case. The SF has
704 * handed us defined values in only the constant offset
705 * field of the setup reg.
707 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
708 struct brw_reg interp
= interp_reg(location
, k
);
709 interp
= suboffset(interp
, 3);
710 interp
.type
= reg
->type
;
711 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
715 /* Smooth/noperspective interpolation case. */
716 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
717 /* FINISHME: At some point we probably want to push
718 * this farther by giving similar treatment to the
719 * other potentially constant components of the
720 * attribute, as well as making brw_vs_constval.c
721 * handle varyings other than gl_TexCoord.
723 if (location
>= FRAG_ATTRIB_TEX0
&&
724 location
<= FRAG_ATTRIB_TEX7
&&
725 k
== 3 && !(c
->key
.proj_attrib_mask
& (1 << location
))) {
726 emit(BRW_OPCODE_MOV
, attr
, fs_reg(1.0f
));
728 struct brw_reg interp
= interp_reg(location
, k
);
729 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
731 if (brw
->needs_unlit_centroid_workaround
&& ir
->centroid
) {
732 /* Get the pixel/sample mask into f0 so that we know
733 * which pixels are lit. Then, for each channel that is
734 * unlit, replace the centroid data with non-centroid
737 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
, attr
);
738 fs_inst
*inst
= emit_linterp(attr
, fs_reg(interp
),
739 interpolation_mode
, false);
740 inst
->predicated
= true;
741 inst
->predicate_inverse
= true;
743 if (intel
->gen
< 6) {
744 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
759 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
761 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
763 /* The frontfacing comes in as a bit in the thread payload. */
764 if (intel
->gen
>= 6) {
765 emit(BRW_OPCODE_ASR
, *reg
,
766 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
768 emit(BRW_OPCODE_NOT
, *reg
, *reg
);
769 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1));
771 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
772 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
775 fs_inst
*inst
= emit(BRW_OPCODE_CMP
, *reg
,
778 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
779 emit(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u));
786 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src
)
789 case SHADER_OPCODE_RCP
:
790 case SHADER_OPCODE_RSQ
:
791 case SHADER_OPCODE_SQRT
:
792 case SHADER_OPCODE_EXP2
:
793 case SHADER_OPCODE_LOG2
:
794 case SHADER_OPCODE_SIN
:
795 case SHADER_OPCODE_COS
:
798 assert(!"not reached: bad math opcode");
802 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
803 * might be able to do better by doing execsize = 1 math and then
804 * expanding that result out, but we would need to be careful with
807 * Gen 6 hardware ignores source modifiers (negate and abs) on math
808 * instructions, so we also move to a temp to set those up.
810 if (intel
->gen
== 6 && (src
.file
== UNIFORM
||
813 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
814 emit(BRW_OPCODE_MOV
, expanded
, src
);
818 fs_inst
*inst
= emit(opcode
, dst
, src
);
820 if (intel
->gen
< 6) {
822 inst
->mlen
= c
->dispatch_width
/ 8;
829 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
835 case SHADER_OPCODE_POW
:
836 case SHADER_OPCODE_INT_QUOTIENT
:
837 case SHADER_OPCODE_INT_REMAINDER
:
840 assert(!"not reached: unsupported binary math opcode.");
844 if (intel
->gen
>= 7) {
845 inst
= emit(opcode
, dst
, src0
, src1
);
846 } else if (intel
->gen
== 6) {
847 /* Can't do hstride == 0 args to gen6 math, so expand it out.
849 * The hardware ignores source modifiers (negate and abs) on math
850 * instructions, so we also move to a temp to set those up.
852 if (src0
.file
== UNIFORM
|| src0
.abs
|| src0
.negate
) {
853 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
854 expanded
.type
= src0
.type
;
855 emit(BRW_OPCODE_MOV
, expanded
, src0
);
859 if (src1
.file
== UNIFORM
|| src1
.abs
|| src1
.negate
) {
860 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
861 expanded
.type
= src1
.type
;
862 emit(BRW_OPCODE_MOV
, expanded
, src1
);
866 inst
= emit(opcode
, dst
, src0
, src1
);
868 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
871 * "Operand0[7]. For the INT DIV functions, this operand is the
874 * "Operand1[7]. For the INT DIV functions, this operand is the
877 bool is_int_div
= opcode
!= SHADER_OPCODE_POW
;
878 fs_reg
&op0
= is_int_div
? src1
: src0
;
879 fs_reg
&op1
= is_int_div
? src0
: src1
;
881 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1, op1
.type
), op1
);
882 inst
= emit(opcode
, dst
, op0
, reg_null_f
);
884 inst
->base_mrf
= base_mrf
;
885 inst
->mlen
= 2 * c
->dispatch_width
/ 8;
891 * To be called after the last _mesa_add_state_reference() call, to
892 * set up prog_data.param[] for assign_curb_setup() and
893 * setup_pull_constants().
896 fs_visitor::setup_paramvalues_refs()
898 if (c
->dispatch_width
!= 8)
901 /* Set up the pointers to ParamValues now that that array is finalized. */
902 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
903 c
->prog_data
.param
[i
] =
904 (const float *)fp
->Base
.Parameters
->ParameterValues
[this->param_index
[i
]] +
905 this->param_offset
[i
];
910 fs_visitor::assign_curb_setup()
912 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
913 if (c
->dispatch_width
== 8) {
914 c
->prog_data
.first_curbe_grf
= c
->nr_payload_regs
;
916 c
->prog_data
.first_curbe_grf_16
= c
->nr_payload_regs
;
919 /* Map the offsets in the UNIFORM file to fixed HW regs. */
920 foreach_list(node
, &this->instructions
) {
921 fs_inst
*inst
= (fs_inst
*)node
;
923 for (unsigned int i
= 0; i
< 3; i
++) {
924 if (inst
->src
[i
].file
== UNIFORM
) {
925 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
926 struct brw_reg brw_reg
= brw_vec1_grf(c
->nr_payload_regs
+
930 inst
->src
[i
].file
= FIXED_HW_REG
;
931 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
938 fs_visitor::calculate_urb_setup()
940 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
945 /* Figure out where each of the incoming setup attributes lands. */
946 if (intel
->gen
>= 6) {
947 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
948 if (fp
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
949 urb_setup
[i
] = urb_next
++;
953 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
954 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
955 /* Point size is packed into the header, not as a general attribute */
956 if (i
== VERT_RESULT_PSIZ
)
959 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
960 int fp_index
= _mesa_vert_result_to_frag_attrib((gl_vert_result
) i
);
962 /* The back color slot is skipped when the front color is
963 * also written to. In addition, some slots can be
964 * written in the vertex shader and not read in the
965 * fragment shader. So the register number must always be
966 * incremented, mapped or not.
969 urb_setup
[fp_index
] = urb_next
;
975 * It's a FS only attribute, and we did interpolation for this attribute
976 * in SF thread. So, count it here, too.
978 * See compile_sf_prog() for more info.
980 if (fp
->Base
.InputsRead
& BITFIELD64_BIT(FRAG_ATTRIB_PNTC
))
981 urb_setup
[FRAG_ATTRIB_PNTC
] = urb_next
++;
984 /* Each attribute is 4 setup channels, each of which is half a reg. */
985 c
->prog_data
.urb_read_length
= urb_next
* 2;
989 fs_visitor::assign_urb_setup()
991 int urb_start
= c
->nr_payload_regs
+ c
->prog_data
.curb_read_length
;
993 /* Offset all the urb_setup[] index by the actual position of the
994 * setup regs, now that the location of the constants has been chosen.
996 foreach_list(node
, &this->instructions
) {
997 fs_inst
*inst
= (fs_inst
*)node
;
999 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1000 assert(inst
->src
[2].file
== FIXED_HW_REG
);
1001 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
1004 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1005 assert(inst
->src
[0].file
== FIXED_HW_REG
);
1006 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1010 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
1014 * Split large virtual GRFs into separate components if we can.
1016 * This is mostly duplicated with what brw_fs_vector_splitting does,
1017 * but that's really conservative because it's afraid of doing
1018 * splitting that doesn't result in real progress after the rest of
1019 * the optimization phases, which would cause infinite looping in
1020 * optimization. We can do it once here, safely. This also has the
1021 * opportunity to split interpolated values, or maybe even uniforms,
1022 * which we don't have at the IR level.
1024 * We want to split, because virtual GRFs are what we register
1025 * allocate and spill (due to contiguousness requirements for some
1026 * instructions), and they're what we naturally generate in the
1027 * codegen process, but most virtual GRFs don't actually need to be
1028 * contiguous sets of GRFs. If we split, we'll end up with reduced
1029 * live intervals and better dead code elimination and coalescing.
1032 fs_visitor::split_virtual_grfs()
1034 int num_vars
= this->virtual_grf_count
;
1035 bool split_grf
[num_vars
];
1036 int new_virtual_grf
[num_vars
];
1038 /* Try to split anything > 0 sized. */
1039 for (int i
= 0; i
< num_vars
; i
++) {
1040 if (this->virtual_grf_sizes
[i
] != 1)
1041 split_grf
[i
] = true;
1043 split_grf
[i
] = false;
1047 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
) {
1048 /* PLN opcodes rely on the delta_xy being contiguous. We only have to
1049 * check this for BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because prior to
1050 * Gen6, that was the only supported interpolation mode, and since Gen6,
1051 * delta_x and delta_y are in fixed hardware registers.
1053 split_grf
[this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
] =
1057 foreach_list(node
, &this->instructions
) {
1058 fs_inst
*inst
= (fs_inst
*)node
;
1060 /* If there's a SEND message that requires contiguous destination
1061 * registers, no splitting is allowed.
1063 if (inst
->regs_written() > 1) {
1064 split_grf
[inst
->dst
.reg
] = false;
1068 /* Allocate new space for split regs. Note that the virtual
1069 * numbers will be contiguous.
1071 for (int i
= 0; i
< num_vars
; i
++) {
1073 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1074 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1075 int reg
= virtual_grf_alloc(1);
1076 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1079 this->virtual_grf_sizes
[i
] = 1;
1083 foreach_list(node
, &this->instructions
) {
1084 fs_inst
*inst
= (fs_inst
*)node
;
1086 if (inst
->dst
.file
== GRF
&&
1087 split_grf
[inst
->dst
.reg
] &&
1088 inst
->dst
.reg_offset
!= 0) {
1089 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1090 inst
->dst
.reg_offset
- 1);
1091 inst
->dst
.reg_offset
= 0;
1093 for (int i
= 0; i
< 3; i
++) {
1094 if (inst
->src
[i
].file
== GRF
&&
1095 split_grf
[inst
->src
[i
].reg
] &&
1096 inst
->src
[i
].reg_offset
!= 0) {
1097 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1098 inst
->src
[i
].reg_offset
- 1);
1099 inst
->src
[i
].reg_offset
= 0;
1103 this->live_intervals_valid
= false;
1107 fs_visitor::remove_dead_constants()
1109 if (c
->dispatch_width
== 8) {
1110 this->params_remap
= ralloc_array(mem_ctx
, int, c
->prog_data
.nr_params
);
1112 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++)
1113 this->params_remap
[i
] = -1;
1115 /* Find which params are still in use. */
1116 foreach_list(node
, &this->instructions
) {
1117 fs_inst
*inst
= (fs_inst
*)node
;
1119 for (int i
= 0; i
< 3; i
++) {
1120 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1122 if (inst
->src
[i
].file
!= UNIFORM
)
1125 assert(constant_nr
< (int)c
->prog_data
.nr_params
);
1127 /* For now, set this to non-negative. We'll give it the
1128 * actual new number in a moment, in order to keep the
1129 * register numbers nicely ordered.
1131 this->params_remap
[constant_nr
] = 0;
1135 /* Figure out what the new numbers for the params will be. At some
1136 * point when we're doing uniform array access, we're going to want
1137 * to keep the distinction between .reg and .reg_offset, but for
1138 * now we don't care.
1140 unsigned int new_nr_params
= 0;
1141 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1142 if (this->params_remap
[i
] != -1) {
1143 this->params_remap
[i
] = new_nr_params
++;
1147 /* Update the list of params to be uploaded to match our new numbering. */
1148 for (unsigned int i
= 0; i
< c
->prog_data
.nr_params
; i
++) {
1149 int remapped
= this->params_remap
[i
];
1154 /* We've already done setup_paramvalues_refs() so no need to worry
1155 * about param_index and param_offset.
1157 c
->prog_data
.param
[remapped
] = c
->prog_data
.param
[i
];
1160 c
->prog_data
.nr_params
= new_nr_params
;
1162 /* This should have been generated in the 8-wide pass already. */
1163 assert(this->params_remap
);
1166 /* Now do the renumbering of the shader to remove unused params. */
1167 foreach_list(node
, &this->instructions
) {
1168 fs_inst
*inst
= (fs_inst
*)node
;
1170 for (int i
= 0; i
< 3; i
++) {
1171 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1173 if (inst
->src
[i
].file
!= UNIFORM
)
1176 assert(this->params_remap
[constant_nr
] != -1);
1177 inst
->src
[i
].reg
= this->params_remap
[constant_nr
];
1178 inst
->src
[i
].reg_offset
= 0;
1186 * Choose accesses from the UNIFORM file to demote to using the pull
1189 * We allow a fragment shader to have more than the specified minimum
1190 * maximum number of fragment shader uniform components (64). If
1191 * there are too many of these, they'd fill up all of register space.
1192 * So, this will push some of them out to the pull constant buffer and
1193 * update the program to load them.
1196 fs_visitor::setup_pull_constants()
1198 /* Only allow 16 registers (128 uniform components) as push constants. */
1199 unsigned int max_uniform_components
= 16 * 8;
1200 if (c
->prog_data
.nr_params
<= max_uniform_components
)
1203 if (c
->dispatch_width
== 16) {
1204 fail("Pull constants not supported in 16-wide\n");
1208 /* Just demote the end of the list. We could probably do better
1209 * here, demoting things that are rarely used in the program first.
1211 int pull_uniform_base
= max_uniform_components
;
1212 int pull_uniform_count
= c
->prog_data
.nr_params
- pull_uniform_base
;
1214 foreach_list(node
, &this->instructions
) {
1215 fs_inst
*inst
= (fs_inst
*)node
;
1217 for (int i
= 0; i
< 3; i
++) {
1218 if (inst
->src
[i
].file
!= UNIFORM
)
1221 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1222 if (uniform_nr
< pull_uniform_base
)
1225 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
1226 fs_reg index
= fs_reg((unsigned)SURF_INDEX_FRAG_CONST_BUFFER
);
1227 fs_reg offset
= fs_reg((unsigned)(((uniform_nr
-
1228 pull_uniform_base
) * 4) & ~15));
1229 fs_inst
*pull
= new(mem_ctx
) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
1230 dst
, index
, offset
);
1231 pull
->ir
= inst
->ir
;
1232 pull
->annotation
= inst
->annotation
;
1233 pull
->base_mrf
= 14;
1236 inst
->insert_before(pull
);
1238 inst
->src
[i
].file
= GRF
;
1239 inst
->src
[i
].reg
= dst
.reg
;
1240 inst
->src
[i
].reg_offset
= 0;
1241 inst
->src
[i
].smear
= (uniform_nr
- pull_uniform_base
) & 3;
1245 for (int i
= 0; i
< pull_uniform_count
; i
++) {
1246 c
->prog_data
.pull_param
[i
] = c
->prog_data
.param
[pull_uniform_base
+ i
];
1248 c
->prog_data
.nr_params
-= pull_uniform_count
;
1249 c
->prog_data
.nr_pull_params
= pull_uniform_count
;
1253 fs_visitor::opt_algebraic()
1255 bool progress
= false;
1257 calculate_live_intervals();
1259 foreach_list(node
, &this->instructions
) {
1260 fs_inst
*inst
= (fs_inst
*)node
;
1262 switch (inst
->opcode
) {
1263 case BRW_OPCODE_MUL
:
1264 if (inst
->src
[1].file
!= IMM
)
1268 if (inst
->src
[1].type
== BRW_REGISTER_TYPE_F
&&
1269 inst
->src
[1].imm
.f
== 1.0) {
1270 inst
->opcode
= BRW_OPCODE_MOV
;
1271 inst
->src
[1] = reg_undef
;
1277 if (inst
->src
[1].type
== BRW_REGISTER_TYPE_F
&&
1278 inst
->src
[1].imm
.f
== 0.0) {
1279 inst
->opcode
= BRW_OPCODE_MOV
;
1280 inst
->src
[0] = fs_reg(0.0f
);
1281 inst
->src
[1] = reg_undef
;
1287 case BRW_OPCODE_ADD
:
1288 if (inst
->src
[1].file
!= IMM
)
1292 if (inst
->src
[1].type
== BRW_REGISTER_TYPE_F
&&
1293 inst
->src
[1].imm
.f
== 0.0) {
1294 inst
->opcode
= BRW_OPCODE_MOV
;
1295 inst
->src
[1] = reg_undef
;
1309 * Must be called after calculate_live_intervales() to remove unused
1310 * writes to registers -- register allocation will fail otherwise
1311 * because something deffed but not used won't be considered to
1312 * interfere with other regs.
1315 fs_visitor::dead_code_eliminate()
1317 bool progress
= false;
1320 calculate_live_intervals();
1322 foreach_list_safe(node
, &this->instructions
) {
1323 fs_inst
*inst
= (fs_inst
*)node
;
1325 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
1334 live_intervals_valid
= false;
1340 * Implements a second type of register coalescing: This one checks if
1341 * the two regs involved in a raw move don't interfere, in which case
1342 * they can both by stored in the same place and the MOV removed.
1345 fs_visitor::register_coalesce_2()
1347 bool progress
= false;
1349 calculate_live_intervals();
1351 foreach_list_safe(node
, &this->instructions
) {
1352 fs_inst
*inst
= (fs_inst
*)node
;
1354 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1357 inst
->src
[0].file
!= GRF
||
1358 inst
->src
[0].negate
||
1360 inst
->src
[0].smear
!= -1 ||
1361 inst
->dst
.file
!= GRF
||
1362 inst
->dst
.type
!= inst
->src
[0].type
||
1363 virtual_grf_sizes
[inst
->src
[0].reg
] != 1 ||
1364 virtual_grf_interferes(inst
->dst
.reg
, inst
->src
[0].reg
)) {
1368 int reg_from
= inst
->src
[0].reg
;
1369 assert(inst
->src
[0].reg_offset
== 0);
1370 int reg_to
= inst
->dst
.reg
;
1371 int reg_to_offset
= inst
->dst
.reg_offset
;
1373 foreach_list_safe(node
, &this->instructions
) {
1374 fs_inst
*scan_inst
= (fs_inst
*)node
;
1376 if (scan_inst
->dst
.file
== GRF
&&
1377 scan_inst
->dst
.reg
== reg_from
) {
1378 scan_inst
->dst
.reg
= reg_to
;
1379 scan_inst
->dst
.reg_offset
= reg_to_offset
;
1381 for (int i
= 0; i
< 3; i
++) {
1382 if (scan_inst
->src
[i
].file
== GRF
&&
1383 scan_inst
->src
[i
].reg
== reg_from
) {
1384 scan_inst
->src
[i
].reg
= reg_to
;
1385 scan_inst
->src
[i
].reg_offset
= reg_to_offset
;
1391 live_intervals_valid
= false;
1400 fs_visitor::register_coalesce()
1402 bool progress
= false;
1406 foreach_list_safe(node
, &this->instructions
) {
1407 fs_inst
*inst
= (fs_inst
*)node
;
1409 /* Make sure that we dominate the instructions we're going to
1410 * scan for interfering with our coalescing, or we won't have
1411 * scanned enough to see if anything interferes with our
1412 * coalescing. We don't dominate the following instructions if
1413 * we're in a loop or an if block.
1415 switch (inst
->opcode
) {
1419 case BRW_OPCODE_WHILE
:
1425 case BRW_OPCODE_ENDIF
:
1431 if (loop_depth
|| if_depth
)
1434 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1437 inst
->dst
.file
!= GRF
|| (inst
->src
[0].file
!= GRF
&&
1438 inst
->src
[0].file
!= UNIFORM
)||
1439 inst
->dst
.type
!= inst
->src
[0].type
)
1442 bool has_source_modifiers
= inst
->src
[0].abs
|| inst
->src
[0].negate
;
1444 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
1445 * them: check for no writes to either one until the exit of the
1448 bool interfered
= false;
1450 for (fs_inst
*scan_inst
= (fs_inst
*)inst
->next
;
1451 !scan_inst
->is_tail_sentinel();
1452 scan_inst
= (fs_inst
*)scan_inst
->next
) {
1453 if (scan_inst
->dst
.file
== GRF
) {
1454 if (scan_inst
->overwrites_reg(inst
->dst
) ||
1455 scan_inst
->overwrites_reg(inst
->src
[0])) {
1461 /* The gen6 MATH instruction can't handle source modifiers or
1462 * unusual register regions, so avoid coalescing those for
1463 * now. We should do something more specific.
1465 if (intel
->gen
>= 6 &&
1466 scan_inst
->is_math() &&
1467 (has_source_modifiers
|| inst
->src
[0].file
== UNIFORM
)) {
1472 /* The accumulator result appears to get used for the
1473 * conditional modifier generation. When negating a UD
1474 * value, there is a 33rd bit generated for the sign in the
1475 * accumulator value, so now you can't check, for example,
1476 * equality with a 32-bit value. See piglit fs-op-neg-uint.
1478 if (scan_inst
->conditional_mod
&&
1479 inst
->src
[0].negate
&&
1480 inst
->src
[0].type
== BRW_REGISTER_TYPE_UD
) {
1489 /* Rewrite the later usage to point at the source of the move to
1492 for (fs_inst
*scan_inst
= inst
;
1493 !scan_inst
->is_tail_sentinel();
1494 scan_inst
= (fs_inst
*)scan_inst
->next
) {
1495 for (int i
= 0; i
< 3; i
++) {
1496 if (scan_inst
->src
[i
].file
== GRF
&&
1497 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
1498 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
1499 fs_reg new_src
= inst
->src
[0];
1500 if (scan_inst
->src
[i
].abs
) {
1504 new_src
.negate
^= scan_inst
->src
[i
].negate
;
1505 scan_inst
->src
[i
] = new_src
;
1515 live_intervals_valid
= false;
1522 fs_visitor::compute_to_mrf()
1524 bool progress
= false;
1527 calculate_live_intervals();
1529 foreach_list_safe(node
, &this->instructions
) {
1530 fs_inst
*inst
= (fs_inst
*)node
;
1535 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1537 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
1538 inst
->dst
.type
!= inst
->src
[0].type
||
1539 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
1542 /* Work out which hardware MRF registers are written by this
1545 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
1547 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
1548 mrf_high
= mrf_low
+ 4;
1549 } else if (c
->dispatch_width
== 16 &&
1550 (!inst
->force_uncompressed
&& !inst
->force_sechalf
)) {
1551 mrf_high
= mrf_low
+ 1;
1556 /* Can't compute-to-MRF this GRF if someone else was going to
1559 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
1562 /* Found a move of a GRF to a MRF. Let's see if we can go
1563 * rewrite the thing that made this GRF to write into the MRF.
1566 for (scan_inst
= (fs_inst
*)inst
->prev
;
1567 scan_inst
->prev
!= NULL
;
1568 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
1569 if (scan_inst
->dst
.file
== GRF
&&
1570 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
1571 /* Found the last thing to write our reg we want to turn
1572 * into a compute-to-MRF.
1575 /* SENDs can only write to GRFs, so no compute-to-MRF. */
1576 if (scan_inst
->mlen
) {
1580 /* If it's predicated, it (probably) didn't populate all
1581 * the channels. We might be able to rewrite everything
1582 * that writes that reg, but it would require smarter
1583 * tracking to delay the rewriting until complete success.
1585 if (scan_inst
->predicated
)
1588 /* If it's half of register setup and not the same half as
1589 * our MOV we're trying to remove, bail for now.
1591 if (scan_inst
->force_uncompressed
!= inst
->force_uncompressed
||
1592 scan_inst
->force_sechalf
!= inst
->force_sechalf
) {
1596 /* SEND instructions can't have MRF as a destination. */
1597 if (scan_inst
->mlen
)
1600 if (intel
->gen
>= 6) {
1601 /* gen6 math instructions must have the destination be
1602 * GRF, so no compute-to-MRF for them.
1604 if (scan_inst
->is_math()) {
1609 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1610 /* Found the creator of our MRF's source value. */
1611 scan_inst
->dst
.file
= MRF
;
1612 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1613 scan_inst
->saturate
|= inst
->saturate
;
1620 /* We don't handle flow control here. Most computation of
1621 * values that end up in MRFs are shortly before the MRF
1624 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
1625 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
1626 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
1627 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
1631 /* You can't read from an MRF, so if someone else reads our
1632 * MRF's source GRF that we wanted to rewrite, that stops us.
1634 bool interfered
= false;
1635 for (int i
= 0; i
< 3; i
++) {
1636 if (scan_inst
->src
[i
].file
== GRF
&&
1637 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
1638 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1645 if (scan_inst
->dst
.file
== MRF
) {
1646 /* If somebody else writes our MRF here, we can't
1647 * compute-to-MRF before that.
1649 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
1652 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
1653 scan_mrf_high
= scan_mrf_low
+ 4;
1654 } else if (c
->dispatch_width
== 16 &&
1655 (!scan_inst
->force_uncompressed
&&
1656 !scan_inst
->force_sechalf
)) {
1657 scan_mrf_high
= scan_mrf_low
+ 1;
1659 scan_mrf_high
= scan_mrf_low
;
1662 if (mrf_low
== scan_mrf_low
||
1663 mrf_low
== scan_mrf_high
||
1664 mrf_high
== scan_mrf_low
||
1665 mrf_high
== scan_mrf_high
) {
1670 if (scan_inst
->mlen
> 0) {
1671 /* Found a SEND instruction, which means that there are
1672 * live values in MRFs from base_mrf to base_mrf +
1673 * scan_inst->mlen - 1. Don't go pushing our MRF write up
1676 if (mrf_low
>= scan_inst
->base_mrf
&&
1677 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1680 if (mrf_high
>= scan_inst
->base_mrf
&&
1681 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1689 live_intervals_valid
= false;
1695 * Walks through basic blocks, looking for repeated MRF writes and
1696 * removing the later ones.
1699 fs_visitor::remove_duplicate_mrf_writes()
1701 fs_inst
*last_mrf_move
[16];
1702 bool progress
= false;
1704 /* Need to update the MRF tracking for compressed instructions. */
1705 if (c
->dispatch_width
== 16)
1708 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
1710 foreach_list_safe(node
, &this->instructions
) {
1711 fs_inst
*inst
= (fs_inst
*)node
;
1713 switch (inst
->opcode
) {
1715 case BRW_OPCODE_WHILE
:
1717 case BRW_OPCODE_ELSE
:
1718 case BRW_OPCODE_ENDIF
:
1719 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
1725 if (inst
->opcode
== BRW_OPCODE_MOV
&&
1726 inst
->dst
.file
== MRF
) {
1727 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
1728 if (prev_inst
&& inst
->equals(prev_inst
)) {
1735 /* Clear out the last-write records for MRFs that were overwritten. */
1736 if (inst
->dst
.file
== MRF
) {
1737 last_mrf_move
[inst
->dst
.reg
] = NULL
;
1740 if (inst
->mlen
> 0) {
1741 /* Found a SEND instruction, which will include two or fewer
1742 * implied MRF writes. We could do better here.
1744 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
1745 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
1749 /* Clear out any MRF move records whose sources got overwritten. */
1750 if (inst
->dst
.file
== GRF
) {
1751 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
1752 if (last_mrf_move
[i
] &&
1753 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
1754 last_mrf_move
[i
] = NULL
;
1759 if (inst
->opcode
== BRW_OPCODE_MOV
&&
1760 inst
->dst
.file
== MRF
&&
1761 inst
->src
[0].file
== GRF
&&
1762 !inst
->predicated
) {
1763 last_mrf_move
[inst
->dst
.reg
] = inst
;
1768 live_intervals_valid
= false;
1774 * Possibly returns an instruction that set up @param reg.
1776 * Sometimes we want to take the result of some expression/variable
1777 * dereference tree and rewrite the instruction generating the result
1778 * of the tree. When processing the tree, we know that the
1779 * instructions generated are all writing temporaries that are dead
1780 * outside of this tree. So, if we have some instructions that write
1781 * a temporary, we're free to point that temp write somewhere else.
1783 * Note that this doesn't guarantee that the instruction generated
1784 * only reg -- it might be the size=4 destination of a texture instruction.
1787 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
1793 end
->force_uncompressed
||
1794 end
->force_sechalf
||
1795 !reg
.equals(end
->dst
)) {
1805 uint32_t prog_offset_16
= 0;
1806 uint32_t orig_nr_params
= c
->prog_data
.nr_params
;
1808 brw_wm_payload_setup(brw
, c
);
1810 if (c
->dispatch_width
== 16) {
1811 /* We have to do a compaction pass now, or the one at the end of
1812 * execution will squash down where our prog_offset start needs
1815 brw_compact_instructions(p
);
1817 /* align to 64 byte boundary. */
1818 while ((c
->func
.nr_insn
* sizeof(struct brw_instruction
)) % 64) {
1822 /* Save off the start of this 16-wide program in case we succeed. */
1823 prog_offset_16
= c
->func
.nr_insn
* sizeof(struct brw_instruction
);
1825 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1831 calculate_urb_setup();
1833 emit_interpolation_setup_gen4();
1835 emit_interpolation_setup_gen6();
1837 /* Generate FS IR for main(). (the visitor only descends into
1838 * functions called "main").
1841 foreach_list(node
, &*shader
->ir
) {
1842 ir_instruction
*ir
= (ir_instruction
*)node
;
1844 this->result
= reg_undef
;
1848 emit_fragment_program_code();
1855 split_virtual_grfs();
1857 setup_paramvalues_refs();
1858 setup_pull_constants();
1864 progress
= remove_duplicate_mrf_writes() || progress
;
1866 progress
= opt_algebraic() || progress
;
1867 progress
= opt_cse() || progress
;
1868 progress
= opt_copy_propagate() || progress
;
1869 progress
= register_coalesce() || progress
;
1870 progress
= register_coalesce_2() || progress
;
1871 progress
= compute_to_mrf() || progress
;
1872 progress
= dead_code_eliminate() || progress
;
1875 remove_dead_constants();
1877 schedule_instructions();
1879 assign_curb_setup();
1883 /* Debug of register spilling: Go spill everything. */
1884 for (int i
= 0; i
< virtual_grf_count
; i
++) {
1890 assign_regs_trivial();
1892 while (!assign_regs()) {
1898 assert(force_uncompressed_stack
== 0);
1899 assert(force_sechalf_stack
== 0);
1906 if (c
->dispatch_width
== 8) {
1907 c
->prog_data
.reg_blocks
= brw_register_blocks(grf_used
);
1909 c
->prog_data
.reg_blocks_16
= brw_register_blocks(grf_used
);
1910 c
->prog_data
.prog_offset_16
= prog_offset_16
;
1912 /* Make sure we didn't try to sneak in an extra uniform */
1913 assert(orig_nr_params
== c
->prog_data
.nr_params
);
1914 (void) orig_nr_params
;
1921 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
,
1922 struct gl_shader_program
*prog
)
1924 struct intel_context
*intel
= &brw
->intel
;
1925 bool start_busy
= false;
1926 float start_time
= 0;
1928 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1929 start_busy
= (intel
->batch
.last_bo
&&
1930 drm_intel_bo_busy(intel
->batch
.last_bo
));
1931 start_time
= get_time();
1934 struct brw_shader
*shader
= NULL
;
1936 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
1938 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1940 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
1941 _mesa_print_ir(shader
->ir
, NULL
);
1944 printf("ARB_fragment_program %d ir for native fragment shader\n",
1945 c
->fp
->program
.Base
.Id
);
1946 _mesa_print_program(&c
->fp
->program
.Base
);
1950 /* Now the main event: Visit the shader IR and generate our FS IR for it.
1952 c
->dispatch_width
= 8;
1954 fs_visitor
v(c
, prog
, shader
);
1956 prog
->LinkStatus
= false;
1957 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1959 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
1965 if (intel
->gen
>= 5 && c
->prog_data
.nr_pull_params
== 0) {
1966 c
->dispatch_width
= 16;
1967 fs_visitor
v2(c
, prog
, shader
);
1968 v2
.import_uniforms(&v
);
1970 perf_debug("16-wide shader failed to compile, falling back to "
1971 "8-wide at a 10-20%% performance cost: %s", v2
.fail_msg
);
1975 c
->prog_data
.dispatch_width
= 8;
1977 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
) && shader
) {
1978 if (shader
->compiled_once
)
1979 brw_wm_debug_recompile(brw
, prog
, &c
->key
);
1980 shader
->compiled_once
= true;
1982 if (start_busy
&& !drm_intel_bo_busy(intel
->batch
.last_bo
)) {
1983 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
1984 (get_time() - start_time
) * 1000);
1992 brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
1994 struct brw_context
*brw
= brw_context(ctx
);
1995 struct intel_context
*intel
= &brw
->intel
;
1996 struct brw_wm_prog_key key
;
1998 if (!prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
])
2001 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)
2002 prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
]->Program
;
2003 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
2004 bool program_uses_dfdy
= fp
->UsesDFdy
;
2006 memset(&key
, 0, sizeof(key
));
2008 if (intel
->gen
< 6) {
2010 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
2012 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
2013 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
2015 /* Just assume depth testing. */
2016 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
2017 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
2020 if (prog
->Name
!= 0)
2021 key
.proj_attrib_mask
= 0xffffffff;
2024 key
.vp_outputs_written
|= BITFIELD64_BIT(FRAG_ATTRIB_WPOS
);
2026 for (int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2027 if (!(fp
->Base
.InputsRead
& BITFIELD64_BIT(i
)))
2030 if (prog
->Name
== 0)
2031 key
.proj_attrib_mask
|= 1 << i
;
2033 if (intel
->gen
< 6) {
2034 int vp_index
= _mesa_vert_result_to_frag_attrib((gl_vert_result
) i
);
2037 key
.vp_outputs_written
|= BITFIELD64_BIT(vp_index
);
2041 key
.clamp_fragment_color
= true;
2043 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
2044 if (fp
->Base
.ShadowSamplers
& (1 << i
)) {
2045 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
2046 key
.tex
.swizzles
[i
] =
2047 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
2049 /* Color sampler: assume no swizzling. */
2050 key
.tex
.swizzles
[i
] = SWIZZLE_XYZW
;
2054 if (fp
->Base
.InputsRead
& FRAG_BIT_WPOS
) {
2055 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
2058 if ((fp
->Base
.InputsRead
& FRAG_BIT_WPOS
) || program_uses_dfdy
) {
2059 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
);
2062 key
.nr_color_regions
= 1;
2064 key
.program_string_id
= bfp
->id
;
2066 uint32_t old_prog_offset
= brw
->wm
.prog_offset
;
2067 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
2069 bool success
= do_wm_prog(brw
, prog
, bfp
, &key
);
2071 brw
->wm
.prog_offset
= old_prog_offset
;
2072 brw
->wm
.prog_data
= old_prog_data
;