2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "glsl/nir/glsl_types.h"
46 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
47 const fs_reg
*src
, unsigned sources
)
49 memset(this, 0, sizeof(*this));
51 this->src
= new fs_reg
[MAX2(sources
, 3)];
52 for (unsigned i
= 0; i
< sources
; i
++)
53 this->src
[i
] = src
[i
];
55 this->opcode
= opcode
;
57 this->sources
= sources
;
58 this->exec_size
= exec_size
;
60 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
62 assert(this->exec_size
!= 0);
64 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
66 /* This will be the case for almost all instructions. */
73 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
77 this->regs_written
= 0;
81 unreachable("Invalid destination register file");
84 this->writes_accumulator
= false;
89 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
92 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
94 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
99 init(opcode
, exec_size
, dst
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
105 const fs_reg src
[1] = { src0
};
106 init(opcode
, exec_size
, dst
, src
, 1);
109 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg
&src0
, const fs_reg
&src1
)
112 const fs_reg src
[2] = { src0
, src1
};
113 init(opcode
, exec_size
, dst
, src
, 2);
116 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
117 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
119 const fs_reg src
[3] = { src0
, src1
, src2
};
120 init(opcode
, exec_size
, dst
, src
, 3);
123 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
124 const fs_reg src
[], unsigned sources
)
126 init(opcode
, exec_width
, dst
, src
, sources
);
129 fs_inst::fs_inst(const fs_inst
&that
)
131 memcpy(this, &that
, sizeof(that
));
133 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
135 for (unsigned i
= 0; i
< that
.sources
; i
++)
136 this->src
[i
] = that
.src
[i
];
145 fs_inst::resize_sources(uint8_t num_sources
)
147 if (this->sources
!= num_sources
) {
148 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
150 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
151 src
[i
] = this->src
[i
];
155 this->sources
= num_sources
;
160 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
162 const fs_reg
&surf_index
,
163 const fs_reg
&varying_offset
,
164 uint32_t const_offset
)
166 /* We have our constant surface use a pitch of 4 bytes, so our index can
167 * be any component of a vector, and then we load 4 contiguous
168 * components starting from that.
170 * We break down the const_offset to a portion added to the variable
171 * offset and a portion done using reg_offset, which means that if you
172 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
173 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
174 * CSE can later notice that those loads are all the same and eliminate
175 * the redundant ones.
177 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
178 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
181 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
182 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
183 * u, v, r) as parameters, or we can just use the SIMD16 message
184 * consisting of (header, u). We choose the second, at the cost of a
185 * longer return length.
191 if (devinfo
->gen
>= 7)
192 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
194 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
196 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
197 fs_reg vec4_result
= fs_reg(VGRF
, alloc
.allocate(regs_written
), dst
.type
);
198 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
199 inst
->regs_written
= regs_written
;
201 if (devinfo
->gen
< 7) {
202 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
203 inst
->header_size
= 1;
204 if (devinfo
->gen
== 4)
207 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
210 bld
.MOV(dst
, offset(vec4_result
, bld
, ((const_offset
& 0xf) / 4) * scale
));
214 * A helper for MOV generation for fixing up broken hardware SEND dependency
218 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
220 /* The caller always wants uncompressed to emit the minimal extra
221 * dependencies, and to avoid having to deal with aligning its regs to 2.
223 const fs_builder ubld
= bld
.annotate("send dependency resolve")
226 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
230 fs_inst::equals(fs_inst
*inst
) const
232 return (opcode
== inst
->opcode
&&
233 dst
.equals(inst
->dst
) &&
234 src
[0].equals(inst
->src
[0]) &&
235 src
[1].equals(inst
->src
[1]) &&
236 src
[2].equals(inst
->src
[2]) &&
237 saturate
== inst
->saturate
&&
238 predicate
== inst
->predicate
&&
239 conditional_mod
== inst
->conditional_mod
&&
240 mlen
== inst
->mlen
&&
241 base_mrf
== inst
->base_mrf
&&
242 target
== inst
->target
&&
244 header_size
== inst
->header_size
&&
245 shadow_compare
== inst
->shadow_compare
&&
246 exec_size
== inst
->exec_size
&&
247 offset
== inst
->offset
);
251 fs_inst::overwrites_reg(const fs_reg
®
) const
253 return reg
.in_range(dst
, regs_written
);
257 fs_inst::is_send_from_grf() const
260 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
261 case SHADER_OPCODE_SHADER_TIME_ADD
:
262 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
263 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
264 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
265 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
266 case SHADER_OPCODE_UNTYPED_ATOMIC
:
267 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
268 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
269 case SHADER_OPCODE_TYPED_ATOMIC
:
270 case SHADER_OPCODE_TYPED_SURFACE_READ
:
271 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
272 case SHADER_OPCODE_URB_WRITE_SIMD8
:
273 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
274 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
275 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
276 case SHADER_OPCODE_URB_READ_SIMD8
:
277 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
279 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
280 return src
[1].file
== VGRF
;
281 case FS_OPCODE_FB_WRITE
:
282 return src
[0].file
== VGRF
;
285 return src
[0].file
== VGRF
;
292 * Returns true if this instruction's sources and destinations cannot
293 * safely be the same register.
295 * In most cases, a register can be written over safely by the same
296 * instruction that is its last use. For a single instruction, the
297 * sources are dereferenced before writing of the destination starts
300 * However, there are a few cases where this can be problematic:
302 * - Virtual opcodes that translate to multiple instructions in the
303 * code generator: if src == dst and one instruction writes the
304 * destination before a later instruction reads the source, then
305 * src will have been clobbered.
307 * - SIMD16 compressed instructions with certain regioning (see below).
309 * The register allocator uses this information to set up conflicts between
310 * GRF sources and the destination.
313 fs_inst::has_source_and_destination_hazard() const
316 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
317 /* Multiple partial writes to the destination */
320 /* The SIMD16 compressed instruction
322 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
324 * is actually decoded in hardware as:
326 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
327 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
329 * Which is safe. However, if we have uniform accesses
330 * happening, we get into trouble:
332 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
333 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
335 * Now our destination for the first instruction overwrote the
336 * second instruction's src0, and we get garbage for those 8
337 * pixels. There's a similar issue for the pre-gen6
338 * pixel_x/pixel_y, which are registers of 16-bit values and thus
339 * would get stomped by the first decode as well.
341 if (exec_size
== 16) {
342 for (int i
= 0; i
< sources
; i
++) {
343 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
344 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
345 src
[i
].type
== BRW_REGISTER_TYPE_W
||
346 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
347 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
357 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
359 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
362 fs_reg reg
= this->src
[0];
363 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
366 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
369 for (int i
= 0; i
< this->sources
; i
++) {
370 reg
.type
= this->src
[i
].type
;
371 if (!this->src
[i
].equals(reg
))
374 if (i
< this->header_size
) {
377 reg
.reg_offset
+= this->exec_size
/ 8;
385 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
387 if (devinfo
->gen
== 6 && is_math())
390 if (is_send_from_grf())
393 if (!backend_instruction::can_do_source_mods())
400 fs_inst::can_change_types() const
402 return dst
.type
== src
[0].type
&&
403 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
404 (opcode
== BRW_OPCODE_MOV
||
405 (opcode
== BRW_OPCODE_SEL
&&
406 dst
.type
== src
[1].type
&&
407 predicate
!= BRW_PREDICATE_NONE
&&
408 !src
[1].abs
&& !src
[1].negate
));
412 fs_inst::has_side_effects() const
414 return this->eot
|| backend_instruction::has_side_effects();
420 memset(this, 0, sizeof(*this));
424 /** Generic unset register constructor. */
428 this->file
= BAD_FILE
;
431 fs_reg::fs_reg(struct ::brw_reg reg
) :
434 this->reg_offset
= 0;
435 this->subreg_offset
= 0;
437 if (this->file
== IMM
&&
438 (this->type
!= BRW_REGISTER_TYPE_V
&&
439 this->type
!= BRW_REGISTER_TYPE_UV
&&
440 this->type
!= BRW_REGISTER_TYPE_VF
)) {
446 fs_reg::equals(const fs_reg
&r
) const
448 return (this->backend_reg::equals(r
) &&
449 subreg_offset
== r
.subreg_offset
&&
454 fs_reg::set_smear(unsigned subreg
)
456 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
457 subreg_offset
= subreg
* type_sz(type
);
463 fs_reg::is_contiguous() const
469 fs_reg::component_size(unsigned width
) const
471 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
474 return MAX2(width
* stride
, 1) * type_sz(type
);
478 type_size_scalar(const struct glsl_type
*type
)
480 unsigned int size
, i
;
482 switch (type
->base_type
) {
485 case GLSL_TYPE_FLOAT
:
487 return type
->components();
488 case GLSL_TYPE_ARRAY
:
489 return type_size_scalar(type
->fields
.array
) * type
->length
;
490 case GLSL_TYPE_STRUCT
:
492 for (i
= 0; i
< type
->length
; i
++) {
493 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
496 case GLSL_TYPE_SAMPLER
:
497 /* Samplers take up no register space, since they're baked in at
501 case GLSL_TYPE_ATOMIC_UINT
:
503 case GLSL_TYPE_SUBROUTINE
:
505 case GLSL_TYPE_IMAGE
:
506 return BRW_IMAGE_PARAM_SIZE
;
508 case GLSL_TYPE_ERROR
:
509 case GLSL_TYPE_INTERFACE
:
510 case GLSL_TYPE_DOUBLE
:
511 case GLSL_TYPE_FUNCTION
:
512 unreachable("not reached");
519 * Returns the number of scalar components needed to store type, assuming
520 * that vectors are padded out to vec4.
522 * This has the packing rules of type_size_vec4(), but counts components
523 * similar to type_size_scalar().
526 type_size_vec4_times_4(const struct glsl_type
*type
)
528 return 4 * type_size_vec4(type
);
532 * Create a MOV to read the timestamp register.
534 * The caller is responsible for emitting the MOV. The return value is
535 * the destination of the MOV, with extra parameters set.
538 fs_visitor::get_timestamp(const fs_builder
&bld
)
540 assert(devinfo
->gen
>= 7);
542 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
545 BRW_REGISTER_TYPE_UD
));
547 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
549 /* We want to read the 3 fields we care about even if it's not enabled in
552 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
558 fs_visitor::emit_shader_time_begin()
560 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
562 /* We want only the low 32 bits of the timestamp. Since it's running
563 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
564 * which is plenty of time for our purposes. It is identical across the
565 * EUs, but since it's tracking GPU core speed it will increment at a
566 * varying rate as render P-states change.
568 shader_start_time
.set_smear(0);
572 fs_visitor::emit_shader_time_end()
574 /* Insert our code just before the final SEND with EOT. */
575 exec_node
*end
= this->instructions
.get_tail();
576 assert(end
&& ((fs_inst
*) end
)->eot
);
577 const fs_builder ibld
= bld
.annotate("shader time end")
578 .exec_all().at(NULL
, end
);
580 fs_reg shader_end_time
= get_timestamp(ibld
);
582 /* We only use the low 32 bits of the timestamp - see
583 * emit_shader_time_begin()).
585 * We could also check if render P-states have changed (or anything
586 * else that might disrupt timing) by setting smear to 2 and checking if
587 * that field is != 0.
589 shader_end_time
.set_smear(0);
591 /* Check that there weren't any timestamp reset events (assuming these
592 * were the only two timestamp reads that happened).
594 fs_reg reset
= shader_end_time
;
596 set_condmod(BRW_CONDITIONAL_Z
,
597 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
598 ibld
.IF(BRW_PREDICATE_NORMAL
);
600 fs_reg start
= shader_start_time
;
602 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
605 const fs_builder cbld
= ibld
.group(1, 0);
606 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
608 /* If there were no instructions between the two timestamp gets, the diff
609 * is 2 cycles. Remove that overhead, so I can forget about that when
610 * trying to determine the time taken for single instructions.
612 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
613 SHADER_TIME_ADD(cbld
, 0, diff
);
614 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
615 ibld
.emit(BRW_OPCODE_ELSE
);
616 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
617 ibld
.emit(BRW_OPCODE_ENDIF
);
621 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
622 int shader_time_subindex
,
625 int index
= shader_time_index
* 3 + shader_time_subindex
;
626 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
629 if (dispatch_width
== 8)
630 payload
= vgrf(glsl_type::uvec2_type
);
632 payload
= vgrf(glsl_type::uint_type
);
634 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
638 fs_visitor::vfail(const char *format
, va_list va
)
647 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
648 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
650 this->fail_msg
= msg
;
653 fprintf(stderr
, "%s", msg
);
658 fs_visitor::fail(const char *format
, ...)
662 va_start(va
, format
);
668 * Mark this program as impossible to compile in SIMD16 mode.
670 * During the SIMD8 compile (which happens first), we can detect and flag
671 * things that are unsupported in SIMD16 mode, so the compiler can skip
672 * the SIMD16 compile altogether.
674 * During a SIMD16 compile (if one happens anyway), this just calls fail().
677 fs_visitor::no16(const char *msg
)
679 if (dispatch_width
== 16) {
682 simd16_unsupported
= true;
684 compiler
->shader_perf_log(log_data
,
685 "SIMD16 shader failed to compile: %s", msg
);
690 * Returns true if the instruction has a flag that means it won't
691 * update an entire destination register.
693 * For example, dead code elimination and live variable analysis want to know
694 * when a write to a variable screens off any preceding values that were in
698 fs_inst::is_partial_write() const
700 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
701 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
702 !this->dst
.is_contiguous());
706 fs_inst::components_read(unsigned i
) const
709 case FS_OPCODE_LINTERP
:
715 case FS_OPCODE_PIXEL_X
:
716 case FS_OPCODE_PIXEL_Y
:
720 case FS_OPCODE_FB_WRITE_LOGICAL
:
721 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
722 /* First/second FB write color. */
724 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
728 case SHADER_OPCODE_TEX_LOGICAL
:
729 case SHADER_OPCODE_TXD_LOGICAL
:
730 case SHADER_OPCODE_TXF_LOGICAL
:
731 case SHADER_OPCODE_TXL_LOGICAL
:
732 case SHADER_OPCODE_TXS_LOGICAL
:
733 case FS_OPCODE_TXB_LOGICAL
:
734 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
735 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
736 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
737 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
738 case SHADER_OPCODE_LOD_LOGICAL
:
739 case SHADER_OPCODE_TG4_LOGICAL
:
740 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
741 assert(src
[9].file
== IMM
&& src
[10].file
== IMM
);
742 /* Texture coordinates. */
745 /* Texture derivatives. */
746 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
748 /* Texture offset. */
752 else if (i
== 5 && opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
757 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
758 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
759 assert(src
[3].file
== IMM
);
760 /* Surface coordinates. */
763 /* Surface operation source (ignored for reads). */
769 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
770 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
771 assert(src
[3].file
== IMM
&&
773 /* Surface coordinates. */
776 /* Surface operation source. */
782 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
783 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
784 assert(src
[3].file
== IMM
&&
786 const unsigned op
= src
[4].ud
;
787 /* Surface coordinates. */
790 /* Surface operation source. */
791 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
793 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
794 op
== BRW_AOP_PREDEC
))
806 fs_inst::regs_read(int arg
) const
809 case FS_OPCODE_FB_WRITE
:
810 case SHADER_OPCODE_URB_WRITE_SIMD8
:
811 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
812 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
813 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
814 case SHADER_OPCODE_URB_READ_SIMD8
:
815 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
816 case SHADER_OPCODE_UNTYPED_ATOMIC
:
817 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
818 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
819 case SHADER_OPCODE_TYPED_ATOMIC
:
820 case SHADER_OPCODE_TYPED_SURFACE_READ
:
821 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
822 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
827 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
828 /* The payload is actually stored in src1 */
833 case FS_OPCODE_LINTERP
:
838 case SHADER_OPCODE_LOAD_PAYLOAD
:
839 if (arg
< this->header_size
)
843 case CS_OPCODE_CS_TERMINATE
:
844 case SHADER_OPCODE_BARRIER
:
847 case SHADER_OPCODE_MOV_INDIRECT
:
849 assert(src
[2].file
== IMM
);
850 unsigned region_length
= src
[2].ud
;
852 if (src
[0].file
== UNIFORM
) {
853 assert(region_length
% 4 == 0);
854 return region_length
/ 4;
855 } else if (src
[0].file
== FIXED_GRF
) {
856 /* If the start of the region is not register aligned, then
857 * there's some portion of the register that's technically
858 * unread at the beginning.
860 * However, the register allocator works in terms of whole
861 * registers, and does not use subnr. It assumes that the
862 * read starts at the beginning of the register, and extends
863 * regs_read() whole registers beyond that.
865 * To compensate, we extend the region length to include this
866 * unread portion at the beginning.
869 region_length
+= src
[0].subnr
;
871 return DIV_ROUND_UP(region_length
, REG_SIZE
);
873 assert(!"Invalid register file");
879 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
884 switch (src
[arg
].file
) {
894 return DIV_ROUND_UP(components_read(arg
) *
895 src
[arg
].component_size(exec_size
),
898 unreachable("MRF registers are not allowed as sources");
904 fs_inst::reads_flag() const
910 fs_inst::writes_flag() const
912 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
913 opcode
!= BRW_OPCODE_IF
&&
914 opcode
!= BRW_OPCODE_WHILE
)) ||
915 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
919 * Returns how many MRFs an FS opcode will write over.
921 * Note that this is not the 0 or 1 implied writes in an actual gen
922 * instruction -- the FS opcodes often generate MOVs in addition.
925 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
930 if (inst
->base_mrf
== -1)
933 switch (inst
->opcode
) {
934 case SHADER_OPCODE_RCP
:
935 case SHADER_OPCODE_RSQ
:
936 case SHADER_OPCODE_SQRT
:
937 case SHADER_OPCODE_EXP2
:
938 case SHADER_OPCODE_LOG2
:
939 case SHADER_OPCODE_SIN
:
940 case SHADER_OPCODE_COS
:
941 return 1 * dispatch_width
/ 8;
942 case SHADER_OPCODE_POW
:
943 case SHADER_OPCODE_INT_QUOTIENT
:
944 case SHADER_OPCODE_INT_REMAINDER
:
945 return 2 * dispatch_width
/ 8;
946 case SHADER_OPCODE_TEX
:
948 case SHADER_OPCODE_TXD
:
949 case SHADER_OPCODE_TXF
:
950 case SHADER_OPCODE_TXF_CMS
:
951 case SHADER_OPCODE_TXF_CMS_W
:
952 case SHADER_OPCODE_TXF_MCS
:
953 case SHADER_OPCODE_TG4
:
954 case SHADER_OPCODE_TG4_OFFSET
:
955 case SHADER_OPCODE_TXL
:
956 case SHADER_OPCODE_TXS
:
957 case SHADER_OPCODE_LOD
:
958 case SHADER_OPCODE_SAMPLEINFO
:
960 case FS_OPCODE_FB_WRITE
:
962 case FS_OPCODE_GET_BUFFER_SIZE
:
963 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
964 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
966 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
968 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
970 case SHADER_OPCODE_UNTYPED_ATOMIC
:
971 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
972 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
973 case SHADER_OPCODE_TYPED_ATOMIC
:
974 case SHADER_OPCODE_TYPED_SURFACE_READ
:
975 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
976 case SHADER_OPCODE_URB_WRITE_SIMD8
:
977 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
978 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
979 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
980 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
981 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
982 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
983 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
986 unreachable("not reached");
991 fs_visitor::vgrf(const glsl_type
*const type
)
993 int reg_width
= dispatch_width
/ 8;
994 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
995 brw_type_for_base_type(type
));
998 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1003 this->type
= BRW_REGISTER_TYPE_F
;
1004 this->stride
= (file
== UNIFORM
? 0 : 1);
1007 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1013 this->stride
= (file
== UNIFORM
? 0 : 1);
1016 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1017 * This brings in those uniform definitions
1020 fs_visitor::import_uniforms(fs_visitor
*v
)
1022 this->push_constant_loc
= v
->push_constant_loc
;
1023 this->pull_constant_loc
= v
->pull_constant_loc
;
1024 this->uniforms
= v
->uniforms
;
1028 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
1029 bool origin_upper_left
)
1031 assert(stage
== MESA_SHADER_FRAGMENT
);
1032 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1033 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1035 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
1037 /* gl_FragCoord.x */
1038 if (pixel_center_integer
) {
1039 bld
.MOV(wpos
, this->pixel_x
);
1041 bld
.ADD(wpos
, this->pixel_x
, brw_imm_f(0.5f
));
1043 wpos
= offset(wpos
, bld
, 1);
1045 /* gl_FragCoord.y */
1046 if (!flip
&& pixel_center_integer
) {
1047 bld
.MOV(wpos
, this->pixel_y
);
1049 fs_reg pixel_y
= this->pixel_y
;
1050 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
1053 pixel_y
.negate
= true;
1054 offset
+= key
->drawable_height
- 1.0f
;
1057 bld
.ADD(wpos
, pixel_y
, brw_imm_f(offset
));
1059 wpos
= offset(wpos
, bld
, 1);
1061 /* gl_FragCoord.z */
1062 if (devinfo
->gen
>= 6) {
1063 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1065 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1066 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1067 interp_reg(VARYING_SLOT_POS
, 2));
1069 wpos
= offset(wpos
, bld
, 1);
1071 /* gl_FragCoord.w: Already set up in emit_interpolation */
1072 bld
.MOV(wpos
, this->wpos_w
);
1078 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1079 glsl_interp_qualifier interpolation_mode
,
1080 bool is_centroid
, bool is_sample
)
1082 brw_wm_barycentric_interp_mode barycoord_mode
;
1083 if (devinfo
->gen
>= 6) {
1085 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1086 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1088 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1089 } else if (is_sample
) {
1090 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1091 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1093 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1095 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1096 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1098 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1101 /* On Ironlake and below, there is only one interpolation mode.
1102 * Centroid interpolation doesn't mean anything on this hardware --
1103 * there is no multisampling.
1105 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1107 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1108 this->delta_xy
[barycoord_mode
], interp
);
1112 fs_visitor::emit_general_interpolation(fs_reg
*attr
, const char *name
,
1113 const glsl_type
*type
,
1114 glsl_interp_qualifier interpolation_mode
,
1115 int *location
, bool mod_centroid
,
1118 assert(stage
== MESA_SHADER_FRAGMENT
);
1119 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1120 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1122 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1124 *location
== VARYING_SLOT_COL0
|| *location
== VARYING_SLOT_COL1
;
1125 if (key
->flat_shade
&& is_gl_Color
) {
1126 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1128 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1132 if (type
->is_array() || type
->is_matrix()) {
1133 const glsl_type
*elem_type
= glsl_get_array_element(type
);
1134 const unsigned length
= glsl_get_length(type
);
1136 for (unsigned i
= 0; i
< length
; i
++) {
1137 emit_general_interpolation(attr
, name
, elem_type
, interpolation_mode
,
1138 location
, mod_centroid
, mod_sample
);
1140 } else if (type
->is_record()) {
1141 for (unsigned i
= 0; i
< type
->length
; i
++) {
1142 const glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
1143 emit_general_interpolation(attr
, name
, field_type
, interpolation_mode
,
1144 location
, mod_centroid
, mod_sample
);
1147 assert(type
->is_scalar() || type
->is_vector());
1149 if (prog_data
->urb_setup
[*location
] == -1) {
1150 /* If there's no incoming setup data for this slot, don't
1151 * emit interpolation for it.
1153 *attr
= offset(*attr
, bld
, type
->vector_elements
);
1158 attr
->type
= brw_type_for_base_type(type
->get_scalar_type());
1160 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1161 /* Constant interpolation (flat shading) case. The SF has
1162 * handed us defined values in only the constant offset
1163 * field of the setup reg.
1165 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1166 struct brw_reg interp
= interp_reg(*location
, i
);
1167 interp
= suboffset(interp
, 3);
1168 interp
.type
= attr
->type
;
1169 bld
.emit(FS_OPCODE_CINTERP
, *attr
, fs_reg(interp
));
1170 *attr
= offset(*attr
, bld
, 1);
1173 /* Smooth/noperspective interpolation case. */
1174 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1175 struct brw_reg interp
= interp_reg(*location
, i
);
1176 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1177 /* Get the pixel/sample mask into f0 so that we know
1178 * which pixels are lit. Then, for each channel that is
1179 * unlit, replace the centroid data with non-centroid
1182 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1185 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1187 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1188 inst
->predicate_inverse
= true;
1189 if (devinfo
->has_pln
)
1190 inst
->no_dd_clear
= true;
1192 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1193 mod_centroid
&& !key
->persample_shading
,
1194 mod_sample
|| key
->persample_shading
);
1195 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1196 inst
->predicate_inverse
= false;
1197 if (devinfo
->has_pln
)
1198 inst
->no_dd_check
= true;
1201 emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1202 mod_centroid
&& !key
->persample_shading
,
1203 mod_sample
|| key
->persample_shading
);
1205 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1206 bld
.MUL(*attr
, *attr
, this->pixel_w
);
1208 *attr
= offset(*attr
, bld
, 1);
1216 fs_visitor::emit_frontfacing_interpolation()
1218 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1220 if (devinfo
->gen
>= 6) {
1221 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1222 * a boolean result from this (~0/true or 0/false).
1224 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1225 * this task in only one instruction:
1226 * - a negation source modifier will flip the bit; and
1227 * - a W -> D type conversion will sign extend the bit into the high
1228 * word of the destination.
1230 * An ASR 15 fills the low word of the destination.
1232 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1235 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1237 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1238 * a boolean result from this (1/true or 0/false).
1240 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1241 * the negation source modifier to flip it. Unfortunately the SHR
1242 * instruction only operates on UD (or D with an abs source modifier)
1243 * sources without negation.
1245 * Instead, use ASR (which will give ~0/true or 0/false).
1247 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1250 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1257 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1259 assert(stage
== MESA_SHADER_FRAGMENT
);
1260 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1261 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1263 if (key
->compute_pos_offset
) {
1264 /* Convert int_sample_pos to floating point */
1265 bld
.MOV(dst
, int_sample_pos
);
1266 /* Scale to the range [0, 1] */
1267 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1270 /* From ARB_sample_shading specification:
1271 * "When rendering to a non-multisample buffer, or if multisample
1272 * rasterization is disabled, gl_SamplePosition will always be
1275 bld
.MOV(dst
, brw_imm_f(0.5f
));
1280 fs_visitor::emit_samplepos_setup()
1282 assert(devinfo
->gen
>= 6);
1284 const fs_builder abld
= bld
.annotate("compute sample position");
1285 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1287 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1288 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1290 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1291 * mode will be enabled.
1293 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1294 * R31.1:0 Position Offset X/Y for Slot[3:0]
1295 * R31.3:2 Position Offset X/Y for Slot[7:4]
1298 * The X, Y sample positions come in as bytes in thread payload. So, read
1299 * the positions using vstride=16, width=8, hstride=2.
1301 struct brw_reg sample_pos_reg
=
1302 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1303 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1305 if (dispatch_width
== 8) {
1306 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1308 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1309 abld
.half(1).MOV(half(int_sample_x
, 1),
1310 fs_reg(suboffset(sample_pos_reg
, 16)));
1312 /* Compute gl_SamplePosition.x */
1313 compute_sample_position(pos
, int_sample_x
);
1314 pos
= offset(pos
, abld
, 1);
1315 if (dispatch_width
== 8) {
1316 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1318 abld
.half(0).MOV(half(int_sample_y
, 0),
1319 fs_reg(suboffset(sample_pos_reg
, 1)));
1320 abld
.half(1).MOV(half(int_sample_y
, 1),
1321 fs_reg(suboffset(sample_pos_reg
, 17)));
1323 /* Compute gl_SamplePosition.y */
1324 compute_sample_position(pos
, int_sample_y
);
1329 fs_visitor::emit_sampleid_setup()
1331 assert(stage
== MESA_SHADER_FRAGMENT
);
1332 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1333 assert(devinfo
->gen
>= 6);
1335 const fs_builder abld
= bld
.annotate("compute sample id");
1336 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1338 if (key
->compute_sample_id
) {
1339 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1341 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1343 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1344 * 8x multisampling, subspan 0 will represent sample N (where N
1345 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1346 * 7. We can find the value of N by looking at R0.0 bits 7:6
1347 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1348 * (since samples are always delivered in pairs). That is, we
1349 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1350 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1351 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1352 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1353 * populating a temporary variable with the sequence (0, 1, 2, 3),
1354 * and then reading from it using vstride=1, width=4, hstride=0.
1355 * These computations hold good for 4x multisampling as well.
1357 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1358 * the first four slots are sample 0 of subspan 0; the next four
1359 * are sample 1 of subspan 0; the third group is sample 0 of
1360 * subspan 1, and finally sample 1 of subspan 1.
1363 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1364 * accomodate 16x MSAA.
1366 unsigned sspi_mask
= devinfo
->gen
>= 9 ? 0x1c0 : 0xc0;
1368 abld
.exec_all().group(1, 0)
1369 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1370 brw_imm_ud(sspi_mask
));
1371 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1373 /* This works for both SIMD8 and SIMD16 */
1374 abld
.exec_all().group(4, 0)
1375 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1377 /* This special instruction takes care of setting vstride=1,
1378 * width=4, hstride=0 of t2 during an ADD instruction.
1380 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1382 /* As per GL_ARB_sample_shading specification:
1383 * "When rendering to a non-multisample buffer, or if multisample
1384 * rasterization is disabled, gl_SampleID will always be zero."
1386 abld
.MOV(*reg
, brw_imm_d(0));
1393 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1395 if (!src
.abs
&& !src
.negate
)
1398 fs_reg temp
= bld
.vgrf(src
.type
);
1405 fs_visitor::emit_discard_jump()
1407 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1409 /* For performance, after a discard, jump to the end of the
1410 * shader if all relevant channels have been discarded.
1412 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1413 discard_jump
->flag_subreg
= 1;
1415 discard_jump
->predicate
= (dispatch_width
== 8)
1416 ? BRW_PREDICATE_ALIGN1_ANY8H
1417 : BRW_PREDICATE_ALIGN1_ANY16H
;
1418 discard_jump
->predicate_inverse
= true;
1422 fs_visitor::emit_gs_thread_end()
1424 assert(stage
== MESA_SHADER_GEOMETRY
);
1426 struct brw_gs_prog_data
*gs_prog_data
=
1427 (struct brw_gs_prog_data
*) prog_data
;
1429 if (gs_compile
->control_data_header_size_bits
> 0) {
1430 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1433 const fs_builder abld
= bld
.annotate("thread end");
1436 if (gs_prog_data
->static_vertex_count
!= -1) {
1437 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1438 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1439 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1440 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1441 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1444 /* Delete now dead instructions. */
1445 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1451 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1455 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1456 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1457 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1460 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1461 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1462 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1463 sources
[1] = this->final_gs_vertex_count
;
1464 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1465 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1473 fs_visitor::assign_curb_setup()
1475 if (dispatch_width
== 8) {
1476 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1478 if (stage
== MESA_SHADER_FRAGMENT
) {
1479 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1480 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1481 } else if (stage
== MESA_SHADER_COMPUTE
) {
1482 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1483 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1485 unreachable("Unsupported shader type!");
1489 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1491 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1492 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1493 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1494 if (inst
->src
[i
].file
== UNIFORM
) {
1495 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1497 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1498 constant_nr
= push_constant_loc
[uniform_nr
];
1500 /* Section 5.11 of the OpenGL 4.1 spec says:
1501 * "Out-of-bounds reads return undefined values, which include
1502 * values from other variables of the active program or zero."
1503 * Just return the first push constant.
1508 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1511 brw_reg
.abs
= inst
->src
[i
].abs
;
1512 brw_reg
.negate
= inst
->src
[i
].negate
;
1514 assert(inst
->src
[i
].stride
== 0);
1515 inst
->src
[i
] = byte_offset(
1516 retype(brw_reg
, inst
->src
[i
].type
),
1517 inst
->src
[i
].subreg_offset
);
1522 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1523 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1527 fs_visitor::calculate_urb_setup()
1529 assert(stage
== MESA_SHADER_FRAGMENT
);
1530 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1531 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1533 memset(prog_data
->urb_setup
, -1,
1534 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1537 /* Figure out where each of the incoming setup attributes lands. */
1538 if (devinfo
->gen
>= 6) {
1539 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1540 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1541 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1542 * first 16 varying inputs, so we can put them wherever we want.
1543 * Just put them in order.
1545 * This is useful because it means that (a) inputs not used by the
1546 * fragment shader won't take up valuable register space, and (b) we
1547 * won't have to recompile the fragment shader if it gets paired with
1548 * a different vertex (or geometry) shader.
1550 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1551 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1552 BITFIELD64_BIT(i
)) {
1553 prog_data
->urb_setup
[i
] = urb_next
++;
1557 bool include_vue_header
=
1558 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1560 /* We have enough input varyings that the SF/SBE pipeline stage can't
1561 * arbitrarily rearrange them to suit our whim; we have to put them
1562 * in an order that matches the output of the previous pipeline stage
1563 * (geometry or vertex shader).
1565 struct brw_vue_map prev_stage_vue_map
;
1566 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1567 key
->input_slots_valid
,
1568 nir
->info
.separate_shader
);
1570 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1572 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1573 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1575 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1576 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1577 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1578 BITFIELD64_BIT(varying
))) {
1579 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1582 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1585 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1586 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1587 /* Point size is packed into the header, not as a general attribute */
1588 if (i
== VARYING_SLOT_PSIZ
)
1591 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1592 /* The back color slot is skipped when the front color is
1593 * also written to. In addition, some slots can be
1594 * written in the vertex shader and not read in the
1595 * fragment shader. So the register number must always be
1596 * incremented, mapped or not.
1598 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1599 prog_data
->urb_setup
[i
] = urb_next
;
1605 * It's a FS only attribute, and we did interpolation for this attribute
1606 * in SF thread. So, count it here, too.
1608 * See compile_sf_prog() for more info.
1610 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1611 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1614 prog_data
->num_varying_inputs
= urb_next
;
1618 fs_visitor::assign_urb_setup()
1620 assert(stage
== MESA_SHADER_FRAGMENT
);
1621 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1623 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1625 /* Offset all the urb_setup[] index by the actual position of the
1626 * setup regs, now that the location of the constants has been chosen.
1628 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1629 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1630 assert(inst
->src
[1].file
== FIXED_GRF
);
1631 inst
->src
[1].nr
+= urb_start
;
1634 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1635 assert(inst
->src
[0].file
== FIXED_GRF
);
1636 inst
->src
[0].nr
+= urb_start
;
1640 /* Each attribute is 4 setup channels, each of which is half a reg. */
1641 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1645 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1647 for (int i
= 0; i
< inst
->sources
; i
++) {
1648 if (inst
->src
[i
].file
== ATTR
) {
1649 int grf
= payload
.num_regs
+
1650 prog_data
->curb_read_length
+
1652 inst
->src
[i
].reg_offset
;
1654 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : inst
->exec_size
;
1655 struct brw_reg reg
=
1656 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1657 inst
->src
[i
].subreg_offset
),
1658 inst
->exec_size
* inst
->src
[i
].stride
,
1659 width
, inst
->src
[i
].stride
);
1660 reg
.abs
= inst
->src
[i
].abs
;
1661 reg
.negate
= inst
->src
[i
].negate
;
1669 fs_visitor::assign_vs_urb_setup()
1671 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1673 assert(stage
== MESA_SHADER_VERTEX
);
1674 int count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1675 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
||
1676 vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1678 if (vs_prog_data
->uses_drawid
)
1681 /* Each attribute is 4 regs. */
1682 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1684 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1686 /* Rewrite all ATTR file references to the hw grf that they land in. */
1687 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1688 convert_attr_sources_to_hw_regs(inst
);
1693 fs_visitor::assign_tes_urb_setup()
1695 assert(stage
== MESA_SHADER_TESS_EVAL
);
1697 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1699 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1701 /* Rewrite all ATTR file references to HW_REGs. */
1702 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1703 convert_attr_sources_to_hw_regs(inst
);
1708 fs_visitor::assign_gs_urb_setup()
1710 assert(stage
== MESA_SHADER_GEOMETRY
);
1712 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1714 first_non_payload_grf
+=
1715 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1717 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1718 /* Rewrite all ATTR file references to GRFs. */
1719 convert_attr_sources_to_hw_regs(inst
);
1725 * Split large virtual GRFs into separate components if we can.
1727 * This is mostly duplicated with what brw_fs_vector_splitting does,
1728 * but that's really conservative because it's afraid of doing
1729 * splitting that doesn't result in real progress after the rest of
1730 * the optimization phases, which would cause infinite looping in
1731 * optimization. We can do it once here, safely. This also has the
1732 * opportunity to split interpolated values, or maybe even uniforms,
1733 * which we don't have at the IR level.
1735 * We want to split, because virtual GRFs are what we register
1736 * allocate and spill (due to contiguousness requirements for some
1737 * instructions), and they're what we naturally generate in the
1738 * codegen process, but most virtual GRFs don't actually need to be
1739 * contiguous sets of GRFs. If we split, we'll end up with reduced
1740 * live intervals and better dead code elimination and coalescing.
1743 fs_visitor::split_virtual_grfs()
1745 int num_vars
= this->alloc
.count
;
1747 /* Count the total number of registers */
1749 int vgrf_to_reg
[num_vars
];
1750 for (int i
= 0; i
< num_vars
; i
++) {
1751 vgrf_to_reg
[i
] = reg_count
;
1752 reg_count
+= alloc
.sizes
[i
];
1755 /* An array of "split points". For each register slot, this indicates
1756 * if this slot can be separated from the previous slot. Every time an
1757 * instruction uses multiple elements of a register (as a source or
1758 * destination), we mark the used slots as inseparable. Then we go
1759 * through and split the registers into the smallest pieces we can.
1761 bool split_points
[reg_count
];
1762 memset(split_points
, 0, sizeof(split_points
));
1764 /* Mark all used registers as fully splittable */
1765 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1766 if (inst
->dst
.file
== VGRF
) {
1767 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1768 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1769 split_points
[reg
+ j
] = true;
1772 for (int i
= 0; i
< inst
->sources
; i
++) {
1773 if (inst
->src
[i
].file
== VGRF
) {
1774 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1775 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1776 split_points
[reg
+ j
] = true;
1781 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1782 if (inst
->dst
.file
== VGRF
) {
1783 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1784 for (int j
= 1; j
< inst
->regs_written
; j
++)
1785 split_points
[reg
+ j
] = false;
1787 for (int i
= 0; i
< inst
->sources
; i
++) {
1788 if (inst
->src
[i
].file
== VGRF
) {
1789 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1790 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1791 split_points
[reg
+ j
] = false;
1796 int new_virtual_grf
[reg_count
];
1797 int new_reg_offset
[reg_count
];
1800 for (int i
= 0; i
< num_vars
; i
++) {
1801 /* The first one should always be 0 as a quick sanity check. */
1802 assert(split_points
[reg
] == false);
1805 new_reg_offset
[reg
] = 0;
1810 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1811 /* If this is a split point, reset the offset to 0 and allocate a
1812 * new virtual GRF for the previous offset many registers
1814 if (split_points
[reg
]) {
1815 assert(offset
<= MAX_VGRF_SIZE
);
1816 int grf
= alloc
.allocate(offset
);
1817 for (int k
= reg
- offset
; k
< reg
; k
++)
1818 new_virtual_grf
[k
] = grf
;
1821 new_reg_offset
[reg
] = offset
;
1826 /* The last one gets the original register number */
1827 assert(offset
<= MAX_VGRF_SIZE
);
1828 alloc
.sizes
[i
] = offset
;
1829 for (int k
= reg
- offset
; k
< reg
; k
++)
1830 new_virtual_grf
[k
] = i
;
1832 assert(reg
== reg_count
);
1834 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1835 if (inst
->dst
.file
== VGRF
) {
1836 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1837 inst
->dst
.nr
= new_virtual_grf
[reg
];
1838 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1839 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1841 for (int i
= 0; i
< inst
->sources
; i
++) {
1842 if (inst
->src
[i
].file
== VGRF
) {
1843 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1844 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1845 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1846 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1850 invalidate_live_intervals();
1854 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1856 * During code generation, we create tons of temporary variables, many of
1857 * which get immediately killed and are never used again. Yet, in later
1858 * optimization and analysis passes, such as compute_live_intervals, we need
1859 * to loop over all the virtual GRFs. Compacting them can save a lot of
1863 fs_visitor::compact_virtual_grfs()
1865 bool progress
= false;
1866 int remap_table
[this->alloc
.count
];
1867 memset(remap_table
, -1, sizeof(remap_table
));
1869 /* Mark which virtual GRFs are used. */
1870 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1871 if (inst
->dst
.file
== VGRF
)
1872 remap_table
[inst
->dst
.nr
] = 0;
1874 for (int i
= 0; i
< inst
->sources
; i
++) {
1875 if (inst
->src
[i
].file
== VGRF
)
1876 remap_table
[inst
->src
[i
].nr
] = 0;
1880 /* Compact the GRF arrays. */
1882 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1883 if (remap_table
[i
] == -1) {
1884 /* We just found an unused register. This means that we are
1885 * actually going to compact something.
1889 remap_table
[i
] = new_index
;
1890 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1891 invalidate_live_intervals();
1896 this->alloc
.count
= new_index
;
1898 /* Patch all the instructions to use the newly renumbered registers */
1899 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1900 if (inst
->dst
.file
== VGRF
)
1901 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1903 for (int i
= 0; i
< inst
->sources
; i
++) {
1904 if (inst
->src
[i
].file
== VGRF
)
1905 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1909 /* Patch all the references to delta_xy, since they're used in register
1910 * allocation. If they're unused, switch them to BAD_FILE so we don't
1911 * think some random VGRF is delta_xy.
1913 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1914 if (delta_xy
[i
].file
== VGRF
) {
1915 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1916 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1918 delta_xy
[i
].file
= BAD_FILE
;
1927 * Assign UNIFORM file registers to either push constants or pull constants.
1929 * We allow a fragment shader to have more than the specified minimum
1930 * maximum number of fragment shader uniform components (64). If
1931 * there are too many of these, they'd fill up all of register space.
1932 * So, this will push some of them out to the pull constant buffer and
1933 * update the program to load them.
1936 fs_visitor::assign_constant_locations()
1938 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1939 if (dispatch_width
!= 8)
1942 bool is_live
[uniforms
];
1943 memset(is_live
, 0, sizeof(is_live
));
1945 /* For each uniform slot, a value of true indicates that the given slot and
1946 * the next slot must remain contiguous. This is used to keep us from
1947 * splitting arrays apart.
1949 bool contiguous
[uniforms
];
1950 memset(contiguous
, 0, sizeof(contiguous
));
1952 /* First, we walk through the instructions and do two things:
1954 * 1) Figure out which uniforms are live.
1956 * 2) Mark any indirectly used ranges of registers as contiguous.
1958 * Note that we don't move constant-indexed accesses to arrays. No
1959 * testing has been done of the performance impact of this choice.
1961 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1962 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1963 if (inst
->src
[i
].file
!= UNIFORM
)
1966 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1968 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
1969 assert(inst
->src
[2].ud
% 4 == 0);
1970 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
1971 assert(last
< uniforms
);
1973 for (unsigned j
= constant_nr
; j
< last
; j
++) {
1975 contiguous
[j
] = true;
1977 is_live
[last
] = true;
1979 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1980 is_live
[constant_nr
] = true;
1985 /* Only allow 16 registers (128 uniform components) as push constants.
1987 * Just demote the end of the list. We could probably do better
1988 * here, demoting things that are rarely used in the program first.
1990 * If changing this value, note the limitation about total_regs in
1993 const unsigned int max_push_components
= 16 * 8;
1995 /* We push small arrays, but no bigger than 16 floats. This is big enough
1996 * for a vec4 but hopefully not large enough to push out other stuff. We
1997 * should probably use a better heuristic at some point.
1999 const unsigned int max_chunk_size
= 16;
2001 unsigned int num_push_constants
= 0;
2002 unsigned int num_pull_constants
= 0;
2004 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2005 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2007 int chunk_start
= -1;
2008 for (unsigned u
= 0; u
< uniforms
; u
++) {
2009 push_constant_loc
[u
] = -1;
2010 pull_constant_loc
[u
] = -1;
2015 /* This is the first live uniform in the chunk */
2016 if (chunk_start
< 0)
2019 /* If this element does not need to be contiguous with the next, we
2020 * split at this point and everthing between chunk_start and u forms a
2023 if (!contiguous
[u
]) {
2024 unsigned chunk_size
= u
- chunk_start
+ 1;
2026 if (num_push_constants
+ chunk_size
<= max_push_components
&&
2027 chunk_size
<= max_chunk_size
) {
2028 for (unsigned j
= chunk_start
; j
<= u
; j
++)
2029 push_constant_loc
[j
] = num_push_constants
++;
2031 for (unsigned j
= chunk_start
; j
<= u
; j
++)
2032 pull_constant_loc
[j
] = num_pull_constants
++;
2039 stage_prog_data
->nr_params
= num_push_constants
;
2040 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2042 /* Up until now, the param[] array has been indexed by reg + reg_offset
2043 * of UNIFORM registers. Move pull constants into pull_param[] and
2044 * condense param[] to only contain the uniforms we chose to push.
2046 * NOTE: Because we are condensing the params[] array, we know that
2047 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2048 * having to make a copy.
2050 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2051 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
2053 if (pull_constant_loc
[i
] != -1) {
2054 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2055 } else if (push_constant_loc
[i
] != -1) {
2056 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2062 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2063 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2066 fs_visitor::lower_constant_loads()
2068 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2070 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2071 /* Set up the annotation tracking for new generated instructions. */
2072 const fs_builder
ibld(this, block
, inst
);
2074 for (int i
= 0; i
< inst
->sources
; i
++) {
2075 if (inst
->src
[i
].file
!= UNIFORM
)
2078 /* We'll handle this case later */
2079 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2082 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2083 if (location
>= uniforms
)
2084 continue; /* Out of bounds access */
2086 int pull_index
= pull_constant_loc
[location
];
2088 if (pull_index
== -1)
2091 assert(inst
->src
[i
].stride
== 0);
2093 fs_reg dst
= vgrf(glsl_type::float_type
);
2094 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2095 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2096 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2097 dst
, brw_imm_ud(index
), offset
);
2099 /* Rewrite the instruction to use the temporary VGRF. */
2100 inst
->src
[i
].file
= VGRF
;
2101 inst
->src
[i
].nr
= dst
.nr
;
2102 inst
->src
[i
].reg_offset
= 0;
2103 inst
->src
[i
].set_smear(pull_index
& 3);
2105 brw_mark_surface_used(prog_data
, index
);
2108 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2109 inst
->src
[0].file
== UNIFORM
) {
2111 unsigned location
= inst
->src
[0].nr
+ inst
->src
[0].reg_offset
;
2112 if (location
>= uniforms
)
2113 continue; /* Out of bounds access */
2115 int pull_index
= pull_constant_loc
[location
];
2117 if (pull_index
== -1)
2120 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2124 inst
->remove(block
);
2126 brw_mark_surface_used(prog_data
, index
);
2129 invalidate_live_intervals();
2133 fs_visitor::opt_algebraic()
2135 bool progress
= false;
2137 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2138 switch (inst
->opcode
) {
2139 case BRW_OPCODE_MOV
:
2140 if (inst
->src
[0].file
!= IMM
)
2143 if (inst
->saturate
) {
2144 if (inst
->dst
.type
!= inst
->src
[0].type
)
2145 assert(!"unimplemented: saturate mixed types");
2147 if (brw_saturate_immediate(inst
->dst
.type
,
2148 &inst
->src
[0].as_brw_reg())) {
2149 inst
->saturate
= false;
2155 case BRW_OPCODE_MUL
:
2156 if (inst
->src
[1].file
!= IMM
)
2160 if (inst
->src
[1].is_one()) {
2161 inst
->opcode
= BRW_OPCODE_MOV
;
2162 inst
->src
[1] = reg_undef
;
2168 if (inst
->src
[1].is_negative_one()) {
2169 inst
->opcode
= BRW_OPCODE_MOV
;
2170 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2171 inst
->src
[1] = reg_undef
;
2177 if (inst
->src
[1].is_zero()) {
2178 inst
->opcode
= BRW_OPCODE_MOV
;
2179 inst
->src
[0] = inst
->src
[1];
2180 inst
->src
[1] = reg_undef
;
2185 if (inst
->src
[0].file
== IMM
) {
2186 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2187 inst
->opcode
= BRW_OPCODE_MOV
;
2188 inst
->src
[0].f
*= inst
->src
[1].f
;
2189 inst
->src
[1] = reg_undef
;
2194 case BRW_OPCODE_ADD
:
2195 if (inst
->src
[1].file
!= IMM
)
2199 if (inst
->src
[1].is_zero()) {
2200 inst
->opcode
= BRW_OPCODE_MOV
;
2201 inst
->src
[1] = reg_undef
;
2206 if (inst
->src
[0].file
== IMM
) {
2207 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2208 inst
->opcode
= BRW_OPCODE_MOV
;
2209 inst
->src
[0].f
+= inst
->src
[1].f
;
2210 inst
->src
[1] = reg_undef
;
2216 if (inst
->src
[0].equals(inst
->src
[1])) {
2217 inst
->opcode
= BRW_OPCODE_MOV
;
2218 inst
->src
[1] = reg_undef
;
2223 case BRW_OPCODE_LRP
:
2224 if (inst
->src
[1].equals(inst
->src
[2])) {
2225 inst
->opcode
= BRW_OPCODE_MOV
;
2226 inst
->src
[0] = inst
->src
[1];
2227 inst
->src
[1] = reg_undef
;
2228 inst
->src
[2] = reg_undef
;
2233 case BRW_OPCODE_CMP
:
2234 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2236 inst
->src
[0].negate
&&
2237 inst
->src
[1].is_zero()) {
2238 inst
->src
[0].abs
= false;
2239 inst
->src
[0].negate
= false;
2240 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2245 case BRW_OPCODE_SEL
:
2246 if (inst
->src
[0].equals(inst
->src
[1])) {
2247 inst
->opcode
= BRW_OPCODE_MOV
;
2248 inst
->src
[1] = reg_undef
;
2249 inst
->predicate
= BRW_PREDICATE_NONE
;
2250 inst
->predicate_inverse
= false;
2252 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2253 switch (inst
->conditional_mod
) {
2254 case BRW_CONDITIONAL_LE
:
2255 case BRW_CONDITIONAL_L
:
2256 switch (inst
->src
[1].type
) {
2257 case BRW_REGISTER_TYPE_F
:
2258 if (inst
->src
[1].f
>= 1.0f
) {
2259 inst
->opcode
= BRW_OPCODE_MOV
;
2260 inst
->src
[1] = reg_undef
;
2261 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2269 case BRW_CONDITIONAL_GE
:
2270 case BRW_CONDITIONAL_G
:
2271 switch (inst
->src
[1].type
) {
2272 case BRW_REGISTER_TYPE_F
:
2273 if (inst
->src
[1].f
<= 0.0f
) {
2274 inst
->opcode
= BRW_OPCODE_MOV
;
2275 inst
->src
[1] = reg_undef
;
2276 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2288 case BRW_OPCODE_MAD
:
2289 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2290 inst
->opcode
= BRW_OPCODE_MOV
;
2291 inst
->src
[1] = reg_undef
;
2292 inst
->src
[2] = reg_undef
;
2294 } else if (inst
->src
[0].is_zero()) {
2295 inst
->opcode
= BRW_OPCODE_MUL
;
2296 inst
->src
[0] = inst
->src
[2];
2297 inst
->src
[2] = reg_undef
;
2299 } else if (inst
->src
[1].is_one()) {
2300 inst
->opcode
= BRW_OPCODE_ADD
;
2301 inst
->src
[1] = inst
->src
[2];
2302 inst
->src
[2] = reg_undef
;
2304 } else if (inst
->src
[2].is_one()) {
2305 inst
->opcode
= BRW_OPCODE_ADD
;
2306 inst
->src
[2] = reg_undef
;
2308 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2309 inst
->opcode
= BRW_OPCODE_ADD
;
2310 inst
->src
[1].f
*= inst
->src
[2].f
;
2311 inst
->src
[2] = reg_undef
;
2315 case SHADER_OPCODE_RCP
: {
2316 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2317 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2318 if (inst
->src
[0].equals(prev
->dst
)) {
2319 inst
->opcode
= SHADER_OPCODE_RSQ
;
2320 inst
->src
[0] = prev
->src
[0];
2326 case SHADER_OPCODE_BROADCAST
:
2327 if (is_uniform(inst
->src
[0])) {
2328 inst
->opcode
= BRW_OPCODE_MOV
;
2330 inst
->force_writemask_all
= true;
2332 } else if (inst
->src
[1].file
== IMM
) {
2333 inst
->opcode
= BRW_OPCODE_MOV
;
2334 inst
->src
[0] = component(inst
->src
[0],
2337 inst
->force_writemask_all
= true;
2346 /* Swap if src[0] is immediate. */
2347 if (progress
&& inst
->is_commutative()) {
2348 if (inst
->src
[0].file
== IMM
) {
2349 fs_reg tmp
= inst
->src
[1];
2350 inst
->src
[1] = inst
->src
[0];
2359 * Optimize sample messages that have constant zero values for the trailing
2360 * texture coordinates. We can just reduce the message length for these
2361 * instructions instead of reserving a register for it. Trailing parameters
2362 * that aren't sent default to zero anyway. This will cause the dead code
2363 * eliminator to remove the MOV instruction that would otherwise be emitted to
2364 * set up the zero value.
2367 fs_visitor::opt_zero_samples()
2369 /* Gen4 infers the texturing opcode based on the message length so we can't
2372 if (devinfo
->gen
< 5)
2375 bool progress
= false;
2377 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2378 if (!inst
->is_tex())
2381 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2383 if (load_payload
->is_head_sentinel() ||
2384 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2387 /* We don't want to remove the message header or the first parameter.
2388 * Removing the first parameter is not allowed, see the Haswell PRM
2389 * volume 7, page 149:
2391 * "Parameter 0 is required except for the sampleinfo message, which
2392 * has no parameter 0"
2394 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2395 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2396 (inst
->exec_size
/ 8) +
2397 inst
->header_size
- 1].is_zero()) {
2398 inst
->mlen
-= inst
->exec_size
/ 8;
2404 invalidate_live_intervals();
2410 * Optimize sample messages which are followed by the final RT write.
2412 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2413 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2414 * final texturing results copied to the framebuffer write payload and modify
2415 * them to write to the framebuffer directly.
2418 fs_visitor::opt_sampler_eot()
2420 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2422 if (stage
!= MESA_SHADER_FRAGMENT
)
2425 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2428 /* FINISHME: It should be possible to implement this optimization when there
2429 * are multiple drawbuffers.
2431 if (key
->nr_color_regions
!= 1)
2434 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2435 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2436 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2437 assert(fb_write
->eot
);
2438 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2440 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2442 /* There wasn't one; nothing to do. */
2443 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2446 /* 3D Sampler » Messages » Message Format
2448 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2449 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2451 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2452 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2453 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2454 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2455 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2458 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2459 * It's very likely to be the previous instruction.
2461 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2462 if (load_payload
->is_head_sentinel() ||
2463 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2466 assert(!tex_inst
->eot
); /* We can't get here twice */
2467 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2469 const fs_builder
ibld(this, block
, tex_inst
);
2471 tex_inst
->offset
|= fb_write
->target
<< 24;
2472 tex_inst
->eot
= true;
2473 tex_inst
->dst
= ibld
.null_reg_ud();
2474 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2476 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2477 * to create a new LOAD_PAYLOAD command with the same sources and a space
2478 * saved for the header. Using a new destination register not only makes sure
2479 * we have enough space, but it will make sure the dead code eliminator kills
2480 * the instruction that this will replace.
2482 if (tex_inst
->header_size
!= 0)
2485 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2486 load_payload
->sources
+ 1);
2487 fs_reg
*new_sources
=
2488 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2490 new_sources
[0] = fs_reg();
2491 for (int i
= 0; i
< load_payload
->sources
; i
++)
2492 new_sources
[i
+1] = load_payload
->src
[i
];
2494 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2495 * requires a lot of information about the sources to appropriately figure
2496 * out the number of registers needed to be used. Given this stage in our
2497 * optimization, we may not have the appropriate GRFs required by
2498 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2499 * manually emit the instruction.
2501 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2502 load_payload
->exec_size
,
2505 load_payload
->sources
+ 1);
2507 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2508 new_load_payload
->header_size
= 1;
2510 tex_inst
->header_size
= 1;
2511 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2512 tex_inst
->src
[0] = send_header
;
2518 fs_visitor::opt_register_renaming()
2520 bool progress
= false;
2523 int remap
[alloc
.count
];
2524 memset(remap
, -1, sizeof(int) * alloc
.count
);
2526 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2527 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2529 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2530 inst
->opcode
== BRW_OPCODE_WHILE
) {
2534 /* Rewrite instruction sources. */
2535 for (int i
= 0; i
< inst
->sources
; i
++) {
2536 if (inst
->src
[i
].file
== VGRF
&&
2537 remap
[inst
->src
[i
].nr
] != -1 &&
2538 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2539 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2544 const int dst
= inst
->dst
.nr
;
2547 inst
->dst
.file
== VGRF
&&
2548 alloc
.sizes
[inst
->dst
.nr
] == inst
->exec_size
/ 8 &&
2549 !inst
->is_partial_write()) {
2550 if (remap
[dst
] == -1) {
2553 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2554 inst
->dst
.nr
= remap
[dst
];
2557 } else if (inst
->dst
.file
== VGRF
&&
2559 remap
[dst
] != dst
) {
2560 inst
->dst
.nr
= remap
[dst
];
2566 invalidate_live_intervals();
2568 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2569 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2570 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2579 * Remove redundant or useless discard jumps.
2581 * For example, we can eliminate jumps in the following sequence:
2583 * discard-jump (redundant with the next jump)
2584 * discard-jump (useless; jumps to the next instruction)
2588 fs_visitor::opt_redundant_discard_jumps()
2590 bool progress
= false;
2592 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2594 fs_inst
*placeholder_halt
= NULL
;
2595 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2596 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2597 placeholder_halt
= inst
;
2602 if (!placeholder_halt
)
2605 /* Delete any HALTs immediately before the placeholder halt. */
2606 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2607 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2608 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2609 prev
->remove(last_bblock
);
2614 invalidate_live_intervals();
2620 fs_visitor::compute_to_mrf()
2622 bool progress
= false;
2625 /* No MRFs on Gen >= 7. */
2626 if (devinfo
->gen
>= 7)
2629 calculate_live_intervals();
2631 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2635 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2636 inst
->is_partial_write() ||
2637 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2638 inst
->dst
.type
!= inst
->src
[0].type
||
2639 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2640 !inst
->src
[0].is_contiguous() ||
2641 inst
->src
[0].subreg_offset
)
2644 /* Work out which hardware MRF registers are written by this
2647 int mrf_low
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2649 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2650 mrf_high
= mrf_low
+ 4;
2651 } else if (inst
->exec_size
== 16) {
2652 mrf_high
= mrf_low
+ 1;
2657 /* Can't compute-to-MRF this GRF if someone else was going to
2660 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2663 /* Found a move of a GRF to a MRF. Let's see if we can go
2664 * rewrite the thing that made this GRF to write into the MRF.
2666 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2667 if (scan_inst
->dst
.file
== VGRF
&&
2668 scan_inst
->dst
.nr
== inst
->src
[0].nr
) {
2669 /* Found the last thing to write our reg we want to turn
2670 * into a compute-to-MRF.
2673 /* If this one instruction didn't populate all the
2674 * channels, bail. We might be able to rewrite everything
2675 * that writes that reg, but it would require smarter
2676 * tracking to delay the rewriting until complete success.
2678 if (scan_inst
->is_partial_write())
2681 /* Things returning more than one register would need us to
2682 * understand coalescing out more than one MOV at a time.
2684 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2687 /* SEND instructions can't have MRF as a destination. */
2688 if (scan_inst
->mlen
)
2691 if (devinfo
->gen
== 6) {
2692 /* gen6 math instructions must have the destination be
2693 * GRF, so no compute-to-MRF for them.
2695 if (scan_inst
->is_math()) {
2700 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2701 /* Found the creator of our MRF's source value. */
2702 scan_inst
->dst
.file
= MRF
;
2703 scan_inst
->dst
.nr
= inst
->dst
.nr
;
2704 scan_inst
->saturate
|= inst
->saturate
;
2705 inst
->remove(block
);
2711 /* We don't handle control flow here. Most computation of
2712 * values that end up in MRFs are shortly before the MRF
2715 if (block
->start() == scan_inst
)
2718 /* You can't read from an MRF, so if someone else reads our
2719 * MRF's source GRF that we wanted to rewrite, that stops us.
2721 bool interfered
= false;
2722 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2723 if (scan_inst
->src
[i
].file
== VGRF
&&
2724 scan_inst
->src
[i
].nr
== inst
->src
[0].nr
&&
2725 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2732 if (scan_inst
->dst
.file
== MRF
) {
2733 /* If somebody else writes our MRF here, we can't
2734 * compute-to-MRF before that.
2736 int scan_mrf_low
= scan_inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2739 if (scan_inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2740 scan_mrf_high
= scan_mrf_low
+ 4;
2741 } else if (scan_inst
->exec_size
== 16) {
2742 scan_mrf_high
= scan_mrf_low
+ 1;
2744 scan_mrf_high
= scan_mrf_low
;
2747 if (mrf_low
== scan_mrf_low
||
2748 mrf_low
== scan_mrf_high
||
2749 mrf_high
== scan_mrf_low
||
2750 mrf_high
== scan_mrf_high
) {
2755 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2756 /* Found a SEND instruction, which means that there are
2757 * live values in MRFs from base_mrf to base_mrf +
2758 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2761 if (mrf_low
>= scan_inst
->base_mrf
&&
2762 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2765 if (mrf_high
>= scan_inst
->base_mrf
&&
2766 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2774 invalidate_live_intervals();
2780 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2781 * flow. We could probably do better here with some form of divergence
2785 fs_visitor::eliminate_find_live_channel()
2787 bool progress
= false;
2790 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2791 switch (inst
->opcode
) {
2797 case BRW_OPCODE_ENDIF
:
2798 case BRW_OPCODE_WHILE
:
2802 case FS_OPCODE_DISCARD_JUMP
:
2803 /* This can potentially make control flow non-uniform until the end
2808 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2810 inst
->opcode
= BRW_OPCODE_MOV
;
2811 inst
->src
[0] = brw_imm_ud(0u);
2813 inst
->force_writemask_all
= true;
2827 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2828 * instructions to FS_OPCODE_REP_FB_WRITE.
2831 fs_visitor::emit_repclear_shader()
2833 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2835 int color_mrf
= base_mrf
+ 2;
2838 if (uniforms
== 1) {
2839 mov
= bld
.exec_all().group(4, 0)
2840 .MOV(brw_message_reg(color_mrf
),
2841 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2843 struct brw_reg reg
=
2844 brw_reg(BRW_GENERAL_REGISTER_FILE
,
2845 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2846 BRW_VERTICAL_STRIDE_8
,
2848 BRW_HORIZONTAL_STRIDE_4
, BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2850 mov
= bld
.exec_all().group(4, 0)
2851 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2855 if (key
->nr_color_regions
== 1) {
2856 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2857 write
->saturate
= key
->clamp_fragment_color
;
2858 write
->base_mrf
= color_mrf
;
2860 write
->header_size
= 0;
2863 assume(key
->nr_color_regions
> 0);
2864 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2865 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2866 write
->saturate
= key
->clamp_fragment_color
;
2867 write
->base_mrf
= base_mrf
;
2869 write
->header_size
= 2;
2877 assign_constant_locations();
2878 assign_curb_setup();
2880 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2881 if (uniforms
== 1) {
2882 assert(mov
->src
[0].file
== FIXED_GRF
);
2883 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2888 * Walks through basic blocks, looking for repeated MRF writes and
2889 * removing the later ones.
2892 fs_visitor::remove_duplicate_mrf_writes()
2894 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2895 bool progress
= false;
2897 /* Need to update the MRF tracking for compressed instructions. */
2898 if (dispatch_width
== 16)
2901 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2903 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2904 if (inst
->is_control_flow()) {
2905 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2908 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2909 inst
->dst
.file
== MRF
) {
2910 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2911 if (prev_inst
&& inst
->equals(prev_inst
)) {
2912 inst
->remove(block
);
2918 /* Clear out the last-write records for MRFs that were overwritten. */
2919 if (inst
->dst
.file
== MRF
) {
2920 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2923 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2924 /* Found a SEND instruction, which will include two or fewer
2925 * implied MRF writes. We could do better here.
2927 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2928 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2932 /* Clear out any MRF move records whose sources got overwritten. */
2933 if (inst
->dst
.file
== VGRF
) {
2934 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2935 if (last_mrf_move
[i
] &&
2936 last_mrf_move
[i
]->src
[0].nr
== inst
->dst
.nr
) {
2937 last_mrf_move
[i
] = NULL
;
2942 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2943 inst
->dst
.file
== MRF
&&
2944 inst
->src
[0].file
== VGRF
&&
2945 !inst
->is_partial_write()) {
2946 last_mrf_move
[inst
->dst
.nr
] = inst
;
2951 invalidate_live_intervals();
2957 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2959 /* Clear the flag for registers that actually got read (as expected). */
2960 for (int i
= 0; i
< inst
->sources
; i
++) {
2962 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
2963 grf
= inst
->src
[i
].nr
;
2968 if (grf
>= first_grf
&&
2969 grf
< first_grf
+ grf_len
) {
2970 deps
[grf
- first_grf
] = false;
2971 if (inst
->exec_size
== 16)
2972 deps
[grf
- first_grf
+ 1] = false;
2978 * Implements this workaround for the original 965:
2980 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2981 * check for post destination dependencies on this instruction, software
2982 * must ensure that there is no destination hazard for the case of ‘write
2983 * followed by a posted write’ shown in the following example.
2986 * 2. send r3.xy <rest of send instruction>
2989 * Due to no post-destination dependency check on the ‘send’, the above
2990 * code sequence could have two instructions (1 and 2) in flight at the
2991 * same time that both consider ‘r3’ as the target of their final writes.
2994 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2997 int write_len
= inst
->regs_written
;
2998 int first_write_grf
= inst
->dst
.nr
;
2999 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3000 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3002 memset(needs_dep
, false, sizeof(needs_dep
));
3003 memset(needs_dep
, true, write_len
);
3005 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3007 /* Walk backwards looking for writes to registers we're writing which
3008 * aren't read since being written. If we hit the start of the program,
3009 * we assume that there are no outstanding dependencies on entry to the
3012 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3013 /* If we hit control flow, assume that there *are* outstanding
3014 * dependencies, and force their cleanup before our instruction.
3016 if (block
->start() == scan_inst
) {
3017 for (int i
= 0; i
< write_len
; i
++) {
3019 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3020 first_write_grf
+ i
);
3025 /* We insert our reads as late as possible on the assumption that any
3026 * instruction but a MOV that might have left us an outstanding
3027 * dependency has more latency than a MOV.
3029 if (scan_inst
->dst
.file
== VGRF
) {
3030 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
3031 int reg
= scan_inst
->dst
.nr
+ i
;
3033 if (reg
>= first_write_grf
&&
3034 reg
< first_write_grf
+ write_len
&&
3035 needs_dep
[reg
- first_write_grf
]) {
3036 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3037 needs_dep
[reg
- first_write_grf
] = false;
3038 if (scan_inst
->exec_size
== 16)
3039 needs_dep
[reg
- first_write_grf
+ 1] = false;
3044 /* Clear the flag for registers that actually got read (as expected). */
3045 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3047 /* Continue the loop only if we haven't resolved all the dependencies */
3049 for (i
= 0; i
< write_len
; i
++) {
3059 * Implements this workaround for the original 965:
3061 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3062 * used as a destination register until after it has been sourced by an
3063 * instruction with a different destination register.
3066 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3068 int write_len
= inst
->regs_written
;
3069 int first_write_grf
= inst
->dst
.nr
;
3070 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3071 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3073 memset(needs_dep
, false, sizeof(needs_dep
));
3074 memset(needs_dep
, true, write_len
);
3075 /* Walk forwards looking for writes to registers we're writing which aren't
3076 * read before being written.
3078 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3079 /* If we hit control flow, force resolve all remaining dependencies. */
3080 if (block
->end() == scan_inst
) {
3081 for (int i
= 0; i
< write_len
; i
++) {
3083 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3084 first_write_grf
+ i
);
3089 /* Clear the flag for registers that actually got read (as expected). */
3090 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3092 /* We insert our reads as late as possible since they're reading the
3093 * result of a SEND, which has massive latency.
3095 if (scan_inst
->dst
.file
== VGRF
&&
3096 scan_inst
->dst
.nr
>= first_write_grf
&&
3097 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3098 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3099 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3101 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3104 /* Continue the loop only if we haven't resolved all the dependencies */
3106 for (i
= 0; i
< write_len
; i
++) {
3116 fs_visitor::insert_gen4_send_dependency_workarounds()
3118 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3121 bool progress
= false;
3123 /* Note that we're done with register allocation, so GRF fs_regs always
3124 * have a .reg_offset of 0.
3127 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3128 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3129 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3130 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3136 invalidate_live_intervals();
3140 * Turns the generic expression-style uniform pull constant load instruction
3141 * into a hardware-specific series of instructions for loading a pull
3144 * The expression style allows the CSE pass before this to optimize out
3145 * repeated loads from the same offset, and gives the pre-register-allocation
3146 * scheduling full flexibility, while the conversion to native instructions
3147 * allows the post-register-allocation scheduler the best information
3150 * Note that execution masking for setting up pull constant loads is special:
3151 * the channels that need to be written are unrelated to the current execution
3152 * mask, since a later instruction will use one of the result channels as a
3153 * source operand for all 8 or 16 of its channels.
3156 fs_visitor::lower_uniform_pull_constant_loads()
3158 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3159 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3162 if (devinfo
->gen
>= 7) {
3163 /* The offset arg is a vec4-aligned immediate byte offset. */
3164 fs_reg const_offset_reg
= inst
->src
[1];
3165 assert(const_offset_reg
.file
== IMM
&&
3166 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3167 assert(const_offset_reg
.ud
% 16 == 0);
3169 fs_reg payload
, offset
;
3170 if (devinfo
->gen
>= 9) {
3171 /* We have to use a message header on Skylake to get SIMD4x2
3172 * mode. Reserve space for the register.
3174 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3175 offset
.reg_offset
++;
3178 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3182 /* This is actually going to be a MOV, but since only the first dword
3183 * is accessed, we have a special opcode to do just that one. Note
3184 * that this needs to be an operation that will be considered a def
3185 * by live variable analysis, or register allocation will explode.
3187 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3188 8, offset
, const_offset_reg
);
3189 setup
->force_writemask_all
= true;
3191 setup
->ir
= inst
->ir
;
3192 setup
->annotation
= inst
->annotation
;
3193 inst
->insert_before(block
, setup
);
3195 /* Similarly, this will only populate the first 4 channels of the
3196 * result register (since we only use smear values from 0-3), but we
3197 * don't tell the optimizer.
3199 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3200 inst
->src
[1] = payload
;
3201 inst
->base_mrf
= -1;
3203 invalidate_live_intervals();
3205 /* Before register allocation, we didn't tell the scheduler about the
3206 * MRF we use. We know it's safe to use this MRF because nothing
3207 * else does except for register spill/unspill, which generates and
3208 * uses its MRF within a single IR instruction.
3210 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3217 fs_visitor::lower_load_payload()
3219 bool progress
= false;
3221 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3222 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3225 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3226 assert(inst
->saturate
== false);
3227 fs_reg dst
= inst
->dst
;
3229 /* Get rid of COMPR4. We'll add it back in if we need it */
3230 if (dst
.file
== MRF
)
3231 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3233 const fs_builder
ibld(this, block
, inst
);
3234 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3236 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3237 if (inst
->src
[i
].file
!= BAD_FILE
) {
3238 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3239 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3240 hbld
.MOV(mov_dst
, mov_src
);
3242 dst
= offset(dst
, hbld
, 1);
3245 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3246 inst
->exec_size
> 8) {
3247 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3248 * a straightforward copy. Instead, the result of the
3249 * LOAD_PAYLOAD is treated as interleaved and the first four
3250 * non-header sources are unpacked as:
3261 * This is used for gen <= 5 fb writes.
3263 assert(inst
->exec_size
== 16);
3264 assert(inst
->header_size
+ 4 <= inst
->sources
);
3265 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3266 if (inst
->src
[i
].file
!= BAD_FILE
) {
3267 if (devinfo
->has_compr4
) {
3268 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3269 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3270 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3272 /* Platform doesn't have COMPR4. We have to fake it */
3273 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3274 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3276 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3283 /* The loop above only ever incremented us through the first set
3284 * of 4 registers. However, thanks to the magic of COMPR4, we
3285 * actually wrote to the first 8 registers, so we need to take
3286 * that into account now.
3290 /* The COMPR4 code took care of the first 4 sources. We'll let
3291 * the regular path handle any remaining sources. Yes, we are
3292 * modifying the instruction but we're about to delete it so
3293 * this really doesn't hurt anything.
3295 inst
->header_size
+= 4;
3298 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3299 if (inst
->src
[i
].file
!= BAD_FILE
)
3300 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3301 dst
= offset(dst
, ibld
, 1);
3304 inst
->remove(block
);
3309 invalidate_live_intervals();
3315 fs_visitor::lower_integer_multiplication()
3317 bool progress
= false;
3319 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3320 const fs_builder
ibld(this, block
, inst
);
3322 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3323 if (inst
->dst
.is_accumulator() ||
3324 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3325 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3328 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3329 * operation directly, but CHV/BXT cannot.
3331 if (devinfo
->gen
>= 8 &&
3332 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3335 if (inst
->src
[1].file
== IMM
&&
3336 inst
->src
[1].ud
< (1 << 16)) {
3337 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3338 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3341 * If multiplying by an immediate value that fits in 16-bits, do a
3342 * single MUL instruction with that value in the proper location.
3344 if (devinfo
->gen
< 7) {
3345 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3347 ibld
.MOV(imm
, inst
->src
[1]);
3348 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3350 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3353 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3354 * do 32-bit integer multiplication in one instruction, but instead
3355 * must do a sequence (which actually calculates a 64-bit result):
3357 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3358 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3359 * mov(8) g2<1>D acc0<8,8,1>D
3361 * But on Gen > 6, the ability to use second accumulator register
3362 * (acc1) for non-float data types was removed, preventing a simple
3363 * implementation in SIMD16. A 16-channel result can be calculated by
3364 * executing the three instructions twice in SIMD8, once with quarter
3365 * control of 1Q for the first eight channels and again with 2Q for
3366 * the second eight channels.
3368 * Which accumulator register is implicitly accessed (by AccWrEnable
3369 * for instance) is determined by the quarter control. Unfortunately
3370 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3371 * implicit accumulator access by an instruction with 2Q will access
3372 * acc1 regardless of whether the data type is usable in acc1.
3374 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3375 * integer data types.
3377 * Since we only want the low 32-bits of the result, we can do two
3378 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3379 * adjust the high result and add them (like the mach is doing):
3381 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3382 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3383 * shl(8) g9<1>D g8<8,8,1>D 16D
3384 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3386 * We avoid the shl instruction by realizing that we only want to add
3387 * the low 16-bits of the "high" result to the high 16-bits of the
3388 * "low" result and using proper regioning on the add:
3390 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3391 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3392 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3394 * Since it does not use the (single) accumulator register, we can
3395 * schedule multi-component multiplications much better.
3398 fs_reg orig_dst
= inst
->dst
;
3399 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3400 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3403 fs_reg low
= inst
->dst
;
3404 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3407 if (devinfo
->gen
>= 7) {
3408 fs_reg src1_0_w
= inst
->src
[1];
3409 fs_reg src1_1_w
= inst
->src
[1];
3411 if (inst
->src
[1].file
== IMM
) {
3412 src1_0_w
.ud
&= 0xffff;
3415 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3416 if (src1_0_w
.stride
!= 0) {
3417 assert(src1_0_w
.stride
== 1);
3418 src1_0_w
.stride
= 2;
3421 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3422 if (src1_1_w
.stride
!= 0) {
3423 assert(src1_1_w
.stride
== 1);
3424 src1_1_w
.stride
= 2;
3426 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3428 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3429 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3431 fs_reg src0_0_w
= inst
->src
[0];
3432 fs_reg src0_1_w
= inst
->src
[0];
3434 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3435 if (src0_0_w
.stride
!= 0) {
3436 assert(src0_0_w
.stride
== 1);
3437 src0_0_w
.stride
= 2;
3440 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3441 if (src0_1_w
.stride
!= 0) {
3442 assert(src0_1_w
.stride
== 1);
3443 src0_1_w
.stride
= 2;
3445 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3447 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3448 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3451 fs_reg dst
= inst
->dst
;
3452 dst
.type
= BRW_REGISTER_TYPE_UW
;
3453 dst
.subreg_offset
= 2;
3456 high
.type
= BRW_REGISTER_TYPE_UW
;
3459 low
.type
= BRW_REGISTER_TYPE_UW
;
3460 low
.subreg_offset
= 2;
3463 ibld
.ADD(dst
, low
, high
);
3465 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3466 set_condmod(inst
->conditional_mod
,
3467 ibld
.MOV(orig_dst
, inst
->dst
));
3471 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3472 /* Should have been lowered to 8-wide. */
3473 assert(inst
->exec_size
<= 8);
3474 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3476 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3477 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3479 if (devinfo
->gen
>= 8) {
3480 /* Until Gen8, integer multiplies read 32-bits from one source,
3481 * and 16-bits from the other, and relying on the MACH instruction
3482 * to generate the high bits of the result.
3484 * On Gen8, the multiply instruction does a full 32x32-bit
3485 * multiply, but in order to do a 64-bit multiply we can simulate
3486 * the previous behavior and then use a MACH instruction.
3488 * FINISHME: Don't use source modifiers on src1.
3490 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3491 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3492 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3493 mul
->src
[1].stride
*= 2;
3495 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3496 inst
->force_sechalf
) {
3497 /* Among other things the quarter control bits influence which
3498 * accumulator register is used by the hardware for instructions
3499 * that access the accumulator implicitly (e.g. MACH). A
3500 * second-half instruction would normally map to acc1, which
3501 * doesn't exist on Gen7 and up (the hardware does emulate it for
3502 * floating-point instructions *only* by taking advantage of the
3503 * extra precision of acc0 not normally used for floating point
3506 * HSW and up are careful enough not to try to access an
3507 * accumulator register that doesn't exist, but on earlier Gen7
3508 * hardware we need to make sure that the quarter control bits are
3509 * zero to avoid non-deterministic behaviour and emit an extra MOV
3510 * to get the result masked correctly according to the current
3513 mach
->force_sechalf
= false;
3514 mach
->force_writemask_all
= true;
3515 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3516 ibld
.MOV(inst
->dst
, mach
->dst
);
3522 inst
->remove(block
);
3527 invalidate_live_intervals();
3533 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3534 fs_reg
*dst
, fs_reg color
, unsigned components
)
3536 if (key
->clamp_fragment_color
) {
3537 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3538 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3540 for (unsigned i
= 0; i
< components
; i
++)
3542 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3547 for (unsigned i
= 0; i
< components
; i
++)
3548 dst
[i
] = offset(color
, bld
, i
);
3552 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3553 const brw_wm_prog_data
*prog_data
,
3554 const brw_wm_prog_key
*key
,
3555 const fs_visitor::thread_payload
&payload
)
3557 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3558 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3559 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3560 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3561 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3562 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3563 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3564 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3565 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3566 const unsigned components
=
3567 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3569 /* We can potentially have a message length of up to 15, so we have to set
3570 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3573 int header_size
= 2, payload_header_size
;
3574 unsigned length
= 0;
3576 /* From the Sandy Bridge PRM, volume 4, page 198:
3578 * "Dispatched Pixel Enables. One bit per pixel indicating
3579 * which pixels were originally enabled when the thread was
3580 * dispatched. This field is only required for the end-of-
3581 * thread message and on all dual-source messages."
3583 if (devinfo
->gen
>= 6 &&
3584 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3585 color1
.file
== BAD_FILE
&&
3586 key
->nr_color_regions
== 1) {
3590 if (header_size
!= 0) {
3591 assert(header_size
== 2);
3592 /* Allocate 2 registers for a header */
3596 if (payload
.aa_dest_stencil_reg
) {
3597 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3598 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3599 .MOV(sources
[length
],
3600 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3604 if (prog_data
->uses_omask
) {
3605 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3606 BRW_REGISTER_TYPE_UD
);
3608 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3609 * relevant. Since it's unsigned single words one vgrf is always
3610 * 16-wide, but only the lower or higher 8 channels will be used by the
3611 * hardware when doing a SIMD8 write depending on whether we have
3612 * selected the subspans for the first or second half respectively.
3614 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3615 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3616 sample_mask
.stride
*= 2;
3618 bld
.exec_all().annotate("FB write oMask")
3619 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3620 inst
->force_sechalf
),
3625 payload_header_size
= length
;
3627 if (src0_alpha
.file
!= BAD_FILE
) {
3628 /* FIXME: This is being passed at the wrong location in the payload and
3629 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3630 * It's supposed to be immediately before oMask but there seems to be no
3631 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3632 * requires header sources to form a contiguous segment at the beginning
3633 * of the message and src0_alpha has per-channel semantics.
3635 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3639 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3642 if (color1
.file
!= BAD_FILE
) {
3643 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3647 if (src_depth
.file
!= BAD_FILE
) {
3648 sources
[length
] = src_depth
;
3652 if (dst_depth
.file
!= BAD_FILE
) {
3653 sources
[length
] = dst_depth
;
3657 if (src_stencil
.file
!= BAD_FILE
) {
3658 assert(devinfo
->gen
>= 9);
3659 assert(bld
.dispatch_width() != 16);
3661 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3662 * available on gen9+. As such it's impossible to have both enabled at the
3663 * same time and therefore length cannot overrun the array.
3665 assert(length
< 15);
3667 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3668 bld
.exec_all().annotate("FB write OS")
3669 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3670 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3675 if (devinfo
->gen
>= 7) {
3676 /* Send from the GRF */
3677 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3678 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3679 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3680 load
->dst
= payload
;
3682 inst
->src
[0] = payload
;
3683 inst
->resize_sources(1);
3684 inst
->base_mrf
= -1;
3686 /* Send from the MRF */
3687 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3688 sources
, length
, payload_header_size
);
3690 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3691 * will do this for us if we just give it a COMPR4 destination.
3693 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3694 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3696 inst
->resize_sources(0);
3700 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3701 inst
->mlen
= load
->regs_written
;
3702 inst
->header_size
= header_size
;
3706 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3707 const fs_reg
&coordinate
,
3708 const fs_reg
&shadow_c
,
3709 const fs_reg
&lod
, const fs_reg
&lod2
,
3710 const fs_reg
&surface
,
3711 const fs_reg
&sampler
,
3712 unsigned coord_components
,
3713 unsigned grad_components
)
3715 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3716 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3717 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3718 fs_reg msg_end
= msg_begin
;
3721 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3723 for (unsigned i
= 0; i
< coord_components
; i
++)
3724 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3725 offset(coordinate
, bld
, i
));
3727 msg_end
= offset(msg_end
, bld
, coord_components
);
3729 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3730 * require all three components to be present and zero if they are unused.
3732 if (coord_components
> 0 &&
3733 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3734 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3735 for (unsigned i
= coord_components
; i
< 3; i
++)
3736 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3738 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3741 if (op
== SHADER_OPCODE_TXD
) {
3742 /* TXD unsupported in SIMD16 mode. */
3743 assert(bld
.dispatch_width() == 8);
3745 /* the slots for u and v are always present, but r is optional */
3746 if (coord_components
< 2)
3747 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3750 * dPdx = dudx, dvdx, drdx
3751 * dPdy = dudy, dvdy, drdy
3753 * 1-arg: Does not exist.
3755 * 2-arg: dudx dvdx dudy dvdy
3756 * dPdx.x dPdx.y dPdy.x dPdy.y
3759 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3760 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3761 * m5 m6 m7 m8 m9 m10
3763 for (unsigned i
= 0; i
< grad_components
; i
++)
3764 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3766 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3768 for (unsigned i
= 0; i
< grad_components
; i
++)
3769 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3771 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3775 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3776 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3778 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3779 bld
.dispatch_width() == 16);
3781 const brw_reg_type type
=
3782 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3783 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3784 bld
.MOV(retype(msg_end
, type
), lod
);
3785 msg_end
= offset(msg_end
, bld
, 1);
3788 if (shadow_c
.file
!= BAD_FILE
) {
3789 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3790 /* There's no plain shadow compare message, so we use shadow
3791 * compare with a bias of 0.0.
3793 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3794 msg_end
= offset(msg_end
, bld
, 1);
3797 bld
.MOV(msg_end
, shadow_c
);
3798 msg_end
= offset(msg_end
, bld
, 1);
3802 inst
->src
[0] = reg_undef
;
3803 inst
->src
[1] = surface
;
3804 inst
->src
[2] = sampler
;
3805 inst
->resize_sources(3);
3806 inst
->base_mrf
= msg_begin
.nr
;
3807 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3808 inst
->header_size
= 1;
3812 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3814 const fs_reg
&shadow_c
,
3815 fs_reg lod
, fs_reg lod2
,
3816 const fs_reg
&sample_index
,
3817 const fs_reg
&surface
,
3818 const fs_reg
&sampler
,
3819 const fs_reg
&offset_value
,
3820 unsigned coord_components
,
3821 unsigned grad_components
)
3823 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3824 fs_reg msg_coords
= message
;
3825 unsigned header_size
= 0;
3827 if (offset_value
.file
!= BAD_FILE
) {
3828 /* The offsets set up by the visitor are in the m1 header, so we can't
3835 for (unsigned i
= 0; i
< coord_components
; i
++) {
3836 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3837 coordinate
= offset(coordinate
, bld
, 1);
3839 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3840 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3842 if (shadow_c
.file
!= BAD_FILE
) {
3843 fs_reg msg_shadow
= msg_lod
;
3844 bld
.MOV(msg_shadow
, shadow_c
);
3845 msg_lod
= offset(msg_shadow
, bld
, 1);
3850 case SHADER_OPCODE_TXL
:
3852 bld
.MOV(msg_lod
, lod
);
3853 msg_end
= offset(msg_lod
, bld
, 1);
3855 case SHADER_OPCODE_TXD
:
3858 * dPdx = dudx, dvdx, drdx
3859 * dPdy = dudy, dvdy, drdy
3861 * Load up these values:
3862 * - dudx dudy dvdx dvdy drdx drdy
3863 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3866 for (unsigned i
= 0; i
< grad_components
; i
++) {
3867 bld
.MOV(msg_end
, lod
);
3868 lod
= offset(lod
, bld
, 1);
3869 msg_end
= offset(msg_end
, bld
, 1);
3871 bld
.MOV(msg_end
, lod2
);
3872 lod2
= offset(lod2
, bld
, 1);
3873 msg_end
= offset(msg_end
, bld
, 1);
3876 case SHADER_OPCODE_TXS
:
3877 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3878 bld
.MOV(msg_lod
, lod
);
3879 msg_end
= offset(msg_lod
, bld
, 1);
3881 case SHADER_OPCODE_TXF
:
3882 msg_lod
= offset(msg_coords
, bld
, 3);
3883 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3884 msg_end
= offset(msg_lod
, bld
, 1);
3886 case SHADER_OPCODE_TXF_CMS
:
3887 msg_lod
= offset(msg_coords
, bld
, 3);
3889 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3891 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3892 msg_end
= offset(msg_lod
, bld
, 2);
3899 inst
->src
[0] = reg_undef
;
3900 inst
->src
[1] = surface
;
3901 inst
->src
[2] = sampler
;
3902 inst
->resize_sources(3);
3903 inst
->base_mrf
= message
.nr
;
3904 inst
->mlen
= msg_end
.nr
- message
.nr
;
3905 inst
->header_size
= header_size
;
3907 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3908 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3912 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3914 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3917 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
3921 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3923 const fs_reg
&shadow_c
,
3924 fs_reg lod
, fs_reg lod2
,
3925 const fs_reg
&sample_index
,
3927 const fs_reg
&surface
,
3928 const fs_reg
&sampler
,
3929 fs_reg offset_value
,
3930 unsigned coord_components
,
3931 unsigned grad_components
)
3933 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3934 int reg_width
= bld
.dispatch_width() / 8;
3935 unsigned header_size
= 0, length
= 0;
3936 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3937 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3938 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3940 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3941 offset_value
.file
!= BAD_FILE
||
3942 is_high_sampler(devinfo
, sampler
)) {
3943 /* For general texture offsets (no txf workaround), we need a header to
3944 * put them in. Note that we're only reserving space for it in the
3945 * message payload as it will be initialized implicitly by the
3948 * TG4 needs to place its channel select in the header, for interaction
3949 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3950 * larger sampler numbers we need to offset the Sampler State Pointer in
3954 sources
[0] = fs_reg();
3958 if (shadow_c
.file
!= BAD_FILE
) {
3959 bld
.MOV(sources
[length
], shadow_c
);
3963 bool coordinate_done
= false;
3965 /* The sampler can only meaningfully compute LOD for fragment shader
3966 * messages. For all other stages, we change the opcode to TXL and
3967 * hardcode the LOD to 0.
3969 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3970 op
== SHADER_OPCODE_TEX
) {
3971 op
= SHADER_OPCODE_TXL
;
3972 lod
= brw_imm_f(0.0f
);
3975 /* Set up the LOD info */
3978 case SHADER_OPCODE_TXL
:
3979 bld
.MOV(sources
[length
], lod
);
3982 case SHADER_OPCODE_TXD
:
3983 /* TXD should have been lowered in SIMD16 mode. */
3984 assert(bld
.dispatch_width() == 8);
3986 /* Load dPdx and the coordinate together:
3987 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3989 for (unsigned i
= 0; i
< coord_components
; i
++) {
3990 bld
.MOV(sources
[length
], coordinate
);
3991 coordinate
= offset(coordinate
, bld
, 1);
3994 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3995 * only derivatives for (u, v, r).
3997 if (i
< grad_components
) {
3998 bld
.MOV(sources
[length
], lod
);
3999 lod
= offset(lod
, bld
, 1);
4002 bld
.MOV(sources
[length
], lod2
);
4003 lod2
= offset(lod2
, bld
, 1);
4008 coordinate_done
= true;
4010 case SHADER_OPCODE_TXS
:
4011 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4014 case SHADER_OPCODE_TXF
:
4015 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4016 * On Gen9 they are u, v, lod, r
4018 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4019 coordinate
= offset(coordinate
, bld
, 1);
4022 if (devinfo
->gen
>= 9) {
4023 if (coord_components
>= 2) {
4024 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4025 coordinate
= offset(coordinate
, bld
, 1);
4030 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4033 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
4034 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4035 coordinate
= offset(coordinate
, bld
, 1);
4039 coordinate_done
= true;
4041 case SHADER_OPCODE_TXF_CMS
:
4042 case SHADER_OPCODE_TXF_CMS_W
:
4043 case SHADER_OPCODE_TXF_UMS
:
4044 case SHADER_OPCODE_TXF_MCS
:
4045 if (op
== SHADER_OPCODE_TXF_UMS
||
4046 op
== SHADER_OPCODE_TXF_CMS
||
4047 op
== SHADER_OPCODE_TXF_CMS_W
) {
4048 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4052 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4053 /* Data from the multisample control surface. */
4054 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4057 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4060 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4061 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4064 offset(mcs
, bld
, 1));
4069 /* There is no offsetting for this message; just copy in the integer
4070 * texture coordinates.
4072 for (unsigned i
= 0; i
< coord_components
; i
++) {
4073 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4074 coordinate
= offset(coordinate
, bld
, 1);
4078 coordinate_done
= true;
4080 case SHADER_OPCODE_TG4_OFFSET
:
4081 /* gather4_po_c should have been lowered in SIMD16 mode. */
4082 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
4084 /* More crazy intermixing */
4085 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
4086 bld
.MOV(sources
[length
], coordinate
);
4087 coordinate
= offset(coordinate
, bld
, 1);
4091 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
4092 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
4093 offset_value
= offset(offset_value
, bld
, 1);
4097 if (coord_components
== 3) { /* r if present */
4098 bld
.MOV(sources
[length
], coordinate
);
4099 coordinate
= offset(coordinate
, bld
, 1);
4103 coordinate_done
= true;
4109 /* Set up the coordinate (except for cases where it was done above) */
4110 if (!coordinate_done
) {
4111 for (unsigned i
= 0; i
< coord_components
; i
++) {
4112 bld
.MOV(sources
[length
], coordinate
);
4113 coordinate
= offset(coordinate
, bld
, 1);
4120 mlen
= length
* reg_width
- header_size
;
4122 mlen
= length
* reg_width
;
4124 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4125 BRW_REGISTER_TYPE_F
);
4126 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4128 /* Generate the SEND. */
4130 inst
->src
[0] = src_payload
;
4131 inst
->src
[1] = surface
;
4132 inst
->src
[2] = sampler
;
4133 inst
->resize_sources(3);
4134 inst
->base_mrf
= -1;
4136 inst
->header_size
= header_size
;
4138 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4139 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4143 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4145 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4146 const fs_reg
&coordinate
= inst
->src
[0];
4147 const fs_reg
&shadow_c
= inst
->src
[1];
4148 const fs_reg
&lod
= inst
->src
[2];
4149 const fs_reg
&lod2
= inst
->src
[3];
4150 const fs_reg
&sample_index
= inst
->src
[4];
4151 const fs_reg
&mcs
= inst
->src
[5];
4152 const fs_reg
&surface
= inst
->src
[6];
4153 const fs_reg
&sampler
= inst
->src
[7];
4154 const fs_reg
&offset_value
= inst
->src
[8];
4155 assert(inst
->src
[9].file
== IMM
&& inst
->src
[10].file
== IMM
);
4156 const unsigned coord_components
= inst
->src
[9].ud
;
4157 const unsigned grad_components
= inst
->src
[10].ud
;
4159 if (devinfo
->gen
>= 7) {
4160 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4161 shadow_c
, lod
, lod2
, sample_index
,
4162 mcs
, surface
, sampler
, offset_value
,
4163 coord_components
, grad_components
);
4164 } else if (devinfo
->gen
>= 5) {
4165 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4166 shadow_c
, lod
, lod2
, sample_index
,
4167 surface
, sampler
, offset_value
,
4168 coord_components
, grad_components
);
4170 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4171 shadow_c
, lod
, lod2
,
4173 coord_components
, grad_components
);
4178 * Initialize the header present in some typed and untyped surface
4182 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4184 fs_builder ubld
= bld
.exec_all().group(8, 0);
4185 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4186 ubld
.MOV(dst
, brw_imm_d(0));
4187 ubld
.MOV(component(dst
, 7), sample_mask
);
4192 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4193 const fs_reg
&sample_mask
)
4195 /* Get the logical send arguments. */
4196 const fs_reg
&addr
= inst
->src
[0];
4197 const fs_reg
&src
= inst
->src
[1];
4198 const fs_reg
&surface
= inst
->src
[2];
4199 const UNUSED fs_reg
&dims
= inst
->src
[3];
4200 const fs_reg
&arg
= inst
->src
[4];
4202 /* Calculate the total number of components of the payload. */
4203 const unsigned addr_sz
= inst
->components_read(0);
4204 const unsigned src_sz
= inst
->components_read(1);
4205 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4206 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4208 /* Allocate space for the payload. */
4209 fs_reg
*const components
= new fs_reg
[sz
];
4210 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4213 /* Construct the payload. */
4215 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4217 for (unsigned i
= 0; i
< addr_sz
; i
++)
4218 components
[n
++] = offset(addr
, bld
, i
);
4220 for (unsigned i
= 0; i
< src_sz
; i
++)
4221 components
[n
++] = offset(src
, bld
, i
);
4223 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4225 /* Update the original instruction. */
4227 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4228 inst
->header_size
= header_sz
;
4230 inst
->src
[0] = payload
;
4231 inst
->src
[1] = surface
;
4233 inst
->resize_sources(3);
4235 delete[] components
;
4239 fs_visitor::lower_logical_sends()
4241 bool progress
= false;
4243 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4244 const fs_builder
ibld(this, block
, inst
);
4246 switch (inst
->opcode
) {
4247 case FS_OPCODE_FB_WRITE_LOGICAL
:
4248 assert(stage
== MESA_SHADER_FRAGMENT
);
4249 lower_fb_write_logical_send(ibld
, inst
,
4250 (const brw_wm_prog_data
*)prog_data
,
4251 (const brw_wm_prog_key
*)key
,
4255 case SHADER_OPCODE_TEX_LOGICAL
:
4256 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4259 case SHADER_OPCODE_TXD_LOGICAL
:
4260 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4263 case SHADER_OPCODE_TXF_LOGICAL
:
4264 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4267 case SHADER_OPCODE_TXL_LOGICAL
:
4268 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4271 case SHADER_OPCODE_TXS_LOGICAL
:
4272 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4275 case FS_OPCODE_TXB_LOGICAL
:
4276 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4279 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4280 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4283 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4284 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4287 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4288 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4291 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4292 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4295 case SHADER_OPCODE_LOD_LOGICAL
:
4296 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4299 case SHADER_OPCODE_TG4_LOGICAL
:
4300 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4303 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4304 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4307 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4308 lower_surface_logical_send(ibld
, inst
,
4309 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4313 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4314 lower_surface_logical_send(ibld
, inst
,
4315 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4316 ibld
.sample_mask_reg());
4319 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4320 lower_surface_logical_send(ibld
, inst
,
4321 SHADER_OPCODE_UNTYPED_ATOMIC
,
4322 ibld
.sample_mask_reg());
4325 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4326 lower_surface_logical_send(ibld
, inst
,
4327 SHADER_OPCODE_TYPED_SURFACE_READ
,
4331 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4332 lower_surface_logical_send(ibld
, inst
,
4333 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4334 ibld
.sample_mask_reg());
4337 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4338 lower_surface_logical_send(ibld
, inst
,
4339 SHADER_OPCODE_TYPED_ATOMIC
,
4340 ibld
.sample_mask_reg());
4351 invalidate_live_intervals();
4357 * Get the closest native SIMD width supported by the hardware for instruction
4358 * \p inst. The instruction will be left untouched by
4359 * fs_visitor::lower_simd_width() if the returned value is equal to the
4360 * original execution size.
4363 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4364 const fs_inst
*inst
)
4366 switch (inst
->opcode
) {
4367 case BRW_OPCODE_MOV
:
4368 case BRW_OPCODE_SEL
:
4369 case BRW_OPCODE_NOT
:
4370 case BRW_OPCODE_AND
:
4372 case BRW_OPCODE_XOR
:
4373 case BRW_OPCODE_SHR
:
4374 case BRW_OPCODE_SHL
:
4375 case BRW_OPCODE_ASR
:
4376 case BRW_OPCODE_CMP
:
4377 case BRW_OPCODE_CMPN
:
4378 case BRW_OPCODE_CSEL
:
4379 case BRW_OPCODE_F32TO16
:
4380 case BRW_OPCODE_F16TO32
:
4381 case BRW_OPCODE_BFREV
:
4382 case BRW_OPCODE_BFE
:
4383 case BRW_OPCODE_BFI1
:
4384 case BRW_OPCODE_BFI2
:
4385 case BRW_OPCODE_ADD
:
4386 case BRW_OPCODE_MUL
:
4387 case BRW_OPCODE_AVG
:
4388 case BRW_OPCODE_FRC
:
4389 case BRW_OPCODE_RNDU
:
4390 case BRW_OPCODE_RNDD
:
4391 case BRW_OPCODE_RNDE
:
4392 case BRW_OPCODE_RNDZ
:
4393 case BRW_OPCODE_LZD
:
4394 case BRW_OPCODE_FBH
:
4395 case BRW_OPCODE_FBL
:
4396 case BRW_OPCODE_CBIT
:
4397 case BRW_OPCODE_SAD2
:
4398 case BRW_OPCODE_MAD
:
4399 case BRW_OPCODE_LRP
:
4400 case SHADER_OPCODE_RCP
:
4401 case SHADER_OPCODE_RSQ
:
4402 case SHADER_OPCODE_SQRT
:
4403 case SHADER_OPCODE_EXP2
:
4404 case SHADER_OPCODE_LOG2
:
4405 case SHADER_OPCODE_POW
:
4406 case SHADER_OPCODE_INT_QUOTIENT
:
4407 case SHADER_OPCODE_INT_REMAINDER
:
4408 case SHADER_OPCODE_SIN
:
4409 case SHADER_OPCODE_COS
: {
4410 /* According to the PRMs:
4411 * "A. In Direct Addressing mode, a source cannot span more than 2
4412 * adjacent GRF registers.
4413 * B. A destination cannot span more than 2 adjacent GRF registers."
4415 * Look for the source or destination with the largest register region
4416 * which is the one that is going to limit the overal execution size of
4417 * the instruction due to this rule.
4419 unsigned reg_count
= inst
->regs_written
;
4421 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4422 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4424 /* Calculate the maximum execution size of the instruction based on the
4425 * factor by which it goes over the hardware limit of 2 GRFs.
4427 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4429 case SHADER_OPCODE_MULH
:
4430 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4431 * is 8-wide on Gen7+.
4433 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4435 case FS_OPCODE_FB_WRITE_LOGICAL
:
4436 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4439 assert(devinfo
->gen
!= 6 ||
4440 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4441 inst
->exec_size
== 8);
4442 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4443 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4444 8 : inst
->exec_size
);
4446 case SHADER_OPCODE_TXD_LOGICAL
:
4447 /* TXD is unsupported in SIMD16 mode. */
4450 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4451 /* gather4_po_c is unsupported in SIMD16 mode. */
4452 const fs_reg
&shadow_c
= inst
->src
[1];
4453 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4455 case SHADER_OPCODE_TXL_LOGICAL
:
4456 case FS_OPCODE_TXB_LOGICAL
: {
4457 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4458 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4459 * mode because the message exceeds the maximum length of 11.
4461 const fs_reg
&shadow_c
= inst
->src
[1];
4462 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4464 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4467 return inst
->exec_size
;
4469 case SHADER_OPCODE_TXF_LOGICAL
:
4470 case SHADER_OPCODE_TXS_LOGICAL
:
4471 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4472 * messages. Use SIMD16 instead.
4474 if (devinfo
->gen
== 4)
4477 return inst
->exec_size
;
4479 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4480 /* This opcode can take up to 6 arguments which means that in some
4481 * circumstances it can end up with a message that is too long in SIMD16
4484 const unsigned coord_components
= inst
->src
[8].ud
;
4485 /* First three arguments are the sample index and the two arguments for
4488 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4491 return inst
->exec_size
;
4494 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4495 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4496 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4499 case SHADER_OPCODE_MOV_INDIRECT
:
4500 /* Prior to Broadwell, we only have 8 address subregisters */
4501 return devinfo
->gen
< 8 ? 8 : inst
->exec_size
;
4504 return inst
->exec_size
;
4509 * The \p rows array of registers represents a \p num_rows by \p num_columns
4510 * matrix in row-major order, write it in column-major order into the register
4511 * passed as destination. \p stride gives the separation between matrix
4512 * elements in the input in fs_builder::dispatch_width() units.
4515 emit_transpose(const fs_builder
&bld
,
4516 const fs_reg
&dst
, const fs_reg
*rows
,
4517 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4519 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4521 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4522 for (unsigned j
= 0; j
< num_rows
; ++j
)
4523 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4526 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4528 delete[] components
;
4532 fs_visitor::lower_simd_width()
4534 bool progress
= false;
4536 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4537 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4539 if (lower_width
!= inst
->exec_size
) {
4540 /* Builder matching the original instruction. We may also need to
4541 * emit an instruction of width larger than the original, set the
4542 * execution size of the builder to the highest of both for now so
4543 * we're sure that both cases can be handled.
4545 const fs_builder ibld
= bld
.at(block
, inst
)
4546 .exec_all(inst
->force_writemask_all
)
4547 .group(MAX2(inst
->exec_size
, lower_width
),
4548 inst
->force_sechalf
);
4550 /* Split the copies in chunks of the execution width of either the
4551 * original or the lowered instruction, whichever is lower.
4553 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4554 const unsigned n
= inst
->exec_size
/ copy_width
;
4555 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4556 inst
->dst
.component_size(inst
->exec_size
);
4559 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4560 !inst
->writes_accumulator
&& !inst
->mlen
);
4562 for (unsigned i
= 0; i
< n
; i
++) {
4563 /* Emit a copy of the original instruction with the lowered width.
4564 * If the EOT flag was set throw it away except for the last
4565 * instruction to avoid killing the thread prematurely.
4567 fs_inst split_inst
= *inst
;
4568 split_inst
.exec_size
= lower_width
;
4569 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4571 /* Select the correct channel enables for the i-th group, then
4572 * transform the sources and destination and emit the lowered
4575 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4577 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4578 if (inst
->src
[j
].file
!= BAD_FILE
&&
4579 !is_uniform(inst
->src
[j
])) {
4580 /* Get the i-th copy_width-wide chunk of the source. */
4581 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4582 const unsigned src_size
= inst
->components_read(j
);
4584 /* Use a trivial transposition to copy one every n
4585 * copy_width-wide components of the register into a
4586 * temporary passed as source to the lowered instruction.
4588 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4589 emit_transpose(lbld
.group(copy_width
, 0),
4590 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4594 if (inst
->regs_written
) {
4595 /* Allocate enough space to hold the result of the lowered
4596 * instruction and fix up the number of registers written.
4598 split_inst
.dst
= dsts
[i
] =
4599 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4600 split_inst
.regs_written
=
4601 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4605 lbld
.emit(split_inst
);
4608 if (inst
->regs_written
) {
4609 /* Distance between useful channels in the temporaries, skipping
4610 * garbage if the lowered instruction is wider than the original.
4612 const unsigned m
= lower_width
/ copy_width
;
4614 /* Interleave the components of the result from the lowered
4615 * instructions. We need to set exec_all() when copying more than
4616 * one half per component, because LOAD_PAYLOAD (in terms of which
4617 * emit_transpose is implemented) can only use the same channel
4618 * enable signals for all of its non-header sources.
4620 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4621 .group(copy_width
, 0),
4622 inst
->dst
, dsts
, n
, dst_size
, m
);
4625 inst
->remove(block
);
4631 invalidate_live_intervals();
4637 fs_visitor::dump_instructions()
4639 dump_instructions(NULL
);
4643 fs_visitor::dump_instructions(const char *name
)
4645 FILE *file
= stderr
;
4646 if (name
&& geteuid() != 0) {
4647 file
= fopen(name
, "w");
4653 calculate_register_pressure();
4654 int ip
= 0, max_pressure
= 0;
4655 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4656 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4657 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4658 dump_instruction(inst
, file
);
4661 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4664 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4665 fprintf(file
, "%4d: ", ip
++);
4666 dump_instruction(inst
, file
);
4670 if (file
!= stderr
) {
4676 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4678 dump_instruction(be_inst
, stderr
);
4682 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4684 fs_inst
*inst
= (fs_inst
*)be_inst
;
4686 if (inst
->predicate
) {
4687 fprintf(file
, "(%cf0.%d) ",
4688 inst
->predicate_inverse
? '-' : '+',
4692 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4694 fprintf(file
, ".sat");
4695 if (inst
->conditional_mod
) {
4696 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4697 if (!inst
->predicate
&&
4698 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4699 inst
->opcode
!= BRW_OPCODE_IF
&&
4700 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4701 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4704 fprintf(file
, "(%d) ", inst
->exec_size
);
4707 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4710 switch (inst
->dst
.file
) {
4712 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
4713 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
4714 inst
->dst
.subreg_offset
)
4715 fprintf(file
, "+%d.%d",
4716 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4719 fprintf(file
, "g%d", inst
->dst
.nr
);
4722 fprintf(file
, "m%d", inst
->dst
.nr
);
4725 fprintf(file
, "(null)");
4728 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4731 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4734 switch (inst
->dst
.nr
) {
4736 fprintf(file
, "null");
4738 case BRW_ARF_ADDRESS
:
4739 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
4741 case BRW_ARF_ACCUMULATOR
:
4742 fprintf(file
, "acc%d", inst
->dst
.subnr
);
4745 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4748 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4751 if (inst
->dst
.subnr
)
4752 fprintf(file
, "+%d", inst
->dst
.subnr
);
4755 unreachable("not reached");
4757 if (inst
->dst
.stride
!= 1)
4758 fprintf(file
, "<%u>", inst
->dst
.stride
);
4759 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4761 for (int i
= 0; i
< inst
->sources
; i
++) {
4762 if (inst
->src
[i
].negate
)
4764 if (inst
->src
[i
].abs
)
4766 switch (inst
->src
[i
].file
) {
4768 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
4769 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
4770 inst
->src
[i
].subreg_offset
)
4771 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4772 inst
->src
[i
].subreg_offset
);
4775 fprintf(file
, "g%d", inst
->src
[i
].nr
);
4778 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
4781 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
4784 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
4785 if (inst
->src
[i
].subreg_offset
) {
4786 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4787 inst
->src
[i
].subreg_offset
);
4791 fprintf(file
, "(null)");
4794 switch (inst
->src
[i
].type
) {
4795 case BRW_REGISTER_TYPE_F
:
4796 fprintf(file
, "%ff", inst
->src
[i
].f
);
4798 case BRW_REGISTER_TYPE_W
:
4799 case BRW_REGISTER_TYPE_D
:
4800 fprintf(file
, "%dd", inst
->src
[i
].d
);
4802 case BRW_REGISTER_TYPE_UW
:
4803 case BRW_REGISTER_TYPE_UD
:
4804 fprintf(file
, "%uu", inst
->src
[i
].ud
);
4806 case BRW_REGISTER_TYPE_VF
:
4807 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4808 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
4809 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
4810 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
4811 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
4814 fprintf(file
, "???");
4819 switch (inst
->src
[i
].nr
) {
4821 fprintf(file
, "null");
4823 case BRW_ARF_ADDRESS
:
4824 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
4826 case BRW_ARF_ACCUMULATOR
:
4827 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
4830 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4833 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4836 if (inst
->src
[i
].subnr
)
4837 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
4840 if (inst
->src
[i
].abs
)
4843 if (inst
->src
[i
].file
!= IMM
) {
4845 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
4846 unsigned hstride
= inst
->src
[i
].hstride
;
4847 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
4849 stride
= inst
->src
[i
].stride
;
4852 fprintf(file
, "<%u>", stride
);
4854 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4857 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4858 fprintf(file
, ", ");
4863 if (inst
->force_writemask_all
)
4864 fprintf(file
, "NoMask ");
4866 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4867 if (inst
->force_sechalf
)
4868 fprintf(file
, "2ndhalf ");
4870 fprintf(file
, "1sthalf ");
4873 fprintf(file
, "\n");
4877 * Possibly returns an instruction that set up @param reg.
4879 * Sometimes we want to take the result of some expression/variable
4880 * dereference tree and rewrite the instruction generating the result
4881 * of the tree. When processing the tree, we know that the
4882 * instructions generated are all writing temporaries that are dead
4883 * outside of this tree. So, if we have some instructions that write
4884 * a temporary, we're free to point that temp write somewhere else.
4886 * Note that this doesn't guarantee that the instruction generated
4887 * only reg -- it might be the size=4 destination of a texture instruction.
4890 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4895 end
->is_partial_write() ||
4896 !reg
.equals(end
->dst
)) {
4904 fs_visitor::setup_payload_gen6()
4907 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4908 unsigned barycentric_interp_modes
=
4909 (stage
== MESA_SHADER_FRAGMENT
) ?
4910 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4912 assert(devinfo
->gen
>= 6);
4914 /* R0-1: masks, pixel X/Y coordinates. */
4915 payload
.num_regs
= 2;
4916 /* R2: only for 32-pixel dispatch.*/
4918 /* R3-26: barycentric interpolation coordinates. These appear in the
4919 * same order that they appear in the brw_wm_barycentric_interp_mode
4920 * enum. Each set of coordinates occupies 2 registers if dispatch width
4921 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4922 * appear if they were enabled using the "Barycentric Interpolation
4923 * Mode" bits in WM_STATE.
4925 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4926 if (barycentric_interp_modes
& (1 << i
)) {
4927 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4928 payload
.num_regs
+= 2;
4929 if (dispatch_width
== 16) {
4930 payload
.num_regs
+= 2;
4935 /* R27: interpolated depth if uses source depth */
4937 payload
.source_depth_reg
= payload
.num_regs
;
4939 if (dispatch_width
== 16) {
4940 /* R28: interpolated depth if not SIMD8. */
4944 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4946 payload
.source_w_reg
= payload
.num_regs
;
4948 if (dispatch_width
== 16) {
4949 /* R30: interpolated W if not SIMD8. */
4954 if (stage
== MESA_SHADER_FRAGMENT
) {
4955 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4956 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4957 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4958 /* R31: MSAA position offsets. */
4959 if (prog_data
->uses_pos_offset
) {
4960 payload
.sample_pos_reg
= payload
.num_regs
;
4965 /* R32: MSAA input coverage mask */
4966 if (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4967 assert(devinfo
->gen
>= 7);
4968 payload
.sample_mask_in_reg
= payload
.num_regs
;
4970 if (dispatch_width
== 16) {
4971 /* R33: input coverage mask if not SIMD8. */
4976 /* R34-: bary for 32-pixel. */
4977 /* R58-59: interp W for 32-pixel. */
4979 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4980 source_depth_to_render_target
= true;
4985 fs_visitor::setup_vs_payload()
4987 /* R0: thread header, R1: urb handles */
4988 payload
.num_regs
= 2;
4992 * We are building the local ID push constant data using the simplest possible
4993 * method. We simply push the local IDs directly as they should appear in the
4994 * registers for the uvec3 gl_LocalInvocationID variable.
4996 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4997 * registers worth of push constant space.
4999 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
5000 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
5003 * FINISHME: There are a few easy optimizations to consider.
5005 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
5006 * no need for using push constant space for that dimension.
5008 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
5009 * easily use 16-bit words rather than 32-bit dwords in the push constant
5012 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
5013 * conveying the data, and thereby reduce push constant usage.
5017 fs_visitor::setup_gs_payload()
5019 assert(stage
== MESA_SHADER_GEOMETRY
);
5021 struct brw_gs_prog_data
*gs_prog_data
=
5022 (struct brw_gs_prog_data
*) prog_data
;
5023 struct brw_vue_prog_data
*vue_prog_data
=
5024 (struct brw_vue_prog_data
*) prog_data
;
5026 /* R0: thread header, R1: output URB handles */
5027 payload
.num_regs
= 2;
5029 if (gs_prog_data
->include_primitive_id
) {
5030 /* R2: Primitive ID 0..7 */
5034 /* Use a maximum of 32 registers for push-model inputs. */
5035 const unsigned max_push_components
= 32;
5037 /* If pushing our inputs would take too many registers, reduce the URB read
5038 * length (which is in HWords, or 8 registers), and resort to pulling.
5040 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5041 * have to multiply by VerticesIn to obtain the total storage requirement.
5043 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5044 max_push_components
) {
5045 gs_prog_data
->base
.include_vue_handles
= true;
5047 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5048 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5050 vue_prog_data
->urb_read_length
=
5051 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5056 fs_visitor::setup_cs_payload()
5058 assert(devinfo
->gen
>= 7);
5059 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
5061 payload
.num_regs
= 1;
5063 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
5064 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
5065 payload
.local_invocation_id_reg
= payload
.num_regs
;
5066 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
5071 fs_visitor::calculate_register_pressure()
5073 invalidate_live_intervals();
5074 calculate_live_intervals();
5076 unsigned num_instructions
= 0;
5077 foreach_block(block
, cfg
)
5078 num_instructions
+= block
->instructions
.length();
5080 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5082 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5083 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5084 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5089 fs_visitor::optimize()
5091 /* Start by validating the shader we currently have. */
5094 /* bld is the common builder object pointing at the end of the program we
5095 * used to translate it into i965 IR. For the optimization and lowering
5096 * passes coming next, any code added after the end of the program without
5097 * having explicitly called fs_builder::at() clearly points at a mistake.
5098 * Ideally optimization passes wouldn't be part of the visitor so they
5099 * wouldn't have access to bld at all, but they do, so just in case some
5100 * pass forgets to ask for a location explicitly set it to NULL here to
5101 * make it trip. The dispatch width is initialized to a bogus value to
5102 * make sure that optimizations set the execution controls explicitly to
5103 * match the code they are manipulating instead of relying on the defaults.
5105 bld
= fs_builder(this, 64);
5107 assign_constant_locations();
5108 lower_constant_loads();
5112 split_virtual_grfs();
5115 #define OPT(pass, args...) ({ \
5117 bool this_progress = pass(args); \
5119 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5120 char filename[64]; \
5121 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5122 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5124 backend_shader::dump_instructions(filename); \
5129 progress = progress || this_progress; \
5133 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5135 snprintf(filename
, 64, "%s%d-%s-00-start",
5136 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5138 backend_shader::dump_instructions(filename
);
5141 bool progress
= false;
5145 OPT(lower_simd_width
);
5146 OPT(lower_logical_sends
);
5153 OPT(remove_duplicate_mrf_writes
);
5157 OPT(opt_copy_propagate
);
5158 OPT(opt_predicated_break
, this);
5159 OPT(opt_cmod_propagation
);
5160 OPT(dead_code_eliminate
);
5161 OPT(opt_peephole_sel
);
5162 OPT(dead_control_flow_eliminate
, this);
5163 OPT(opt_register_renaming
);
5164 OPT(opt_redundant_discard_jumps
);
5165 OPT(opt_saturate_propagation
);
5166 OPT(opt_zero_samples
);
5167 OPT(register_coalesce
);
5168 OPT(compute_to_mrf
);
5169 OPT(eliminate_find_live_channel
);
5171 OPT(compact_virtual_grfs
);
5176 OPT(opt_sampler_eot
);
5178 if (OPT(lower_load_payload
)) {
5179 split_virtual_grfs();
5180 OPT(register_coalesce
);
5181 OPT(compute_to_mrf
);
5182 OPT(dead_code_eliminate
);
5185 OPT(opt_combine_constants
);
5186 OPT(lower_integer_multiplication
);
5188 lower_uniform_pull_constant_loads();
5194 * Three source instruction must have a GRF/MRF destination register.
5195 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5198 fs_visitor::fixup_3src_null_dest()
5200 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5201 if (inst
->is_3src() && inst
->dst
.is_null()) {
5202 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5209 fs_visitor::allocate_registers()
5211 bool allocated_without_spills
;
5213 static const enum instruction_scheduler_mode pre_modes
[] = {
5215 SCHEDULE_PRE_NON_LIFO
,
5219 /* Try each scheduling heuristic to see if it can successfully register
5220 * allocate without spilling. They should be ordered by decreasing
5221 * performance but increasing likelihood of allocating.
5223 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5224 schedule_instructions(pre_modes
[i
]);
5227 assign_regs_trivial();
5228 allocated_without_spills
= true;
5230 allocated_without_spills
= assign_regs(false);
5232 if (allocated_without_spills
)
5236 if (!allocated_without_spills
) {
5237 /* We assume that any spilling is worse than just dropping back to
5238 * SIMD8. There's probably actually some intermediate point where
5239 * SIMD16 with a couple of spills is still better.
5241 if (dispatch_width
== 16) {
5242 fail("Failure to register allocate. Reduce number of "
5243 "live scalar values to avoid this.");
5245 compiler
->shader_perf_log(log_data
,
5246 "%s shader triggered register spilling. "
5247 "Try reducing the number of live scalar "
5248 "values to improve performance.\n",
5252 /* Since we're out of heuristics, just go spill registers until we
5253 * get an allocation.
5255 while (!assign_regs(true)) {
5261 /* This must come after all optimization and register allocation, since
5262 * it inserts dead code that happens to have side effects, and it does
5263 * so based on the actual physical registers in use.
5265 insert_gen4_send_dependency_workarounds();
5270 schedule_instructions(SCHEDULE_POST
);
5272 if (last_scratch
> 0)
5273 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5277 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5279 assert(stage
== MESA_SHADER_VERTEX
);
5283 if (shader_time_index
>= 0)
5284 emit_shader_time_begin();
5291 compute_clip_distance(clip_planes
);
5295 if (shader_time_index
>= 0)
5296 emit_shader_time_end();
5302 assign_curb_setup();
5303 assign_vs_urb_setup();
5305 fixup_3src_null_dest();
5306 allocate_registers();
5312 fs_visitor::run_tes()
5314 assert(stage
== MESA_SHADER_TESS_EVAL
);
5316 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
5317 payload
.num_regs
= 5;
5319 if (shader_time_index
>= 0)
5320 emit_shader_time_begin();
5329 if (shader_time_index
>= 0)
5330 emit_shader_time_end();
5336 assign_curb_setup();
5337 assign_tes_urb_setup();
5339 fixup_3src_null_dest();
5340 allocate_registers();
5346 fs_visitor::run_gs()
5348 assert(stage
== MESA_SHADER_GEOMETRY
);
5352 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
5354 if (gs_compile
->control_data_header_size_bits
> 0) {
5355 /* Create a VGRF to store accumulated control data bits. */
5356 this->control_data_bits
= vgrf(glsl_type::uint_type
);
5358 /* If we're outputting more than 32 control data bits, then EmitVertex()
5359 * will set control_data_bits to 0 after emitting the first vertex.
5360 * Otherwise, we need to initialize it to 0 here.
5362 if (gs_compile
->control_data_header_size_bits
<= 32) {
5363 const fs_builder abld
= bld
.annotate("initialize control data bits");
5364 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
5368 if (shader_time_index
>= 0)
5369 emit_shader_time_begin();
5373 emit_gs_thread_end();
5375 if (shader_time_index
>= 0)
5376 emit_shader_time_end();
5385 assign_curb_setup();
5386 assign_gs_urb_setup();
5388 fixup_3src_null_dest();
5389 allocate_registers();
5395 fs_visitor::run_fs(bool do_rep_send
)
5397 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5398 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5400 assert(stage
== MESA_SHADER_FRAGMENT
);
5402 if (devinfo
->gen
>= 6)
5403 setup_payload_gen6();
5405 setup_payload_gen4();
5409 } else if (do_rep_send
) {
5410 assert(dispatch_width
== 16);
5411 emit_repclear_shader();
5413 if (shader_time_index
>= 0)
5414 emit_shader_time_begin();
5416 calculate_urb_setup();
5417 if (nir
->info
.inputs_read
> 0) {
5418 if (devinfo
->gen
< 6)
5419 emit_interpolation_setup_gen4();
5421 emit_interpolation_setup_gen6();
5424 /* We handle discards by keeping track of the still-live pixels in f0.1.
5425 * Initialize it with the dispatched pixels.
5427 if (wm_prog_data
->uses_kill
) {
5428 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5429 discard_init
->flag_subreg
= 1;
5432 /* Generate FS IR for main(). (the visitor only descends into
5433 * functions called "main").
5440 if (wm_prog_data
->uses_kill
)
5441 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5443 if (wm_key
->alpha_test_func
)
5448 if (shader_time_index
>= 0)
5449 emit_shader_time_end();
5455 assign_curb_setup();
5458 fixup_3src_null_dest();
5459 allocate_registers();
5465 if (dispatch_width
== 8)
5466 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5468 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5474 fs_visitor::run_cs()
5476 assert(stage
== MESA_SHADER_COMPUTE
);
5480 if (shader_time_index
>= 0)
5481 emit_shader_time_begin();
5488 emit_cs_terminate();
5490 if (shader_time_index
>= 0)
5491 emit_shader_time_end();
5497 assign_curb_setup();
5499 fixup_3src_null_dest();
5500 allocate_registers();
5509 * Return a bitfield where bit n is set if barycentric interpolation mode n
5510 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5513 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5514 bool shade_model_flat
,
5515 bool persample_shading
,
5516 const nir_shader
*shader
)
5518 unsigned barycentric_interp_modes
= 0;
5520 nir_foreach_variable(var
, &shader
->inputs
) {
5521 enum glsl_interp_qualifier interp_qualifier
=
5522 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5523 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5524 bool is_sample
= var
->data
.sample
|| persample_shading
;
5525 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5526 (var
->data
.location
== VARYING_SLOT_COL1
);
5528 /* Ignore WPOS and FACE, because they don't require interpolation. */
5529 if (var
->data
.location
== VARYING_SLOT_POS
||
5530 var
->data
.location
== VARYING_SLOT_FACE
)
5533 /* Determine the set (or sets) of barycentric coordinates needed to
5534 * interpolate this variable. Note that when
5535 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5536 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5537 * for lit pixels, so we need both sets of barycentric coordinates.
5539 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5541 barycentric_interp_modes
|=
5542 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5543 } else if (is_sample
) {
5544 barycentric_interp_modes
|=
5545 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5547 if ((!is_centroid
&& !is_sample
) ||
5548 devinfo
->needs_unlit_centroid_workaround
) {
5549 barycentric_interp_modes
|=
5550 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5552 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5553 (!(shade_model_flat
&& is_gl_Color
) &&
5554 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5556 barycentric_interp_modes
|=
5557 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5558 } else if (is_sample
) {
5559 barycentric_interp_modes
|=
5560 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5562 if ((!is_centroid
&& !is_sample
) ||
5563 devinfo
->needs_unlit_centroid_workaround
) {
5564 barycentric_interp_modes
|=
5565 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5570 return barycentric_interp_modes
;
5574 computed_depth_mode(const nir_shader
*shader
)
5576 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5577 switch (shader
->info
.fs
.depth_layout
) {
5578 case FRAG_DEPTH_LAYOUT_NONE
:
5579 case FRAG_DEPTH_LAYOUT_ANY
:
5580 return BRW_PSCDEPTH_ON
;
5581 case FRAG_DEPTH_LAYOUT_GREATER
:
5582 return BRW_PSCDEPTH_ON_GE
;
5583 case FRAG_DEPTH_LAYOUT_LESS
:
5584 return BRW_PSCDEPTH_ON_LE
;
5585 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5586 return BRW_PSCDEPTH_OFF
;
5589 return BRW_PSCDEPTH_OFF
;
5593 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5595 const struct brw_wm_prog_key
*key
,
5596 struct brw_wm_prog_data
*prog_data
,
5597 const nir_shader
*src_shader
,
5598 struct gl_program
*prog
,
5599 int shader_time_index8
, int shader_time_index16
,
5601 unsigned *final_assembly_size
,
5604 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5605 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5607 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5609 /* key->alpha_test_func means simulating alpha testing via discards,
5610 * so the shader definitely kills pixels.
5612 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5613 prog_data
->uses_omask
=
5614 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5615 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5616 prog_data
->computed_stencil
=
5617 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5619 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5621 prog_data
->barycentric_interp_modes
=
5622 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5624 key
->persample_shading
,
5627 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5628 &prog_data
->base
, prog
, shader
, 8,
5629 shader_time_index8
);
5630 if (!v
.run_fs(false /* do_rep_send */)) {
5632 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5637 cfg_t
*simd16_cfg
= NULL
;
5638 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5639 &prog_data
->base
, prog
, shader
, 16,
5640 shader_time_index16
);
5641 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5642 if (!v
.simd16_unsupported
) {
5643 /* Try a SIMD16 compile */
5644 v2
.import_uniforms(&v
);
5645 if (!v2
.run_fs(use_rep_send
)) {
5646 compiler
->shader_perf_log(log_data
,
5647 "SIMD16 shader failed to compile: %s",
5650 simd16_cfg
= v2
.cfg
;
5656 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5657 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5659 prog_data
->no_8
= true;
5662 prog_data
->no_8
= false;
5665 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5666 v
.promoted_constants
, v
.runtime_check_aads_emit
,
5667 MESA_SHADER_FRAGMENT
);
5669 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5670 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5671 shader
->info
.label
? shader
->info
.label
:
5673 shader
->info
.name
));
5677 g
.generate_code(simd8_cfg
, 8);
5679 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5681 return g
.get_assembly(final_assembly_size
);
5685 fs_visitor::emit_cs_local_invocation_id_setup()
5687 assert(stage
== MESA_SHADER_COMPUTE
);
5689 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5691 struct brw_reg src
=
5692 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5693 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5695 src
.nr
+= dispatch_width
/ 8;
5696 bld
.MOV(offset(*reg
, bld
, 1), src
);
5697 src
.nr
+= dispatch_width
/ 8;
5698 bld
.MOV(offset(*reg
, bld
, 2), src
);
5704 fs_visitor::emit_cs_work_group_id_setup()
5706 assert(stage
== MESA_SHADER_COMPUTE
);
5708 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5710 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5711 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5712 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5714 bld
.MOV(*reg
, r0_1
);
5715 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5716 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5722 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5724 const struct brw_cs_prog_key
*key
,
5725 struct brw_cs_prog_data
*prog_data
,
5726 const nir_shader
*src_shader
,
5727 int shader_time_index
,
5728 unsigned *final_assembly_size
,
5731 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5732 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5734 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5736 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5737 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5738 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5739 unsigned local_workgroup_size
=
5740 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5741 shader
->info
.cs
.local_size
[2];
5743 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5746 const char *fail_msg
= NULL
;
5748 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5750 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5751 NULL
, /* Never used in core profile */
5752 shader
, 8, shader_time_index
);
5754 fail_msg
= v8
.fail_msg
;
5755 } else if (local_workgroup_size
<= 8 * max_cs_threads
) {
5757 prog_data
->simd_size
= 8;
5760 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5761 NULL
, /* Never used in core profile */
5762 shader
, 16, shader_time_index
);
5763 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5764 !fail_msg
&& !v8
.simd16_unsupported
&&
5765 local_workgroup_size
<= 16 * max_cs_threads
) {
5766 /* Try a SIMD16 compile */
5767 v16
.import_uniforms(&v8
);
5768 if (!v16
.run_cs()) {
5769 compiler
->shader_perf_log(log_data
,
5770 "SIMD16 shader failed to compile: %s",
5774 "Couldn't generate SIMD16 program and not "
5775 "enough threads for SIMD8";
5779 prog_data
->simd_size
= 16;
5783 if (unlikely(cfg
== NULL
)) {
5786 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5791 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5792 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
5793 MESA_SHADER_COMPUTE
);
5794 if (INTEL_DEBUG
& DEBUG_CS
) {
5795 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5796 shader
->info
.label
? shader
->info
.label
:
5799 g
.enable_debug(name
);
5802 g
.generate_code(cfg
, prog_data
->simd_size
);
5804 return g
.get_assembly(final_assembly_size
);
5808 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
5809 void *buffer
, uint32_t threads
, uint32_t stride
)
5811 if (prog_data
->local_invocation_id_regs
== 0)
5814 /* 'stride' should be an integer number of registers, that is, a multiple
5817 assert(stride
% 32 == 0);
5819 unsigned x
= 0, y
= 0, z
= 0;
5820 for (unsigned t
= 0; t
< threads
; t
++) {
5821 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
5823 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
5824 param
[0 * prog_data
->simd_size
+ i
] = x
;
5825 param
[1 * prog_data
->simd_size
+ i
] = y
;
5826 param
[2 * prog_data
->simd_size
+ i
] = z
;
5829 if (x
== prog_data
->local_size
[0]) {
5832 if (y
== prog_data
->local_size
[1]) {
5835 if (z
== prog_data
->local_size
[2])