2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "brw_vec4_gs_visitor.h"
48 #include "brw_dead_control_flow.h"
49 #include "main/uniforms.h"
50 #include "brw_fs_live_variables.h"
51 #include "glsl/nir/glsl_types.h"
52 #include "program/sampler.h"
57 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
58 const fs_reg
*src
, unsigned sources
)
60 memset(this, 0, sizeof(*this));
62 this->src
= new fs_reg
[MAX2(sources
, 3)];
63 for (unsigned i
= 0; i
< sources
; i
++)
64 this->src
[i
] = src
[i
];
66 this->opcode
= opcode
;
68 this->sources
= sources
;
69 this->exec_size
= exec_size
;
71 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
73 assert(this->exec_size
!= 0);
75 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
77 /* This will be the case for almost all instructions. */
83 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
87 this->regs_written
= 0;
91 unreachable("Invalid destination register file");
94 this->writes_accumulator
= false;
99 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
104 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
107 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
109 init(opcode
, exec_size
, dst
, NULL
, 0);
112 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
115 const fs_reg src
[1] = { src0
};
116 init(opcode
, exec_size
, dst
, src
, 1);
119 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
120 const fs_reg
&src0
, const fs_reg
&src1
)
122 const fs_reg src
[2] = { src0
, src1
};
123 init(opcode
, exec_size
, dst
, src
, 2);
126 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
127 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
129 const fs_reg src
[3] = { src0
, src1
, src2
};
130 init(opcode
, exec_size
, dst
, src
, 3);
133 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
134 const fs_reg src
[], unsigned sources
)
136 init(opcode
, exec_width
, dst
, src
, sources
);
139 fs_inst::fs_inst(const fs_inst
&that
)
141 memcpy(this, &that
, sizeof(that
));
143 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
145 for (unsigned i
= 0; i
< that
.sources
; i
++)
146 this->src
[i
] = that
.src
[i
];
155 fs_inst::resize_sources(uint8_t num_sources
)
157 if (this->sources
!= num_sources
) {
158 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
160 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
161 src
[i
] = this->src
[i
];
165 this->sources
= num_sources
;
170 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
172 const fs_reg
&surf_index
,
173 const fs_reg
&varying_offset
,
174 uint32_t const_offset
)
176 /* We have our constant surface use a pitch of 4 bytes, so our index can
177 * be any component of a vector, and then we load 4 contiguous
178 * components starting from that.
180 * We break down the const_offset to a portion added to the variable
181 * offset and a portion done using reg_offset, which means that if you
182 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
183 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
184 * CSE can later notice that those loads are all the same and eliminate
185 * the redundant ones.
187 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
188 bld
.ADD(vec4_offset
, varying_offset
, fs_reg(const_offset
& ~3));
191 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
192 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
193 * u, v, r) as parameters, or we can just use the SIMD16 message
194 * consisting of (header, u). We choose the second, at the cost of a
195 * longer return length.
201 if (devinfo
->gen
>= 7)
202 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
204 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
206 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
207 fs_reg vec4_result
= fs_reg(GRF
, alloc
.allocate(regs_written
), dst
.type
);
208 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
209 inst
->regs_written
= regs_written
;
211 if (devinfo
->gen
< 7) {
212 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
213 inst
->header_size
= 1;
214 if (devinfo
->gen
== 4)
217 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
220 bld
.MOV(dst
, offset(vec4_result
, bld
, (const_offset
& 3) * scale
));
224 * A helper for MOV generation for fixing up broken hardware SEND dependency
228 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
230 /* The caller always wants uncompressed to emit the minimal extra
231 * dependencies, and to avoid having to deal with aligning its regs to 2.
233 const fs_builder ubld
= bld
.annotate("send dependency resolve")
236 ubld
.MOV(ubld
.null_reg_f(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
240 fs_inst::equals(fs_inst
*inst
) const
242 return (opcode
== inst
->opcode
&&
243 dst
.equals(inst
->dst
) &&
244 src
[0].equals(inst
->src
[0]) &&
245 src
[1].equals(inst
->src
[1]) &&
246 src
[2].equals(inst
->src
[2]) &&
247 saturate
== inst
->saturate
&&
248 predicate
== inst
->predicate
&&
249 conditional_mod
== inst
->conditional_mod
&&
250 mlen
== inst
->mlen
&&
251 base_mrf
== inst
->base_mrf
&&
252 target
== inst
->target
&&
254 header_size
== inst
->header_size
&&
255 shadow_compare
== inst
->shadow_compare
&&
256 exec_size
== inst
->exec_size
&&
257 offset
== inst
->offset
);
261 fs_inst::overwrites_reg(const fs_reg
®
) const
263 return reg
.in_range(dst
, regs_written
);
267 fs_inst::is_send_from_grf() const
270 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
271 case SHADER_OPCODE_SHADER_TIME_ADD
:
272 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
273 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
274 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
275 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
276 case SHADER_OPCODE_UNTYPED_ATOMIC
:
277 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
278 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
279 case SHADER_OPCODE_TYPED_ATOMIC
:
280 case SHADER_OPCODE_TYPED_SURFACE_READ
:
281 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
282 case SHADER_OPCODE_URB_WRITE_SIMD8
:
283 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
284 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
285 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
286 case SHADER_OPCODE_URB_READ_SIMD8
:
288 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
289 return src
[1].file
== GRF
;
290 case FS_OPCODE_FB_WRITE
:
291 return src
[0].file
== GRF
;
294 return src
[0].file
== GRF
;
301 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
303 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
306 fs_reg reg
= this->src
[0];
307 if (reg
.file
!= GRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
310 if (grf_alloc
.sizes
[reg
.reg
] != this->regs_written
)
313 for (int i
= 0; i
< this->sources
; i
++) {
314 reg
.type
= this->src
[i
].type
;
315 if (!this->src
[i
].equals(reg
))
318 if (i
< this->header_size
) {
321 reg
.reg_offset
+= this->exec_size
/ 8;
329 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
331 if (devinfo
->gen
== 6 && is_math())
334 if (is_send_from_grf())
337 if (!backend_instruction::can_do_source_mods())
344 fs_inst::can_change_types() const
346 return dst
.type
== src
[0].type
&&
347 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
348 (opcode
== BRW_OPCODE_MOV
||
349 (opcode
== BRW_OPCODE_SEL
&&
350 dst
.type
== src
[1].type
&&
351 predicate
!= BRW_PREDICATE_NONE
&&
352 !src
[1].abs
&& !src
[1].negate
));
356 fs_inst::has_side_effects() const
358 return this->eot
|| backend_instruction::has_side_effects();
364 memset(this, 0, sizeof(*this));
368 /** Generic unset register constructor. */
372 this->file
= BAD_FILE
;
375 /** Immediate value constructor. */
376 fs_reg::fs_reg(float f
)
380 this->type
= BRW_REGISTER_TYPE_F
;
382 this->fixed_hw_reg
.dw1
.f
= f
;
385 /** Immediate value constructor. */
386 fs_reg::fs_reg(int32_t i
)
390 this->type
= BRW_REGISTER_TYPE_D
;
392 this->fixed_hw_reg
.dw1
.d
= i
;
395 /** Immediate value constructor. */
396 fs_reg::fs_reg(uint32_t u
)
400 this->type
= BRW_REGISTER_TYPE_UD
;
402 this->fixed_hw_reg
.dw1
.ud
= u
;
405 /** Vector float immediate value constructor. */
406 fs_reg::fs_reg(uint8_t vf
[4])
410 this->type
= BRW_REGISTER_TYPE_VF
;
411 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
414 /** Vector float immediate value constructor. */
415 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
419 this->type
= BRW_REGISTER_TYPE_VF
;
420 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
426 /** Fixed brw_reg. */
427 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
431 this->fixed_hw_reg
= fixed_hw_reg
;
432 this->type
= fixed_hw_reg
.type
;
436 fs_reg::equals(const fs_reg
&r
) const
438 return (file
== r
.file
&&
440 reg_offset
== r
.reg_offset
&&
441 subreg_offset
== r
.subreg_offset
&&
443 negate
== r
.negate
&&
445 !reladdr
&& !r
.reladdr
&&
446 ((file
!= HW_REG
&& file
!= IMM
) ||
447 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
448 sizeof(fixed_hw_reg
)) == 0) &&
453 fs_reg::set_smear(unsigned subreg
)
455 assert(file
!= HW_REG
&& file
!= IMM
);
456 subreg_offset
= subreg
* type_sz(type
);
462 fs_reg::is_contiguous() const
468 fs_reg::component_size(unsigned width
) const
470 const unsigned stride
= (file
!= HW_REG
? this->stride
:
471 fixed_hw_reg
.hstride
== 0 ? 0 :
472 1 << (fixed_hw_reg
.hstride
- 1));
473 return MAX2(width
* stride
, 1) * type_sz(type
);
477 type_size_scalar(const struct glsl_type
*type
)
479 unsigned int size
, i
;
481 switch (type
->base_type
) {
484 case GLSL_TYPE_FLOAT
:
486 return type
->components();
487 case GLSL_TYPE_ARRAY
:
488 return type_size_scalar(type
->fields
.array
) * type
->length
;
489 case GLSL_TYPE_STRUCT
:
491 for (i
= 0; i
< type
->length
; i
++) {
492 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
495 case GLSL_TYPE_SAMPLER
:
496 /* Samplers take up no register space, since they're baked in at
500 case GLSL_TYPE_ATOMIC_UINT
:
502 case GLSL_TYPE_SUBROUTINE
:
504 case GLSL_TYPE_IMAGE
:
505 return BRW_IMAGE_PARAM_SIZE
;
507 case GLSL_TYPE_ERROR
:
508 case GLSL_TYPE_INTERFACE
:
509 case GLSL_TYPE_DOUBLE
:
510 unreachable("not reached");
517 * Create a MOV to read the timestamp register.
519 * The caller is responsible for emitting the MOV. The return value is
520 * the destination of the MOV, with extra parameters set.
523 fs_visitor::get_timestamp(const fs_builder
&bld
)
525 assert(devinfo
->gen
>= 7);
527 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
530 BRW_REGISTER_TYPE_UD
));
532 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
534 /* We want to read the 3 fields we care about even if it's not enabled in
537 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
543 fs_visitor::emit_shader_time_begin()
545 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
547 /* We want only the low 32 bits of the timestamp. Since it's running
548 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
549 * which is plenty of time for our purposes. It is identical across the
550 * EUs, but since it's tracking GPU core speed it will increment at a
551 * varying rate as render P-states change.
553 shader_start_time
.set_smear(0);
557 fs_visitor::emit_shader_time_end()
559 /* Insert our code just before the final SEND with EOT. */
560 exec_node
*end
= this->instructions
.get_tail();
561 assert(end
&& ((fs_inst
*) end
)->eot
);
562 const fs_builder ibld
= bld
.annotate("shader time end")
563 .exec_all().at(NULL
, end
);
565 fs_reg shader_end_time
= get_timestamp(ibld
);
567 /* We only use the low 32 bits of the timestamp - see
568 * emit_shader_time_begin()).
570 * We could also check if render P-states have changed (or anything
571 * else that might disrupt timing) by setting smear to 2 and checking if
572 * that field is != 0.
574 shader_end_time
.set_smear(0);
576 /* Check that there weren't any timestamp reset events (assuming these
577 * were the only two timestamp reads that happened).
579 fs_reg reset
= shader_end_time
;
581 set_condmod(BRW_CONDITIONAL_Z
,
582 ibld
.AND(ibld
.null_reg_ud(), reset
, fs_reg(1u)));
583 ibld
.IF(BRW_PREDICATE_NORMAL
);
585 fs_reg start
= shader_start_time
;
587 fs_reg diff
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
590 const fs_builder cbld
= ibld
.group(1, 0);
591 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
593 /* If there were no instructions between the two timestamp gets, the diff
594 * is 2 cycles. Remove that overhead, so I can forget about that when
595 * trying to determine the time taken for single instructions.
597 cbld
.ADD(diff
, diff
, fs_reg(-2u));
598 SHADER_TIME_ADD(cbld
, 0, diff
);
599 SHADER_TIME_ADD(cbld
, 1, fs_reg(1u));
600 ibld
.emit(BRW_OPCODE_ELSE
);
601 SHADER_TIME_ADD(cbld
, 2, fs_reg(1u));
602 ibld
.emit(BRW_OPCODE_ENDIF
);
606 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
607 int shader_time_subindex
,
610 int index
= shader_time_index
* 3 + shader_time_subindex
;
611 fs_reg offset
= fs_reg(index
* SHADER_TIME_STRIDE
);
614 if (dispatch_width
== 8)
615 payload
= vgrf(glsl_type::uvec2_type
);
617 payload
= vgrf(glsl_type::uint_type
);
619 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
623 fs_visitor::vfail(const char *format
, va_list va
)
632 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
633 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
635 this->fail_msg
= msg
;
638 fprintf(stderr
, "%s", msg
);
643 fs_visitor::fail(const char *format
, ...)
647 va_start(va
, format
);
653 * Mark this program as impossible to compile in SIMD16 mode.
655 * During the SIMD8 compile (which happens first), we can detect and flag
656 * things that are unsupported in SIMD16 mode, so the compiler can skip
657 * the SIMD16 compile altogether.
659 * During a SIMD16 compile (if one happens anyway), this just calls fail().
662 fs_visitor::no16(const char *msg
)
664 if (dispatch_width
== 16) {
667 simd16_unsupported
= true;
669 compiler
->shader_perf_log(log_data
,
670 "SIMD16 shader failed to compile: %s", msg
);
675 * Returns true if the instruction has a flag that means it won't
676 * update an entire destination register.
678 * For example, dead code elimination and live variable analysis want to know
679 * when a write to a variable screens off any preceding values that were in
683 fs_inst::is_partial_write() const
685 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
686 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
687 !this->dst
.is_contiguous());
691 fs_inst::components_read(unsigned i
) const
694 case FS_OPCODE_LINTERP
:
700 case FS_OPCODE_PIXEL_X
:
701 case FS_OPCODE_PIXEL_Y
:
705 case FS_OPCODE_FB_WRITE_LOGICAL
:
706 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
707 /* First/second FB write color. */
709 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].fixed_hw_reg
.dw1
.ud
;
713 case SHADER_OPCODE_TEX_LOGICAL
:
714 case SHADER_OPCODE_TXD_LOGICAL
:
715 case SHADER_OPCODE_TXF_LOGICAL
:
716 case SHADER_OPCODE_TXL_LOGICAL
:
717 case SHADER_OPCODE_TXS_LOGICAL
:
718 case FS_OPCODE_TXB_LOGICAL
:
719 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
720 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
721 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
722 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
723 case SHADER_OPCODE_LOD_LOGICAL
:
724 case SHADER_OPCODE_TG4_LOGICAL
:
725 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
726 assert(src
[8].file
== IMM
&& src
[9].file
== IMM
);
727 /* Texture coordinates. */
729 return src
[8].fixed_hw_reg
.dw1
.ud
;
730 /* Texture derivatives. */
731 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
732 return src
[9].fixed_hw_reg
.dw1
.ud
;
733 /* Texture offset. */
737 else if (i
== 5 && opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
742 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
743 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
744 assert(src
[3].file
== IMM
);
745 /* Surface coordinates. */
747 return src
[3].fixed_hw_reg
.dw1
.ud
;
748 /* Surface operation source (ignored for reads). */
754 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
755 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
756 assert(src
[3].file
== IMM
&&
758 /* Surface coordinates. */
760 return src
[3].fixed_hw_reg
.dw1
.ud
;
761 /* Surface operation source. */
763 return src
[4].fixed_hw_reg
.dw1
.ud
;
767 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
768 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
769 assert(src
[3].file
== IMM
&&
771 const unsigned op
= src
[4].fixed_hw_reg
.dw1
.ud
;
772 /* Surface coordinates. */
774 return src
[3].fixed_hw_reg
.dw1
.ud
;
775 /* Surface operation source. */
776 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
778 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
779 op
== BRW_AOP_PREDEC
))
791 fs_inst::regs_read(int arg
) const
794 case FS_OPCODE_FB_WRITE
:
795 case SHADER_OPCODE_URB_WRITE_SIMD8
:
796 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
797 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
798 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
799 case SHADER_OPCODE_URB_READ_SIMD8
:
800 case SHADER_OPCODE_UNTYPED_ATOMIC
:
801 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
802 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
803 case SHADER_OPCODE_TYPED_ATOMIC
:
804 case SHADER_OPCODE_TYPED_SURFACE_READ
:
805 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
806 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
811 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
812 /* The payload is actually stored in src1 */
817 case FS_OPCODE_LINTERP
:
822 case SHADER_OPCODE_LOAD_PAYLOAD
:
823 if (arg
< this->header_size
)
827 case CS_OPCODE_CS_TERMINATE
:
828 case SHADER_OPCODE_BARRIER
:
832 if (is_tex() && arg
== 0 && src
[0].file
== GRF
)
837 switch (src
[arg
].file
) {
846 return DIV_ROUND_UP(components_read(arg
) *
847 src
[arg
].component_size(exec_size
),
850 unreachable("MRF registers are not allowed as sources");
856 fs_inst::reads_flag() const
862 fs_inst::writes_flag() const
864 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
865 opcode
!= BRW_OPCODE_IF
&&
866 opcode
!= BRW_OPCODE_WHILE
)) ||
867 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
871 * Returns how many MRFs an FS opcode will write over.
873 * Note that this is not the 0 or 1 implied writes in an actual gen
874 * instruction -- the FS opcodes often generate MOVs in addition.
877 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
882 if (inst
->base_mrf
== -1)
885 switch (inst
->opcode
) {
886 case SHADER_OPCODE_RCP
:
887 case SHADER_OPCODE_RSQ
:
888 case SHADER_OPCODE_SQRT
:
889 case SHADER_OPCODE_EXP2
:
890 case SHADER_OPCODE_LOG2
:
891 case SHADER_OPCODE_SIN
:
892 case SHADER_OPCODE_COS
:
893 return 1 * dispatch_width
/ 8;
894 case SHADER_OPCODE_POW
:
895 case SHADER_OPCODE_INT_QUOTIENT
:
896 case SHADER_OPCODE_INT_REMAINDER
:
897 return 2 * dispatch_width
/ 8;
898 case SHADER_OPCODE_TEX
:
900 case SHADER_OPCODE_TXD
:
901 case SHADER_OPCODE_TXF
:
902 case SHADER_OPCODE_TXF_CMS
:
903 case SHADER_OPCODE_TXF_CMS_W
:
904 case SHADER_OPCODE_TXF_MCS
:
905 case SHADER_OPCODE_TG4
:
906 case SHADER_OPCODE_TG4_OFFSET
:
907 case SHADER_OPCODE_TXL
:
908 case SHADER_OPCODE_TXS
:
909 case SHADER_OPCODE_LOD
:
910 case SHADER_OPCODE_SAMPLEINFO
:
912 case FS_OPCODE_FB_WRITE
:
914 case FS_OPCODE_GET_BUFFER_SIZE
:
915 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
916 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
918 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
920 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
922 case SHADER_OPCODE_UNTYPED_ATOMIC
:
923 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
924 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
925 case SHADER_OPCODE_TYPED_ATOMIC
:
926 case SHADER_OPCODE_TYPED_SURFACE_READ
:
927 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
928 case SHADER_OPCODE_URB_WRITE_SIMD8
:
929 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
930 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
931 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
932 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
933 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
934 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
935 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
938 unreachable("not reached");
943 fs_visitor::vgrf(const glsl_type
*const type
)
945 int reg_width
= dispatch_width
/ 8;
946 return fs_reg(GRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
947 brw_type_for_base_type(type
));
950 /** Fixed HW reg constructor. */
951 fs_reg::fs_reg(enum register_file file
, int reg
)
956 this->type
= BRW_REGISTER_TYPE_F
;
957 this->stride
= (file
== UNIFORM
? 0 : 1);
960 /** Fixed HW reg constructor. */
961 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
)
967 this->stride
= (file
== UNIFORM
? 0 : 1);
970 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
971 * This brings in those uniform definitions
974 fs_visitor::import_uniforms(fs_visitor
*v
)
976 this->push_constant_loc
= v
->push_constant_loc
;
977 this->pull_constant_loc
= v
->pull_constant_loc
;
978 this->uniforms
= v
->uniforms
;
979 this->param_size
= v
->param_size
;
983 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
984 bool origin_upper_left
)
986 assert(stage
== MESA_SHADER_FRAGMENT
);
987 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
988 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
990 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
993 if (pixel_center_integer
) {
994 bld
.MOV(wpos
, this->pixel_x
);
996 bld
.ADD(wpos
, this->pixel_x
, fs_reg(0.5f
));
998 wpos
= offset(wpos
, bld
, 1);
1000 /* gl_FragCoord.y */
1001 if (!flip
&& pixel_center_integer
) {
1002 bld
.MOV(wpos
, this->pixel_y
);
1004 fs_reg pixel_y
= this->pixel_y
;
1005 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
1008 pixel_y
.negate
= true;
1009 offset
+= key
->drawable_height
- 1.0f
;
1012 bld
.ADD(wpos
, pixel_y
, fs_reg(offset
));
1014 wpos
= offset(wpos
, bld
, 1);
1016 /* gl_FragCoord.z */
1017 if (devinfo
->gen
>= 6) {
1018 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1020 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1021 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1022 interp_reg(VARYING_SLOT_POS
, 2));
1024 wpos
= offset(wpos
, bld
, 1);
1026 /* gl_FragCoord.w: Already set up in emit_interpolation */
1027 bld
.MOV(wpos
, this->wpos_w
);
1033 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1034 glsl_interp_qualifier interpolation_mode
,
1035 bool is_centroid
, bool is_sample
)
1037 brw_wm_barycentric_interp_mode barycoord_mode
;
1038 if (devinfo
->gen
>= 6) {
1040 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1041 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1043 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1044 } else if (is_sample
) {
1045 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1046 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1048 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1050 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1051 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1053 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1056 /* On Ironlake and below, there is only one interpolation mode.
1057 * Centroid interpolation doesn't mean anything on this hardware --
1058 * there is no multisampling.
1060 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1062 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1063 this->delta_xy
[barycoord_mode
], interp
);
1067 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1068 const glsl_type
*type
,
1069 glsl_interp_qualifier interpolation_mode
,
1070 int location
, bool mod_centroid
,
1073 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1075 assert(stage
== MESA_SHADER_FRAGMENT
);
1076 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1077 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1079 unsigned int array_elements
;
1081 if (type
->is_array()) {
1082 array_elements
= type
->arrays_of_arrays_size();
1083 if (array_elements
== 0) {
1084 fail("dereferenced array '%s' has length 0\n", name
);
1086 type
= type
->without_array();
1091 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1093 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1094 if (key
->flat_shade
&& is_gl_Color
) {
1095 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1097 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1101 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1102 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1103 if (prog_data
->urb_setup
[location
] == -1) {
1104 /* If there's no incoming setup data for this slot, don't
1105 * emit interpolation for it.
1107 attr
= offset(attr
, bld
, type
->vector_elements
);
1112 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1113 /* Constant interpolation (flat shading) case. The SF has
1114 * handed us defined values in only the constant offset
1115 * field of the setup reg.
1117 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1118 struct brw_reg interp
= interp_reg(location
, k
);
1119 interp
= suboffset(interp
, 3);
1120 interp
.type
= attr
.type
;
1121 bld
.emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1122 attr
= offset(attr
, bld
, 1);
1125 /* Smooth/noperspective interpolation case. */
1126 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1127 struct brw_reg interp
= interp_reg(location
, k
);
1128 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1129 /* Get the pixel/sample mask into f0 so that we know
1130 * which pixels are lit. Then, for each channel that is
1131 * unlit, replace the centroid data with non-centroid
1134 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1137 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1139 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1140 inst
->predicate_inverse
= true;
1141 if (devinfo
->has_pln
)
1142 inst
->no_dd_clear
= true;
1144 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1145 mod_centroid
&& !key
->persample_shading
,
1146 mod_sample
|| key
->persample_shading
);
1147 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1148 inst
->predicate_inverse
= false;
1149 if (devinfo
->has_pln
)
1150 inst
->no_dd_check
= true;
1153 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1154 mod_centroid
&& !key
->persample_shading
,
1155 mod_sample
|| key
->persample_shading
);
1157 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1158 bld
.MUL(attr
, attr
, this->pixel_w
);
1160 attr
= offset(attr
, bld
, 1);
1170 fs_visitor::emit_frontfacing_interpolation()
1172 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1174 if (devinfo
->gen
>= 6) {
1175 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1176 * a boolean result from this (~0/true or 0/false).
1178 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1179 * this task in only one instruction:
1180 * - a negation source modifier will flip the bit; and
1181 * - a W -> D type conversion will sign extend the bit into the high
1182 * word of the destination.
1184 * An ASR 15 fills the low word of the destination.
1186 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1189 bld
.ASR(*reg
, g0
, fs_reg(15));
1191 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1192 * a boolean result from this (1/true or 0/false).
1194 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1195 * the negation source modifier to flip it. Unfortunately the SHR
1196 * instruction only operates on UD (or D with an abs source modifier)
1197 * sources without negation.
1199 * Instead, use ASR (which will give ~0/true or 0/false).
1201 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1204 bld
.ASR(*reg
, g1_6
, fs_reg(31));
1211 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1213 assert(stage
== MESA_SHADER_FRAGMENT
);
1214 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1215 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1217 if (key
->compute_pos_offset
) {
1218 /* Convert int_sample_pos to floating point */
1219 bld
.MOV(dst
, int_sample_pos
);
1220 /* Scale to the range [0, 1] */
1221 bld
.MUL(dst
, dst
, fs_reg(1 / 16.0f
));
1224 /* From ARB_sample_shading specification:
1225 * "When rendering to a non-multisample buffer, or if multisample
1226 * rasterization is disabled, gl_SamplePosition will always be
1229 bld
.MOV(dst
, fs_reg(0.5f
));
1234 fs_visitor::emit_samplepos_setup()
1236 assert(devinfo
->gen
>= 6);
1238 const fs_builder abld
= bld
.annotate("compute sample position");
1239 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1241 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1242 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1244 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1245 * mode will be enabled.
1247 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1248 * R31.1:0 Position Offset X/Y for Slot[3:0]
1249 * R31.3:2 Position Offset X/Y for Slot[7:4]
1252 * The X, Y sample positions come in as bytes in thread payload. So, read
1253 * the positions using vstride=16, width=8, hstride=2.
1255 struct brw_reg sample_pos_reg
=
1256 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1257 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1259 if (dispatch_width
== 8) {
1260 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1262 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1263 abld
.half(1).MOV(half(int_sample_x
, 1),
1264 fs_reg(suboffset(sample_pos_reg
, 16)));
1266 /* Compute gl_SamplePosition.x */
1267 compute_sample_position(pos
, int_sample_x
);
1268 pos
= offset(pos
, abld
, 1);
1269 if (dispatch_width
== 8) {
1270 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1272 abld
.half(0).MOV(half(int_sample_y
, 0),
1273 fs_reg(suboffset(sample_pos_reg
, 1)));
1274 abld
.half(1).MOV(half(int_sample_y
, 1),
1275 fs_reg(suboffset(sample_pos_reg
, 17)));
1277 /* Compute gl_SamplePosition.y */
1278 compute_sample_position(pos
, int_sample_y
);
1283 fs_visitor::emit_sampleid_setup()
1285 assert(stage
== MESA_SHADER_FRAGMENT
);
1286 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1287 assert(devinfo
->gen
>= 6);
1289 const fs_builder abld
= bld
.annotate("compute sample id");
1290 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1292 if (key
->compute_sample_id
) {
1293 fs_reg
t1(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1295 fs_reg
t2(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1297 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1298 * 8x multisampling, subspan 0 will represent sample N (where N
1299 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1300 * 7. We can find the value of N by looking at R0.0 bits 7:6
1301 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1302 * (since samples are always delivered in pairs). That is, we
1303 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1304 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1305 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1306 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1307 * populating a temporary variable with the sequence (0, 1, 2, 3),
1308 * and then reading from it using vstride=1, width=4, hstride=0.
1309 * These computations hold good for 4x multisampling as well.
1311 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1312 * the first four slots are sample 0 of subspan 0; the next four
1313 * are sample 1 of subspan 0; the third group is sample 0 of
1314 * subspan 1, and finally sample 1 of subspan 1.
1317 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1318 * accomodate 16x MSAA.
1320 unsigned sspi_mask
= devinfo
->gen
>= 9 ? 0x1c0 : 0xc0;
1322 abld
.exec_all().group(1, 0)
1323 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1325 abld
.exec_all().group(1, 0).SHR(t1
, t1
, fs_reg(5));
1327 /* This works for both SIMD8 and SIMD16 */
1328 abld
.exec_all().group(4, 0)
1329 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1331 /* This special instruction takes care of setting vstride=1,
1332 * width=4, hstride=0 of t2 during an ADD instruction.
1334 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1336 /* As per GL_ARB_sample_shading specification:
1337 * "When rendering to a non-multisample buffer, or if multisample
1338 * rasterization is disabled, gl_SampleID will always be zero."
1340 abld
.MOV(*reg
, fs_reg(0));
1347 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1349 if (!src
.abs
&& !src
.negate
)
1352 fs_reg temp
= bld
.vgrf(src
.type
);
1359 fs_visitor::emit_discard_jump()
1361 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1363 /* For performance, after a discard, jump to the end of the
1364 * shader if all relevant channels have been discarded.
1366 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1367 discard_jump
->flag_subreg
= 1;
1369 discard_jump
->predicate
= (dispatch_width
== 8)
1370 ? BRW_PREDICATE_ALIGN1_ANY8H
1371 : BRW_PREDICATE_ALIGN1_ANY16H
;
1372 discard_jump
->predicate_inverse
= true;
1376 fs_visitor::emit_gs_thread_end()
1378 assert(stage
== MESA_SHADER_GEOMETRY
);
1380 struct brw_gs_prog_data
*gs_prog_data
=
1381 (struct brw_gs_prog_data
*) prog_data
;
1383 if (gs_compile
->control_data_header_size_bits
> 0) {
1384 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1387 const fs_builder abld
= bld
.annotate("thread end");
1390 if (gs_prog_data
->static_vertex_count
!= -1) {
1391 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1392 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1393 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1394 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1395 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1398 /* Delete now dead instructions. */
1399 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1405 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1409 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1410 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1411 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1414 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1415 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1416 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1417 sources
[1] = this->final_gs_vertex_count
;
1418 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1419 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1427 fs_visitor::assign_curb_setup()
1429 if (dispatch_width
== 8) {
1430 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1432 if (stage
== MESA_SHADER_FRAGMENT
) {
1433 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1434 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1435 } else if (stage
== MESA_SHADER_COMPUTE
) {
1436 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1437 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1439 unreachable("Unsupported shader type!");
1443 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1445 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1446 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1447 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1448 if (inst
->src
[i
].file
== UNIFORM
) {
1449 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1451 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1452 constant_nr
= push_constant_loc
[uniform_nr
];
1454 /* Section 5.11 of the OpenGL 4.1 spec says:
1455 * "Out-of-bounds reads return undefined values, which include
1456 * values from other variables of the active program or zero."
1457 * Just return the first push constant.
1462 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1466 assert(inst
->src
[i
].stride
== 0);
1467 inst
->src
[i
].file
= HW_REG
;
1468 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1469 retype(brw_reg
, inst
->src
[i
].type
),
1470 inst
->src
[i
].subreg_offset
);
1475 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1476 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1480 fs_visitor::calculate_urb_setup()
1482 assert(stage
== MESA_SHADER_FRAGMENT
);
1483 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1484 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1486 memset(prog_data
->urb_setup
, -1,
1487 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1490 /* Figure out where each of the incoming setup attributes lands. */
1491 if (devinfo
->gen
>= 6) {
1492 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1493 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1494 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1495 * first 16 varying inputs, so we can put them wherever we want.
1496 * Just put them in order.
1498 * This is useful because it means that (a) inputs not used by the
1499 * fragment shader won't take up valuable register space, and (b) we
1500 * won't have to recompile the fragment shader if it gets paired with
1501 * a different vertex (or geometry) shader.
1503 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1504 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1505 BITFIELD64_BIT(i
)) {
1506 prog_data
->urb_setup
[i
] = urb_next
++;
1510 bool include_vue_header
=
1511 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1513 /* We have enough input varyings that the SF/SBE pipeline stage can't
1514 * arbitrarily rearrange them to suit our whim; we have to put them
1515 * in an order that matches the output of the previous pipeline stage
1516 * (geometry or vertex shader).
1518 struct brw_vue_map prev_stage_vue_map
;
1519 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1520 key
->input_slots_valid
,
1521 nir
->info
.separate_shader
);
1523 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1525 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1526 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1528 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1529 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1530 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1531 BITFIELD64_BIT(varying
))) {
1532 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1535 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1538 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1539 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1540 /* Point size is packed into the header, not as a general attribute */
1541 if (i
== VARYING_SLOT_PSIZ
)
1544 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1545 /* The back color slot is skipped when the front color is
1546 * also written to. In addition, some slots can be
1547 * written in the vertex shader and not read in the
1548 * fragment shader. So the register number must always be
1549 * incremented, mapped or not.
1551 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1552 prog_data
->urb_setup
[i
] = urb_next
;
1558 * It's a FS only attribute, and we did interpolation for this attribute
1559 * in SF thread. So, count it here, too.
1561 * See compile_sf_prog() for more info.
1563 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1564 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1567 prog_data
->num_varying_inputs
= urb_next
;
1571 fs_visitor::assign_urb_setup()
1573 assert(stage
== MESA_SHADER_FRAGMENT
);
1574 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1576 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1578 /* Offset all the urb_setup[] index by the actual position of the
1579 * setup regs, now that the location of the constants has been chosen.
1581 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1582 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1583 assert(inst
->src
[1].file
== HW_REG
);
1584 inst
->src
[1].fixed_hw_reg
.nr
+= urb_start
;
1587 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1588 assert(inst
->src
[0].file
== HW_REG
);
1589 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1593 /* Each attribute is 4 setup channels, each of which is half a reg. */
1594 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1598 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1600 for (int i
= 0; i
< inst
->sources
; i
++) {
1601 if (inst
->src
[i
].file
== ATTR
) {
1602 int grf
= payload
.num_regs
+
1603 prog_data
->curb_read_length
+
1605 inst
->src
[i
].reg_offset
;
1607 inst
->src
[i
].file
= HW_REG
;
1608 inst
->src
[i
].fixed_hw_reg
=
1609 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1610 inst
->src
[i
].subreg_offset
),
1611 inst
->exec_size
* inst
->src
[i
].stride
,
1612 inst
->exec_size
, inst
->src
[i
].stride
);
1618 fs_visitor::assign_vs_urb_setup()
1620 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1622 assert(stage
== MESA_SHADER_VERTEX
);
1623 int count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1624 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1627 /* Each attribute is 4 regs. */
1628 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1630 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1632 /* Rewrite all ATTR file references to the hw grf that they land in. */
1633 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1634 convert_attr_sources_to_hw_regs(inst
);
1639 fs_visitor::assign_gs_urb_setup()
1641 assert(stage
== MESA_SHADER_GEOMETRY
);
1643 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1645 first_non_payload_grf
+=
1646 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1648 const unsigned first_icp_handle
= payload
.num_regs
-
1649 (vue_prog_data
->include_vue_handles
? nir
->info
.gs
.vertices_in
: 0);
1651 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1652 /* Lower URB_READ_SIMD8 opcodes into real messages. */
1653 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8
) {
1654 assert(inst
->src
[0].file
== IMM
);
1655 inst
->src
[0] = retype(brw_vec8_grf(first_icp_handle
+
1656 inst
->src
[0].fixed_hw_reg
.dw1
.ud
,
1657 0), BRW_REGISTER_TYPE_UD
);
1658 /* for now, assume constant - we can do per-slot offsets later */
1659 assert(inst
->src
[1].file
== IMM
);
1660 inst
->offset
= inst
->src
[1].fixed_hw_reg
.dw1
.ud
;
1661 inst
->src
[1] = fs_reg();
1663 inst
->base_mrf
= -1;
1666 /* Rewrite all ATTR file references to HW_REGs. */
1667 convert_attr_sources_to_hw_regs(inst
);
1673 * Split large virtual GRFs into separate components if we can.
1675 * This is mostly duplicated with what brw_fs_vector_splitting does,
1676 * but that's really conservative because it's afraid of doing
1677 * splitting that doesn't result in real progress after the rest of
1678 * the optimization phases, which would cause infinite looping in
1679 * optimization. We can do it once here, safely. This also has the
1680 * opportunity to split interpolated values, or maybe even uniforms,
1681 * which we don't have at the IR level.
1683 * We want to split, because virtual GRFs are what we register
1684 * allocate and spill (due to contiguousness requirements for some
1685 * instructions), and they're what we naturally generate in the
1686 * codegen process, but most virtual GRFs don't actually need to be
1687 * contiguous sets of GRFs. If we split, we'll end up with reduced
1688 * live intervals and better dead code elimination and coalescing.
1691 fs_visitor::split_virtual_grfs()
1693 int num_vars
= this->alloc
.count
;
1695 /* Count the total number of registers */
1697 int vgrf_to_reg
[num_vars
];
1698 for (int i
= 0; i
< num_vars
; i
++) {
1699 vgrf_to_reg
[i
] = reg_count
;
1700 reg_count
+= alloc
.sizes
[i
];
1703 /* An array of "split points". For each register slot, this indicates
1704 * if this slot can be separated from the previous slot. Every time an
1705 * instruction uses multiple elements of a register (as a source or
1706 * destination), we mark the used slots as inseparable. Then we go
1707 * through and split the registers into the smallest pieces we can.
1709 bool split_points
[reg_count
];
1710 memset(split_points
, 0, sizeof(split_points
));
1712 /* Mark all used registers as fully splittable */
1713 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1714 if (inst
->dst
.file
== GRF
) {
1715 int reg
= vgrf_to_reg
[inst
->dst
.reg
];
1716 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.reg
]; j
++)
1717 split_points
[reg
+ j
] = true;
1720 for (int i
= 0; i
< inst
->sources
; i
++) {
1721 if (inst
->src
[i
].file
== GRF
) {
1722 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
];
1723 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].reg
]; j
++)
1724 split_points
[reg
+ j
] = true;
1729 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1730 if (inst
->dst
.file
== GRF
) {
1731 int reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1732 for (int j
= 1; j
< inst
->regs_written
; j
++)
1733 split_points
[reg
+ j
] = false;
1735 for (int i
= 0; i
< inst
->sources
; i
++) {
1736 if (inst
->src
[i
].file
== GRF
) {
1737 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1738 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1739 split_points
[reg
+ j
] = false;
1744 int new_virtual_grf
[reg_count
];
1745 int new_reg_offset
[reg_count
];
1748 for (int i
= 0; i
< num_vars
; i
++) {
1749 /* The first one should always be 0 as a quick sanity check. */
1750 assert(split_points
[reg
] == false);
1753 new_reg_offset
[reg
] = 0;
1758 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1759 /* If this is a split point, reset the offset to 0 and allocate a
1760 * new virtual GRF for the previous offset many registers
1762 if (split_points
[reg
]) {
1763 assert(offset
<= MAX_VGRF_SIZE
);
1764 int grf
= alloc
.allocate(offset
);
1765 for (int k
= reg
- offset
; k
< reg
; k
++)
1766 new_virtual_grf
[k
] = grf
;
1769 new_reg_offset
[reg
] = offset
;
1774 /* The last one gets the original register number */
1775 assert(offset
<= MAX_VGRF_SIZE
);
1776 alloc
.sizes
[i
] = offset
;
1777 for (int k
= reg
- offset
; k
< reg
; k
++)
1778 new_virtual_grf
[k
] = i
;
1780 assert(reg
== reg_count
);
1782 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1783 if (inst
->dst
.file
== GRF
) {
1784 reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1785 inst
->dst
.reg
= new_virtual_grf
[reg
];
1786 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1787 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1789 for (int i
= 0; i
< inst
->sources
; i
++) {
1790 if (inst
->src
[i
].file
== GRF
) {
1791 reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1792 inst
->src
[i
].reg
= new_virtual_grf
[reg
];
1793 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1794 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1798 invalidate_live_intervals();
1802 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1804 * During code generation, we create tons of temporary variables, many of
1805 * which get immediately killed and are never used again. Yet, in later
1806 * optimization and analysis passes, such as compute_live_intervals, we need
1807 * to loop over all the virtual GRFs. Compacting them can save a lot of
1811 fs_visitor::compact_virtual_grfs()
1813 bool progress
= false;
1814 int remap_table
[this->alloc
.count
];
1815 memset(remap_table
, -1, sizeof(remap_table
));
1817 /* Mark which virtual GRFs are used. */
1818 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1819 if (inst
->dst
.file
== GRF
)
1820 remap_table
[inst
->dst
.reg
] = 0;
1822 for (int i
= 0; i
< inst
->sources
; i
++) {
1823 if (inst
->src
[i
].file
== GRF
)
1824 remap_table
[inst
->src
[i
].reg
] = 0;
1828 /* Compact the GRF arrays. */
1830 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1831 if (remap_table
[i
] == -1) {
1832 /* We just found an unused register. This means that we are
1833 * actually going to compact something.
1837 remap_table
[i
] = new_index
;
1838 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1839 invalidate_live_intervals();
1844 this->alloc
.count
= new_index
;
1846 /* Patch all the instructions to use the newly renumbered registers */
1847 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1848 if (inst
->dst
.file
== GRF
)
1849 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1851 for (int i
= 0; i
< inst
->sources
; i
++) {
1852 if (inst
->src
[i
].file
== GRF
)
1853 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1857 /* Patch all the references to delta_xy, since they're used in register
1858 * allocation. If they're unused, switch them to BAD_FILE so we don't
1859 * think some random VGRF is delta_xy.
1861 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1862 if (delta_xy
[i
].file
== GRF
) {
1863 if (remap_table
[delta_xy
[i
].reg
] != -1) {
1864 delta_xy
[i
].reg
= remap_table
[delta_xy
[i
].reg
];
1866 delta_xy
[i
].file
= BAD_FILE
;
1875 * Assign UNIFORM file registers to either push constants or pull constants.
1877 * We allow a fragment shader to have more than the specified minimum
1878 * maximum number of fragment shader uniform components (64). If
1879 * there are too many of these, they'd fill up all of register space.
1880 * So, this will push some of them out to the pull constant buffer and
1881 * update the program to load them. We also use pull constants for all
1882 * indirect constant loads because we don't support indirect accesses in
1886 fs_visitor::assign_constant_locations()
1888 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1889 if (dispatch_width
!= 8)
1892 unsigned int num_pull_constants
= 0;
1894 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1895 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1897 bool is_live
[uniforms
];
1898 memset(is_live
, 0, sizeof(is_live
));
1900 /* First, we walk through the instructions and do two things:
1902 * 1) Figure out which uniforms are live.
1904 * 2) Find all indirect access of uniform arrays and flag them as needing
1905 * to go into the pull constant buffer.
1907 * Note that we don't move constant-indexed accesses to arrays. No
1908 * testing has been done of the performance impact of this choice.
1910 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1911 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1912 if (inst
->src
[i
].file
!= UNIFORM
)
1915 if (inst
->src
[i
].reladdr
) {
1916 int uniform
= inst
->src
[i
].reg
;
1918 /* If this array isn't already present in the pull constant buffer,
1921 if (pull_constant_loc
[uniform
] == -1) {
1922 assert(param_size
[uniform
]);
1923 for (int j
= 0; j
< param_size
[uniform
]; j
++)
1924 pull_constant_loc
[uniform
+ j
] = num_pull_constants
++;
1927 /* Mark the the one accessed uniform as live */
1928 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1929 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1930 is_live
[constant_nr
] = true;
1935 /* Only allow 16 registers (128 uniform components) as push constants.
1937 * Just demote the end of the list. We could probably do better
1938 * here, demoting things that are rarely used in the program first.
1940 * If changing this value, note the limitation about total_regs in
1943 unsigned int max_push_components
= 16 * 8;
1944 unsigned int num_push_constants
= 0;
1946 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1948 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1949 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1950 /* This UNIFORM register is either dead, or has already been demoted
1951 * to a pull const. Mark it as no longer living in the param[] array.
1953 push_constant_loc
[i
] = -1;
1957 if (num_push_constants
< max_push_components
) {
1958 /* Retain as a push constant. Record the location in the params[]
1961 push_constant_loc
[i
] = num_push_constants
++;
1963 /* Demote to a pull constant. */
1964 push_constant_loc
[i
] = -1;
1965 pull_constant_loc
[i
] = num_pull_constants
++;
1969 stage_prog_data
->nr_params
= num_push_constants
;
1970 stage_prog_data
->nr_pull_params
= num_pull_constants
;
1972 /* Up until now, the param[] array has been indexed by reg + reg_offset
1973 * of UNIFORM registers. Move pull constants into pull_param[] and
1974 * condense param[] to only contain the uniforms we chose to push.
1976 * NOTE: Because we are condensing the params[] array, we know that
1977 * push_constant_loc[i] <= i and we can do it in one smooth loop without
1978 * having to make a copy.
1980 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1981 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
1983 if (pull_constant_loc
[i
] != -1) {
1984 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
1985 } else if (push_constant_loc
[i
] != -1) {
1986 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
1992 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
1993 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
1996 fs_visitor::demote_pull_constants()
1998 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1999 for (int i
= 0; i
< inst
->sources
; i
++) {
2000 if (inst
->src
[i
].file
!= UNIFORM
)
2004 unsigned location
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
2005 if (location
>= uniforms
) /* Out of bounds access */
2008 pull_index
= pull_constant_loc
[location
];
2010 if (pull_index
== -1)
2013 /* Set up the annotation tracking for new generated instructions. */
2014 const fs_builder
ibld(this, block
, inst
);
2015 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2016 fs_reg dst
= vgrf(glsl_type::float_type
);
2018 assert(inst
->src
[i
].stride
== 0);
2020 /* Generate a pull load into dst. */
2021 if (inst
->src
[i
].reladdr
) {
2022 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
2024 *inst
->src
[i
].reladdr
,
2026 inst
->src
[i
].reladdr
= NULL
;
2027 inst
->src
[i
].stride
= 1;
2028 brw_mark_surface_used(prog_data
, index
);
2030 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2031 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
2032 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2033 dst
, fs_reg(index
), offset
);
2034 inst
->src
[i
].set_smear(pull_index
& 3);
2037 /* Rewrite the instruction to use the temporary VGRF. */
2038 inst
->src
[i
].file
= GRF
;
2039 inst
->src
[i
].reg
= dst
.reg
;
2040 inst
->src
[i
].reg_offset
= 0;
2043 invalidate_live_intervals();
2047 fs_visitor::opt_algebraic()
2049 bool progress
= false;
2051 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2052 switch (inst
->opcode
) {
2053 case BRW_OPCODE_MOV
:
2054 if (inst
->src
[0].file
!= IMM
)
2057 if (inst
->saturate
) {
2058 if (inst
->dst
.type
!= inst
->src
[0].type
)
2059 assert(!"unimplemented: saturate mixed types");
2061 if (brw_saturate_immediate(inst
->dst
.type
,
2062 &inst
->src
[0].fixed_hw_reg
)) {
2063 inst
->saturate
= false;
2069 case BRW_OPCODE_MUL
:
2070 if (inst
->src
[1].file
!= IMM
)
2074 if (inst
->src
[1].is_one()) {
2075 inst
->opcode
= BRW_OPCODE_MOV
;
2076 inst
->src
[1] = reg_undef
;
2082 if (inst
->src
[1].is_negative_one()) {
2083 inst
->opcode
= BRW_OPCODE_MOV
;
2084 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2085 inst
->src
[1] = reg_undef
;
2091 if (inst
->src
[1].is_zero()) {
2092 inst
->opcode
= BRW_OPCODE_MOV
;
2093 inst
->src
[0] = inst
->src
[1];
2094 inst
->src
[1] = reg_undef
;
2099 if (inst
->src
[0].file
== IMM
) {
2100 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2101 inst
->opcode
= BRW_OPCODE_MOV
;
2102 inst
->src
[0].fixed_hw_reg
.dw1
.f
*= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2103 inst
->src
[1] = reg_undef
;
2108 case BRW_OPCODE_ADD
:
2109 if (inst
->src
[1].file
!= IMM
)
2113 if (inst
->src
[1].is_zero()) {
2114 inst
->opcode
= BRW_OPCODE_MOV
;
2115 inst
->src
[1] = reg_undef
;
2120 if (inst
->src
[0].file
== IMM
) {
2121 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2122 inst
->opcode
= BRW_OPCODE_MOV
;
2123 inst
->src
[0].fixed_hw_reg
.dw1
.f
+= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2124 inst
->src
[1] = reg_undef
;
2130 if (inst
->src
[0].equals(inst
->src
[1])) {
2131 inst
->opcode
= BRW_OPCODE_MOV
;
2132 inst
->src
[1] = reg_undef
;
2137 case BRW_OPCODE_LRP
:
2138 if (inst
->src
[1].equals(inst
->src
[2])) {
2139 inst
->opcode
= BRW_OPCODE_MOV
;
2140 inst
->src
[0] = inst
->src
[1];
2141 inst
->src
[1] = reg_undef
;
2142 inst
->src
[2] = reg_undef
;
2147 case BRW_OPCODE_CMP
:
2148 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2150 inst
->src
[0].negate
&&
2151 inst
->src
[1].is_zero()) {
2152 inst
->src
[0].abs
= false;
2153 inst
->src
[0].negate
= false;
2154 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2159 case BRW_OPCODE_SEL
:
2160 if (inst
->src
[0].equals(inst
->src
[1])) {
2161 inst
->opcode
= BRW_OPCODE_MOV
;
2162 inst
->src
[1] = reg_undef
;
2163 inst
->predicate
= BRW_PREDICATE_NONE
;
2164 inst
->predicate_inverse
= false;
2166 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2167 switch (inst
->conditional_mod
) {
2168 case BRW_CONDITIONAL_LE
:
2169 case BRW_CONDITIONAL_L
:
2170 switch (inst
->src
[1].type
) {
2171 case BRW_REGISTER_TYPE_F
:
2172 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
>= 1.0f
) {
2173 inst
->opcode
= BRW_OPCODE_MOV
;
2174 inst
->src
[1] = reg_undef
;
2175 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2183 case BRW_CONDITIONAL_GE
:
2184 case BRW_CONDITIONAL_G
:
2185 switch (inst
->src
[1].type
) {
2186 case BRW_REGISTER_TYPE_F
:
2187 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
<= 0.0f
) {
2188 inst
->opcode
= BRW_OPCODE_MOV
;
2189 inst
->src
[1] = reg_undef
;
2190 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2202 case BRW_OPCODE_MAD
:
2203 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2204 inst
->opcode
= BRW_OPCODE_MOV
;
2205 inst
->src
[1] = reg_undef
;
2206 inst
->src
[2] = reg_undef
;
2208 } else if (inst
->src
[0].is_zero()) {
2209 inst
->opcode
= BRW_OPCODE_MUL
;
2210 inst
->src
[0] = inst
->src
[2];
2211 inst
->src
[2] = reg_undef
;
2213 } else if (inst
->src
[1].is_one()) {
2214 inst
->opcode
= BRW_OPCODE_ADD
;
2215 inst
->src
[1] = inst
->src
[2];
2216 inst
->src
[2] = reg_undef
;
2218 } else if (inst
->src
[2].is_one()) {
2219 inst
->opcode
= BRW_OPCODE_ADD
;
2220 inst
->src
[2] = reg_undef
;
2222 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2223 inst
->opcode
= BRW_OPCODE_ADD
;
2224 inst
->src
[1].fixed_hw_reg
.dw1
.f
*= inst
->src
[2].fixed_hw_reg
.dw1
.f
;
2225 inst
->src
[2] = reg_undef
;
2229 case SHADER_OPCODE_RCP
: {
2230 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2231 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2232 if (inst
->src
[0].equals(prev
->dst
)) {
2233 inst
->opcode
= SHADER_OPCODE_RSQ
;
2234 inst
->src
[0] = prev
->src
[0];
2240 case SHADER_OPCODE_BROADCAST
:
2241 if (is_uniform(inst
->src
[0])) {
2242 inst
->opcode
= BRW_OPCODE_MOV
;
2244 inst
->force_writemask_all
= true;
2246 } else if (inst
->src
[1].file
== IMM
) {
2247 inst
->opcode
= BRW_OPCODE_MOV
;
2248 inst
->src
[0] = component(inst
->src
[0],
2249 inst
->src
[1].fixed_hw_reg
.dw1
.ud
);
2251 inst
->force_writemask_all
= true;
2260 /* Swap if src[0] is immediate. */
2261 if (progress
&& inst
->is_commutative()) {
2262 if (inst
->src
[0].file
== IMM
) {
2263 fs_reg tmp
= inst
->src
[1];
2264 inst
->src
[1] = inst
->src
[0];
2273 * Optimize sample messages that have constant zero values for the trailing
2274 * texture coordinates. We can just reduce the message length for these
2275 * instructions instead of reserving a register for it. Trailing parameters
2276 * that aren't sent default to zero anyway. This will cause the dead code
2277 * eliminator to remove the MOV instruction that would otherwise be emitted to
2278 * set up the zero value.
2281 fs_visitor::opt_zero_samples()
2283 /* Gen4 infers the texturing opcode based on the message length so we can't
2286 if (devinfo
->gen
< 5)
2289 bool progress
= false;
2291 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2292 if (!inst
->is_tex())
2295 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2297 if (load_payload
->is_head_sentinel() ||
2298 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2301 /* We don't want to remove the message header or the first parameter.
2302 * Removing the first parameter is not allowed, see the Haswell PRM
2303 * volume 7, page 149:
2305 * "Parameter 0 is required except for the sampleinfo message, which
2306 * has no parameter 0"
2308 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2309 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2310 (inst
->exec_size
/ 8) +
2311 inst
->header_size
- 1].is_zero()) {
2312 inst
->mlen
-= inst
->exec_size
/ 8;
2318 invalidate_live_intervals();
2324 * Optimize sample messages which are followed by the final RT write.
2326 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2327 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2328 * final texturing results copied to the framebuffer write payload and modify
2329 * them to write to the framebuffer directly.
2332 fs_visitor::opt_sampler_eot()
2334 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2336 if (stage
!= MESA_SHADER_FRAGMENT
)
2339 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2342 /* FINISHME: It should be possible to implement this optimization when there
2343 * are multiple drawbuffers.
2345 if (key
->nr_color_regions
!= 1)
2348 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2349 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2350 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2351 assert(fb_write
->eot
);
2352 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2354 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2356 /* There wasn't one; nothing to do. */
2357 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2360 /* 3D Sampler » Messages » Message Format
2362 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2363 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2365 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2366 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2367 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2368 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2369 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2372 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2373 * It's very likely to be the previous instruction.
2375 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2376 if (load_payload
->is_head_sentinel() ||
2377 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2380 assert(!tex_inst
->eot
); /* We can't get here twice */
2381 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2383 const fs_builder
ibld(this, block
, tex_inst
);
2385 tex_inst
->offset
|= fb_write
->target
<< 24;
2386 tex_inst
->eot
= true;
2387 tex_inst
->dst
= ibld
.null_reg_ud();
2388 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2390 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2391 * to create a new LOAD_PAYLOAD command with the same sources and a space
2392 * saved for the header. Using a new destination register not only makes sure
2393 * we have enough space, but it will make sure the dead code eliminator kills
2394 * the instruction that this will replace.
2396 if (tex_inst
->header_size
!= 0)
2399 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2400 load_payload
->sources
+ 1);
2401 fs_reg
*new_sources
=
2402 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2404 new_sources
[0] = fs_reg();
2405 for (int i
= 0; i
< load_payload
->sources
; i
++)
2406 new_sources
[i
+1] = load_payload
->src
[i
];
2408 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2409 * requires a lot of information about the sources to appropriately figure
2410 * out the number of registers needed to be used. Given this stage in our
2411 * optimization, we may not have the appropriate GRFs required by
2412 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2413 * manually emit the instruction.
2415 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2416 load_payload
->exec_size
,
2419 load_payload
->sources
+ 1);
2421 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2422 new_load_payload
->header_size
= 1;
2424 tex_inst
->header_size
= 1;
2425 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2426 tex_inst
->src
[0] = send_header
;
2432 fs_visitor::opt_register_renaming()
2434 bool progress
= false;
2437 int remap
[alloc
.count
];
2438 memset(remap
, -1, sizeof(int) * alloc
.count
);
2440 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2441 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2443 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2444 inst
->opcode
== BRW_OPCODE_WHILE
) {
2448 /* Rewrite instruction sources. */
2449 for (int i
= 0; i
< inst
->sources
; i
++) {
2450 if (inst
->src
[i
].file
== GRF
&&
2451 remap
[inst
->src
[i
].reg
] != -1 &&
2452 remap
[inst
->src
[i
].reg
] != inst
->src
[i
].reg
) {
2453 inst
->src
[i
].reg
= remap
[inst
->src
[i
].reg
];
2458 const int dst
= inst
->dst
.reg
;
2461 inst
->dst
.file
== GRF
&&
2462 alloc
.sizes
[inst
->dst
.reg
] == inst
->exec_size
/ 8 &&
2463 !inst
->is_partial_write()) {
2464 if (remap
[dst
] == -1) {
2467 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2468 inst
->dst
.reg
= remap
[dst
];
2471 } else if (inst
->dst
.file
== GRF
&&
2473 remap
[dst
] != dst
) {
2474 inst
->dst
.reg
= remap
[dst
];
2480 invalidate_live_intervals();
2482 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2483 if (delta_xy
[i
].file
== GRF
&& remap
[delta_xy
[i
].reg
] != -1) {
2484 delta_xy
[i
].reg
= remap
[delta_xy
[i
].reg
];
2493 * Remove redundant or useless discard jumps.
2495 * For example, we can eliminate jumps in the following sequence:
2497 * discard-jump (redundant with the next jump)
2498 * discard-jump (useless; jumps to the next instruction)
2502 fs_visitor::opt_redundant_discard_jumps()
2504 bool progress
= false;
2506 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2508 fs_inst
*placeholder_halt
= NULL
;
2509 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2510 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2511 placeholder_halt
= inst
;
2516 if (!placeholder_halt
)
2519 /* Delete any HALTs immediately before the placeholder halt. */
2520 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2521 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2522 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2523 prev
->remove(last_bblock
);
2528 invalidate_live_intervals();
2534 fs_visitor::compute_to_mrf()
2536 bool progress
= false;
2539 /* No MRFs on Gen >= 7. */
2540 if (devinfo
->gen
>= 7)
2543 calculate_live_intervals();
2545 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2549 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2550 inst
->is_partial_write() ||
2551 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2552 inst
->dst
.type
!= inst
->src
[0].type
||
2553 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2554 !inst
->src
[0].is_contiguous() ||
2555 inst
->src
[0].subreg_offset
)
2558 /* Work out which hardware MRF registers are written by this
2561 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2563 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2564 mrf_high
= mrf_low
+ 4;
2565 } else if (inst
->exec_size
== 16) {
2566 mrf_high
= mrf_low
+ 1;
2571 /* Can't compute-to-MRF this GRF if someone else was going to
2574 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2577 /* Found a move of a GRF to a MRF. Let's see if we can go
2578 * rewrite the thing that made this GRF to write into the MRF.
2580 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2581 if (scan_inst
->dst
.file
== GRF
&&
2582 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2583 /* Found the last thing to write our reg we want to turn
2584 * into a compute-to-MRF.
2587 /* If this one instruction didn't populate all the
2588 * channels, bail. We might be able to rewrite everything
2589 * that writes that reg, but it would require smarter
2590 * tracking to delay the rewriting until complete success.
2592 if (scan_inst
->is_partial_write())
2595 /* Things returning more than one register would need us to
2596 * understand coalescing out more than one MOV at a time.
2598 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2601 /* SEND instructions can't have MRF as a destination. */
2602 if (scan_inst
->mlen
)
2605 if (devinfo
->gen
== 6) {
2606 /* gen6 math instructions must have the destination be
2607 * GRF, so no compute-to-MRF for them.
2609 if (scan_inst
->is_math()) {
2614 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2615 /* Found the creator of our MRF's source value. */
2616 scan_inst
->dst
.file
= MRF
;
2617 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2618 scan_inst
->saturate
|= inst
->saturate
;
2619 inst
->remove(block
);
2625 /* We don't handle control flow here. Most computation of
2626 * values that end up in MRFs are shortly before the MRF
2629 if (block
->start() == scan_inst
)
2632 /* You can't read from an MRF, so if someone else reads our
2633 * MRF's source GRF that we wanted to rewrite, that stops us.
2635 bool interfered
= false;
2636 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2637 if (scan_inst
->src
[i
].file
== GRF
&&
2638 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2639 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2646 if (scan_inst
->dst
.file
== MRF
) {
2647 /* If somebody else writes our MRF here, we can't
2648 * compute-to-MRF before that.
2650 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2653 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2654 scan_mrf_high
= scan_mrf_low
+ 4;
2655 } else if (scan_inst
->exec_size
== 16) {
2656 scan_mrf_high
= scan_mrf_low
+ 1;
2658 scan_mrf_high
= scan_mrf_low
;
2661 if (mrf_low
== scan_mrf_low
||
2662 mrf_low
== scan_mrf_high
||
2663 mrf_high
== scan_mrf_low
||
2664 mrf_high
== scan_mrf_high
) {
2669 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2670 /* Found a SEND instruction, which means that there are
2671 * live values in MRFs from base_mrf to base_mrf +
2672 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2675 if (mrf_low
>= scan_inst
->base_mrf
&&
2676 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2679 if (mrf_high
>= scan_inst
->base_mrf
&&
2680 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2688 invalidate_live_intervals();
2694 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2695 * flow. We could probably do better here with some form of divergence
2699 fs_visitor::eliminate_find_live_channel()
2701 bool progress
= false;
2704 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2705 switch (inst
->opcode
) {
2711 case BRW_OPCODE_ENDIF
:
2712 case BRW_OPCODE_WHILE
:
2716 case FS_OPCODE_DISCARD_JUMP
:
2717 /* This can potentially make control flow non-uniform until the end
2722 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2724 inst
->opcode
= BRW_OPCODE_MOV
;
2725 inst
->src
[0] = fs_reg(0u);
2727 inst
->force_writemask_all
= true;
2741 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2742 * instructions to FS_OPCODE_REP_FB_WRITE.
2745 fs_visitor::emit_repclear_shader()
2747 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2749 int color_mrf
= base_mrf
+ 2;
2751 fs_inst
*mov
= bld
.exec_all().group(4, 0)
2752 .MOV(brw_message_reg(color_mrf
),
2753 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2756 if (key
->nr_color_regions
== 1) {
2757 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2758 write
->saturate
= key
->clamp_fragment_color
;
2759 write
->base_mrf
= color_mrf
;
2761 write
->header_size
= 0;
2764 assume(key
->nr_color_regions
> 0);
2765 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2766 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2767 write
->saturate
= key
->clamp_fragment_color
;
2768 write
->base_mrf
= base_mrf
;
2770 write
->header_size
= 2;
2778 assign_constant_locations();
2779 assign_curb_setup();
2781 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2782 assert(mov
->src
[0].file
== HW_REG
);
2783 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].fixed_hw_reg
.nr
, 0);
2787 * Walks through basic blocks, looking for repeated MRF writes and
2788 * removing the later ones.
2791 fs_visitor::remove_duplicate_mrf_writes()
2793 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2794 bool progress
= false;
2796 /* Need to update the MRF tracking for compressed instructions. */
2797 if (dispatch_width
== 16)
2800 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2802 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2803 if (inst
->is_control_flow()) {
2804 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2807 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2808 inst
->dst
.file
== MRF
) {
2809 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2810 if (prev_inst
&& inst
->equals(prev_inst
)) {
2811 inst
->remove(block
);
2817 /* Clear out the last-write records for MRFs that were overwritten. */
2818 if (inst
->dst
.file
== MRF
) {
2819 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2822 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2823 /* Found a SEND instruction, which will include two or fewer
2824 * implied MRF writes. We could do better here.
2826 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2827 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2831 /* Clear out any MRF move records whose sources got overwritten. */
2832 if (inst
->dst
.file
== GRF
) {
2833 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2834 if (last_mrf_move
[i
] &&
2835 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2836 last_mrf_move
[i
] = NULL
;
2841 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2842 inst
->dst
.file
== MRF
&&
2843 inst
->src
[0].file
== GRF
&&
2844 !inst
->is_partial_write()) {
2845 last_mrf_move
[inst
->dst
.reg
] = inst
;
2850 invalidate_live_intervals();
2856 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2858 /* Clear the flag for registers that actually got read (as expected). */
2859 for (int i
= 0; i
< inst
->sources
; i
++) {
2861 if (inst
->src
[i
].file
== GRF
) {
2862 grf
= inst
->src
[i
].reg
;
2863 } else if (inst
->src
[i
].file
== HW_REG
&&
2864 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2865 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2870 if (grf
>= first_grf
&&
2871 grf
< first_grf
+ grf_len
) {
2872 deps
[grf
- first_grf
] = false;
2873 if (inst
->exec_size
== 16)
2874 deps
[grf
- first_grf
+ 1] = false;
2880 * Implements this workaround for the original 965:
2882 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2883 * check for post destination dependencies on this instruction, software
2884 * must ensure that there is no destination hazard for the case of ‘write
2885 * followed by a posted write’ shown in the following example.
2888 * 2. send r3.xy <rest of send instruction>
2891 * Due to no post-destination dependency check on the ‘send’, the above
2892 * code sequence could have two instructions (1 and 2) in flight at the
2893 * same time that both consider ‘r3’ as the target of their final writes.
2896 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2899 int write_len
= inst
->regs_written
;
2900 int first_write_grf
= inst
->dst
.reg
;
2901 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2902 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2904 memset(needs_dep
, false, sizeof(needs_dep
));
2905 memset(needs_dep
, true, write_len
);
2907 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2909 /* Walk backwards looking for writes to registers we're writing which
2910 * aren't read since being written. If we hit the start of the program,
2911 * we assume that there are no outstanding dependencies on entry to the
2914 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2915 /* If we hit control flow, assume that there *are* outstanding
2916 * dependencies, and force their cleanup before our instruction.
2918 if (block
->start() == scan_inst
) {
2919 for (int i
= 0; i
< write_len
; i
++) {
2921 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
2922 first_write_grf
+ i
);
2927 /* We insert our reads as late as possible on the assumption that any
2928 * instruction but a MOV that might have left us an outstanding
2929 * dependency has more latency than a MOV.
2931 if (scan_inst
->dst
.file
== GRF
) {
2932 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2933 int reg
= scan_inst
->dst
.reg
+ i
;
2935 if (reg
>= first_write_grf
&&
2936 reg
< first_write_grf
+ write_len
&&
2937 needs_dep
[reg
- first_write_grf
]) {
2938 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
2939 needs_dep
[reg
- first_write_grf
] = false;
2940 if (scan_inst
->exec_size
== 16)
2941 needs_dep
[reg
- first_write_grf
+ 1] = false;
2946 /* Clear the flag for registers that actually got read (as expected). */
2947 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2949 /* Continue the loop only if we haven't resolved all the dependencies */
2951 for (i
= 0; i
< write_len
; i
++) {
2961 * Implements this workaround for the original 965:
2963 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2964 * used as a destination register until after it has been sourced by an
2965 * instruction with a different destination register.
2968 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2970 int write_len
= inst
->regs_written
;
2971 int first_write_grf
= inst
->dst
.reg
;
2972 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2973 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2975 memset(needs_dep
, false, sizeof(needs_dep
));
2976 memset(needs_dep
, true, write_len
);
2977 /* Walk forwards looking for writes to registers we're writing which aren't
2978 * read before being written.
2980 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
2981 /* If we hit control flow, force resolve all remaining dependencies. */
2982 if (block
->end() == scan_inst
) {
2983 for (int i
= 0; i
< write_len
; i
++) {
2985 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2986 first_write_grf
+ i
);
2991 /* Clear the flag for registers that actually got read (as expected). */
2992 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2994 /* We insert our reads as late as possible since they're reading the
2995 * result of a SEND, which has massive latency.
2997 if (scan_inst
->dst
.file
== GRF
&&
2998 scan_inst
->dst
.reg
>= first_write_grf
&&
2999 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
3000 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
3001 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3002 scan_inst
->dst
.reg
);
3003 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
3006 /* Continue the loop only if we haven't resolved all the dependencies */
3008 for (i
= 0; i
< write_len
; i
++) {
3018 fs_visitor::insert_gen4_send_dependency_workarounds()
3020 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3023 bool progress
= false;
3025 /* Note that we're done with register allocation, so GRF fs_regs always
3026 * have a .reg_offset of 0.
3029 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3030 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
3031 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3032 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3038 invalidate_live_intervals();
3042 * Turns the generic expression-style uniform pull constant load instruction
3043 * into a hardware-specific series of instructions for loading a pull
3046 * The expression style allows the CSE pass before this to optimize out
3047 * repeated loads from the same offset, and gives the pre-register-allocation
3048 * scheduling full flexibility, while the conversion to native instructions
3049 * allows the post-register-allocation scheduler the best information
3052 * Note that execution masking for setting up pull constant loads is special:
3053 * the channels that need to be written are unrelated to the current execution
3054 * mask, since a later instruction will use one of the result channels as a
3055 * source operand for all 8 or 16 of its channels.
3058 fs_visitor::lower_uniform_pull_constant_loads()
3060 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3061 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3064 if (devinfo
->gen
>= 7) {
3065 /* The offset arg before was a vec4-aligned byte offset. We need to
3066 * turn it into a dword offset.
3068 fs_reg const_offset_reg
= inst
->src
[1];
3069 assert(const_offset_reg
.file
== IMM
&&
3070 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3071 const_offset_reg
.fixed_hw_reg
.dw1
.ud
/= 4;
3073 fs_reg payload
, offset
;
3074 if (devinfo
->gen
>= 9) {
3075 /* We have to use a message header on Skylake to get SIMD4x2
3076 * mode. Reserve space for the register.
3078 offset
= payload
= fs_reg(GRF
, alloc
.allocate(2));
3079 offset
.reg_offset
++;
3082 offset
= payload
= fs_reg(GRF
, alloc
.allocate(1));
3086 /* This is actually going to be a MOV, but since only the first dword
3087 * is accessed, we have a special opcode to do just that one. Note
3088 * that this needs to be an operation that will be considered a def
3089 * by live variable analysis, or register allocation will explode.
3091 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3092 8, offset
, const_offset_reg
);
3093 setup
->force_writemask_all
= true;
3095 setup
->ir
= inst
->ir
;
3096 setup
->annotation
= inst
->annotation
;
3097 inst
->insert_before(block
, setup
);
3099 /* Similarly, this will only populate the first 4 channels of the
3100 * result register (since we only use smear values from 0-3), but we
3101 * don't tell the optimizer.
3103 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3104 inst
->src
[1] = payload
;
3105 inst
->base_mrf
= -1;
3107 invalidate_live_intervals();
3109 /* Before register allocation, we didn't tell the scheduler about the
3110 * MRF we use. We know it's safe to use this MRF because nothing
3111 * else does except for register spill/unspill, which generates and
3112 * uses its MRF within a single IR instruction.
3114 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3121 fs_visitor::lower_load_payload()
3123 bool progress
= false;
3125 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3126 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3129 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== GRF
);
3130 assert(inst
->saturate
== false);
3131 fs_reg dst
= inst
->dst
;
3133 /* Get rid of COMPR4. We'll add it back in if we need it */
3134 if (dst
.file
== MRF
)
3135 dst
.reg
= dst
.reg
& ~BRW_MRF_COMPR4
;
3137 const fs_builder
ibld(this, block
, inst
);
3138 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3140 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3141 if (inst
->src
[i
].file
!= BAD_FILE
) {
3142 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3143 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3144 hbld
.MOV(mov_dst
, mov_src
);
3146 dst
= offset(dst
, hbld
, 1);
3149 if (inst
->dst
.file
== MRF
&& (inst
->dst
.reg
& BRW_MRF_COMPR4
) &&
3150 inst
->exec_size
> 8) {
3151 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3152 * a straightforward copy. Instead, the result of the
3153 * LOAD_PAYLOAD is treated as interleaved and the first four
3154 * non-header sources are unpacked as:
3165 * This is used for gen <= 5 fb writes.
3167 assert(inst
->exec_size
== 16);
3168 assert(inst
->header_size
+ 4 <= inst
->sources
);
3169 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3170 if (inst
->src
[i
].file
!= BAD_FILE
) {
3171 if (devinfo
->has_compr4
) {
3172 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3173 compr4_dst
.reg
|= BRW_MRF_COMPR4
;
3174 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3176 /* Platform doesn't have COMPR4. We have to fake it */
3177 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3178 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3180 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3187 /* The loop above only ever incremented us through the first set
3188 * of 4 registers. However, thanks to the magic of COMPR4, we
3189 * actually wrote to the first 8 registers, so we need to take
3190 * that into account now.
3194 /* The COMPR4 code took care of the first 4 sources. We'll let
3195 * the regular path handle any remaining sources. Yes, we are
3196 * modifying the instruction but we're about to delete it so
3197 * this really doesn't hurt anything.
3199 inst
->header_size
+= 4;
3202 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3203 if (inst
->src
[i
].file
!= BAD_FILE
)
3204 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3205 dst
= offset(dst
, ibld
, 1);
3208 inst
->remove(block
);
3213 invalidate_live_intervals();
3219 fs_visitor::lower_integer_multiplication()
3221 bool progress
= false;
3223 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3224 const fs_builder
ibld(this, block
, inst
);
3226 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3227 if (inst
->dst
.is_accumulator() ||
3228 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3229 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3232 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3233 * operation directly, but CHV/BXT cannot.
3235 if (devinfo
->gen
>= 8 &&
3236 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3239 if (inst
->src
[1].file
== IMM
&&
3240 inst
->src
[1].fixed_hw_reg
.dw1
.ud
< (1 << 16)) {
3241 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3242 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3245 * If multiplying by an immediate value that fits in 16-bits, do a
3246 * single MUL instruction with that value in the proper location.
3248 if (devinfo
->gen
< 7) {
3249 fs_reg
imm(GRF
, alloc
.allocate(dispatch_width
/ 8),
3251 ibld
.MOV(imm
, inst
->src
[1]);
3252 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3254 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3257 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3258 * do 32-bit integer multiplication in one instruction, but instead
3259 * must do a sequence (which actually calculates a 64-bit result):
3261 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3262 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3263 * mov(8) g2<1>D acc0<8,8,1>D
3265 * But on Gen > 6, the ability to use second accumulator register
3266 * (acc1) for non-float data types was removed, preventing a simple
3267 * implementation in SIMD16. A 16-channel result can be calculated by
3268 * executing the three instructions twice in SIMD8, once with quarter
3269 * control of 1Q for the first eight channels and again with 2Q for
3270 * the second eight channels.
3272 * Which accumulator register is implicitly accessed (by AccWrEnable
3273 * for instance) is determined by the quarter control. Unfortunately
3274 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3275 * implicit accumulator access by an instruction with 2Q will access
3276 * acc1 regardless of whether the data type is usable in acc1.
3278 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3279 * integer data types.
3281 * Since we only want the low 32-bits of the result, we can do two
3282 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3283 * adjust the high result and add them (like the mach is doing):
3285 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3286 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3287 * shl(8) g9<1>D g8<8,8,1>D 16D
3288 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3290 * We avoid the shl instruction by realizing that we only want to add
3291 * the low 16-bits of the "high" result to the high 16-bits of the
3292 * "low" result and using proper regioning on the add:
3294 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3295 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3296 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3298 * Since it does not use the (single) accumulator register, we can
3299 * schedule multi-component multiplications much better.
3302 fs_reg orig_dst
= inst
->dst
;
3303 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3304 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
3307 fs_reg low
= inst
->dst
;
3308 fs_reg
high(GRF
, alloc
.allocate(dispatch_width
/ 8),
3311 if (devinfo
->gen
>= 7) {
3312 fs_reg src1_0_w
= inst
->src
[1];
3313 fs_reg src1_1_w
= inst
->src
[1];
3315 if (inst
->src
[1].file
== IMM
) {
3316 src1_0_w
.fixed_hw_reg
.dw1
.ud
&= 0xffff;
3317 src1_1_w
.fixed_hw_reg
.dw1
.ud
>>= 16;
3319 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3320 if (src1_0_w
.stride
!= 0) {
3321 assert(src1_0_w
.stride
== 1);
3322 src1_0_w
.stride
= 2;
3325 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3326 if (src1_1_w
.stride
!= 0) {
3327 assert(src1_1_w
.stride
== 1);
3328 src1_1_w
.stride
= 2;
3330 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3332 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3333 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3335 fs_reg src0_0_w
= inst
->src
[0];
3336 fs_reg src0_1_w
= inst
->src
[0];
3338 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3339 if (src0_0_w
.stride
!= 0) {
3340 assert(src0_0_w
.stride
== 1);
3341 src0_0_w
.stride
= 2;
3344 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3345 if (src0_1_w
.stride
!= 0) {
3346 assert(src0_1_w
.stride
== 1);
3347 src0_1_w
.stride
= 2;
3349 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3351 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3352 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3355 fs_reg dst
= inst
->dst
;
3356 dst
.type
= BRW_REGISTER_TYPE_UW
;
3357 dst
.subreg_offset
= 2;
3360 high
.type
= BRW_REGISTER_TYPE_UW
;
3363 low
.type
= BRW_REGISTER_TYPE_UW
;
3364 low
.subreg_offset
= 2;
3367 ibld
.ADD(dst
, low
, high
);
3369 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3370 set_condmod(inst
->conditional_mod
,
3371 ibld
.MOV(orig_dst
, inst
->dst
));
3375 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3376 /* Should have been lowered to 8-wide. */
3377 assert(inst
->exec_size
<= 8);
3378 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3380 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3381 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3383 if (devinfo
->gen
>= 8) {
3384 /* Until Gen8, integer multiplies read 32-bits from one source,
3385 * and 16-bits from the other, and relying on the MACH instruction
3386 * to generate the high bits of the result.
3388 * On Gen8, the multiply instruction does a full 32x32-bit
3389 * multiply, but in order to do a 64-bit multiply we can simulate
3390 * the previous behavior and then use a MACH instruction.
3392 * FINISHME: Don't use source modifiers on src1.
3394 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3395 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3396 mul
->src
[1].type
= (type_is_signed(mul
->src
[1].type
) ?
3397 BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
3398 mul
->src
[1].stride
*= 2;
3400 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3401 inst
->force_sechalf
) {
3402 /* Among other things the quarter control bits influence which
3403 * accumulator register is used by the hardware for instructions
3404 * that access the accumulator implicitly (e.g. MACH). A
3405 * second-half instruction would normally map to acc1, which
3406 * doesn't exist on Gen7 and up (the hardware does emulate it for
3407 * floating-point instructions *only* by taking advantage of the
3408 * extra precision of acc0 not normally used for floating point
3411 * HSW and up are careful enough not to try to access an
3412 * accumulator register that doesn't exist, but on earlier Gen7
3413 * hardware we need to make sure that the quarter control bits are
3414 * zero to avoid non-deterministic behaviour and emit an extra MOV
3415 * to get the result masked correctly according to the current
3418 mach
->force_sechalf
= false;
3419 mach
->force_writemask_all
= true;
3420 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3421 ibld
.MOV(inst
->dst
, mach
->dst
);
3427 inst
->remove(block
);
3432 invalidate_live_intervals();
3438 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3439 fs_reg
*dst
, fs_reg color
, unsigned components
)
3441 if (key
->clamp_fragment_color
) {
3442 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3443 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3445 for (unsigned i
= 0; i
< components
; i
++)
3447 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3452 for (unsigned i
= 0; i
< components
; i
++)
3453 dst
[i
] = offset(color
, bld
, i
);
3457 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3458 const brw_wm_prog_data
*prog_data
,
3459 const brw_wm_prog_key
*key
,
3460 const fs_visitor::thread_payload
&payload
)
3462 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3463 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3464 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3465 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3466 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3467 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3468 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3469 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3470 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3471 const unsigned components
=
3472 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].fixed_hw_reg
.dw1
.ud
;
3474 /* We can potentially have a message length of up to 15, so we have to set
3475 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3478 int header_size
= 2, payload_header_size
;
3479 unsigned length
= 0;
3481 /* From the Sandy Bridge PRM, volume 4, page 198:
3483 * "Dispatched Pixel Enables. One bit per pixel indicating
3484 * which pixels were originally enabled when the thread was
3485 * dispatched. This field is only required for the end-of-
3486 * thread message and on all dual-source messages."
3488 if (devinfo
->gen
>= 6 &&
3489 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3490 color1
.file
== BAD_FILE
&&
3491 key
->nr_color_regions
== 1) {
3495 if (header_size
!= 0) {
3496 assert(header_size
== 2);
3497 /* Allocate 2 registers for a header */
3501 if (payload
.aa_dest_stencil_reg
) {
3502 sources
[length
] = fs_reg(GRF
, bld
.shader
->alloc
.allocate(1));
3503 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3504 .MOV(sources
[length
],
3505 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3509 if (prog_data
->uses_omask
) {
3510 sources
[length
] = fs_reg(GRF
, bld
.shader
->alloc
.allocate(1),
3511 BRW_REGISTER_TYPE_UD
);
3513 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3514 * relevant. Since it's unsigned single words one vgrf is always
3515 * 16-wide, but only the lower or higher 8 channels will be used by the
3516 * hardware when doing a SIMD8 write depending on whether we have
3517 * selected the subspans for the first or second half respectively.
3519 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3520 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3521 sample_mask
.stride
*= 2;
3523 bld
.exec_all().annotate("FB write oMask")
3524 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3525 inst
->force_sechalf
),
3530 payload_header_size
= length
;
3532 if (src0_alpha
.file
!= BAD_FILE
) {
3533 /* FIXME: This is being passed at the wrong location in the payload and
3534 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3535 * It's supposed to be immediately before oMask but there seems to be no
3536 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3537 * requires header sources to form a contiguous segment at the beginning
3538 * of the message and src0_alpha has per-channel semantics.
3540 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3544 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3547 if (color1
.file
!= BAD_FILE
) {
3548 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3552 if (src_depth
.file
!= BAD_FILE
) {
3553 sources
[length
] = src_depth
;
3557 if (dst_depth
.file
!= BAD_FILE
) {
3558 sources
[length
] = dst_depth
;
3562 if (src_stencil
.file
!= BAD_FILE
) {
3563 assert(devinfo
->gen
>= 9);
3564 assert(bld
.dispatch_width() != 16);
3566 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3567 bld
.exec_all().annotate("FB write OS")
3568 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3569 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3574 if (devinfo
->gen
>= 7) {
3575 /* Send from the GRF */
3576 fs_reg payload
= fs_reg(GRF
, -1, BRW_REGISTER_TYPE_F
);
3577 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3578 payload
.reg
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3579 load
->dst
= payload
;
3581 inst
->src
[0] = payload
;
3582 inst
->resize_sources(1);
3583 inst
->base_mrf
= -1;
3585 /* Send from the MRF */
3586 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3587 sources
, length
, payload_header_size
);
3589 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3590 * will do this for us if we just give it a COMPR4 destination.
3592 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3593 load
->dst
.reg
|= BRW_MRF_COMPR4
;
3595 inst
->resize_sources(0);
3599 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3600 inst
->mlen
= load
->regs_written
;
3601 inst
->header_size
= header_size
;
3605 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3606 const fs_reg
&coordinate
,
3607 const fs_reg
&shadow_c
,
3608 const fs_reg
&lod
, const fs_reg
&lod2
,
3609 const fs_reg
&sampler
,
3610 unsigned coord_components
,
3611 unsigned grad_components
)
3613 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3614 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3615 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3616 fs_reg msg_end
= msg_begin
;
3619 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3621 for (unsigned i
= 0; i
< coord_components
; i
++)
3622 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3623 offset(coordinate
, bld
, i
));
3625 msg_end
= offset(msg_end
, bld
, coord_components
);
3627 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3628 * require all three components to be present and zero if they are unused.
3630 if (coord_components
> 0 &&
3631 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3632 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3633 for (unsigned i
= coord_components
; i
< 3; i
++)
3634 bld
.MOV(offset(msg_end
, bld
, i
), fs_reg(0.0f
));
3636 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3639 if (op
== SHADER_OPCODE_TXD
) {
3640 /* TXD unsupported in SIMD16 mode. */
3641 assert(bld
.dispatch_width() == 8);
3643 /* the slots for u and v are always present, but r is optional */
3644 if (coord_components
< 2)
3645 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3648 * dPdx = dudx, dvdx, drdx
3649 * dPdy = dudy, dvdy, drdy
3651 * 1-arg: Does not exist.
3653 * 2-arg: dudx dvdx dudy dvdy
3654 * dPdx.x dPdx.y dPdy.x dPdy.y
3657 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3658 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3659 * m5 m6 m7 m8 m9 m10
3661 for (unsigned i
= 0; i
< grad_components
; i
++)
3662 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3664 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3666 for (unsigned i
= 0; i
< grad_components
; i
++)
3667 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3669 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3673 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3674 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3676 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3677 bld
.dispatch_width() == 16);
3679 const brw_reg_type type
=
3680 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3681 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3682 bld
.MOV(retype(msg_end
, type
), lod
);
3683 msg_end
= offset(msg_end
, bld
, 1);
3686 if (shadow_c
.file
!= BAD_FILE
) {
3687 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3688 /* There's no plain shadow compare message, so we use shadow
3689 * compare with a bias of 0.0.
3691 bld
.MOV(msg_end
, fs_reg(0.0f
));
3692 msg_end
= offset(msg_end
, bld
, 1);
3695 bld
.MOV(msg_end
, shadow_c
);
3696 msg_end
= offset(msg_end
, bld
, 1);
3700 inst
->src
[0] = reg_undef
;
3701 inst
->src
[1] = sampler
;
3702 inst
->resize_sources(2);
3703 inst
->base_mrf
= msg_begin
.reg
;
3704 inst
->mlen
= msg_end
.reg
- msg_begin
.reg
;
3705 inst
->header_size
= 1;
3709 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3711 const fs_reg
&shadow_c
,
3712 fs_reg lod
, fs_reg lod2
,
3713 const fs_reg
&sample_index
,
3714 const fs_reg
&sampler
,
3715 const fs_reg
&offset_value
,
3716 unsigned coord_components
,
3717 unsigned grad_components
)
3719 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3720 fs_reg msg_coords
= message
;
3721 unsigned header_size
= 0;
3723 if (offset_value
.file
!= BAD_FILE
) {
3724 /* The offsets set up by the visitor are in the m1 header, so we can't
3731 for (unsigned i
= 0; i
< coord_components
; i
++) {
3732 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3733 coordinate
= offset(coordinate
, bld
, 1);
3735 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3736 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3738 if (shadow_c
.file
!= BAD_FILE
) {
3739 fs_reg msg_shadow
= msg_lod
;
3740 bld
.MOV(msg_shadow
, shadow_c
);
3741 msg_lod
= offset(msg_shadow
, bld
, 1);
3746 case SHADER_OPCODE_TXL
:
3748 bld
.MOV(msg_lod
, lod
);
3749 msg_end
= offset(msg_lod
, bld
, 1);
3751 case SHADER_OPCODE_TXD
:
3754 * dPdx = dudx, dvdx, drdx
3755 * dPdy = dudy, dvdy, drdy
3757 * Load up these values:
3758 * - dudx dudy dvdx dvdy drdx drdy
3759 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3762 for (unsigned i
= 0; i
< grad_components
; i
++) {
3763 bld
.MOV(msg_end
, lod
);
3764 lod
= offset(lod
, bld
, 1);
3765 msg_end
= offset(msg_end
, bld
, 1);
3767 bld
.MOV(msg_end
, lod2
);
3768 lod2
= offset(lod2
, bld
, 1);
3769 msg_end
= offset(msg_end
, bld
, 1);
3772 case SHADER_OPCODE_TXS
:
3773 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3774 bld
.MOV(msg_lod
, lod
);
3775 msg_end
= offset(msg_lod
, bld
, 1);
3777 case SHADER_OPCODE_TXF
:
3778 msg_lod
= offset(msg_coords
, bld
, 3);
3779 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3780 msg_end
= offset(msg_lod
, bld
, 1);
3782 case SHADER_OPCODE_TXF_CMS
:
3783 msg_lod
= offset(msg_coords
, bld
, 3);
3785 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
3787 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3788 msg_end
= offset(msg_lod
, bld
, 2);
3795 inst
->src
[0] = reg_undef
;
3796 inst
->src
[1] = sampler
;
3797 inst
->resize_sources(2);
3798 inst
->base_mrf
= message
.reg
;
3799 inst
->mlen
= msg_end
.reg
- message
.reg
;
3800 inst
->header_size
= header_size
;
3802 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3803 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3807 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3809 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3812 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
3816 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3818 const fs_reg
&shadow_c
,
3819 fs_reg lod
, fs_reg lod2
,
3820 const fs_reg
&sample_index
,
3821 const fs_reg
&mcs
, const fs_reg
&sampler
,
3822 fs_reg offset_value
,
3823 unsigned coord_components
,
3824 unsigned grad_components
)
3826 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3827 int reg_width
= bld
.dispatch_width() / 8;
3828 unsigned header_size
= 0, length
= 0;
3829 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3830 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3831 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3833 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3834 offset_value
.file
!= BAD_FILE
||
3835 is_high_sampler(devinfo
, sampler
)) {
3836 /* For general texture offsets (no txf workaround), we need a header to
3837 * put them in. Note that we're only reserving space for it in the
3838 * message payload as it will be initialized implicitly by the
3841 * TG4 needs to place its channel select in the header, for interaction
3842 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3843 * larger sampler numbers we need to offset the Sampler State Pointer in
3847 sources
[0] = fs_reg();
3851 if (shadow_c
.file
!= BAD_FILE
) {
3852 bld
.MOV(sources
[length
], shadow_c
);
3856 bool coordinate_done
= false;
3858 /* The sampler can only meaningfully compute LOD for fragment shader
3859 * messages. For all other stages, we change the opcode to TXL and
3860 * hardcode the LOD to 0.
3862 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3863 op
== SHADER_OPCODE_TEX
) {
3864 op
= SHADER_OPCODE_TXL
;
3868 /* Set up the LOD info */
3871 case SHADER_OPCODE_TXL
:
3872 bld
.MOV(sources
[length
], lod
);
3875 case SHADER_OPCODE_TXD
:
3876 /* TXD should have been lowered in SIMD16 mode. */
3877 assert(bld
.dispatch_width() == 8);
3879 /* Load dPdx and the coordinate together:
3880 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3882 for (unsigned i
= 0; i
< coord_components
; i
++) {
3883 bld
.MOV(sources
[length
], coordinate
);
3884 coordinate
= offset(coordinate
, bld
, 1);
3887 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3888 * only derivatives for (u, v, r).
3890 if (i
< grad_components
) {
3891 bld
.MOV(sources
[length
], lod
);
3892 lod
= offset(lod
, bld
, 1);
3895 bld
.MOV(sources
[length
], lod2
);
3896 lod2
= offset(lod2
, bld
, 1);
3901 coordinate_done
= true;
3903 case SHADER_OPCODE_TXS
:
3904 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3907 case SHADER_OPCODE_TXF
:
3908 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3909 * On Gen9 they are u, v, lod, r
3911 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3912 coordinate
= offset(coordinate
, bld
, 1);
3915 if (devinfo
->gen
>= 9) {
3916 if (coord_components
>= 2) {
3917 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3918 coordinate
= offset(coordinate
, bld
, 1);
3923 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
3926 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
3927 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3928 coordinate
= offset(coordinate
, bld
, 1);
3932 coordinate_done
= true;
3934 case SHADER_OPCODE_TXF_CMS
:
3935 case SHADER_OPCODE_TXF_CMS_W
:
3936 case SHADER_OPCODE_TXF_UMS
:
3937 case SHADER_OPCODE_TXF_MCS
:
3938 if (op
== SHADER_OPCODE_TXF_UMS
||
3939 op
== SHADER_OPCODE_TXF_CMS
||
3940 op
== SHADER_OPCODE_TXF_CMS_W
) {
3941 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
3945 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
3946 /* Data from the multisample control surface. */
3947 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
3950 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
3953 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
3954 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
3957 offset(mcs
, bld
, 1));
3962 /* There is no offsetting for this message; just copy in the integer
3963 * texture coordinates.
3965 for (unsigned i
= 0; i
< coord_components
; i
++) {
3966 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3967 coordinate
= offset(coordinate
, bld
, 1);
3971 coordinate_done
= true;
3973 case SHADER_OPCODE_TG4_OFFSET
:
3974 /* gather4_po_c should have been lowered in SIMD16 mode. */
3975 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
3977 /* More crazy intermixing */
3978 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
3979 bld
.MOV(sources
[length
], coordinate
);
3980 coordinate
= offset(coordinate
, bld
, 1);
3984 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
3985 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
3986 offset_value
= offset(offset_value
, bld
, 1);
3990 if (coord_components
== 3) { /* r if present */
3991 bld
.MOV(sources
[length
], coordinate
);
3992 coordinate
= offset(coordinate
, bld
, 1);
3996 coordinate_done
= true;
4002 /* Set up the coordinate (except for cases where it was done above) */
4003 if (!coordinate_done
) {
4004 for (unsigned i
= 0; i
< coord_components
; i
++) {
4005 bld
.MOV(sources
[length
], coordinate
);
4006 coordinate
= offset(coordinate
, bld
, 1);
4013 mlen
= length
* reg_width
- header_size
;
4015 mlen
= length
* reg_width
;
4017 const fs_reg src_payload
= fs_reg(GRF
, bld
.shader
->alloc
.allocate(mlen
),
4018 BRW_REGISTER_TYPE_F
);
4019 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4021 /* Generate the SEND. */
4023 inst
->src
[0] = src_payload
;
4024 inst
->src
[1] = sampler
;
4025 inst
->resize_sources(2);
4026 inst
->base_mrf
= -1;
4028 inst
->header_size
= header_size
;
4030 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4031 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4035 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4037 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4038 const fs_reg
&coordinate
= inst
->src
[0];
4039 const fs_reg
&shadow_c
= inst
->src
[1];
4040 const fs_reg
&lod
= inst
->src
[2];
4041 const fs_reg
&lod2
= inst
->src
[3];
4042 const fs_reg
&sample_index
= inst
->src
[4];
4043 const fs_reg
&mcs
= inst
->src
[5];
4044 const fs_reg
&sampler
= inst
->src
[6];
4045 const fs_reg
&offset_value
= inst
->src
[7];
4046 assert(inst
->src
[8].file
== IMM
&& inst
->src
[9].file
== IMM
);
4047 const unsigned coord_components
= inst
->src
[8].fixed_hw_reg
.dw1
.ud
;
4048 const unsigned grad_components
= inst
->src
[9].fixed_hw_reg
.dw1
.ud
;
4050 if (devinfo
->gen
>= 7) {
4051 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4052 shadow_c
, lod
, lod2
, sample_index
,
4053 mcs
, sampler
, offset_value
,
4054 coord_components
, grad_components
);
4055 } else if (devinfo
->gen
>= 5) {
4056 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4057 shadow_c
, lod
, lod2
, sample_index
,
4058 sampler
, offset_value
,
4059 coord_components
, grad_components
);
4061 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4062 shadow_c
, lod
, lod2
, sampler
,
4063 coord_components
, grad_components
);
4068 * Initialize the header present in some typed and untyped surface
4072 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4074 fs_builder ubld
= bld
.exec_all().group(8, 0);
4075 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4076 ubld
.MOV(dst
, fs_reg(0));
4077 ubld
.MOV(component(dst
, 7), sample_mask
);
4082 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4083 const fs_reg
&sample_mask
)
4085 /* Get the logical send arguments. */
4086 const fs_reg
&addr
= inst
->src
[0];
4087 const fs_reg
&src
= inst
->src
[1];
4088 const fs_reg
&surface
= inst
->src
[2];
4089 const UNUSED fs_reg
&dims
= inst
->src
[3];
4090 const fs_reg
&arg
= inst
->src
[4];
4092 /* Calculate the total number of components of the payload. */
4093 const unsigned addr_sz
= inst
->components_read(0);
4094 const unsigned src_sz
= inst
->components_read(1);
4095 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4096 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4098 /* Allocate space for the payload. */
4099 fs_reg
*const components
= new fs_reg
[sz
];
4100 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4103 /* Construct the payload. */
4105 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4107 for (unsigned i
= 0; i
< addr_sz
; i
++)
4108 components
[n
++] = offset(addr
, bld
, i
);
4110 for (unsigned i
= 0; i
< src_sz
; i
++)
4111 components
[n
++] = offset(src
, bld
, i
);
4113 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4115 /* Update the original instruction. */
4117 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4118 inst
->header_size
= header_sz
;
4120 inst
->src
[0] = payload
;
4121 inst
->src
[1] = surface
;
4123 inst
->resize_sources(3);
4125 delete[] components
;
4129 fs_visitor::lower_logical_sends()
4131 bool progress
= false;
4133 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4134 const fs_builder
ibld(this, block
, inst
);
4136 switch (inst
->opcode
) {
4137 case FS_OPCODE_FB_WRITE_LOGICAL
:
4138 assert(stage
== MESA_SHADER_FRAGMENT
);
4139 lower_fb_write_logical_send(ibld
, inst
,
4140 (const brw_wm_prog_data
*)prog_data
,
4141 (const brw_wm_prog_key
*)key
,
4145 case SHADER_OPCODE_TEX_LOGICAL
:
4146 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4149 case SHADER_OPCODE_TXD_LOGICAL
:
4150 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4153 case SHADER_OPCODE_TXF_LOGICAL
:
4154 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4157 case SHADER_OPCODE_TXL_LOGICAL
:
4158 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4161 case SHADER_OPCODE_TXS_LOGICAL
:
4162 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4165 case FS_OPCODE_TXB_LOGICAL
:
4166 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4169 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4170 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4173 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4174 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4177 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4178 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4181 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4182 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4185 case SHADER_OPCODE_LOD_LOGICAL
:
4186 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4189 case SHADER_OPCODE_TG4_LOGICAL
:
4190 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4193 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4194 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4197 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4198 lower_surface_logical_send(ibld
, inst
,
4199 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4203 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4204 lower_surface_logical_send(ibld
, inst
,
4205 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4206 ibld
.sample_mask_reg());
4209 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4210 lower_surface_logical_send(ibld
, inst
,
4211 SHADER_OPCODE_UNTYPED_ATOMIC
,
4212 ibld
.sample_mask_reg());
4215 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4216 lower_surface_logical_send(ibld
, inst
,
4217 SHADER_OPCODE_TYPED_SURFACE_READ
,
4221 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4222 lower_surface_logical_send(ibld
, inst
,
4223 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4224 ibld
.sample_mask_reg());
4227 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4228 lower_surface_logical_send(ibld
, inst
,
4229 SHADER_OPCODE_TYPED_ATOMIC
,
4230 ibld
.sample_mask_reg());
4241 invalidate_live_intervals();
4247 * Get the closest native SIMD width supported by the hardware for instruction
4248 * \p inst. The instruction will be left untouched by
4249 * fs_visitor::lower_simd_width() if the returned value is equal to the
4250 * original execution size.
4253 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4254 const fs_inst
*inst
)
4256 switch (inst
->opcode
) {
4257 case BRW_OPCODE_MOV
:
4258 case BRW_OPCODE_SEL
:
4259 case BRW_OPCODE_NOT
:
4260 case BRW_OPCODE_AND
:
4262 case BRW_OPCODE_XOR
:
4263 case BRW_OPCODE_SHR
:
4264 case BRW_OPCODE_SHL
:
4265 case BRW_OPCODE_ASR
:
4266 case BRW_OPCODE_CMP
:
4267 case BRW_OPCODE_CMPN
:
4268 case BRW_OPCODE_CSEL
:
4269 case BRW_OPCODE_F32TO16
:
4270 case BRW_OPCODE_F16TO32
:
4271 case BRW_OPCODE_BFREV
:
4272 case BRW_OPCODE_BFE
:
4273 case BRW_OPCODE_BFI1
:
4274 case BRW_OPCODE_BFI2
:
4275 case BRW_OPCODE_ADD
:
4276 case BRW_OPCODE_MUL
:
4277 case BRW_OPCODE_AVG
:
4278 case BRW_OPCODE_FRC
:
4279 case BRW_OPCODE_RNDU
:
4280 case BRW_OPCODE_RNDD
:
4281 case BRW_OPCODE_RNDE
:
4282 case BRW_OPCODE_RNDZ
:
4283 case BRW_OPCODE_LZD
:
4284 case BRW_OPCODE_FBH
:
4285 case BRW_OPCODE_FBL
:
4286 case BRW_OPCODE_CBIT
:
4287 case BRW_OPCODE_SAD2
:
4288 case BRW_OPCODE_MAD
:
4289 case BRW_OPCODE_LRP
:
4290 case SHADER_OPCODE_RCP
:
4291 case SHADER_OPCODE_RSQ
:
4292 case SHADER_OPCODE_SQRT
:
4293 case SHADER_OPCODE_EXP2
:
4294 case SHADER_OPCODE_LOG2
:
4295 case SHADER_OPCODE_POW
:
4296 case SHADER_OPCODE_INT_QUOTIENT
:
4297 case SHADER_OPCODE_INT_REMAINDER
:
4298 case SHADER_OPCODE_SIN
:
4299 case SHADER_OPCODE_COS
: {
4300 /* According to the PRMs:
4301 * "A. In Direct Addressing mode, a source cannot span more than 2
4302 * adjacent GRF registers.
4303 * B. A destination cannot span more than 2 adjacent GRF registers."
4305 * Look for the source or destination with the largest register region
4306 * which is the one that is going to limit the overal execution size of
4307 * the instruction due to this rule.
4309 unsigned reg_count
= inst
->regs_written
;
4311 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4312 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4314 /* Calculate the maximum execution size of the instruction based on the
4315 * factor by which it goes over the hardware limit of 2 GRFs.
4317 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4319 case SHADER_OPCODE_MULH
:
4320 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4321 * is 8-wide on Gen7+.
4323 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4325 case FS_OPCODE_FB_WRITE_LOGICAL
:
4326 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4329 assert(devinfo
->gen
!= 6 ||
4330 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4331 inst
->exec_size
== 8);
4332 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4333 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4334 8 : inst
->exec_size
);
4336 case SHADER_OPCODE_TXD_LOGICAL
:
4337 /* TXD is unsupported in SIMD16 mode. */
4340 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4341 /* gather4_po_c is unsupported in SIMD16 mode. */
4342 const fs_reg
&shadow_c
= inst
->src
[1];
4343 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4345 case SHADER_OPCODE_TXL_LOGICAL
:
4346 case FS_OPCODE_TXB_LOGICAL
: {
4347 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4348 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4349 * mode because the message exceeds the maximum length of 11.
4351 const fs_reg
&shadow_c
= inst
->src
[1];
4352 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4354 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4357 return inst
->exec_size
;
4359 case SHADER_OPCODE_TXF_LOGICAL
:
4360 case SHADER_OPCODE_TXS_LOGICAL
:
4361 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4362 * messages. Use SIMD16 instead.
4364 if (devinfo
->gen
== 4)
4367 return inst
->exec_size
;
4369 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4370 /* This opcode can take up to 6 arguments which means that in some
4371 * circumstances it can end up with a message that is too long in SIMD16
4374 const unsigned coord_components
= inst
->src
[8].fixed_hw_reg
.dw1
.ud
;
4375 /* First three arguments are the sample index and the two arguments for
4378 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4381 return inst
->exec_size
;
4384 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4385 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4386 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4390 return inst
->exec_size
;
4395 * The \p rows array of registers represents a \p num_rows by \p num_columns
4396 * matrix in row-major order, write it in column-major order into the register
4397 * passed as destination. \p stride gives the separation between matrix
4398 * elements in the input in fs_builder::dispatch_width() units.
4401 emit_transpose(const fs_builder
&bld
,
4402 const fs_reg
&dst
, const fs_reg
*rows
,
4403 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4405 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4407 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4408 for (unsigned j
= 0; j
< num_rows
; ++j
)
4409 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4412 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4414 delete[] components
;
4418 fs_visitor::lower_simd_width()
4420 bool progress
= false;
4422 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4423 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4425 if (lower_width
!= inst
->exec_size
) {
4426 /* Builder matching the original instruction. We may also need to
4427 * emit an instruction of width larger than the original, set the
4428 * execution size of the builder to the highest of both for now so
4429 * we're sure that both cases can be handled.
4431 const fs_builder ibld
= bld
.at(block
, inst
)
4432 .exec_all(inst
->force_writemask_all
)
4433 .group(MAX2(inst
->exec_size
, lower_width
),
4434 inst
->force_sechalf
);
4436 /* Split the copies in chunks of the execution width of either the
4437 * original or the lowered instruction, whichever is lower.
4439 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4440 const unsigned n
= inst
->exec_size
/ copy_width
;
4441 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4442 inst
->dst
.component_size(inst
->exec_size
);
4445 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4446 !inst
->writes_accumulator
&& !inst
->mlen
);
4448 for (unsigned i
= 0; i
< n
; i
++) {
4449 /* Emit a copy of the original instruction with the lowered width.
4450 * If the EOT flag was set throw it away except for the last
4451 * instruction to avoid killing the thread prematurely.
4453 fs_inst split_inst
= *inst
;
4454 split_inst
.exec_size
= lower_width
;
4455 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4457 /* Select the correct channel enables for the i-th group, then
4458 * transform the sources and destination and emit the lowered
4461 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4463 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4464 if (inst
->src
[j
].file
!= BAD_FILE
&&
4465 !is_uniform(inst
->src
[j
])) {
4466 /* Get the i-th copy_width-wide chunk of the source. */
4467 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4468 const unsigned src_size
= inst
->components_read(j
);
4470 /* Use a trivial transposition to copy one every n
4471 * copy_width-wide components of the register into a
4472 * temporary passed as source to the lowered instruction.
4474 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4475 emit_transpose(lbld
.group(copy_width
, 0),
4476 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4480 if (inst
->regs_written
) {
4481 /* Allocate enough space to hold the result of the lowered
4482 * instruction and fix up the number of registers written.
4484 split_inst
.dst
= dsts
[i
] =
4485 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4486 split_inst
.regs_written
=
4487 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4491 lbld
.emit(split_inst
);
4494 if (inst
->regs_written
) {
4495 /* Distance between useful channels in the temporaries, skipping
4496 * garbage if the lowered instruction is wider than the original.
4498 const unsigned m
= lower_width
/ copy_width
;
4500 /* Interleave the components of the result from the lowered
4501 * instructions. We need to set exec_all() when copying more than
4502 * one half per component, because LOAD_PAYLOAD (in terms of which
4503 * emit_transpose is implemented) can only use the same channel
4504 * enable signals for all of its non-header sources.
4506 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4507 .group(copy_width
, 0),
4508 inst
->dst
, dsts
, n
, dst_size
, m
);
4511 inst
->remove(block
);
4517 invalidate_live_intervals();
4523 fs_visitor::dump_instructions()
4525 dump_instructions(NULL
);
4529 fs_visitor::dump_instructions(const char *name
)
4531 FILE *file
= stderr
;
4532 if (name
&& geteuid() != 0) {
4533 file
= fopen(name
, "w");
4539 calculate_register_pressure();
4540 int ip
= 0, max_pressure
= 0;
4541 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4542 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4543 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4544 dump_instruction(inst
, file
);
4547 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4550 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4551 fprintf(file
, "%4d: ", ip
++);
4552 dump_instruction(inst
, file
);
4556 if (file
!= stderr
) {
4562 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4564 dump_instruction(be_inst
, stderr
);
4568 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4570 fs_inst
*inst
= (fs_inst
*)be_inst
;
4572 if (inst
->predicate
) {
4573 fprintf(file
, "(%cf0.%d) ",
4574 inst
->predicate_inverse
? '-' : '+',
4578 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4580 fprintf(file
, ".sat");
4581 if (inst
->conditional_mod
) {
4582 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4583 if (!inst
->predicate
&&
4584 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4585 inst
->opcode
!= BRW_OPCODE_IF
&&
4586 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4587 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4590 fprintf(file
, "(%d) ", inst
->exec_size
);
4593 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4596 switch (inst
->dst
.file
) {
4598 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
4599 if (alloc
.sizes
[inst
->dst
.reg
] != inst
->regs_written
||
4600 inst
->dst
.subreg_offset
)
4601 fprintf(file
, "+%d.%d",
4602 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4605 fprintf(file
, "m%d", inst
->dst
.reg
);
4608 fprintf(file
, "(null)");
4611 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
4614 fprintf(file
, "***attr%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
4617 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
4618 switch (inst
->dst
.fixed_hw_reg
.nr
) {
4620 fprintf(file
, "null");
4622 case BRW_ARF_ADDRESS
:
4623 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
4625 case BRW_ARF_ACCUMULATOR
:
4626 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
4629 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
4630 inst
->dst
.fixed_hw_reg
.subnr
);
4633 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
4634 inst
->dst
.fixed_hw_reg
.subnr
);
4638 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
4640 if (inst
->dst
.fixed_hw_reg
.subnr
)
4641 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
4644 unreachable("not reached");
4646 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4648 for (int i
= 0; i
< inst
->sources
; i
++) {
4649 if (inst
->src
[i
].negate
)
4651 if (inst
->src
[i
].abs
)
4653 switch (inst
->src
[i
].file
) {
4655 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
4656 if (alloc
.sizes
[inst
->src
[i
].reg
] != (unsigned)inst
->regs_read(i
) ||
4657 inst
->src
[i
].subreg_offset
)
4658 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4659 inst
->src
[i
].subreg_offset
);
4662 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
4665 fprintf(file
, "attr%d+%d", inst
->src
[i
].reg
, inst
->src
[i
].reg_offset
);
4668 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
4669 if (inst
->src
[i
].reladdr
) {
4670 fprintf(file
, "+reladdr");
4671 } else if (inst
->src
[i
].subreg_offset
) {
4672 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4673 inst
->src
[i
].subreg_offset
);
4677 fprintf(file
, "(null)");
4680 switch (inst
->src
[i
].type
) {
4681 case BRW_REGISTER_TYPE_F
:
4682 fprintf(file
, "%ff", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
4684 case BRW_REGISTER_TYPE_W
:
4685 case BRW_REGISTER_TYPE_D
:
4686 fprintf(file
, "%dd", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
4688 case BRW_REGISTER_TYPE_UW
:
4689 case BRW_REGISTER_TYPE_UD
:
4690 fprintf(file
, "%uu", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
4692 case BRW_REGISTER_TYPE_VF
:
4693 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4694 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
4695 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
4696 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
4697 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
4700 fprintf(file
, "???");
4705 if (inst
->src
[i
].fixed_hw_reg
.negate
)
4707 if (inst
->src
[i
].fixed_hw_reg
.abs
)
4709 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
4710 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
4712 fprintf(file
, "null");
4714 case BRW_ARF_ADDRESS
:
4715 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4717 case BRW_ARF_ACCUMULATOR
:
4718 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4721 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
4722 inst
->src
[i
].fixed_hw_reg
.subnr
);
4725 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
4726 inst
->src
[i
].fixed_hw_reg
.subnr
);
4730 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
4732 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
4733 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4734 if (inst
->src
[i
].fixed_hw_reg
.abs
)
4738 if (inst
->src
[i
].abs
)
4741 if (inst
->src
[i
].file
!= IMM
) {
4742 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4745 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4746 fprintf(file
, ", ");
4751 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4752 if (inst
->force_sechalf
)
4753 fprintf(file
, "2ndhalf ");
4755 fprintf(file
, "1sthalf ");
4758 fprintf(file
, "\n");
4762 * Possibly returns an instruction that set up @param reg.
4764 * Sometimes we want to take the result of some expression/variable
4765 * dereference tree and rewrite the instruction generating the result
4766 * of the tree. When processing the tree, we know that the
4767 * instructions generated are all writing temporaries that are dead
4768 * outside of this tree. So, if we have some instructions that write
4769 * a temporary, we're free to point that temp write somewhere else.
4771 * Note that this doesn't guarantee that the instruction generated
4772 * only reg -- it might be the size=4 destination of a texture instruction.
4775 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4780 end
->is_partial_write() ||
4782 !reg
.equals(end
->dst
)) {
4790 fs_visitor::setup_payload_gen6()
4793 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4794 unsigned barycentric_interp_modes
=
4795 (stage
== MESA_SHADER_FRAGMENT
) ?
4796 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4798 assert(devinfo
->gen
>= 6);
4800 /* R0-1: masks, pixel X/Y coordinates. */
4801 payload
.num_regs
= 2;
4802 /* R2: only for 32-pixel dispatch.*/
4804 /* R3-26: barycentric interpolation coordinates. These appear in the
4805 * same order that they appear in the brw_wm_barycentric_interp_mode
4806 * enum. Each set of coordinates occupies 2 registers if dispatch width
4807 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4808 * appear if they were enabled using the "Barycentric Interpolation
4809 * Mode" bits in WM_STATE.
4811 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4812 if (barycentric_interp_modes
& (1 << i
)) {
4813 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4814 payload
.num_regs
+= 2;
4815 if (dispatch_width
== 16) {
4816 payload
.num_regs
+= 2;
4821 /* R27: interpolated depth if uses source depth */
4823 payload
.source_depth_reg
= payload
.num_regs
;
4825 if (dispatch_width
== 16) {
4826 /* R28: interpolated depth if not SIMD8. */
4830 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4832 payload
.source_w_reg
= payload
.num_regs
;
4834 if (dispatch_width
== 16) {
4835 /* R30: interpolated W if not SIMD8. */
4840 if (stage
== MESA_SHADER_FRAGMENT
) {
4841 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4842 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4843 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4844 /* R31: MSAA position offsets. */
4845 if (prog_data
->uses_pos_offset
) {
4846 payload
.sample_pos_reg
= payload
.num_regs
;
4851 /* R32: MSAA input coverage mask */
4852 if (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4853 assert(devinfo
->gen
>= 7);
4854 payload
.sample_mask_in_reg
= payload
.num_regs
;
4856 if (dispatch_width
== 16) {
4857 /* R33: input coverage mask if not SIMD8. */
4862 /* R34-: bary for 32-pixel. */
4863 /* R58-59: interp W for 32-pixel. */
4865 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4866 source_depth_to_render_target
= true;
4871 fs_visitor::setup_vs_payload()
4873 /* R0: thread header, R1: urb handles */
4874 payload
.num_regs
= 2;
4878 * We are building the local ID push constant data using the simplest possible
4879 * method. We simply push the local IDs directly as they should appear in the
4880 * registers for the uvec3 gl_LocalInvocationID variable.
4882 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4883 * registers worth of push constant space.
4885 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
4886 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
4889 * FINISHME: There are a few easy optimizations to consider.
4891 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
4892 * no need for using push constant space for that dimension.
4894 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
4895 * easily use 16-bit words rather than 32-bit dwords in the push constant
4898 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
4899 * conveying the data, and thereby reduce push constant usage.
4903 fs_visitor::setup_gs_payload()
4905 assert(stage
== MESA_SHADER_GEOMETRY
);
4907 struct brw_gs_prog_data
*gs_prog_data
=
4908 (struct brw_gs_prog_data
*) prog_data
;
4909 struct brw_vue_prog_data
*vue_prog_data
=
4910 (struct brw_vue_prog_data
*) prog_data
;
4912 /* R0: thread header, R1: output URB handles */
4913 payload
.num_regs
= 2;
4915 if (gs_prog_data
->include_primitive_id
) {
4916 /* R2: Primitive ID 0..7 */
4920 /* Use a maximum of 32 registers for push-model inputs. */
4921 const unsigned max_push_components
= 32;
4923 /* If pushing our inputs would take too many registers, reduce the URB read
4924 * length (which is in HWords, or 8 registers), and resort to pulling.
4926 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
4927 * have to multiply by VerticesIn to obtain the total storage requirement.
4929 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
4930 max_push_components
) {
4931 gs_prog_data
->base
.include_vue_handles
= true;
4933 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
4934 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
4936 vue_prog_data
->urb_read_length
=
4937 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
4942 fs_visitor::setup_cs_payload()
4944 assert(devinfo
->gen
>= 7);
4945 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
4947 payload
.num_regs
= 1;
4949 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
4950 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
4951 payload
.local_invocation_id_reg
= payload
.num_regs
;
4952 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
4957 fs_visitor::calculate_register_pressure()
4959 invalidate_live_intervals();
4960 calculate_live_intervals();
4962 unsigned num_instructions
= 0;
4963 foreach_block(block
, cfg
)
4964 num_instructions
+= block
->instructions
.length();
4966 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
4968 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
4969 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
4970 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
4975 fs_visitor::optimize()
4977 /* Start by validating the shader we currently have. */
4980 /* bld is the common builder object pointing at the end of the program we
4981 * used to translate it into i965 IR. For the optimization and lowering
4982 * passes coming next, any code added after the end of the program without
4983 * having explicitly called fs_builder::at() clearly points at a mistake.
4984 * Ideally optimization passes wouldn't be part of the visitor so they
4985 * wouldn't have access to bld at all, but they do, so just in case some
4986 * pass forgets to ask for a location explicitly set it to NULL here to
4987 * make it trip. The dispatch width is initialized to a bogus value to
4988 * make sure that optimizations set the execution controls explicitly to
4989 * match the code they are manipulating instead of relying on the defaults.
4991 bld
= fs_builder(this, 64);
4993 assign_constant_locations();
4994 demote_pull_constants();
4998 split_virtual_grfs();
5001 #define OPT(pass, args...) ({ \
5003 bool this_progress = pass(args); \
5005 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5006 char filename[64]; \
5007 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5008 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5010 backend_shader::dump_instructions(filename); \
5015 progress = progress || this_progress; \
5019 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5021 snprintf(filename
, 64, "%s%d-%s-00-start",
5022 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5024 backend_shader::dump_instructions(filename
);
5027 bool progress
= false;
5031 OPT(lower_simd_width
);
5032 OPT(lower_logical_sends
);
5039 OPT(remove_duplicate_mrf_writes
);
5043 OPT(opt_copy_propagate
);
5044 OPT(opt_predicated_break
, this);
5045 OPT(opt_cmod_propagation
);
5046 OPT(dead_code_eliminate
);
5047 OPT(opt_peephole_sel
);
5048 OPT(dead_control_flow_eliminate
, this);
5049 OPT(opt_register_renaming
);
5050 OPT(opt_redundant_discard_jumps
);
5051 OPT(opt_saturate_propagation
);
5052 OPT(opt_zero_samples
);
5053 OPT(register_coalesce
);
5054 OPT(compute_to_mrf
);
5055 OPT(eliminate_find_live_channel
);
5057 OPT(compact_virtual_grfs
);
5062 OPT(opt_sampler_eot
);
5064 if (OPT(lower_load_payload
)) {
5065 split_virtual_grfs();
5066 OPT(register_coalesce
);
5067 OPT(compute_to_mrf
);
5068 OPT(dead_code_eliminate
);
5071 OPT(opt_combine_constants
);
5072 OPT(lower_integer_multiplication
);
5074 lower_uniform_pull_constant_loads();
5080 * Three source instruction must have a GRF/MRF destination register.
5081 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5084 fs_visitor::fixup_3src_null_dest()
5086 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5087 if (inst
->is_3src() && inst
->dst
.is_null()) {
5088 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
5095 fs_visitor::allocate_registers()
5097 bool allocated_without_spills
;
5099 static const enum instruction_scheduler_mode pre_modes
[] = {
5101 SCHEDULE_PRE_NON_LIFO
,
5105 /* Try each scheduling heuristic to see if it can successfully register
5106 * allocate without spilling. They should be ordered by decreasing
5107 * performance but increasing likelihood of allocating.
5109 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5110 schedule_instructions(pre_modes
[i
]);
5113 assign_regs_trivial();
5114 allocated_without_spills
= true;
5116 allocated_without_spills
= assign_regs(false);
5118 if (allocated_without_spills
)
5122 if (!allocated_without_spills
) {
5123 /* We assume that any spilling is worse than just dropping back to
5124 * SIMD8. There's probably actually some intermediate point where
5125 * SIMD16 with a couple of spills is still better.
5127 if (dispatch_width
== 16) {
5128 fail("Failure to register allocate. Reduce number of "
5129 "live scalar values to avoid this.");
5131 compiler
->shader_perf_log(log_data
,
5132 "%s shader triggered register spilling. "
5133 "Try reducing the number of live scalar "
5134 "values to improve performance.\n",
5138 /* Since we're out of heuristics, just go spill registers until we
5139 * get an allocation.
5141 while (!assign_regs(true)) {
5147 /* This must come after all optimization and register allocation, since
5148 * it inserts dead code that happens to have side effects, and it does
5149 * so based on the actual physical registers in use.
5151 insert_gen4_send_dependency_workarounds();
5156 schedule_instructions(SCHEDULE_POST
);
5158 if (last_scratch
> 0)
5159 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5163 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5165 assert(stage
== MESA_SHADER_VERTEX
);
5169 if (shader_time_index
>= 0)
5170 emit_shader_time_begin();
5177 compute_clip_distance(clip_planes
);
5181 if (shader_time_index
>= 0)
5182 emit_shader_time_end();
5188 assign_curb_setup();
5189 assign_vs_urb_setup();
5191 fixup_3src_null_dest();
5192 allocate_registers();
5198 fs_visitor::run_gs()
5200 assert(stage
== MESA_SHADER_GEOMETRY
);
5204 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
5206 if (gs_compile
->control_data_header_size_bits
> 0) {
5207 /* Create a VGRF to store accumulated control data bits. */
5208 this->control_data_bits
= vgrf(glsl_type::uint_type
);
5210 /* If we're outputting more than 32 control data bits, then EmitVertex()
5211 * will set control_data_bits to 0 after emitting the first vertex.
5212 * Otherwise, we need to initialize it to 0 here.
5214 if (gs_compile
->control_data_header_size_bits
<= 32) {
5215 const fs_builder abld
= bld
.annotate("initialize control data bits");
5216 abld
.MOV(this->control_data_bits
, fs_reg(0u));
5220 if (shader_time_index
>= 0)
5221 emit_shader_time_begin();
5225 emit_gs_thread_end();
5227 if (shader_time_index
>= 0)
5228 emit_shader_time_end();
5237 assign_curb_setup();
5238 assign_gs_urb_setup();
5240 fixup_3src_null_dest();
5241 allocate_registers();
5247 fs_visitor::run_fs(bool do_rep_send
)
5249 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5250 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5252 assert(stage
== MESA_SHADER_FRAGMENT
);
5254 if (devinfo
->gen
>= 6)
5255 setup_payload_gen6();
5257 setup_payload_gen4();
5261 } else if (do_rep_send
) {
5262 assert(dispatch_width
== 16);
5263 emit_repclear_shader();
5265 if (shader_time_index
>= 0)
5266 emit_shader_time_begin();
5268 calculate_urb_setup();
5269 if (nir
->info
.inputs_read
> 0) {
5270 if (devinfo
->gen
< 6)
5271 emit_interpolation_setup_gen4();
5273 emit_interpolation_setup_gen6();
5276 /* We handle discards by keeping track of the still-live pixels in f0.1.
5277 * Initialize it with the dispatched pixels.
5279 if (wm_prog_data
->uses_kill
) {
5280 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5281 discard_init
->flag_subreg
= 1;
5284 /* Generate FS IR for main(). (the visitor only descends into
5285 * functions called "main").
5292 if (wm_prog_data
->uses_kill
)
5293 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5295 if (wm_key
->alpha_test_func
)
5300 if (shader_time_index
>= 0)
5301 emit_shader_time_end();
5307 assign_curb_setup();
5310 fixup_3src_null_dest();
5311 allocate_registers();
5317 if (dispatch_width
== 8)
5318 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5320 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5326 fs_visitor::run_cs()
5328 assert(stage
== MESA_SHADER_COMPUTE
);
5332 if (shader_time_index
>= 0)
5333 emit_shader_time_begin();
5340 emit_cs_terminate();
5342 if (shader_time_index
>= 0)
5343 emit_shader_time_end();
5349 assign_curb_setup();
5351 fixup_3src_null_dest();
5352 allocate_registers();
5361 * Return a bitfield where bit n is set if barycentric interpolation mode n
5362 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5365 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5366 bool shade_model_flat
,
5367 bool persample_shading
,
5368 const nir_shader
*shader
)
5370 unsigned barycentric_interp_modes
= 0;
5372 nir_foreach_variable(var
, &shader
->inputs
) {
5373 enum glsl_interp_qualifier interp_qualifier
=
5374 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5375 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5376 bool is_sample
= var
->data
.sample
|| persample_shading
;
5377 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5378 (var
->data
.location
== VARYING_SLOT_COL1
);
5380 /* Ignore WPOS and FACE, because they don't require interpolation. */
5381 if (var
->data
.location
== VARYING_SLOT_POS
||
5382 var
->data
.location
== VARYING_SLOT_FACE
)
5385 /* Determine the set (or sets) of barycentric coordinates needed to
5386 * interpolate this variable. Note that when
5387 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5388 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5389 * for lit pixels, so we need both sets of barycentric coordinates.
5391 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5393 barycentric_interp_modes
|=
5394 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5395 } else if (is_sample
) {
5396 barycentric_interp_modes
|=
5397 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5399 if ((!is_centroid
&& !is_sample
) ||
5400 devinfo
->needs_unlit_centroid_workaround
) {
5401 barycentric_interp_modes
|=
5402 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5404 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5405 (!(shade_model_flat
&& is_gl_Color
) &&
5406 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5408 barycentric_interp_modes
|=
5409 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5410 } else if (is_sample
) {
5411 barycentric_interp_modes
|=
5412 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5414 if ((!is_centroid
&& !is_sample
) ||
5415 devinfo
->needs_unlit_centroid_workaround
) {
5416 barycentric_interp_modes
|=
5417 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5422 return barycentric_interp_modes
;
5426 computed_depth_mode(const nir_shader
*shader
)
5428 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5429 switch (shader
->info
.fs
.depth_layout
) {
5430 case FRAG_DEPTH_LAYOUT_NONE
:
5431 case FRAG_DEPTH_LAYOUT_ANY
:
5432 return BRW_PSCDEPTH_ON
;
5433 case FRAG_DEPTH_LAYOUT_GREATER
:
5434 return BRW_PSCDEPTH_ON_GE
;
5435 case FRAG_DEPTH_LAYOUT_LESS
:
5436 return BRW_PSCDEPTH_ON_LE
;
5437 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5438 return BRW_PSCDEPTH_OFF
;
5441 return BRW_PSCDEPTH_OFF
;
5445 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5447 const struct brw_wm_prog_key
*key
,
5448 struct brw_wm_prog_data
*prog_data
,
5449 const nir_shader
*shader
,
5450 struct gl_program
*prog
,
5451 int shader_time_index8
, int shader_time_index16
,
5453 unsigned *final_assembly_size
,
5456 /* key->alpha_test_func means simulating alpha testing via discards,
5457 * so the shader definitely kills pixels.
5459 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5460 prog_data
->uses_omask
=
5461 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5462 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5463 prog_data
->computed_stencil
=
5464 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5466 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5468 prog_data
->barycentric_interp_modes
=
5469 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5471 key
->persample_shading
,
5474 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5475 &prog_data
->base
, prog
, shader
, 8,
5476 shader_time_index8
);
5477 if (!v
.run_fs(false /* do_rep_send */)) {
5479 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5484 cfg_t
*simd16_cfg
= NULL
;
5485 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5486 &prog_data
->base
, prog
, shader
, 16,
5487 shader_time_index16
);
5488 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5489 if (!v
.simd16_unsupported
) {
5490 /* Try a SIMD16 compile */
5491 v2
.import_uniforms(&v
);
5492 if (!v2
.run_fs(use_rep_send
)) {
5493 compiler
->shader_perf_log(log_data
,
5494 "SIMD16 shader failed to compile: %s",
5497 simd16_cfg
= v2
.cfg
;
5503 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5504 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5506 prog_data
->no_8
= true;
5509 prog_data
->no_8
= false;
5512 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5513 v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
5515 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5516 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5517 shader
->info
.label
? shader
->info
.label
:
5519 shader
->info
.name
));
5523 g
.generate_code(simd8_cfg
, 8);
5525 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5527 return g
.get_assembly(final_assembly_size
);
5531 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
5532 void *buffer
, uint32_t threads
, uint32_t stride
)
5534 if (prog_data
->local_invocation_id_regs
== 0)
5537 /* 'stride' should be an integer number of registers, that is, a multiple
5540 assert(stride
% 32 == 0);
5542 unsigned x
= 0, y
= 0, z
= 0;
5543 for (unsigned t
= 0; t
< threads
; t
++) {
5544 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
5546 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
5547 param
[0 * prog_data
->simd_size
+ i
] = x
;
5548 param
[1 * prog_data
->simd_size
+ i
] = y
;
5549 param
[2 * prog_data
->simd_size
+ i
] = z
;
5552 if (x
== prog_data
->local_size
[0]) {
5555 if (y
== prog_data
->local_size
[1]) {
5558 if (z
== prog_data
->local_size
[2])
5567 fs_visitor::emit_cs_local_invocation_id_setup()
5569 assert(stage
== MESA_SHADER_COMPUTE
);
5571 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5573 struct brw_reg src
=
5574 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5575 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5577 src
.nr
+= dispatch_width
/ 8;
5578 bld
.MOV(offset(*reg
, bld
, 1), src
);
5579 src
.nr
+= dispatch_width
/ 8;
5580 bld
.MOV(offset(*reg
, bld
, 2), src
);
5586 fs_visitor::emit_cs_work_group_id_setup()
5588 assert(stage
== MESA_SHADER_COMPUTE
);
5590 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5592 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5593 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5594 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5596 bld
.MOV(*reg
, r0_1
);
5597 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5598 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5604 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5606 const struct brw_cs_prog_key
*key
,
5607 struct brw_cs_prog_data
*prog_data
,
5608 const nir_shader
*shader
,
5609 int shader_time_index
,
5610 unsigned *final_assembly_size
,
5613 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5614 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5615 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5616 unsigned local_workgroup_size
=
5617 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5618 shader
->info
.cs
.local_size
[2];
5620 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5623 const char *fail_msg
= NULL
;
5625 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5627 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5628 NULL
, /* Never used in core profile */
5629 shader
, 8, shader_time_index
);
5631 fail_msg
= v8
.fail_msg
;
5632 } else if (local_workgroup_size
<= 8 * max_cs_threads
) {
5634 prog_data
->simd_size
= 8;
5637 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5638 NULL
, /* Never used in core profile */
5639 shader
, 16, shader_time_index
);
5640 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5641 !fail_msg
&& !v8
.simd16_unsupported
&&
5642 local_workgroup_size
<= 16 * max_cs_threads
) {
5643 /* Try a SIMD16 compile */
5644 v16
.import_uniforms(&v8
);
5645 if (!v16
.run_cs()) {
5646 compiler
->shader_perf_log(log_data
,
5647 "SIMD16 shader failed to compile: %s",
5651 "Couldn't generate SIMD16 program and not "
5652 "enough threads for SIMD8";
5656 prog_data
->simd_size
= 16;
5660 if (unlikely(cfg
== NULL
)) {
5663 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5668 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5669 v8
.promoted_constants
, v8
.runtime_check_aads_emit
, "CS");
5670 if (INTEL_DEBUG
& DEBUG_CS
) {
5671 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5672 shader
->info
.label
? shader
->info
.label
:
5675 g
.enable_debug(name
);
5678 g
.generate_code(cfg
, prog_data
->simd_size
);
5680 return g
.get_assembly(final_assembly_size
);