2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "compiler/glsl_types.h"
42 #include "program/prog_parameter.h"
47 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
48 const fs_reg
*src
, unsigned sources
)
50 memset(this, 0, sizeof(*this));
52 this->src
= new fs_reg
[MAX2(sources
, 3)];
53 for (unsigned i
= 0; i
< sources
; i
++)
54 this->src
[i
] = src
[i
];
56 this->opcode
= opcode
;
58 this->sources
= sources
;
59 this->exec_size
= exec_size
;
61 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
63 assert(this->exec_size
!= 0);
65 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
67 /* This will be the case for almost all instructions. */
74 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
78 this->regs_written
= 0;
82 unreachable("Invalid destination register file");
85 this->writes_accumulator
= false;
90 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
93 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
95 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
98 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
100 init(opcode
, exec_size
, dst
, NULL
, 0);
103 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
106 const fs_reg src
[1] = { src0
};
107 init(opcode
, exec_size
, dst
, src
, 1);
110 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
111 const fs_reg
&src0
, const fs_reg
&src1
)
113 const fs_reg src
[2] = { src0
, src1
};
114 init(opcode
, exec_size
, dst
, src
, 2);
117 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
118 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
120 const fs_reg src
[3] = { src0
, src1
, src2
};
121 init(opcode
, exec_size
, dst
, src
, 3);
124 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
125 const fs_reg src
[], unsigned sources
)
127 init(opcode
, exec_width
, dst
, src
, sources
);
130 fs_inst::fs_inst(const fs_inst
&that
)
132 memcpy(this, &that
, sizeof(that
));
134 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
136 for (unsigned i
= 0; i
< that
.sources
; i
++)
137 this->src
[i
] = that
.src
[i
];
146 fs_inst::resize_sources(uint8_t num_sources
)
148 if (this->sources
!= num_sources
) {
149 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
151 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
152 src
[i
] = this->src
[i
];
156 this->sources
= num_sources
;
161 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
163 const fs_reg
&surf_index
,
164 const fs_reg
&varying_offset
,
165 uint32_t const_offset
)
167 /* We have our constant surface use a pitch of 4 bytes, so our index can
168 * be any component of a vector, and then we load 4 contiguous
169 * components starting from that.
171 * We break down the const_offset to a portion added to the variable
172 * offset and a portion done using reg_offset, which means that if you
173 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
174 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
175 * CSE can later notice that those loads are all the same and eliminate
176 * the redundant ones.
178 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
179 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
182 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
183 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
184 * u, v, r) as parameters, or we can just use the SIMD16 message
185 * consisting of (header, u). We choose the second, at the cost of a
186 * longer return length.
192 if (devinfo
->gen
>= 7)
193 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
195 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
197 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
198 fs_reg vec4_result
= fs_reg(VGRF
, alloc
.allocate(regs_written
), dst
.type
);
199 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
200 inst
->regs_written
= regs_written
;
202 if (devinfo
->gen
< 7) {
203 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
204 inst
->header_size
= 1;
205 if (devinfo
->gen
== 4)
208 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
211 bld
.MOV(dst
, offset(vec4_result
, bld
, ((const_offset
& 0xf) / 4) * scale
));
215 * A helper for MOV generation for fixing up broken hardware SEND dependency
219 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
221 /* The caller always wants uncompressed to emit the minimal extra
222 * dependencies, and to avoid having to deal with aligning its regs to 2.
224 const fs_builder ubld
= bld
.annotate("send dependency resolve")
227 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
231 fs_inst::equals(fs_inst
*inst
) const
233 return (opcode
== inst
->opcode
&&
234 dst
.equals(inst
->dst
) &&
235 src
[0].equals(inst
->src
[0]) &&
236 src
[1].equals(inst
->src
[1]) &&
237 src
[2].equals(inst
->src
[2]) &&
238 saturate
== inst
->saturate
&&
239 predicate
== inst
->predicate
&&
240 conditional_mod
== inst
->conditional_mod
&&
241 mlen
== inst
->mlen
&&
242 base_mrf
== inst
->base_mrf
&&
243 target
== inst
->target
&&
245 header_size
== inst
->header_size
&&
246 shadow_compare
== inst
->shadow_compare
&&
247 exec_size
== inst
->exec_size
&&
248 offset
== inst
->offset
);
252 fs_inst::overwrites_reg(const fs_reg
®
) const
254 return reg
.in_range(dst
, regs_written
);
258 fs_inst::is_send_from_grf() const
261 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
262 case SHADER_OPCODE_SHADER_TIME_ADD
:
263 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
264 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
265 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
266 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
267 case SHADER_OPCODE_UNTYPED_ATOMIC
:
268 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
269 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
270 case SHADER_OPCODE_TYPED_ATOMIC
:
271 case SHADER_OPCODE_TYPED_SURFACE_READ
:
272 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
273 case SHADER_OPCODE_URB_WRITE_SIMD8
:
274 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
275 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
276 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
277 case SHADER_OPCODE_URB_READ_SIMD8
:
278 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
280 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
281 return src
[1].file
== VGRF
;
282 case FS_OPCODE_FB_WRITE
:
283 return src
[0].file
== VGRF
;
286 return src
[0].file
== VGRF
;
293 * Returns true if this instruction's sources and destinations cannot
294 * safely be the same register.
296 * In most cases, a register can be written over safely by the same
297 * instruction that is its last use. For a single instruction, the
298 * sources are dereferenced before writing of the destination starts
301 * However, there are a few cases where this can be problematic:
303 * - Virtual opcodes that translate to multiple instructions in the
304 * code generator: if src == dst and one instruction writes the
305 * destination before a later instruction reads the source, then
306 * src will have been clobbered.
308 * - SIMD16 compressed instructions with certain regioning (see below).
310 * The register allocator uses this information to set up conflicts between
311 * GRF sources and the destination.
314 fs_inst::has_source_and_destination_hazard() const
317 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
318 /* Multiple partial writes to the destination */
321 /* The SIMD16 compressed instruction
323 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
325 * is actually decoded in hardware as:
327 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
328 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
330 * Which is safe. However, if we have uniform accesses
331 * happening, we get into trouble:
333 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
334 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
336 * Now our destination for the first instruction overwrote the
337 * second instruction's src0, and we get garbage for those 8
338 * pixels. There's a similar issue for the pre-gen6
339 * pixel_x/pixel_y, which are registers of 16-bit values and thus
340 * would get stomped by the first decode as well.
342 if (exec_size
== 16) {
343 for (int i
= 0; i
< sources
; i
++) {
344 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
345 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
346 src
[i
].type
== BRW_REGISTER_TYPE_W
||
347 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
348 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
358 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
360 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
363 fs_reg reg
= this->src
[0];
364 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
367 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
370 for (int i
= 0; i
< this->sources
; i
++) {
371 reg
.type
= this->src
[i
].type
;
372 if (!this->src
[i
].equals(reg
))
375 if (i
< this->header_size
) {
378 reg
= horiz_offset(reg
, this->exec_size
);
386 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
388 if (devinfo
->gen
== 6 && is_math())
391 if (is_send_from_grf())
394 if (!backend_instruction::can_do_source_mods())
401 fs_inst::can_change_types() const
403 return dst
.type
== src
[0].type
&&
404 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
405 (opcode
== BRW_OPCODE_MOV
||
406 (opcode
== BRW_OPCODE_SEL
&&
407 dst
.type
== src
[1].type
&&
408 predicate
!= BRW_PREDICATE_NONE
&&
409 !src
[1].abs
&& !src
[1].negate
));
413 fs_inst::has_side_effects() const
415 return this->eot
|| backend_instruction::has_side_effects();
421 memset(this, 0, sizeof(*this));
425 /** Generic unset register constructor. */
429 this->file
= BAD_FILE
;
432 fs_reg::fs_reg(struct ::brw_reg reg
) :
435 this->reg_offset
= 0;
436 this->subreg_offset
= 0;
438 if (this->file
== IMM
&&
439 (this->type
!= BRW_REGISTER_TYPE_V
&&
440 this->type
!= BRW_REGISTER_TYPE_UV
&&
441 this->type
!= BRW_REGISTER_TYPE_VF
)) {
447 fs_reg::equals(const fs_reg
&r
) const
449 return (this->backend_reg::equals(r
) &&
450 subreg_offset
== r
.subreg_offset
&&
455 fs_reg::set_smear(unsigned subreg
)
457 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
458 subreg_offset
= subreg
* type_sz(type
);
464 fs_reg::is_contiguous() const
470 fs_reg::component_size(unsigned width
) const
472 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
475 return MAX2(width
* stride
, 1) * type_sz(type
);
479 type_size_scalar(const struct glsl_type
*type
)
481 unsigned int size
, i
;
483 switch (type
->base_type
) {
486 case GLSL_TYPE_FLOAT
:
488 return type
->components();
489 case GLSL_TYPE_DOUBLE
:
490 return type
->components() * 2;
491 case GLSL_TYPE_ARRAY
:
492 return type_size_scalar(type
->fields
.array
) * type
->length
;
493 case GLSL_TYPE_STRUCT
:
495 for (i
= 0; i
< type
->length
; i
++) {
496 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
499 case GLSL_TYPE_SAMPLER
:
500 /* Samplers take up no register space, since they're baked in at
504 case GLSL_TYPE_ATOMIC_UINT
:
506 case GLSL_TYPE_SUBROUTINE
:
508 case GLSL_TYPE_IMAGE
:
509 return BRW_IMAGE_PARAM_SIZE
;
511 case GLSL_TYPE_ERROR
:
512 case GLSL_TYPE_INTERFACE
:
513 case GLSL_TYPE_FUNCTION
:
514 unreachable("not reached");
521 * Returns the number of scalar components needed to store type, assuming
522 * that vectors are padded out to vec4.
524 * This has the packing rules of type_size_vec4(), but counts components
525 * similar to type_size_scalar().
528 type_size_vec4_times_4(const struct glsl_type
*type
)
530 return 4 * type_size_vec4(type
);
534 * Create a MOV to read the timestamp register.
536 * The caller is responsible for emitting the MOV. The return value is
537 * the destination of the MOV, with extra parameters set.
540 fs_visitor::get_timestamp(const fs_builder
&bld
)
542 assert(devinfo
->gen
>= 7);
544 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
547 BRW_REGISTER_TYPE_UD
));
549 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
551 /* We want to read the 3 fields we care about even if it's not enabled in
554 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
560 fs_visitor::emit_shader_time_begin()
562 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
564 /* We want only the low 32 bits of the timestamp. Since it's running
565 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
566 * which is plenty of time for our purposes. It is identical across the
567 * EUs, but since it's tracking GPU core speed it will increment at a
568 * varying rate as render P-states change.
570 shader_start_time
.set_smear(0);
574 fs_visitor::emit_shader_time_end()
576 /* Insert our code just before the final SEND with EOT. */
577 exec_node
*end
= this->instructions
.get_tail();
578 assert(end
&& ((fs_inst
*) end
)->eot
);
579 const fs_builder ibld
= bld
.annotate("shader time end")
580 .exec_all().at(NULL
, end
);
582 fs_reg shader_end_time
= get_timestamp(ibld
);
584 /* We only use the low 32 bits of the timestamp - see
585 * emit_shader_time_begin()).
587 * We could also check if render P-states have changed (or anything
588 * else that might disrupt timing) by setting smear to 2 and checking if
589 * that field is != 0.
591 shader_end_time
.set_smear(0);
593 /* Check that there weren't any timestamp reset events (assuming these
594 * were the only two timestamp reads that happened).
596 fs_reg reset
= shader_end_time
;
598 set_condmod(BRW_CONDITIONAL_Z
,
599 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
600 ibld
.IF(BRW_PREDICATE_NORMAL
);
602 fs_reg start
= shader_start_time
;
604 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
607 const fs_builder cbld
= ibld
.group(1, 0);
608 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
610 /* If there were no instructions between the two timestamp gets, the diff
611 * is 2 cycles. Remove that overhead, so I can forget about that when
612 * trying to determine the time taken for single instructions.
614 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
615 SHADER_TIME_ADD(cbld
, 0, diff
);
616 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
617 ibld
.emit(BRW_OPCODE_ELSE
);
618 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
619 ibld
.emit(BRW_OPCODE_ENDIF
);
623 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
624 int shader_time_subindex
,
627 int index
= shader_time_index
* 3 + shader_time_subindex
;
628 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
631 if (dispatch_width
== 8)
632 payload
= vgrf(glsl_type::uvec2_type
);
634 payload
= vgrf(glsl_type::uint_type
);
636 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
640 fs_visitor::vfail(const char *format
, va_list va
)
649 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
650 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
652 this->fail_msg
= msg
;
655 fprintf(stderr
, "%s", msg
);
660 fs_visitor::fail(const char *format
, ...)
664 va_start(va
, format
);
670 * Mark this program as impossible to compile in SIMD16 mode.
672 * During the SIMD8 compile (which happens first), we can detect and flag
673 * things that are unsupported in SIMD16 mode, so the compiler can skip
674 * the SIMD16 compile altogether.
676 * During a SIMD16 compile (if one happens anyway), this just calls fail().
679 fs_visitor::no16(const char *msg
)
681 if (dispatch_width
== 16) {
684 simd16_unsupported
= true;
686 compiler
->shader_perf_log(log_data
,
687 "SIMD16 shader failed to compile: %s", msg
);
692 * Returns true if the instruction has a flag that means it won't
693 * update an entire destination register.
695 * For example, dead code elimination and live variable analysis want to know
696 * when a write to a variable screens off any preceding values that were in
700 fs_inst::is_partial_write() const
702 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
703 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
704 !this->dst
.is_contiguous() ||
705 this->dst
.subreg_offset
> 0);
709 fs_inst::components_read(unsigned i
) const
712 case FS_OPCODE_LINTERP
:
718 case FS_OPCODE_PIXEL_X
:
719 case FS_OPCODE_PIXEL_Y
:
723 case FS_OPCODE_FB_WRITE_LOGICAL
:
724 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
725 /* First/second FB write color. */
727 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
731 case SHADER_OPCODE_TEX_LOGICAL
:
732 case SHADER_OPCODE_TXD_LOGICAL
:
733 case SHADER_OPCODE_TXF_LOGICAL
:
734 case SHADER_OPCODE_TXL_LOGICAL
:
735 case SHADER_OPCODE_TXS_LOGICAL
:
736 case FS_OPCODE_TXB_LOGICAL
:
737 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
738 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
739 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
740 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
741 case SHADER_OPCODE_LOD_LOGICAL
:
742 case SHADER_OPCODE_TG4_LOGICAL
:
743 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
744 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
745 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
746 /* Texture coordinates. */
747 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
748 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
749 /* Texture derivatives. */
750 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
751 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
752 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
753 /* Texture offset. */
754 else if (i
== TEX_LOGICAL_SRC_OFFSET_VALUE
)
757 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
762 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
763 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
764 assert(src
[3].file
== IMM
);
765 /* Surface coordinates. */
768 /* Surface operation source (ignored for reads). */
774 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
775 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
776 assert(src
[3].file
== IMM
&&
778 /* Surface coordinates. */
781 /* Surface operation source. */
787 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
788 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
789 assert(src
[3].file
== IMM
&&
791 const unsigned op
= src
[4].ud
;
792 /* Surface coordinates. */
795 /* Surface operation source. */
796 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
798 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
799 op
== BRW_AOP_PREDEC
))
811 fs_inst::regs_read(int arg
) const
814 case FS_OPCODE_FB_WRITE
:
815 case SHADER_OPCODE_URB_WRITE_SIMD8
:
816 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
817 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
818 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
819 case SHADER_OPCODE_URB_READ_SIMD8
:
820 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
821 case SHADER_OPCODE_UNTYPED_ATOMIC
:
822 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
823 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
824 case SHADER_OPCODE_TYPED_ATOMIC
:
825 case SHADER_OPCODE_TYPED_SURFACE_READ
:
826 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
827 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
832 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
833 /* The payload is actually stored in src1 */
838 case FS_OPCODE_LINTERP
:
843 case SHADER_OPCODE_LOAD_PAYLOAD
:
844 if (arg
< this->header_size
)
848 case CS_OPCODE_CS_TERMINATE
:
849 case SHADER_OPCODE_BARRIER
:
852 case SHADER_OPCODE_MOV_INDIRECT
:
854 assert(src
[2].file
== IMM
);
855 unsigned region_length
= src
[2].ud
;
857 if (src
[0].file
== UNIFORM
) {
858 assert(region_length
% 4 == 0);
859 return region_length
/ 4;
860 } else if (src
[0].file
== FIXED_GRF
) {
861 /* If the start of the region is not register aligned, then
862 * there's some portion of the register that's technically
863 * unread at the beginning.
865 * However, the register allocator works in terms of whole
866 * registers, and does not use subnr. It assumes that the
867 * read starts at the beginning of the register, and extends
868 * regs_read() whole registers beyond that.
870 * To compensate, we extend the region length to include this
871 * unread portion at the beginning.
874 region_length
+= src
[0].subnr
;
876 return DIV_ROUND_UP(region_length
, REG_SIZE
);
878 assert(!"Invalid register file");
884 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
889 switch (src
[arg
].file
) {
899 return DIV_ROUND_UP(components_read(arg
) *
900 src
[arg
].component_size(exec_size
),
903 unreachable("MRF registers are not allowed as sources");
909 fs_inst::reads_flag() const
915 fs_inst::writes_flag() const
917 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
918 opcode
!= BRW_OPCODE_IF
&&
919 opcode
!= BRW_OPCODE_WHILE
)) ||
920 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
924 * Returns how many MRFs an FS opcode will write over.
926 * Note that this is not the 0 or 1 implied writes in an actual gen
927 * instruction -- the FS opcodes often generate MOVs in addition.
930 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
935 if (inst
->base_mrf
== -1)
938 switch (inst
->opcode
) {
939 case SHADER_OPCODE_RCP
:
940 case SHADER_OPCODE_RSQ
:
941 case SHADER_OPCODE_SQRT
:
942 case SHADER_OPCODE_EXP2
:
943 case SHADER_OPCODE_LOG2
:
944 case SHADER_OPCODE_SIN
:
945 case SHADER_OPCODE_COS
:
946 return 1 * dispatch_width
/ 8;
947 case SHADER_OPCODE_POW
:
948 case SHADER_OPCODE_INT_QUOTIENT
:
949 case SHADER_OPCODE_INT_REMAINDER
:
950 return 2 * dispatch_width
/ 8;
951 case SHADER_OPCODE_TEX
:
953 case SHADER_OPCODE_TXD
:
954 case SHADER_OPCODE_TXF
:
955 case SHADER_OPCODE_TXF_CMS
:
956 case SHADER_OPCODE_TXF_CMS_W
:
957 case SHADER_OPCODE_TXF_MCS
:
958 case SHADER_OPCODE_TG4
:
959 case SHADER_OPCODE_TG4_OFFSET
:
960 case SHADER_OPCODE_TXL
:
961 case SHADER_OPCODE_TXS
:
962 case SHADER_OPCODE_LOD
:
963 case SHADER_OPCODE_SAMPLEINFO
:
965 case FS_OPCODE_FB_WRITE
:
967 case FS_OPCODE_GET_BUFFER_SIZE
:
968 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
969 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
971 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
973 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
975 case SHADER_OPCODE_UNTYPED_ATOMIC
:
976 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
977 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
978 case SHADER_OPCODE_TYPED_ATOMIC
:
979 case SHADER_OPCODE_TYPED_SURFACE_READ
:
980 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
981 case SHADER_OPCODE_URB_WRITE_SIMD8
:
982 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
983 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
984 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
985 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
986 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
987 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
988 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
991 unreachable("not reached");
996 fs_visitor::vgrf(const glsl_type
*const type
)
998 int reg_width
= dispatch_width
/ 8;
999 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
1000 brw_type_for_base_type(type
));
1003 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1008 this->type
= BRW_REGISTER_TYPE_F
;
1009 this->stride
= (file
== UNIFORM
? 0 : 1);
1012 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1018 this->stride
= (file
== UNIFORM
? 0 : 1);
1021 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1022 * This brings in those uniform definitions
1025 fs_visitor::import_uniforms(fs_visitor
*v
)
1027 this->push_constant_loc
= v
->push_constant_loc
;
1028 this->pull_constant_loc
= v
->pull_constant_loc
;
1029 this->uniforms
= v
->uniforms
;
1033 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
1034 bool origin_upper_left
)
1036 assert(stage
== MESA_SHADER_FRAGMENT
);
1037 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1038 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1040 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
1042 /* gl_FragCoord.x */
1043 if (pixel_center_integer
) {
1044 bld
.MOV(wpos
, this->pixel_x
);
1046 bld
.ADD(wpos
, this->pixel_x
, brw_imm_f(0.5f
));
1048 wpos
= offset(wpos
, bld
, 1);
1050 /* gl_FragCoord.y */
1051 if (!flip
&& pixel_center_integer
) {
1052 bld
.MOV(wpos
, this->pixel_y
);
1054 fs_reg pixel_y
= this->pixel_y
;
1055 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
1058 pixel_y
.negate
= true;
1059 offset
+= key
->drawable_height
- 1.0f
;
1062 bld
.ADD(wpos
, pixel_y
, brw_imm_f(offset
));
1064 wpos
= offset(wpos
, bld
, 1);
1066 /* gl_FragCoord.z */
1067 if (devinfo
->gen
>= 6) {
1068 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1070 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1071 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1072 interp_reg(VARYING_SLOT_POS
, 2));
1074 wpos
= offset(wpos
, bld
, 1);
1076 /* gl_FragCoord.w: Already set up in emit_interpolation */
1077 bld
.MOV(wpos
, this->wpos_w
);
1083 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1084 glsl_interp_qualifier interpolation_mode
,
1085 bool is_centroid
, bool is_sample
)
1087 brw_wm_barycentric_interp_mode barycoord_mode
;
1088 if (devinfo
->gen
>= 6) {
1090 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1091 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1093 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1094 } else if (is_sample
) {
1095 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1096 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1098 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1100 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1101 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1103 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1106 /* On Ironlake and below, there is only one interpolation mode.
1107 * Centroid interpolation doesn't mean anything on this hardware --
1108 * there is no multisampling.
1110 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1112 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1113 this->delta_xy
[barycoord_mode
], interp
);
1117 fs_visitor::emit_general_interpolation(fs_reg
*attr
, const char *name
,
1118 const glsl_type
*type
,
1119 glsl_interp_qualifier interpolation_mode
,
1120 int *location
, bool mod_centroid
,
1123 assert(stage
== MESA_SHADER_FRAGMENT
);
1124 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1125 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1127 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1129 *location
== VARYING_SLOT_COL0
|| *location
== VARYING_SLOT_COL1
;
1130 if (key
->flat_shade
&& is_gl_Color
) {
1131 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1133 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1137 if (type
->is_array() || type
->is_matrix()) {
1138 const glsl_type
*elem_type
= glsl_get_array_element(type
);
1139 const unsigned length
= glsl_get_length(type
);
1141 for (unsigned i
= 0; i
< length
; i
++) {
1142 emit_general_interpolation(attr
, name
, elem_type
, interpolation_mode
,
1143 location
, mod_centroid
, mod_sample
);
1145 } else if (type
->is_record()) {
1146 for (unsigned i
= 0; i
< type
->length
; i
++) {
1147 const glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
1148 emit_general_interpolation(attr
, name
, field_type
, interpolation_mode
,
1149 location
, mod_centroid
, mod_sample
);
1152 assert(type
->is_scalar() || type
->is_vector());
1154 if (prog_data
->urb_setup
[*location
] == -1) {
1155 /* If there's no incoming setup data for this slot, don't
1156 * emit interpolation for it.
1158 *attr
= offset(*attr
, bld
, type
->vector_elements
);
1163 attr
->type
= brw_type_for_base_type(type
->get_scalar_type());
1165 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1166 /* Constant interpolation (flat shading) case. The SF has
1167 * handed us defined values in only the constant offset
1168 * field of the setup reg.
1170 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1171 struct brw_reg interp
= interp_reg(*location
, i
);
1172 interp
= suboffset(interp
, 3);
1173 interp
.type
= attr
->type
;
1174 bld
.emit(FS_OPCODE_CINTERP
, *attr
, fs_reg(interp
));
1175 *attr
= offset(*attr
, bld
, 1);
1178 /* Smooth/noperspective interpolation case. */
1179 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1180 struct brw_reg interp
= interp_reg(*location
, i
);
1181 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1182 /* Get the pixel/sample mask into f0 so that we know
1183 * which pixels are lit. Then, for each channel that is
1184 * unlit, replace the centroid data with non-centroid
1187 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1190 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1192 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1193 inst
->predicate_inverse
= true;
1194 if (devinfo
->has_pln
)
1195 inst
->no_dd_clear
= true;
1197 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1198 mod_centroid
&& !key
->persample_shading
,
1199 mod_sample
|| key
->persample_shading
);
1200 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1201 inst
->predicate_inverse
= false;
1202 if (devinfo
->has_pln
)
1203 inst
->no_dd_check
= true;
1206 emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1207 mod_centroid
&& !key
->persample_shading
,
1208 mod_sample
|| key
->persample_shading
);
1210 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1211 bld
.MUL(*attr
, *attr
, this->pixel_w
);
1213 *attr
= offset(*attr
, bld
, 1);
1221 fs_visitor::emit_frontfacing_interpolation()
1223 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1225 if (devinfo
->gen
>= 6) {
1226 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1227 * a boolean result from this (~0/true or 0/false).
1229 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1230 * this task in only one instruction:
1231 * - a negation source modifier will flip the bit; and
1232 * - a W -> D type conversion will sign extend the bit into the high
1233 * word of the destination.
1235 * An ASR 15 fills the low word of the destination.
1237 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1240 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1242 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1243 * a boolean result from this (1/true or 0/false).
1245 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1246 * the negation source modifier to flip it. Unfortunately the SHR
1247 * instruction only operates on UD (or D with an abs source modifier)
1248 * sources without negation.
1250 * Instead, use ASR (which will give ~0/true or 0/false).
1252 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1255 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1262 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1264 assert(stage
== MESA_SHADER_FRAGMENT
);
1265 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1266 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1268 if (key
->compute_pos_offset
) {
1269 /* Convert int_sample_pos to floating point */
1270 bld
.MOV(dst
, int_sample_pos
);
1271 /* Scale to the range [0, 1] */
1272 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1275 /* From ARB_sample_shading specification:
1276 * "When rendering to a non-multisample buffer, or if multisample
1277 * rasterization is disabled, gl_SamplePosition will always be
1280 bld
.MOV(dst
, brw_imm_f(0.5f
));
1285 fs_visitor::emit_samplepos_setup()
1287 assert(devinfo
->gen
>= 6);
1289 const fs_builder abld
= bld
.annotate("compute sample position");
1290 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1292 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1293 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1295 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1296 * mode will be enabled.
1298 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1299 * R31.1:0 Position Offset X/Y for Slot[3:0]
1300 * R31.3:2 Position Offset X/Y for Slot[7:4]
1303 * The X, Y sample positions come in as bytes in thread payload. So, read
1304 * the positions using vstride=16, width=8, hstride=2.
1306 struct brw_reg sample_pos_reg
=
1307 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1308 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1310 if (dispatch_width
== 8) {
1311 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1313 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1314 abld
.half(1).MOV(half(int_sample_x
, 1),
1315 fs_reg(suboffset(sample_pos_reg
, 16)));
1317 /* Compute gl_SamplePosition.x */
1318 compute_sample_position(pos
, int_sample_x
);
1319 pos
= offset(pos
, abld
, 1);
1320 if (dispatch_width
== 8) {
1321 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1323 abld
.half(0).MOV(half(int_sample_y
, 0),
1324 fs_reg(suboffset(sample_pos_reg
, 1)));
1325 abld
.half(1).MOV(half(int_sample_y
, 1),
1326 fs_reg(suboffset(sample_pos_reg
, 17)));
1328 /* Compute gl_SamplePosition.y */
1329 compute_sample_position(pos
, int_sample_y
);
1334 fs_visitor::emit_sampleid_setup()
1336 assert(stage
== MESA_SHADER_FRAGMENT
);
1337 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1338 assert(devinfo
->gen
>= 6);
1340 const fs_builder abld
= bld
.annotate("compute sample id");
1341 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1343 if (!key
->multisample_fbo
) {
1344 /* As per GL_ARB_sample_shading specification:
1345 * "When rendering to a non-multisample buffer, or if multisample
1346 * rasterization is disabled, gl_SampleID will always be zero."
1348 abld
.MOV(*reg
, brw_imm_d(0));
1349 } else if (devinfo
->gen
>= 8) {
1350 /* Sample ID comes in as 4-bit numbers in g1.0:
1352 * 15:12 Slot 3 SampleID (only used in SIMD16)
1353 * 11:8 Slot 2 SampleID (only used in SIMD16)
1354 * 7:4 Slot 1 SampleID
1355 * 3:0 Slot 0 SampleID
1357 * Each slot corresponds to four channels, so we want to replicate each
1358 * half-byte value to 4 channels in a row:
1360 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1361 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1363 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1364 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1366 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1367 * channels to read the first byte (7:0), and the second group of 8
1368 * channels to read the second byte (15:8). Then, we shift right by
1369 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1370 * values into place. Finally, we AND with 0xf to keep the low nibble.
1372 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1373 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1375 * TODO: These payload bits exist on Gen7 too, but they appear to always
1376 * be zero, so this code fails to work. We should find out why.
1378 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1380 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1381 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1382 brw_imm_v(0x44440000));
1383 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1385 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1387 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1389 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1390 * 8x multisampling, subspan 0 will represent sample N (where N
1391 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1392 * 7. We can find the value of N by looking at R0.0 bits 7:6
1393 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1394 * (since samples are always delivered in pairs). That is, we
1395 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1396 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1397 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1398 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1399 * populating a temporary variable with the sequence (0, 1, 2, 3),
1400 * and then reading from it using vstride=1, width=4, hstride=0.
1401 * These computations hold good for 4x multisampling as well.
1403 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1404 * the first four slots are sample 0 of subspan 0; the next four
1405 * are sample 1 of subspan 0; the third group is sample 0 of
1406 * subspan 1, and finally sample 1 of subspan 1.
1409 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1410 * accomodate 16x MSAA.
1412 abld
.exec_all().group(1, 0)
1413 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1415 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1417 /* This works for both SIMD8 and SIMD16 */
1418 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1420 /* This special instruction takes care of setting vstride=1,
1421 * width=4, hstride=0 of t2 during an ADD instruction.
1423 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1430 fs_visitor::emit_samplemaskin_setup()
1432 assert(stage
== MESA_SHADER_FRAGMENT
);
1433 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1434 assert(devinfo
->gen
>= 6);
1436 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1438 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1439 BRW_REGISTER_TYPE_D
));
1441 if (key
->persample_shading
) {
1442 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1443 * and a mask representing which sample is being processed by the
1444 * current shader invocation.
1446 * From the OES_sample_variables specification:
1447 * "When per-sample shading is active due to the use of a fragment input
1448 * qualified by "sample" or due to the use of the gl_SampleID or
1449 * gl_SamplePosition variables, only the bit for the current sample is
1450 * set in gl_SampleMaskIn."
1452 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1454 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1455 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1457 fs_reg one
= vgrf(glsl_type::int_type
);
1458 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1459 abld
.MOV(one
, brw_imm_d(1));
1460 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1461 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1463 /* In per-pixel mode, the coverage mask is sufficient. */
1464 *reg
= coverage_mask
;
1470 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1472 if (!src
.abs
&& !src
.negate
)
1475 fs_reg temp
= bld
.vgrf(src
.type
);
1482 fs_visitor::emit_discard_jump()
1484 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1486 /* For performance, after a discard, jump to the end of the
1487 * shader if all relevant channels have been discarded.
1489 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1490 discard_jump
->flag_subreg
= 1;
1492 discard_jump
->predicate
= (dispatch_width
== 8)
1493 ? BRW_PREDICATE_ALIGN1_ANY8H
1494 : BRW_PREDICATE_ALIGN1_ANY16H
;
1495 discard_jump
->predicate_inverse
= true;
1499 fs_visitor::emit_gs_thread_end()
1501 assert(stage
== MESA_SHADER_GEOMETRY
);
1503 struct brw_gs_prog_data
*gs_prog_data
=
1504 (struct brw_gs_prog_data
*) prog_data
;
1506 if (gs_compile
->control_data_header_size_bits
> 0) {
1507 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1510 const fs_builder abld
= bld
.annotate("thread end");
1513 if (gs_prog_data
->static_vertex_count
!= -1) {
1514 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1515 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1516 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1517 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1518 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1521 /* Delete now dead instructions. */
1522 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1528 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1532 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1533 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1534 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1537 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1538 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1539 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1540 sources
[1] = this->final_gs_vertex_count
;
1541 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1542 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1550 fs_visitor::assign_curb_setup()
1552 if (dispatch_width
== 8) {
1553 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1555 if (stage
== MESA_SHADER_FRAGMENT
) {
1556 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1557 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1558 } else if (stage
== MESA_SHADER_COMPUTE
) {
1559 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1560 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1562 unreachable("Unsupported shader type!");
1566 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1568 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1569 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1570 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1571 if (inst
->src
[i
].file
== UNIFORM
) {
1572 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1574 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1575 constant_nr
= push_constant_loc
[uniform_nr
];
1577 /* Section 5.11 of the OpenGL 4.1 spec says:
1578 * "Out-of-bounds reads return undefined values, which include
1579 * values from other variables of the active program or zero."
1580 * Just return the first push constant.
1585 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1588 brw_reg
.abs
= inst
->src
[i
].abs
;
1589 brw_reg
.negate
= inst
->src
[i
].negate
;
1591 assert(inst
->src
[i
].stride
== 0);
1592 inst
->src
[i
] = byte_offset(
1593 retype(brw_reg
, inst
->src
[i
].type
),
1594 inst
->src
[i
].subreg_offset
);
1599 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1600 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1604 fs_visitor::calculate_urb_setup()
1606 assert(stage
== MESA_SHADER_FRAGMENT
);
1607 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1608 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1610 memset(prog_data
->urb_setup
, -1,
1611 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1614 /* Figure out where each of the incoming setup attributes lands. */
1615 if (devinfo
->gen
>= 6) {
1616 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1617 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1618 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1619 * first 16 varying inputs, so we can put them wherever we want.
1620 * Just put them in order.
1622 * This is useful because it means that (a) inputs not used by the
1623 * fragment shader won't take up valuable register space, and (b) we
1624 * won't have to recompile the fragment shader if it gets paired with
1625 * a different vertex (or geometry) shader.
1627 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1628 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1629 BITFIELD64_BIT(i
)) {
1630 prog_data
->urb_setup
[i
] = urb_next
++;
1634 bool include_vue_header
=
1635 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1637 /* We have enough input varyings that the SF/SBE pipeline stage can't
1638 * arbitrarily rearrange them to suit our whim; we have to put them
1639 * in an order that matches the output of the previous pipeline stage
1640 * (geometry or vertex shader).
1642 struct brw_vue_map prev_stage_vue_map
;
1643 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1644 key
->input_slots_valid
,
1645 nir
->info
.separate_shader
);
1647 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1649 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1650 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1652 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1653 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1654 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1655 BITFIELD64_BIT(varying
))) {
1656 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1659 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1662 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1663 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1664 /* Point size is packed into the header, not as a general attribute */
1665 if (i
== VARYING_SLOT_PSIZ
)
1668 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1669 /* The back color slot is skipped when the front color is
1670 * also written to. In addition, some slots can be
1671 * written in the vertex shader and not read in the
1672 * fragment shader. So the register number must always be
1673 * incremented, mapped or not.
1675 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1676 prog_data
->urb_setup
[i
] = urb_next
;
1682 * It's a FS only attribute, and we did interpolation for this attribute
1683 * in SF thread. So, count it here, too.
1685 * See compile_sf_prog() for more info.
1687 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1688 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1691 prog_data
->num_varying_inputs
= urb_next
;
1695 fs_visitor::assign_urb_setup()
1697 assert(stage
== MESA_SHADER_FRAGMENT
);
1698 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1700 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1702 /* Offset all the urb_setup[] index by the actual position of the
1703 * setup regs, now that the location of the constants has been chosen.
1705 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1706 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1707 assert(inst
->src
[1].file
== FIXED_GRF
);
1708 inst
->src
[1].nr
+= urb_start
;
1711 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1712 assert(inst
->src
[0].file
== FIXED_GRF
);
1713 inst
->src
[0].nr
+= urb_start
;
1717 /* Each attribute is 4 setup channels, each of which is half a reg. */
1718 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1722 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1724 for (int i
= 0; i
< inst
->sources
; i
++) {
1725 if (inst
->src
[i
].file
== ATTR
) {
1726 int grf
= payload
.num_regs
+
1727 prog_data
->curb_read_length
+
1729 inst
->src
[i
].reg_offset
;
1731 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : inst
->exec_size
;
1732 struct brw_reg reg
=
1733 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1734 inst
->src
[i
].subreg_offset
),
1735 inst
->exec_size
* inst
->src
[i
].stride
,
1736 width
, inst
->src
[i
].stride
);
1737 reg
.abs
= inst
->src
[i
].abs
;
1738 reg
.negate
= inst
->src
[i
].negate
;
1746 fs_visitor::assign_vs_urb_setup()
1748 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1750 assert(stage
== MESA_SHADER_VERTEX
);
1752 /* Each attribute is 4 regs. */
1753 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1755 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1757 /* Rewrite all ATTR file references to the hw grf that they land in. */
1758 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1759 convert_attr_sources_to_hw_regs(inst
);
1764 fs_visitor::assign_tcs_single_patch_urb_setup()
1766 assert(stage
== MESA_SHADER_TESS_CTRL
);
1768 /* Rewrite all ATTR file references to HW_REGs. */
1769 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1770 convert_attr_sources_to_hw_regs(inst
);
1775 fs_visitor::assign_tes_urb_setup()
1777 assert(stage
== MESA_SHADER_TESS_EVAL
);
1779 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1781 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1783 /* Rewrite all ATTR file references to HW_REGs. */
1784 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1785 convert_attr_sources_to_hw_regs(inst
);
1790 fs_visitor::assign_gs_urb_setup()
1792 assert(stage
== MESA_SHADER_GEOMETRY
);
1794 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1796 first_non_payload_grf
+=
1797 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1799 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1800 /* Rewrite all ATTR file references to GRFs. */
1801 convert_attr_sources_to_hw_regs(inst
);
1807 * Split large virtual GRFs into separate components if we can.
1809 * This is mostly duplicated with what brw_fs_vector_splitting does,
1810 * but that's really conservative because it's afraid of doing
1811 * splitting that doesn't result in real progress after the rest of
1812 * the optimization phases, which would cause infinite looping in
1813 * optimization. We can do it once here, safely. This also has the
1814 * opportunity to split interpolated values, or maybe even uniforms,
1815 * which we don't have at the IR level.
1817 * We want to split, because virtual GRFs are what we register
1818 * allocate and spill (due to contiguousness requirements for some
1819 * instructions), and they're what we naturally generate in the
1820 * codegen process, but most virtual GRFs don't actually need to be
1821 * contiguous sets of GRFs. If we split, we'll end up with reduced
1822 * live intervals and better dead code elimination and coalescing.
1825 fs_visitor::split_virtual_grfs()
1827 int num_vars
= this->alloc
.count
;
1829 /* Count the total number of registers */
1831 int vgrf_to_reg
[num_vars
];
1832 for (int i
= 0; i
< num_vars
; i
++) {
1833 vgrf_to_reg
[i
] = reg_count
;
1834 reg_count
+= alloc
.sizes
[i
];
1837 /* An array of "split points". For each register slot, this indicates
1838 * if this slot can be separated from the previous slot. Every time an
1839 * instruction uses multiple elements of a register (as a source or
1840 * destination), we mark the used slots as inseparable. Then we go
1841 * through and split the registers into the smallest pieces we can.
1843 bool split_points
[reg_count
];
1844 memset(split_points
, 0, sizeof(split_points
));
1846 /* Mark all used registers as fully splittable */
1847 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1848 if (inst
->dst
.file
== VGRF
) {
1849 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1850 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1851 split_points
[reg
+ j
] = true;
1854 for (int i
= 0; i
< inst
->sources
; i
++) {
1855 if (inst
->src
[i
].file
== VGRF
) {
1856 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1857 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1858 split_points
[reg
+ j
] = true;
1863 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1864 if (inst
->dst
.file
== VGRF
) {
1865 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1866 for (int j
= 1; j
< inst
->regs_written
; j
++)
1867 split_points
[reg
+ j
] = false;
1869 for (int i
= 0; i
< inst
->sources
; i
++) {
1870 if (inst
->src
[i
].file
== VGRF
) {
1871 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1872 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1873 split_points
[reg
+ j
] = false;
1878 int new_virtual_grf
[reg_count
];
1879 int new_reg_offset
[reg_count
];
1882 for (int i
= 0; i
< num_vars
; i
++) {
1883 /* The first one should always be 0 as a quick sanity check. */
1884 assert(split_points
[reg
] == false);
1887 new_reg_offset
[reg
] = 0;
1892 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1893 /* If this is a split point, reset the offset to 0 and allocate a
1894 * new virtual GRF for the previous offset many registers
1896 if (split_points
[reg
]) {
1897 assert(offset
<= MAX_VGRF_SIZE
);
1898 int grf
= alloc
.allocate(offset
);
1899 for (int k
= reg
- offset
; k
< reg
; k
++)
1900 new_virtual_grf
[k
] = grf
;
1903 new_reg_offset
[reg
] = offset
;
1908 /* The last one gets the original register number */
1909 assert(offset
<= MAX_VGRF_SIZE
);
1910 alloc
.sizes
[i
] = offset
;
1911 for (int k
= reg
- offset
; k
< reg
; k
++)
1912 new_virtual_grf
[k
] = i
;
1914 assert(reg
== reg_count
);
1916 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1917 if (inst
->dst
.file
== VGRF
) {
1918 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1919 inst
->dst
.nr
= new_virtual_grf
[reg
];
1920 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1921 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1923 for (int i
= 0; i
< inst
->sources
; i
++) {
1924 if (inst
->src
[i
].file
== VGRF
) {
1925 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1926 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1927 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1928 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1932 invalidate_live_intervals();
1936 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1938 * During code generation, we create tons of temporary variables, many of
1939 * which get immediately killed and are never used again. Yet, in later
1940 * optimization and analysis passes, such as compute_live_intervals, we need
1941 * to loop over all the virtual GRFs. Compacting them can save a lot of
1945 fs_visitor::compact_virtual_grfs()
1947 bool progress
= false;
1948 int remap_table
[this->alloc
.count
];
1949 memset(remap_table
, -1, sizeof(remap_table
));
1951 /* Mark which virtual GRFs are used. */
1952 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1953 if (inst
->dst
.file
== VGRF
)
1954 remap_table
[inst
->dst
.nr
] = 0;
1956 for (int i
= 0; i
< inst
->sources
; i
++) {
1957 if (inst
->src
[i
].file
== VGRF
)
1958 remap_table
[inst
->src
[i
].nr
] = 0;
1962 /* Compact the GRF arrays. */
1964 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1965 if (remap_table
[i
] == -1) {
1966 /* We just found an unused register. This means that we are
1967 * actually going to compact something.
1971 remap_table
[i
] = new_index
;
1972 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1973 invalidate_live_intervals();
1978 this->alloc
.count
= new_index
;
1980 /* Patch all the instructions to use the newly renumbered registers */
1981 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1982 if (inst
->dst
.file
== VGRF
)
1983 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1985 for (int i
= 0; i
< inst
->sources
; i
++) {
1986 if (inst
->src
[i
].file
== VGRF
)
1987 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1991 /* Patch all the references to delta_xy, since they're used in register
1992 * allocation. If they're unused, switch them to BAD_FILE so we don't
1993 * think some random VGRF is delta_xy.
1995 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1996 if (delta_xy
[i
].file
== VGRF
) {
1997 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1998 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
2000 delta_xy
[i
].file
= BAD_FILE
;
2009 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
, bool contiguous
,
2010 int *push_constant_loc
, int *pull_constant_loc
,
2011 unsigned *num_push_constants
,
2012 unsigned *num_pull_constants
,
2013 const unsigned max_push_components
,
2014 const unsigned max_chunk_size
,
2015 struct brw_stage_prog_data
*stage_prog_data
)
2017 /* This is the first live uniform in the chunk */
2018 if (*chunk_start
< 0)
2019 *chunk_start
= uniform
;
2021 /* If this element does not need to be contiguous with the next, we
2022 * split at this point and everything between chunk_start and u forms a
2026 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
2028 /* Decide whether we should push or pull this parameter. In the
2029 * Vulkan driver, push constants are explicitly exposed via the API
2030 * so we push everything. In GL, we only push small arrays.
2032 if (stage_prog_data
->pull_param
== NULL
||
2033 (*num_push_constants
+ chunk_size
<= max_push_components
&&
2034 chunk_size
<= max_chunk_size
)) {
2035 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
2036 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
2037 push_constant_loc
[j
] = (*num_push_constants
)++;
2039 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
2040 pull_constant_loc
[j
] = (*num_pull_constants
)++;
2048 * Assign UNIFORM file registers to either push constants or pull constants.
2050 * We allow a fragment shader to have more than the specified minimum
2051 * maximum number of fragment shader uniform components (64). If
2052 * there are too many of these, they'd fill up all of register space.
2053 * So, this will push some of them out to the pull constant buffer and
2054 * update the program to load them.
2057 fs_visitor::assign_constant_locations()
2059 /* Only the first compile gets to decide on locations. */
2060 if (dispatch_width
!= min_dispatch_width
)
2063 bool is_live
[uniforms
];
2064 memset(is_live
, 0, sizeof(is_live
));
2065 bool is_live_64bit
[uniforms
];
2066 memset(is_live_64bit
, 0, sizeof(is_live_64bit
));
2068 /* For each uniform slot, a value of true indicates that the given slot and
2069 * the next slot must remain contiguous. This is used to keep us from
2070 * splitting arrays apart.
2072 bool contiguous
[uniforms
];
2073 memset(contiguous
, 0, sizeof(contiguous
));
2075 /* First, we walk through the instructions and do two things:
2077 * 1) Figure out which uniforms are live.
2079 * 2) Mark any indirectly used ranges of registers as contiguous.
2081 * Note that we don't move constant-indexed accesses to arrays. No
2082 * testing has been done of the performance impact of this choice.
2084 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2085 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2086 if (inst
->src
[i
].file
!= UNIFORM
)
2089 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2091 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2092 assert(inst
->src
[2].ud
% 4 == 0);
2093 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
2094 assert(last
< uniforms
);
2096 for (unsigned j
= constant_nr
; j
< last
; j
++) {
2098 contiguous
[j
] = true;
2099 if (type_sz(inst
->src
[i
].type
) == 8) {
2100 is_live_64bit
[j
] = true;
2103 is_live
[last
] = true;
2105 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
2106 int regs_read
= inst
->components_read(i
) *
2107 type_sz(inst
->src
[i
].type
) / 4;
2108 for (int j
= 0; j
< regs_read
; j
++) {
2109 is_live
[constant_nr
+ j
] = true;
2110 if (type_sz(inst
->src
[i
].type
) == 8) {
2111 is_live_64bit
[constant_nr
+ j
] = true;
2119 /* Only allow 16 registers (128 uniform components) as push constants.
2121 * Just demote the end of the list. We could probably do better
2122 * here, demoting things that are rarely used in the program first.
2124 * If changing this value, note the limitation about total_regs in
2127 const unsigned int max_push_components
= 16 * 8;
2129 /* We push small arrays, but no bigger than 16 floats. This is big enough
2130 * for a vec4 but hopefully not large enough to push out other stuff. We
2131 * should probably use a better heuristic at some point.
2133 const unsigned int max_chunk_size
= 16;
2135 unsigned int num_push_constants
= 0;
2136 unsigned int num_pull_constants
= 0;
2138 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2139 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2141 int chunk_start
= -1;
2143 /* First push 64-bit uniforms to ensure they are properly aligned */
2144 for (unsigned u
= 0; u
< uniforms
; u
++) {
2145 if (!is_live
[u
] || !is_live_64bit
[u
])
2148 pull_constant_loc
[u
] = -1;
2149 push_constant_loc
[u
] = -1;
2151 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2152 push_constant_loc
, pull_constant_loc
,
2153 &num_push_constants
, &num_pull_constants
,
2154 max_push_components
, max_chunk_size
,
2159 /* Then push the rest of uniforms */
2160 for (unsigned u
= 0; u
< uniforms
; u
++) {
2161 if (!is_live
[u
] || is_live_64bit
[u
])
2164 pull_constant_loc
[u
] = -1;
2165 push_constant_loc
[u
] = -1;
2167 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2168 push_constant_loc
, pull_constant_loc
,
2169 &num_push_constants
, &num_pull_constants
,
2170 max_push_components
, max_chunk_size
,
2174 /* As the uniforms are going to be reordered, take the data from a temporary
2175 * copy of the original param[].
2177 gl_constant_value
**param
= ralloc_array(NULL
, gl_constant_value
*,
2178 stage_prog_data
->nr_params
);
2179 memcpy(param
, stage_prog_data
->param
,
2180 sizeof(gl_constant_value
*) * stage_prog_data
->nr_params
);
2181 stage_prog_data
->nr_params
= num_push_constants
;
2182 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2184 /* Up until now, the param[] array has been indexed by reg + reg_offset
2185 * of UNIFORM registers. Move pull constants into pull_param[] and
2186 * condense param[] to only contain the uniforms we chose to push.
2188 * NOTE: Because we are condensing the params[] array, we know that
2189 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2190 * having to make a copy.
2192 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2193 const gl_constant_value
*value
= param
[i
];
2195 if (pull_constant_loc
[i
] != -1) {
2196 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2197 } else if (push_constant_loc
[i
] != -1) {
2198 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2205 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2206 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2209 fs_visitor::lower_constant_loads()
2211 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2213 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2214 /* Set up the annotation tracking for new generated instructions. */
2215 const fs_builder
ibld(this, block
, inst
);
2217 for (int i
= 0; i
< inst
->sources
; i
++) {
2218 if (inst
->src
[i
].file
!= UNIFORM
)
2221 /* We'll handle this case later */
2222 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2225 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2226 if (location
>= uniforms
)
2227 continue; /* Out of bounds access */
2229 int pull_index
= pull_constant_loc
[location
];
2231 if (pull_index
== -1)
2234 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2237 if (type_sz(inst
->src
[i
].type
) <= 4)
2238 dst
= vgrf(glsl_type::float_type
);
2240 dst
= vgrf(glsl_type::double_type
);
2242 assert(inst
->src
[i
].stride
== 0);
2244 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2245 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2246 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2247 dst
, brw_imm_ud(index
), offset
);
2249 /* Rewrite the instruction to use the temporary VGRF. */
2250 inst
->src
[i
].file
= VGRF
;
2251 inst
->src
[i
].nr
= dst
.nr
;
2252 inst
->src
[i
].reg_offset
= 0;
2253 inst
->src
[i
].set_smear(pull_index
& 3);
2255 brw_mark_surface_used(prog_data
, index
);
2258 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2259 inst
->src
[0].file
== UNIFORM
) {
2261 unsigned location
= inst
->src
[0].nr
+ inst
->src
[0].reg_offset
;
2262 if (location
>= uniforms
)
2263 continue; /* Out of bounds access */
2265 int pull_index
= pull_constant_loc
[location
];
2267 if (pull_index
== -1)
2270 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2274 inst
->remove(block
);
2276 brw_mark_surface_used(prog_data
, index
);
2279 invalidate_live_intervals();
2283 fs_visitor::opt_algebraic()
2285 bool progress
= false;
2287 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2288 switch (inst
->opcode
) {
2289 case BRW_OPCODE_MOV
:
2290 if (inst
->src
[0].file
!= IMM
)
2293 if (inst
->saturate
) {
2294 if (inst
->dst
.type
!= inst
->src
[0].type
)
2295 assert(!"unimplemented: saturate mixed types");
2297 if (brw_saturate_immediate(inst
->dst
.type
,
2298 &inst
->src
[0].as_brw_reg())) {
2299 inst
->saturate
= false;
2305 case BRW_OPCODE_MUL
:
2306 if (inst
->src
[1].file
!= IMM
)
2310 if (inst
->src
[1].is_one()) {
2311 inst
->opcode
= BRW_OPCODE_MOV
;
2312 inst
->src
[1] = reg_undef
;
2318 if (inst
->src
[1].is_negative_one()) {
2319 inst
->opcode
= BRW_OPCODE_MOV
;
2320 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2321 inst
->src
[1] = reg_undef
;
2327 if (inst
->src
[1].is_zero()) {
2328 inst
->opcode
= BRW_OPCODE_MOV
;
2329 inst
->src
[0] = inst
->src
[1];
2330 inst
->src
[1] = reg_undef
;
2335 if (inst
->src
[0].file
== IMM
) {
2336 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2337 inst
->opcode
= BRW_OPCODE_MOV
;
2338 inst
->src
[0].f
*= inst
->src
[1].f
;
2339 inst
->src
[1] = reg_undef
;
2344 case BRW_OPCODE_ADD
:
2345 if (inst
->src
[1].file
!= IMM
)
2349 if (inst
->src
[1].is_zero()) {
2350 inst
->opcode
= BRW_OPCODE_MOV
;
2351 inst
->src
[1] = reg_undef
;
2356 if (inst
->src
[0].file
== IMM
) {
2357 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2358 inst
->opcode
= BRW_OPCODE_MOV
;
2359 inst
->src
[0].f
+= inst
->src
[1].f
;
2360 inst
->src
[1] = reg_undef
;
2366 if (inst
->src
[0].equals(inst
->src
[1])) {
2367 inst
->opcode
= BRW_OPCODE_MOV
;
2368 inst
->src
[1] = reg_undef
;
2373 case BRW_OPCODE_LRP
:
2374 if (inst
->src
[1].equals(inst
->src
[2])) {
2375 inst
->opcode
= BRW_OPCODE_MOV
;
2376 inst
->src
[0] = inst
->src
[1];
2377 inst
->src
[1] = reg_undef
;
2378 inst
->src
[2] = reg_undef
;
2383 case BRW_OPCODE_CMP
:
2384 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2386 inst
->src
[0].negate
&&
2387 inst
->src
[1].is_zero()) {
2388 inst
->src
[0].abs
= false;
2389 inst
->src
[0].negate
= false;
2390 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2395 case BRW_OPCODE_SEL
:
2396 if (inst
->src
[0].equals(inst
->src
[1])) {
2397 inst
->opcode
= BRW_OPCODE_MOV
;
2398 inst
->src
[1] = reg_undef
;
2399 inst
->predicate
= BRW_PREDICATE_NONE
;
2400 inst
->predicate_inverse
= false;
2402 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2403 switch (inst
->conditional_mod
) {
2404 case BRW_CONDITIONAL_LE
:
2405 case BRW_CONDITIONAL_L
:
2406 switch (inst
->src
[1].type
) {
2407 case BRW_REGISTER_TYPE_F
:
2408 if (inst
->src
[1].f
>= 1.0f
) {
2409 inst
->opcode
= BRW_OPCODE_MOV
;
2410 inst
->src
[1] = reg_undef
;
2411 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2419 case BRW_CONDITIONAL_GE
:
2420 case BRW_CONDITIONAL_G
:
2421 switch (inst
->src
[1].type
) {
2422 case BRW_REGISTER_TYPE_F
:
2423 if (inst
->src
[1].f
<= 0.0f
) {
2424 inst
->opcode
= BRW_OPCODE_MOV
;
2425 inst
->src
[1] = reg_undef
;
2426 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2438 case BRW_OPCODE_MAD
:
2439 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2440 inst
->opcode
= BRW_OPCODE_MOV
;
2441 inst
->src
[1] = reg_undef
;
2442 inst
->src
[2] = reg_undef
;
2444 } else if (inst
->src
[0].is_zero()) {
2445 inst
->opcode
= BRW_OPCODE_MUL
;
2446 inst
->src
[0] = inst
->src
[2];
2447 inst
->src
[2] = reg_undef
;
2449 } else if (inst
->src
[1].is_one()) {
2450 inst
->opcode
= BRW_OPCODE_ADD
;
2451 inst
->src
[1] = inst
->src
[2];
2452 inst
->src
[2] = reg_undef
;
2454 } else if (inst
->src
[2].is_one()) {
2455 inst
->opcode
= BRW_OPCODE_ADD
;
2456 inst
->src
[2] = reg_undef
;
2458 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2459 inst
->opcode
= BRW_OPCODE_ADD
;
2460 inst
->src
[1].f
*= inst
->src
[2].f
;
2461 inst
->src
[2] = reg_undef
;
2465 case SHADER_OPCODE_BROADCAST
:
2466 if (is_uniform(inst
->src
[0])) {
2467 inst
->opcode
= BRW_OPCODE_MOV
;
2469 inst
->force_writemask_all
= true;
2471 } else if (inst
->src
[1].file
== IMM
) {
2472 inst
->opcode
= BRW_OPCODE_MOV
;
2473 inst
->src
[0] = component(inst
->src
[0],
2476 inst
->force_writemask_all
= true;
2485 /* Swap if src[0] is immediate. */
2486 if (progress
&& inst
->is_commutative()) {
2487 if (inst
->src
[0].file
== IMM
) {
2488 fs_reg tmp
= inst
->src
[1];
2489 inst
->src
[1] = inst
->src
[0];
2498 * Optimize sample messages that have constant zero values for the trailing
2499 * texture coordinates. We can just reduce the message length for these
2500 * instructions instead of reserving a register for it. Trailing parameters
2501 * that aren't sent default to zero anyway. This will cause the dead code
2502 * eliminator to remove the MOV instruction that would otherwise be emitted to
2503 * set up the zero value.
2506 fs_visitor::opt_zero_samples()
2508 /* Gen4 infers the texturing opcode based on the message length so we can't
2511 if (devinfo
->gen
< 5)
2514 bool progress
= false;
2516 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2517 if (!inst
->is_tex())
2520 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2522 if (load_payload
->is_head_sentinel() ||
2523 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2526 /* We don't want to remove the message header or the first parameter.
2527 * Removing the first parameter is not allowed, see the Haswell PRM
2528 * volume 7, page 149:
2530 * "Parameter 0 is required except for the sampleinfo message, which
2531 * has no parameter 0"
2533 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2534 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2535 (inst
->exec_size
/ 8) +
2536 inst
->header_size
- 1].is_zero()) {
2537 inst
->mlen
-= inst
->exec_size
/ 8;
2543 invalidate_live_intervals();
2549 * Optimize sample messages which are followed by the final RT write.
2551 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2552 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2553 * final texturing results copied to the framebuffer write payload and modify
2554 * them to write to the framebuffer directly.
2557 fs_visitor::opt_sampler_eot()
2559 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2561 if (stage
!= MESA_SHADER_FRAGMENT
)
2564 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2567 /* FINISHME: It should be possible to implement this optimization when there
2568 * are multiple drawbuffers.
2570 if (key
->nr_color_regions
!= 1)
2573 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2574 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2575 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2576 assert(fb_write
->eot
);
2577 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2579 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2581 /* There wasn't one; nothing to do. */
2582 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2585 /* 3D Sampler » Messages » Message Format
2587 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2588 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2590 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2591 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2592 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2593 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2594 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2597 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2598 * It's very likely to be the previous instruction.
2600 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2601 if (load_payload
->is_head_sentinel() ||
2602 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2605 assert(!tex_inst
->eot
); /* We can't get here twice */
2606 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2608 const fs_builder
ibld(this, block
, tex_inst
);
2610 tex_inst
->offset
|= fb_write
->target
<< 24;
2611 tex_inst
->eot
= true;
2612 tex_inst
->dst
= ibld
.null_reg_ud();
2613 tex_inst
->regs_written
= 0;
2614 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2616 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2617 * to create a new LOAD_PAYLOAD command with the same sources and a space
2618 * saved for the header. Using a new destination register not only makes sure
2619 * we have enough space, but it will make sure the dead code eliminator kills
2620 * the instruction that this will replace.
2622 if (tex_inst
->header_size
!= 0) {
2623 invalidate_live_intervals();
2627 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2628 load_payload
->sources
+ 1);
2629 fs_reg
*new_sources
=
2630 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2632 new_sources
[0] = fs_reg();
2633 for (int i
= 0; i
< load_payload
->sources
; i
++)
2634 new_sources
[i
+1] = load_payload
->src
[i
];
2636 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2637 * requires a lot of information about the sources to appropriately figure
2638 * out the number of registers needed to be used. Given this stage in our
2639 * optimization, we may not have the appropriate GRFs required by
2640 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2641 * manually emit the instruction.
2643 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2644 load_payload
->exec_size
,
2647 load_payload
->sources
+ 1);
2649 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2650 new_load_payload
->header_size
= 1;
2652 tex_inst
->header_size
= 1;
2653 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2654 tex_inst
->src
[0] = send_header
;
2656 invalidate_live_intervals();
2661 fs_visitor::opt_register_renaming()
2663 bool progress
= false;
2666 int remap
[alloc
.count
];
2667 memset(remap
, -1, sizeof(int) * alloc
.count
);
2669 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2670 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2672 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2673 inst
->opcode
== BRW_OPCODE_WHILE
) {
2677 /* Rewrite instruction sources. */
2678 for (int i
= 0; i
< inst
->sources
; i
++) {
2679 if (inst
->src
[i
].file
== VGRF
&&
2680 remap
[inst
->src
[i
].nr
] != -1 &&
2681 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2682 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2687 const int dst
= inst
->dst
.nr
;
2690 inst
->dst
.file
== VGRF
&&
2691 alloc
.sizes
[inst
->dst
.nr
] == inst
->exec_size
/ 8 &&
2692 !inst
->is_partial_write()) {
2693 if (remap
[dst
] == -1) {
2696 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2697 inst
->dst
.nr
= remap
[dst
];
2700 } else if (inst
->dst
.file
== VGRF
&&
2702 remap
[dst
] != dst
) {
2703 inst
->dst
.nr
= remap
[dst
];
2709 invalidate_live_intervals();
2711 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2712 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2713 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2722 * Remove redundant or useless discard jumps.
2724 * For example, we can eliminate jumps in the following sequence:
2726 * discard-jump (redundant with the next jump)
2727 * discard-jump (useless; jumps to the next instruction)
2731 fs_visitor::opt_redundant_discard_jumps()
2733 bool progress
= false;
2735 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2737 fs_inst
*placeholder_halt
= NULL
;
2738 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2739 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2740 placeholder_halt
= inst
;
2745 if (!placeholder_halt
)
2748 /* Delete any HALTs immediately before the placeholder halt. */
2749 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2750 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2751 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2752 prev
->remove(last_bblock
);
2757 invalidate_live_intervals();
2763 fs_visitor::compute_to_mrf()
2765 bool progress
= false;
2768 /* No MRFs on Gen >= 7. */
2769 if (devinfo
->gen
>= 7)
2772 calculate_live_intervals();
2774 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2778 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2779 inst
->is_partial_write() ||
2780 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2781 inst
->dst
.type
!= inst
->src
[0].type
||
2782 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2783 !inst
->src
[0].is_contiguous() ||
2784 inst
->src
[0].subreg_offset
)
2787 /* Work out which hardware MRF registers are written by this
2790 int mrf_low
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2792 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2793 mrf_high
= mrf_low
+ 4;
2794 } else if (inst
->exec_size
== 16) {
2795 mrf_high
= mrf_low
+ 1;
2800 /* Can't compute-to-MRF this GRF if someone else was going to
2803 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2806 /* Found a move of a GRF to a MRF. Let's see if we can go
2807 * rewrite the thing that made this GRF to write into the MRF.
2809 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2810 if (scan_inst
->dst
.file
== VGRF
&&
2811 scan_inst
->dst
.nr
== inst
->src
[0].nr
) {
2812 /* Found the last thing to write our reg we want to turn
2813 * into a compute-to-MRF.
2816 /* If this one instruction didn't populate all the
2817 * channels, bail. We might be able to rewrite everything
2818 * that writes that reg, but it would require smarter
2819 * tracking to delay the rewriting until complete success.
2821 if (scan_inst
->is_partial_write())
2824 /* Things returning more than one register would need us to
2825 * understand coalescing out more than one MOV at a time.
2827 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2830 /* SEND instructions can't have MRF as a destination. */
2831 if (scan_inst
->mlen
)
2834 if (devinfo
->gen
== 6) {
2835 /* gen6 math instructions must have the destination be
2836 * GRF, so no compute-to-MRF for them.
2838 if (scan_inst
->is_math()) {
2843 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2844 /* Found the creator of our MRF's source value. */
2845 scan_inst
->dst
.file
= MRF
;
2846 scan_inst
->dst
.nr
= inst
->dst
.nr
;
2847 scan_inst
->saturate
|= inst
->saturate
;
2848 inst
->remove(block
);
2854 /* We don't handle control flow here. Most computation of
2855 * values that end up in MRFs are shortly before the MRF
2858 if (block
->start() == scan_inst
)
2861 /* You can't read from an MRF, so if someone else reads our
2862 * MRF's source GRF that we wanted to rewrite, that stops us.
2864 bool interfered
= false;
2865 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2866 if (scan_inst
->src
[i
].file
== VGRF
&&
2867 scan_inst
->src
[i
].nr
== inst
->src
[0].nr
&&
2868 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2875 if (scan_inst
->dst
.file
== MRF
) {
2876 /* If somebody else writes our MRF here, we can't
2877 * compute-to-MRF before that.
2879 int scan_mrf_low
= scan_inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2882 if (scan_inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2883 scan_mrf_high
= scan_mrf_low
+ 4;
2884 } else if (scan_inst
->exec_size
== 16) {
2885 scan_mrf_high
= scan_mrf_low
+ 1;
2887 scan_mrf_high
= scan_mrf_low
;
2890 if (mrf_low
== scan_mrf_low
||
2891 mrf_low
== scan_mrf_high
||
2892 mrf_high
== scan_mrf_low
||
2893 mrf_high
== scan_mrf_high
) {
2898 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2899 /* Found a SEND instruction, which means that there are
2900 * live values in MRFs from base_mrf to base_mrf +
2901 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2904 if (mrf_low
>= scan_inst
->base_mrf
&&
2905 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2908 if (mrf_high
>= scan_inst
->base_mrf
&&
2909 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2917 invalidate_live_intervals();
2923 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2924 * flow. We could probably do better here with some form of divergence
2928 fs_visitor::eliminate_find_live_channel()
2930 bool progress
= false;
2933 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2934 switch (inst
->opcode
) {
2940 case BRW_OPCODE_ENDIF
:
2941 case BRW_OPCODE_WHILE
:
2945 case FS_OPCODE_DISCARD_JUMP
:
2946 /* This can potentially make control flow non-uniform until the end
2951 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2953 inst
->opcode
= BRW_OPCODE_MOV
;
2954 inst
->src
[0] = brw_imm_ud(0u);
2956 inst
->force_writemask_all
= true;
2970 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2971 * instructions to FS_OPCODE_REP_FB_WRITE.
2974 fs_visitor::emit_repclear_shader()
2976 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2978 int color_mrf
= base_mrf
+ 2;
2982 mov
= bld
.exec_all().group(4, 0)
2983 .MOV(brw_message_reg(color_mrf
),
2984 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2986 struct brw_reg reg
=
2987 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2988 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
2989 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2991 mov
= bld
.exec_all().group(4, 0)
2992 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2996 if (key
->nr_color_regions
== 1) {
2997 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2998 write
->saturate
= key
->clamp_fragment_color
;
2999 write
->base_mrf
= color_mrf
;
3001 write
->header_size
= 0;
3004 assume(key
->nr_color_regions
> 0);
3005 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3006 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3007 write
->saturate
= key
->clamp_fragment_color
;
3008 write
->base_mrf
= base_mrf
;
3010 write
->header_size
= 2;
3018 assign_constant_locations();
3019 assign_curb_setup();
3021 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3023 assert(mov
->src
[0].file
== FIXED_GRF
);
3024 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3029 * Walks through basic blocks, looking for repeated MRF writes and
3030 * removing the later ones.
3033 fs_visitor::remove_duplicate_mrf_writes()
3035 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3036 bool progress
= false;
3038 /* Need to update the MRF tracking for compressed instructions. */
3039 if (dispatch_width
== 16)
3042 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3044 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3045 if (inst
->is_control_flow()) {
3046 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3049 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3050 inst
->dst
.file
== MRF
) {
3051 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3052 if (prev_inst
&& inst
->equals(prev_inst
)) {
3053 inst
->remove(block
);
3059 /* Clear out the last-write records for MRFs that were overwritten. */
3060 if (inst
->dst
.file
== MRF
) {
3061 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3064 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3065 /* Found a SEND instruction, which will include two or fewer
3066 * implied MRF writes. We could do better here.
3068 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3069 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3073 /* Clear out any MRF move records whose sources got overwritten. */
3074 if (inst
->dst
.file
== VGRF
) {
3075 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3076 if (last_mrf_move
[i
] &&
3077 last_mrf_move
[i
]->src
[0].nr
== inst
->dst
.nr
) {
3078 last_mrf_move
[i
] = NULL
;
3083 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3084 inst
->dst
.file
== MRF
&&
3085 inst
->src
[0].file
== VGRF
&&
3086 !inst
->is_partial_write()) {
3087 last_mrf_move
[inst
->dst
.nr
] = inst
;
3092 invalidate_live_intervals();
3098 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3100 /* Clear the flag for registers that actually got read (as expected). */
3101 for (int i
= 0; i
< inst
->sources
; i
++) {
3103 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3104 grf
= inst
->src
[i
].nr
;
3109 if (grf
>= first_grf
&&
3110 grf
< first_grf
+ grf_len
) {
3111 deps
[grf
- first_grf
] = false;
3112 if (inst
->exec_size
== 16)
3113 deps
[grf
- first_grf
+ 1] = false;
3119 * Implements this workaround for the original 965:
3121 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3122 * check for post destination dependencies on this instruction, software
3123 * must ensure that there is no destination hazard for the case of ‘write
3124 * followed by a posted write’ shown in the following example.
3127 * 2. send r3.xy <rest of send instruction>
3130 * Due to no post-destination dependency check on the ‘send’, the above
3131 * code sequence could have two instructions (1 and 2) in flight at the
3132 * same time that both consider ‘r3’ as the target of their final writes.
3135 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3138 int write_len
= inst
->regs_written
;
3139 int first_write_grf
= inst
->dst
.nr
;
3140 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3141 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3143 memset(needs_dep
, false, sizeof(needs_dep
));
3144 memset(needs_dep
, true, write_len
);
3146 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3148 /* Walk backwards looking for writes to registers we're writing which
3149 * aren't read since being written. If we hit the start of the program,
3150 * we assume that there are no outstanding dependencies on entry to the
3153 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3154 /* If we hit control flow, assume that there *are* outstanding
3155 * dependencies, and force their cleanup before our instruction.
3157 if (block
->start() == scan_inst
) {
3158 for (int i
= 0; i
< write_len
; i
++) {
3160 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3161 first_write_grf
+ i
);
3166 /* We insert our reads as late as possible on the assumption that any
3167 * instruction but a MOV that might have left us an outstanding
3168 * dependency has more latency than a MOV.
3170 if (scan_inst
->dst
.file
== VGRF
) {
3171 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
3172 int reg
= scan_inst
->dst
.nr
+ i
;
3174 if (reg
>= first_write_grf
&&
3175 reg
< first_write_grf
+ write_len
&&
3176 needs_dep
[reg
- first_write_grf
]) {
3177 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3178 needs_dep
[reg
- first_write_grf
] = false;
3179 if (scan_inst
->exec_size
== 16)
3180 needs_dep
[reg
- first_write_grf
+ 1] = false;
3185 /* Clear the flag for registers that actually got read (as expected). */
3186 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3188 /* Continue the loop only if we haven't resolved all the dependencies */
3190 for (i
= 0; i
< write_len
; i
++) {
3200 * Implements this workaround for the original 965:
3202 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3203 * used as a destination register until after it has been sourced by an
3204 * instruction with a different destination register.
3207 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3209 int write_len
= inst
->regs_written
;
3210 int first_write_grf
= inst
->dst
.nr
;
3211 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3212 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3214 memset(needs_dep
, false, sizeof(needs_dep
));
3215 memset(needs_dep
, true, write_len
);
3216 /* Walk forwards looking for writes to registers we're writing which aren't
3217 * read before being written.
3219 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3220 /* If we hit control flow, force resolve all remaining dependencies. */
3221 if (block
->end() == scan_inst
) {
3222 for (int i
= 0; i
< write_len
; i
++) {
3224 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3225 first_write_grf
+ i
);
3230 /* Clear the flag for registers that actually got read (as expected). */
3231 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3233 /* We insert our reads as late as possible since they're reading the
3234 * result of a SEND, which has massive latency.
3236 if (scan_inst
->dst
.file
== VGRF
&&
3237 scan_inst
->dst
.nr
>= first_write_grf
&&
3238 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3239 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3240 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3242 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3245 /* Continue the loop only if we haven't resolved all the dependencies */
3247 for (i
= 0; i
< write_len
; i
++) {
3257 fs_visitor::insert_gen4_send_dependency_workarounds()
3259 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3262 bool progress
= false;
3264 /* Note that we're done with register allocation, so GRF fs_regs always
3265 * have a .reg_offset of 0.
3268 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3269 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3270 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3271 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3277 invalidate_live_intervals();
3281 * Turns the generic expression-style uniform pull constant load instruction
3282 * into a hardware-specific series of instructions for loading a pull
3285 * The expression style allows the CSE pass before this to optimize out
3286 * repeated loads from the same offset, and gives the pre-register-allocation
3287 * scheduling full flexibility, while the conversion to native instructions
3288 * allows the post-register-allocation scheduler the best information
3291 * Note that execution masking for setting up pull constant loads is special:
3292 * the channels that need to be written are unrelated to the current execution
3293 * mask, since a later instruction will use one of the result channels as a
3294 * source operand for all 8 or 16 of its channels.
3297 fs_visitor::lower_uniform_pull_constant_loads()
3299 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3300 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3303 if (devinfo
->gen
>= 7) {
3304 /* The offset arg is a vec4-aligned immediate byte offset. */
3305 fs_reg const_offset_reg
= inst
->src
[1];
3306 assert(const_offset_reg
.file
== IMM
&&
3307 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3308 assert(const_offset_reg
.ud
% 16 == 0);
3310 fs_reg payload
, offset
;
3311 if (devinfo
->gen
>= 9) {
3312 /* We have to use a message header on Skylake to get SIMD4x2
3313 * mode. Reserve space for the register.
3315 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3316 offset
.reg_offset
++;
3319 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3323 /* This is actually going to be a MOV, but since only the first dword
3324 * is accessed, we have a special opcode to do just that one. Note
3325 * that this needs to be an operation that will be considered a def
3326 * by live variable analysis, or register allocation will explode.
3328 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3329 8, offset
, const_offset_reg
);
3330 setup
->force_writemask_all
= true;
3332 setup
->ir
= inst
->ir
;
3333 setup
->annotation
= inst
->annotation
;
3334 inst
->insert_before(block
, setup
);
3336 /* Similarly, this will only populate the first 4 channels of the
3337 * result register (since we only use smear values from 0-3), but we
3338 * don't tell the optimizer.
3340 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3341 inst
->src
[1] = payload
;
3342 inst
->base_mrf
= -1;
3344 invalidate_live_intervals();
3346 /* Before register allocation, we didn't tell the scheduler about the
3347 * MRF we use. We know it's safe to use this MRF because nothing
3348 * else does except for register spill/unspill, which generates and
3349 * uses its MRF within a single IR instruction.
3351 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3358 fs_visitor::lower_load_payload()
3360 bool progress
= false;
3362 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3363 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3366 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3367 assert(inst
->saturate
== false);
3368 fs_reg dst
= inst
->dst
;
3370 /* Get rid of COMPR4. We'll add it back in if we need it */
3371 if (dst
.file
== MRF
)
3372 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3374 const fs_builder
ibld(this, block
, inst
);
3375 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3377 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3378 if (inst
->src
[i
].file
!= BAD_FILE
) {
3379 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3380 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3381 hbld
.MOV(mov_dst
, mov_src
);
3383 dst
= offset(dst
, hbld
, 1);
3386 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3387 inst
->exec_size
> 8) {
3388 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3389 * a straightforward copy. Instead, the result of the
3390 * LOAD_PAYLOAD is treated as interleaved and the first four
3391 * non-header sources are unpacked as:
3402 * This is used for gen <= 5 fb writes.
3404 assert(inst
->exec_size
== 16);
3405 assert(inst
->header_size
+ 4 <= inst
->sources
);
3406 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3407 if (inst
->src
[i
].file
!= BAD_FILE
) {
3408 if (devinfo
->has_compr4
) {
3409 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3410 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3411 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3413 /* Platform doesn't have COMPR4. We have to fake it */
3414 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3415 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3417 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3424 /* The loop above only ever incremented us through the first set
3425 * of 4 registers. However, thanks to the magic of COMPR4, we
3426 * actually wrote to the first 8 registers, so we need to take
3427 * that into account now.
3431 /* The COMPR4 code took care of the first 4 sources. We'll let
3432 * the regular path handle any remaining sources. Yes, we are
3433 * modifying the instruction but we're about to delete it so
3434 * this really doesn't hurt anything.
3436 inst
->header_size
+= 4;
3439 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3440 if (inst
->src
[i
].file
!= BAD_FILE
)
3441 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3442 dst
= offset(dst
, ibld
, 1);
3445 inst
->remove(block
);
3450 invalidate_live_intervals();
3456 fs_visitor::lower_integer_multiplication()
3458 bool progress
= false;
3460 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3461 const fs_builder
ibld(this, block
, inst
);
3463 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3464 if (inst
->dst
.is_accumulator() ||
3465 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3466 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3469 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3470 * operation directly, but CHV/BXT cannot.
3472 if (devinfo
->gen
>= 8 &&
3473 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3476 if (inst
->src
[1].file
== IMM
&&
3477 inst
->src
[1].ud
< (1 << 16)) {
3478 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3479 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3482 * If multiplying by an immediate value that fits in 16-bits, do a
3483 * single MUL instruction with that value in the proper location.
3485 if (devinfo
->gen
< 7) {
3486 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3488 ibld
.MOV(imm
, inst
->src
[1]);
3489 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3491 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3494 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3495 * do 32-bit integer multiplication in one instruction, but instead
3496 * must do a sequence (which actually calculates a 64-bit result):
3498 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3499 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3500 * mov(8) g2<1>D acc0<8,8,1>D
3502 * But on Gen > 6, the ability to use second accumulator register
3503 * (acc1) for non-float data types was removed, preventing a simple
3504 * implementation in SIMD16. A 16-channel result can be calculated by
3505 * executing the three instructions twice in SIMD8, once with quarter
3506 * control of 1Q for the first eight channels and again with 2Q for
3507 * the second eight channels.
3509 * Which accumulator register is implicitly accessed (by AccWrEnable
3510 * for instance) is determined by the quarter control. Unfortunately
3511 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3512 * implicit accumulator access by an instruction with 2Q will access
3513 * acc1 regardless of whether the data type is usable in acc1.
3515 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3516 * integer data types.
3518 * Since we only want the low 32-bits of the result, we can do two
3519 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3520 * adjust the high result and add them (like the mach is doing):
3522 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3523 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3524 * shl(8) g9<1>D g8<8,8,1>D 16D
3525 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3527 * We avoid the shl instruction by realizing that we only want to add
3528 * the low 16-bits of the "high" result to the high 16-bits of the
3529 * "low" result and using proper regioning on the add:
3531 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3532 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3533 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3535 * Since it does not use the (single) accumulator register, we can
3536 * schedule multi-component multiplications much better.
3539 fs_reg orig_dst
= inst
->dst
;
3540 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3541 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3544 fs_reg low
= inst
->dst
;
3545 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3548 if (devinfo
->gen
>= 7) {
3549 fs_reg src1_0_w
= inst
->src
[1];
3550 fs_reg src1_1_w
= inst
->src
[1];
3552 if (inst
->src
[1].file
== IMM
) {
3553 src1_0_w
.ud
&= 0xffff;
3556 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3557 if (src1_0_w
.stride
!= 0) {
3558 assert(src1_0_w
.stride
== 1);
3559 src1_0_w
.stride
= 2;
3562 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3563 if (src1_1_w
.stride
!= 0) {
3564 assert(src1_1_w
.stride
== 1);
3565 src1_1_w
.stride
= 2;
3567 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3569 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3570 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3572 fs_reg src0_0_w
= inst
->src
[0];
3573 fs_reg src0_1_w
= inst
->src
[0];
3575 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3576 if (src0_0_w
.stride
!= 0) {
3577 assert(src0_0_w
.stride
== 1);
3578 src0_0_w
.stride
= 2;
3581 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3582 if (src0_1_w
.stride
!= 0) {
3583 assert(src0_1_w
.stride
== 1);
3584 src0_1_w
.stride
= 2;
3586 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3588 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3589 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3592 fs_reg dst
= inst
->dst
;
3593 dst
.type
= BRW_REGISTER_TYPE_UW
;
3594 dst
.subreg_offset
= 2;
3597 high
.type
= BRW_REGISTER_TYPE_UW
;
3600 low
.type
= BRW_REGISTER_TYPE_UW
;
3601 low
.subreg_offset
= 2;
3604 ibld
.ADD(dst
, low
, high
);
3606 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3607 set_condmod(inst
->conditional_mod
,
3608 ibld
.MOV(orig_dst
, inst
->dst
));
3612 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3613 /* Should have been lowered to 8-wide. */
3614 assert(inst
->exec_size
<= 8);
3615 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3617 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3618 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3620 if (devinfo
->gen
>= 8) {
3621 /* Until Gen8, integer multiplies read 32-bits from one source,
3622 * and 16-bits from the other, and relying on the MACH instruction
3623 * to generate the high bits of the result.
3625 * On Gen8, the multiply instruction does a full 32x32-bit
3626 * multiply, but in order to do a 64-bit multiply we can simulate
3627 * the previous behavior and then use a MACH instruction.
3629 * FINISHME: Don't use source modifiers on src1.
3631 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3632 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3633 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3634 mul
->src
[1].stride
*= 2;
3636 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3637 inst
->force_sechalf
) {
3638 /* Among other things the quarter control bits influence which
3639 * accumulator register is used by the hardware for instructions
3640 * that access the accumulator implicitly (e.g. MACH). A
3641 * second-half instruction would normally map to acc1, which
3642 * doesn't exist on Gen7 and up (the hardware does emulate it for
3643 * floating-point instructions *only* by taking advantage of the
3644 * extra precision of acc0 not normally used for floating point
3647 * HSW and up are careful enough not to try to access an
3648 * accumulator register that doesn't exist, but on earlier Gen7
3649 * hardware we need to make sure that the quarter control bits are
3650 * zero to avoid non-deterministic behaviour and emit an extra MOV
3651 * to get the result masked correctly according to the current
3654 mach
->force_sechalf
= false;
3655 mach
->force_writemask_all
= true;
3656 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3657 ibld
.MOV(inst
->dst
, mach
->dst
);
3663 inst
->remove(block
);
3668 invalidate_live_intervals();
3674 fs_visitor::lower_minmax()
3676 assert(devinfo
->gen
< 6);
3678 bool progress
= false;
3680 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3681 const fs_builder
ibld(this, block
, inst
);
3683 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3684 inst
->predicate
== BRW_PREDICATE_NONE
) {
3685 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3686 * the original SEL.L/GE instruction
3688 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3689 inst
->conditional_mod
);
3690 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3691 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3698 invalidate_live_intervals();
3704 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3705 fs_reg
*dst
, fs_reg color
, unsigned components
)
3707 if (key
->clamp_fragment_color
) {
3708 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3709 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3711 for (unsigned i
= 0; i
< components
; i
++)
3713 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3718 for (unsigned i
= 0; i
< components
; i
++)
3719 dst
[i
] = offset(color
, bld
, i
);
3723 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3724 const brw_wm_prog_data
*prog_data
,
3725 const brw_wm_prog_key
*key
,
3726 const fs_visitor::thread_payload
&payload
)
3728 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3729 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3730 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3731 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3732 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3733 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3734 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3735 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3736 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3737 const unsigned components
=
3738 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3740 /* We can potentially have a message length of up to 15, so we have to set
3741 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3744 int header_size
= 2, payload_header_size
;
3745 unsigned length
= 0;
3747 /* From the Sandy Bridge PRM, volume 4, page 198:
3749 * "Dispatched Pixel Enables. One bit per pixel indicating
3750 * which pixels were originally enabled when the thread was
3751 * dispatched. This field is only required for the end-of-
3752 * thread message and on all dual-source messages."
3754 if (devinfo
->gen
>= 6 &&
3755 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3756 color1
.file
== BAD_FILE
&&
3757 key
->nr_color_regions
== 1) {
3761 if (header_size
!= 0) {
3762 assert(header_size
== 2);
3763 /* Allocate 2 registers for a header */
3767 if (payload
.aa_dest_stencil_reg
) {
3768 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3769 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3770 .MOV(sources
[length
],
3771 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3775 if (prog_data
->uses_omask
) {
3776 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3777 BRW_REGISTER_TYPE_UD
);
3779 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3780 * relevant. Since it's unsigned single words one vgrf is always
3781 * 16-wide, but only the lower or higher 8 channels will be used by the
3782 * hardware when doing a SIMD8 write depending on whether we have
3783 * selected the subspans for the first or second half respectively.
3785 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3786 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3787 sample_mask
.stride
*= 2;
3789 bld
.exec_all().annotate("FB write oMask")
3790 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3791 inst
->force_sechalf
),
3796 payload_header_size
= length
;
3798 if (src0_alpha
.file
!= BAD_FILE
) {
3799 /* FIXME: This is being passed at the wrong location in the payload and
3800 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3801 * It's supposed to be immediately before oMask but there seems to be no
3802 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3803 * requires header sources to form a contiguous segment at the beginning
3804 * of the message and src0_alpha has per-channel semantics.
3806 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3810 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3813 if (color1
.file
!= BAD_FILE
) {
3814 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3818 if (src_depth
.file
!= BAD_FILE
) {
3819 sources
[length
] = src_depth
;
3823 if (dst_depth
.file
!= BAD_FILE
) {
3824 sources
[length
] = dst_depth
;
3828 if (src_stencil
.file
!= BAD_FILE
) {
3829 assert(devinfo
->gen
>= 9);
3830 assert(bld
.dispatch_width() != 16);
3832 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3833 * available on gen9+. As such it's impossible to have both enabled at the
3834 * same time and therefore length cannot overrun the array.
3836 assert(length
< 15);
3838 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3839 bld
.exec_all().annotate("FB write OS")
3840 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3841 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3846 if (devinfo
->gen
>= 7) {
3847 /* Send from the GRF */
3848 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3849 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3850 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3851 load
->dst
= payload
;
3853 inst
->src
[0] = payload
;
3854 inst
->resize_sources(1);
3855 inst
->base_mrf
= -1;
3857 /* Send from the MRF */
3858 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3859 sources
, length
, payload_header_size
);
3861 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3862 * will do this for us if we just give it a COMPR4 destination.
3864 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3865 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3867 inst
->resize_sources(0);
3871 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3872 inst
->mlen
= load
->regs_written
;
3873 inst
->header_size
= header_size
;
3877 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3878 const fs_reg
&coordinate
,
3879 const fs_reg
&shadow_c
,
3880 const fs_reg
&lod
, const fs_reg
&lod2
,
3881 const fs_reg
&surface
,
3882 const fs_reg
&sampler
,
3883 unsigned coord_components
,
3884 unsigned grad_components
)
3886 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3887 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3888 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3889 fs_reg msg_end
= msg_begin
;
3892 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3894 for (unsigned i
= 0; i
< coord_components
; i
++)
3895 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3896 offset(coordinate
, bld
, i
));
3898 msg_end
= offset(msg_end
, bld
, coord_components
);
3900 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3901 * require all three components to be present and zero if they are unused.
3903 if (coord_components
> 0 &&
3904 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3905 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3906 for (unsigned i
= coord_components
; i
< 3; i
++)
3907 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3909 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3912 if (op
== SHADER_OPCODE_TXD
) {
3913 /* TXD unsupported in SIMD16 mode. */
3914 assert(bld
.dispatch_width() == 8);
3916 /* the slots for u and v are always present, but r is optional */
3917 if (coord_components
< 2)
3918 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3921 * dPdx = dudx, dvdx, drdx
3922 * dPdy = dudy, dvdy, drdy
3924 * 1-arg: Does not exist.
3926 * 2-arg: dudx dvdx dudy dvdy
3927 * dPdx.x dPdx.y dPdy.x dPdy.y
3930 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3931 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3932 * m5 m6 m7 m8 m9 m10
3934 for (unsigned i
= 0; i
< grad_components
; i
++)
3935 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3937 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3939 for (unsigned i
= 0; i
< grad_components
; i
++)
3940 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3942 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3946 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3947 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3949 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3950 bld
.dispatch_width() == 16);
3952 const brw_reg_type type
=
3953 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3954 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3955 bld
.MOV(retype(msg_end
, type
), lod
);
3956 msg_end
= offset(msg_end
, bld
, 1);
3959 if (shadow_c
.file
!= BAD_FILE
) {
3960 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3961 /* There's no plain shadow compare message, so we use shadow
3962 * compare with a bias of 0.0.
3964 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3965 msg_end
= offset(msg_end
, bld
, 1);
3968 bld
.MOV(msg_end
, shadow_c
);
3969 msg_end
= offset(msg_end
, bld
, 1);
3973 inst
->src
[0] = reg_undef
;
3974 inst
->src
[1] = surface
;
3975 inst
->src
[2] = sampler
;
3976 inst
->resize_sources(3);
3977 inst
->base_mrf
= msg_begin
.nr
;
3978 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3979 inst
->header_size
= 1;
3983 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3985 const fs_reg
&shadow_c
,
3986 fs_reg lod
, fs_reg lod2
,
3987 const fs_reg
&sample_index
,
3988 const fs_reg
&surface
,
3989 const fs_reg
&sampler
,
3990 const fs_reg
&offset_value
,
3991 unsigned coord_components
,
3992 unsigned grad_components
)
3994 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3995 fs_reg msg_coords
= message
;
3996 unsigned header_size
= 0;
3998 if (offset_value
.file
!= BAD_FILE
) {
3999 /* The offsets set up by the visitor are in the m1 header, so we can't
4006 for (unsigned i
= 0; i
< coord_components
; i
++) {
4007 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
4008 coordinate
= offset(coordinate
, bld
, 1);
4010 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
4011 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
4013 if (shadow_c
.file
!= BAD_FILE
) {
4014 fs_reg msg_shadow
= msg_lod
;
4015 bld
.MOV(msg_shadow
, shadow_c
);
4016 msg_lod
= offset(msg_shadow
, bld
, 1);
4021 case SHADER_OPCODE_TXL
:
4023 bld
.MOV(msg_lod
, lod
);
4024 msg_end
= offset(msg_lod
, bld
, 1);
4026 case SHADER_OPCODE_TXD
:
4029 * dPdx = dudx, dvdx, drdx
4030 * dPdy = dudy, dvdy, drdy
4032 * Load up these values:
4033 * - dudx dudy dvdx dvdy drdx drdy
4034 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4037 for (unsigned i
= 0; i
< grad_components
; i
++) {
4038 bld
.MOV(msg_end
, lod
);
4039 lod
= offset(lod
, bld
, 1);
4040 msg_end
= offset(msg_end
, bld
, 1);
4042 bld
.MOV(msg_end
, lod2
);
4043 lod2
= offset(lod2
, bld
, 1);
4044 msg_end
= offset(msg_end
, bld
, 1);
4047 case SHADER_OPCODE_TXS
:
4048 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4049 bld
.MOV(msg_lod
, lod
);
4050 msg_end
= offset(msg_lod
, bld
, 1);
4052 case SHADER_OPCODE_TXF
:
4053 msg_lod
= offset(msg_coords
, bld
, 3);
4054 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4055 msg_end
= offset(msg_lod
, bld
, 1);
4057 case SHADER_OPCODE_TXF_CMS
:
4058 msg_lod
= offset(msg_coords
, bld
, 3);
4060 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4062 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4063 msg_end
= offset(msg_lod
, bld
, 2);
4070 inst
->src
[0] = reg_undef
;
4071 inst
->src
[1] = surface
;
4072 inst
->src
[2] = sampler
;
4073 inst
->resize_sources(3);
4074 inst
->base_mrf
= message
.nr
;
4075 inst
->mlen
= msg_end
.nr
- message
.nr
;
4076 inst
->header_size
= header_size
;
4078 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4079 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4083 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
4085 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4088 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4092 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4094 const fs_reg
&shadow_c
,
4095 fs_reg lod
, fs_reg lod2
,
4096 const fs_reg
&sample_index
,
4098 const fs_reg
&surface
,
4099 const fs_reg
&sampler
,
4100 fs_reg offset_value
,
4101 unsigned coord_components
,
4102 unsigned grad_components
)
4104 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4105 int reg_width
= bld
.dispatch_width() / 8;
4106 unsigned header_size
= 0, length
= 0;
4107 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4108 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4109 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4111 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4112 offset_value
.file
!= BAD_FILE
||
4113 is_high_sampler(devinfo
, sampler
)) {
4114 /* For general texture offsets (no txf workaround), we need a header to
4115 * put them in. Note that we're only reserving space for it in the
4116 * message payload as it will be initialized implicitly by the
4119 * TG4 needs to place its channel select in the header, for interaction
4120 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4121 * larger sampler numbers we need to offset the Sampler State Pointer in
4125 sources
[0] = fs_reg();
4128 /* If we're requesting fewer than four channels worth of response,
4129 * and we have an explicit header, we need to set up the sampler
4130 * writemask. It's reversed from normal: 1 means "don't write".
4132 if (inst
->regs_written
!= 4 * reg_width
) {
4133 assert((inst
->regs_written
% reg_width
) == 0);
4134 unsigned mask
= ~((1 << (inst
->regs_written
/ reg_width
)) - 1) & 0xf;
4135 inst
->offset
|= mask
<< 12;
4139 if (shadow_c
.file
!= BAD_FILE
) {
4140 bld
.MOV(sources
[length
], shadow_c
);
4144 bool coordinate_done
= false;
4146 /* The sampler can only meaningfully compute LOD for fragment shader
4147 * messages. For all other stages, we change the opcode to TXL and
4148 * hardcode the LOD to 0.
4150 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
4151 op
== SHADER_OPCODE_TEX
) {
4152 op
= SHADER_OPCODE_TXL
;
4153 lod
= brw_imm_f(0.0f
);
4156 /* Set up the LOD info */
4159 case SHADER_OPCODE_TXL
:
4160 bld
.MOV(sources
[length
], lod
);
4163 case SHADER_OPCODE_TXD
:
4164 /* TXD should have been lowered in SIMD16 mode. */
4165 assert(bld
.dispatch_width() == 8);
4167 /* Load dPdx and the coordinate together:
4168 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4170 for (unsigned i
= 0; i
< coord_components
; i
++) {
4171 bld
.MOV(sources
[length
], coordinate
);
4172 coordinate
= offset(coordinate
, bld
, 1);
4175 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4176 * only derivatives for (u, v, r).
4178 if (i
< grad_components
) {
4179 bld
.MOV(sources
[length
], lod
);
4180 lod
= offset(lod
, bld
, 1);
4183 bld
.MOV(sources
[length
], lod2
);
4184 lod2
= offset(lod2
, bld
, 1);
4189 coordinate_done
= true;
4191 case SHADER_OPCODE_TXS
:
4192 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4195 case SHADER_OPCODE_TXF
:
4196 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4197 * On Gen9 they are u, v, lod, r
4199 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4200 coordinate
= offset(coordinate
, bld
, 1);
4203 if (devinfo
->gen
>= 9) {
4204 if (coord_components
>= 2) {
4205 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4206 coordinate
= offset(coordinate
, bld
, 1);
4211 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4214 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
4215 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4216 coordinate
= offset(coordinate
, bld
, 1);
4220 coordinate_done
= true;
4222 case SHADER_OPCODE_TXF_CMS
:
4223 case SHADER_OPCODE_TXF_CMS_W
:
4224 case SHADER_OPCODE_TXF_UMS
:
4225 case SHADER_OPCODE_TXF_MCS
:
4226 if (op
== SHADER_OPCODE_TXF_UMS
||
4227 op
== SHADER_OPCODE_TXF_CMS
||
4228 op
== SHADER_OPCODE_TXF_CMS_W
) {
4229 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4233 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4234 /* Data from the multisample control surface. */
4235 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4238 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4241 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4242 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4245 offset(mcs
, bld
, 1));
4250 /* There is no offsetting for this message; just copy in the integer
4251 * texture coordinates.
4253 for (unsigned i
= 0; i
< coord_components
; i
++) {
4254 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4255 coordinate
= offset(coordinate
, bld
, 1);
4259 coordinate_done
= true;
4261 case SHADER_OPCODE_TG4_OFFSET
:
4262 /* gather4_po_c should have been lowered in SIMD16 mode. */
4263 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
4265 /* More crazy intermixing */
4266 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
4267 bld
.MOV(sources
[length
], coordinate
);
4268 coordinate
= offset(coordinate
, bld
, 1);
4272 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
4273 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
4274 offset_value
= offset(offset_value
, bld
, 1);
4278 if (coord_components
== 3) { /* r if present */
4279 bld
.MOV(sources
[length
], coordinate
);
4280 coordinate
= offset(coordinate
, bld
, 1);
4284 coordinate_done
= true;
4290 /* Set up the coordinate (except for cases where it was done above) */
4291 if (!coordinate_done
) {
4292 for (unsigned i
= 0; i
< coord_components
; i
++) {
4293 bld
.MOV(sources
[length
], coordinate
);
4294 coordinate
= offset(coordinate
, bld
, 1);
4301 mlen
= length
* reg_width
- header_size
;
4303 mlen
= length
* reg_width
;
4305 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4306 BRW_REGISTER_TYPE_F
);
4307 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4309 /* Generate the SEND. */
4311 inst
->src
[0] = src_payload
;
4312 inst
->src
[1] = surface
;
4313 inst
->src
[2] = sampler
;
4314 inst
->resize_sources(3);
4315 inst
->base_mrf
= -1;
4317 inst
->header_size
= header_size
;
4319 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4320 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4324 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4326 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4327 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4328 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4329 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4330 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4331 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4332 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4333 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4334 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4335 const fs_reg
&offset_value
= inst
->src
[TEX_LOGICAL_SRC_OFFSET_VALUE
];
4336 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4337 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4338 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4339 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4341 if (devinfo
->gen
>= 7) {
4342 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4343 shadow_c
, lod
, lod2
, sample_index
,
4344 mcs
, surface
, sampler
, offset_value
,
4345 coord_components
, grad_components
);
4346 } else if (devinfo
->gen
>= 5) {
4347 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4348 shadow_c
, lod
, lod2
, sample_index
,
4349 surface
, sampler
, offset_value
,
4350 coord_components
, grad_components
);
4352 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4353 shadow_c
, lod
, lod2
,
4355 coord_components
, grad_components
);
4360 * Initialize the header present in some typed and untyped surface
4364 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4366 fs_builder ubld
= bld
.exec_all().group(8, 0);
4367 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4368 ubld
.MOV(dst
, brw_imm_d(0));
4369 ubld
.MOV(component(dst
, 7), sample_mask
);
4374 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4375 const fs_reg
&sample_mask
)
4377 /* Get the logical send arguments. */
4378 const fs_reg
&addr
= inst
->src
[0];
4379 const fs_reg
&src
= inst
->src
[1];
4380 const fs_reg
&surface
= inst
->src
[2];
4381 const UNUSED fs_reg
&dims
= inst
->src
[3];
4382 const fs_reg
&arg
= inst
->src
[4];
4384 /* Calculate the total number of components of the payload. */
4385 const unsigned addr_sz
= inst
->components_read(0);
4386 const unsigned src_sz
= inst
->components_read(1);
4387 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4388 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4390 /* Allocate space for the payload. */
4391 fs_reg
*const components
= new fs_reg
[sz
];
4392 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4395 /* Construct the payload. */
4397 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4399 for (unsigned i
= 0; i
< addr_sz
; i
++)
4400 components
[n
++] = offset(addr
, bld
, i
);
4402 for (unsigned i
= 0; i
< src_sz
; i
++)
4403 components
[n
++] = offset(src
, bld
, i
);
4405 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4407 /* Update the original instruction. */
4409 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4410 inst
->header_size
= header_sz
;
4412 inst
->src
[0] = payload
;
4413 inst
->src
[1] = surface
;
4415 inst
->resize_sources(3);
4417 delete[] components
;
4421 fs_visitor::lower_logical_sends()
4423 bool progress
= false;
4425 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4426 const fs_builder
ibld(this, block
, inst
);
4428 switch (inst
->opcode
) {
4429 case FS_OPCODE_FB_WRITE_LOGICAL
:
4430 assert(stage
== MESA_SHADER_FRAGMENT
);
4431 lower_fb_write_logical_send(ibld
, inst
,
4432 (const brw_wm_prog_data
*)prog_data
,
4433 (const brw_wm_prog_key
*)key
,
4437 case SHADER_OPCODE_TEX_LOGICAL
:
4438 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4441 case SHADER_OPCODE_TXD_LOGICAL
:
4442 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4445 case SHADER_OPCODE_TXF_LOGICAL
:
4446 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4449 case SHADER_OPCODE_TXL_LOGICAL
:
4450 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4453 case SHADER_OPCODE_TXS_LOGICAL
:
4454 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4457 case FS_OPCODE_TXB_LOGICAL
:
4458 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4461 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4462 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4465 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4466 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4469 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4470 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4473 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4474 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4477 case SHADER_OPCODE_LOD_LOGICAL
:
4478 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4481 case SHADER_OPCODE_TG4_LOGICAL
:
4482 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4485 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4486 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4489 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4490 lower_surface_logical_send(ibld
, inst
,
4491 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4495 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4496 lower_surface_logical_send(ibld
, inst
,
4497 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4498 ibld
.sample_mask_reg());
4501 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4502 lower_surface_logical_send(ibld
, inst
,
4503 SHADER_OPCODE_UNTYPED_ATOMIC
,
4504 ibld
.sample_mask_reg());
4507 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4508 lower_surface_logical_send(ibld
, inst
,
4509 SHADER_OPCODE_TYPED_SURFACE_READ
,
4513 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4514 lower_surface_logical_send(ibld
, inst
,
4515 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4516 ibld
.sample_mask_reg());
4519 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4520 lower_surface_logical_send(ibld
, inst
,
4521 SHADER_OPCODE_TYPED_ATOMIC
,
4522 ibld
.sample_mask_reg());
4533 invalidate_live_intervals();
4539 * Get the closest native SIMD width supported by the hardware for instruction
4540 * \p inst. The instruction will be left untouched by
4541 * fs_visitor::lower_simd_width() if the returned value is equal to the
4542 * original execution size.
4545 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4546 const fs_inst
*inst
)
4548 switch (inst
->opcode
) {
4549 case BRW_OPCODE_MOV
:
4550 case BRW_OPCODE_SEL
:
4551 case BRW_OPCODE_NOT
:
4552 case BRW_OPCODE_AND
:
4554 case BRW_OPCODE_XOR
:
4555 case BRW_OPCODE_SHR
:
4556 case BRW_OPCODE_SHL
:
4557 case BRW_OPCODE_ASR
:
4558 case BRW_OPCODE_CMP
:
4559 case BRW_OPCODE_CMPN
:
4560 case BRW_OPCODE_CSEL
:
4561 case BRW_OPCODE_F32TO16
:
4562 case BRW_OPCODE_F16TO32
:
4563 case BRW_OPCODE_BFREV
:
4564 case BRW_OPCODE_BFE
:
4565 case BRW_OPCODE_BFI1
:
4566 case BRW_OPCODE_BFI2
:
4567 case BRW_OPCODE_ADD
:
4568 case BRW_OPCODE_MUL
:
4569 case BRW_OPCODE_AVG
:
4570 case BRW_OPCODE_FRC
:
4571 case BRW_OPCODE_RNDU
:
4572 case BRW_OPCODE_RNDD
:
4573 case BRW_OPCODE_RNDE
:
4574 case BRW_OPCODE_RNDZ
:
4575 case BRW_OPCODE_LZD
:
4576 case BRW_OPCODE_FBH
:
4577 case BRW_OPCODE_FBL
:
4578 case BRW_OPCODE_CBIT
:
4579 case BRW_OPCODE_SAD2
:
4580 case BRW_OPCODE_MAD
:
4581 case BRW_OPCODE_LRP
:
4582 case SHADER_OPCODE_RCP
:
4583 case SHADER_OPCODE_RSQ
:
4584 case SHADER_OPCODE_SQRT
:
4585 case SHADER_OPCODE_EXP2
:
4586 case SHADER_OPCODE_LOG2
:
4587 case SHADER_OPCODE_POW
:
4588 case SHADER_OPCODE_INT_QUOTIENT
:
4589 case SHADER_OPCODE_INT_REMAINDER
:
4590 case SHADER_OPCODE_SIN
:
4591 case SHADER_OPCODE_COS
:
4592 case FS_OPCODE_PACK
: {
4593 /* According to the PRMs:
4594 * "A. In Direct Addressing mode, a source cannot span more than 2
4595 * adjacent GRF registers.
4596 * B. A destination cannot span more than 2 adjacent GRF registers."
4598 * Look for the source or destination with the largest register region
4599 * which is the one that is going to limit the overal execution size of
4600 * the instruction due to this rule.
4602 unsigned reg_count
= inst
->regs_written
;
4604 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4605 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4607 /* Calculate the maximum execution size of the instruction based on the
4608 * factor by which it goes over the hardware limit of 2 GRFs.
4610 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4612 case SHADER_OPCODE_MULH
:
4613 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4614 * is 8-wide on Gen7+.
4616 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4618 case FS_OPCODE_FB_WRITE_LOGICAL
:
4619 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4622 assert(devinfo
->gen
!= 6 ||
4623 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4624 inst
->exec_size
== 8);
4625 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4626 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4627 8 : inst
->exec_size
);
4629 case SHADER_OPCODE_TXD_LOGICAL
:
4630 /* TXD is unsupported in SIMD16 mode. */
4633 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4634 /* gather4_po_c is unsupported in SIMD16 mode. */
4635 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4636 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4638 case SHADER_OPCODE_TXL_LOGICAL
:
4639 case FS_OPCODE_TXB_LOGICAL
: {
4640 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4641 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4642 * mode because the message exceeds the maximum length of 11.
4644 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4645 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4647 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4650 return inst
->exec_size
;
4652 case SHADER_OPCODE_TXF_LOGICAL
:
4653 case SHADER_OPCODE_TXS_LOGICAL
:
4654 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4655 * messages. Use SIMD16 instead.
4657 if (devinfo
->gen
== 4)
4660 return inst
->exec_size
;
4662 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4663 /* This opcode can take up to 6 arguments which means that in some
4664 * circumstances it can end up with a message that is too long in SIMD16
4667 const unsigned coord_components
=
4668 inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4669 /* First three arguments are the sample index and the two arguments for
4672 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4675 return inst
->exec_size
;
4678 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4679 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4680 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4683 case SHADER_OPCODE_MOV_INDIRECT
:
4684 /* Prior to Broadwell, we only have 8 address subregisters */
4685 return devinfo
->gen
< 8 ? 8 : MIN2(inst
->exec_size
, 16);
4688 return inst
->exec_size
;
4693 * The \p rows array of registers represents a \p num_rows by \p num_columns
4694 * matrix in row-major order, write it in column-major order into the register
4695 * passed as destination. \p stride gives the separation between matrix
4696 * elements in the input in fs_builder::dispatch_width() units.
4699 emit_transpose(const fs_builder
&bld
,
4700 const fs_reg
&dst
, const fs_reg
*rows
,
4701 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4703 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4705 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4706 for (unsigned j
= 0; j
< num_rows
; ++j
)
4707 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4710 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4712 delete[] components
;
4716 fs_visitor::lower_simd_width()
4718 bool progress
= false;
4720 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4721 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4723 if (lower_width
!= inst
->exec_size
) {
4724 /* Builder matching the original instruction. We may also need to
4725 * emit an instruction of width larger than the original, set the
4726 * execution size of the builder to the highest of both for now so
4727 * we're sure that both cases can be handled.
4729 const fs_builder ibld
= bld
.at(block
, inst
)
4730 .exec_all(inst
->force_writemask_all
)
4731 .group(MAX2(inst
->exec_size
, lower_width
),
4732 inst
->force_sechalf
);
4734 /* Split the copies in chunks of the execution width of either the
4735 * original or the lowered instruction, whichever is lower.
4737 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4738 const unsigned n
= inst
->exec_size
/ copy_width
;
4739 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4740 inst
->dst
.component_size(inst
->exec_size
);
4743 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4744 !inst
->writes_accumulator
&& !inst
->mlen
);
4746 for (unsigned i
= 0; i
< n
; i
++) {
4747 /* Emit a copy of the original instruction with the lowered width.
4748 * If the EOT flag was set throw it away except for the last
4749 * instruction to avoid killing the thread prematurely.
4751 fs_inst split_inst
= *inst
;
4752 split_inst
.exec_size
= lower_width
;
4753 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4755 /* Select the correct channel enables for the i-th group, then
4756 * transform the sources and destination and emit the lowered
4759 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4761 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4762 if (inst
->src
[j
].file
!= BAD_FILE
&&
4763 !is_uniform(inst
->src
[j
])) {
4764 /* Get the i-th copy_width-wide chunk of the source. */
4765 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4766 const unsigned src_size
= inst
->components_read(j
);
4768 /* Use a trivial transposition to copy one every n
4769 * copy_width-wide components of the register into a
4770 * temporary passed as source to the lowered instruction.
4772 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4773 emit_transpose(lbld
.group(copy_width
, 0),
4774 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4778 if (inst
->regs_written
) {
4779 /* Allocate enough space to hold the result of the lowered
4780 * instruction and fix up the number of registers written.
4782 split_inst
.dst
= dsts
[i
] =
4783 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4784 split_inst
.regs_written
=
4785 DIV_ROUND_UP(type_sz(inst
->dst
.type
) * dst_size
* lower_width
,
4789 lbld
.emit(split_inst
);
4792 if (inst
->regs_written
) {
4793 /* Distance between useful channels in the temporaries, skipping
4794 * garbage if the lowered instruction is wider than the original.
4796 const unsigned m
= lower_width
/ copy_width
;
4798 /* Interleave the components of the result from the lowered
4799 * instructions. We need to set exec_all() when copying more than
4800 * one half per component, because LOAD_PAYLOAD (in terms of which
4801 * emit_transpose is implemented) can only use the same channel
4802 * enable signals for all of its non-header sources.
4804 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4805 .group(copy_width
, 0),
4806 inst
->dst
, dsts
, n
, dst_size
, m
);
4809 inst
->remove(block
);
4815 invalidate_live_intervals();
4821 fs_visitor::dump_instructions()
4823 dump_instructions(NULL
);
4827 fs_visitor::dump_instructions(const char *name
)
4829 FILE *file
= stderr
;
4830 if (name
&& geteuid() != 0) {
4831 file
= fopen(name
, "w");
4837 calculate_register_pressure();
4838 int ip
= 0, max_pressure
= 0;
4839 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4840 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4841 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4842 dump_instruction(inst
, file
);
4845 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4848 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4849 fprintf(file
, "%4d: ", ip
++);
4850 dump_instruction(inst
, file
);
4854 if (file
!= stderr
) {
4860 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4862 dump_instruction(be_inst
, stderr
);
4866 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4868 fs_inst
*inst
= (fs_inst
*)be_inst
;
4870 if (inst
->predicate
) {
4871 fprintf(file
, "(%cf0.%d) ",
4872 inst
->predicate_inverse
? '-' : '+',
4876 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
4878 fprintf(file
, ".sat");
4879 if (inst
->conditional_mod
) {
4880 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4881 if (!inst
->predicate
&&
4882 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4883 inst
->opcode
!= BRW_OPCODE_IF
&&
4884 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4885 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4888 fprintf(file
, "(%d) ", inst
->exec_size
);
4891 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4894 switch (inst
->dst
.file
) {
4896 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
4897 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
4898 inst
->dst
.subreg_offset
)
4899 fprintf(file
, "+%d.%d",
4900 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4903 fprintf(file
, "g%d", inst
->dst
.nr
);
4906 fprintf(file
, "m%d", inst
->dst
.nr
);
4909 fprintf(file
, "(null)");
4912 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4915 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4918 switch (inst
->dst
.nr
) {
4920 fprintf(file
, "null");
4922 case BRW_ARF_ADDRESS
:
4923 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
4925 case BRW_ARF_ACCUMULATOR
:
4926 fprintf(file
, "acc%d", inst
->dst
.subnr
);
4929 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4932 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4935 if (inst
->dst
.subnr
)
4936 fprintf(file
, "+%d", inst
->dst
.subnr
);
4939 unreachable("not reached");
4941 if (inst
->dst
.stride
!= 1)
4942 fprintf(file
, "<%u>", inst
->dst
.stride
);
4943 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4945 for (int i
= 0; i
< inst
->sources
; i
++) {
4946 if (inst
->src
[i
].negate
)
4948 if (inst
->src
[i
].abs
)
4950 switch (inst
->src
[i
].file
) {
4952 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
4953 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
4954 inst
->src
[i
].subreg_offset
)
4955 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4956 inst
->src
[i
].subreg_offset
);
4959 fprintf(file
, "g%d", inst
->src
[i
].nr
);
4962 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
4965 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
4968 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
4969 if (inst
->src
[i
].subreg_offset
) {
4970 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4971 inst
->src
[i
].subreg_offset
);
4975 fprintf(file
, "(null)");
4978 switch (inst
->src
[i
].type
) {
4979 case BRW_REGISTER_TYPE_F
:
4980 fprintf(file
, "%-gf", inst
->src
[i
].f
);
4982 case BRW_REGISTER_TYPE_DF
:
4983 fprintf(file
, "%fdf", inst
->src
[i
].df
);
4985 case BRW_REGISTER_TYPE_W
:
4986 case BRW_REGISTER_TYPE_D
:
4987 fprintf(file
, "%dd", inst
->src
[i
].d
);
4989 case BRW_REGISTER_TYPE_UW
:
4990 case BRW_REGISTER_TYPE_UD
:
4991 fprintf(file
, "%uu", inst
->src
[i
].ud
);
4993 case BRW_REGISTER_TYPE_VF
:
4994 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4995 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
4996 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
4997 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
4998 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5001 fprintf(file
, "???");
5006 switch (inst
->src
[i
].nr
) {
5008 fprintf(file
, "null");
5010 case BRW_ARF_ADDRESS
:
5011 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5013 case BRW_ARF_ACCUMULATOR
:
5014 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5017 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5020 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5023 if (inst
->src
[i
].subnr
)
5024 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
5027 if (inst
->src
[i
].abs
)
5030 if (inst
->src
[i
].file
!= IMM
) {
5032 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5033 unsigned hstride
= inst
->src
[i
].hstride
;
5034 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5036 stride
= inst
->src
[i
].stride
;
5039 fprintf(file
, "<%u>", stride
);
5041 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
5044 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5045 fprintf(file
, ", ");
5050 if (inst
->force_writemask_all
)
5051 fprintf(file
, "NoMask ");
5053 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
5054 if (inst
->force_sechalf
)
5055 fprintf(file
, "2ndhalf ");
5057 fprintf(file
, "1sthalf ");
5060 fprintf(file
, "\n");
5064 * Possibly returns an instruction that set up @param reg.
5066 * Sometimes we want to take the result of some expression/variable
5067 * dereference tree and rewrite the instruction generating the result
5068 * of the tree. When processing the tree, we know that the
5069 * instructions generated are all writing temporaries that are dead
5070 * outside of this tree. So, if we have some instructions that write
5071 * a temporary, we're free to point that temp write somewhere else.
5073 * Note that this doesn't guarantee that the instruction generated
5074 * only reg -- it might be the size=4 destination of a texture instruction.
5077 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5082 end
->is_partial_write() ||
5083 !reg
.equals(end
->dst
)) {
5091 fs_visitor::setup_fs_payload_gen6()
5093 assert(stage
== MESA_SHADER_FRAGMENT
);
5094 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5095 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
5097 unsigned barycentric_interp_modes
=
5098 (stage
== MESA_SHADER_FRAGMENT
) ?
5099 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
5101 assert(devinfo
->gen
>= 6);
5103 /* R0-1: masks, pixel X/Y coordinates. */
5104 payload
.num_regs
= 2;
5105 /* R2: only for 32-pixel dispatch.*/
5107 /* R3-26: barycentric interpolation coordinates. These appear in the
5108 * same order that they appear in the brw_wm_barycentric_interp_mode
5109 * enum. Each set of coordinates occupies 2 registers if dispatch width
5110 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5111 * appear if they were enabled using the "Barycentric Interpolation
5112 * Mode" bits in WM_STATE.
5114 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
5115 if (barycentric_interp_modes
& (1 << i
)) {
5116 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5117 payload
.num_regs
+= 2;
5118 if (dispatch_width
== 16) {
5119 payload
.num_regs
+= 2;
5124 /* R27: interpolated depth if uses source depth */
5125 prog_data
->uses_src_depth
=
5126 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5127 if (prog_data
->uses_src_depth
) {
5128 payload
.source_depth_reg
= payload
.num_regs
;
5130 if (dispatch_width
== 16) {
5131 /* R28: interpolated depth if not SIMD8. */
5136 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5137 prog_data
->uses_src_w
=
5138 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5139 if (prog_data
->uses_src_w
) {
5140 payload
.source_w_reg
= payload
.num_regs
;
5142 if (dispatch_width
== 16) {
5143 /* R30: interpolated W if not SIMD8. */
5148 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
5149 /* R31: MSAA position offsets. */
5150 if (prog_data
->uses_pos_offset
) {
5151 payload
.sample_pos_reg
= payload
.num_regs
;
5155 /* R32: MSAA input coverage mask */
5156 prog_data
->uses_sample_mask
=
5157 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5158 if (prog_data
->uses_sample_mask
) {
5159 assert(devinfo
->gen
>= 7);
5160 payload
.sample_mask_in_reg
= payload
.num_regs
;
5162 if (dispatch_width
== 16) {
5163 /* R33: input coverage mask if not SIMD8. */
5168 /* R34-: bary for 32-pixel. */
5169 /* R58-59: interp W for 32-pixel. */
5171 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5172 source_depth_to_render_target
= true;
5177 fs_visitor::setup_vs_payload()
5179 /* R0: thread header, R1: urb handles */
5180 payload
.num_regs
= 2;
5184 * We are building the local ID push constant data using the simplest possible
5185 * method. We simply push the local IDs directly as they should appear in the
5186 * registers for the uvec3 gl_LocalInvocationID variable.
5188 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
5189 * registers worth of push constant space.
5191 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
5192 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
5195 * FINISHME: There are a few easy optimizations to consider.
5197 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
5198 * no need for using push constant space for that dimension.
5200 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
5201 * easily use 16-bit words rather than 32-bit dwords in the push constant
5204 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
5205 * conveying the data, and thereby reduce push constant usage.
5209 fs_visitor::setup_gs_payload()
5211 assert(stage
== MESA_SHADER_GEOMETRY
);
5213 struct brw_gs_prog_data
*gs_prog_data
=
5214 (struct brw_gs_prog_data
*) prog_data
;
5215 struct brw_vue_prog_data
*vue_prog_data
=
5216 (struct brw_vue_prog_data
*) prog_data
;
5218 /* R0: thread header, R1: output URB handles */
5219 payload
.num_regs
= 2;
5221 if (gs_prog_data
->include_primitive_id
) {
5222 /* R2: Primitive ID 0..7 */
5226 /* Use a maximum of 32 registers for push-model inputs. */
5227 const unsigned max_push_components
= 32;
5229 /* If pushing our inputs would take too many registers, reduce the URB read
5230 * length (which is in HWords, or 8 registers), and resort to pulling.
5232 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5233 * have to multiply by VerticesIn to obtain the total storage requirement.
5235 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5236 max_push_components
) {
5237 gs_prog_data
->base
.include_vue_handles
= true;
5239 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5240 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5242 vue_prog_data
->urb_read_length
=
5243 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5248 fs_visitor::setup_cs_payload()
5250 assert(devinfo
->gen
>= 7);
5251 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
5253 payload
.num_regs
= 1;
5255 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
5256 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
5257 payload
.local_invocation_id_reg
= payload
.num_regs
;
5258 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
5263 fs_visitor::calculate_register_pressure()
5265 invalidate_live_intervals();
5266 calculate_live_intervals();
5268 unsigned num_instructions
= 0;
5269 foreach_block(block
, cfg
)
5270 num_instructions
+= block
->instructions
.length();
5272 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5274 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5275 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5276 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5281 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5283 * The needs_unlit_centroid_workaround ends up producing one of these per
5284 * channel of centroid input, so it's good to clean them up.
5286 * An assumption here is that nothing ever modifies the dispatched pixels
5287 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5288 * dictates that anyway.
5291 fs_visitor::opt_drop_redundant_mov_to_flags()
5293 bool flag_mov_found
[2] = {false};
5294 bool progress
= false;
5296 /* Instructions removed by this pass can only be added if this were true */
5297 if (!devinfo
->needs_unlit_centroid_workaround
)
5300 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5301 if (inst
->is_control_flow()) {
5302 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5303 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5304 if (!flag_mov_found
[inst
->flag_subreg
]) {
5305 flag_mov_found
[inst
->flag_subreg
] = true;
5307 inst
->remove(block
);
5310 } else if (inst
->writes_flag()) {
5311 flag_mov_found
[inst
->flag_subreg
] = false;
5319 fs_visitor::optimize()
5321 /* Start by validating the shader we currently have. */
5324 /* bld is the common builder object pointing at the end of the program we
5325 * used to translate it into i965 IR. For the optimization and lowering
5326 * passes coming next, any code added after the end of the program without
5327 * having explicitly called fs_builder::at() clearly points at a mistake.
5328 * Ideally optimization passes wouldn't be part of the visitor so they
5329 * wouldn't have access to bld at all, but they do, so just in case some
5330 * pass forgets to ask for a location explicitly set it to NULL here to
5331 * make it trip. The dispatch width is initialized to a bogus value to
5332 * make sure that optimizations set the execution controls explicitly to
5333 * match the code they are manipulating instead of relying on the defaults.
5335 bld
= fs_builder(this, 64);
5337 assign_constant_locations();
5338 lower_constant_loads();
5342 split_virtual_grfs();
5345 #define OPT(pass, args...) ({ \
5347 bool this_progress = pass(args); \
5349 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5350 char filename[64]; \
5351 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5352 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5354 backend_shader::dump_instructions(filename); \
5359 progress = progress || this_progress; \
5363 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5365 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5366 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5368 backend_shader::dump_instructions(filename
);
5371 bool progress
= false;
5375 OPT(opt_drop_redundant_mov_to_flags
);
5377 OPT(lower_simd_width
);
5378 OPT(lower_logical_sends
);
5385 OPT(remove_duplicate_mrf_writes
);
5389 OPT(opt_copy_propagate
);
5390 OPT(opt_predicated_break
, this);
5391 OPT(opt_cmod_propagation
);
5392 OPT(dead_code_eliminate
);
5393 OPT(opt_peephole_sel
);
5394 OPT(dead_control_flow_eliminate
, this);
5395 OPT(opt_register_renaming
);
5396 OPT(opt_redundant_discard_jumps
);
5397 OPT(opt_saturate_propagation
);
5398 OPT(opt_zero_samples
);
5399 OPT(register_coalesce
);
5400 OPT(compute_to_mrf
);
5401 OPT(eliminate_find_live_channel
);
5403 OPT(compact_virtual_grfs
);
5408 OPT(opt_sampler_eot
);
5410 if (OPT(lower_load_payload
)) {
5411 split_virtual_grfs();
5412 OPT(register_coalesce
);
5413 OPT(compute_to_mrf
);
5414 OPT(dead_code_eliminate
);
5417 if (OPT(lower_pack
)) {
5418 OPT(register_coalesce
);
5419 OPT(dead_code_eliminate
);
5422 if (OPT(lower_d2x
)) {
5423 OPT(opt_copy_propagate
);
5424 OPT(dead_code_eliminate
);
5427 OPT(opt_combine_constants
);
5428 OPT(lower_integer_multiplication
);
5430 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5431 OPT(opt_cmod_propagation
);
5433 OPT(opt_copy_propagate
);
5434 OPT(dead_code_eliminate
);
5437 lower_uniform_pull_constant_loads();
5443 * Three source instruction must have a GRF/MRF destination register.
5444 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5447 fs_visitor::fixup_3src_null_dest()
5449 bool progress
= false;
5451 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5452 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5453 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5460 invalidate_live_intervals();
5464 fs_visitor::allocate_registers()
5466 bool allocated_without_spills
;
5468 static const enum instruction_scheduler_mode pre_modes
[] = {
5470 SCHEDULE_PRE_NON_LIFO
,
5474 /* Try each scheduling heuristic to see if it can successfully register
5475 * allocate without spilling. They should be ordered by decreasing
5476 * performance but increasing likelihood of allocating.
5478 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5479 schedule_instructions(pre_modes
[i
]);
5482 assign_regs_trivial();
5483 allocated_without_spills
= true;
5485 allocated_without_spills
= assign_regs(false);
5487 if (allocated_without_spills
)
5491 if (!allocated_without_spills
) {
5492 /* We assume that any spilling is worse than just dropping back to
5493 * SIMD8. There's probably actually some intermediate point where
5494 * SIMD16 with a couple of spills is still better.
5496 if (dispatch_width
== 16 && min_dispatch_width
<= 8) {
5497 fail("Failure to register allocate. Reduce number of "
5498 "live scalar values to avoid this.");
5500 compiler
->shader_perf_log(log_data
,
5501 "%s shader triggered register spilling. "
5502 "Try reducing the number of live scalar "
5503 "values to improve performance.\n",
5507 /* Since we're out of heuristics, just go spill registers until we
5508 * get an allocation.
5510 while (!assign_regs(true)) {
5516 /* This must come after all optimization and register allocation, since
5517 * it inserts dead code that happens to have side effects, and it does
5518 * so based on the actual physical registers in use.
5520 insert_gen4_send_dependency_workarounds();
5525 schedule_instructions(SCHEDULE_POST
);
5527 if (last_scratch
> 0)
5528 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5532 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5534 assert(stage
== MESA_SHADER_VERTEX
);
5538 if (shader_time_index
>= 0)
5539 emit_shader_time_begin();
5546 compute_clip_distance(clip_planes
);
5550 if (shader_time_index
>= 0)
5551 emit_shader_time_end();
5557 assign_curb_setup();
5558 assign_vs_urb_setup();
5560 fixup_3src_null_dest();
5561 allocate_registers();
5567 fs_visitor::run_tcs_single_patch()
5569 assert(stage
== MESA_SHADER_TESS_CTRL
);
5571 struct brw_tcs_prog_data
*tcs_prog_data
=
5572 (struct brw_tcs_prog_data
*) prog_data
;
5574 /* r1-r4 contain the ICP handles. */
5575 payload
.num_regs
= 5;
5577 if (shader_time_index
>= 0)
5578 emit_shader_time_begin();
5580 /* Initialize gl_InvocationID */
5581 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
5582 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5583 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
5584 bld
.MOV(channels_ud
, channels_uw
);
5586 if (tcs_prog_data
->instances
== 1) {
5587 invocation_id
= channels_ud
;
5589 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5591 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
5592 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5593 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5594 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
5595 brw_imm_ud(INTEL_MASK(23, 17)));
5596 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
5598 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
5601 /* Fix the disptach mask */
5602 if (nir
->info
.tcs
.vertices_out
% 8) {
5603 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
5604 brw_imm_ud(nir
->info
.tcs
.vertices_out
), BRW_CONDITIONAL_L
);
5605 bld
.IF(BRW_PREDICATE_NORMAL
);
5610 if (nir
->info
.tcs
.vertices_out
% 8) {
5611 bld
.emit(BRW_OPCODE_ENDIF
);
5614 /* Emit EOT write; set TR DS Cache bit */
5616 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
5617 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
5618 fs_reg(brw_imm_ud(0)),
5620 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
5621 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
5623 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
5624 bld
.null_reg_ud(), payload
);
5626 inst
->base_mrf
= -1;
5629 if (shader_time_index
>= 0)
5630 emit_shader_time_end();
5639 assign_curb_setup();
5640 assign_tcs_single_patch_urb_setup();
5642 fixup_3src_null_dest();
5643 allocate_registers();
5649 fs_visitor::run_tes()
5651 assert(stage
== MESA_SHADER_TESS_EVAL
);
5653 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
5654 payload
.num_regs
= 5;
5656 if (shader_time_index
>= 0)
5657 emit_shader_time_begin();
5666 if (shader_time_index
>= 0)
5667 emit_shader_time_end();
5673 assign_curb_setup();
5674 assign_tes_urb_setup();
5676 fixup_3src_null_dest();
5677 allocate_registers();
5683 fs_visitor::run_gs()
5685 assert(stage
== MESA_SHADER_GEOMETRY
);
5689 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
5691 if (gs_compile
->control_data_header_size_bits
> 0) {
5692 /* Create a VGRF to store accumulated control data bits. */
5693 this->control_data_bits
= vgrf(glsl_type::uint_type
);
5695 /* If we're outputting more than 32 control data bits, then EmitVertex()
5696 * will set control_data_bits to 0 after emitting the first vertex.
5697 * Otherwise, we need to initialize it to 0 here.
5699 if (gs_compile
->control_data_header_size_bits
<= 32) {
5700 const fs_builder abld
= bld
.annotate("initialize control data bits");
5701 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
5705 if (shader_time_index
>= 0)
5706 emit_shader_time_begin();
5710 emit_gs_thread_end();
5712 if (shader_time_index
>= 0)
5713 emit_shader_time_end();
5722 assign_curb_setup();
5723 assign_gs_urb_setup();
5725 fixup_3src_null_dest();
5726 allocate_registers();
5732 fs_visitor::run_fs(bool do_rep_send
)
5734 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5735 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5737 assert(stage
== MESA_SHADER_FRAGMENT
);
5739 if (devinfo
->gen
>= 6)
5740 setup_fs_payload_gen6();
5742 setup_fs_payload_gen4();
5746 } else if (do_rep_send
) {
5747 assert(dispatch_width
== 16);
5748 emit_repclear_shader();
5750 if (shader_time_index
>= 0)
5751 emit_shader_time_begin();
5753 calculate_urb_setup();
5754 if (nir
->info
.inputs_read
> 0) {
5755 if (devinfo
->gen
< 6)
5756 emit_interpolation_setup_gen4();
5758 emit_interpolation_setup_gen6();
5761 /* We handle discards by keeping track of the still-live pixels in f0.1.
5762 * Initialize it with the dispatched pixels.
5764 if (wm_prog_data
->uses_kill
) {
5765 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5766 discard_init
->flag_subreg
= 1;
5769 /* Generate FS IR for main(). (the visitor only descends into
5770 * functions called "main").
5777 if (wm_prog_data
->uses_kill
)
5778 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5780 if (wm_key
->alpha_test_func
)
5785 if (shader_time_index
>= 0)
5786 emit_shader_time_end();
5792 assign_curb_setup();
5795 fixup_3src_null_dest();
5796 allocate_registers();
5802 if (dispatch_width
== 8)
5803 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5805 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5811 fs_visitor::run_cs()
5813 assert(stage
== MESA_SHADER_COMPUTE
);
5817 if (shader_time_index
>= 0)
5818 emit_shader_time_begin();
5820 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
5821 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
5822 const fs_builder abld
= bld
.exec_all().group(1, 0);
5823 abld
.MOV(retype(suboffset(brw_sr0_reg(), 1), BRW_REGISTER_TYPE_UW
),
5824 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
5832 emit_cs_terminate();
5834 if (shader_time_index
>= 0)
5835 emit_shader_time_end();
5841 assign_curb_setup();
5843 fixup_3src_null_dest();
5844 allocate_registers();
5853 * Return a bitfield where bit n is set if barycentric interpolation mode n
5854 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5857 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5858 bool shade_model_flat
,
5859 bool persample_shading
,
5860 const nir_shader
*shader
)
5862 unsigned barycentric_interp_modes
= 0;
5864 nir_foreach_variable(var
, &shader
->inputs
) {
5865 enum glsl_interp_qualifier interp_qualifier
=
5866 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5867 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5868 bool is_sample
= var
->data
.sample
|| persample_shading
;
5869 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5870 (var
->data
.location
== VARYING_SLOT_COL1
);
5872 /* Ignore WPOS and FACE, because they don't require interpolation. */
5873 if (var
->data
.location
== VARYING_SLOT_POS
||
5874 var
->data
.location
== VARYING_SLOT_FACE
)
5877 /* Determine the set (or sets) of barycentric coordinates needed to
5878 * interpolate this variable. Note that when
5879 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5880 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5881 * for lit pixels, so we need both sets of barycentric coordinates.
5883 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5885 barycentric_interp_modes
|=
5886 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5887 } else if (is_sample
) {
5888 barycentric_interp_modes
|=
5889 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5891 if ((!is_centroid
&& !is_sample
) ||
5892 devinfo
->needs_unlit_centroid_workaround
) {
5893 barycentric_interp_modes
|=
5894 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5896 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5897 (!(shade_model_flat
&& is_gl_Color
) &&
5898 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5900 barycentric_interp_modes
|=
5901 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5902 } else if (is_sample
) {
5903 barycentric_interp_modes
|=
5904 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5906 if ((!is_centroid
&& !is_sample
) ||
5907 devinfo
->needs_unlit_centroid_workaround
) {
5908 barycentric_interp_modes
|=
5909 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5914 return barycentric_interp_modes
;
5918 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
5919 bool shade_model_flat
, const nir_shader
*shader
)
5921 prog_data
->flat_inputs
= 0;
5923 nir_foreach_variable(var
, &shader
->inputs
) {
5924 enum glsl_interp_qualifier interp_qualifier
=
5925 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5926 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5927 (var
->data
.location
== VARYING_SLOT_COL1
);
5929 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
5931 if (input_index
< 0)
5935 if (interp_qualifier
== INTERP_QUALIFIER_FLAT
||
5936 (shade_model_flat
&& is_gl_Color
&&
5937 interp_qualifier
== INTERP_QUALIFIER_NONE
))
5938 prog_data
->flat_inputs
|= (1 << input_index
);
5943 computed_depth_mode(const nir_shader
*shader
)
5945 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5946 switch (shader
->info
.fs
.depth_layout
) {
5947 case FRAG_DEPTH_LAYOUT_NONE
:
5948 case FRAG_DEPTH_LAYOUT_ANY
:
5949 return BRW_PSCDEPTH_ON
;
5950 case FRAG_DEPTH_LAYOUT_GREATER
:
5951 return BRW_PSCDEPTH_ON_GE
;
5952 case FRAG_DEPTH_LAYOUT_LESS
:
5953 return BRW_PSCDEPTH_ON_LE
;
5954 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5955 return BRW_PSCDEPTH_OFF
;
5958 return BRW_PSCDEPTH_OFF
;
5962 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5964 const struct brw_wm_prog_key
*key
,
5965 struct brw_wm_prog_data
*prog_data
,
5966 const nir_shader
*src_shader
,
5967 struct gl_program
*prog
,
5968 int shader_time_index8
, int shader_time_index16
,
5970 unsigned *final_assembly_size
,
5973 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5974 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5976 brw_nir_lower_fs_inputs(shader
);
5977 brw_nir_lower_fs_outputs(shader
);
5978 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5980 /* key->alpha_test_func means simulating alpha testing via discards,
5981 * so the shader definitely kills pixels.
5983 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5984 prog_data
->uses_omask
= key
->multisample_fbo
&&
5985 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5986 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5987 prog_data
->computed_stencil
=
5988 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5990 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5992 prog_data
->barycentric_interp_modes
=
5993 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5995 key
->persample_shading
,
5998 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5999 &prog_data
->base
, prog
, shader
, 8,
6000 shader_time_index8
);
6001 if (!v
.run_fs(false /* do_rep_send */)) {
6003 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
6008 cfg_t
*simd16_cfg
= NULL
;
6009 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
6010 &prog_data
->base
, prog
, shader
, 16,
6011 shader_time_index16
);
6012 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6013 if (!v
.simd16_unsupported
) {
6014 /* Try a SIMD16 compile */
6015 v2
.import_uniforms(&v
);
6016 if (!v2
.run_fs(use_rep_send
)) {
6017 compiler
->shader_perf_log(log_data
,
6018 "SIMD16 shader failed to compile: %s",
6021 simd16_cfg
= v2
.cfg
;
6026 /* We have to compute the flat inputs after the visitor is finished running
6027 * because it relies on prog_data->urb_setup which is computed in
6028 * fs_visitor::calculate_urb_setup().
6030 brw_compute_flat_inputs(prog_data
, key
->flat_shade
, shader
);
6033 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
6034 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
6036 prog_data
->no_8
= true;
6039 prog_data
->no_8
= false;
6042 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6043 v
.promoted_constants
, v
.runtime_check_aads_emit
,
6044 MESA_SHADER_FRAGMENT
);
6046 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6047 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6048 shader
->info
.label
? shader
->info
.label
:
6050 shader
->info
.name
));
6054 g
.generate_code(simd8_cfg
, 8);
6056 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
6058 return g
.get_assembly(final_assembly_size
);
6062 fs_visitor::emit_cs_local_invocation_id_setup()
6064 assert(stage
== MESA_SHADER_COMPUTE
);
6066 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6068 struct brw_reg src
=
6069 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
6070 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
6072 src
.nr
+= dispatch_width
/ 8;
6073 bld
.MOV(offset(*reg
, bld
, 1), src
);
6074 src
.nr
+= dispatch_width
/ 8;
6075 bld
.MOV(offset(*reg
, bld
, 2), src
);
6081 fs_visitor::emit_cs_work_group_id_setup()
6083 assert(stage
== MESA_SHADER_COMPUTE
);
6085 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6087 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6088 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6089 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6091 bld
.MOV(*reg
, r0_1
);
6092 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6093 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6099 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6101 const struct brw_cs_prog_key
*key
,
6102 struct brw_cs_prog_data
*prog_data
,
6103 const nir_shader
*src_shader
,
6104 int shader_time_index
,
6105 unsigned *final_assembly_size
,
6108 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6109 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6111 brw_nir_lower_cs_shared(shader
);
6112 prog_data
->base
.total_shared
+= shader
->num_shared
;
6113 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6115 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
6116 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
6117 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
6118 unsigned local_workgroup_size
=
6119 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
6120 shader
->info
.cs
.local_size
[2];
6122 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
6123 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
6126 const char *fail_msg
= NULL
;
6128 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6130 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6131 NULL
, /* Never used in core profile */
6132 shader
, 8, shader_time_index
);
6133 if (simd_required
<= 8) {
6135 fail_msg
= v8
.fail_msg
;
6138 prog_data
->simd_size
= 8;
6142 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6143 NULL
, /* Never used in core profile */
6144 shader
, 16, shader_time_index
);
6145 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6146 !fail_msg
&& !v8
.simd16_unsupported
&&
6147 local_workgroup_size
<= 16 * max_cs_threads
) {
6148 /* Try a SIMD16 compile */
6149 if (simd_required
<= 8)
6150 v16
.import_uniforms(&v8
);
6151 if (!v16
.run_cs()) {
6152 compiler
->shader_perf_log(log_data
,
6153 "SIMD16 shader failed to compile: %s",
6157 "Couldn't generate SIMD16 program and not "
6158 "enough threads for SIMD8";
6162 prog_data
->simd_size
= 16;
6166 if (unlikely(cfg
== NULL
)) {
6169 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6174 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6175 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6176 MESA_SHADER_COMPUTE
);
6177 if (INTEL_DEBUG
& DEBUG_CS
) {
6178 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6179 shader
->info
.label
? shader
->info
.label
:
6182 g
.enable_debug(name
);
6185 g
.generate_code(cfg
, prog_data
->simd_size
);
6187 return g
.get_assembly(final_assembly_size
);
6191 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
6192 void *buffer
, uint32_t threads
, uint32_t stride
)
6194 if (prog_data
->local_invocation_id_regs
== 0)
6197 /* 'stride' should be an integer number of registers, that is, a multiple
6200 assert(stride
% 32 == 0);
6202 unsigned x
= 0, y
= 0, z
= 0;
6203 for (unsigned t
= 0; t
< threads
; t
++) {
6204 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
6206 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
6207 param
[0 * prog_data
->simd_size
+ i
] = x
;
6208 param
[1 * prog_data
->simd_size
+ i
] = y
;
6209 param
[2 * prog_data
->simd_size
+ i
] = z
;
6212 if (x
== prog_data
->local_size
[0]) {
6215 if (y
== prog_data
->local_size
[1]) {
6218 if (z
== prog_data
->local_size
[2])