2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/sampler.h"
39 #include "program/hash_table.h"
40 #include "brw_context.h"
45 #include "../glsl/glsl_types.h"
46 #include "../glsl/ir_optimization.h"
47 #include "../glsl/ir_print_visitor.h"
50 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
51 GRF
= BRW_GENERAL_REGISTER_FILE
,
52 MRF
= BRW_MESSAGE_REGISTER_FILE
,
53 IMM
= BRW_IMMEDIATE_VALUE
,
54 FIXED_HW_REG
, /* a struct brw_reg */
55 UNIFORM
, /* prog_data->params[hw_reg] */
60 FS_OPCODE_FB_WRITE
= 256,
78 static int using_new_fs
= -1;
79 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
82 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
84 struct brw_shader
*shader
;
86 shader
= talloc_zero(NULL
, struct brw_shader
);
88 shader
->base
.Type
= type
;
89 shader
->base
.Name
= name
;
90 _mesa_init_shader(ctx
, &shader
->base
);
96 struct gl_shader_program
*
97 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
99 struct brw_shader_program
*prog
;
100 prog
= talloc_zero(NULL
, struct brw_shader_program
);
102 prog
->base
.Name
= name
;
103 _mesa_init_shader_program(ctx
, &prog
->base
);
109 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
111 if (!_mesa_ir_compile_shader(ctx
, shader
))
118 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
120 if (using_new_fs
== -1)
121 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
123 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
124 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
126 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
127 void *mem_ctx
= talloc_new(NULL
);
131 talloc_free(shader
->ir
);
132 shader
->ir
= new(shader
) exec_list
;
133 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
135 do_mat_op_to_vec(shader
->ir
);
136 do_mod_to_fract(shader
->ir
);
137 do_div_to_mul_rcp(shader
->ir
);
138 do_sub_to_add_neg(shader
->ir
);
139 do_explog_to_explog2(shader
->ir
);
144 brw_do_channel_expressions(shader
->ir
);
145 brw_do_vector_splitting(shader
->ir
);
147 progress
= do_lower_jumps(shader
->ir
, true, true,
148 true, /* main return */
149 false, /* continue */
153 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
155 progress
= lower_noise(shader
->ir
) || progress
;
157 lower_variable_index_to_cond_assign(shader
->ir
,
159 GL_TRUE
, /* output */
161 GL_TRUE
/* uniform */
165 validate_ir_tree(shader
->ir
);
167 reparent_ir(shader
->ir
, shader
->ir
);
168 talloc_free(mem_ctx
);
172 if (!_mesa_ir_link_shader(ctx
, prog
))
179 type_size(const struct glsl_type
*type
)
181 unsigned int size
, i
;
183 switch (type
->base_type
) {
186 case GLSL_TYPE_FLOAT
:
188 return type
->components();
189 case GLSL_TYPE_ARRAY
:
190 return type_size(type
->fields
.array
) * type
->length
;
191 case GLSL_TYPE_STRUCT
:
193 for (i
= 0; i
< type
->length
; i
++) {
194 size
+= type_size(type
->fields
.structure
[i
].type
);
197 case GLSL_TYPE_SAMPLER
:
198 /* Samplers take up no register space, since they're baked in at
203 assert(!"not reached");
210 /* Callers of this talloc-based new need not call delete. It's
211 * easier to just talloc_free 'ctx' (or any of its ancestors). */
212 static void* operator new(size_t size
, void *ctx
)
216 node
= talloc_size(ctx
, size
);
217 assert(node
!= NULL
);
225 this->reg_offset
= 0;
231 /** Generic unset register constructor. */
235 this->file
= BAD_FILE
;
238 /** Immediate value constructor. */
243 this->type
= BRW_REGISTER_TYPE_F
;
247 /** Immediate value constructor. */
252 this->type
= BRW_REGISTER_TYPE_D
;
256 /** Immediate value constructor. */
261 this->type
= BRW_REGISTER_TYPE_UD
;
265 /** Fixed brw_reg Immediate value constructor. */
266 fs_reg(struct brw_reg fixed_hw_reg
)
269 this->file
= FIXED_HW_REG
;
270 this->fixed_hw_reg
= fixed_hw_reg
;
271 this->type
= fixed_hw_reg
.type
;
274 fs_reg(enum register_file file
, int hw_reg
);
275 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
277 /** Register file: ARF, GRF, MRF, IMM. */
278 enum register_file file
;
279 /** Abstract register number. 0 = fixed hw reg */
281 /** Offset within the abstract register. */
283 /** HW register number. Generally unset until register allocation. */
285 /** Register type. BRW_REGISTER_TYPE_* */
289 struct brw_reg fixed_hw_reg
;
291 /** Value for file == BRW_IMMMEDIATE_FILE */
299 static const fs_reg reg_undef
;
300 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
302 class fs_inst
: public exec_node
{
304 /* Callers of this talloc-based new need not call delete. It's
305 * easier to just talloc_free 'ctx' (or any of its ancestors). */
306 static void* operator new(size_t size
, void *ctx
)
310 node
= talloc_zero_size(ctx
, size
);
311 assert(node
!= NULL
);
318 this->opcode
= BRW_OPCODE_NOP
;
319 this->saturate
= false;
320 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
321 this->predicated
= false;
325 this->shadow_compare
= false;
336 this->opcode
= opcode
;
339 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
)
342 this->opcode
= opcode
;
347 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
350 this->opcode
= opcode
;
356 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg src2
)
359 this->opcode
= opcode
;
366 int opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
371 int conditional_mod
; /**< BRW_CONDITIONAL_* */
373 int mlen
; /**< SEND message length */
375 int target
; /**< MRT target. */
380 * Annotation for the generated IR. One of the two can be set.
383 const char *annotation
;
387 class fs_visitor
: public ir_visitor
391 fs_visitor(struct brw_wm_compile
*c
, struct brw_shader
*shader
)
396 this->fp
= brw
->fragment_program
;
397 this->intel
= &brw
->intel
;
398 this->ctx
= &intel
->ctx
;
399 this->mem_ctx
= talloc_new(NULL
);
400 this->shader
= shader
;
402 this->next_abstract_grf
= 1;
403 this->variable_ht
= hash_table_ctor(0,
404 hash_table_pointer_hash
,
405 hash_table_pointer_compare
);
407 this->frag_color
= NULL
;
408 this->frag_data
= NULL
;
409 this->frag_depth
= NULL
;
410 this->first_non_payload_grf
= 0;
412 this->current_annotation
= NULL
;
413 this->annotation_string
= NULL
;
414 this->annotation_ir
= NULL
;
415 this->base_ir
= NULL
;
419 talloc_free(this->mem_ctx
);
420 hash_table_dtor(this->variable_ht
);
423 fs_reg
*variable_storage(ir_variable
*var
);
425 void visit(ir_variable
*ir
);
426 void visit(ir_assignment
*ir
);
427 void visit(ir_dereference_variable
*ir
);
428 void visit(ir_dereference_record
*ir
);
429 void visit(ir_dereference_array
*ir
);
430 void visit(ir_expression
*ir
);
431 void visit(ir_texture
*ir
);
432 void visit(ir_if
*ir
);
433 void visit(ir_constant
*ir
);
434 void visit(ir_swizzle
*ir
);
435 void visit(ir_return
*ir
);
436 void visit(ir_loop
*ir
);
437 void visit(ir_loop_jump
*ir
);
438 void visit(ir_discard
*ir
);
439 void visit(ir_call
*ir
);
440 void visit(ir_function
*ir
);
441 void visit(ir_function_signature
*ir
);
443 fs_inst
*emit(fs_inst inst
);
444 void assign_curb_setup();
445 void assign_urb_setup();
447 void generate_code();
448 void generate_fb_write(fs_inst
*inst
);
449 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
450 struct brw_reg
*src
);
451 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
452 void generate_math(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg
*src
);
453 void generate_discard(fs_inst
*inst
, struct brw_reg temp
);
454 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
455 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
457 void emit_dummy_fs();
458 void emit_fragcoord_interpolation(ir_variable
*ir
);
459 void emit_general_interpolation(ir_variable
*ir
);
460 void emit_interpolation_setup();
461 void emit_fb_writes();
463 struct brw_reg
interp_reg(int location
, int channel
);
464 int setup_uniform_values(int loc
, const glsl_type
*type
);
465 void setup_builtin_uniform_values(ir_variable
*ir
);
467 struct brw_context
*brw
;
468 const struct gl_fragment_program
*fp
;
469 struct intel_context
*intel
;
471 struct brw_wm_compile
*c
;
472 struct brw_compile
*p
;
473 struct brw_shader
*shader
;
475 exec_list instructions
;
476 int next_abstract_grf
;
477 struct hash_table
*variable_ht
;
478 ir_variable
*frag_color
, *frag_data
, *frag_depth
;
479 int first_non_payload_grf
;
481 /** @{ debug annotation info */
482 const char *current_annotation
;
483 ir_instruction
*base_ir
;
484 const char **annotation_string
;
485 ir_instruction
**annotation_ir
;
490 /* Result of last visit() method. */
504 /** Fixed HW reg constructor. */
505 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
509 this->hw_reg
= hw_reg
;
510 this->type
= BRW_REGISTER_TYPE_F
;
514 brw_type_for_base_type(const struct glsl_type
*type
)
516 switch (type
->base_type
) {
517 case GLSL_TYPE_FLOAT
:
518 return BRW_REGISTER_TYPE_F
;
521 return BRW_REGISTER_TYPE_D
;
523 return BRW_REGISTER_TYPE_UD
;
524 case GLSL_TYPE_ARRAY
:
525 case GLSL_TYPE_STRUCT
:
526 /* These should be overridden with the type of the member when
527 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
528 * way to trip up if we don't.
530 return BRW_REGISTER_TYPE_UD
;
532 assert(!"not reached");
533 return BRW_REGISTER_TYPE_F
;
537 /** Automatic reg constructor. */
538 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
543 this->reg
= v
->next_abstract_grf
;
544 this->reg_offset
= 0;
545 v
->next_abstract_grf
+= type_size(type
);
546 this->type
= brw_type_for_base_type(type
);
550 fs_visitor::variable_storage(ir_variable
*var
)
552 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
555 /* Our support for uniforms is piggy-backed on the struct
556 * gl_fragment_program, because that's where the values actually
557 * get stored, rather than in some global gl_shader_program uniform
561 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
563 unsigned int offset
= 0;
566 if (type
->is_matrix()) {
567 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
568 type
->vector_elements
,
571 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
572 offset
+= setup_uniform_values(loc
+ offset
, column
);
578 switch (type
->base_type
) {
579 case GLSL_TYPE_FLOAT
:
583 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
584 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
585 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
589 case GLSL_TYPE_STRUCT
:
590 for (unsigned int i
= 0; i
< type
->length
; i
++) {
591 offset
+= setup_uniform_values(loc
+ offset
,
592 type
->fields
.structure
[i
].type
);
596 case GLSL_TYPE_ARRAY
:
597 for (unsigned int i
= 0; i
< type
->length
; i
++) {
598 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
602 case GLSL_TYPE_SAMPLER
:
603 /* The sampler takes up a slot, but we don't use any values from it. */
607 assert(!"not reached");
613 /* Our support for builtin uniforms is even scarier than non-builtin.
614 * It sits on top of the PROG_STATE_VAR parameters that are
615 * automatically updated from GL context state.
618 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
620 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
622 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
623 statevar
= &_mesa_builtin_uniform_desc
[i
];
624 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
628 if (!statevar
->name
) {
630 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
635 if (ir
->type
->is_array()) {
636 array_count
= ir
->type
->length
;
641 for (int a
= 0; a
< array_count
; a
++) {
642 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
643 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
644 int tokens
[STATE_LENGTH
];
646 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
647 if (ir
->type
->is_array()) {
651 /* This state reference has already been setup by ir_to_mesa,
652 * but we'll get the same index back here.
654 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
655 (gl_state_index
*)tokens
);
656 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
658 /* Add each of the unique swizzles of the element as a
659 * parameter. This'll end up matching the expected layout of
660 * the array/matrix/structure we're trying to fill in.
663 for (unsigned int i
= 0; i
< 4; i
++) {
664 int this_swiz
= GET_SWZ(element
->swizzle
, i
);
665 if (this_swiz
== last_swiz
)
667 last_swiz
= this_swiz
;
669 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
676 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
678 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
680 fs_reg neg_y
= this->pixel_y
;
684 if (ir
->pixel_center_integer
) {
685 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
687 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
692 if (ir
->origin_upper_left
&& ir
->pixel_center_integer
) {
693 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
695 fs_reg pixel_y
= this->pixel_y
;
696 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
698 if (!ir
->origin_upper_left
) {
699 pixel_y
.negate
= true;
700 offset
+= c
->key
.drawable_height
- 1.0;
703 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
708 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
709 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
712 /* gl_FragCoord.w: Already set up in emit_interpolation */
713 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
715 hash_table_insert(this->variable_ht
, reg
, ir
);
720 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
722 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
723 /* Interpolation is always in floating point regs. */
724 reg
->type
= BRW_REGISTER_TYPE_F
;
727 unsigned int array_elements
;
728 const glsl_type
*type
;
730 if (ir
->type
->is_array()) {
731 array_elements
= ir
->type
->length
;
732 if (array_elements
== 0) {
735 type
= ir
->type
->fields
.array
;
741 int location
= ir
->location
;
742 for (unsigned int i
= 0; i
< array_elements
; i
++) {
743 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
744 if (!(fp
->Base
.InputsRead
& BITFIELD64_BIT(location
))) {
745 /* If there's no incoming setup data for this slot, don't
746 * emit interpolation for it (since it's not used, and
747 * we'd fall over later trying to find the setup data.
749 attr
.reg_offset
+= type
->vector_elements
;
753 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
754 struct brw_reg interp
= interp_reg(location
, c
);
755 emit(fs_inst(FS_OPCODE_LINTERP
,
762 attr
.reg_offset
-= type
->vector_elements
;
764 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
765 emit(fs_inst(BRW_OPCODE_MUL
,
775 hash_table_insert(this->variable_ht
, reg
, ir
);
779 fs_visitor::visit(ir_variable
*ir
)
783 if (variable_storage(ir
))
786 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
787 this->frag_color
= ir
;
788 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
789 this->frag_data
= ir
;
790 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
791 this->frag_depth
= ir
;
794 if (ir
->mode
== ir_var_in
) {
795 if (!strcmp(ir
->name
, "gl_FragCoord")) {
796 emit_fragcoord_interpolation(ir
);
798 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
799 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
800 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
801 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
804 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
808 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
809 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
811 emit_general_interpolation(ir
);
816 if (ir
->mode
== ir_var_uniform
) {
817 int param_index
= c
->prog_data
.nr_params
;
819 if (!strncmp(ir
->name
, "gl_", 3)) {
820 setup_builtin_uniform_values(ir
);
822 setup_uniform_values(ir
->location
, ir
->type
);
825 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
829 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
831 hash_table_insert(this->variable_ht
, reg
, ir
);
835 fs_visitor::visit(ir_dereference_variable
*ir
)
837 fs_reg
*reg
= variable_storage(ir
->var
);
842 fs_visitor::visit(ir_dereference_record
*ir
)
844 const glsl_type
*struct_type
= ir
->record
->type
;
846 ir
->record
->accept(this);
848 unsigned int offset
= 0;
849 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
850 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
852 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
854 this->result
.reg_offset
+= offset
;
855 this->result
.type
= brw_type_for_base_type(ir
->type
);
859 fs_visitor::visit(ir_dereference_array
*ir
)
864 ir
->array
->accept(this);
865 index
= ir
->array_index
->as_constant();
867 element_size
= type_size(ir
->type
);
868 this->result
.type
= brw_type_for_base_type(ir
->type
);
871 assert(this->result
.file
== UNIFORM
||
872 (this->result
.file
== GRF
&&
873 this->result
.reg
!= 0));
874 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
876 assert(!"FINISHME: non-constant array element");
881 fs_visitor::visit(ir_expression
*ir
)
883 unsigned int operand
;
888 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
889 ir
->operands
[operand
]->accept(this);
890 if (this->result
.file
== BAD_FILE
) {
892 printf("Failed to get tree for expression operand:\n");
893 ir
->operands
[operand
]->accept(&v
);
896 op
[operand
] = this->result
;
898 /* Matrix expression operands should have been broken down to vector
899 * operations already.
901 assert(!ir
->operands
[operand
]->type
->is_matrix());
902 /* And then those vector operands should have been broken down to scalar.
904 assert(!ir
->operands
[operand
]->type
->is_vector());
907 /* Storage for our result. If our result goes into an assignment, it will
908 * just get copy-propagated out, so no worries.
910 this->result
= fs_reg(this, ir
->type
);
912 switch (ir
->operation
) {
913 case ir_unop_logic_not
:
914 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
917 op
[0].negate
= !op
[0].negate
;
918 this->result
= op
[0];
922 this->result
= op
[0];
925 temp
= fs_reg(this, ir
->type
);
927 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
929 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
930 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
931 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
932 inst
->predicated
= true;
934 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
935 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
936 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
937 inst
->predicated
= true;
941 emit(fs_inst(FS_OPCODE_RCP
, this->result
, op
[0]));
945 emit(fs_inst(FS_OPCODE_EXP2
, this->result
, op
[0]));
948 emit(fs_inst(FS_OPCODE_LOG2
, this->result
, op
[0]));
952 assert(!"not reached: should be handled by ir_explog_to_explog2");
955 emit(fs_inst(FS_OPCODE_SIN
, this->result
, op
[0]));
958 emit(fs_inst(FS_OPCODE_COS
, this->result
, op
[0]));
962 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
965 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
969 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
972 assert(!"not reached: should be handled by ir_sub_to_add_neg");
976 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
979 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
982 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
986 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
987 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
988 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
990 case ir_binop_greater
:
991 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
992 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
993 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
995 case ir_binop_lequal
:
996 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
997 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
998 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1000 case ir_binop_gequal
:
1001 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1002 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1003 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1005 case ir_binop_equal
:
1006 case ir_binop_all_equal
: /* same as nequal for scalars */
1007 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1008 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1009 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1011 case ir_binop_nequal
:
1012 case ir_binop_any_nequal
: /* same as nequal for scalars */
1013 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1014 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1015 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1018 case ir_binop_logic_xor
:
1019 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
1022 case ir_binop_logic_or
:
1023 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
1026 case ir_binop_logic_and
:
1027 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
1031 case ir_binop_cross
:
1033 assert(!"not reached: should be handled by brw_fs_channel_expressions");
1037 assert(!"not reached: should be handled by lower_noise");
1041 emit(fs_inst(FS_OPCODE_SQRT
, this->result
, op
[0]));
1045 emit(fs_inst(FS_OPCODE_RSQ
, this->result
, op
[0]));
1051 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1054 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1058 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
1059 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1062 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1065 op
[0].negate
= ~op
[0].negate
;
1066 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1067 this->result
.negate
= true;
1070 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1073 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
1077 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1078 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1080 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1081 inst
->predicated
= true;
1084 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1085 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1087 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1088 inst
->predicated
= true;
1092 inst
= emit(fs_inst(FS_OPCODE_POW
, this->result
, op
[0], op
[1]));
1095 case ir_unop_bit_not
:
1097 case ir_binop_lshift
:
1098 case ir_binop_rshift
:
1099 case ir_binop_bit_and
:
1100 case ir_binop_bit_xor
:
1101 case ir_binop_bit_or
:
1102 assert(!"GLSL 1.30 features unsupported");
1108 fs_visitor::visit(ir_assignment
*ir
)
1115 /* FINISHME: arrays on the lhs */
1116 ir
->lhs
->accept(this);
1119 ir
->rhs
->accept(this);
1122 /* FINISHME: This should really set to the correct maximal writemask for each
1123 * FINISHME: component written (in the loops below). This case can only
1124 * FINISHME: occur for matrices, arrays, and structures.
1126 if (ir
->write_mask
== 0) {
1127 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
1128 write_mask
= WRITEMASK_XYZW
;
1130 assert(ir
->lhs
->type
->is_vector() || ir
->lhs
->type
->is_scalar());
1131 write_mask
= ir
->write_mask
;
1134 assert(l
.file
!= BAD_FILE
);
1135 assert(r
.file
!= BAD_FILE
);
1137 if (ir
->condition
) {
1138 /* Get the condition bool into the predicate. */
1139 ir
->condition
->accept(this);
1140 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, this->result
, fs_reg(0)));
1141 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1144 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1145 if (i
>= 4 || (write_mask
& (1 << i
))) {
1146 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1148 inst
->predicated
= true;
1156 fs_visitor::visit(ir_texture
*ir
)
1159 fs_inst
*inst
= NULL
;
1160 unsigned int mlen
= 0;
1162 ir
->coordinate
->accept(this);
1163 fs_reg coordinate
= this->result
;
1165 if (ir
->projector
) {
1166 fs_reg inv_proj
= fs_reg(this, glsl_type::float_type
);
1168 ir
->projector
->accept(this);
1169 emit(fs_inst(FS_OPCODE_RCP
, inv_proj
, this->result
));
1171 fs_reg proj_coordinate
= fs_reg(this, ir
->coordinate
->type
);
1172 for (unsigned int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1173 emit(fs_inst(BRW_OPCODE_MUL
, proj_coordinate
, coordinate
, inv_proj
));
1174 coordinate
.reg_offset
++;
1175 proj_coordinate
.reg_offset
++;
1177 proj_coordinate
.reg_offset
= 0;
1179 coordinate
= proj_coordinate
;
1182 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1183 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1184 coordinate
.reg_offset
++;
1187 /* Pre-Ironlake, the 8-wide sampler always took u,v,r. */
1191 if (ir
->shadow_comparitor
) {
1192 /* For shadow comparisons, we have to supply u,v,r. */
1195 ir
->shadow_comparitor
->accept(this);
1196 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1200 /* Do we ever want to handle writemasking on texture samples? Is it
1201 * performance relevant?
1203 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1207 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
1210 ir
->lod_info
.bias
->accept(this);
1211 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1214 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
1217 ir
->lod_info
.lod
->accept(this);
1218 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1221 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
1225 assert(!"GLSL 1.30 features unsupported");
1230 _mesa_get_sampler_uniform_value(ir
->sampler
,
1231 ctx
->Shader
.CurrentProgram
,
1232 &brw
->fragment_program
->Base
);
1233 inst
->sampler
= c
->fp
->program
.Base
.SamplerUnits
[inst
->sampler
];
1237 if (ir
->shadow_comparitor
)
1238 inst
->shadow_compare
= true;
1243 fs_visitor::visit(ir_swizzle
*ir
)
1245 ir
->val
->accept(this);
1246 fs_reg val
= this->result
;
1248 fs_reg result
= fs_reg(this, ir
->type
);
1249 this->result
= result
;
1251 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1252 fs_reg channel
= val
;
1270 channel
.reg_offset
+= swiz
;
1271 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1272 result
.reg_offset
++;
1277 fs_visitor::visit(ir_discard
*ir
)
1279 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1281 assert(ir
->condition
== NULL
); /* FINISHME */
1283 emit(fs_inst(FS_OPCODE_DISCARD
, temp
, temp
));
1287 fs_visitor::visit(ir_constant
*ir
)
1289 fs_reg
reg(this, ir
->type
);
1292 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1293 switch (ir
->type
->base_type
) {
1294 case GLSL_TYPE_FLOAT
:
1295 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1297 case GLSL_TYPE_UINT
:
1298 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1301 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1303 case GLSL_TYPE_BOOL
:
1304 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1307 assert(!"Non-float/uint/int/bool constant");
1314 fs_visitor::visit(ir_if
*ir
)
1318 /* Don't point the annotation at the if statement, because then it plus
1319 * the then and else blocks get printed.
1321 this->base_ir
= ir
->condition
;
1323 /* Generate the condition into the condition code. */
1324 ir
->condition
->accept(this);
1325 inst
= emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(brw_null_reg()), this->result
));
1326 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1328 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1329 inst
->predicated
= true;
1331 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1332 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1338 if (!ir
->else_instructions
.is_empty()) {
1339 emit(fs_inst(BRW_OPCODE_ELSE
));
1341 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1342 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1349 emit(fs_inst(BRW_OPCODE_ENDIF
));
1353 fs_visitor::visit(ir_loop
*ir
)
1355 fs_reg counter
= reg_undef
;
1358 this->base_ir
= ir
->counter
;
1359 ir
->counter
->accept(this);
1360 counter
= *(variable_storage(ir
->counter
));
1363 this->base_ir
= ir
->from
;
1364 ir
->from
->accept(this);
1366 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1370 /* Start a safety counter. If the user messed up their loop
1371 * counting, we don't want to hang the GPU.
1373 fs_reg max_iter
= fs_reg(this, glsl_type::int_type
);
1374 emit(fs_inst(BRW_OPCODE_MOV
, max_iter
, fs_reg(10000)));
1376 emit(fs_inst(BRW_OPCODE_DO
));
1379 this->base_ir
= ir
->to
;
1380 ir
->to
->accept(this);
1382 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
,
1383 counter
, this->result
));
1385 case ir_binop_equal
:
1386 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1388 case ir_binop_nequal
:
1389 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1391 case ir_binop_gequal
:
1392 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1394 case ir_binop_lequal
:
1395 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1397 case ir_binop_greater
:
1398 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1401 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1404 assert(!"not reached: unknown loop condition");
1409 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1410 inst
->predicated
= true;
1413 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1414 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1420 /* Check the maximum loop iters counter. */
1421 inst
= emit(fs_inst(BRW_OPCODE_ADD
, max_iter
, max_iter
, fs_reg(-1)));
1422 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1424 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1425 inst
->predicated
= true;
1428 if (ir
->increment
) {
1429 this->base_ir
= ir
->increment
;
1430 ir
->increment
->accept(this);
1431 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1434 emit(fs_inst(BRW_OPCODE_WHILE
));
1438 fs_visitor::visit(ir_loop_jump
*ir
)
1441 case ir_loop_jump::jump_break
:
1442 emit(fs_inst(BRW_OPCODE_BREAK
));
1444 case ir_loop_jump::jump_continue
:
1445 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1451 fs_visitor::visit(ir_call
*ir
)
1453 assert(!"FINISHME");
1457 fs_visitor::visit(ir_return
*ir
)
1459 assert(!"FINISHME");
1463 fs_visitor::visit(ir_function
*ir
)
1465 /* Ignore function bodies other than main() -- we shouldn't see calls to
1466 * them since they should all be inlined before we get to ir_to_mesa.
1468 if (strcmp(ir
->name
, "main") == 0) {
1469 const ir_function_signature
*sig
;
1472 sig
= ir
->matching_signature(&empty
);
1476 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1477 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1486 fs_visitor::visit(ir_function_signature
*ir
)
1488 assert(!"not reached");
1493 fs_visitor::emit(fs_inst inst
)
1495 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1498 list_inst
->annotation
= this->current_annotation
;
1499 list_inst
->ir
= this->base_ir
;
1501 this->instructions
.push_tail(list_inst
);
1506 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1508 fs_visitor::emit_dummy_fs()
1510 /* Everyone's favorite color. */
1511 emit(fs_inst(BRW_OPCODE_MOV
,
1514 emit(fs_inst(BRW_OPCODE_MOV
,
1517 emit(fs_inst(BRW_OPCODE_MOV
,
1520 emit(fs_inst(BRW_OPCODE_MOV
,
1525 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1530 /* The register location here is relative to the start of the URB
1531 * data. It will get adjusted to be a real location before
1532 * generate_code() time.
1535 fs_visitor::interp_reg(int location
, int channel
)
1537 int regnr
= location
* 2 + channel
/ 2;
1538 int stride
= (channel
& 1) * 4;
1540 return brw_vec1_grf(regnr
, stride
);
1543 /** Emits the interpolation for the varying inputs. */
1545 fs_visitor::emit_interpolation_setup()
1547 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1549 this->current_annotation
= "compute pixel centers";
1550 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1551 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1552 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1553 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1554 emit(fs_inst(BRW_OPCODE_ADD
,
1556 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1557 fs_reg(brw_imm_v(0x10101010))));
1558 emit(fs_inst(BRW_OPCODE_ADD
,
1560 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1561 fs_reg(brw_imm_v(0x11001100))));
1563 this->current_annotation
= "compute pixel deltas from v0";
1564 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1565 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1566 emit(fs_inst(BRW_OPCODE_ADD
,
1569 fs_reg(negate(brw_vec1_grf(1, 0)))));
1570 emit(fs_inst(BRW_OPCODE_ADD
,
1573 fs_reg(negate(brw_vec1_grf(1, 1)))));
1575 this->current_annotation
= "compute pos.w and 1/pos.w";
1576 /* Compute wpos.w. It's always in our setup, since it's needed to
1577 * interpolate the other attributes.
1579 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1580 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1581 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1582 /* Compute the pixel 1/W value from wpos.w. */
1583 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1584 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
));
1585 this->current_annotation
= NULL
;
1589 fs_visitor::emit_fb_writes()
1591 this->current_annotation
= "FB write header";
1597 if (c
->key
.aa_dest_stencil_reg
) {
1598 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1599 fs_reg(brw_vec8_grf(c
->key
.aa_dest_stencil_reg
, 0))));
1602 /* Reserve space for color. It'll be filled in per MRT below. */
1606 if (c
->key
.source_depth_to_render_target
) {
1607 if (c
->key
.computes_depth
) {
1608 /* Hand over gl_FragDepth. */
1609 assert(this->frag_depth
);
1610 fs_reg depth
= *(variable_storage(this->frag_depth
));
1612 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
1614 /* Pass through the payload depth. */
1615 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1616 fs_reg(brw_vec8_grf(c
->key
.source_depth_reg
, 0))));
1620 if (c
->key
.dest_depth_reg
) {
1621 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1622 fs_reg(brw_vec8_grf(c
->key
.dest_depth_reg
, 0))));
1625 fs_reg color
= reg_undef
;
1626 if (this->frag_color
)
1627 color
= *(variable_storage(this->frag_color
));
1628 else if (this->frag_data
)
1629 color
= *(variable_storage(this->frag_data
));
1631 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1632 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1633 "FB write target %d",
1635 if (this->frag_color
|| this->frag_data
) {
1636 for (int i
= 0; i
< 4; i
++) {
1637 emit(fs_inst(BRW_OPCODE_MOV
,
1638 fs_reg(MRF
, color_mrf
+ i
),
1644 if (this->frag_color
)
1645 color
.reg_offset
-= 4;
1647 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1648 reg_undef
, reg_undef
));
1649 inst
->target
= target
;
1651 if (target
== c
->key
.nr_color_regions
- 1)
1655 if (c
->key
.nr_color_regions
== 0) {
1656 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1657 reg_undef
, reg_undef
));
1662 this->current_annotation
= NULL
;
1666 fs_visitor::generate_fb_write(fs_inst
*inst
)
1668 GLboolean eot
= inst
->eot
;
1670 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1673 brw_push_insn_state(p
);
1674 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1675 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1678 brw_vec8_grf(1, 0));
1679 brw_pop_insn_state(p
);
1682 8, /* dispatch_width */
1683 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
1685 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
1693 fs_visitor::generate_linterp(fs_inst
*inst
,
1694 struct brw_reg dst
, struct brw_reg
*src
)
1696 struct brw_reg delta_x
= src
[0];
1697 struct brw_reg delta_y
= src
[1];
1698 struct brw_reg interp
= src
[2];
1701 delta_y
.nr
== delta_x
.nr
+ 1 &&
1702 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
1703 brw_PLN(p
, dst
, interp
, delta_x
);
1705 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
1706 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
1711 fs_visitor::generate_math(fs_inst
*inst
,
1712 struct brw_reg dst
, struct brw_reg
*src
)
1716 switch (inst
->opcode
) {
1718 op
= BRW_MATH_FUNCTION_INV
;
1721 op
= BRW_MATH_FUNCTION_RSQ
;
1723 case FS_OPCODE_SQRT
:
1724 op
= BRW_MATH_FUNCTION_SQRT
;
1726 case FS_OPCODE_EXP2
:
1727 op
= BRW_MATH_FUNCTION_EXP
;
1729 case FS_OPCODE_LOG2
:
1730 op
= BRW_MATH_FUNCTION_LOG
;
1733 op
= BRW_MATH_FUNCTION_POW
;
1736 op
= BRW_MATH_FUNCTION_SIN
;
1739 op
= BRW_MATH_FUNCTION_COS
;
1742 assert(!"not reached: unknown math function");
1747 if (inst
->opcode
== FS_OPCODE_POW
) {
1748 brw_MOV(p
, brw_message_reg(3), src
[1]);
1753 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
1754 BRW_MATH_SATURATE_NONE
,
1756 BRW_MATH_DATA_VECTOR
,
1757 BRW_MATH_PRECISION_FULL
);
1761 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
1766 if (intel
->gen
== 5) {
1767 switch (inst
->opcode
) {
1769 if (inst
->shadow_compare
) {
1770 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
1772 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
1776 if (inst
->shadow_compare
) {
1777 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
1779 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
1784 switch (inst
->opcode
) {
1786 /* Note that G45 and older determines shadow compare and dispatch width
1787 * from message length for most messages.
1789 if (inst
->shadow_compare
) {
1790 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1792 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1795 if (inst
->shadow_compare
) {
1796 assert(!"FINISHME: shadow compare with bias.");
1797 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1799 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1805 assert(msg_type
!= -1);
1811 retype(dst
, BRW_REGISTER_TYPE_UW
),
1813 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
1814 SURF_INDEX_TEXTURE(inst
->sampler
),
1822 BRW_SAMPLER_SIMD_MODE_SIMD8
);
1826 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1829 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1831 * and we're trying to produce:
1834 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1835 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1836 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1837 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1838 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1839 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1840 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1841 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1843 * and add another set of two more subspans if in 16-pixel dispatch mode.
1845 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1846 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1847 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
1848 * between each other. We could probably do it like ddx and swizzle the right
1849 * order later, but bail for now and just produce
1850 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
1853 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
1855 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
1856 BRW_REGISTER_TYPE_F
,
1857 BRW_VERTICAL_STRIDE_2
,
1859 BRW_HORIZONTAL_STRIDE_0
,
1860 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1861 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1862 BRW_REGISTER_TYPE_F
,
1863 BRW_VERTICAL_STRIDE_2
,
1865 BRW_HORIZONTAL_STRIDE_0
,
1866 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1867 brw_ADD(p
, dst
, src0
, negate(src1
));
1871 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
1873 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1874 BRW_REGISTER_TYPE_F
,
1875 BRW_VERTICAL_STRIDE_4
,
1877 BRW_HORIZONTAL_STRIDE_0
,
1878 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1879 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
1880 BRW_REGISTER_TYPE_F
,
1881 BRW_VERTICAL_STRIDE_4
,
1883 BRW_HORIZONTAL_STRIDE_0
,
1884 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1885 brw_ADD(p
, dst
, src0
, negate(src1
));
1889 fs_visitor::generate_discard(fs_inst
*inst
, struct brw_reg temp
)
1891 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1892 temp
= brw_uw1_reg(temp
.file
, temp
.nr
, 0);
1894 brw_push_insn_state(p
);
1895 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1896 brw_NOT(p
, temp
, brw_mask_reg(1)); /* IMASK */
1897 brw_AND(p
, g0
, temp
, g0
);
1898 brw_pop_insn_state(p
);
1902 trivial_assign_reg(int header_size
, fs_reg
*reg
)
1904 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
1905 reg
->hw_reg
= header_size
+ reg
->reg
- 1 + reg
->reg_offset
;
1911 fs_visitor::assign_curb_setup()
1913 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
1914 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
1916 if (intel
->gen
== 5 && (c
->prog_data
.first_curbe_grf
+
1917 c
->prog_data
.curb_read_length
) & 1) {
1918 /* Align the start of the interpolation coefficients so that we can use
1919 * the PLN instruction.
1921 c
->prog_data
.first_curbe_grf
++;
1924 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1925 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1926 fs_inst
*inst
= (fs_inst
*)iter
.get();
1928 for (unsigned int i
= 0; i
< 3; i
++) {
1929 if (inst
->src
[i
].file
== UNIFORM
) {
1930 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
1931 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
1935 inst
->src
[i
].file
= FIXED_HW_REG
;
1936 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
1943 fs_visitor::assign_urb_setup()
1945 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
1946 int interp_reg_nr
[FRAG_ATTRIB_MAX
];
1948 c
->prog_data
.urb_read_length
= 0;
1950 /* Figure out where each of the incoming setup attributes lands. */
1951 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
1952 interp_reg_nr
[i
] = -1;
1954 if (i
!= FRAG_ATTRIB_WPOS
&&
1955 !(brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)))
1958 /* Each attribute is 4 setup channels, each of which is half a reg. */
1959 interp_reg_nr
[i
] = urb_start
+ c
->prog_data
.urb_read_length
;
1960 c
->prog_data
.urb_read_length
+= 2;
1963 /* Map the register numbers for FS_OPCODE_LINTERP so that it uses
1964 * the correct setup input.
1966 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1967 fs_inst
*inst
= (fs_inst
*)iter
.get();
1969 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
1972 assert(inst
->src
[2].file
== FIXED_HW_REG
);
1974 int location
= inst
->src
[2].fixed_hw_reg
.nr
/ 2;
1975 assert(interp_reg_nr
[location
] != -1);
1976 inst
->src
[2].fixed_hw_reg
.nr
= (interp_reg_nr
[location
] +
1977 (inst
->src
[2].fixed_hw_reg
.nr
& 1));
1980 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
1984 fs_visitor::assign_regs()
1986 int header_size
= this->first_non_payload_grf
;
1989 /* FINISHME: trivial assignment of register numbers */
1990 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1991 fs_inst
*inst
= (fs_inst
*)iter
.get();
1993 trivial_assign_reg(header_size
, &inst
->dst
);
1994 trivial_assign_reg(header_size
, &inst
->src
[0]);
1995 trivial_assign_reg(header_size
, &inst
->src
[1]);
1997 last_grf
= MAX2(last_grf
, inst
->dst
.hw_reg
);
1998 last_grf
= MAX2(last_grf
, inst
->src
[0].hw_reg
);
1999 last_grf
= MAX2(last_grf
, inst
->src
[1].hw_reg
);
2002 this->grf_used
= last_grf
+ 1;
2005 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
2007 struct brw_reg brw_reg
;
2009 switch (reg
->file
) {
2013 brw_reg
= brw_vec8_reg(reg
->file
,
2015 brw_reg
= retype(brw_reg
, reg
->type
);
2018 switch (reg
->type
) {
2019 case BRW_REGISTER_TYPE_F
:
2020 brw_reg
= brw_imm_f(reg
->imm
.f
);
2022 case BRW_REGISTER_TYPE_D
:
2023 brw_reg
= brw_imm_d(reg
->imm
.i
);
2025 case BRW_REGISTER_TYPE_UD
:
2026 brw_reg
= brw_imm_ud(reg
->imm
.u
);
2029 assert(!"not reached");
2034 brw_reg
= reg
->fixed_hw_reg
;
2037 /* Probably unused. */
2038 brw_reg
= brw_null_reg();
2041 assert(!"not reached");
2042 brw_reg
= brw_null_reg();
2046 brw_reg
= brw_abs(brw_reg
);
2048 brw_reg
= negate(brw_reg
);
2054 fs_visitor::generate_code()
2056 unsigned int annotation_len
= 0;
2057 int last_native_inst
= 0;
2058 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
2059 int if_stack_depth
= 0, loop_stack_depth
= 0;
2060 int if_depth_in_loop
[16];
2062 if_depth_in_loop
[loop_stack_depth
] = 0;
2064 memset(&if_stack
, 0, sizeof(if_stack
));
2065 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2066 fs_inst
*inst
= (fs_inst
*)iter
.get();
2067 struct brw_reg src
[3], dst
;
2069 for (unsigned int i
= 0; i
< 3; i
++) {
2070 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
2072 dst
= brw_reg_from_fs_reg(&inst
->dst
);
2074 brw_set_conditionalmod(p
, inst
->conditional_mod
);
2075 brw_set_predicate_control(p
, inst
->predicated
);
2077 switch (inst
->opcode
) {
2078 case BRW_OPCODE_MOV
:
2079 brw_MOV(p
, dst
, src
[0]);
2081 case BRW_OPCODE_ADD
:
2082 brw_ADD(p
, dst
, src
[0], src
[1]);
2084 case BRW_OPCODE_MUL
:
2085 brw_MUL(p
, dst
, src
[0], src
[1]);
2088 case BRW_OPCODE_FRC
:
2089 brw_FRC(p
, dst
, src
[0]);
2091 case BRW_OPCODE_RNDD
:
2092 brw_RNDD(p
, dst
, src
[0]);
2094 case BRW_OPCODE_RNDZ
:
2095 brw_RNDZ(p
, dst
, src
[0]);
2098 case BRW_OPCODE_AND
:
2099 brw_AND(p
, dst
, src
[0], src
[1]);
2102 brw_OR(p
, dst
, src
[0], src
[1]);
2104 case BRW_OPCODE_XOR
:
2105 brw_XOR(p
, dst
, src
[0], src
[1]);
2108 case BRW_OPCODE_CMP
:
2109 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
2111 case BRW_OPCODE_SEL
:
2112 brw_SEL(p
, dst
, src
[0], src
[1]);
2116 assert(if_stack_depth
< 16);
2117 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
2118 if_depth_in_loop
[loop_stack_depth
]++;
2121 case BRW_OPCODE_ELSE
:
2122 if_stack
[if_stack_depth
- 1] =
2123 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
2125 case BRW_OPCODE_ENDIF
:
2127 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
2128 if_depth_in_loop
[loop_stack_depth
]--;
2132 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
2133 if_depth_in_loop
[loop_stack_depth
] = 0;
2136 case BRW_OPCODE_BREAK
:
2137 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
2138 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2140 case BRW_OPCODE_CONTINUE
:
2141 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
2142 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2145 case BRW_OPCODE_WHILE
: {
2146 struct brw_instruction
*inst0
, *inst1
;
2149 if (intel
->gen
== 5)
2152 assert(loop_stack_depth
> 0);
2154 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
2155 /* patch all the BREAK/CONT instructions from last BGNLOOP */
2156 while (inst0
> loop_stack
[loop_stack_depth
]) {
2158 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
2159 inst0
->bits3
.if_else
.jump_count
== 0) {
2160 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
2162 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
2163 inst0
->bits3
.if_else
.jump_count
== 0) {
2164 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
2172 case FS_OPCODE_SQRT
:
2173 case FS_OPCODE_EXP2
:
2174 case FS_OPCODE_LOG2
:
2178 generate_math(inst
, dst
, src
);
2180 case FS_OPCODE_LINTERP
:
2181 generate_linterp(inst
, dst
, src
);
2186 generate_tex(inst
, dst
, src
[0]);
2188 case FS_OPCODE_DISCARD
:
2189 generate_discard(inst
, dst
/* src0 == dst */);
2192 generate_ddx(inst
, dst
, src
[0]);
2195 generate_ddy(inst
, dst
, src
[0]);
2197 case FS_OPCODE_FB_WRITE
:
2198 generate_fb_write(inst
);
2201 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
2202 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
2203 brw_opcodes
[inst
->opcode
].name
);
2205 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
2210 if (annotation_len
< p
->nr_insn
) {
2211 annotation_len
*= 2;
2212 if (annotation_len
< 16)
2213 annotation_len
= 16;
2215 this->annotation_string
= talloc_realloc(this->mem_ctx
,
2219 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
2225 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
2226 this->annotation_string
[i
] = inst
->annotation
;
2227 this->annotation_ir
[i
] = inst
->ir
;
2229 last_native_inst
= p
->nr_insn
;
2234 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
2236 struct brw_compile
*p
= &c
->func
;
2237 struct intel_context
*intel
= &brw
->intel
;
2238 GLcontext
*ctx
= &intel
->ctx
;
2239 struct brw_shader
*shader
= NULL
;
2240 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
2248 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
2249 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
2250 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
2257 /* We always use 8-wide mode, at least for now. For one, flow
2258 * control only works in 8-wide. Also, when we're fragment shader
2259 * bound, we're almost always under register pressure as well, so
2260 * 8-wide would save us from the performance cliff of spilling
2263 c
->dispatch_width
= 8;
2265 if (INTEL_DEBUG
& DEBUG_WM
) {
2266 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
2267 _mesa_print_ir(shader
->ir
, NULL
);
2271 /* Now the main event: Visit the shader IR and generate our FS IR for it.
2273 fs_visitor
v(c
, shader
);
2278 v
.emit_interpolation_setup();
2280 /* Generate FS IR for main(). (the visitor only descends into
2281 * functions called "main").
2283 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
2284 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
2290 v
.assign_curb_setup();
2291 v
.assign_urb_setup();
2297 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
2302 if (INTEL_DEBUG
& DEBUG_WM
) {
2303 const char *last_annotation_string
= NULL
;
2304 ir_instruction
*last_annotation_ir
= NULL
;
2306 printf("Native code for fragment shader %d:\n", prog
->Name
);
2307 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
2308 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
2309 last_annotation_ir
= v
.annotation_ir
[i
];
2310 if (last_annotation_ir
) {
2312 last_annotation_ir
->print();
2316 if (last_annotation_string
!= v
.annotation_string
[i
]) {
2317 last_annotation_string
= v
.annotation_string
[i
];
2318 if (last_annotation_string
)
2319 printf(" %s\n", last_annotation_string
);
2321 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
2326 c
->prog_data
.total_grf
= v
.grf_used
;
2327 c
->prog_data
.total_scratch
= 0;