i956: Make new FS discard do its work in a temp, not the null reg!
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 extern "C" {
29
30 #include <sys/types.h>
31
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/sampler.h"
39 #include "program/hash_table.h"
40 #include "brw_context.h"
41 #include "brw_eu.h"
42 #include "brw_wm.h"
43 #include "talloc.h"
44 }
45 #include "../glsl/glsl_types.h"
46 #include "../glsl/ir_optimization.h"
47 #include "../glsl/ir_print_visitor.h"
48
49 enum register_file {
50 ARF = BRW_ARCHITECTURE_REGISTER_FILE,
51 GRF = BRW_GENERAL_REGISTER_FILE,
52 MRF = BRW_MESSAGE_REGISTER_FILE,
53 IMM = BRW_IMMEDIATE_VALUE,
54 FIXED_HW_REG, /* a struct brw_reg */
55 UNIFORM, /* prog_data->params[hw_reg] */
56 BAD_FILE
57 };
58
59 enum fs_opcodes {
60 FS_OPCODE_FB_WRITE = 256,
61 FS_OPCODE_RCP,
62 FS_OPCODE_RSQ,
63 FS_OPCODE_SQRT,
64 FS_OPCODE_EXP2,
65 FS_OPCODE_LOG2,
66 FS_OPCODE_POW,
67 FS_OPCODE_SIN,
68 FS_OPCODE_COS,
69 FS_OPCODE_DDX,
70 FS_OPCODE_DDY,
71 FS_OPCODE_LINTERP,
72 FS_OPCODE_TEX,
73 FS_OPCODE_TXB,
74 FS_OPCODE_TXL,
75 FS_OPCODE_DISCARD,
76 };
77
78 static int using_new_fs = -1;
79 static struct brw_reg brw_reg_from_fs_reg(class fs_reg *reg);
80
81 struct gl_shader *
82 brw_new_shader(GLcontext *ctx, GLuint name, GLuint type)
83 {
84 struct brw_shader *shader;
85
86 shader = talloc_zero(NULL, struct brw_shader);
87 if (shader) {
88 shader->base.Type = type;
89 shader->base.Name = name;
90 _mesa_init_shader(ctx, &shader->base);
91 }
92
93 return &shader->base;
94 }
95
96 struct gl_shader_program *
97 brw_new_shader_program(GLcontext *ctx, GLuint name)
98 {
99 struct brw_shader_program *prog;
100 prog = talloc_zero(NULL, struct brw_shader_program);
101 if (prog) {
102 prog->base.Name = name;
103 _mesa_init_shader_program(ctx, &prog->base);
104 }
105 return &prog->base;
106 }
107
108 GLboolean
109 brw_compile_shader(GLcontext *ctx, struct gl_shader *shader)
110 {
111 if (!_mesa_ir_compile_shader(ctx, shader))
112 return GL_FALSE;
113
114 return GL_TRUE;
115 }
116
117 GLboolean
118 brw_link_shader(GLcontext *ctx, struct gl_shader_program *prog)
119 {
120 if (using_new_fs == -1)
121 using_new_fs = getenv("INTEL_NEW_FS") != NULL;
122
123 for (unsigned i = 0; i < prog->_NumLinkedShaders; i++) {
124 struct brw_shader *shader = (struct brw_shader *)prog->_LinkedShaders[i];
125
126 if (using_new_fs && shader->base.Type == GL_FRAGMENT_SHADER) {
127 void *mem_ctx = talloc_new(NULL);
128 bool progress;
129
130 if (shader->ir)
131 talloc_free(shader->ir);
132 shader->ir = new(shader) exec_list;
133 clone_ir_list(mem_ctx, shader->ir, shader->base.ir);
134
135 do_mat_op_to_vec(shader->ir);
136 do_mod_to_fract(shader->ir);
137 do_div_to_mul_rcp(shader->ir);
138 do_sub_to_add_neg(shader->ir);
139 do_explog_to_explog2(shader->ir);
140
141 do {
142 progress = false;
143
144 brw_do_channel_expressions(shader->ir);
145 brw_do_vector_splitting(shader->ir);
146
147 progress = do_lower_jumps(shader->ir, true, true,
148 true, /* main return */
149 false, /* continue */
150 false /* loops */
151 ) || progress;
152
153 progress = do_common_optimization(shader->ir, true, 32) || progress;
154
155 progress = lower_noise(shader->ir) || progress;
156 progress =
157 lower_variable_index_to_cond_assign(shader->ir,
158 GL_TRUE, /* input */
159 GL_TRUE, /* output */
160 GL_TRUE, /* temp */
161 GL_TRUE /* uniform */
162 ) || progress;
163 } while (progress);
164
165 validate_ir_tree(shader->ir);
166
167 reparent_ir(shader->ir, shader->ir);
168 talloc_free(mem_ctx);
169 }
170 }
171
172 if (!_mesa_ir_link_shader(ctx, prog))
173 return GL_FALSE;
174
175 return GL_TRUE;
176 }
177
178 static int
179 type_size(const struct glsl_type *type)
180 {
181 unsigned int size, i;
182
183 switch (type->base_type) {
184 case GLSL_TYPE_UINT:
185 case GLSL_TYPE_INT:
186 case GLSL_TYPE_FLOAT:
187 case GLSL_TYPE_BOOL:
188 return type->components();
189 case GLSL_TYPE_ARRAY:
190 return type_size(type->fields.array) * type->length;
191 case GLSL_TYPE_STRUCT:
192 size = 0;
193 for (i = 0; i < type->length; i++) {
194 size += type_size(type->fields.structure[i].type);
195 }
196 return size;
197 case GLSL_TYPE_SAMPLER:
198 /* Samplers take up no register space, since they're baked in at
199 * link time.
200 */
201 return 0;
202 default:
203 assert(!"not reached");
204 return 0;
205 }
206 }
207
208 class fs_reg {
209 public:
210 /* Callers of this talloc-based new need not call delete. It's
211 * easier to just talloc_free 'ctx' (or any of its ancestors). */
212 static void* operator new(size_t size, void *ctx)
213 {
214 void *node;
215
216 node = talloc_size(ctx, size);
217 assert(node != NULL);
218
219 return node;
220 }
221
222 void init()
223 {
224 this->reg = 0;
225 this->reg_offset = 0;
226 this->negate = 0;
227 this->abs = 0;
228 this->hw_reg = -1;
229 }
230
231 /** Generic unset register constructor. */
232 fs_reg()
233 {
234 init();
235 this->file = BAD_FILE;
236 }
237
238 /** Immediate value constructor. */
239 fs_reg(float f)
240 {
241 init();
242 this->file = IMM;
243 this->type = BRW_REGISTER_TYPE_F;
244 this->imm.f = f;
245 }
246
247 /** Immediate value constructor. */
248 fs_reg(int32_t i)
249 {
250 init();
251 this->file = IMM;
252 this->type = BRW_REGISTER_TYPE_D;
253 this->imm.i = i;
254 }
255
256 /** Immediate value constructor. */
257 fs_reg(uint32_t u)
258 {
259 init();
260 this->file = IMM;
261 this->type = BRW_REGISTER_TYPE_UD;
262 this->imm.u = u;
263 }
264
265 /** Fixed brw_reg Immediate value constructor. */
266 fs_reg(struct brw_reg fixed_hw_reg)
267 {
268 init();
269 this->file = FIXED_HW_REG;
270 this->fixed_hw_reg = fixed_hw_reg;
271 this->type = fixed_hw_reg.type;
272 }
273
274 fs_reg(enum register_file file, int hw_reg);
275 fs_reg(class fs_visitor *v, const struct glsl_type *type);
276
277 /** Register file: ARF, GRF, MRF, IMM. */
278 enum register_file file;
279 /** Abstract register number. 0 = fixed hw reg */
280 int reg;
281 /** Offset within the abstract register. */
282 int reg_offset;
283 /** HW register number. Generally unset until register allocation. */
284 int hw_reg;
285 /** Register type. BRW_REGISTER_TYPE_* */
286 int type;
287 bool negate;
288 bool abs;
289 struct brw_reg fixed_hw_reg;
290
291 /** Value for file == BRW_IMMMEDIATE_FILE */
292 union {
293 int32_t i;
294 uint32_t u;
295 float f;
296 } imm;
297 };
298
299 static const fs_reg reg_undef;
300 static const fs_reg reg_null(ARF, BRW_ARF_NULL);
301
302 class fs_inst : public exec_node {
303 public:
304 /* Callers of this talloc-based new need not call delete. It's
305 * easier to just talloc_free 'ctx' (or any of its ancestors). */
306 static void* operator new(size_t size, void *ctx)
307 {
308 void *node;
309
310 node = talloc_zero_size(ctx, size);
311 assert(node != NULL);
312
313 return node;
314 }
315
316 void init()
317 {
318 this->opcode = BRW_OPCODE_NOP;
319 this->saturate = false;
320 this->conditional_mod = BRW_CONDITIONAL_NONE;
321 this->predicated = false;
322 this->sampler = 0;
323 this->target = 0;
324 this->eot = false;
325 this->shadow_compare = false;
326 }
327
328 fs_inst()
329 {
330 init();
331 }
332
333 fs_inst(int opcode)
334 {
335 init();
336 this->opcode = opcode;
337 }
338
339 fs_inst(int opcode, fs_reg dst, fs_reg src0)
340 {
341 init();
342 this->opcode = opcode;
343 this->dst = dst;
344 this->src[0] = src0;
345 }
346
347 fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1)
348 {
349 init();
350 this->opcode = opcode;
351 this->dst = dst;
352 this->src[0] = src0;
353 this->src[1] = src1;
354 }
355
356 fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2)
357 {
358 init();
359 this->opcode = opcode;
360 this->dst = dst;
361 this->src[0] = src0;
362 this->src[1] = src1;
363 this->src[2] = src2;
364 }
365
366 int opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
367 fs_reg dst;
368 fs_reg src[3];
369 bool saturate;
370 bool predicated;
371 int conditional_mod; /**< BRW_CONDITIONAL_* */
372
373 int mlen; /**< SEND message length */
374 int sampler;
375 int target; /**< MRT target. */
376 bool eot;
377 bool shadow_compare;
378
379 /** @{
380 * Annotation for the generated IR. One of the two can be set.
381 */
382 ir_instruction *ir;
383 const char *annotation;
384 /** @} */
385 };
386
387 class fs_visitor : public ir_visitor
388 {
389 public:
390
391 fs_visitor(struct brw_wm_compile *c, struct brw_shader *shader)
392 {
393 this->c = c;
394 this->p = &c->func;
395 this->brw = p->brw;
396 this->fp = brw->fragment_program;
397 this->intel = &brw->intel;
398 this->ctx = &intel->ctx;
399 this->mem_ctx = talloc_new(NULL);
400 this->shader = shader;
401 this->fail = false;
402 this->next_abstract_grf = 1;
403 this->variable_ht = hash_table_ctor(0,
404 hash_table_pointer_hash,
405 hash_table_pointer_compare);
406
407 this->frag_color = NULL;
408 this->frag_data = NULL;
409 this->frag_depth = NULL;
410 this->first_non_payload_grf = 0;
411
412 this->current_annotation = NULL;
413 this->annotation_string = NULL;
414 this->annotation_ir = NULL;
415 this->base_ir = NULL;
416 }
417 ~fs_visitor()
418 {
419 talloc_free(this->mem_ctx);
420 hash_table_dtor(this->variable_ht);
421 }
422
423 fs_reg *variable_storage(ir_variable *var);
424
425 void visit(ir_variable *ir);
426 void visit(ir_assignment *ir);
427 void visit(ir_dereference_variable *ir);
428 void visit(ir_dereference_record *ir);
429 void visit(ir_dereference_array *ir);
430 void visit(ir_expression *ir);
431 void visit(ir_texture *ir);
432 void visit(ir_if *ir);
433 void visit(ir_constant *ir);
434 void visit(ir_swizzle *ir);
435 void visit(ir_return *ir);
436 void visit(ir_loop *ir);
437 void visit(ir_loop_jump *ir);
438 void visit(ir_discard *ir);
439 void visit(ir_call *ir);
440 void visit(ir_function *ir);
441 void visit(ir_function_signature *ir);
442
443 fs_inst *emit(fs_inst inst);
444 void assign_curb_setup();
445 void assign_urb_setup();
446 void assign_regs();
447 void generate_code();
448 void generate_fb_write(fs_inst *inst);
449 void generate_linterp(fs_inst *inst, struct brw_reg dst,
450 struct brw_reg *src);
451 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
452 void generate_math(fs_inst *inst, struct brw_reg dst, struct brw_reg *src);
453 void generate_discard(fs_inst *inst, struct brw_reg temp);
454 void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
455 void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
456
457 void emit_dummy_fs();
458 void emit_fragcoord_interpolation(ir_variable *ir);
459 void emit_general_interpolation(ir_variable *ir);
460 void emit_interpolation_setup();
461 void emit_fb_writes();
462
463 struct brw_reg interp_reg(int location, int channel);
464 int setup_uniform_values(int loc, const glsl_type *type);
465 void setup_builtin_uniform_values(ir_variable *ir);
466
467 struct brw_context *brw;
468 const struct gl_fragment_program *fp;
469 struct intel_context *intel;
470 GLcontext *ctx;
471 struct brw_wm_compile *c;
472 struct brw_compile *p;
473 struct brw_shader *shader;
474 void *mem_ctx;
475 exec_list instructions;
476 int next_abstract_grf;
477 struct hash_table *variable_ht;
478 ir_variable *frag_color, *frag_data, *frag_depth;
479 int first_non_payload_grf;
480
481 /** @{ debug annotation info */
482 const char *current_annotation;
483 ir_instruction *base_ir;
484 const char **annotation_string;
485 ir_instruction **annotation_ir;
486 /** @} */
487
488 bool fail;
489
490 /* Result of last visit() method. */
491 fs_reg result;
492
493 fs_reg pixel_x;
494 fs_reg pixel_y;
495 fs_reg wpos_w;
496 fs_reg pixel_w;
497 fs_reg delta_x;
498 fs_reg delta_y;
499
500 int grf_used;
501
502 };
503
504 /** Fixed HW reg constructor. */
505 fs_reg::fs_reg(enum register_file file, int hw_reg)
506 {
507 init();
508 this->file = file;
509 this->hw_reg = hw_reg;
510 this->type = BRW_REGISTER_TYPE_F;
511 }
512
513 int
514 brw_type_for_base_type(const struct glsl_type *type)
515 {
516 switch (type->base_type) {
517 case GLSL_TYPE_FLOAT:
518 return BRW_REGISTER_TYPE_F;
519 case GLSL_TYPE_INT:
520 case GLSL_TYPE_BOOL:
521 return BRW_REGISTER_TYPE_D;
522 case GLSL_TYPE_UINT:
523 return BRW_REGISTER_TYPE_UD;
524 case GLSL_TYPE_ARRAY:
525 case GLSL_TYPE_STRUCT:
526 /* These should be overridden with the type of the member when
527 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
528 * way to trip up if we don't.
529 */
530 return BRW_REGISTER_TYPE_UD;
531 default:
532 assert(!"not reached");
533 return BRW_REGISTER_TYPE_F;
534 }
535 }
536
537 /** Automatic reg constructor. */
538 fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type)
539 {
540 init();
541
542 this->file = GRF;
543 this->reg = v->next_abstract_grf;
544 this->reg_offset = 0;
545 v->next_abstract_grf += type_size(type);
546 this->type = brw_type_for_base_type(type);
547 }
548
549 fs_reg *
550 fs_visitor::variable_storage(ir_variable *var)
551 {
552 return (fs_reg *)hash_table_find(this->variable_ht, var);
553 }
554
555 /* Our support for uniforms is piggy-backed on the struct
556 * gl_fragment_program, because that's where the values actually
557 * get stored, rather than in some global gl_shader_program uniform
558 * store.
559 */
560 int
561 fs_visitor::setup_uniform_values(int loc, const glsl_type *type)
562 {
563 unsigned int offset = 0;
564 float *vec_values;
565
566 if (type->is_matrix()) {
567 const glsl_type *column = glsl_type::get_instance(GLSL_TYPE_FLOAT,
568 type->vector_elements,
569 1);
570
571 for (unsigned int i = 0; i < type->matrix_columns; i++) {
572 offset += setup_uniform_values(loc + offset, column);
573 }
574
575 return offset;
576 }
577
578 switch (type->base_type) {
579 case GLSL_TYPE_FLOAT:
580 case GLSL_TYPE_UINT:
581 case GLSL_TYPE_INT:
582 case GLSL_TYPE_BOOL:
583 vec_values = fp->Base.Parameters->ParameterValues[loc];
584 for (unsigned int i = 0; i < type->vector_elements; i++) {
585 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[i];
586 }
587 return 1;
588
589 case GLSL_TYPE_STRUCT:
590 for (unsigned int i = 0; i < type->length; i++) {
591 offset += setup_uniform_values(loc + offset,
592 type->fields.structure[i].type);
593 }
594 return offset;
595
596 case GLSL_TYPE_ARRAY:
597 for (unsigned int i = 0; i < type->length; i++) {
598 offset += setup_uniform_values(loc + offset, type->fields.array);
599 }
600 return offset;
601
602 case GLSL_TYPE_SAMPLER:
603 /* The sampler takes up a slot, but we don't use any values from it. */
604 return 1;
605
606 default:
607 assert(!"not reached");
608 return 0;
609 }
610 }
611
612
613 /* Our support for builtin uniforms is even scarier than non-builtin.
614 * It sits on top of the PROG_STATE_VAR parameters that are
615 * automatically updated from GL context state.
616 */
617 void
618 fs_visitor::setup_builtin_uniform_values(ir_variable *ir)
619 {
620 const struct gl_builtin_uniform_desc *statevar = NULL;
621
622 for (unsigned int i = 0; _mesa_builtin_uniform_desc[i].name; i++) {
623 statevar = &_mesa_builtin_uniform_desc[i];
624 if (strcmp(ir->name, _mesa_builtin_uniform_desc[i].name) == 0)
625 break;
626 }
627
628 if (!statevar->name) {
629 this->fail = true;
630 printf("Failed to find builtin uniform `%s'\n", ir->name);
631 return;
632 }
633
634 int array_count;
635 if (ir->type->is_array()) {
636 array_count = ir->type->length;
637 } else {
638 array_count = 1;
639 }
640
641 for (int a = 0; a < array_count; a++) {
642 for (unsigned int i = 0; i < statevar->num_elements; i++) {
643 struct gl_builtin_uniform_element *element = &statevar->elements[i];
644 int tokens[STATE_LENGTH];
645
646 memcpy(tokens, element->tokens, sizeof(element->tokens));
647 if (ir->type->is_array()) {
648 tokens[1] = a;
649 }
650
651 /* This state reference has already been setup by ir_to_mesa,
652 * but we'll get the same index back here.
653 */
654 int index = _mesa_add_state_reference(this->fp->Base.Parameters,
655 (gl_state_index *)tokens);
656 float *vec_values = this->fp->Base.Parameters->ParameterValues[index];
657
658 /* Add each of the unique swizzles of the element as a
659 * parameter. This'll end up matching the expected layout of
660 * the array/matrix/structure we're trying to fill in.
661 */
662 int last_swiz = -1;
663 for (unsigned int i = 0; i < 4; i++) {
664 int this_swiz = GET_SWZ(element->swizzle, i);
665 if (this_swiz == last_swiz)
666 break;
667 last_swiz = this_swiz;
668
669 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[i];
670 }
671 }
672 }
673 }
674
675 void
676 fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
677 {
678 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
679 fs_reg wpos = *reg;
680 fs_reg neg_y = this->pixel_y;
681 neg_y.negate = true;
682
683 /* gl_FragCoord.x */
684 if (ir->pixel_center_integer) {
685 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_x));
686 } else {
687 emit(fs_inst(BRW_OPCODE_ADD, wpos, this->pixel_x, fs_reg(0.5f)));
688 }
689 wpos.reg_offset++;
690
691 /* gl_FragCoord.y */
692 if (ir->origin_upper_left && ir->pixel_center_integer) {
693 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_y));
694 } else {
695 fs_reg pixel_y = this->pixel_y;
696 float offset = (ir->pixel_center_integer ? 0.0 : 0.5);
697
698 if (!ir->origin_upper_left) {
699 pixel_y.negate = true;
700 offset += c->key.drawable_height - 1.0;
701 }
702
703 emit(fs_inst(BRW_OPCODE_ADD, wpos, pixel_y, fs_reg(offset)));
704 }
705 wpos.reg_offset++;
706
707 /* gl_FragCoord.z */
708 emit(fs_inst(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y,
709 interp_reg(FRAG_ATTRIB_WPOS, 2)));
710 wpos.reg_offset++;
711
712 /* gl_FragCoord.w: Already set up in emit_interpolation */
713 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->wpos_w));
714
715 hash_table_insert(this->variable_ht, reg, ir);
716 }
717
718
719 void
720 fs_visitor::emit_general_interpolation(ir_variable *ir)
721 {
722 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
723 /* Interpolation is always in floating point regs. */
724 reg->type = BRW_REGISTER_TYPE_F;
725 fs_reg attr = *reg;
726
727 unsigned int array_elements;
728 const glsl_type *type;
729
730 if (ir->type->is_array()) {
731 array_elements = ir->type->length;
732 if (array_elements == 0) {
733 this->fail = true;
734 }
735 type = ir->type->fields.array;
736 } else {
737 array_elements = 1;
738 type = ir->type;
739 }
740
741 int location = ir->location;
742 for (unsigned int i = 0; i < array_elements; i++) {
743 for (unsigned int j = 0; j < type->matrix_columns; j++) {
744 if (!(fp->Base.InputsRead & BITFIELD64_BIT(location))) {
745 /* If there's no incoming setup data for this slot, don't
746 * emit interpolation for it (since it's not used, and
747 * we'd fall over later trying to find the setup data.
748 */
749 attr.reg_offset += type->vector_elements;
750 continue;
751 }
752
753 for (unsigned int c = 0; c < type->vector_elements; c++) {
754 struct brw_reg interp = interp_reg(location, c);
755 emit(fs_inst(FS_OPCODE_LINTERP,
756 attr,
757 this->delta_x,
758 this->delta_y,
759 fs_reg(interp)));
760 attr.reg_offset++;
761 }
762 attr.reg_offset -= type->vector_elements;
763
764 for (unsigned int c = 0; c < type->vector_elements; c++) {
765 emit(fs_inst(BRW_OPCODE_MUL,
766 attr,
767 attr,
768 this->pixel_w));
769 attr.reg_offset++;
770 }
771 location++;
772 }
773 }
774
775 hash_table_insert(this->variable_ht, reg, ir);
776 }
777
778 void
779 fs_visitor::visit(ir_variable *ir)
780 {
781 fs_reg *reg = NULL;
782
783 if (variable_storage(ir))
784 return;
785
786 if (strcmp(ir->name, "gl_FragColor") == 0) {
787 this->frag_color = ir;
788 } else if (strcmp(ir->name, "gl_FragData") == 0) {
789 this->frag_data = ir;
790 } else if (strcmp(ir->name, "gl_FragDepth") == 0) {
791 this->frag_depth = ir;
792 }
793
794 if (ir->mode == ir_var_in) {
795 if (!strcmp(ir->name, "gl_FragCoord")) {
796 emit_fragcoord_interpolation(ir);
797 return;
798 } else if (!strcmp(ir->name, "gl_FrontFacing")) {
799 reg = new(this->mem_ctx) fs_reg(this, ir->type);
800 struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD);
801 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
802 * us front face
803 */
804 fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP,
805 *reg,
806 fs_reg(r1_6ud),
807 fs_reg(1u << 31)));
808 inst->conditional_mod = BRW_CONDITIONAL_L;
809 emit(fs_inst(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u)));
810 } else {
811 emit_general_interpolation(ir);
812 return;
813 }
814 }
815
816 if (ir->mode == ir_var_uniform) {
817 int param_index = c->prog_data.nr_params;
818
819 if (!strncmp(ir->name, "gl_", 3)) {
820 setup_builtin_uniform_values(ir);
821 } else {
822 setup_uniform_values(ir->location, ir->type);
823 }
824
825 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index);
826 }
827
828 if (!reg)
829 reg = new(this->mem_ctx) fs_reg(this, ir->type);
830
831 hash_table_insert(this->variable_ht, reg, ir);
832 }
833
834 void
835 fs_visitor::visit(ir_dereference_variable *ir)
836 {
837 fs_reg *reg = variable_storage(ir->var);
838 this->result = *reg;
839 }
840
841 void
842 fs_visitor::visit(ir_dereference_record *ir)
843 {
844 const glsl_type *struct_type = ir->record->type;
845
846 ir->record->accept(this);
847
848 unsigned int offset = 0;
849 for (unsigned int i = 0; i < struct_type->length; i++) {
850 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0)
851 break;
852 offset += type_size(struct_type->fields.structure[i].type);
853 }
854 this->result.reg_offset += offset;
855 this->result.type = brw_type_for_base_type(ir->type);
856 }
857
858 void
859 fs_visitor::visit(ir_dereference_array *ir)
860 {
861 ir_constant *index;
862 int element_size;
863
864 ir->array->accept(this);
865 index = ir->array_index->as_constant();
866
867 element_size = type_size(ir->type);
868 this->result.type = brw_type_for_base_type(ir->type);
869
870 if (index) {
871 assert(this->result.file == UNIFORM ||
872 (this->result.file == GRF &&
873 this->result.reg != 0));
874 this->result.reg_offset += index->value.i[0] * element_size;
875 } else {
876 assert(!"FINISHME: non-constant array element");
877 }
878 }
879
880 void
881 fs_visitor::visit(ir_expression *ir)
882 {
883 unsigned int operand;
884 fs_reg op[2], temp;
885 fs_reg result;
886 fs_inst *inst;
887
888 for (operand = 0; operand < ir->get_num_operands(); operand++) {
889 ir->operands[operand]->accept(this);
890 if (this->result.file == BAD_FILE) {
891 ir_print_visitor v;
892 printf("Failed to get tree for expression operand:\n");
893 ir->operands[operand]->accept(&v);
894 this->fail = true;
895 }
896 op[operand] = this->result;
897
898 /* Matrix expression operands should have been broken down to vector
899 * operations already.
900 */
901 assert(!ir->operands[operand]->type->is_matrix());
902 /* And then those vector operands should have been broken down to scalar.
903 */
904 assert(!ir->operands[operand]->type->is_vector());
905 }
906
907 /* Storage for our result. If our result goes into an assignment, it will
908 * just get copy-propagated out, so no worries.
909 */
910 this->result = fs_reg(this, ir->type);
911
912 switch (ir->operation) {
913 case ir_unop_logic_not:
914 emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], fs_reg(-1)));
915 break;
916 case ir_unop_neg:
917 op[0].negate = !op[0].negate;
918 this->result = op[0];
919 break;
920 case ir_unop_abs:
921 op[0].abs = true;
922 this->result = op[0];
923 break;
924 case ir_unop_sign:
925 temp = fs_reg(this, ir->type);
926
927 emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)));
928
929 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, op[0], fs_reg(0.0f)));
930 inst->conditional_mod = BRW_CONDITIONAL_G;
931 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)));
932 inst->predicated = true;
933
934 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, op[0], fs_reg(0.0f)));
935 inst->conditional_mod = BRW_CONDITIONAL_L;
936 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)));
937 inst->predicated = true;
938
939 break;
940 case ir_unop_rcp:
941 emit(fs_inst(FS_OPCODE_RCP, this->result, op[0]));
942 break;
943
944 case ir_unop_exp2:
945 emit(fs_inst(FS_OPCODE_EXP2, this->result, op[0]));
946 break;
947 case ir_unop_log2:
948 emit(fs_inst(FS_OPCODE_LOG2, this->result, op[0]));
949 break;
950 case ir_unop_exp:
951 case ir_unop_log:
952 assert(!"not reached: should be handled by ir_explog_to_explog2");
953 break;
954 case ir_unop_sin:
955 emit(fs_inst(FS_OPCODE_SIN, this->result, op[0]));
956 break;
957 case ir_unop_cos:
958 emit(fs_inst(FS_OPCODE_COS, this->result, op[0]));
959 break;
960
961 case ir_unop_dFdx:
962 emit(fs_inst(FS_OPCODE_DDX, this->result, op[0]));
963 break;
964 case ir_unop_dFdy:
965 emit(fs_inst(FS_OPCODE_DDY, this->result, op[0]));
966 break;
967
968 case ir_binop_add:
969 emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], op[1]));
970 break;
971 case ir_binop_sub:
972 assert(!"not reached: should be handled by ir_sub_to_add_neg");
973 break;
974
975 case ir_binop_mul:
976 emit(fs_inst(BRW_OPCODE_MUL, this->result, op[0], op[1]));
977 break;
978 case ir_binop_div:
979 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
980 break;
981 case ir_binop_mod:
982 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
983 break;
984
985 case ir_binop_less:
986 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
987 inst->conditional_mod = BRW_CONDITIONAL_L;
988 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
989 break;
990 case ir_binop_greater:
991 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
992 inst->conditional_mod = BRW_CONDITIONAL_G;
993 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
994 break;
995 case ir_binop_lequal:
996 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
997 inst->conditional_mod = BRW_CONDITIONAL_LE;
998 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
999 break;
1000 case ir_binop_gequal:
1001 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1002 inst->conditional_mod = BRW_CONDITIONAL_GE;
1003 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
1004 break;
1005 case ir_binop_equal:
1006 case ir_binop_all_equal: /* same as nequal for scalars */
1007 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1008 inst->conditional_mod = BRW_CONDITIONAL_Z;
1009 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
1010 break;
1011 case ir_binop_nequal:
1012 case ir_binop_any_nequal: /* same as nequal for scalars */
1013 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1014 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1015 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
1016 break;
1017
1018 case ir_binop_logic_xor:
1019 emit(fs_inst(BRW_OPCODE_XOR, this->result, op[0], op[1]));
1020 break;
1021
1022 case ir_binop_logic_or:
1023 emit(fs_inst(BRW_OPCODE_OR, this->result, op[0], op[1]));
1024 break;
1025
1026 case ir_binop_logic_and:
1027 emit(fs_inst(BRW_OPCODE_AND, this->result, op[0], op[1]));
1028 break;
1029
1030 case ir_binop_dot:
1031 case ir_binop_cross:
1032 case ir_unop_any:
1033 assert(!"not reached: should be handled by brw_fs_channel_expressions");
1034 break;
1035
1036 case ir_unop_noise:
1037 assert(!"not reached: should be handled by lower_noise");
1038 break;
1039
1040 case ir_unop_sqrt:
1041 emit(fs_inst(FS_OPCODE_SQRT, this->result, op[0]));
1042 break;
1043
1044 case ir_unop_rsq:
1045 emit(fs_inst(FS_OPCODE_RSQ, this->result, op[0]));
1046 break;
1047
1048 case ir_unop_i2f:
1049 case ir_unop_b2f:
1050 case ir_unop_b2i:
1051 emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0]));
1052 break;
1053 case ir_unop_f2i:
1054 emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0]));
1055 break;
1056 case ir_unop_f2b:
1057 case ir_unop_i2b:
1058 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], fs_reg(0.0f)));
1059 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1060
1061 case ir_unop_trunc:
1062 emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
1063 break;
1064 case ir_unop_ceil:
1065 op[0].negate = ~op[0].negate;
1066 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
1067 this->result.negate = true;
1068 break;
1069 case ir_unop_floor:
1070 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
1071 break;
1072 case ir_unop_fract:
1073 inst = emit(fs_inst(BRW_OPCODE_FRC, this->result, op[0]));
1074 break;
1075
1076 case ir_binop_min:
1077 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1078 inst->conditional_mod = BRW_CONDITIONAL_L;
1079
1080 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1]));
1081 inst->predicated = true;
1082 break;
1083 case ir_binop_max:
1084 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
1085 inst->conditional_mod = BRW_CONDITIONAL_G;
1086
1087 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1]));
1088 inst->predicated = true;
1089 break;
1090
1091 case ir_binop_pow:
1092 inst = emit(fs_inst(FS_OPCODE_POW, this->result, op[0], op[1]));
1093 break;
1094
1095 case ir_unop_bit_not:
1096 case ir_unop_u2f:
1097 case ir_binop_lshift:
1098 case ir_binop_rshift:
1099 case ir_binop_bit_and:
1100 case ir_binop_bit_xor:
1101 case ir_binop_bit_or:
1102 assert(!"GLSL 1.30 features unsupported");
1103 break;
1104 }
1105 }
1106
1107 void
1108 fs_visitor::visit(ir_assignment *ir)
1109 {
1110 struct fs_reg l, r;
1111 int i;
1112 int write_mask;
1113 fs_inst *inst;
1114
1115 /* FINISHME: arrays on the lhs */
1116 ir->lhs->accept(this);
1117 l = this->result;
1118
1119 ir->rhs->accept(this);
1120 r = this->result;
1121
1122 /* FINISHME: This should really set to the correct maximal writemask for each
1123 * FINISHME: component written (in the loops below). This case can only
1124 * FINISHME: occur for matrices, arrays, and structures.
1125 */
1126 if (ir->write_mask == 0) {
1127 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
1128 write_mask = WRITEMASK_XYZW;
1129 } else {
1130 assert(ir->lhs->type->is_vector() || ir->lhs->type->is_scalar());
1131 write_mask = ir->write_mask;
1132 }
1133
1134 assert(l.file != BAD_FILE);
1135 assert(r.file != BAD_FILE);
1136
1137 if (ir->condition) {
1138 /* Get the condition bool into the predicate. */
1139 ir->condition->accept(this);
1140 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, this->result, fs_reg(0)));
1141 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1142 }
1143
1144 for (i = 0; i < type_size(ir->lhs->type); i++) {
1145 if (i >= 4 || (write_mask & (1 << i))) {
1146 inst = emit(fs_inst(BRW_OPCODE_MOV, l, r));
1147 if (ir->condition)
1148 inst->predicated = true;
1149 r.reg_offset++;
1150 }
1151 l.reg_offset++;
1152 }
1153 }
1154
1155 void
1156 fs_visitor::visit(ir_texture *ir)
1157 {
1158 int base_mrf = 2;
1159 fs_inst *inst = NULL;
1160 unsigned int mlen = 0;
1161
1162 ir->coordinate->accept(this);
1163 fs_reg coordinate = this->result;
1164
1165 if (ir->projector) {
1166 fs_reg inv_proj = fs_reg(this, glsl_type::float_type);
1167
1168 ir->projector->accept(this);
1169 emit(fs_inst(FS_OPCODE_RCP, inv_proj, this->result));
1170
1171 fs_reg proj_coordinate = fs_reg(this, ir->coordinate->type);
1172 for (unsigned int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1173 emit(fs_inst(BRW_OPCODE_MUL, proj_coordinate, coordinate, inv_proj));
1174 coordinate.reg_offset++;
1175 proj_coordinate.reg_offset++;
1176 }
1177 proj_coordinate.reg_offset = 0;
1178
1179 coordinate = proj_coordinate;
1180 }
1181
1182 for (mlen = 0; mlen < ir->coordinate->type->vector_elements; mlen++) {
1183 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate));
1184 coordinate.reg_offset++;
1185 }
1186
1187 /* Pre-Ironlake, the 8-wide sampler always took u,v,r. */
1188 if (intel->gen < 5)
1189 mlen = 3;
1190
1191 if (ir->shadow_comparitor) {
1192 /* For shadow comparisons, we have to supply u,v,r. */
1193 mlen = 3;
1194
1195 ir->shadow_comparitor->accept(this);
1196 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1197 mlen++;
1198 }
1199
1200 /* Do we ever want to handle writemasking on texture samples? Is it
1201 * performance relevant?
1202 */
1203 fs_reg dst = fs_reg(this, glsl_type::vec4_type);
1204
1205 switch (ir->op) {
1206 case ir_tex:
1207 inst = emit(fs_inst(FS_OPCODE_TEX, dst, fs_reg(MRF, base_mrf)));
1208 break;
1209 case ir_txb:
1210 ir->lod_info.bias->accept(this);
1211 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1212 mlen++;
1213
1214 inst = emit(fs_inst(FS_OPCODE_TXB, dst, fs_reg(MRF, base_mrf)));
1215 break;
1216 case ir_txl:
1217 ir->lod_info.lod->accept(this);
1218 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1219 mlen++;
1220
1221 inst = emit(fs_inst(FS_OPCODE_TXL, dst, fs_reg(MRF, base_mrf)));
1222 break;
1223 case ir_txd:
1224 case ir_txf:
1225 assert(!"GLSL 1.30 features unsupported");
1226 break;
1227 }
1228
1229 inst->sampler =
1230 _mesa_get_sampler_uniform_value(ir->sampler,
1231 ctx->Shader.CurrentProgram,
1232 &brw->fragment_program->Base);
1233 inst->sampler = c->fp->program.Base.SamplerUnits[inst->sampler];
1234
1235 this->result = dst;
1236
1237 if (ir->shadow_comparitor)
1238 inst->shadow_compare = true;
1239 inst->mlen = mlen;
1240 }
1241
1242 void
1243 fs_visitor::visit(ir_swizzle *ir)
1244 {
1245 ir->val->accept(this);
1246 fs_reg val = this->result;
1247
1248 fs_reg result = fs_reg(this, ir->type);
1249 this->result = result;
1250
1251 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1252 fs_reg channel = val;
1253 int swiz = 0;
1254
1255 switch (i) {
1256 case 0:
1257 swiz = ir->mask.x;
1258 break;
1259 case 1:
1260 swiz = ir->mask.y;
1261 break;
1262 case 2:
1263 swiz = ir->mask.z;
1264 break;
1265 case 3:
1266 swiz = ir->mask.w;
1267 break;
1268 }
1269
1270 channel.reg_offset += swiz;
1271 emit(fs_inst(BRW_OPCODE_MOV, result, channel));
1272 result.reg_offset++;
1273 }
1274 }
1275
1276 void
1277 fs_visitor::visit(ir_discard *ir)
1278 {
1279 fs_reg temp = fs_reg(this, glsl_type::uint_type);
1280
1281 assert(ir->condition == NULL); /* FINISHME */
1282
1283 emit(fs_inst(FS_OPCODE_DISCARD, temp, temp));
1284 }
1285
1286 void
1287 fs_visitor::visit(ir_constant *ir)
1288 {
1289 fs_reg reg(this, ir->type);
1290 this->result = reg;
1291
1292 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1293 switch (ir->type->base_type) {
1294 case GLSL_TYPE_FLOAT:
1295 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.f[i])));
1296 break;
1297 case GLSL_TYPE_UINT:
1298 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.u[i])));
1299 break;
1300 case GLSL_TYPE_INT:
1301 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.i[i])));
1302 break;
1303 case GLSL_TYPE_BOOL:
1304 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg((int)ir->value.b[i])));
1305 break;
1306 default:
1307 assert(!"Non-float/uint/int/bool constant");
1308 }
1309 reg.reg_offset++;
1310 }
1311 }
1312
1313 void
1314 fs_visitor::visit(ir_if *ir)
1315 {
1316 fs_inst *inst;
1317
1318 /* Don't point the annotation at the if statement, because then it plus
1319 * the then and else blocks get printed.
1320 */
1321 this->base_ir = ir->condition;
1322
1323 /* Generate the condition into the condition code. */
1324 ir->condition->accept(this);
1325 inst = emit(fs_inst(BRW_OPCODE_MOV, fs_reg(brw_null_reg()), this->result));
1326 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1327
1328 inst = emit(fs_inst(BRW_OPCODE_IF));
1329 inst->predicated = true;
1330
1331 foreach_iter(exec_list_iterator, iter, ir->then_instructions) {
1332 ir_instruction *ir = (ir_instruction *)iter.get();
1333 this->base_ir = ir;
1334
1335 ir->accept(this);
1336 }
1337
1338 if (!ir->else_instructions.is_empty()) {
1339 emit(fs_inst(BRW_OPCODE_ELSE));
1340
1341 foreach_iter(exec_list_iterator, iter, ir->else_instructions) {
1342 ir_instruction *ir = (ir_instruction *)iter.get();
1343 this->base_ir = ir;
1344
1345 ir->accept(this);
1346 }
1347 }
1348
1349 emit(fs_inst(BRW_OPCODE_ENDIF));
1350 }
1351
1352 void
1353 fs_visitor::visit(ir_loop *ir)
1354 {
1355 fs_reg counter = reg_undef;
1356
1357 if (ir->counter) {
1358 this->base_ir = ir->counter;
1359 ir->counter->accept(this);
1360 counter = *(variable_storage(ir->counter));
1361
1362 if (ir->from) {
1363 this->base_ir = ir->from;
1364 ir->from->accept(this);
1365
1366 emit(fs_inst(BRW_OPCODE_MOV, counter, this->result));
1367 }
1368 }
1369
1370 /* Start a safety counter. If the user messed up their loop
1371 * counting, we don't want to hang the GPU.
1372 */
1373 fs_reg max_iter = fs_reg(this, glsl_type::int_type);
1374 emit(fs_inst(BRW_OPCODE_MOV, max_iter, fs_reg(10000)));
1375
1376 emit(fs_inst(BRW_OPCODE_DO));
1377
1378 if (ir->to) {
1379 this->base_ir = ir->to;
1380 ir->to->accept(this);
1381
1382 fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null,
1383 counter, this->result));
1384 switch (ir->cmp) {
1385 case ir_binop_equal:
1386 inst->conditional_mod = BRW_CONDITIONAL_Z;
1387 break;
1388 case ir_binop_nequal:
1389 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1390 break;
1391 case ir_binop_gequal:
1392 inst->conditional_mod = BRW_CONDITIONAL_GE;
1393 break;
1394 case ir_binop_lequal:
1395 inst->conditional_mod = BRW_CONDITIONAL_LE;
1396 break;
1397 case ir_binop_greater:
1398 inst->conditional_mod = BRW_CONDITIONAL_G;
1399 break;
1400 case ir_binop_less:
1401 inst->conditional_mod = BRW_CONDITIONAL_L;
1402 break;
1403 default:
1404 assert(!"not reached: unknown loop condition");
1405 this->fail = true;
1406 break;
1407 }
1408
1409 inst = emit(fs_inst(BRW_OPCODE_BREAK));
1410 inst->predicated = true;
1411 }
1412
1413 foreach_iter(exec_list_iterator, iter, ir->body_instructions) {
1414 ir_instruction *ir = (ir_instruction *)iter.get();
1415 fs_inst *inst;
1416
1417 this->base_ir = ir;
1418 ir->accept(this);
1419
1420 /* Check the maximum loop iters counter. */
1421 inst = emit(fs_inst(BRW_OPCODE_ADD, max_iter, max_iter, fs_reg(-1)));
1422 inst->conditional_mod = BRW_CONDITIONAL_Z;
1423
1424 inst = emit(fs_inst(BRW_OPCODE_BREAK));
1425 inst->predicated = true;
1426 }
1427
1428 if (ir->increment) {
1429 this->base_ir = ir->increment;
1430 ir->increment->accept(this);
1431 emit(fs_inst(BRW_OPCODE_ADD, counter, counter, this->result));
1432 }
1433
1434 emit(fs_inst(BRW_OPCODE_WHILE));
1435 }
1436
1437 void
1438 fs_visitor::visit(ir_loop_jump *ir)
1439 {
1440 switch (ir->mode) {
1441 case ir_loop_jump::jump_break:
1442 emit(fs_inst(BRW_OPCODE_BREAK));
1443 break;
1444 case ir_loop_jump::jump_continue:
1445 emit(fs_inst(BRW_OPCODE_CONTINUE));
1446 break;
1447 }
1448 }
1449
1450 void
1451 fs_visitor::visit(ir_call *ir)
1452 {
1453 assert(!"FINISHME");
1454 }
1455
1456 void
1457 fs_visitor::visit(ir_return *ir)
1458 {
1459 assert(!"FINISHME");
1460 }
1461
1462 void
1463 fs_visitor::visit(ir_function *ir)
1464 {
1465 /* Ignore function bodies other than main() -- we shouldn't see calls to
1466 * them since they should all be inlined before we get to ir_to_mesa.
1467 */
1468 if (strcmp(ir->name, "main") == 0) {
1469 const ir_function_signature *sig;
1470 exec_list empty;
1471
1472 sig = ir->matching_signature(&empty);
1473
1474 assert(sig);
1475
1476 foreach_iter(exec_list_iterator, iter, sig->body) {
1477 ir_instruction *ir = (ir_instruction *)iter.get();
1478 this->base_ir = ir;
1479
1480 ir->accept(this);
1481 }
1482 }
1483 }
1484
1485 void
1486 fs_visitor::visit(ir_function_signature *ir)
1487 {
1488 assert(!"not reached");
1489 (void)ir;
1490 }
1491
1492 fs_inst *
1493 fs_visitor::emit(fs_inst inst)
1494 {
1495 fs_inst *list_inst = new(mem_ctx) fs_inst;
1496 *list_inst = inst;
1497
1498 list_inst->annotation = this->current_annotation;
1499 list_inst->ir = this->base_ir;
1500
1501 this->instructions.push_tail(list_inst);
1502
1503 return list_inst;
1504 }
1505
1506 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1507 void
1508 fs_visitor::emit_dummy_fs()
1509 {
1510 /* Everyone's favorite color. */
1511 emit(fs_inst(BRW_OPCODE_MOV,
1512 fs_reg(MRF, 2),
1513 fs_reg(1.0f)));
1514 emit(fs_inst(BRW_OPCODE_MOV,
1515 fs_reg(MRF, 3),
1516 fs_reg(0.0f)));
1517 emit(fs_inst(BRW_OPCODE_MOV,
1518 fs_reg(MRF, 4),
1519 fs_reg(1.0f)));
1520 emit(fs_inst(BRW_OPCODE_MOV,
1521 fs_reg(MRF, 5),
1522 fs_reg(0.0f)));
1523
1524 fs_inst *write;
1525 write = emit(fs_inst(FS_OPCODE_FB_WRITE,
1526 fs_reg(0),
1527 fs_reg(0)));
1528 }
1529
1530 /* The register location here is relative to the start of the URB
1531 * data. It will get adjusted to be a real location before
1532 * generate_code() time.
1533 */
1534 struct brw_reg
1535 fs_visitor::interp_reg(int location, int channel)
1536 {
1537 int regnr = location * 2 + channel / 2;
1538 int stride = (channel & 1) * 4;
1539
1540 return brw_vec1_grf(regnr, stride);
1541 }
1542
1543 /** Emits the interpolation for the varying inputs. */
1544 void
1545 fs_visitor::emit_interpolation_setup()
1546 {
1547 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
1548
1549 this->current_annotation = "compute pixel centers";
1550 this->pixel_x = fs_reg(this, glsl_type::uint_type);
1551 this->pixel_y = fs_reg(this, glsl_type::uint_type);
1552 this->pixel_x.type = BRW_REGISTER_TYPE_UW;
1553 this->pixel_y.type = BRW_REGISTER_TYPE_UW;
1554 emit(fs_inst(BRW_OPCODE_ADD,
1555 this->pixel_x,
1556 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
1557 fs_reg(brw_imm_v(0x10101010))));
1558 emit(fs_inst(BRW_OPCODE_ADD,
1559 this->pixel_y,
1560 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
1561 fs_reg(brw_imm_v(0x11001100))));
1562
1563 this->current_annotation = "compute pixel deltas from v0";
1564 this->delta_x = fs_reg(this, glsl_type::float_type);
1565 this->delta_y = fs_reg(this, glsl_type::float_type);
1566 emit(fs_inst(BRW_OPCODE_ADD,
1567 this->delta_x,
1568 this->pixel_x,
1569 fs_reg(negate(brw_vec1_grf(1, 0)))));
1570 emit(fs_inst(BRW_OPCODE_ADD,
1571 this->delta_y,
1572 this->pixel_y,
1573 fs_reg(negate(brw_vec1_grf(1, 1)))));
1574
1575 this->current_annotation = "compute pos.w and 1/pos.w";
1576 /* Compute wpos.w. It's always in our setup, since it's needed to
1577 * interpolate the other attributes.
1578 */
1579 this->wpos_w = fs_reg(this, glsl_type::float_type);
1580 emit(fs_inst(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y,
1581 interp_reg(FRAG_ATTRIB_WPOS, 3)));
1582 /* Compute the pixel 1/W value from wpos.w. */
1583 this->pixel_w = fs_reg(this, glsl_type::float_type);
1584 emit(fs_inst(FS_OPCODE_RCP, this->pixel_w, wpos_w));
1585 this->current_annotation = NULL;
1586 }
1587
1588 void
1589 fs_visitor::emit_fb_writes()
1590 {
1591 this->current_annotation = "FB write header";
1592 int nr = 0;
1593
1594 /* m0, m1 header */
1595 nr += 2;
1596
1597 if (c->key.aa_dest_stencil_reg) {
1598 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
1599 fs_reg(brw_vec8_grf(c->key.aa_dest_stencil_reg, 0))));
1600 }
1601
1602 /* Reserve space for color. It'll be filled in per MRT below. */
1603 int color_mrf = nr;
1604 nr += 4;
1605
1606 if (c->key.source_depth_to_render_target) {
1607 if (c->key.computes_depth) {
1608 /* Hand over gl_FragDepth. */
1609 assert(this->frag_depth);
1610 fs_reg depth = *(variable_storage(this->frag_depth));
1611
1612 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++), depth));
1613 } else {
1614 /* Pass through the payload depth. */
1615 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
1616 fs_reg(brw_vec8_grf(c->key.source_depth_reg, 0))));
1617 }
1618 }
1619
1620 if (c->key.dest_depth_reg) {
1621 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
1622 fs_reg(brw_vec8_grf(c->key.dest_depth_reg, 0))));
1623 }
1624
1625 fs_reg color = reg_undef;
1626 if (this->frag_color)
1627 color = *(variable_storage(this->frag_color));
1628 else if (this->frag_data)
1629 color = *(variable_storage(this->frag_data));
1630
1631 for (int target = 0; target < c->key.nr_color_regions; target++) {
1632 this->current_annotation = talloc_asprintf(this->mem_ctx,
1633 "FB write target %d",
1634 target);
1635 if (this->frag_color || this->frag_data) {
1636 for (int i = 0; i < 4; i++) {
1637 emit(fs_inst(BRW_OPCODE_MOV,
1638 fs_reg(MRF, color_mrf + i),
1639 color));
1640 color.reg_offset++;
1641 }
1642 }
1643
1644 if (this->frag_color)
1645 color.reg_offset -= 4;
1646
1647 fs_inst *inst = emit(fs_inst(FS_OPCODE_FB_WRITE,
1648 reg_undef, reg_undef));
1649 inst->target = target;
1650 inst->mlen = nr;
1651 if (target == c->key.nr_color_regions - 1)
1652 inst->eot = true;
1653 }
1654
1655 if (c->key.nr_color_regions == 0) {
1656 fs_inst *inst = emit(fs_inst(FS_OPCODE_FB_WRITE,
1657 reg_undef, reg_undef));
1658 inst->mlen = nr;
1659 inst->eot = true;
1660 }
1661
1662 this->current_annotation = NULL;
1663 }
1664
1665 void
1666 fs_visitor::generate_fb_write(fs_inst *inst)
1667 {
1668 GLboolean eot = inst->eot;
1669
1670 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1671 * move, here's g1.
1672 */
1673 brw_push_insn_state(p);
1674 brw_set_mask_control(p, BRW_MASK_DISABLE);
1675 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1676 brw_MOV(p,
1677 brw_message_reg(1),
1678 brw_vec8_grf(1, 0));
1679 brw_pop_insn_state(p);
1680
1681 brw_fb_WRITE(p,
1682 8, /* dispatch_width */
1683 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW),
1684 0, /* base MRF */
1685 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
1686 inst->target,
1687 inst->mlen,
1688 0,
1689 eot);
1690 }
1691
1692 void
1693 fs_visitor::generate_linterp(fs_inst *inst,
1694 struct brw_reg dst, struct brw_reg *src)
1695 {
1696 struct brw_reg delta_x = src[0];
1697 struct brw_reg delta_y = src[1];
1698 struct brw_reg interp = src[2];
1699
1700 if (brw->has_pln &&
1701 delta_y.nr == delta_x.nr + 1 &&
1702 (intel->gen >= 6 || (delta_x.nr & 1) == 0)) {
1703 brw_PLN(p, dst, interp, delta_x);
1704 } else {
1705 brw_LINE(p, brw_null_reg(), interp, delta_x);
1706 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
1707 }
1708 }
1709
1710 void
1711 fs_visitor::generate_math(fs_inst *inst,
1712 struct brw_reg dst, struct brw_reg *src)
1713 {
1714 int op;
1715
1716 switch (inst->opcode) {
1717 case FS_OPCODE_RCP:
1718 op = BRW_MATH_FUNCTION_INV;
1719 break;
1720 case FS_OPCODE_RSQ:
1721 op = BRW_MATH_FUNCTION_RSQ;
1722 break;
1723 case FS_OPCODE_SQRT:
1724 op = BRW_MATH_FUNCTION_SQRT;
1725 break;
1726 case FS_OPCODE_EXP2:
1727 op = BRW_MATH_FUNCTION_EXP;
1728 break;
1729 case FS_OPCODE_LOG2:
1730 op = BRW_MATH_FUNCTION_LOG;
1731 break;
1732 case FS_OPCODE_POW:
1733 op = BRW_MATH_FUNCTION_POW;
1734 break;
1735 case FS_OPCODE_SIN:
1736 op = BRW_MATH_FUNCTION_SIN;
1737 break;
1738 case FS_OPCODE_COS:
1739 op = BRW_MATH_FUNCTION_COS;
1740 break;
1741 default:
1742 assert(!"not reached: unknown math function");
1743 op = 0;
1744 break;
1745 }
1746
1747 if (inst->opcode == FS_OPCODE_POW) {
1748 brw_MOV(p, brw_message_reg(3), src[1]);
1749 }
1750
1751 brw_math(p, dst,
1752 op,
1753 inst->saturate ? BRW_MATH_SATURATE_SATURATE :
1754 BRW_MATH_SATURATE_NONE,
1755 2, src[0],
1756 BRW_MATH_DATA_VECTOR,
1757 BRW_MATH_PRECISION_FULL);
1758 }
1759
1760 void
1761 fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
1762 {
1763 int msg_type = -1;
1764 int rlen = 4;
1765
1766 if (intel->gen == 5) {
1767 switch (inst->opcode) {
1768 case FS_OPCODE_TEX:
1769 if (inst->shadow_compare) {
1770 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5;
1771 } else {
1772 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_GEN5;
1773 }
1774 break;
1775 case FS_OPCODE_TXB:
1776 if (inst->shadow_compare) {
1777 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5;
1778 } else {
1779 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5;
1780 }
1781 break;
1782 }
1783 } else {
1784 switch (inst->opcode) {
1785 case FS_OPCODE_TEX:
1786 /* Note that G45 and older determines shadow compare and dispatch width
1787 * from message length for most messages.
1788 */
1789 if (inst->shadow_compare) {
1790 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
1791 } else {
1792 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
1793 }
1794 case FS_OPCODE_TXB:
1795 if (inst->shadow_compare) {
1796 assert(!"FINISHME: shadow compare with bias.");
1797 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
1798 } else {
1799 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
1800 rlen = 8;
1801 }
1802 break;
1803 }
1804 }
1805 assert(msg_type != -1);
1806
1807 /* g0 header. */
1808 src.nr--;
1809
1810 brw_SAMPLE(p,
1811 retype(dst, BRW_REGISTER_TYPE_UW),
1812 src.nr,
1813 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
1814 SURF_INDEX_TEXTURE(inst->sampler),
1815 inst->sampler,
1816 WRITEMASK_XYZW,
1817 msg_type,
1818 rlen,
1819 inst->mlen + 1,
1820 0,
1821 1,
1822 BRW_SAMPLER_SIMD_MODE_SIMD8);
1823 }
1824
1825
1826 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1827 * looking like:
1828 *
1829 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1830 *
1831 * and we're trying to produce:
1832 *
1833 * DDX DDY
1834 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1835 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1836 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1837 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1838 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1839 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1840 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1841 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1842 *
1843 * and add another set of two more subspans if in 16-pixel dispatch mode.
1844 *
1845 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1846 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1847 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
1848 * between each other. We could probably do it like ddx and swizzle the right
1849 * order later, but bail for now and just produce
1850 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
1851 */
1852 void
1853 fs_visitor::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
1854 {
1855 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
1856 BRW_REGISTER_TYPE_F,
1857 BRW_VERTICAL_STRIDE_2,
1858 BRW_WIDTH_2,
1859 BRW_HORIZONTAL_STRIDE_0,
1860 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1861 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1862 BRW_REGISTER_TYPE_F,
1863 BRW_VERTICAL_STRIDE_2,
1864 BRW_WIDTH_2,
1865 BRW_HORIZONTAL_STRIDE_0,
1866 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1867 brw_ADD(p, dst, src0, negate(src1));
1868 }
1869
1870 void
1871 fs_visitor::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
1872 {
1873 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1874 BRW_REGISTER_TYPE_F,
1875 BRW_VERTICAL_STRIDE_4,
1876 BRW_WIDTH_4,
1877 BRW_HORIZONTAL_STRIDE_0,
1878 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1879 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
1880 BRW_REGISTER_TYPE_F,
1881 BRW_VERTICAL_STRIDE_4,
1882 BRW_WIDTH_4,
1883 BRW_HORIZONTAL_STRIDE_0,
1884 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1885 brw_ADD(p, dst, src0, negate(src1));
1886 }
1887
1888 void
1889 fs_visitor::generate_discard(fs_inst *inst, struct brw_reg temp)
1890 {
1891 struct brw_reg g0 = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1892 temp = brw_uw1_reg(temp.file, temp.nr, 0);
1893
1894 brw_push_insn_state(p);
1895 brw_set_mask_control(p, BRW_MASK_DISABLE);
1896 brw_NOT(p, temp, brw_mask_reg(1)); /* IMASK */
1897 brw_AND(p, g0, temp, g0);
1898 brw_pop_insn_state(p);
1899 }
1900
1901 static void
1902 trivial_assign_reg(int header_size, fs_reg *reg)
1903 {
1904 if (reg->file == GRF && reg->reg != 0) {
1905 reg->hw_reg = header_size + reg->reg - 1 + reg->reg_offset;
1906 reg->reg = 0;
1907 }
1908 }
1909
1910 void
1911 fs_visitor::assign_curb_setup()
1912 {
1913 c->prog_data.first_curbe_grf = c->key.nr_payload_regs;
1914 c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8;
1915
1916 if (intel->gen == 5 && (c->prog_data.first_curbe_grf +
1917 c->prog_data.curb_read_length) & 1) {
1918 /* Align the start of the interpolation coefficients so that we can use
1919 * the PLN instruction.
1920 */
1921 c->prog_data.first_curbe_grf++;
1922 }
1923
1924 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1925 foreach_iter(exec_list_iterator, iter, this->instructions) {
1926 fs_inst *inst = (fs_inst *)iter.get();
1927
1928 for (unsigned int i = 0; i < 3; i++) {
1929 if (inst->src[i].file == UNIFORM) {
1930 int constant_nr = inst->src[i].hw_reg + inst->src[i].reg_offset;
1931 struct brw_reg brw_reg = brw_vec1_grf(c->prog_data.first_curbe_grf +
1932 constant_nr / 8,
1933 constant_nr % 8);
1934
1935 inst->src[i].file = FIXED_HW_REG;
1936 inst->src[i].fixed_hw_reg = brw_reg;
1937 }
1938 }
1939 }
1940 }
1941
1942 void
1943 fs_visitor::assign_urb_setup()
1944 {
1945 int urb_start = c->prog_data.first_curbe_grf + c->prog_data.curb_read_length;
1946 int interp_reg_nr[FRAG_ATTRIB_MAX];
1947
1948 c->prog_data.urb_read_length = 0;
1949
1950 /* Figure out where each of the incoming setup attributes lands. */
1951 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
1952 interp_reg_nr[i] = -1;
1953
1954 if (i != FRAG_ATTRIB_WPOS &&
1955 !(brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(i)))
1956 continue;
1957
1958 /* Each attribute is 4 setup channels, each of which is half a reg. */
1959 interp_reg_nr[i] = urb_start + c->prog_data.urb_read_length;
1960 c->prog_data.urb_read_length += 2;
1961 }
1962
1963 /* Map the register numbers for FS_OPCODE_LINTERP so that it uses
1964 * the correct setup input.
1965 */
1966 foreach_iter(exec_list_iterator, iter, this->instructions) {
1967 fs_inst *inst = (fs_inst *)iter.get();
1968
1969 if (inst->opcode != FS_OPCODE_LINTERP)
1970 continue;
1971
1972 assert(inst->src[2].file == FIXED_HW_REG);
1973
1974 int location = inst->src[2].fixed_hw_reg.nr / 2;
1975 assert(interp_reg_nr[location] != -1);
1976 inst->src[2].fixed_hw_reg.nr = (interp_reg_nr[location] +
1977 (inst->src[2].fixed_hw_reg.nr & 1));
1978 }
1979
1980 this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length;
1981 }
1982
1983 void
1984 fs_visitor::assign_regs()
1985 {
1986 int header_size = this->first_non_payload_grf;
1987 int last_grf = 0;
1988
1989 /* FINISHME: trivial assignment of register numbers */
1990 foreach_iter(exec_list_iterator, iter, this->instructions) {
1991 fs_inst *inst = (fs_inst *)iter.get();
1992
1993 trivial_assign_reg(header_size, &inst->dst);
1994 trivial_assign_reg(header_size, &inst->src[0]);
1995 trivial_assign_reg(header_size, &inst->src[1]);
1996
1997 last_grf = MAX2(last_grf, inst->dst.hw_reg);
1998 last_grf = MAX2(last_grf, inst->src[0].hw_reg);
1999 last_grf = MAX2(last_grf, inst->src[1].hw_reg);
2000 }
2001
2002 this->grf_used = last_grf + 1;
2003 }
2004
2005 static struct brw_reg brw_reg_from_fs_reg(fs_reg *reg)
2006 {
2007 struct brw_reg brw_reg;
2008
2009 switch (reg->file) {
2010 case GRF:
2011 case ARF:
2012 case MRF:
2013 brw_reg = brw_vec8_reg(reg->file,
2014 reg->hw_reg, 0);
2015 brw_reg = retype(brw_reg, reg->type);
2016 break;
2017 case IMM:
2018 switch (reg->type) {
2019 case BRW_REGISTER_TYPE_F:
2020 brw_reg = brw_imm_f(reg->imm.f);
2021 break;
2022 case BRW_REGISTER_TYPE_D:
2023 brw_reg = brw_imm_d(reg->imm.i);
2024 break;
2025 case BRW_REGISTER_TYPE_UD:
2026 brw_reg = brw_imm_ud(reg->imm.u);
2027 break;
2028 default:
2029 assert(!"not reached");
2030 break;
2031 }
2032 break;
2033 case FIXED_HW_REG:
2034 brw_reg = reg->fixed_hw_reg;
2035 break;
2036 case BAD_FILE:
2037 /* Probably unused. */
2038 brw_reg = brw_null_reg();
2039 break;
2040 case UNIFORM:
2041 assert(!"not reached");
2042 brw_reg = brw_null_reg();
2043 break;
2044 }
2045 if (reg->abs)
2046 brw_reg = brw_abs(brw_reg);
2047 if (reg->negate)
2048 brw_reg = negate(brw_reg);
2049
2050 return brw_reg;
2051 }
2052
2053 void
2054 fs_visitor::generate_code()
2055 {
2056 unsigned int annotation_len = 0;
2057 int last_native_inst = 0;
2058 struct brw_instruction *if_stack[16], *loop_stack[16];
2059 int if_stack_depth = 0, loop_stack_depth = 0;
2060 int if_depth_in_loop[16];
2061
2062 if_depth_in_loop[loop_stack_depth] = 0;
2063
2064 memset(&if_stack, 0, sizeof(if_stack));
2065 foreach_iter(exec_list_iterator, iter, this->instructions) {
2066 fs_inst *inst = (fs_inst *)iter.get();
2067 struct brw_reg src[3], dst;
2068
2069 for (unsigned int i = 0; i < 3; i++) {
2070 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
2071 }
2072 dst = brw_reg_from_fs_reg(&inst->dst);
2073
2074 brw_set_conditionalmod(p, inst->conditional_mod);
2075 brw_set_predicate_control(p, inst->predicated);
2076
2077 switch (inst->opcode) {
2078 case BRW_OPCODE_MOV:
2079 brw_MOV(p, dst, src[0]);
2080 break;
2081 case BRW_OPCODE_ADD:
2082 brw_ADD(p, dst, src[0], src[1]);
2083 break;
2084 case BRW_OPCODE_MUL:
2085 brw_MUL(p, dst, src[0], src[1]);
2086 break;
2087
2088 case BRW_OPCODE_FRC:
2089 brw_FRC(p, dst, src[0]);
2090 break;
2091 case BRW_OPCODE_RNDD:
2092 brw_RNDD(p, dst, src[0]);
2093 break;
2094 case BRW_OPCODE_RNDZ:
2095 brw_RNDZ(p, dst, src[0]);
2096 break;
2097
2098 case BRW_OPCODE_AND:
2099 brw_AND(p, dst, src[0], src[1]);
2100 break;
2101 case BRW_OPCODE_OR:
2102 brw_OR(p, dst, src[0], src[1]);
2103 break;
2104 case BRW_OPCODE_XOR:
2105 brw_XOR(p, dst, src[0], src[1]);
2106 break;
2107
2108 case BRW_OPCODE_CMP:
2109 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
2110 break;
2111 case BRW_OPCODE_SEL:
2112 brw_SEL(p, dst, src[0], src[1]);
2113 break;
2114
2115 case BRW_OPCODE_IF:
2116 assert(if_stack_depth < 16);
2117 if_stack[if_stack_depth] = brw_IF(p, BRW_EXECUTE_8);
2118 if_depth_in_loop[loop_stack_depth]++;
2119 if_stack_depth++;
2120 break;
2121 case BRW_OPCODE_ELSE:
2122 if_stack[if_stack_depth - 1] =
2123 brw_ELSE(p, if_stack[if_stack_depth - 1]);
2124 break;
2125 case BRW_OPCODE_ENDIF:
2126 if_stack_depth--;
2127 brw_ENDIF(p , if_stack[if_stack_depth]);
2128 if_depth_in_loop[loop_stack_depth]--;
2129 break;
2130
2131 case BRW_OPCODE_DO:
2132 loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
2133 if_depth_in_loop[loop_stack_depth] = 0;
2134 break;
2135
2136 case BRW_OPCODE_BREAK:
2137 brw_BREAK(p, if_depth_in_loop[loop_stack_depth]);
2138 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
2139 break;
2140 case BRW_OPCODE_CONTINUE:
2141 brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
2142 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
2143 break;
2144
2145 case BRW_OPCODE_WHILE: {
2146 struct brw_instruction *inst0, *inst1;
2147 GLuint br = 1;
2148
2149 if (intel->gen == 5)
2150 br = 2;
2151
2152 assert(loop_stack_depth > 0);
2153 loop_stack_depth--;
2154 inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
2155 /* patch all the BREAK/CONT instructions from last BGNLOOP */
2156 while (inst0 > loop_stack[loop_stack_depth]) {
2157 inst0--;
2158 if (inst0->header.opcode == BRW_OPCODE_BREAK &&
2159 inst0->bits3.if_else.jump_count == 0) {
2160 inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
2161 }
2162 else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
2163 inst0->bits3.if_else.jump_count == 0) {
2164 inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
2165 }
2166 }
2167 }
2168 break;
2169
2170 case FS_OPCODE_RCP:
2171 case FS_OPCODE_RSQ:
2172 case FS_OPCODE_SQRT:
2173 case FS_OPCODE_EXP2:
2174 case FS_OPCODE_LOG2:
2175 case FS_OPCODE_POW:
2176 case FS_OPCODE_SIN:
2177 case FS_OPCODE_COS:
2178 generate_math(inst, dst, src);
2179 break;
2180 case FS_OPCODE_LINTERP:
2181 generate_linterp(inst, dst, src);
2182 break;
2183 case FS_OPCODE_TEX:
2184 case FS_OPCODE_TXB:
2185 case FS_OPCODE_TXL:
2186 generate_tex(inst, dst, src[0]);
2187 break;
2188 case FS_OPCODE_DISCARD:
2189 generate_discard(inst, dst /* src0 == dst */);
2190 break;
2191 case FS_OPCODE_DDX:
2192 generate_ddx(inst, dst, src[0]);
2193 break;
2194 case FS_OPCODE_DDY:
2195 generate_ddy(inst, dst, src[0]);
2196 break;
2197 case FS_OPCODE_FB_WRITE:
2198 generate_fb_write(inst);
2199 break;
2200 default:
2201 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
2202 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
2203 brw_opcodes[inst->opcode].name);
2204 } else {
2205 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
2206 }
2207 this->fail = true;
2208 }
2209
2210 if (annotation_len < p->nr_insn) {
2211 annotation_len *= 2;
2212 if (annotation_len < 16)
2213 annotation_len = 16;
2214
2215 this->annotation_string = talloc_realloc(this->mem_ctx,
2216 annotation_string,
2217 const char *,
2218 annotation_len);
2219 this->annotation_ir = talloc_realloc(this->mem_ctx,
2220 annotation_ir,
2221 ir_instruction *,
2222 annotation_len);
2223 }
2224
2225 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
2226 this->annotation_string[i] = inst->annotation;
2227 this->annotation_ir[i] = inst->ir;
2228 }
2229 last_native_inst = p->nr_insn;
2230 }
2231 }
2232
2233 GLboolean
2234 brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c)
2235 {
2236 struct brw_compile *p = &c->func;
2237 struct intel_context *intel = &brw->intel;
2238 GLcontext *ctx = &intel->ctx;
2239 struct brw_shader *shader = NULL;
2240 struct gl_shader_program *prog = ctx->Shader.CurrentProgram;
2241
2242 if (!prog)
2243 return GL_FALSE;
2244
2245 if (!using_new_fs)
2246 return GL_FALSE;
2247
2248 for (unsigned int i = 0; i < prog->_NumLinkedShaders; i++) {
2249 if (prog->_LinkedShaders[i]->Type == GL_FRAGMENT_SHADER) {
2250 shader = (struct brw_shader *)prog->_LinkedShaders[i];
2251 break;
2252 }
2253 }
2254 if (!shader)
2255 return GL_FALSE;
2256
2257 /* We always use 8-wide mode, at least for now. For one, flow
2258 * control only works in 8-wide. Also, when we're fragment shader
2259 * bound, we're almost always under register pressure as well, so
2260 * 8-wide would save us from the performance cliff of spilling
2261 * regs.
2262 */
2263 c->dispatch_width = 8;
2264
2265 if (INTEL_DEBUG & DEBUG_WM) {
2266 printf("GLSL IR for native fragment shader %d:\n", prog->Name);
2267 _mesa_print_ir(shader->ir, NULL);
2268 printf("\n");
2269 }
2270
2271 /* Now the main event: Visit the shader IR and generate our FS IR for it.
2272 */
2273 fs_visitor v(c, shader);
2274
2275 if (0) {
2276 v.emit_dummy_fs();
2277 } else {
2278 v.emit_interpolation_setup();
2279
2280 /* Generate FS IR for main(). (the visitor only descends into
2281 * functions called "main").
2282 */
2283 foreach_iter(exec_list_iterator, iter, *shader->ir) {
2284 ir_instruction *ir = (ir_instruction *)iter.get();
2285 v.base_ir = ir;
2286 ir->accept(&v);
2287 }
2288
2289 v.emit_fb_writes();
2290 v.assign_curb_setup();
2291 v.assign_urb_setup();
2292 v.assign_regs();
2293 }
2294
2295 v.generate_code();
2296
2297 assert(!v.fail); /* FINISHME: Cleanly fail, tested at link time, etc. */
2298
2299 if (v.fail)
2300 return GL_FALSE;
2301
2302 if (INTEL_DEBUG & DEBUG_WM) {
2303 const char *last_annotation_string = NULL;
2304 ir_instruction *last_annotation_ir = NULL;
2305
2306 printf("Native code for fragment shader %d:\n", prog->Name);
2307 for (unsigned int i = 0; i < p->nr_insn; i++) {
2308 if (last_annotation_ir != v.annotation_ir[i]) {
2309 last_annotation_ir = v.annotation_ir[i];
2310 if (last_annotation_ir) {
2311 printf(" ");
2312 last_annotation_ir->print();
2313 printf("\n");
2314 }
2315 }
2316 if (last_annotation_string != v.annotation_string[i]) {
2317 last_annotation_string = v.annotation_string[i];
2318 if (last_annotation_string)
2319 printf(" %s\n", last_annotation_string);
2320 }
2321 brw_disasm(stdout, &p->store[i], intel->gen);
2322 }
2323 printf("\n");
2324 }
2325
2326 c->prog_data.total_grf = v.grf_used;
2327 c->prog_data.total_scratch = 0;
2328
2329 return GL_TRUE;
2330 }