2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "brw_dead_control_flow.h"
47 #include "main/uniforms.h"
48 #include "brw_fs_live_variables.h"
49 #include "glsl/glsl_types.h"
50 #include "program/sampler.h"
55 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
56 const fs_reg
*src
, unsigned sources
)
58 memset(this, 0, sizeof(*this));
60 this->src
= new fs_reg
[MAX2(sources
, 3)];
61 for (unsigned i
= 0; i
< sources
; i
++)
62 this->src
[i
] = src
[i
];
64 this->opcode
= opcode
;
66 this->sources
= sources
;
67 this->exec_size
= exec_size
;
69 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
71 /* If exec_size == 0, try to guess it from the registers. Since all
72 * manner of things may use hardware registers, we first try to guess
73 * based on GRF registers. If this fails, we will go ahead and take the
74 * width from the destination register.
76 if (this->exec_size
== 0) {
77 if (dst
.file
== GRF
) {
78 this->exec_size
= dst
.width
;
80 for (unsigned i
= 0; i
< sources
; ++i
) {
81 if (src
[i
].file
!= GRF
&& src
[i
].file
!= ATTR
)
84 if (this->exec_size
<= 1)
85 this->exec_size
= src
[i
].width
;
86 assert(src
[i
].width
== 1 || src
[i
].width
== this->exec_size
);
90 if (this->exec_size
== 0 && dst
.file
!= BAD_FILE
)
91 this->exec_size
= dst
.width
;
93 assert(this->exec_size
!= 0);
95 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
97 /* This will be the case for almost all instructions. */
104 DIV_ROUND_UP(MAX2(dst
.width
* dst
.stride
, 1) * type_sz(dst
.type
), 32);
107 this->regs_written
= 0;
111 unreachable("Invalid destination register file");
113 unreachable("Invalid register file");
116 this->writes_accumulator
= false;
121 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
124 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
126 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
129 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
)
131 init(opcode
, 0, dst
, NULL
, 0);
134 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
137 const fs_reg src
[1] = { src0
};
138 init(opcode
, exec_size
, dst
, src
, 1);
141 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
)
143 const fs_reg src
[1] = { src0
};
144 init(opcode
, 0, dst
, src
, 1);
147 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
148 const fs_reg
&src0
, const fs_reg
&src1
)
150 const fs_reg src
[2] = { src0
, src1
};
151 init(opcode
, exec_size
, dst
, src
, 2);
154 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
157 const fs_reg src
[2] = { src0
, src1
};
158 init(opcode
, 0, dst
, src
, 2);
161 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
162 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
164 const fs_reg src
[3] = { src0
, src1
, src2
};
165 init(opcode
, exec_size
, dst
, src
, 3);
168 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
169 const fs_reg
&src1
, const fs_reg
&src2
)
171 const fs_reg src
[3] = { src0
, src1
, src2
};
172 init(opcode
, 0, dst
, src
, 3);
175 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
,
176 const fs_reg src
[], unsigned sources
)
178 init(opcode
, 0, dst
, src
, sources
);
181 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
182 const fs_reg src
[], unsigned sources
)
184 init(opcode
, exec_width
, dst
, src
, sources
);
187 fs_inst::fs_inst(const fs_inst
&that
)
189 memcpy(this, &that
, sizeof(that
));
191 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
193 for (unsigned i
= 0; i
< that
.sources
; i
++)
194 this->src
[i
] = that
.src
[i
];
203 fs_inst::resize_sources(uint8_t num_sources
)
205 if (this->sources
!= num_sources
) {
206 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
208 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
209 src
[i
] = this->src
[i
];
213 this->sources
= num_sources
;
218 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
220 const fs_reg
&surf_index
,
221 const fs_reg
&varying_offset
,
222 uint32_t const_offset
)
224 /* We have our constant surface use a pitch of 4 bytes, so our index can
225 * be any component of a vector, and then we load 4 contiguous
226 * components starting from that.
228 * We break down the const_offset to a portion added to the variable
229 * offset and a portion done using reg_offset, which means that if you
230 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
231 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
232 * CSE can later notice that those loads are all the same and eliminate
233 * the redundant ones.
235 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
236 bld
.ADD(vec4_offset
, varying_offset
, fs_reg(const_offset
& ~3));
239 if (devinfo
->gen
== 4 && dst
.width
== 8) {
240 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
241 * u, v, r) as parameters, or we can just use the SIMD16 message
242 * consisting of (header, u). We choose the second, at the cost of a
243 * longer return length.
249 if (devinfo
->gen
>= 7)
250 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
252 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
254 assert(dst
.width
% 8 == 0);
255 int regs_written
= 4 * (dst
.width
/ 8) * scale
;
256 fs_reg vec4_result
= fs_reg(GRF
, alloc
.allocate(regs_written
),
257 dst
.type
, dst
.width
);
258 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
259 inst
->regs_written
= regs_written
;
261 if (devinfo
->gen
< 7) {
263 inst
->header_size
= 1;
264 if (devinfo
->gen
== 4)
267 inst
->mlen
= 1 + dispatch_width
/ 8;
270 bld
.MOV(dst
, offset(vec4_result
, (const_offset
& 3) * scale
));
274 * A helper for MOV generation for fixing up broken hardware SEND dependency
278 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
280 /* The caller always wants uncompressed to emit the minimal extra
281 * dependencies, and to avoid having to deal with aligning its regs to 2.
283 const fs_builder ubld
= bld
.annotate("send dependency resolve")
286 ubld
.MOV(ubld
.null_reg_f(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
290 fs_inst::equals(fs_inst
*inst
) const
292 return (opcode
== inst
->opcode
&&
293 dst
.equals(inst
->dst
) &&
294 src
[0].equals(inst
->src
[0]) &&
295 src
[1].equals(inst
->src
[1]) &&
296 src
[2].equals(inst
->src
[2]) &&
297 saturate
== inst
->saturate
&&
298 predicate
== inst
->predicate
&&
299 conditional_mod
== inst
->conditional_mod
&&
300 mlen
== inst
->mlen
&&
301 base_mrf
== inst
->base_mrf
&&
302 target
== inst
->target
&&
304 header_size
== inst
->header_size
&&
305 shadow_compare
== inst
->shadow_compare
&&
306 exec_size
== inst
->exec_size
&&
307 offset
== inst
->offset
);
311 fs_inst::overwrites_reg(const fs_reg
®
) const
313 return reg
.in_range(dst
, regs_written
);
317 fs_inst::is_send_from_grf() const
320 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
321 case SHADER_OPCODE_SHADER_TIME_ADD
:
322 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
323 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
324 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
325 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
326 case SHADER_OPCODE_UNTYPED_ATOMIC
:
327 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
328 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
329 case SHADER_OPCODE_TYPED_ATOMIC
:
330 case SHADER_OPCODE_TYPED_SURFACE_READ
:
331 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
332 case SHADER_OPCODE_URB_WRITE_SIMD8
:
334 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
335 return src
[1].file
== GRF
;
336 case FS_OPCODE_FB_WRITE
:
337 return src
[0].file
== GRF
;
340 return src
[0].file
== GRF
;
347 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
349 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
352 fs_reg reg
= this->src
[0];
353 if (reg
.file
!= GRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
356 if (grf_alloc
.sizes
[reg
.reg
] != this->regs_written
)
359 for (int i
= 0; i
< this->sources
; i
++) {
360 reg
.type
= this->src
[i
].type
;
361 reg
.width
= this->src
[i
].width
;
362 if (!this->src
[i
].equals(reg
))
364 reg
= ::offset(reg
, 1);
371 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
373 if (devinfo
->gen
== 6 && is_math())
376 if (is_send_from_grf())
379 if (!backend_instruction::can_do_source_mods())
386 fs_inst::has_side_effects() const
388 return this->eot
|| backend_instruction::has_side_effects();
394 memset(this, 0, sizeof(*this));
398 /** Generic unset register constructor. */
402 this->file
= BAD_FILE
;
405 /** Immediate value constructor. */
406 fs_reg::fs_reg(float f
)
410 this->type
= BRW_REGISTER_TYPE_F
;
411 this->fixed_hw_reg
.dw1
.f
= f
;
415 /** Immediate value constructor. */
416 fs_reg::fs_reg(int32_t i
)
420 this->type
= BRW_REGISTER_TYPE_D
;
421 this->fixed_hw_reg
.dw1
.d
= i
;
425 /** Immediate value constructor. */
426 fs_reg::fs_reg(uint32_t u
)
430 this->type
= BRW_REGISTER_TYPE_UD
;
431 this->fixed_hw_reg
.dw1
.ud
= u
;
435 /** Vector float immediate value constructor. */
436 fs_reg::fs_reg(uint8_t vf
[4])
440 this->type
= BRW_REGISTER_TYPE_VF
;
441 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
444 /** Vector float immediate value constructor. */
445 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
449 this->type
= BRW_REGISTER_TYPE_VF
;
450 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
456 /** Fixed brw_reg. */
457 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
461 this->fixed_hw_reg
= fixed_hw_reg
;
462 this->type
= fixed_hw_reg
.type
;
463 this->width
= 1 << fixed_hw_reg
.width
;
467 fs_reg::equals(const fs_reg
&r
) const
469 return (file
== r
.file
&&
471 reg_offset
== r
.reg_offset
&&
472 subreg_offset
== r
.subreg_offset
&&
474 negate
== r
.negate
&&
476 !reladdr
&& !r
.reladdr
&&
477 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
, sizeof(fixed_hw_reg
)) == 0 &&
483 fs_reg::set_smear(unsigned subreg
)
485 assert(file
!= HW_REG
&& file
!= IMM
);
486 subreg_offset
= subreg
* type_sz(type
);
492 fs_reg::is_contiguous() const
498 fs_visitor::type_size(const struct glsl_type
*type
)
500 unsigned int size
, i
;
502 switch (type
->base_type
) {
505 case GLSL_TYPE_FLOAT
:
507 return type
->components();
508 case GLSL_TYPE_ARRAY
:
509 return type_size(type
->fields
.array
) * type
->length
;
510 case GLSL_TYPE_STRUCT
:
512 for (i
= 0; i
< type
->length
; i
++) {
513 size
+= type_size(type
->fields
.structure
[i
].type
);
516 case GLSL_TYPE_SAMPLER
:
517 /* Samplers take up no register space, since they're baked in at
521 case GLSL_TYPE_ATOMIC_UINT
:
523 case GLSL_TYPE_IMAGE
:
525 case GLSL_TYPE_ERROR
:
526 case GLSL_TYPE_INTERFACE
:
527 case GLSL_TYPE_DOUBLE
:
528 unreachable("not reached");
535 * Create a MOV to read the timestamp register.
537 * The caller is responsible for emitting the MOV. The return value is
538 * the destination of the MOV, with extra parameters set.
541 fs_visitor::get_timestamp(const fs_builder
&bld
)
543 assert(devinfo
->gen
>= 7);
545 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
548 BRW_REGISTER_TYPE_UD
));
550 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
, 4);
552 /* We want to read the 3 fields we care about even if it's not enabled in
555 bld
.exec_all().MOV(dst
, ts
);
557 /* The caller wants the low 32 bits of the timestamp. Since it's running
558 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
559 * which is plenty of time for our purposes. It is identical across the
560 * EUs, but since it's tracking GPU core speed it will increment at a
561 * varying rate as render P-states change.
563 * The caller could also check if render P-states have changed (or anything
564 * else that might disrupt timing) by setting smear to 2 and checking if
565 * that field is != 0.
573 fs_visitor::emit_shader_time_begin()
575 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
579 fs_visitor::emit_shader_time_end()
581 /* Insert our code just before the final SEND with EOT. */
582 exec_node
*end
= this->instructions
.get_tail();
583 assert(end
&& ((fs_inst
*) end
)->eot
);
584 const fs_builder ibld
= bld
.annotate("shader time end")
585 .exec_all().at(NULL
, end
);
587 fs_reg shader_end_time
= get_timestamp(ibld
);
589 /* Check that there weren't any timestamp reset events (assuming these
590 * were the only two timestamp reads that happened).
592 fs_reg reset
= shader_end_time
;
594 set_condmod(BRW_CONDITIONAL_Z
,
595 ibld
.AND(ibld
.null_reg_ud(), reset
, fs_reg(1u)));
596 ibld
.IF(BRW_PREDICATE_NORMAL
);
598 fs_reg start
= shader_start_time
;
600 fs_reg diff
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
, 1);
602 ibld
.ADD(diff
, start
, shader_end_time
);
604 /* If there were no instructions between the two timestamp gets, the diff
605 * is 2 cycles. Remove that overhead, so I can forget about that when
606 * trying to determine the time taken for single instructions.
608 ibld
.ADD(diff
, diff
, fs_reg(-2u));
609 SHADER_TIME_ADD(ibld
, 0, diff
);
610 SHADER_TIME_ADD(ibld
, 1, fs_reg(1u));
611 ibld
.emit(BRW_OPCODE_ELSE
);
612 SHADER_TIME_ADD(ibld
, 2, fs_reg(1u));
613 ibld
.emit(BRW_OPCODE_ENDIF
);
617 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
618 int shader_time_subindex
,
621 int index
= shader_time_index
* 3 + shader_time_subindex
;
622 fs_reg offset
= fs_reg(index
* SHADER_TIME_STRIDE
);
625 if (dispatch_width
== 8)
626 payload
= vgrf(glsl_type::uvec2_type
);
628 payload
= vgrf(glsl_type::uint_type
);
630 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
634 fs_visitor::vfail(const char *format
, va_list va
)
643 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
644 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
646 this->fail_msg
= msg
;
649 fprintf(stderr
, "%s", msg
);
654 fs_visitor::fail(const char *format
, ...)
658 va_start(va
, format
);
664 * Mark this program as impossible to compile in SIMD16 mode.
666 * During the SIMD8 compile (which happens first), we can detect and flag
667 * things that are unsupported in SIMD16 mode, so the compiler can skip
668 * the SIMD16 compile altogether.
670 * During a SIMD16 compile (if one happens anyway), this just calls fail().
673 fs_visitor::no16(const char *msg
)
675 if (dispatch_width
== 16) {
678 simd16_unsupported
= true;
680 compiler
->shader_perf_log(log_data
,
681 "SIMD16 shader failed to compile: %s", msg
);
686 * Returns true if the instruction has a flag that means it won't
687 * update an entire destination register.
689 * For example, dead code elimination and live variable analysis want to know
690 * when a write to a variable screens off any preceding values that were in
694 fs_inst::is_partial_write() const
696 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
697 (this->dst
.width
* type_sz(this->dst
.type
)) < 32 ||
698 !this->dst
.is_contiguous());
702 fs_inst::regs_read(int arg
) const
704 unsigned components
= 1;
706 case FS_OPCODE_FB_WRITE
:
707 case SHADER_OPCODE_URB_WRITE_SIMD8
:
708 case SHADER_OPCODE_UNTYPED_ATOMIC
:
709 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
710 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
711 case SHADER_OPCODE_TYPED_ATOMIC
:
712 case SHADER_OPCODE_TYPED_SURFACE_READ
:
713 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
714 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
719 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
720 /* The payload is actually stored in src1 */
725 case FS_OPCODE_LINTERP
:
727 return exec_size
/ 4;
730 case FS_OPCODE_PIXEL_X
:
731 case FS_OPCODE_PIXEL_Y
:
737 if (is_tex() && arg
== 0 && src
[0].file
== GRF
)
742 switch (src
[arg
].file
) {
749 if (src
[arg
].stride
== 0) {
752 int size
= components
* src
[arg
].width
* type_sz(src
[arg
].type
);
753 return DIV_ROUND_UP(size
* src
[arg
].stride
, 32);
756 unreachable("MRF registers are not allowed as sources");
758 unreachable("Invalid register file");
763 fs_inst::reads_flag() const
769 fs_inst::writes_flag() const
771 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
772 opcode
!= BRW_OPCODE_IF
&&
773 opcode
!= BRW_OPCODE_WHILE
)) ||
774 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
778 * Returns how many MRFs an FS opcode will write over.
780 * Note that this is not the 0 or 1 implied writes in an actual gen
781 * instruction -- the FS opcodes often generate MOVs in addition.
784 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
789 if (inst
->base_mrf
== -1)
792 switch (inst
->opcode
) {
793 case SHADER_OPCODE_RCP
:
794 case SHADER_OPCODE_RSQ
:
795 case SHADER_OPCODE_SQRT
:
796 case SHADER_OPCODE_EXP2
:
797 case SHADER_OPCODE_LOG2
:
798 case SHADER_OPCODE_SIN
:
799 case SHADER_OPCODE_COS
:
800 return 1 * dispatch_width
/ 8;
801 case SHADER_OPCODE_POW
:
802 case SHADER_OPCODE_INT_QUOTIENT
:
803 case SHADER_OPCODE_INT_REMAINDER
:
804 return 2 * dispatch_width
/ 8;
805 case SHADER_OPCODE_TEX
:
807 case SHADER_OPCODE_TXD
:
808 case SHADER_OPCODE_TXF
:
809 case SHADER_OPCODE_TXF_CMS
:
810 case SHADER_OPCODE_TXF_MCS
:
811 case SHADER_OPCODE_TG4
:
812 case SHADER_OPCODE_TG4_OFFSET
:
813 case SHADER_OPCODE_TXL
:
814 case SHADER_OPCODE_TXS
:
815 case SHADER_OPCODE_LOD
:
817 case FS_OPCODE_FB_WRITE
:
819 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
820 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
822 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
824 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
826 case SHADER_OPCODE_UNTYPED_ATOMIC
:
827 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
828 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
829 case SHADER_OPCODE_TYPED_ATOMIC
:
830 case SHADER_OPCODE_TYPED_SURFACE_READ
:
831 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
832 case SHADER_OPCODE_URB_WRITE_SIMD8
:
833 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
834 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
835 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
836 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
839 unreachable("not reached");
844 fs_visitor::vgrf(const glsl_type
*const type
)
846 int reg_width
= dispatch_width
/ 8;
847 return fs_reg(GRF
, alloc
.allocate(type_size(type
) * reg_width
),
848 brw_type_for_base_type(type
), dispatch_width
);
851 /** Fixed HW reg constructor. */
852 fs_reg::fs_reg(enum register_file file
, int reg
)
857 this->type
= BRW_REGISTER_TYPE_F
;
868 /** Fixed HW reg constructor. */
869 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
)
885 /** Fixed HW reg constructor. */
886 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
,
896 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
897 * This brings in those uniform definitions
900 fs_visitor::import_uniforms(fs_visitor
*v
)
902 this->push_constant_loc
= v
->push_constant_loc
;
903 this->pull_constant_loc
= v
->pull_constant_loc
;
904 this->uniforms
= v
->uniforms
;
905 this->param_size
= v
->param_size
;
909 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
910 bool origin_upper_left
)
912 assert(stage
== MESA_SHADER_FRAGMENT
);
913 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
914 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
916 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
919 if (pixel_center_integer
) {
920 bld
.MOV(wpos
, this->pixel_x
);
922 bld
.ADD(wpos
, this->pixel_x
, fs_reg(0.5f
));
924 wpos
= offset(wpos
, 1);
927 if (!flip
&& pixel_center_integer
) {
928 bld
.MOV(wpos
, this->pixel_y
);
930 fs_reg pixel_y
= this->pixel_y
;
931 float offset
= (pixel_center_integer
? 0.0 : 0.5);
934 pixel_y
.negate
= true;
935 offset
+= key
->drawable_height
- 1.0;
938 bld
.ADD(wpos
, pixel_y
, fs_reg(offset
));
940 wpos
= offset(wpos
, 1);
943 if (devinfo
->gen
>= 6) {
944 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
946 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
947 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
948 interp_reg(VARYING_SLOT_POS
, 2));
950 wpos
= offset(wpos
, 1);
952 /* gl_FragCoord.w: Already set up in emit_interpolation */
953 bld
.MOV(wpos
, this->wpos_w
);
959 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
960 glsl_interp_qualifier interpolation_mode
,
961 bool is_centroid
, bool is_sample
)
963 brw_wm_barycentric_interp_mode barycoord_mode
;
964 if (devinfo
->gen
>= 6) {
966 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
967 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
969 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
970 } else if (is_sample
) {
971 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
972 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
974 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
976 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
977 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
979 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
982 /* On Ironlake and below, there is only one interpolation mode.
983 * Centroid interpolation doesn't mean anything on this hardware --
984 * there is no multisampling.
986 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
988 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
989 this->delta_xy
[barycoord_mode
], interp
);
993 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
994 const glsl_type
*type
,
995 glsl_interp_qualifier interpolation_mode
,
996 int location
, bool mod_centroid
,
999 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1001 assert(stage
== MESA_SHADER_FRAGMENT
);
1002 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1003 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1005 unsigned int array_elements
;
1007 if (type
->is_array()) {
1008 array_elements
= type
->length
;
1009 if (array_elements
== 0) {
1010 fail("dereferenced array '%s' has length 0\n", name
);
1012 type
= type
->fields
.array
;
1017 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1019 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1020 if (key
->flat_shade
&& is_gl_Color
) {
1021 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1023 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1027 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1028 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1029 if (prog_data
->urb_setup
[location
] == -1) {
1030 /* If there's no incoming setup data for this slot, don't
1031 * emit interpolation for it.
1033 attr
= offset(attr
, type
->vector_elements
);
1038 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1039 /* Constant interpolation (flat shading) case. The SF has
1040 * handed us defined values in only the constant offset
1041 * field of the setup reg.
1043 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1044 struct brw_reg interp
= interp_reg(location
, k
);
1045 interp
= suboffset(interp
, 3);
1046 interp
.type
= attr
.type
;
1047 bld
.emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1048 attr
= offset(attr
, 1);
1051 /* Smooth/noperspective interpolation case. */
1052 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1053 struct brw_reg interp
= interp_reg(location
, k
);
1054 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1055 /* Get the pixel/sample mask into f0 so that we know
1056 * which pixels are lit. Then, for each channel that is
1057 * unlit, replace the centroid data with non-centroid
1060 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1063 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1065 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1066 inst
->predicate_inverse
= true;
1067 if (devinfo
->has_pln
)
1068 inst
->no_dd_clear
= true;
1070 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1071 mod_centroid
&& !key
->persample_shading
,
1072 mod_sample
|| key
->persample_shading
);
1073 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1074 inst
->predicate_inverse
= false;
1075 if (devinfo
->has_pln
)
1076 inst
->no_dd_check
= true;
1079 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1080 mod_centroid
&& !key
->persample_shading
,
1081 mod_sample
|| key
->persample_shading
);
1083 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1084 bld
.MUL(attr
, attr
, this->pixel_w
);
1086 attr
= offset(attr
, 1);
1096 fs_visitor::emit_frontfacing_interpolation()
1098 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1100 if (devinfo
->gen
>= 6) {
1101 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1102 * a boolean result from this (~0/true or 0/false).
1104 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1105 * this task in only one instruction:
1106 * - a negation source modifier will flip the bit; and
1107 * - a W -> D type conversion will sign extend the bit into the high
1108 * word of the destination.
1110 * An ASR 15 fills the low word of the destination.
1112 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1115 bld
.ASR(*reg
, g0
, fs_reg(15));
1117 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1118 * a boolean result from this (1/true or 0/false).
1120 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1121 * the negation source modifier to flip it. Unfortunately the SHR
1122 * instruction only operates on UD (or D with an abs source modifier)
1123 * sources without negation.
1125 * Instead, use ASR (which will give ~0/true or 0/false).
1127 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1130 bld
.ASR(*reg
, g1_6
, fs_reg(31));
1137 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1139 assert(stage
== MESA_SHADER_FRAGMENT
);
1140 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1141 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1143 if (key
->compute_pos_offset
) {
1144 /* Convert int_sample_pos to floating point */
1145 bld
.MOV(dst
, int_sample_pos
);
1146 /* Scale to the range [0, 1] */
1147 bld
.MUL(dst
, dst
, fs_reg(1 / 16.0f
));
1150 /* From ARB_sample_shading specification:
1151 * "When rendering to a non-multisample buffer, or if multisample
1152 * rasterization is disabled, gl_SamplePosition will always be
1155 bld
.MOV(dst
, fs_reg(0.5f
));
1160 fs_visitor::emit_samplepos_setup()
1162 assert(devinfo
->gen
>= 6);
1164 const fs_builder abld
= bld
.annotate("compute sample position");
1165 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1167 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1168 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1170 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1171 * mode will be enabled.
1173 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1174 * R31.1:0 Position Offset X/Y for Slot[3:0]
1175 * R31.3:2 Position Offset X/Y for Slot[7:4]
1178 * The X, Y sample positions come in as bytes in thread payload. So, read
1179 * the positions using vstride=16, width=8, hstride=2.
1181 struct brw_reg sample_pos_reg
=
1182 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1183 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1185 if (dispatch_width
== 8) {
1186 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1188 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1189 abld
.half(1).MOV(half(int_sample_x
, 1),
1190 fs_reg(suboffset(sample_pos_reg
, 16)));
1192 /* Compute gl_SamplePosition.x */
1193 compute_sample_position(pos
, int_sample_x
);
1194 pos
= offset(pos
, 1);
1195 if (dispatch_width
== 8) {
1196 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1198 abld
.half(0).MOV(half(int_sample_y
, 0),
1199 fs_reg(suboffset(sample_pos_reg
, 1)));
1200 abld
.half(1).MOV(half(int_sample_y
, 1),
1201 fs_reg(suboffset(sample_pos_reg
, 17)));
1203 /* Compute gl_SamplePosition.y */
1204 compute_sample_position(pos
, int_sample_y
);
1209 fs_visitor::emit_sampleid_setup()
1211 assert(stage
== MESA_SHADER_FRAGMENT
);
1212 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1213 assert(devinfo
->gen
>= 6);
1215 const fs_builder abld
= bld
.annotate("compute sample id");
1216 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1218 if (key
->compute_sample_id
) {
1219 fs_reg t1
= vgrf(glsl_type::int_type
);
1220 fs_reg t2
= vgrf(glsl_type::int_type
);
1221 t2
.type
= BRW_REGISTER_TYPE_UW
;
1223 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1224 * 8x multisampling, subspan 0 will represent sample N (where N
1225 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1226 * 7. We can find the value of N by looking at R0.0 bits 7:6
1227 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1228 * (since samples are always delivered in pairs). That is, we
1229 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1230 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1231 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1232 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1233 * populating a temporary variable with the sequence (0, 1, 2, 3),
1234 * and then reading from it using vstride=1, width=4, hstride=0.
1235 * These computations hold good for 4x multisampling as well.
1237 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1238 * the first four slots are sample 0 of subspan 0; the next four
1239 * are sample 1 of subspan 0; the third group is sample 0 of
1240 * subspan 1, and finally sample 1 of subspan 1.
1243 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1245 abld
.exec_all().SHR(t1
, t1
, fs_reg(5));
1247 /* This works for both SIMD8 and SIMD16 */
1249 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1251 /* This special instruction takes care of setting vstride=1,
1252 * width=4, hstride=0 of t2 during an ADD instruction.
1254 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1256 /* As per GL_ARB_sample_shading specification:
1257 * "When rendering to a non-multisample buffer, or if multisample
1258 * rasterization is disabled, gl_SampleID will always be zero."
1260 abld
.MOV(*reg
, fs_reg(0));
1267 fs_visitor::resolve_source_modifiers(fs_reg
*src
)
1269 if (!src
->abs
&& !src
->negate
)
1272 fs_reg temp
= bld
.vgrf(src
->type
);
1273 bld
.MOV(temp
, *src
);
1278 fs_visitor::emit_discard_jump()
1280 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1282 /* For performance, after a discard, jump to the end of the
1283 * shader if all relevant channels have been discarded.
1285 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1286 discard_jump
->flag_subreg
= 1;
1288 discard_jump
->predicate
= (dispatch_width
== 8)
1289 ? BRW_PREDICATE_ALIGN1_ANY8H
1290 : BRW_PREDICATE_ALIGN1_ANY16H
;
1291 discard_jump
->predicate_inverse
= true;
1295 fs_visitor::assign_curb_setup()
1297 if (dispatch_width
== 8) {
1298 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1300 if (stage
== MESA_SHADER_FRAGMENT
) {
1301 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1302 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1303 } else if (stage
== MESA_SHADER_COMPUTE
) {
1304 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1305 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1307 unreachable("Unsupported shader type!");
1311 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1313 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1314 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1315 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1316 if (inst
->src
[i
].file
== UNIFORM
) {
1317 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1319 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1320 constant_nr
= push_constant_loc
[uniform_nr
];
1322 /* Section 5.11 of the OpenGL 4.1 spec says:
1323 * "Out-of-bounds reads return undefined values, which include
1324 * values from other variables of the active program or zero."
1325 * Just return the first push constant.
1330 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1334 inst
->src
[i
].file
= HW_REG
;
1335 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1336 retype(brw_reg
, inst
->src
[i
].type
),
1337 inst
->src
[i
].subreg_offset
);
1344 fs_visitor::calculate_urb_setup()
1346 assert(stage
== MESA_SHADER_FRAGMENT
);
1347 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1348 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1350 memset(prog_data
->urb_setup
, -1,
1351 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1354 /* Figure out where each of the incoming setup attributes lands. */
1355 if (devinfo
->gen
>= 6) {
1356 if (_mesa_bitcount_64(prog
->InputsRead
&
1357 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1358 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1359 * first 16 varying inputs, so we can put them wherever we want.
1360 * Just put them in order.
1362 * This is useful because it means that (a) inputs not used by the
1363 * fragment shader won't take up valuable register space, and (b) we
1364 * won't have to recompile the fragment shader if it gets paired with
1365 * a different vertex (or geometry) shader.
1367 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1368 if (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1369 BITFIELD64_BIT(i
)) {
1370 prog_data
->urb_setup
[i
] = urb_next
++;
1374 /* We have enough input varyings that the SF/SBE pipeline stage can't
1375 * arbitrarily rearrange them to suit our whim; we have to put them
1376 * in an order that matches the output of the previous pipeline stage
1377 * (geometry or vertex shader).
1379 struct brw_vue_map prev_stage_vue_map
;
1380 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1381 key
->input_slots_valid
);
1382 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1383 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1384 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1386 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1387 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1390 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1391 (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1392 BITFIELD64_BIT(varying
))) {
1393 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1396 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1399 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1400 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1401 /* Point size is packed into the header, not as a general attribute */
1402 if (i
== VARYING_SLOT_PSIZ
)
1405 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1406 /* The back color slot is skipped when the front color is
1407 * also written to. In addition, some slots can be
1408 * written in the vertex shader and not read in the
1409 * fragment shader. So the register number must always be
1410 * incremented, mapped or not.
1412 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1413 prog_data
->urb_setup
[i
] = urb_next
;
1419 * It's a FS only attribute, and we did interpolation for this attribute
1420 * in SF thread. So, count it here, too.
1422 * See compile_sf_prog() for more info.
1424 if (prog
->InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1425 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1428 prog_data
->num_varying_inputs
= urb_next
;
1432 fs_visitor::assign_urb_setup()
1434 assert(stage
== MESA_SHADER_FRAGMENT
);
1435 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1437 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1439 /* Offset all the urb_setup[] index by the actual position of the
1440 * setup regs, now that the location of the constants has been chosen.
1442 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1443 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1444 assert(inst
->src
[1].file
== HW_REG
);
1445 inst
->src
[1].fixed_hw_reg
.nr
+= urb_start
;
1448 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1449 assert(inst
->src
[0].file
== HW_REG
);
1450 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1454 /* Each attribute is 4 setup channels, each of which is half a reg. */
1455 this->first_non_payload_grf
=
1456 urb_start
+ prog_data
->num_varying_inputs
* 2;
1460 fs_visitor::assign_vs_urb_setup()
1462 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1463 int grf
, count
, slot
, channel
, attr
;
1465 assert(stage
== MESA_SHADER_VERTEX
);
1466 count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1467 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1470 /* Each attribute is 4 regs. */
1471 this->first_non_payload_grf
=
1472 payload
.num_regs
+ prog_data
->curb_read_length
+ count
* 4;
1474 unsigned vue_entries
=
1475 MAX2(count
, vs_prog_data
->base
.vue_map
.num_slots
);
1477 vs_prog_data
->base
.urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1478 vs_prog_data
->base
.urb_read_length
= (count
+ 1) / 2;
1480 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1482 /* Rewrite all ATTR file references to the hw grf that they land in. */
1483 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1484 for (int i
= 0; i
< inst
->sources
; i
++) {
1485 if (inst
->src
[i
].file
== ATTR
) {
1487 if (inst
->src
[i
].reg
== VERT_ATTRIB_MAX
) {
1490 /* Attributes come in in a contiguous block, ordered by their
1491 * gl_vert_attrib value. That means we can compute the slot
1492 * number for an attribute by masking out the enabled
1493 * attributes before it and counting the bits.
1495 attr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
/ 4;
1496 slot
= _mesa_bitcount_64(vs_prog_data
->inputs_read
&
1497 BITFIELD64_MASK(attr
));
1500 channel
= inst
->src
[i
].reg_offset
& 3;
1502 grf
= payload
.num_regs
+
1503 prog_data
->curb_read_length
+
1506 inst
->src
[i
].file
= HW_REG
;
1507 inst
->src
[i
].fixed_hw_reg
=
1508 retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
);
1515 * Split large virtual GRFs into separate components if we can.
1517 * This is mostly duplicated with what brw_fs_vector_splitting does,
1518 * but that's really conservative because it's afraid of doing
1519 * splitting that doesn't result in real progress after the rest of
1520 * the optimization phases, which would cause infinite looping in
1521 * optimization. We can do it once here, safely. This also has the
1522 * opportunity to split interpolated values, or maybe even uniforms,
1523 * which we don't have at the IR level.
1525 * We want to split, because virtual GRFs are what we register
1526 * allocate and spill (due to contiguousness requirements for some
1527 * instructions), and they're what we naturally generate in the
1528 * codegen process, but most virtual GRFs don't actually need to be
1529 * contiguous sets of GRFs. If we split, we'll end up with reduced
1530 * live intervals and better dead code elimination and coalescing.
1533 fs_visitor::split_virtual_grfs()
1535 int num_vars
= this->alloc
.count
;
1537 /* Count the total number of registers */
1539 int vgrf_to_reg
[num_vars
];
1540 for (int i
= 0; i
< num_vars
; i
++) {
1541 vgrf_to_reg
[i
] = reg_count
;
1542 reg_count
+= alloc
.sizes
[i
];
1545 /* An array of "split points". For each register slot, this indicates
1546 * if this slot can be separated from the previous slot. Every time an
1547 * instruction uses multiple elements of a register (as a source or
1548 * destination), we mark the used slots as inseparable. Then we go
1549 * through and split the registers into the smallest pieces we can.
1551 bool split_points
[reg_count
];
1552 memset(split_points
, 0, sizeof(split_points
));
1554 /* Mark all used registers as fully splittable */
1555 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1556 if (inst
->dst
.file
== GRF
) {
1557 int reg
= vgrf_to_reg
[inst
->dst
.reg
];
1558 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.reg
]; j
++)
1559 split_points
[reg
+ j
] = true;
1562 for (int i
= 0; i
< inst
->sources
; i
++) {
1563 if (inst
->src
[i
].file
== GRF
) {
1564 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
];
1565 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].reg
]; j
++)
1566 split_points
[reg
+ j
] = true;
1571 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1572 if (inst
->dst
.file
== GRF
) {
1573 int reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1574 for (int j
= 1; j
< inst
->regs_written
; j
++)
1575 split_points
[reg
+ j
] = false;
1577 for (int i
= 0; i
< inst
->sources
; i
++) {
1578 if (inst
->src
[i
].file
== GRF
) {
1579 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1580 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1581 split_points
[reg
+ j
] = false;
1586 int new_virtual_grf
[reg_count
];
1587 int new_reg_offset
[reg_count
];
1590 for (int i
= 0; i
< num_vars
; i
++) {
1591 /* The first one should always be 0 as a quick sanity check. */
1592 assert(split_points
[reg
] == false);
1595 new_reg_offset
[reg
] = 0;
1600 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1601 /* If this is a split point, reset the offset to 0 and allocate a
1602 * new virtual GRF for the previous offset many registers
1604 if (split_points
[reg
]) {
1605 assert(offset
<= MAX_VGRF_SIZE
);
1606 int grf
= alloc
.allocate(offset
);
1607 for (int k
= reg
- offset
; k
< reg
; k
++)
1608 new_virtual_grf
[k
] = grf
;
1611 new_reg_offset
[reg
] = offset
;
1616 /* The last one gets the original register number */
1617 assert(offset
<= MAX_VGRF_SIZE
);
1618 alloc
.sizes
[i
] = offset
;
1619 for (int k
= reg
- offset
; k
< reg
; k
++)
1620 new_virtual_grf
[k
] = i
;
1622 assert(reg
== reg_count
);
1624 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1625 if (inst
->dst
.file
== GRF
) {
1626 reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1627 inst
->dst
.reg
= new_virtual_grf
[reg
];
1628 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1629 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1631 for (int i
= 0; i
< inst
->sources
; i
++) {
1632 if (inst
->src
[i
].file
== GRF
) {
1633 reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1634 inst
->src
[i
].reg
= new_virtual_grf
[reg
];
1635 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1636 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1640 invalidate_live_intervals();
1644 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1646 * During code generation, we create tons of temporary variables, many of
1647 * which get immediately killed and are never used again. Yet, in later
1648 * optimization and analysis passes, such as compute_live_intervals, we need
1649 * to loop over all the virtual GRFs. Compacting them can save a lot of
1653 fs_visitor::compact_virtual_grfs()
1655 bool progress
= false;
1656 int remap_table
[this->alloc
.count
];
1657 memset(remap_table
, -1, sizeof(remap_table
));
1659 /* Mark which virtual GRFs are used. */
1660 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1661 if (inst
->dst
.file
== GRF
)
1662 remap_table
[inst
->dst
.reg
] = 0;
1664 for (int i
= 0; i
< inst
->sources
; i
++) {
1665 if (inst
->src
[i
].file
== GRF
)
1666 remap_table
[inst
->src
[i
].reg
] = 0;
1670 /* Compact the GRF arrays. */
1672 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1673 if (remap_table
[i
] == -1) {
1674 /* We just found an unused register. This means that we are
1675 * actually going to compact something.
1679 remap_table
[i
] = new_index
;
1680 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1681 invalidate_live_intervals();
1686 this->alloc
.count
= new_index
;
1688 /* Patch all the instructions to use the newly renumbered registers */
1689 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1690 if (inst
->dst
.file
== GRF
)
1691 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1693 for (int i
= 0; i
< inst
->sources
; i
++) {
1694 if (inst
->src
[i
].file
== GRF
)
1695 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1699 /* Patch all the references to delta_xy, since they're used in register
1700 * allocation. If they're unused, switch them to BAD_FILE so we don't
1701 * think some random VGRF is delta_xy.
1703 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1704 if (delta_xy
[i
].file
== GRF
) {
1705 if (remap_table
[delta_xy
[i
].reg
] != -1) {
1706 delta_xy
[i
].reg
= remap_table
[delta_xy
[i
].reg
];
1708 delta_xy
[i
].file
= BAD_FILE
;
1717 * Implements array access of uniforms by inserting a
1718 * PULL_CONSTANT_LOAD instruction.
1720 * Unlike temporary GRF array access (where we don't support it due to
1721 * the difficulty of doing relative addressing on instruction
1722 * destinations), we could potentially do array access of uniforms
1723 * that were loaded in GRF space as push constants. In real-world
1724 * usage we've seen, though, the arrays being used are always larger
1725 * than we could load as push constants, so just always move all
1726 * uniform array access out to a pull constant buffer.
1729 fs_visitor::move_uniform_array_access_to_pull_constants()
1731 if (dispatch_width
!= 8)
1734 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1735 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1737 /* Walk through and find array access of uniforms. Put a copy of that
1738 * uniform in the pull constant buffer.
1740 * Note that we don't move constant-indexed accesses to arrays. No
1741 * testing has been done of the performance impact of this choice.
1743 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1744 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1745 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
1748 int uniform
= inst
->src
[i
].reg
;
1750 /* If this array isn't already present in the pull constant buffer,
1753 if (pull_constant_loc
[uniform
] == -1) {
1754 const gl_constant_value
**values
= &stage_prog_data
->param
[uniform
];
1756 assert(param_size
[uniform
]);
1758 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
1759 pull_constant_loc
[uniform
+ j
] = stage_prog_data
->nr_pull_params
;
1761 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
1770 * Assign UNIFORM file registers to either push constants or pull constants.
1772 * We allow a fragment shader to have more than the specified minimum
1773 * maximum number of fragment shader uniform components (64). If
1774 * there are too many of these, they'd fill up all of register space.
1775 * So, this will push some of them out to the pull constant buffer and
1776 * update the program to load them.
1779 fs_visitor::assign_constant_locations()
1781 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1782 if (dispatch_width
!= 8)
1785 /* Find which UNIFORM registers are still in use. */
1786 bool is_live
[uniforms
];
1787 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1791 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1792 for (int i
= 0; i
< inst
->sources
; i
++) {
1793 if (inst
->src
[i
].file
!= UNIFORM
)
1796 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1797 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1798 is_live
[constant_nr
] = true;
1802 /* Only allow 16 registers (128 uniform components) as push constants.
1804 * Just demote the end of the list. We could probably do better
1805 * here, demoting things that are rarely used in the program first.
1807 * If changing this value, note the limitation about total_regs in
1810 unsigned int max_push_components
= 16 * 8;
1811 unsigned int num_push_constants
= 0;
1813 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1815 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1816 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1817 /* This UNIFORM register is either dead, or has already been demoted
1818 * to a pull const. Mark it as no longer living in the param[] array.
1820 push_constant_loc
[i
] = -1;
1824 if (num_push_constants
< max_push_components
) {
1825 /* Retain as a push constant. Record the location in the params[]
1828 push_constant_loc
[i
] = num_push_constants
++;
1830 /* Demote to a pull constant. */
1831 push_constant_loc
[i
] = -1;
1833 int pull_index
= stage_prog_data
->nr_pull_params
++;
1834 stage_prog_data
->pull_param
[pull_index
] = stage_prog_data
->param
[i
];
1835 pull_constant_loc
[i
] = pull_index
;
1839 stage_prog_data
->nr_params
= num_push_constants
;
1841 /* Up until now, the param[] array has been indexed by reg + reg_offset
1842 * of UNIFORM registers. Condense it to only contain the uniforms we
1843 * chose to upload as push constants.
1845 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1846 int remapped
= push_constant_loc
[i
];
1851 assert(remapped
<= (int)i
);
1852 stage_prog_data
->param
[remapped
] = stage_prog_data
->param
[i
];
1857 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
1858 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
1861 fs_visitor::demote_pull_constants()
1863 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1864 for (int i
= 0; i
< inst
->sources
; i
++) {
1865 if (inst
->src
[i
].file
!= UNIFORM
)
1869 unsigned location
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1870 if (location
>= uniforms
) /* Out of bounds access */
1873 pull_index
= pull_constant_loc
[location
];
1875 if (pull_index
== -1)
1878 /* Set up the annotation tracking for new generated instructions. */
1879 const fs_builder ibld
= bld
.annotate(inst
->annotation
, inst
->ir
)
1881 fs_reg
surf_index(stage_prog_data
->binding_table
.pull_constants_start
);
1882 fs_reg dst
= vgrf(glsl_type::float_type
);
1884 /* Generate a pull load into dst. */
1885 if (inst
->src
[i
].reladdr
) {
1886 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
1888 *inst
->src
[i
].reladdr
,
1890 inst
->src
[i
].reladdr
= NULL
;
1892 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
1893 ibld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
1894 dst
, surf_index
, offset
);
1895 inst
->src
[i
].set_smear(pull_index
& 3);
1898 /* Rewrite the instruction to use the temporary VGRF. */
1899 inst
->src
[i
].file
= GRF
;
1900 inst
->src
[i
].reg
= dst
.reg
;
1901 inst
->src
[i
].reg_offset
= 0;
1902 inst
->src
[i
].width
= dispatch_width
;
1905 invalidate_live_intervals();
1909 fs_visitor::opt_algebraic()
1911 bool progress
= false;
1913 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1914 switch (inst
->opcode
) {
1915 case BRW_OPCODE_MOV
:
1916 if (inst
->src
[0].file
!= IMM
)
1919 if (inst
->saturate
) {
1920 if (inst
->dst
.type
!= inst
->src
[0].type
)
1921 assert(!"unimplemented: saturate mixed types");
1923 if (brw_saturate_immediate(inst
->dst
.type
,
1924 &inst
->src
[0].fixed_hw_reg
)) {
1925 inst
->saturate
= false;
1931 case BRW_OPCODE_MUL
:
1932 if (inst
->src
[1].file
!= IMM
)
1936 if (inst
->src
[1].is_one()) {
1937 inst
->opcode
= BRW_OPCODE_MOV
;
1938 inst
->src
[1] = reg_undef
;
1944 if (inst
->src
[1].is_negative_one()) {
1945 inst
->opcode
= BRW_OPCODE_MOV
;
1946 inst
->src
[0].negate
= !inst
->src
[0].negate
;
1947 inst
->src
[1] = reg_undef
;
1953 if (inst
->src
[1].is_zero()) {
1954 inst
->opcode
= BRW_OPCODE_MOV
;
1955 inst
->src
[0] = inst
->src
[1];
1956 inst
->src
[1] = reg_undef
;
1961 if (inst
->src
[0].file
== IMM
) {
1962 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
1963 inst
->opcode
= BRW_OPCODE_MOV
;
1964 inst
->src
[0].fixed_hw_reg
.dw1
.f
*= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
1965 inst
->src
[1] = reg_undef
;
1970 case BRW_OPCODE_ADD
:
1971 if (inst
->src
[1].file
!= IMM
)
1975 if (inst
->src
[1].is_zero()) {
1976 inst
->opcode
= BRW_OPCODE_MOV
;
1977 inst
->src
[1] = reg_undef
;
1982 if (inst
->src
[0].file
== IMM
) {
1983 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
1984 inst
->opcode
= BRW_OPCODE_MOV
;
1985 inst
->src
[0].fixed_hw_reg
.dw1
.f
+= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
1986 inst
->src
[1] = reg_undef
;
1992 if (inst
->src
[0].equals(inst
->src
[1])) {
1993 inst
->opcode
= BRW_OPCODE_MOV
;
1994 inst
->src
[1] = reg_undef
;
1999 case BRW_OPCODE_LRP
:
2000 if (inst
->src
[1].equals(inst
->src
[2])) {
2001 inst
->opcode
= BRW_OPCODE_MOV
;
2002 inst
->src
[0] = inst
->src
[1];
2003 inst
->src
[1] = reg_undef
;
2004 inst
->src
[2] = reg_undef
;
2009 case BRW_OPCODE_CMP
:
2010 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2012 inst
->src
[0].negate
&&
2013 inst
->src
[1].is_zero()) {
2014 inst
->src
[0].abs
= false;
2015 inst
->src
[0].negate
= false;
2016 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2021 case BRW_OPCODE_SEL
:
2022 if (inst
->src
[0].equals(inst
->src
[1])) {
2023 inst
->opcode
= BRW_OPCODE_MOV
;
2024 inst
->src
[1] = reg_undef
;
2025 inst
->predicate
= BRW_PREDICATE_NONE
;
2026 inst
->predicate_inverse
= false;
2028 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2029 switch (inst
->conditional_mod
) {
2030 case BRW_CONDITIONAL_LE
:
2031 case BRW_CONDITIONAL_L
:
2032 switch (inst
->src
[1].type
) {
2033 case BRW_REGISTER_TYPE_F
:
2034 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
>= 1.0f
) {
2035 inst
->opcode
= BRW_OPCODE_MOV
;
2036 inst
->src
[1] = reg_undef
;
2037 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2045 case BRW_CONDITIONAL_GE
:
2046 case BRW_CONDITIONAL_G
:
2047 switch (inst
->src
[1].type
) {
2048 case BRW_REGISTER_TYPE_F
:
2049 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
<= 0.0f
) {
2050 inst
->opcode
= BRW_OPCODE_MOV
;
2051 inst
->src
[1] = reg_undef
;
2052 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2064 case BRW_OPCODE_MAD
:
2065 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2066 inst
->opcode
= BRW_OPCODE_MOV
;
2067 inst
->src
[1] = reg_undef
;
2068 inst
->src
[2] = reg_undef
;
2070 } else if (inst
->src
[0].is_zero()) {
2071 inst
->opcode
= BRW_OPCODE_MUL
;
2072 inst
->src
[0] = inst
->src
[2];
2073 inst
->src
[2] = reg_undef
;
2075 } else if (inst
->src
[1].is_one()) {
2076 inst
->opcode
= BRW_OPCODE_ADD
;
2077 inst
->src
[1] = inst
->src
[2];
2078 inst
->src
[2] = reg_undef
;
2080 } else if (inst
->src
[2].is_one()) {
2081 inst
->opcode
= BRW_OPCODE_ADD
;
2082 inst
->src
[2] = reg_undef
;
2084 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2085 inst
->opcode
= BRW_OPCODE_ADD
;
2086 inst
->src
[1].fixed_hw_reg
.dw1
.f
*= inst
->src
[2].fixed_hw_reg
.dw1
.f
;
2087 inst
->src
[2] = reg_undef
;
2091 case SHADER_OPCODE_RCP
: {
2092 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2093 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2094 if (inst
->src
[0].equals(prev
->dst
)) {
2095 inst
->opcode
= SHADER_OPCODE_RSQ
;
2096 inst
->src
[0] = prev
->src
[0];
2102 case SHADER_OPCODE_BROADCAST
:
2103 if (is_uniform(inst
->src
[0])) {
2104 inst
->opcode
= BRW_OPCODE_MOV
;
2106 inst
->force_writemask_all
= true;
2108 } else if (inst
->src
[1].file
== IMM
) {
2109 inst
->opcode
= BRW_OPCODE_MOV
;
2110 inst
->src
[0] = component(inst
->src
[0],
2111 inst
->src
[1].fixed_hw_reg
.dw1
.ud
);
2113 inst
->force_writemask_all
= true;
2122 /* Swap if src[0] is immediate. */
2123 if (progress
&& inst
->is_commutative()) {
2124 if (inst
->src
[0].file
== IMM
) {
2125 fs_reg tmp
= inst
->src
[1];
2126 inst
->src
[1] = inst
->src
[0];
2135 * Optimize sample messages that have constant zero values for the trailing
2136 * texture coordinates. We can just reduce the message length for these
2137 * instructions instead of reserving a register for it. Trailing parameters
2138 * that aren't sent default to zero anyway. This will cause the dead code
2139 * eliminator to remove the MOV instruction that would otherwise be emitted to
2140 * set up the zero value.
2143 fs_visitor::opt_zero_samples()
2145 /* Gen4 infers the texturing opcode based on the message length so we can't
2148 if (devinfo
->gen
< 5)
2151 bool progress
= false;
2153 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2154 if (!inst
->is_tex())
2157 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2159 if (load_payload
->is_head_sentinel() ||
2160 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2163 /* We don't want to remove the message header or the first parameter.
2164 * Removing the first parameter is not allowed, see the Haswell PRM
2165 * volume 7, page 149:
2167 * "Parameter 0 is required except for the sampleinfo message, which
2168 * has no parameter 0"
2170 while (inst
->mlen
> inst
->header_size
+ dispatch_width
/ 8 &&
2171 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2172 (dispatch_width
/ 8) +
2173 inst
->header_size
- 1].is_zero()) {
2174 inst
->mlen
-= dispatch_width
/ 8;
2180 invalidate_live_intervals();
2186 * Optimize sample messages which are followed by the final RT write.
2188 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2189 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2190 * final texturing results copied to the framebuffer write payload and modify
2191 * them to write to the framebuffer directly.
2194 fs_visitor::opt_sampler_eot()
2196 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2198 if (stage
!= MESA_SHADER_FRAGMENT
)
2201 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2204 /* FINISHME: It should be possible to implement this optimization when there
2205 * are multiple drawbuffers.
2207 if (key
->nr_color_regions
!= 1)
2210 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2211 fs_inst
*fb_write
= (fs_inst
*) cfg
->blocks
[cfg
->num_blocks
- 1]->end();
2212 assert(fb_write
->eot
);
2213 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2215 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2217 /* There wasn't one; nothing to do. */
2218 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2221 /* This optimisation doesn't seem to work for textureGather for some
2222 * reason. I can't find any documentation or known workarounds to indicate
2223 * that this is expected, but considering that it is probably pretty
2224 * unlikely that a shader would directly write out the results from
2225 * textureGather we might as well just disable it.
2227 if (tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2228 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2231 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2232 * It's very likely to be the previous instruction.
2234 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2235 if (load_payload
->is_head_sentinel() ||
2236 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2239 assert(!tex_inst
->eot
); /* We can't get here twice */
2240 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2242 tex_inst
->offset
|= fb_write
->target
<< 24;
2243 tex_inst
->eot
= true;
2244 tex_inst
->dst
= bld
.null_reg_ud();
2245 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2247 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2248 * to create a new LOAD_PAYLOAD command with the same sources and a space
2249 * saved for the header. Using a new destination register not only makes sure
2250 * we have enough space, but it will make sure the dead code eliminator kills
2251 * the instruction that this will replace.
2253 if (tex_inst
->header_size
!= 0)
2256 fs_reg send_header
= bld
.vgrf(BRW_REGISTER_TYPE_F
,
2257 load_payload
->sources
+ 1);
2258 fs_reg
*new_sources
=
2259 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2261 new_sources
[0] = fs_reg();
2262 for (int i
= 0; i
< load_payload
->sources
; i
++)
2263 new_sources
[i
+1] = load_payload
->src
[i
];
2265 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2266 * requires a lot of information about the sources to appropriately figure
2267 * out the number of registers needed to be used. Given this stage in our
2268 * optimization, we may not have the appropriate GRFs required by
2269 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2270 * manually emit the instruction.
2272 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2273 load_payload
->exec_size
,
2276 load_payload
->sources
+ 1);
2278 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2279 new_load_payload
->header_size
= 1;
2281 tex_inst
->header_size
= 1;
2282 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2283 tex_inst
->src
[0] = send_header
;
2289 fs_visitor::opt_register_renaming()
2291 bool progress
= false;
2294 int remap
[alloc
.count
];
2295 memset(remap
, -1, sizeof(int) * alloc
.count
);
2297 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2298 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2300 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2301 inst
->opcode
== BRW_OPCODE_WHILE
) {
2305 /* Rewrite instruction sources. */
2306 for (int i
= 0; i
< inst
->sources
; i
++) {
2307 if (inst
->src
[i
].file
== GRF
&&
2308 remap
[inst
->src
[i
].reg
] != -1 &&
2309 remap
[inst
->src
[i
].reg
] != inst
->src
[i
].reg
) {
2310 inst
->src
[i
].reg
= remap
[inst
->src
[i
].reg
];
2315 const int dst
= inst
->dst
.reg
;
2318 inst
->dst
.file
== GRF
&&
2319 alloc
.sizes
[inst
->dst
.reg
] == inst
->dst
.width
/ 8 &&
2320 !inst
->is_partial_write()) {
2321 if (remap
[dst
] == -1) {
2324 remap
[dst
] = alloc
.allocate(inst
->dst
.width
/ 8);
2325 inst
->dst
.reg
= remap
[dst
];
2328 } else if (inst
->dst
.file
== GRF
&&
2330 remap
[dst
] != dst
) {
2331 inst
->dst
.reg
= remap
[dst
];
2337 invalidate_live_intervals();
2339 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2340 if (delta_xy
[i
].file
== GRF
&& remap
[delta_xy
[i
].reg
] != -1) {
2341 delta_xy
[i
].reg
= remap
[delta_xy
[i
].reg
];
2350 * Remove redundant or useless discard jumps.
2352 * For example, we can eliminate jumps in the following sequence:
2354 * discard-jump (redundant with the next jump)
2355 * discard-jump (useless; jumps to the next instruction)
2359 fs_visitor::opt_redundant_discard_jumps()
2361 bool progress
= false;
2363 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2365 fs_inst
*placeholder_halt
= NULL
;
2366 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2367 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2368 placeholder_halt
= inst
;
2373 if (!placeholder_halt
)
2376 /* Delete any HALTs immediately before the placeholder halt. */
2377 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2378 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2379 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2380 prev
->remove(last_bblock
);
2385 invalidate_live_intervals();
2391 fs_visitor::compute_to_mrf()
2393 bool progress
= false;
2396 /* No MRFs on Gen >= 7. */
2397 if (devinfo
->gen
>= 7)
2400 calculate_live_intervals();
2402 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2406 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2407 inst
->is_partial_write() ||
2408 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2409 inst
->dst
.type
!= inst
->src
[0].type
||
2410 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2411 !inst
->src
[0].is_contiguous() ||
2412 inst
->src
[0].subreg_offset
)
2415 /* Work out which hardware MRF registers are written by this
2418 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2420 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2421 mrf_high
= mrf_low
+ 4;
2422 } else if (inst
->exec_size
== 16) {
2423 mrf_high
= mrf_low
+ 1;
2428 /* Can't compute-to-MRF this GRF if someone else was going to
2431 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2434 /* Found a move of a GRF to a MRF. Let's see if we can go
2435 * rewrite the thing that made this GRF to write into the MRF.
2437 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2438 if (scan_inst
->dst
.file
== GRF
&&
2439 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2440 /* Found the last thing to write our reg we want to turn
2441 * into a compute-to-MRF.
2444 /* If this one instruction didn't populate all the
2445 * channels, bail. We might be able to rewrite everything
2446 * that writes that reg, but it would require smarter
2447 * tracking to delay the rewriting until complete success.
2449 if (scan_inst
->is_partial_write())
2452 /* Things returning more than one register would need us to
2453 * understand coalescing out more than one MOV at a time.
2455 if (scan_inst
->regs_written
> scan_inst
->dst
.width
/ 8)
2458 /* SEND instructions can't have MRF as a destination. */
2459 if (scan_inst
->mlen
)
2462 if (devinfo
->gen
== 6) {
2463 /* gen6 math instructions must have the destination be
2464 * GRF, so no compute-to-MRF for them.
2466 if (scan_inst
->is_math()) {
2471 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2472 /* Found the creator of our MRF's source value. */
2473 scan_inst
->dst
.file
= MRF
;
2474 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2475 scan_inst
->saturate
|= inst
->saturate
;
2476 inst
->remove(block
);
2482 /* We don't handle control flow here. Most computation of
2483 * values that end up in MRFs are shortly before the MRF
2486 if (block
->start() == scan_inst
)
2489 /* You can't read from an MRF, so if someone else reads our
2490 * MRF's source GRF that we wanted to rewrite, that stops us.
2492 bool interfered
= false;
2493 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2494 if (scan_inst
->src
[i
].file
== GRF
&&
2495 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2496 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2503 if (scan_inst
->dst
.file
== MRF
) {
2504 /* If somebody else writes our MRF here, we can't
2505 * compute-to-MRF before that.
2507 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2510 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2511 scan_mrf_high
= scan_mrf_low
+ 4;
2512 } else if (scan_inst
->exec_size
== 16) {
2513 scan_mrf_high
= scan_mrf_low
+ 1;
2515 scan_mrf_high
= scan_mrf_low
;
2518 if (mrf_low
== scan_mrf_low
||
2519 mrf_low
== scan_mrf_high
||
2520 mrf_high
== scan_mrf_low
||
2521 mrf_high
== scan_mrf_high
) {
2526 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2527 /* Found a SEND instruction, which means that there are
2528 * live values in MRFs from base_mrf to base_mrf +
2529 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2532 if (mrf_low
>= scan_inst
->base_mrf
&&
2533 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2536 if (mrf_high
>= scan_inst
->base_mrf
&&
2537 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2545 invalidate_live_intervals();
2551 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2552 * flow. We could probably do better here with some form of divergence
2556 fs_visitor::eliminate_find_live_channel()
2558 bool progress
= false;
2561 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2562 switch (inst
->opcode
) {
2568 case BRW_OPCODE_ENDIF
:
2569 case BRW_OPCODE_WHILE
:
2573 case FS_OPCODE_DISCARD_JUMP
:
2574 /* This can potentially make control flow non-uniform until the end
2579 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2581 inst
->opcode
= BRW_OPCODE_MOV
;
2582 inst
->src
[0] = fs_reg(0);
2584 inst
->force_writemask_all
= true;
2598 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2599 * instructions to FS_OPCODE_REP_FB_WRITE.
2602 fs_visitor::emit_repclear_shader()
2604 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2606 int color_mrf
= base_mrf
+ 2;
2608 fs_inst
*mov
= bld
.exec_all().MOV(vec4(brw_message_reg(color_mrf
)),
2609 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2612 if (key
->nr_color_regions
== 1) {
2613 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2614 write
->saturate
= key
->clamp_fragment_color
;
2615 write
->base_mrf
= color_mrf
;
2617 write
->header_size
= 0;
2620 assume(key
->nr_color_regions
> 0);
2621 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2622 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2623 write
->saturate
= key
->clamp_fragment_color
;
2624 write
->base_mrf
= base_mrf
;
2626 write
->header_size
= 2;
2634 assign_constant_locations();
2635 assign_curb_setup();
2637 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2638 assert(mov
->src
[0].file
== HW_REG
);
2639 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].fixed_hw_reg
.nr
, 0);
2643 * Walks through basic blocks, looking for repeated MRF writes and
2644 * removing the later ones.
2647 fs_visitor::remove_duplicate_mrf_writes()
2649 fs_inst
*last_mrf_move
[16];
2650 bool progress
= false;
2652 /* Need to update the MRF tracking for compressed instructions. */
2653 if (dispatch_width
== 16)
2656 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2658 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2659 if (inst
->is_control_flow()) {
2660 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2663 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2664 inst
->dst
.file
== MRF
) {
2665 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2666 if (prev_inst
&& inst
->equals(prev_inst
)) {
2667 inst
->remove(block
);
2673 /* Clear out the last-write records for MRFs that were overwritten. */
2674 if (inst
->dst
.file
== MRF
) {
2675 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2678 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2679 /* Found a SEND instruction, which will include two or fewer
2680 * implied MRF writes. We could do better here.
2682 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2683 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2687 /* Clear out any MRF move records whose sources got overwritten. */
2688 if (inst
->dst
.file
== GRF
) {
2689 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2690 if (last_mrf_move
[i
] &&
2691 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2692 last_mrf_move
[i
] = NULL
;
2697 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2698 inst
->dst
.file
== MRF
&&
2699 inst
->src
[0].file
== GRF
&&
2700 !inst
->is_partial_write()) {
2701 last_mrf_move
[inst
->dst
.reg
] = inst
;
2706 invalidate_live_intervals();
2712 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2714 /* Clear the flag for registers that actually got read (as expected). */
2715 for (int i
= 0; i
< inst
->sources
; i
++) {
2717 if (inst
->src
[i
].file
== GRF
) {
2718 grf
= inst
->src
[i
].reg
;
2719 } else if (inst
->src
[i
].file
== HW_REG
&&
2720 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2721 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2726 if (grf
>= first_grf
&&
2727 grf
< first_grf
+ grf_len
) {
2728 deps
[grf
- first_grf
] = false;
2729 if (inst
->exec_size
== 16)
2730 deps
[grf
- first_grf
+ 1] = false;
2736 * Implements this workaround for the original 965:
2738 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2739 * check for post destination dependencies on this instruction, software
2740 * must ensure that there is no destination hazard for the case of ‘write
2741 * followed by a posted write’ shown in the following example.
2744 * 2. send r3.xy <rest of send instruction>
2747 * Due to no post-destination dependency check on the ‘send’, the above
2748 * code sequence could have two instructions (1 and 2) in flight at the
2749 * same time that both consider ‘r3’ as the target of their final writes.
2752 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2755 int write_len
= inst
->regs_written
;
2756 int first_write_grf
= inst
->dst
.reg
;
2757 bool needs_dep
[BRW_MAX_MRF
];
2758 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2760 memset(needs_dep
, false, sizeof(needs_dep
));
2761 memset(needs_dep
, true, write_len
);
2763 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2765 /* Walk backwards looking for writes to registers we're writing which
2766 * aren't read since being written. If we hit the start of the program,
2767 * we assume that there are no outstanding dependencies on entry to the
2770 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2771 /* If we hit control flow, assume that there *are* outstanding
2772 * dependencies, and force their cleanup before our instruction.
2774 if (block
->start() == scan_inst
) {
2775 for (int i
= 0; i
< write_len
; i
++) {
2777 DEP_RESOLVE_MOV(bld
.at(block
, inst
), first_write_grf
+ i
);
2782 /* We insert our reads as late as possible on the assumption that any
2783 * instruction but a MOV that might have left us an outstanding
2784 * dependency has more latency than a MOV.
2786 if (scan_inst
->dst
.file
== GRF
) {
2787 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2788 int reg
= scan_inst
->dst
.reg
+ i
;
2790 if (reg
>= first_write_grf
&&
2791 reg
< first_write_grf
+ write_len
&&
2792 needs_dep
[reg
- first_write_grf
]) {
2793 DEP_RESOLVE_MOV(bld
.at(block
, inst
), reg
);
2794 needs_dep
[reg
- first_write_grf
] = false;
2795 if (scan_inst
->exec_size
== 16)
2796 needs_dep
[reg
- first_write_grf
+ 1] = false;
2801 /* Clear the flag for registers that actually got read (as expected). */
2802 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2804 /* Continue the loop only if we haven't resolved all the dependencies */
2806 for (i
= 0; i
< write_len
; i
++) {
2816 * Implements this workaround for the original 965:
2818 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2819 * used as a destination register until after it has been sourced by an
2820 * instruction with a different destination register.
2823 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2825 int write_len
= inst
->regs_written
;
2826 int first_write_grf
= inst
->dst
.reg
;
2827 bool needs_dep
[BRW_MAX_MRF
];
2828 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2830 memset(needs_dep
, false, sizeof(needs_dep
));
2831 memset(needs_dep
, true, write_len
);
2832 /* Walk forwards looking for writes to registers we're writing which aren't
2833 * read before being written.
2835 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2836 /* If we hit control flow, force resolve all remaining dependencies. */
2837 if (block
->end() == scan_inst
) {
2838 for (int i
= 0; i
< write_len
; i
++) {
2840 DEP_RESOLVE_MOV(bld
.at(block
, scan_inst
), first_write_grf
+ i
);
2845 /* Clear the flag for registers that actually got read (as expected). */
2846 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2848 /* We insert our reads as late as possible since they're reading the
2849 * result of a SEND, which has massive latency.
2851 if (scan_inst
->dst
.file
== GRF
&&
2852 scan_inst
->dst
.reg
>= first_write_grf
&&
2853 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
2854 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
2855 DEP_RESOLVE_MOV(bld
.at(block
, scan_inst
), scan_inst
->dst
.reg
);
2856 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
2859 /* Continue the loop only if we haven't resolved all the dependencies */
2861 for (i
= 0; i
< write_len
; i
++) {
2871 fs_visitor::insert_gen4_send_dependency_workarounds()
2873 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
2876 bool progress
= false;
2878 /* Note that we're done with register allocation, so GRF fs_regs always
2879 * have a .reg_offset of 0.
2882 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2883 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
2884 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
2885 insert_gen4_post_send_dependency_workarounds(block
, inst
);
2891 invalidate_live_intervals();
2895 * Turns the generic expression-style uniform pull constant load instruction
2896 * into a hardware-specific series of instructions for loading a pull
2899 * The expression style allows the CSE pass before this to optimize out
2900 * repeated loads from the same offset, and gives the pre-register-allocation
2901 * scheduling full flexibility, while the conversion to native instructions
2902 * allows the post-register-allocation scheduler the best information
2905 * Note that execution masking for setting up pull constant loads is special:
2906 * the channels that need to be written are unrelated to the current execution
2907 * mask, since a later instruction will use one of the result channels as a
2908 * source operand for all 8 or 16 of its channels.
2911 fs_visitor::lower_uniform_pull_constant_loads()
2913 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2914 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
2917 if (devinfo
->gen
>= 7) {
2918 /* The offset arg before was a vec4-aligned byte offset. We need to
2919 * turn it into a dword offset.
2921 fs_reg const_offset_reg
= inst
->src
[1];
2922 assert(const_offset_reg
.file
== IMM
&&
2923 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
2924 const_offset_reg
.fixed_hw_reg
.dw1
.ud
/= 4;
2926 fs_reg payload
, offset
;
2927 if (devinfo
->gen
>= 9) {
2928 /* We have to use a message header on Skylake to get SIMD4x2
2929 * mode. Reserve space for the register.
2931 offset
= payload
= fs_reg(GRF
, alloc
.allocate(2));
2932 offset
.reg_offset
++;
2935 offset
= payload
= fs_reg(GRF
, alloc
.allocate(1));
2939 /* This is actually going to be a MOV, but since only the first dword
2940 * is accessed, we have a special opcode to do just that one. Note
2941 * that this needs to be an operation that will be considered a def
2942 * by live variable analysis, or register allocation will explode.
2944 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
2945 8, offset
, const_offset_reg
);
2946 setup
->force_writemask_all
= true;
2948 setup
->ir
= inst
->ir
;
2949 setup
->annotation
= inst
->annotation
;
2950 inst
->insert_before(block
, setup
);
2952 /* Similarly, this will only populate the first 4 channels of the
2953 * result register (since we only use smear values from 0-3), but we
2954 * don't tell the optimizer.
2956 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
2957 inst
->src
[1] = payload
;
2958 inst
->base_mrf
= -1;
2960 invalidate_live_intervals();
2962 /* Before register allocation, we didn't tell the scheduler about the
2963 * MRF we use. We know it's safe to use this MRF because nothing
2964 * else does except for register spill/unspill, which generates and
2965 * uses its MRF within a single IR instruction.
2967 inst
->base_mrf
= 14;
2974 fs_visitor::lower_load_payload()
2976 bool progress
= false;
2978 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2979 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2982 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== GRF
);
2983 assert(inst
->saturate
== false);
2985 const fs_builder ibld
= bld
.group(inst
->exec_size
, inst
->force_sechalf
)
2986 .exec_all(inst
->force_writemask_all
)
2988 fs_reg dst
= inst
->dst
;
2990 /* Get rid of COMPR4. We'll add it back in if we need it */
2991 if (dst
.file
== MRF
)
2992 dst
.reg
= dst
.reg
& ~BRW_MRF_COMPR4
;
2995 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
2996 if (inst
->src
[i
].file
!= BAD_FILE
) {
2997 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
2998 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3000 ibld
.exec_all().MOV(mov_dst
, mov_src
);
3002 dst
= offset(dst
, 1);
3005 dst
.width
= inst
->exec_size
;
3006 if (inst
->dst
.file
== MRF
&& (inst
->dst
.reg
& BRW_MRF_COMPR4
) &&
3007 inst
->exec_size
> 8) {
3008 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3009 * a straightforward copy. Instead, the result of the
3010 * LOAD_PAYLOAD is treated as interleaved and the first four
3011 * non-header sources are unpacked as:
3022 * This is used for gen <= 5 fb writes.
3024 assert(inst
->exec_size
== 16);
3025 assert(inst
->header_size
+ 4 <= inst
->sources
);
3026 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3027 if (inst
->src
[i
].file
!= BAD_FILE
) {
3028 if (devinfo
->has_compr4
) {
3029 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3030 compr4_dst
.reg
|= BRW_MRF_COMPR4
;
3031 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3033 /* Platform doesn't have COMPR4. We have to fake it */
3034 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3036 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3037 ibld
.half(1).MOV(offset(mov_dst
, 4), half(inst
->src
[i
], 1));
3044 /* The loop above only ever incremented us through the first set
3045 * of 4 registers. However, thanks to the magic of COMPR4, we
3046 * actually wrote to the first 8 registers, so we need to take
3047 * that into account now.
3051 /* The COMPR4 code took care of the first 4 sources. We'll let
3052 * the regular path handle any remaining sources. Yes, we are
3053 * modifying the instruction but we're about to delete it so
3054 * this really doesn't hurt anything.
3056 inst
->header_size
+= 4;
3059 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3060 if (inst
->src
[i
].file
!= BAD_FILE
)
3061 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3062 dst
= offset(dst
, 1);
3065 inst
->remove(block
);
3070 invalidate_live_intervals();
3076 fs_visitor::lower_integer_multiplication()
3078 bool progress
= false;
3080 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit operation
3081 * directly, but Cherryview cannot.
3083 if (devinfo
->gen
>= 8 && !devinfo
->is_cherryview
)
3086 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3087 if (inst
->opcode
!= BRW_OPCODE_MUL
||
3088 inst
->dst
.is_accumulator() ||
3089 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3090 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3093 const fs_builder ibld
= bld
.at(block
, inst
);
3095 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3096 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3099 * If multiplying by an immediate value that fits in 16-bits, do a
3100 * single MUL instruction with that value in the proper location.
3102 if (inst
->src
[1].file
== IMM
&&
3103 inst
->src
[1].fixed_hw_reg
.dw1
.ud
< (1 << 16)) {
3104 if (devinfo
->gen
< 7) {
3105 fs_reg
imm(GRF
, alloc
.allocate(dispatch_width
/ 8),
3106 inst
->dst
.type
, dispatch_width
);
3107 ibld
.MOV(imm
, inst
->src
[1]);
3108 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3110 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3113 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3114 * do 32-bit integer multiplication in one instruction, but instead
3115 * must do a sequence (which actually calculates a 64-bit result):
3117 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3118 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3119 * mov(8) g2<1>D acc0<8,8,1>D
3121 * But on Gen > 6, the ability to use second accumulator register
3122 * (acc1) for non-float data types was removed, preventing a simple
3123 * implementation in SIMD16. A 16-channel result can be calculated by
3124 * executing the three instructions twice in SIMD8, once with quarter
3125 * control of 1Q for the first eight channels and again with 2Q for
3126 * the second eight channels.
3128 * Which accumulator register is implicitly accessed (by AccWrEnable
3129 * for instance) is determined by the quarter control. Unfortunately
3130 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3131 * implicit accumulator access by an instruction with 2Q will access
3132 * acc1 regardless of whether the data type is usable in acc1.
3134 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3135 * integer data types.
3137 * Since we only want the low 32-bits of the result, we can do two
3138 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3139 * adjust the high result and add them (like the mach is doing):
3141 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3142 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3143 * shl(8) g9<1>D g8<8,8,1>D 16D
3144 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3146 * We avoid the shl instruction by realizing that we only want to add
3147 * the low 16-bits of the "high" result to the high 16-bits of the
3148 * "low" result and using proper regioning on the add:
3150 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3151 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3152 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3154 * Since it does not use the (single) accumulator register, we can
3155 * schedule multi-component multiplications much better.
3158 if (inst
->conditional_mod
&& inst
->dst
.is_null()) {
3159 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
3160 inst
->dst
.type
, dispatch_width
);
3162 fs_reg low
= inst
->dst
;
3163 fs_reg
high(GRF
, alloc
.allocate(dispatch_width
/ 8),
3164 inst
->dst
.type
, dispatch_width
);
3166 if (devinfo
->gen
>= 7) {
3167 fs_reg src1_0_w
= inst
->src
[1];
3168 fs_reg src1_1_w
= inst
->src
[1];
3170 if (inst
->src
[1].file
== IMM
) {
3171 src1_0_w
.fixed_hw_reg
.dw1
.ud
&= 0xffff;
3172 src1_1_w
.fixed_hw_reg
.dw1
.ud
>>= 16;
3174 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3175 if (src1_0_w
.stride
!= 0) {
3176 assert(src1_0_w
.stride
== 1);
3177 src1_0_w
.stride
= 2;
3180 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3181 if (src1_1_w
.stride
!= 0) {
3182 assert(src1_1_w
.stride
== 1);
3183 src1_1_w
.stride
= 2;
3185 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3187 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3188 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3190 fs_reg src0_0_w
= inst
->src
[0];
3191 fs_reg src0_1_w
= inst
->src
[0];
3193 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3194 if (src0_0_w
.stride
!= 0) {
3195 assert(src0_0_w
.stride
== 1);
3196 src0_0_w
.stride
= 2;
3199 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3200 if (src0_1_w
.stride
!= 0) {
3201 assert(src0_1_w
.stride
== 1);
3202 src0_1_w
.stride
= 2;
3204 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3206 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3207 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3210 fs_reg dst
= inst
->dst
;
3211 dst
.type
= BRW_REGISTER_TYPE_UW
;
3212 dst
.subreg_offset
= 2;
3215 high
.type
= BRW_REGISTER_TYPE_UW
;
3218 low
.type
= BRW_REGISTER_TYPE_UW
;
3219 low
.subreg_offset
= 2;
3222 ibld
.ADD(dst
, low
, high
);
3224 if (inst
->conditional_mod
) {
3225 fs_reg
null(retype(ibld
.null_reg_f(), inst
->dst
.type
));
3226 set_condmod(inst
->conditional_mod
,
3227 ibld
.MOV(null
, inst
->dst
));
3231 inst
->remove(block
);
3236 invalidate_live_intervals();
3242 fs_visitor::dump_instructions()
3244 dump_instructions(NULL
);
3248 fs_visitor::dump_instructions(const char *name
)
3250 FILE *file
= stderr
;
3251 if (name
&& geteuid() != 0) {
3252 file
= fopen(name
, "w");
3258 calculate_register_pressure();
3259 int ip
= 0, max_pressure
= 0;
3260 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
3261 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
3262 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
3263 dump_instruction(inst
, file
);
3266 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
3269 foreach_in_list(backend_instruction
, inst
, &instructions
) {
3270 fprintf(file
, "%4d: ", ip
++);
3271 dump_instruction(inst
, file
);
3275 if (file
!= stderr
) {
3281 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
3283 dump_instruction(be_inst
, stderr
);
3287 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
3289 fs_inst
*inst
= (fs_inst
*)be_inst
;
3291 if (inst
->predicate
) {
3292 fprintf(file
, "(%cf0.%d) ",
3293 inst
->predicate_inverse
? '-' : '+',
3297 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
3299 fprintf(file
, ".sat");
3300 if (inst
->conditional_mod
) {
3301 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
3302 if (!inst
->predicate
&&
3303 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
3304 inst
->opcode
!= BRW_OPCODE_IF
&&
3305 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
3306 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
3309 fprintf(file
, "(%d) ", inst
->exec_size
);
3312 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
3315 switch (inst
->dst
.file
) {
3317 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
3318 if (inst
->dst
.width
!= dispatch_width
)
3319 fprintf(file
, "@%d", inst
->dst
.width
);
3320 if (alloc
.sizes
[inst
->dst
.reg
] != inst
->dst
.width
/ 8 ||
3321 inst
->dst
.subreg_offset
)
3322 fprintf(file
, "+%d.%d",
3323 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
3326 fprintf(file
, "m%d", inst
->dst
.reg
);
3329 fprintf(file
, "(null)");
3332 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
3335 fprintf(file
, "***attr%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
3338 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3339 switch (inst
->dst
.fixed_hw_reg
.nr
) {
3341 fprintf(file
, "null");
3343 case BRW_ARF_ADDRESS
:
3344 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
3346 case BRW_ARF_ACCUMULATOR
:
3347 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
3350 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3351 inst
->dst
.fixed_hw_reg
.subnr
);
3354 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3355 inst
->dst
.fixed_hw_reg
.subnr
);
3359 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
3361 if (inst
->dst
.fixed_hw_reg
.subnr
)
3362 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
3365 fprintf(file
, "???");
3368 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
3370 for (int i
= 0; i
< inst
->sources
; i
++) {
3371 if (inst
->src
[i
].negate
)
3373 if (inst
->src
[i
].abs
)
3375 switch (inst
->src
[i
].file
) {
3377 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
3378 if (inst
->src
[i
].width
!= dispatch_width
)
3379 fprintf(file
, "@%d", inst
->src
[i
].width
);
3380 if (alloc
.sizes
[inst
->src
[i
].reg
] != inst
->src
[i
].width
/ 8 ||
3381 inst
->src
[i
].subreg_offset
)
3382 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
3383 inst
->src
[i
].subreg_offset
);
3386 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
3389 fprintf(file
, "attr%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
3392 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
3393 if (inst
->src
[i
].reladdr
) {
3394 fprintf(file
, "+reladdr");
3395 } else if (inst
->src
[i
].subreg_offset
) {
3396 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
3397 inst
->src
[i
].subreg_offset
);
3401 fprintf(file
, "(null)");
3404 switch (inst
->src
[i
].type
) {
3405 case BRW_REGISTER_TYPE_F
:
3406 fprintf(file
, "%ff", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
3408 case BRW_REGISTER_TYPE_W
:
3409 case BRW_REGISTER_TYPE_D
:
3410 fprintf(file
, "%dd", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
3412 case BRW_REGISTER_TYPE_UW
:
3413 case BRW_REGISTER_TYPE_UD
:
3414 fprintf(file
, "%uu", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
3416 case BRW_REGISTER_TYPE_VF
:
3417 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
3418 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
3419 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
3420 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
3421 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
3424 fprintf(file
, "???");
3429 if (inst
->src
[i
].fixed_hw_reg
.negate
)
3431 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3433 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3434 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
3436 fprintf(file
, "null");
3438 case BRW_ARF_ADDRESS
:
3439 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3441 case BRW_ARF_ACCUMULATOR
:
3442 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3445 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3446 inst
->src
[i
].fixed_hw_reg
.subnr
);
3449 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3450 inst
->src
[i
].fixed_hw_reg
.subnr
);
3454 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
3456 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
3457 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3458 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3462 fprintf(file
, "???");
3465 if (inst
->src
[i
].abs
)
3468 if (inst
->src
[i
].file
!= IMM
) {
3469 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
3472 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
3473 fprintf(file
, ", ");
3478 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
3479 if (inst
->force_sechalf
)
3480 fprintf(file
, "2ndhalf ");
3482 fprintf(file
, "1sthalf ");
3485 fprintf(file
, "\n");
3489 * Possibly returns an instruction that set up @param reg.
3491 * Sometimes we want to take the result of some expression/variable
3492 * dereference tree and rewrite the instruction generating the result
3493 * of the tree. When processing the tree, we know that the
3494 * instructions generated are all writing temporaries that are dead
3495 * outside of this tree. So, if we have some instructions that write
3496 * a temporary, we're free to point that temp write somewhere else.
3498 * Note that this doesn't guarantee that the instruction generated
3499 * only reg -- it might be the size=4 destination of a texture instruction.
3502 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
3507 end
->is_partial_write() ||
3509 !reg
.equals(end
->dst
)) {
3517 fs_visitor::setup_payload_gen6()
3520 (prog
->InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
3521 unsigned barycentric_interp_modes
=
3522 (stage
== MESA_SHADER_FRAGMENT
) ?
3523 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
3525 assert(devinfo
->gen
>= 6);
3527 /* R0-1: masks, pixel X/Y coordinates. */
3528 payload
.num_regs
= 2;
3529 /* R2: only for 32-pixel dispatch.*/
3531 /* R3-26: barycentric interpolation coordinates. These appear in the
3532 * same order that they appear in the brw_wm_barycentric_interp_mode
3533 * enum. Each set of coordinates occupies 2 registers if dispatch width
3534 * == 8 and 4 registers if dispatch width == 16. Coordinates only
3535 * appear if they were enabled using the "Barycentric Interpolation
3536 * Mode" bits in WM_STATE.
3538 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
3539 if (barycentric_interp_modes
& (1 << i
)) {
3540 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
3541 payload
.num_regs
+= 2;
3542 if (dispatch_width
== 16) {
3543 payload
.num_regs
+= 2;
3548 /* R27: interpolated depth if uses source depth */
3550 payload
.source_depth_reg
= payload
.num_regs
;
3552 if (dispatch_width
== 16) {
3553 /* R28: interpolated depth if not SIMD8. */
3557 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
3559 payload
.source_w_reg
= payload
.num_regs
;
3561 if (dispatch_width
== 16) {
3562 /* R30: interpolated W if not SIMD8. */
3567 if (stage
== MESA_SHADER_FRAGMENT
) {
3568 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3569 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3570 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
3571 /* R31: MSAA position offsets. */
3572 if (prog_data
->uses_pos_offset
) {
3573 payload
.sample_pos_reg
= payload
.num_regs
;
3578 /* R32: MSAA input coverage mask */
3579 if (prog
->SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
3580 assert(devinfo
->gen
>= 7);
3581 payload
.sample_mask_in_reg
= payload
.num_regs
;
3583 if (dispatch_width
== 16) {
3584 /* R33: input coverage mask if not SIMD8. */
3589 /* R34-: bary for 32-pixel. */
3590 /* R58-59: interp W for 32-pixel. */
3592 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3593 source_depth_to_render_target
= true;
3598 fs_visitor::setup_vs_payload()
3600 /* R0: thread header, R1: urb handles */
3601 payload
.num_regs
= 2;
3605 fs_visitor::setup_cs_payload()
3607 assert(devinfo
->gen
>= 7);
3609 payload
.num_regs
= 1;
3613 fs_visitor::assign_binding_table_offsets()
3615 assert(stage
== MESA_SHADER_FRAGMENT
);
3616 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3617 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3618 uint32_t next_binding_table_offset
= 0;
3620 /* If there are no color regions, we still perform an FB write to a null
3621 * renderbuffer, which we place at surface index 0.
3623 prog_data
->binding_table
.render_target_start
= next_binding_table_offset
;
3624 next_binding_table_offset
+= MAX2(key
->nr_color_regions
, 1);
3626 assign_common_binding_table_offsets(next_binding_table_offset
);
3630 fs_visitor::calculate_register_pressure()
3632 invalidate_live_intervals();
3633 calculate_live_intervals();
3635 unsigned num_instructions
= 0;
3636 foreach_block(block
, cfg
)
3637 num_instructions
+= block
->instructions
.length();
3639 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
3641 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
3642 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
3643 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
3648 fs_visitor::optimize()
3650 /* bld is the common builder object pointing at the end of the program we
3651 * used to translate it into i965 IR. For the optimization and lowering
3652 * passes coming next, any code added after the end of the program without
3653 * having explicitly called fs_builder::at() clearly points at a mistake.
3654 * Ideally optimization passes wouldn't be part of the visitor so they
3655 * wouldn't have access to bld at all, but they do, so just in case some
3656 * pass forgets to ask for a location explicitly set it to NULL here to
3659 bld
= bld
.at(NULL
, NULL
);
3661 split_virtual_grfs();
3663 move_uniform_array_access_to_pull_constants();
3664 assign_constant_locations();
3665 demote_pull_constants();
3667 #define OPT(pass, args...) ({ \
3669 bool this_progress = pass(args); \
3671 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
3672 char filename[64]; \
3673 snprintf(filename, 64, "%s%d-%04d-%02d-%02d-" #pass, \
3674 stage_abbrev, dispatch_width, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
3676 backend_shader::dump_instructions(filename); \
3679 progress = progress || this_progress; \
3683 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
3685 snprintf(filename
, 64, "%s%d-%04d-00-start",
3686 stage_abbrev
, dispatch_width
,
3687 shader_prog
? shader_prog
->Name
: 0);
3689 backend_shader::dump_instructions(filename
);
3700 OPT(remove_duplicate_mrf_writes
);
3704 OPT(opt_copy_propagate
);
3705 OPT(opt_peephole_predicated_break
);
3706 OPT(opt_cmod_propagation
);
3707 OPT(dead_code_eliminate
);
3708 OPT(opt_peephole_sel
);
3709 OPT(dead_control_flow_eliminate
, this);
3710 OPT(opt_register_renaming
);
3711 OPT(opt_redundant_discard_jumps
);
3712 OPT(opt_saturate_propagation
);
3713 OPT(opt_zero_samples
);
3714 OPT(register_coalesce
);
3715 OPT(compute_to_mrf
);
3716 OPT(eliminate_find_live_channel
);
3718 OPT(compact_virtual_grfs
);
3723 OPT(opt_sampler_eot
);
3725 if (OPT(lower_load_payload
)) {
3726 split_virtual_grfs();
3727 OPT(register_coalesce
);
3728 OPT(compute_to_mrf
);
3729 OPT(dead_code_eliminate
);
3732 OPT(opt_combine_constants
);
3733 OPT(lower_integer_multiplication
);
3735 lower_uniform_pull_constant_loads();
3739 * Three source instruction must have a GRF/MRF destination register.
3740 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
3743 fs_visitor::fixup_3src_null_dest()
3745 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3746 if (inst
->is_3src() && inst
->dst
.is_null()) {
3747 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
3754 fs_visitor::allocate_registers()
3756 bool allocated_without_spills
;
3758 static const enum instruction_scheduler_mode pre_modes
[] = {
3760 SCHEDULE_PRE_NON_LIFO
,
3764 /* Try each scheduling heuristic to see if it can successfully register
3765 * allocate without spilling. They should be ordered by decreasing
3766 * performance but increasing likelihood of allocating.
3768 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
3769 schedule_instructions(pre_modes
[i
]);
3772 assign_regs_trivial();
3773 allocated_without_spills
= true;
3775 allocated_without_spills
= assign_regs(false);
3777 if (allocated_without_spills
)
3781 if (!allocated_without_spills
) {
3782 /* We assume that any spilling is worse than just dropping back to
3783 * SIMD8. There's probably actually some intermediate point where
3784 * SIMD16 with a couple of spills is still better.
3786 if (dispatch_width
== 16) {
3787 fail("Failure to register allocate. Reduce number of "
3788 "live scalar values to avoid this.");
3790 compiler
->shader_perf_log(log_data
,
3791 "%s shader triggered register spilling. "
3792 "Try reducing the number of live scalar "
3793 "values to improve performance.\n",
3797 /* Since we're out of heuristics, just go spill registers until we
3798 * get an allocation.
3800 while (!assign_regs(true)) {
3806 /* This must come after all optimization and register allocation, since
3807 * it inserts dead code that happens to have side effects, and it does
3808 * so based on the actual physical registers in use.
3810 insert_gen4_send_dependency_workarounds();
3815 if (!allocated_without_spills
)
3816 schedule_instructions(SCHEDULE_POST
);
3818 if (last_scratch
> 0)
3819 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
3823 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
3825 assert(stage
== MESA_SHADER_VERTEX
);
3827 assign_common_binding_table_offsets(0);
3830 if (shader_time_index
>= 0)
3831 emit_shader_time_begin();
3838 compute_clip_distance(clip_planes
);
3842 if (shader_time_index
>= 0)
3843 emit_shader_time_end();
3849 assign_curb_setup();
3850 assign_vs_urb_setup();
3852 fixup_3src_null_dest();
3853 allocate_registers();
3859 fs_visitor::run_fs(bool do_rep_send
)
3861 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3862 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
3864 assert(stage
== MESA_SHADER_FRAGMENT
);
3866 sanity_param_count
= prog
->Parameters
->NumParameters
;
3868 assign_binding_table_offsets();
3870 if (devinfo
->gen
>= 6)
3871 setup_payload_gen6();
3873 setup_payload_gen4();
3877 } else if (do_rep_send
) {
3878 assert(dispatch_width
== 16);
3879 emit_repclear_shader();
3881 if (shader_time_index
>= 0)
3882 emit_shader_time_begin();
3884 calculate_urb_setup();
3885 if (prog
->InputsRead
> 0) {
3886 if (devinfo
->gen
< 6)
3887 emit_interpolation_setup_gen4();
3889 emit_interpolation_setup_gen6();
3892 /* We handle discards by keeping track of the still-live pixels in f0.1.
3893 * Initialize it with the dispatched pixels.
3895 if (wm_prog_data
->uses_kill
) {
3896 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
3897 discard_init
->flag_subreg
= 1;
3900 /* Generate FS IR for main(). (the visitor only descends into
3901 * functions called "main").
3908 if (wm_prog_data
->uses_kill
)
3909 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
3911 if (wm_key
->alpha_test_func
)
3916 if (shader_time_index
>= 0)
3917 emit_shader_time_end();
3923 assign_curb_setup();
3926 fixup_3src_null_dest();
3927 allocate_registers();
3933 if (dispatch_width
== 8)
3934 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
3936 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
3938 /* If any state parameters were appended, then ParameterValues could have
3939 * been realloced, in which case the driver uniform storage set up by
3940 * _mesa_associate_uniform_storage() would point to freed memory. Make
3941 * sure that didn't happen.
3943 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
3949 fs_visitor::run_cs()
3951 assert(stage
== MESA_SHADER_COMPUTE
);
3954 sanity_param_count
= prog
->Parameters
->NumParameters
;
3956 assign_common_binding_table_offsets(0);
3960 if (shader_time_index
>= 0)
3961 emit_shader_time_begin();
3968 emit_cs_terminate();
3970 if (shader_time_index
>= 0)
3971 emit_shader_time_end();
3977 assign_curb_setup();
3979 fixup_3src_null_dest();
3980 allocate_registers();
3985 /* If any state parameters were appended, then ParameterValues could have
3986 * been realloced, in which case the driver uniform storage set up by
3987 * _mesa_associate_uniform_storage() would point to freed memory. Make
3988 * sure that didn't happen.
3990 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
3996 brw_wm_fs_emit(struct brw_context
*brw
,
3998 const struct brw_wm_prog_key
*key
,
3999 struct brw_wm_prog_data
*prog_data
,
4000 struct gl_fragment_program
*fp
,
4001 struct gl_shader_program
*prog
,
4002 unsigned *final_assembly_size
)
4004 bool start_busy
= false;
4005 double start_time
= 0;
4007 if (unlikely(brw
->perf_debug
)) {
4008 start_busy
= (brw
->batch
.last_bo
&&
4009 drm_intel_bo_busy(brw
->batch
.last_bo
));
4010 start_time
= get_time();
4013 struct brw_shader
*shader
= NULL
;
4015 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
4017 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
4018 brw_dump_ir("fragment", prog
, &shader
->base
, &fp
->Base
);
4020 int st_index8
= -1, st_index16
= -1;
4021 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
4022 st_index8
= brw_get_shader_time_index(brw
, prog
, &fp
->Base
, ST_FS8
);
4023 st_index16
= brw_get_shader_time_index(brw
, prog
, &fp
->Base
, ST_FS16
);
4026 /* Now the main event: Visit the shader IR and generate our FS IR for it.
4028 fs_visitor
v(brw
->intelScreen
->compiler
, brw
,
4029 mem_ctx
, MESA_SHADER_FRAGMENT
, key
, &prog_data
->base
,
4030 prog
, &fp
->Base
, 8, st_index8
);
4031 if (!v
.run_fs(false /* do_rep_send */)) {
4033 prog
->LinkStatus
= false;
4034 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
4037 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
4043 cfg_t
*simd16_cfg
= NULL
;
4044 fs_visitor
v2(brw
->intelScreen
->compiler
, brw
,
4045 mem_ctx
, MESA_SHADER_FRAGMENT
, key
, &prog_data
->base
,
4046 prog
, &fp
->Base
, 16, st_index16
);
4047 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || brw
->use_rep_send
)) {
4048 if (!v
.simd16_unsupported
) {
4049 /* Try a SIMD16 compile */
4050 v2
.import_uniforms(&v
);
4051 if (!v2
.run_fs(brw
->use_rep_send
)) {
4052 perf_debug("SIMD16 shader failed to compile: %s", v2
.fail_msg
);
4054 simd16_cfg
= v2
.cfg
;
4060 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || brw
->no_simd8
;
4061 if ((no_simd8
|| brw
->gen
< 5) && simd16_cfg
) {
4063 prog_data
->no_8
= true;
4066 prog_data
->no_8
= false;
4069 fs_generator
g(brw
->intelScreen
->compiler
, brw
,
4070 mem_ctx
, (void *) key
, &prog_data
->base
,
4071 &fp
->Base
, v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
4073 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
4076 name
= ralloc_asprintf(mem_ctx
, "%s fragment shader %d",
4077 prog
->Label
? prog
->Label
: "unnamed",
4080 name
= ralloc_asprintf(mem_ctx
, "fragment program %d", fp
->Base
.Id
);
4082 g
.enable_debug(name
);
4086 g
.generate_code(simd8_cfg
, 8);
4088 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
4090 if (unlikely(brw
->perf_debug
) && shader
) {
4091 if (shader
->compiled_once
)
4092 brw_wm_debug_recompile(brw
, prog
, key
);
4093 shader
->compiled_once
= true;
4095 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
4096 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
4097 (get_time() - start_time
) * 1000);
4101 return g
.get_assembly(final_assembly_size
);
4105 brw_fs_precompile(struct gl_context
*ctx
,
4106 struct gl_shader_program
*shader_prog
,
4107 struct gl_program
*prog
)
4109 struct brw_context
*brw
= brw_context(ctx
);
4110 struct brw_wm_prog_key key
;
4112 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*) prog
;
4113 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
4114 bool program_uses_dfdy
= fp
->UsesDFdy
;
4116 memset(&key
, 0, sizeof(key
));
4120 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
4122 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
4123 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
4125 /* Just assume depth testing. */
4126 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
4127 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
4130 if (brw
->gen
< 6 || _mesa_bitcount_64(fp
->Base
.InputsRead
&
4131 BRW_FS_VARYING_INPUT_MASK
) > 16)
4132 key
.input_slots_valid
= fp
->Base
.InputsRead
| VARYING_BIT_POS
;
4134 brw_setup_tex_for_precompile(brw
, &key
.tex
, &fp
->Base
);
4136 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
) {
4137 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
4140 key
.nr_color_regions
= _mesa_bitcount_64(fp
->Base
.OutputsWritten
&
4141 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
4142 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
)));
4144 if ((fp
->Base
.InputsRead
& VARYING_BIT_POS
) || program_uses_dfdy
) {
4145 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
) ||
4146 key
.nr_color_regions
> 1;
4149 key
.program_string_id
= bfp
->id
;
4151 uint32_t old_prog_offset
= brw
->wm
.base
.prog_offset
;
4152 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
4154 bool success
= brw_codegen_wm_prog(brw
, shader_prog
, bfp
, &key
);
4156 brw
->wm
.base
.prog_offset
= old_prog_offset
;
4157 brw
->wm
.prog_data
= old_prog_data
;
4163 brw_setup_tex_for_precompile(struct brw_context
*brw
,
4164 struct brw_sampler_prog_key_data
*tex
,
4165 struct gl_program
*prog
)
4167 const bool has_shader_channel_select
= brw
->is_haswell
|| brw
->gen
>= 8;
4168 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
4169 for (unsigned i
= 0; i
< sampler_count
; i
++) {
4170 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
4171 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
4173 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
4175 /* Color sampler: assume no swizzling. */
4176 tex
->swizzles
[i
] = SWIZZLE_XYZW
;