i965: Handle all_equal/any_nequal in the new FS.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 extern "C" {
29
30 #include <sys/types.h>
31
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_optimize.h"
37 #include "program/hash_table.h"
38 #include "brw_context.h"
39 #include "brw_eu.h"
40 #include "brw_wm.h"
41 #include "talloc.h"
42 }
43 #include "../glsl/glsl_types.h"
44 #include "../glsl/ir_optimization.h"
45 #include "../glsl/ir_print_visitor.h"
46
47 enum register_file {
48 ARF = BRW_ARCHITECTURE_REGISTER_FILE,
49 GRF = BRW_GENERAL_REGISTER_FILE,
50 MRF = BRW_MESSAGE_REGISTER_FILE,
51 IMM = BRW_IMMEDIATE_VALUE,
52 FIXED_HW_REG, /* a struct brw_reg */
53 UNIFORM, /* prog_data->params[hw_reg] */
54 BAD_FILE
55 };
56
57 enum fs_opcodes {
58 FS_OPCODE_FB_WRITE = 256,
59 FS_OPCODE_RCP,
60 FS_OPCODE_RSQ,
61 FS_OPCODE_SQRT,
62 FS_OPCODE_EXP2,
63 FS_OPCODE_LOG2,
64 FS_OPCODE_POW,
65 FS_OPCODE_SIN,
66 FS_OPCODE_COS,
67 FS_OPCODE_DDX,
68 FS_OPCODE_DDY,
69 FS_OPCODE_LINTERP,
70 FS_OPCODE_TEX,
71 FS_OPCODE_TXB,
72 FS_OPCODE_TXL,
73 FS_OPCODE_DISCARD,
74 };
75
76 static int using_new_fs = -1;
77
78 struct gl_shader *
79 brw_new_shader(GLcontext *ctx, GLuint name, GLuint type)
80 {
81 struct brw_shader *shader;
82
83 shader = talloc_zero(NULL, struct brw_shader);
84 if (shader) {
85 shader->base.Type = type;
86 shader->base.Name = name;
87 _mesa_init_shader(ctx, &shader->base);
88 }
89
90 return &shader->base;
91 }
92
93 struct gl_shader_program *
94 brw_new_shader_program(GLcontext *ctx, GLuint name)
95 {
96 struct brw_shader_program *prog;
97 prog = talloc_zero(NULL, struct brw_shader_program);
98 if (prog) {
99 prog->base.Name = name;
100 _mesa_init_shader_program(ctx, &prog->base);
101 }
102 return &prog->base;
103 }
104
105 GLboolean
106 brw_compile_shader(GLcontext *ctx, struct gl_shader *shader)
107 {
108 if (!_mesa_ir_compile_shader(ctx, shader))
109 return GL_FALSE;
110
111 return GL_TRUE;
112 }
113
114 GLboolean
115 brw_link_shader(GLcontext *ctx, struct gl_shader_program *prog)
116 {
117 if (using_new_fs == -1)
118 using_new_fs = getenv("INTEL_NEW_FS") != NULL;
119
120 for (unsigned i = 0; i < prog->_NumLinkedShaders; i++) {
121 struct brw_shader *shader = (struct brw_shader *)prog->_LinkedShaders[i];
122
123 if (using_new_fs && shader->base.Type == GL_FRAGMENT_SHADER) {
124 void *mem_ctx = talloc_new(NULL);
125 bool progress;
126
127 if (shader->ir)
128 talloc_free(shader->ir);
129 shader->ir = new(shader) exec_list;
130 clone_ir_list(mem_ctx, shader->ir, shader->base.ir);
131
132 do_mat_op_to_vec(shader->ir);
133 do_mod_to_fract(shader->ir);
134 do_div_to_mul_rcp(shader->ir);
135 do_sub_to_add_neg(shader->ir);
136 do_explog_to_explog2(shader->ir);
137
138 brw_do_channel_expressions(shader->ir);
139 brw_do_vector_splitting(shader->ir);
140
141 do {
142 progress = false;
143
144 progress = do_common_optimization(shader->ir, true, 32) || progress;
145 } while (progress);
146
147 validate_ir_tree(shader->ir);
148
149 reparent_ir(shader->ir, shader->ir);
150 talloc_free(mem_ctx);
151 }
152 }
153
154 if (!_mesa_ir_link_shader(ctx, prog))
155 return GL_FALSE;
156
157 return GL_TRUE;
158 }
159
160 static int
161 type_size(const struct glsl_type *type)
162 {
163 unsigned int size, i;
164
165 switch (type->base_type) {
166 case GLSL_TYPE_UINT:
167 case GLSL_TYPE_INT:
168 case GLSL_TYPE_FLOAT:
169 case GLSL_TYPE_BOOL:
170 return type->components();
171 case GLSL_TYPE_ARRAY:
172 /* FINISHME: uniform/varying arrays. */
173 return type_size(type->fields.array) * type->length;
174 case GLSL_TYPE_STRUCT:
175 size = 0;
176 for (i = 0; i < type->length; i++) {
177 size += type_size(type->fields.structure[i].type);
178 }
179 return size;
180 case GLSL_TYPE_SAMPLER:
181 /* Samplers take up no register space, since they're baked in at
182 * link time.
183 */
184 return 0;
185 default:
186 assert(!"not reached");
187 return 0;
188 }
189 }
190
191 class fs_reg {
192 public:
193 /* Callers of this talloc-based new need not call delete. It's
194 * easier to just talloc_free 'ctx' (or any of its ancestors). */
195 static void* operator new(size_t size, void *ctx)
196 {
197 void *node;
198
199 node = talloc_size(ctx, size);
200 assert(node != NULL);
201
202 return node;
203 }
204
205 void init()
206 {
207 this->reg = 0;
208 this->reg_offset = 0;
209 this->negate = 0;
210 this->abs = 0;
211 this->hw_reg = -1;
212 }
213
214 /** Generic unset register constructor. */
215 fs_reg()
216 {
217 init();
218 this->file = BAD_FILE;
219 }
220
221 /** Immediate value constructor. */
222 fs_reg(float f)
223 {
224 init();
225 this->file = IMM;
226 this->type = BRW_REGISTER_TYPE_F;
227 this->imm.f = f;
228 }
229
230 /** Immediate value constructor. */
231 fs_reg(int32_t i)
232 {
233 init();
234 this->file = IMM;
235 this->type = BRW_REGISTER_TYPE_D;
236 this->imm.i = i;
237 }
238
239 /** Immediate value constructor. */
240 fs_reg(uint32_t u)
241 {
242 init();
243 this->file = IMM;
244 this->type = BRW_REGISTER_TYPE_UD;
245 this->imm.u = u;
246 }
247
248 /** Fixed brw_reg Immediate value constructor. */
249 fs_reg(struct brw_reg fixed_hw_reg)
250 {
251 init();
252 this->file = FIXED_HW_REG;
253 this->fixed_hw_reg = fixed_hw_reg;
254 this->type = fixed_hw_reg.type;
255 }
256
257 fs_reg(enum register_file file, int hw_reg);
258 fs_reg(class fs_visitor *v, const struct glsl_type *type);
259
260 /** Register file: ARF, GRF, MRF, IMM. */
261 enum register_file file;
262 /** Abstract register number. 0 = fixed hw reg */
263 int reg;
264 /** Offset within the abstract register. */
265 int reg_offset;
266 /** HW register number. Generally unset until register allocation. */
267 int hw_reg;
268 /** Register type. BRW_REGISTER_TYPE_* */
269 int type;
270 bool negate;
271 bool abs;
272 struct brw_reg fixed_hw_reg;
273
274 /** Value for file == BRW_IMMMEDIATE_FILE */
275 union {
276 int32_t i;
277 uint32_t u;
278 float f;
279 } imm;
280 };
281
282 static const fs_reg reg_undef;
283 static const fs_reg reg_null(ARF, BRW_ARF_NULL);
284
285 class fs_inst : public exec_node {
286 public:
287 /* Callers of this talloc-based new need not call delete. It's
288 * easier to just talloc_free 'ctx' (or any of its ancestors). */
289 static void* operator new(size_t size, void *ctx)
290 {
291 void *node;
292
293 node = talloc_zero_size(ctx, size);
294 assert(node != NULL);
295
296 return node;
297 }
298
299 void init()
300 {
301 this->opcode = BRW_OPCODE_NOP;
302 this->saturate = false;
303 this->conditional_mod = BRW_CONDITIONAL_NONE;
304 this->predicated = false;
305 this->sampler = 0;
306 this->shadow_compare = false;
307 }
308
309 fs_inst()
310 {
311 init();
312 }
313
314 fs_inst(int opcode)
315 {
316 init();
317 this->opcode = opcode;
318 }
319
320 fs_inst(int opcode, fs_reg dst, fs_reg src0)
321 {
322 init();
323 this->opcode = opcode;
324 this->dst = dst;
325 this->src[0] = src0;
326 }
327
328 fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1)
329 {
330 init();
331 this->opcode = opcode;
332 this->dst = dst;
333 this->src[0] = src0;
334 this->src[1] = src1;
335 }
336
337 fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2)
338 {
339 init();
340 this->opcode = opcode;
341 this->dst = dst;
342 this->src[0] = src0;
343 this->src[1] = src1;
344 this->src[2] = src2;
345 }
346
347 int opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
348 fs_reg dst;
349 fs_reg src[3];
350 bool saturate;
351 bool predicated;
352 int conditional_mod; /**< BRW_CONDITIONAL_* */
353
354 int mlen; /** SEND message length */
355 int sampler;
356 bool shadow_compare;
357
358 /** @{
359 * Annotation for the generated IR. One of the two can be set.
360 */
361 ir_instruction *ir;
362 const char *annotation;
363 /** @} */
364 };
365
366 class fs_visitor : public ir_visitor
367 {
368 public:
369
370 fs_visitor(struct brw_wm_compile *c, struct brw_shader *shader)
371 {
372 this->c = c;
373 this->p = &c->func;
374 this->brw = p->brw;
375 this->intel = &brw->intel;
376 this->ctx = &intel->ctx;
377 this->mem_ctx = talloc_new(NULL);
378 this->shader = shader;
379 this->fail = false;
380 this->next_abstract_grf = 1;
381 this->variable_ht = hash_table_ctor(0,
382 hash_table_pointer_hash,
383 hash_table_pointer_compare);
384
385 this->frag_color = NULL;
386 this->frag_data = NULL;
387 this->frag_depth = NULL;
388 this->first_non_payload_grf = 0;
389
390 this->current_annotation = NULL;
391 this->annotation_string = NULL;
392 this->annotation_ir = NULL;
393 }
394 ~fs_visitor()
395 {
396 talloc_free(this->mem_ctx);
397 hash_table_dtor(this->variable_ht);
398 }
399
400 fs_reg *variable_storage(ir_variable *var);
401
402 void visit(ir_variable *ir);
403 void visit(ir_assignment *ir);
404 void visit(ir_dereference_variable *ir);
405 void visit(ir_dereference_record *ir);
406 void visit(ir_dereference_array *ir);
407 void visit(ir_expression *ir);
408 void visit(ir_texture *ir);
409 void visit(ir_if *ir);
410 void visit(ir_constant *ir);
411 void visit(ir_swizzle *ir);
412 void visit(ir_return *ir);
413 void visit(ir_loop *ir);
414 void visit(ir_loop_jump *ir);
415 void visit(ir_discard *ir);
416 void visit(ir_call *ir);
417 void visit(ir_function *ir);
418 void visit(ir_function_signature *ir);
419
420 fs_inst *emit(fs_inst inst);
421 void assign_curb_setup();
422 void assign_urb_setup();
423 void assign_regs();
424 void generate_code();
425 void generate_fb_write(fs_inst *inst);
426 void generate_linterp(fs_inst *inst, struct brw_reg dst,
427 struct brw_reg *src);
428 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
429 void generate_math(fs_inst *inst, struct brw_reg dst, struct brw_reg *src);
430 void generate_discard(fs_inst *inst);
431
432 void emit_dummy_fs();
433 void emit_interpolation();
434 void emit_pinterp(int location);
435 void emit_fb_writes();
436
437 struct brw_reg interp_reg(int location, int channel);
438
439 struct brw_context *brw;
440 struct intel_context *intel;
441 GLcontext *ctx;
442 struct brw_wm_compile *c;
443 struct brw_compile *p;
444 struct brw_shader *shader;
445 void *mem_ctx;
446 exec_list instructions;
447 int next_abstract_grf;
448 struct hash_table *variable_ht;
449 ir_variable *frag_color, *frag_data, *frag_depth;
450 int first_non_payload_grf;
451
452 /** @{ debug annotation info */
453 const char *current_annotation;
454 ir_instruction *base_ir;
455 const char **annotation_string;
456 ir_instruction **annotation_ir;
457 /** @} */
458
459 bool fail;
460
461 /* Result of last visit() method. */
462 fs_reg result;
463
464 fs_reg pixel_x;
465 fs_reg pixel_y;
466 fs_reg pixel_w;
467 fs_reg delta_x;
468 fs_reg delta_y;
469 fs_reg interp_attrs[64];
470
471 int grf_used;
472
473 };
474
475 /** Fixed HW reg constructor. */
476 fs_reg::fs_reg(enum register_file file, int hw_reg)
477 {
478 init();
479 this->file = file;
480 this->hw_reg = hw_reg;
481 this->type = BRW_REGISTER_TYPE_F;
482 }
483
484 /** Automatic reg constructor. */
485 fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type)
486 {
487 init();
488
489 this->file = GRF;
490 this->reg = v->next_abstract_grf;
491 this->reg_offset = 0;
492 v->next_abstract_grf += type_size(type);
493
494 switch (type->base_type) {
495 case GLSL_TYPE_FLOAT:
496 this->type = BRW_REGISTER_TYPE_F;
497 break;
498 case GLSL_TYPE_INT:
499 case GLSL_TYPE_BOOL:
500 this->type = BRW_REGISTER_TYPE_D;
501 break;
502 case GLSL_TYPE_UINT:
503 this->type = BRW_REGISTER_TYPE_UD;
504 break;
505 default:
506 assert(!"not reached");
507 this->type = BRW_REGISTER_TYPE_F;
508 break;
509 }
510 }
511
512 fs_reg *
513 fs_visitor::variable_storage(ir_variable *var)
514 {
515 return (fs_reg *)hash_table_find(this->variable_ht, var);
516 }
517
518 void
519 fs_visitor::visit(ir_variable *ir)
520 {
521 fs_reg *reg = NULL;
522
523 if (strcmp(ir->name, "gl_FragColor") == 0) {
524 this->frag_color = ir;
525 } else if (strcmp(ir->name, "gl_FragData") == 0) {
526 this->frag_data = ir;
527 } else if (strcmp(ir->name, "gl_FragDepth") == 0) {
528 this->frag_depth = ir;
529 assert(!"FINISHME: this hangs currently.");
530 }
531
532 if (ir->mode == ir_var_in) {
533 reg = &this->interp_attrs[ir->location];
534 }
535
536 if (ir->mode == ir_var_uniform) {
537 const float *vec_values;
538 int param_index = c->prog_data.nr_params;
539
540 /* FINISHME: This is wildly incomplete. */
541 assert(ir->type->is_scalar() || ir->type->is_vector() ||
542 ir->type->is_sampler());
543
544 const struct gl_program *fp = &this->brw->fragment_program->Base;
545 /* Our support for uniforms is piggy-backed on the struct
546 * gl_fragment_program, because that's where the values actually
547 * get stored, rather than in some global gl_shader_program uniform
548 * store.
549 */
550 vec_values = fp->Parameters->ParameterValues[ir->location];
551 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
552 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[i];
553 }
554
555 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index);
556 }
557
558 if (!reg)
559 reg = new(this->mem_ctx) fs_reg(this, ir->type);
560
561 hash_table_insert(this->variable_ht, reg, ir);
562 }
563
564 void
565 fs_visitor::visit(ir_dereference_variable *ir)
566 {
567 fs_reg *reg = variable_storage(ir->var);
568 this->result = *reg;
569 }
570
571 void
572 fs_visitor::visit(ir_dereference_record *ir)
573 {
574 assert(!"FINISHME");
575 }
576
577 void
578 fs_visitor::visit(ir_dereference_array *ir)
579 {
580 ir_constant *index;
581 int element_size;
582
583 ir->array->accept(this);
584 index = ir->array_index->as_constant();
585
586 if (ir->type->is_matrix()) {
587 element_size = ir->type->vector_elements;
588 } else {
589 element_size = type_size(ir->type);
590 }
591
592 if (index) {
593 assert(this->result.file == UNIFORM ||
594 (this->result.file == GRF &&
595 this->result.reg != 0));
596 this->result.reg_offset += index->value.i[0] * element_size;
597 } else {
598 assert(!"FINISHME: non-constant matrix column");
599 }
600 }
601
602 void
603 fs_visitor::visit(ir_expression *ir)
604 {
605 unsigned int operand;
606 fs_reg op[2], temp;
607 fs_reg result;
608 fs_inst *inst;
609
610 for (operand = 0; operand < ir->get_num_operands(); operand++) {
611 ir->operands[operand]->accept(this);
612 if (this->result.file == BAD_FILE) {
613 ir_print_visitor v;
614 printf("Failed to get tree for expression operand:\n");
615 ir->operands[operand]->accept(&v);
616 this->fail = true;
617 }
618 op[operand] = this->result;
619
620 /* Matrix expression operands should have been broken down to vector
621 * operations already.
622 */
623 assert(!ir->operands[operand]->type->is_matrix());
624 /* And then those vector operands should have been broken down to scalar.
625 */
626 assert(!ir->operands[operand]->type->is_vector());
627 }
628
629 /* Storage for our result. If our result goes into an assignment, it will
630 * just get copy-propagated out, so no worries.
631 */
632 this->result = fs_reg(this, ir->type);
633
634 switch (ir->operation) {
635 case ir_unop_logic_not:
636 emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], fs_reg(-1)));
637 break;
638 case ir_unop_neg:
639 op[0].negate = ~op[0].negate;
640 this->result = op[0];
641 break;
642 case ir_unop_abs:
643 op[0].abs = true;
644 this->result = op[0];
645 break;
646 case ir_unop_sign:
647 temp = fs_reg(this, ir->type);
648
649 emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)));
650
651 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, op[0], fs_reg(0.0f)));
652 inst->conditional_mod = BRW_CONDITIONAL_G;
653 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)));
654 inst->predicated = true;
655
656 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, op[0], fs_reg(0.0f)));
657 inst->conditional_mod = BRW_CONDITIONAL_L;
658 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)));
659 inst->predicated = true;
660
661 break;
662 case ir_unop_rcp:
663 emit(fs_inst(FS_OPCODE_RCP, this->result, op[0]));
664 break;
665
666 case ir_unop_exp2:
667 emit(fs_inst(FS_OPCODE_EXP2, this->result, op[0]));
668 break;
669 case ir_unop_log2:
670 emit(fs_inst(FS_OPCODE_LOG2, this->result, op[0]));
671 break;
672 case ir_unop_exp:
673 case ir_unop_log:
674 assert(!"not reached: should be handled by ir_explog_to_explog2");
675 break;
676 case ir_unop_sin:
677 emit(fs_inst(FS_OPCODE_SIN, this->result, op[0]));
678 break;
679 case ir_unop_cos:
680 emit(fs_inst(FS_OPCODE_COS, this->result, op[0]));
681 break;
682
683 case ir_unop_dFdx:
684 emit(fs_inst(FS_OPCODE_DDX, this->result, op[0]));
685 break;
686 case ir_unop_dFdy:
687 emit(fs_inst(FS_OPCODE_DDY, this->result, op[0]));
688 break;
689
690 case ir_binop_add:
691 emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], op[1]));
692 break;
693 case ir_binop_sub:
694 assert(!"not reached: should be handled by ir_sub_to_add_neg");
695 break;
696
697 case ir_binop_mul:
698 emit(fs_inst(BRW_OPCODE_MUL, this->result, op[0], op[1]));
699 break;
700 case ir_binop_div:
701 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
702 break;
703 case ir_binop_mod:
704 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
705 break;
706
707 case ir_binop_less:
708 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
709 inst->conditional_mod = BRW_CONDITIONAL_L;
710 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
711 break;
712 case ir_binop_greater:
713 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
714 inst->conditional_mod = BRW_CONDITIONAL_G;
715 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
716 break;
717 case ir_binop_lequal:
718 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
719 inst->conditional_mod = BRW_CONDITIONAL_LE;
720 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
721 break;
722 case ir_binop_gequal:
723 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
724 inst->conditional_mod = BRW_CONDITIONAL_GE;
725 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
726 break;
727 case ir_binop_equal:
728 case ir_binop_all_equal: /* same as nequal for scalars */
729 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
730 inst->conditional_mod = BRW_CONDITIONAL_Z;
731 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
732 break;
733 case ir_binop_nequal:
734 case ir_binop_any_nequal: /* same as nequal for scalars */
735 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
736 inst->conditional_mod = BRW_CONDITIONAL_NZ;
737 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
738 break;
739
740 case ir_binop_logic_xor:
741 emit(fs_inst(BRW_OPCODE_XOR, this->result, op[0], op[1]));
742 break;
743
744 case ir_binop_logic_or:
745 emit(fs_inst(BRW_OPCODE_OR, this->result, op[0], op[1]));
746 break;
747
748 case ir_binop_logic_and:
749 emit(fs_inst(BRW_OPCODE_AND, this->result, op[0], op[1]));
750 break;
751
752 case ir_binop_dot:
753 case ir_binop_cross:
754 case ir_unop_any:
755 assert(!"not reached: should be handled by brw_fs_channel_expressions");
756 break;
757
758 case ir_unop_noise:
759 assert(!"not reached: should be handled by lower_noise");
760 break;
761
762 case ir_unop_sqrt:
763 emit(fs_inst(FS_OPCODE_SQRT, this->result, op[0]));
764 break;
765
766 case ir_unop_rsq:
767 emit(fs_inst(FS_OPCODE_RSQ, this->result, op[0]));
768 break;
769
770 case ir_unop_i2f:
771 case ir_unop_b2f:
772 case ir_unop_b2i:
773 emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0]));
774 break;
775 case ir_unop_f2i:
776 emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0]));
777 break;
778 case ir_unop_f2b:
779 case ir_unop_i2b:
780 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], fs_reg(0.0f)));
781 inst->conditional_mod = BRW_CONDITIONAL_NZ;
782
783 case ir_unop_trunc:
784 emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
785 break;
786 case ir_unop_ceil:
787 op[0].negate = ~op[0].negate;
788 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
789 this->result.negate = true;
790 break;
791 case ir_unop_floor:
792 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
793 break;
794 case ir_unop_fract:
795 inst = emit(fs_inst(BRW_OPCODE_FRC, this->result, op[0]));
796 break;
797
798 case ir_binop_min:
799 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
800 inst->conditional_mod = BRW_CONDITIONAL_L;
801
802 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1]));
803 inst->predicated = true;
804 break;
805 case ir_binop_max:
806 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
807 inst->conditional_mod = BRW_CONDITIONAL_G;
808
809 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1]));
810 inst->predicated = true;
811 break;
812
813 case ir_binop_pow:
814 inst = emit(fs_inst(FS_OPCODE_POW, this->result, op[0], op[1]));
815 break;
816
817 case ir_unop_bit_not:
818 case ir_unop_u2f:
819 case ir_binop_lshift:
820 case ir_binop_rshift:
821 case ir_binop_bit_and:
822 case ir_binop_bit_xor:
823 case ir_binop_bit_or:
824 assert(!"GLSL 1.30 features unsupported");
825 break;
826 }
827 }
828
829 void
830 fs_visitor::visit(ir_assignment *ir)
831 {
832 struct fs_reg l, r;
833 int i;
834 int write_mask;
835 fs_inst *inst;
836
837 /* FINISHME: arrays on the lhs */
838 ir->lhs->accept(this);
839 l = this->result;
840
841 ir->rhs->accept(this);
842 r = this->result;
843
844 /* FINISHME: This should really set to the correct maximal writemask for each
845 * FINISHME: component written (in the loops below). This case can only
846 * FINISHME: occur for matrices, arrays, and structures.
847 */
848 if (ir->write_mask == 0) {
849 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
850 write_mask = WRITEMASK_XYZW;
851 } else {
852 assert(ir->lhs->type->is_vector() || ir->lhs->type->is_scalar());
853 write_mask = ir->write_mask;
854 }
855
856 assert(l.file != BAD_FILE);
857 assert(r.file != BAD_FILE);
858
859 if (ir->condition) {
860 /* Get the condition bool into the predicate. */
861 ir->condition->accept(this);
862 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, fs_reg(0)));
863 inst->conditional_mod = BRW_CONDITIONAL_NZ;
864 }
865
866 for (i = 0; i < type_size(ir->lhs->type); i++) {
867 if (i >= 4 || (write_mask & (1 << i))) {
868 inst = emit(fs_inst(BRW_OPCODE_MOV, l, r));
869 if (ir->condition)
870 inst->predicated = true;
871 r.reg_offset++;
872 }
873 l.reg_offset++;
874 }
875 }
876
877 void
878 fs_visitor::visit(ir_texture *ir)
879 {
880 int base_mrf = 2;
881 fs_inst *inst = NULL;
882 unsigned int mlen = 0;
883
884 ir->coordinate->accept(this);
885 fs_reg coordinate = this->result;
886
887 if (ir->projector) {
888 fs_reg inv_proj = fs_reg(this, glsl_type::float_type);
889
890 ir->projector->accept(this);
891 emit(fs_inst(FS_OPCODE_RCP, inv_proj, this->result));
892
893 fs_reg proj_coordinate = fs_reg(this, ir->coordinate->type);
894 for (unsigned int i = 0; i < ir->coordinate->type->vector_elements; i++) {
895 emit(fs_inst(BRW_OPCODE_MUL, proj_coordinate, coordinate, inv_proj));
896 coordinate.reg_offset++;
897 proj_coordinate.reg_offset++;
898 }
899 proj_coordinate.reg_offset = 0;
900
901 coordinate = proj_coordinate;
902 }
903
904 for (mlen = 0; mlen < ir->coordinate->type->vector_elements; mlen++) {
905 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate));
906 coordinate.reg_offset++;
907 }
908
909 /* Pre-Ironlake, the 8-wide sampler always took u,v,r. */
910 if (intel->gen < 5)
911 mlen = 3;
912
913 if (ir->shadow_comparitor) {
914 /* For shadow comparisons, we have to supply u,v,r. */
915 mlen = 3;
916
917 ir->shadow_comparitor->accept(this);
918 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
919 mlen++;
920 }
921
922 /* Do we ever want to handle writemasking on texture samples? Is it
923 * performance relevant?
924 */
925 fs_reg dst = fs_reg(this, glsl_type::vec4_type);
926
927 switch (ir->op) {
928 case ir_tex:
929 inst = emit(fs_inst(FS_OPCODE_TEX, dst, fs_reg(MRF, base_mrf)));
930 break;
931 case ir_txb:
932 ir->lod_info.bias->accept(this);
933 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
934 mlen++;
935
936 inst = emit(fs_inst(FS_OPCODE_TXB, dst, fs_reg(MRF, base_mrf)));
937 break;
938 case ir_txl:
939 ir->lod_info.lod->accept(this);
940 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
941 mlen++;
942
943 inst = emit(fs_inst(FS_OPCODE_TXL, dst, fs_reg(MRF, base_mrf)));
944 break;
945 case ir_txd:
946 case ir_txf:
947 assert(!"GLSL 1.30 features unsupported");
948 break;
949 }
950
951 this->result = dst;
952
953 if (ir->shadow_comparitor)
954 inst->shadow_compare = true;
955 inst->mlen = mlen;
956 }
957
958 void
959 fs_visitor::visit(ir_swizzle *ir)
960 {
961 ir->val->accept(this);
962 fs_reg val = this->result;
963
964 fs_reg result = fs_reg(this, ir->type);
965 this->result = result;
966
967 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
968 fs_reg channel = val;
969 int swiz = 0;
970
971 switch (i) {
972 case 0:
973 swiz = ir->mask.x;
974 break;
975 case 1:
976 swiz = ir->mask.y;
977 break;
978 case 2:
979 swiz = ir->mask.z;
980 break;
981 case 3:
982 swiz = ir->mask.w;
983 break;
984 }
985
986 channel.reg_offset += swiz;
987 emit(fs_inst(BRW_OPCODE_MOV, result, channel));
988 result.reg_offset++;
989 }
990 }
991
992 void
993 fs_visitor::visit(ir_discard *ir)
994 {
995 assert(ir->condition == NULL); /* FINISHME */
996
997 emit(fs_inst(FS_OPCODE_DISCARD));
998 }
999
1000 void
1001 fs_visitor::visit(ir_constant *ir)
1002 {
1003 fs_reg reg(this, ir->type);
1004 this->result = reg;
1005
1006 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1007 switch (ir->type->base_type) {
1008 case GLSL_TYPE_FLOAT:
1009 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.f[i])));
1010 break;
1011 case GLSL_TYPE_UINT:
1012 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.u[i])));
1013 break;
1014 case GLSL_TYPE_INT:
1015 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.i[i])));
1016 break;
1017 case GLSL_TYPE_BOOL:
1018 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg((int)ir->value.b[i])));
1019 break;
1020 default:
1021 assert(!"Non-float/uint/int/bool constant");
1022 }
1023 reg.reg_offset++;
1024 }
1025 }
1026
1027 void
1028 fs_visitor::visit(ir_if *ir)
1029 {
1030 fs_inst *inst;
1031
1032 /* Don't point the annotation at the if statement, because then it plus
1033 * the then and else blocks get printed.
1034 */
1035 this->base_ir = ir->condition;
1036
1037 /* Generate the condition into the condition code. */
1038 ir->condition->accept(this);
1039 inst = emit(fs_inst(BRW_OPCODE_MOV, fs_reg(brw_null_reg()), this->result));
1040 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1041
1042 inst = emit(fs_inst(BRW_OPCODE_IF));
1043 inst->predicated = true;
1044
1045 foreach_iter(exec_list_iterator, iter, ir->then_instructions) {
1046 ir_instruction *ir = (ir_instruction *)iter.get();
1047 this->base_ir = ir;
1048
1049 ir->accept(this);
1050 }
1051
1052 if (!ir->else_instructions.is_empty()) {
1053 emit(fs_inst(BRW_OPCODE_ELSE));
1054
1055 foreach_iter(exec_list_iterator, iter, ir->else_instructions) {
1056 ir_instruction *ir = (ir_instruction *)iter.get();
1057 this->base_ir = ir;
1058
1059 ir->accept(this);
1060 }
1061 }
1062
1063 emit(fs_inst(BRW_OPCODE_ENDIF));
1064 }
1065
1066 void
1067 fs_visitor::visit(ir_loop *ir)
1068 {
1069 assert(!ir->from);
1070 assert(!ir->to);
1071 assert(!ir->increment);
1072 assert(!ir->counter);
1073
1074 emit(fs_inst(BRW_OPCODE_DO));
1075
1076 /* Start a safety counter. If the user messed up their loop
1077 * counting, we don't want to hang the GPU.
1078 */
1079 fs_reg max_iter = fs_reg(this, glsl_type::int_type);
1080 emit(fs_inst(BRW_OPCODE_MOV, max_iter, fs_reg(10000)));
1081
1082 foreach_iter(exec_list_iterator, iter, ir->body_instructions) {
1083 ir_instruction *ir = (ir_instruction *)iter.get();
1084 fs_inst *inst;
1085
1086 this->base_ir = ir;
1087 ir->accept(this);
1088
1089 /* Check the maximum loop iters counter. */
1090 inst = emit(fs_inst(BRW_OPCODE_ADD, max_iter, max_iter, fs_reg(-1)));
1091 inst->conditional_mod = BRW_CONDITIONAL_Z;
1092
1093 inst = emit(fs_inst(BRW_OPCODE_BREAK));
1094 inst->predicated = true;
1095 }
1096
1097 emit(fs_inst(BRW_OPCODE_WHILE));
1098 }
1099
1100 void
1101 fs_visitor::visit(ir_loop_jump *ir)
1102 {
1103 switch (ir->mode) {
1104 case ir_loop_jump::jump_break:
1105 emit(fs_inst(BRW_OPCODE_BREAK));
1106 break;
1107 case ir_loop_jump::jump_continue:
1108 emit(fs_inst(BRW_OPCODE_CONTINUE));
1109 break;
1110 }
1111 }
1112
1113 void
1114 fs_visitor::visit(ir_call *ir)
1115 {
1116 assert(!"FINISHME");
1117 }
1118
1119 void
1120 fs_visitor::visit(ir_return *ir)
1121 {
1122 assert(!"FINISHME");
1123 }
1124
1125 void
1126 fs_visitor::visit(ir_function *ir)
1127 {
1128 /* Ignore function bodies other than main() -- we shouldn't see calls to
1129 * them since they should all be inlined before we get to ir_to_mesa.
1130 */
1131 if (strcmp(ir->name, "main") == 0) {
1132 const ir_function_signature *sig;
1133 exec_list empty;
1134
1135 sig = ir->matching_signature(&empty);
1136
1137 assert(sig);
1138
1139 foreach_iter(exec_list_iterator, iter, sig->body) {
1140 ir_instruction *ir = (ir_instruction *)iter.get();
1141 this->base_ir = ir;
1142
1143 ir->accept(this);
1144 }
1145 }
1146 }
1147
1148 void
1149 fs_visitor::visit(ir_function_signature *ir)
1150 {
1151 assert(!"not reached");
1152 (void)ir;
1153 }
1154
1155 fs_inst *
1156 fs_visitor::emit(fs_inst inst)
1157 {
1158 fs_inst *list_inst = new(mem_ctx) fs_inst;
1159 *list_inst = inst;
1160
1161 list_inst->annotation = this->current_annotation;
1162 list_inst->ir = this->base_ir;
1163
1164 this->instructions.push_tail(list_inst);
1165
1166 return list_inst;
1167 }
1168
1169 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1170 void
1171 fs_visitor::emit_dummy_fs()
1172 {
1173 /* Everyone's favorite color. */
1174 emit(fs_inst(BRW_OPCODE_MOV,
1175 fs_reg(MRF, 2),
1176 fs_reg(1.0f)));
1177 emit(fs_inst(BRW_OPCODE_MOV,
1178 fs_reg(MRF, 3),
1179 fs_reg(0.0f)));
1180 emit(fs_inst(BRW_OPCODE_MOV,
1181 fs_reg(MRF, 4),
1182 fs_reg(1.0f)));
1183 emit(fs_inst(BRW_OPCODE_MOV,
1184 fs_reg(MRF, 5),
1185 fs_reg(0.0f)));
1186
1187 fs_inst *write;
1188 write = emit(fs_inst(FS_OPCODE_FB_WRITE,
1189 fs_reg(0),
1190 fs_reg(0)));
1191 }
1192
1193 /* The register location here is relative to the start of the URB
1194 * data. It will get adjusted to be a real location before
1195 * generate_code() time.
1196 */
1197 struct brw_reg
1198 fs_visitor::interp_reg(int location, int channel)
1199 {
1200 int regnr = location * 2 + channel / 2;
1201 int stride = (channel & 1) * 4;
1202
1203 return brw_vec1_grf(regnr, stride);
1204 }
1205
1206 /** Emits the interpolation for the varying inputs. */
1207 void
1208 fs_visitor::emit_interpolation()
1209 {
1210 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
1211 /* For now, the source regs for the setup URB data will be unset,
1212 * since we don't know until codegen how many push constants we'll
1213 * use, and therefore what the setup URB offset is.
1214 */
1215 fs_reg src_reg = reg_undef;
1216
1217 this->current_annotation = "compute pixel centers";
1218 this->pixel_x = fs_reg(this, glsl_type::uint_type);
1219 this->pixel_y = fs_reg(this, glsl_type::uint_type);
1220 this->pixel_x.type = BRW_REGISTER_TYPE_UW;
1221 this->pixel_y.type = BRW_REGISTER_TYPE_UW;
1222 emit(fs_inst(BRW_OPCODE_ADD,
1223 this->pixel_x,
1224 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
1225 fs_reg(brw_imm_v(0x10101010))));
1226 emit(fs_inst(BRW_OPCODE_ADD,
1227 this->pixel_y,
1228 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
1229 fs_reg(brw_imm_v(0x11001100))));
1230
1231 this->current_annotation = "compute pixel deltas from v0";
1232 this->delta_x = fs_reg(this, glsl_type::float_type);
1233 this->delta_y = fs_reg(this, glsl_type::float_type);
1234 emit(fs_inst(BRW_OPCODE_ADD,
1235 this->delta_x,
1236 this->pixel_x,
1237 fs_reg(negate(brw_vec1_grf(1, 0)))));
1238 emit(fs_inst(BRW_OPCODE_ADD,
1239 this->delta_y,
1240 this->pixel_y,
1241 fs_reg(brw_vec1_grf(1, 1))));
1242
1243 this->current_annotation = "compute pos.w and 1/pos.w";
1244 /* Compute wpos. Unlike many other varying inputs, we usually need it
1245 * to produce 1/w, and the varying variable wouldn't show up.
1246 */
1247 fs_reg wpos = fs_reg(this, glsl_type::vec4_type);
1248 this->interp_attrs[FRAG_ATTRIB_WPOS] = wpos;
1249 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_x)); /* FINISHME: ARB_fcc */
1250 wpos.reg_offset++;
1251 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_y)); /* FINISHME: ARB_fcc */
1252 wpos.reg_offset++;
1253 emit(fs_inst(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y,
1254 interp_reg(FRAG_ATTRIB_WPOS, 2)));
1255 wpos.reg_offset++;
1256 emit(fs_inst(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y,
1257 interp_reg(FRAG_ATTRIB_WPOS, 3)));
1258 /* Compute the pixel W value from wpos.w. */
1259 this->pixel_w = fs_reg(this, glsl_type::float_type);
1260 emit(fs_inst(FS_OPCODE_RCP, this->pixel_w, wpos));
1261
1262 /* FINISHME: gl_FrontFacing */
1263
1264 foreach_iter(exec_list_iterator, iter, *this->shader->ir) {
1265 ir_instruction *ir = (ir_instruction *)iter.get();
1266 ir_variable *var = ir->as_variable();
1267
1268 if (!var)
1269 continue;
1270
1271 if (var->mode != ir_var_in)
1272 continue;
1273
1274 /* If it's already set up (WPOS), skip. */
1275 if (var->location == 0)
1276 continue;
1277
1278 this->current_annotation = talloc_asprintf(this->mem_ctx,
1279 "interpolate %s "
1280 "(FRAG_ATTRIB[%d])",
1281 var->name,
1282 var->location);
1283 emit_pinterp(var->location);
1284 }
1285 this->current_annotation = NULL;
1286 }
1287
1288 void
1289 fs_visitor::emit_pinterp(int location)
1290 {
1291 fs_reg interp_attr = fs_reg(this, glsl_type::vec4_type);
1292 this->interp_attrs[location] = interp_attr;
1293
1294 for (unsigned int i = 0; i < 4; i++) {
1295 struct brw_reg interp = interp_reg(location, i);
1296 emit(fs_inst(FS_OPCODE_LINTERP,
1297 interp_attr,
1298 this->delta_x,
1299 this->delta_y,
1300 fs_reg(interp)));
1301 interp_attr.reg_offset++;
1302 }
1303 interp_attr.reg_offset -= 4;
1304
1305 for (unsigned int i = 0; i < 4; i++) {
1306 emit(fs_inst(BRW_OPCODE_MUL,
1307 interp_attr,
1308 interp_attr,
1309 this->pixel_w));
1310 interp_attr.reg_offset++;
1311 }
1312 }
1313
1314 void
1315 fs_visitor::emit_fb_writes()
1316 {
1317 this->current_annotation = "FB write";
1318
1319 assert(this->frag_color || !"FINISHME: MRT");
1320 fs_reg color = *(variable_storage(this->frag_color));
1321
1322 for (int i = 0; i < 4; i++) {
1323 emit(fs_inst(BRW_OPCODE_MOV,
1324 fs_reg(MRF, 2 + i),
1325 color));
1326 color.reg_offset++;
1327 }
1328
1329 emit(fs_inst(FS_OPCODE_FB_WRITE,
1330 fs_reg(0),
1331 fs_reg(0)));
1332
1333 this->current_annotation = NULL;
1334 }
1335
1336 void
1337 fs_visitor::generate_fb_write(fs_inst *inst)
1338 {
1339 GLboolean eot = 1; /* FINISHME: MRT */
1340 /* FINISHME: AADS */
1341
1342 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1343 * move, here's g1.
1344 */
1345 brw_push_insn_state(p);
1346 brw_set_mask_control(p, BRW_MASK_DISABLE);
1347 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1348 brw_MOV(p,
1349 brw_message_reg(1),
1350 brw_vec8_grf(1, 0));
1351 brw_pop_insn_state(p);
1352
1353 int nr = 2 + 4;
1354
1355 brw_fb_WRITE(p,
1356 8, /* dispatch_width */
1357 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW),
1358 0, /* base MRF */
1359 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
1360 0, /* FINISHME: MRT target */
1361 nr,
1362 0,
1363 eot);
1364 }
1365
1366 void
1367 fs_visitor::generate_linterp(fs_inst *inst,
1368 struct brw_reg dst, struct brw_reg *src)
1369 {
1370 struct brw_reg delta_x = src[0];
1371 struct brw_reg delta_y = src[1];
1372 struct brw_reg interp = src[2];
1373
1374 if (brw->has_pln &&
1375 delta_y.nr == delta_x.nr + 1 &&
1376 (intel->gen >= 6 || (delta_x.nr & 1) == 0)) {
1377 brw_PLN(p, dst, interp, delta_x);
1378 } else {
1379 brw_LINE(p, brw_null_reg(), interp, delta_x);
1380 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
1381 }
1382 }
1383
1384 void
1385 fs_visitor::generate_math(fs_inst *inst,
1386 struct brw_reg dst, struct brw_reg *src)
1387 {
1388 int op;
1389
1390 switch (inst->opcode) {
1391 case FS_OPCODE_RCP:
1392 op = BRW_MATH_FUNCTION_INV;
1393 break;
1394 case FS_OPCODE_RSQ:
1395 op = BRW_MATH_FUNCTION_RSQ;
1396 break;
1397 case FS_OPCODE_SQRT:
1398 op = BRW_MATH_FUNCTION_SQRT;
1399 break;
1400 case FS_OPCODE_EXP2:
1401 op = BRW_MATH_FUNCTION_EXP;
1402 break;
1403 case FS_OPCODE_LOG2:
1404 op = BRW_MATH_FUNCTION_LOG;
1405 break;
1406 case FS_OPCODE_POW:
1407 op = BRW_MATH_FUNCTION_POW;
1408 break;
1409 case FS_OPCODE_SIN:
1410 op = BRW_MATH_FUNCTION_SIN;
1411 break;
1412 case FS_OPCODE_COS:
1413 op = BRW_MATH_FUNCTION_COS;
1414 break;
1415 default:
1416 assert(!"not reached: unknown math function");
1417 op = 0;
1418 break;
1419 }
1420
1421 if (inst->opcode == FS_OPCODE_POW) {
1422 brw_MOV(p, brw_message_reg(3), src[1]);
1423 }
1424
1425 brw_math(p, dst,
1426 op,
1427 inst->saturate ? BRW_MATH_SATURATE_SATURATE :
1428 BRW_MATH_SATURATE_NONE,
1429 2, src[0],
1430 BRW_MATH_DATA_VECTOR,
1431 BRW_MATH_PRECISION_FULL);
1432 }
1433
1434 void
1435 fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
1436 {
1437 int msg_type = -1;
1438 int rlen = 4;
1439
1440 if (intel->gen == 5) {
1441 switch (inst->opcode) {
1442 case FS_OPCODE_TEX:
1443 if (inst->shadow_compare) {
1444 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5;
1445 } else {
1446 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_GEN5;
1447 }
1448 break;
1449 case FS_OPCODE_TXB:
1450 if (inst->shadow_compare) {
1451 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5;
1452 } else {
1453 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5;
1454 }
1455 break;
1456 }
1457 } else {
1458 switch (inst->opcode) {
1459 case FS_OPCODE_TEX:
1460 /* Note that G45 and older determines shadow compare and dispatch width
1461 * from message length for most messages.
1462 */
1463 if (inst->shadow_compare) {
1464 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
1465 } else {
1466 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
1467 }
1468 case FS_OPCODE_TXB:
1469 if (inst->shadow_compare) {
1470 assert(!"FINISHME: shadow compare with bias.");
1471 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
1472 } else {
1473 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
1474 rlen = 8;
1475 }
1476 break;
1477 }
1478 }
1479 assert(msg_type != -1);
1480
1481 /* g0 header. */
1482 src.nr--;
1483
1484 brw_SAMPLE(p,
1485 retype(dst, BRW_REGISTER_TYPE_UW),
1486 src.nr,
1487 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
1488 SURF_INDEX_TEXTURE(inst->sampler),
1489 inst->sampler,
1490 WRITEMASK_XYZW,
1491 msg_type,
1492 rlen,
1493 inst->mlen + 1,
1494 0,
1495 1,
1496 BRW_SAMPLER_SIMD_MODE_SIMD8);
1497 }
1498
1499 void
1500 fs_visitor::generate_discard(fs_inst *inst)
1501 {
1502 struct brw_reg g0 = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1503 brw_push_insn_state(p);
1504 brw_set_mask_control(p, BRW_MASK_DISABLE);
1505 brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); /* IMASK */
1506 brw_AND(p, g0, c->emit_mask_reg, g0);
1507 brw_pop_insn_state(p);
1508 }
1509
1510 static void
1511 trivial_assign_reg(int header_size, fs_reg *reg)
1512 {
1513 if (reg->file == GRF && reg->reg != 0) {
1514 reg->hw_reg = header_size + reg->reg - 1 + reg->reg_offset;
1515 reg->reg = 0;
1516 }
1517 }
1518
1519 void
1520 fs_visitor::assign_curb_setup()
1521 {
1522 c->prog_data.first_curbe_grf = c->key.nr_payload_regs;
1523 c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8;
1524
1525 if (intel->gen == 5 && (c->prog_data.first_curbe_grf +
1526 c->prog_data.curb_read_length) & 1) {
1527 /* Align the start of the interpolation coefficients so that we can use
1528 * the PLN instruction.
1529 */
1530 c->prog_data.first_curbe_grf++;
1531 }
1532
1533 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1534 foreach_iter(exec_list_iterator, iter, this->instructions) {
1535 fs_inst *inst = (fs_inst *)iter.get();
1536
1537 for (unsigned int i = 0; i < 3; i++) {
1538 if (inst->src[i].file == UNIFORM) {
1539 int constant_nr = inst->src[i].hw_reg + inst->src[i].reg_offset;
1540 struct brw_reg brw_reg = brw_vec1_grf(c->prog_data.first_curbe_grf +
1541 constant_nr / 8,
1542 constant_nr % 8);
1543
1544 inst->src[i].file = FIXED_HW_REG;
1545 inst->src[i].fixed_hw_reg = brw_reg;
1546 }
1547 }
1548 }
1549 }
1550
1551 void
1552 fs_visitor::assign_urb_setup()
1553 {
1554 int urb_start = c->prog_data.first_curbe_grf + c->prog_data.curb_read_length;
1555 int interp_reg_nr[FRAG_ATTRIB_MAX];
1556
1557 c->prog_data.urb_read_length = 0;
1558
1559 /* Figure out where each of the incoming setup attributes lands. */
1560 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
1561 interp_reg_nr[i] = -1;
1562
1563 if (i != FRAG_ATTRIB_WPOS &&
1564 !(brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(i)))
1565 continue;
1566
1567 /* Each attribute is 4 setup channels, each of which is half a reg. */
1568 interp_reg_nr[i] = urb_start + c->prog_data.urb_read_length;
1569 c->prog_data.urb_read_length += 2;
1570 }
1571
1572 /* Map the register numbers for FS_OPCODE_LINTERP so that it uses
1573 * the correct setup input.
1574 */
1575 foreach_iter(exec_list_iterator, iter, this->instructions) {
1576 fs_inst *inst = (fs_inst *)iter.get();
1577
1578 if (inst->opcode != FS_OPCODE_LINTERP)
1579 continue;
1580
1581 assert(inst->src[2].file == FIXED_HW_REG);
1582
1583 int location = inst->src[2].fixed_hw_reg.nr / 2;
1584 assert(interp_reg_nr[location] != -1);
1585 inst->src[2].fixed_hw_reg.nr = (interp_reg_nr[location] +
1586 (inst->src[2].fixed_hw_reg.nr & 1));
1587 }
1588
1589 this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length;
1590 }
1591
1592 void
1593 fs_visitor::assign_regs()
1594 {
1595 int header_size = this->first_non_payload_grf;
1596 int last_grf = 0;
1597
1598 /* FINISHME: trivial assignment of register numbers */
1599 foreach_iter(exec_list_iterator, iter, this->instructions) {
1600 fs_inst *inst = (fs_inst *)iter.get();
1601
1602 trivial_assign_reg(header_size, &inst->dst);
1603 trivial_assign_reg(header_size, &inst->src[0]);
1604 trivial_assign_reg(header_size, &inst->src[1]);
1605
1606 last_grf = MAX2(last_grf, inst->dst.hw_reg);
1607 last_grf = MAX2(last_grf, inst->src[0].hw_reg);
1608 last_grf = MAX2(last_grf, inst->src[1].hw_reg);
1609 }
1610
1611 this->grf_used = last_grf + 1;
1612 }
1613
1614 static struct brw_reg brw_reg_from_fs_reg(fs_reg *reg)
1615 {
1616 struct brw_reg brw_reg;
1617
1618 switch (reg->file) {
1619 case GRF:
1620 case ARF:
1621 case MRF:
1622 brw_reg = brw_vec8_reg(reg->file,
1623 reg->hw_reg, 0);
1624 brw_reg = retype(brw_reg, reg->type);
1625 break;
1626 case IMM:
1627 switch (reg->type) {
1628 case BRW_REGISTER_TYPE_F:
1629 brw_reg = brw_imm_f(reg->imm.f);
1630 break;
1631 case BRW_REGISTER_TYPE_D:
1632 brw_reg = brw_imm_d(reg->imm.i);
1633 break;
1634 case BRW_REGISTER_TYPE_UD:
1635 brw_reg = brw_imm_ud(reg->imm.u);
1636 break;
1637 default:
1638 assert(!"not reached");
1639 break;
1640 }
1641 break;
1642 case FIXED_HW_REG:
1643 brw_reg = reg->fixed_hw_reg;
1644 break;
1645 case BAD_FILE:
1646 /* Probably unused. */
1647 brw_reg = brw_null_reg();
1648 break;
1649 case UNIFORM:
1650 assert(!"not reached");
1651 brw_reg = brw_null_reg();
1652 break;
1653 }
1654 if (reg->abs)
1655 brw_reg = brw_abs(brw_reg);
1656 if (reg->negate)
1657 brw_reg = negate(brw_reg);
1658
1659 return brw_reg;
1660 }
1661
1662 void
1663 fs_visitor::generate_code()
1664 {
1665 unsigned int annotation_len = 0;
1666 int last_native_inst = 0;
1667 struct brw_instruction *if_stack[16], *loop_stack[16];
1668 int if_stack_depth = 0, loop_stack_depth = 0;
1669 int if_depth_in_loop[16];
1670
1671 if_depth_in_loop[loop_stack_depth] = 0;
1672
1673 memset(&if_stack, 0, sizeof(if_stack));
1674 foreach_iter(exec_list_iterator, iter, this->instructions) {
1675 fs_inst *inst = (fs_inst *)iter.get();
1676 struct brw_reg src[3], dst;
1677
1678 for (unsigned int i = 0; i < 3; i++) {
1679 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1680 }
1681 dst = brw_reg_from_fs_reg(&inst->dst);
1682
1683 brw_set_conditionalmod(p, inst->conditional_mod);
1684 brw_set_predicate_control(p, inst->predicated);
1685
1686 switch (inst->opcode) {
1687 case BRW_OPCODE_MOV:
1688 brw_MOV(p, dst, src[0]);
1689 break;
1690 case BRW_OPCODE_ADD:
1691 brw_ADD(p, dst, src[0], src[1]);
1692 break;
1693 case BRW_OPCODE_MUL:
1694 brw_MUL(p, dst, src[0], src[1]);
1695 break;
1696
1697 case BRW_OPCODE_FRC:
1698 brw_FRC(p, dst, src[0]);
1699 break;
1700 case BRW_OPCODE_RNDD:
1701 brw_RNDD(p, dst, src[0]);
1702 break;
1703 case BRW_OPCODE_RNDZ:
1704 brw_RNDZ(p, dst, src[0]);
1705 break;
1706
1707 case BRW_OPCODE_AND:
1708 brw_AND(p, dst, src[0], src[1]);
1709 break;
1710 case BRW_OPCODE_OR:
1711 brw_OR(p, dst, src[0], src[1]);
1712 break;
1713 case BRW_OPCODE_XOR:
1714 brw_XOR(p, dst, src[0], src[1]);
1715 break;
1716
1717 case BRW_OPCODE_CMP:
1718 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1719 break;
1720 case BRW_OPCODE_SEL:
1721 brw_SEL(p, dst, src[0], src[1]);
1722 break;
1723
1724 case BRW_OPCODE_IF:
1725 assert(if_stack_depth < 16);
1726 if_stack[if_stack_depth] = brw_IF(p, BRW_EXECUTE_8);
1727 if_stack_depth++;
1728 break;
1729 case BRW_OPCODE_ELSE:
1730 if_stack[if_stack_depth - 1] =
1731 brw_ELSE(p, if_stack[if_stack_depth - 1]);
1732 break;
1733 case BRW_OPCODE_ENDIF:
1734 if_stack_depth--;
1735 brw_ENDIF(p , if_stack[if_stack_depth]);
1736 break;
1737
1738 case BRW_OPCODE_DO:
1739 loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
1740 if_depth_in_loop[loop_stack_depth] = 0;
1741 break;
1742
1743 case BRW_OPCODE_BREAK:
1744 brw_BREAK(p, if_depth_in_loop[loop_stack_depth]);
1745 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1746 break;
1747 case BRW_OPCODE_CONTINUE:
1748 brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
1749 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1750 break;
1751
1752 case BRW_OPCODE_WHILE: {
1753 struct brw_instruction *inst0, *inst1;
1754 GLuint br = 1;
1755
1756 if (intel->gen == 5)
1757 br = 2;
1758
1759 assert(loop_stack_depth > 0);
1760 loop_stack_depth--;
1761 inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
1762 /* patch all the BREAK/CONT instructions from last BGNLOOP */
1763 while (inst0 > loop_stack[loop_stack_depth]) {
1764 inst0--;
1765 if (inst0->header.opcode == BRW_OPCODE_BREAK &&
1766 inst0->bits3.if_else.jump_count == 0) {
1767 inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
1768 }
1769 else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
1770 inst0->bits3.if_else.jump_count == 0) {
1771 inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
1772 }
1773 }
1774 }
1775 break;
1776
1777 case FS_OPCODE_RCP:
1778 case FS_OPCODE_RSQ:
1779 case FS_OPCODE_SQRT:
1780 case FS_OPCODE_EXP2:
1781 case FS_OPCODE_LOG2:
1782 case FS_OPCODE_POW:
1783 case FS_OPCODE_SIN:
1784 case FS_OPCODE_COS:
1785 generate_math(inst, dst, src);
1786 break;
1787 case FS_OPCODE_LINTERP:
1788 generate_linterp(inst, dst, src);
1789 break;
1790 case FS_OPCODE_TEX:
1791 case FS_OPCODE_TXB:
1792 case FS_OPCODE_TXL:
1793 generate_tex(inst, dst, src[0]);
1794 break;
1795 case FS_OPCODE_DISCARD:
1796 generate_discard(inst);
1797 break;
1798 case FS_OPCODE_FB_WRITE:
1799 generate_fb_write(inst);
1800 break;
1801 default:
1802 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
1803 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1804 brw_opcodes[inst->opcode].name);
1805 } else {
1806 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1807 }
1808 this->fail = true;
1809 }
1810
1811 if (annotation_len < p->nr_insn) {
1812 annotation_len *= 2;
1813 if (annotation_len < 16)
1814 annotation_len = 16;
1815
1816 this->annotation_string = talloc_realloc(this->mem_ctx,
1817 annotation_string,
1818 const char *,
1819 annotation_len);
1820 this->annotation_ir = talloc_realloc(this->mem_ctx,
1821 annotation_ir,
1822 ir_instruction *,
1823 annotation_len);
1824 }
1825
1826 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
1827 this->annotation_string[i] = inst->annotation;
1828 this->annotation_ir[i] = inst->ir;
1829 }
1830 last_native_inst = p->nr_insn;
1831 }
1832 }
1833
1834 GLboolean
1835 brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c)
1836 {
1837 struct brw_compile *p = &c->func;
1838 struct intel_context *intel = &brw->intel;
1839 GLcontext *ctx = &intel->ctx;
1840 struct brw_shader *shader = NULL;
1841 struct gl_shader_program *prog = ctx->Shader.CurrentProgram;
1842
1843 if (!prog)
1844 return GL_FALSE;
1845
1846 if (!using_new_fs)
1847 return GL_FALSE;
1848
1849 for (unsigned int i = 0; i < prog->_NumLinkedShaders; i++) {
1850 if (prog->_LinkedShaders[i]->Type == GL_FRAGMENT_SHADER) {
1851 shader = (struct brw_shader *)prog->_LinkedShaders[i];
1852 break;
1853 }
1854 }
1855 if (!shader)
1856 return GL_FALSE;
1857
1858 /* We always use 8-wide mode, at least for now. For one, flow
1859 * control only works in 8-wide. Also, when we're fragment shader
1860 * bound, we're almost always under register pressure as well, so
1861 * 8-wide would save us from the performance cliff of spilling
1862 * regs.
1863 */
1864 c->dispatch_width = 8;
1865
1866 if (INTEL_DEBUG & DEBUG_WM) {
1867 printf("GLSL IR for native fragment shader %d:\n", prog->Name);
1868 _mesa_print_ir(shader->ir, NULL);
1869 printf("\n");
1870 }
1871
1872 /* Now the main event: Visit the shader IR and generate our FS IR for it.
1873 */
1874 fs_visitor v(c, shader);
1875
1876 if (0) {
1877 v.emit_dummy_fs();
1878 } else {
1879 v.emit_interpolation();
1880
1881 /* Generate FS IR for main(). (the visitor only descends into
1882 * functions called "main").
1883 */
1884 foreach_iter(exec_list_iterator, iter, *shader->ir) {
1885 ir_instruction *ir = (ir_instruction *)iter.get();
1886 v.base_ir = ir;
1887 ir->accept(&v);
1888 }
1889
1890 v.emit_fb_writes();
1891 v.assign_curb_setup();
1892 v.assign_urb_setup();
1893 v.assign_regs();
1894 }
1895
1896 v.generate_code();
1897
1898 assert(!v.fail); /* FINISHME: Cleanly fail, tested at link time, etc. */
1899
1900 if (v.fail)
1901 return GL_FALSE;
1902
1903 if (INTEL_DEBUG & DEBUG_WM) {
1904 const char *last_annotation_string = NULL;
1905 ir_instruction *last_annotation_ir = NULL;
1906
1907 printf("Native code for fragment shader %d:\n", prog->Name);
1908 for (unsigned int i = 0; i < p->nr_insn; i++) {
1909 if (last_annotation_ir != v.annotation_ir[i]) {
1910 last_annotation_ir = v.annotation_ir[i];
1911 if (last_annotation_ir) {
1912 printf(" ");
1913 last_annotation_ir->print();
1914 printf("\n");
1915 }
1916 }
1917 if (last_annotation_string != v.annotation_string[i]) {
1918 last_annotation_string = v.annotation_string[i];
1919 if (last_annotation_string)
1920 printf(" %s\n", last_annotation_string);
1921 }
1922 brw_disasm(stdout, &p->store[i], intel->gen);
1923 }
1924 printf("\n");
1925 }
1926
1927 c->prog_data.total_grf = v.grf_used;
1928 c->prog_data.total_scratch = 0;
1929
1930 return GL_TRUE;
1931 }