2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_optimize.h"
37 #include "program/hash_table.h"
38 #include "brw_context.h"
43 #include "../glsl/glsl_types.h"
44 #include "../glsl/ir_optimization.h"
45 #include "../glsl/ir_print_visitor.h"
48 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
49 GRF
= BRW_GENERAL_REGISTER_FILE
,
50 MRF
= BRW_MESSAGE_REGISTER_FILE
,
51 IMM
= BRW_IMMEDIATE_VALUE
,
52 FIXED_HW_REG
, /* a struct brw_reg */
53 UNIFORM
, /* prog_data->params[hw_reg] */
58 FS_OPCODE_FB_WRITE
= 256,
76 static int using_new_fs
= -1;
79 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
81 struct brw_shader
*shader
;
83 shader
= talloc_zero(NULL
, struct brw_shader
);
85 shader
->base
.Type
= type
;
86 shader
->base
.Name
= name
;
87 _mesa_init_shader(ctx
, &shader
->base
);
93 struct gl_shader_program
*
94 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
96 struct brw_shader_program
*prog
;
97 prog
= talloc_zero(NULL
, struct brw_shader_program
);
99 prog
->base
.Name
= name
;
100 _mesa_init_shader_program(ctx
, &prog
->base
);
106 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
108 if (!_mesa_ir_compile_shader(ctx
, shader
))
115 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
117 if (using_new_fs
== -1)
118 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
120 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
121 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
123 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
124 void *mem_ctx
= talloc_new(NULL
);
128 talloc_free(shader
->ir
);
129 shader
->ir
= new(shader
) exec_list
;
130 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
132 do_mat_op_to_vec(shader
->ir
);
133 do_mod_to_fract(shader
->ir
);
134 do_div_to_mul_rcp(shader
->ir
);
135 do_sub_to_add_neg(shader
->ir
);
136 do_explog_to_explog2(shader
->ir
);
138 brw_do_channel_expressions(shader
->ir
);
139 brw_do_vector_splitting(shader
->ir
);
144 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
147 validate_ir_tree(shader
->ir
);
149 reparent_ir(shader
->ir
, shader
->ir
);
150 talloc_free(mem_ctx
);
154 if (!_mesa_ir_link_shader(ctx
, prog
))
161 type_size(const struct glsl_type
*type
)
163 unsigned int size
, i
;
165 switch (type
->base_type
) {
168 case GLSL_TYPE_FLOAT
:
170 return type
->components();
171 case GLSL_TYPE_ARRAY
:
172 /* FINISHME: uniform/varying arrays. */
173 return type_size(type
->fields
.array
) * type
->length
;
174 case GLSL_TYPE_STRUCT
:
176 for (i
= 0; i
< type
->length
; i
++) {
177 size
+= type_size(type
->fields
.structure
[i
].type
);
180 case GLSL_TYPE_SAMPLER
:
181 /* Samplers take up no register space, since they're baked in at
186 assert(!"not reached");
193 /* Callers of this talloc-based new need not call delete. It's
194 * easier to just talloc_free 'ctx' (or any of its ancestors). */
195 static void* operator new(size_t size
, void *ctx
)
199 node
= talloc_size(ctx
, size
);
200 assert(node
!= NULL
);
208 this->reg_offset
= 0;
214 /** Generic unset register constructor. */
218 this->file
= BAD_FILE
;
221 /** Immediate value constructor. */
226 this->type
= BRW_REGISTER_TYPE_F
;
230 /** Immediate value constructor. */
235 this->type
= BRW_REGISTER_TYPE_D
;
239 /** Immediate value constructor. */
244 this->type
= BRW_REGISTER_TYPE_UD
;
248 /** Fixed brw_reg Immediate value constructor. */
249 fs_reg(struct brw_reg fixed_hw_reg
)
252 this->file
= FIXED_HW_REG
;
253 this->fixed_hw_reg
= fixed_hw_reg
;
254 this->type
= fixed_hw_reg
.type
;
257 fs_reg(enum register_file file
, int hw_reg
);
258 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
260 /** Register file: ARF, GRF, MRF, IMM. */
261 enum register_file file
;
262 /** Abstract register number. 0 = fixed hw reg */
264 /** Offset within the abstract register. */
266 /** HW register number. Generally unset until register allocation. */
268 /** Register type. BRW_REGISTER_TYPE_* */
272 struct brw_reg fixed_hw_reg
;
274 /** Value for file == BRW_IMMMEDIATE_FILE */
282 static const fs_reg reg_undef
;
283 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
285 class fs_inst
: public exec_node
{
287 /* Callers of this talloc-based new need not call delete. It's
288 * easier to just talloc_free 'ctx' (or any of its ancestors). */
289 static void* operator new(size_t size
, void *ctx
)
293 node
= talloc_zero_size(ctx
, size
);
294 assert(node
!= NULL
);
301 this->opcode
= BRW_OPCODE_NOP
;
302 this->saturate
= false;
303 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
304 this->predicated
= false;
306 this->shadow_compare
= false;
317 this->opcode
= opcode
;
320 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
)
323 this->opcode
= opcode
;
328 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
331 this->opcode
= opcode
;
337 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg src2
)
340 this->opcode
= opcode
;
347 int opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
352 int conditional_mod
; /**< BRW_CONDITIONAL_* */
354 int mlen
; /** SEND message length */
359 * Annotation for the generated IR. One of the two can be set.
362 const char *annotation
;
366 class fs_visitor
: public ir_visitor
370 fs_visitor(struct brw_wm_compile
*c
, struct brw_shader
*shader
)
375 this->intel
= &brw
->intel
;
376 this->ctx
= &intel
->ctx
;
377 this->mem_ctx
= talloc_new(NULL
);
378 this->shader
= shader
;
380 this->next_abstract_grf
= 1;
381 this->variable_ht
= hash_table_ctor(0,
382 hash_table_pointer_hash
,
383 hash_table_pointer_compare
);
385 this->frag_color
= NULL
;
386 this->frag_data
= NULL
;
387 this->frag_depth
= NULL
;
388 this->first_non_payload_grf
= 0;
390 this->current_annotation
= NULL
;
391 this->annotation_string
= NULL
;
392 this->annotation_ir
= NULL
;
396 talloc_free(this->mem_ctx
);
397 hash_table_dtor(this->variable_ht
);
400 fs_reg
*variable_storage(ir_variable
*var
);
402 void visit(ir_variable
*ir
);
403 void visit(ir_assignment
*ir
);
404 void visit(ir_dereference_variable
*ir
);
405 void visit(ir_dereference_record
*ir
);
406 void visit(ir_dereference_array
*ir
);
407 void visit(ir_expression
*ir
);
408 void visit(ir_texture
*ir
);
409 void visit(ir_if
*ir
);
410 void visit(ir_constant
*ir
);
411 void visit(ir_swizzle
*ir
);
412 void visit(ir_return
*ir
);
413 void visit(ir_loop
*ir
);
414 void visit(ir_loop_jump
*ir
);
415 void visit(ir_discard
*ir
);
416 void visit(ir_call
*ir
);
417 void visit(ir_function
*ir
);
418 void visit(ir_function_signature
*ir
);
420 fs_inst
*emit(fs_inst inst
);
421 void assign_curb_setup();
422 void assign_urb_setup();
424 void generate_code();
425 void generate_fb_write(fs_inst
*inst
);
426 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
427 struct brw_reg
*src
);
428 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
429 void generate_math(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg
*src
);
430 void generate_discard(fs_inst
*inst
);
432 void emit_dummy_fs();
433 void emit_interpolation();
434 void emit_pinterp(int location
);
435 void emit_fb_writes();
437 struct brw_reg
interp_reg(int location
, int channel
);
439 struct brw_context
*brw
;
440 struct intel_context
*intel
;
442 struct brw_wm_compile
*c
;
443 struct brw_compile
*p
;
444 struct brw_shader
*shader
;
446 exec_list instructions
;
447 int next_abstract_grf
;
448 struct hash_table
*variable_ht
;
449 ir_variable
*frag_color
, *frag_data
, *frag_depth
;
450 int first_non_payload_grf
;
452 /** @{ debug annotation info */
453 const char *current_annotation
;
454 ir_instruction
*base_ir
;
455 const char **annotation_string
;
456 ir_instruction
**annotation_ir
;
461 /* Result of last visit() method. */
469 fs_reg interp_attrs
[64];
475 /** Fixed HW reg constructor. */
476 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
480 this->hw_reg
= hw_reg
;
481 this->type
= BRW_REGISTER_TYPE_F
;
484 /** Automatic reg constructor. */
485 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
490 this->reg
= v
->next_abstract_grf
;
491 this->reg_offset
= 0;
492 v
->next_abstract_grf
+= type_size(type
);
494 switch (type
->base_type
) {
495 case GLSL_TYPE_FLOAT
:
496 this->type
= BRW_REGISTER_TYPE_F
;
500 this->type
= BRW_REGISTER_TYPE_D
;
503 this->type
= BRW_REGISTER_TYPE_UD
;
506 assert(!"not reached");
507 this->type
= BRW_REGISTER_TYPE_F
;
513 fs_visitor::variable_storage(ir_variable
*var
)
515 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
519 fs_visitor::visit(ir_variable
*ir
)
523 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
524 this->frag_color
= ir
;
525 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
526 this->frag_data
= ir
;
527 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
528 this->frag_depth
= ir
;
529 assert(!"FINISHME: this hangs currently.");
532 if (ir
->mode
== ir_var_in
) {
533 reg
= &this->interp_attrs
[ir
->location
];
536 if (ir
->mode
== ir_var_uniform
) {
537 const float *vec_values
;
538 int param_index
= c
->prog_data
.nr_params
;
540 /* FINISHME: This is wildly incomplete. */
541 assert(ir
->type
->is_scalar() || ir
->type
->is_vector() ||
542 ir
->type
->is_sampler());
544 const struct gl_program
*fp
= &this->brw
->fragment_program
->Base
;
545 /* Our support for uniforms is piggy-backed on the struct
546 * gl_fragment_program, because that's where the values actually
547 * get stored, rather than in some global gl_shader_program uniform
550 vec_values
= fp
->Parameters
->ParameterValues
[ir
->location
];
551 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
552 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
555 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
559 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
561 hash_table_insert(this->variable_ht
, reg
, ir
);
565 fs_visitor::visit(ir_dereference_variable
*ir
)
567 fs_reg
*reg
= variable_storage(ir
->var
);
572 fs_visitor::visit(ir_dereference_record
*ir
)
578 fs_visitor::visit(ir_dereference_array
*ir
)
583 ir
->array
->accept(this);
584 index
= ir
->array_index
->as_constant();
586 if (ir
->type
->is_matrix()) {
587 element_size
= ir
->type
->vector_elements
;
589 element_size
= type_size(ir
->type
);
593 assert(this->result
.file
== UNIFORM
||
594 (this->result
.file
== GRF
&&
595 this->result
.reg
!= 0));
596 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
598 assert(!"FINISHME: non-constant matrix column");
603 fs_visitor::visit(ir_expression
*ir
)
605 unsigned int operand
;
610 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
611 ir
->operands
[operand
]->accept(this);
612 if (this->result
.file
== BAD_FILE
) {
614 printf("Failed to get tree for expression operand:\n");
615 ir
->operands
[operand
]->accept(&v
);
618 op
[operand
] = this->result
;
620 /* Matrix expression operands should have been broken down to vector
621 * operations already.
623 assert(!ir
->operands
[operand
]->type
->is_matrix());
624 /* And then those vector operands should have been broken down to scalar.
626 assert(!ir
->operands
[operand
]->type
->is_vector());
629 /* Storage for our result. If our result goes into an assignment, it will
630 * just get copy-propagated out, so no worries.
632 this->result
= fs_reg(this, ir
->type
);
634 switch (ir
->operation
) {
635 case ir_unop_logic_not
:
636 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
639 op
[0].negate
= ~op
[0].negate
;
640 this->result
= op
[0];
644 this->result
= op
[0];
647 temp
= fs_reg(this, ir
->type
);
649 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
651 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
652 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
653 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
654 inst
->predicated
= true;
656 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
657 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
658 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
659 inst
->predicated
= true;
663 emit(fs_inst(FS_OPCODE_RCP
, this->result
, op
[0]));
667 emit(fs_inst(FS_OPCODE_EXP2
, this->result
, op
[0]));
670 emit(fs_inst(FS_OPCODE_LOG2
, this->result
, op
[0]));
674 assert(!"not reached: should be handled by ir_explog_to_explog2");
677 emit(fs_inst(FS_OPCODE_SIN
, this->result
, op
[0]));
680 emit(fs_inst(FS_OPCODE_COS
, this->result
, op
[0]));
684 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
687 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
691 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
694 assert(!"not reached: should be handled by ir_sub_to_add_neg");
698 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
701 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
704 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
708 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
709 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
710 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
712 case ir_binop_greater
:
713 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
714 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
715 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
717 case ir_binop_lequal
:
718 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
719 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
720 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
722 case ir_binop_gequal
:
723 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
724 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
725 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
728 case ir_binop_all_equal
: /* same as nequal for scalars */
729 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
730 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
731 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
733 case ir_binop_nequal
:
734 case ir_binop_any_nequal
: /* same as nequal for scalars */
735 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
736 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
737 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
740 case ir_binop_logic_xor
:
741 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
744 case ir_binop_logic_or
:
745 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
748 case ir_binop_logic_and
:
749 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
755 assert(!"not reached: should be handled by brw_fs_channel_expressions");
759 assert(!"not reached: should be handled by lower_noise");
763 emit(fs_inst(FS_OPCODE_SQRT
, this->result
, op
[0]));
767 emit(fs_inst(FS_OPCODE_RSQ
, this->result
, op
[0]));
773 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
776 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
780 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
781 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
784 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
787 op
[0].negate
= ~op
[0].negate
;
788 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
789 this->result
.negate
= true;
792 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
795 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
799 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
800 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
802 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
803 inst
->predicated
= true;
806 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
807 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
809 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
810 inst
->predicated
= true;
814 inst
= emit(fs_inst(FS_OPCODE_POW
, this->result
, op
[0], op
[1]));
817 case ir_unop_bit_not
:
819 case ir_binop_lshift
:
820 case ir_binop_rshift
:
821 case ir_binop_bit_and
:
822 case ir_binop_bit_xor
:
823 case ir_binop_bit_or
:
824 assert(!"GLSL 1.30 features unsupported");
830 fs_visitor::visit(ir_assignment
*ir
)
837 /* FINISHME: arrays on the lhs */
838 ir
->lhs
->accept(this);
841 ir
->rhs
->accept(this);
844 /* FINISHME: This should really set to the correct maximal writemask for each
845 * FINISHME: component written (in the loops below). This case can only
846 * FINISHME: occur for matrices, arrays, and structures.
848 if (ir
->write_mask
== 0) {
849 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
850 write_mask
= WRITEMASK_XYZW
;
852 assert(ir
->lhs
->type
->is_vector() || ir
->lhs
->type
->is_scalar());
853 write_mask
= ir
->write_mask
;
856 assert(l
.file
!= BAD_FILE
);
857 assert(r
.file
!= BAD_FILE
);
860 /* Get the condition bool into the predicate. */
861 ir
->condition
->accept(this);
862 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, fs_reg(0)));
863 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
866 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
867 if (i
>= 4 || (write_mask
& (1 << i
))) {
868 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
870 inst
->predicated
= true;
878 fs_visitor::visit(ir_texture
*ir
)
881 fs_inst
*inst
= NULL
;
882 unsigned int mlen
= 0;
884 ir
->coordinate
->accept(this);
885 fs_reg coordinate
= this->result
;
888 fs_reg inv_proj
= fs_reg(this, glsl_type::float_type
);
890 ir
->projector
->accept(this);
891 emit(fs_inst(FS_OPCODE_RCP
, inv_proj
, this->result
));
893 fs_reg proj_coordinate
= fs_reg(this, ir
->coordinate
->type
);
894 for (unsigned int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
895 emit(fs_inst(BRW_OPCODE_MUL
, proj_coordinate
, coordinate
, inv_proj
));
896 coordinate
.reg_offset
++;
897 proj_coordinate
.reg_offset
++;
899 proj_coordinate
.reg_offset
= 0;
901 coordinate
= proj_coordinate
;
904 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
905 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
906 coordinate
.reg_offset
++;
909 /* Pre-Ironlake, the 8-wide sampler always took u,v,r. */
913 if (ir
->shadow_comparitor
) {
914 /* For shadow comparisons, we have to supply u,v,r. */
917 ir
->shadow_comparitor
->accept(this);
918 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
922 /* Do we ever want to handle writemasking on texture samples? Is it
923 * performance relevant?
925 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
929 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
932 ir
->lod_info
.bias
->accept(this);
933 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
936 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
939 ir
->lod_info
.lod
->accept(this);
940 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
943 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
947 assert(!"GLSL 1.30 features unsupported");
953 if (ir
->shadow_comparitor
)
954 inst
->shadow_compare
= true;
959 fs_visitor::visit(ir_swizzle
*ir
)
961 ir
->val
->accept(this);
962 fs_reg val
= this->result
;
964 fs_reg result
= fs_reg(this, ir
->type
);
965 this->result
= result
;
967 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
968 fs_reg channel
= val
;
986 channel
.reg_offset
+= swiz
;
987 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
993 fs_visitor::visit(ir_discard
*ir
)
995 assert(ir
->condition
== NULL
); /* FINISHME */
997 emit(fs_inst(FS_OPCODE_DISCARD
));
1001 fs_visitor::visit(ir_constant
*ir
)
1003 fs_reg
reg(this, ir
->type
);
1006 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1007 switch (ir
->type
->base_type
) {
1008 case GLSL_TYPE_FLOAT
:
1009 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1011 case GLSL_TYPE_UINT
:
1012 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1015 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1017 case GLSL_TYPE_BOOL
:
1018 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1021 assert(!"Non-float/uint/int/bool constant");
1028 fs_visitor::visit(ir_if
*ir
)
1032 /* Don't point the annotation at the if statement, because then it plus
1033 * the then and else blocks get printed.
1035 this->base_ir
= ir
->condition
;
1037 /* Generate the condition into the condition code. */
1038 ir
->condition
->accept(this);
1039 inst
= emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(brw_null_reg()), this->result
));
1040 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1042 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1043 inst
->predicated
= true;
1045 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1046 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1052 if (!ir
->else_instructions
.is_empty()) {
1053 emit(fs_inst(BRW_OPCODE_ELSE
));
1055 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1056 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1063 emit(fs_inst(BRW_OPCODE_ENDIF
));
1067 fs_visitor::visit(ir_loop
*ir
)
1071 assert(!ir
->increment
);
1072 assert(!ir
->counter
);
1074 emit(fs_inst(BRW_OPCODE_DO
));
1076 /* Start a safety counter. If the user messed up their loop
1077 * counting, we don't want to hang the GPU.
1079 fs_reg max_iter
= fs_reg(this, glsl_type::int_type
);
1080 emit(fs_inst(BRW_OPCODE_MOV
, max_iter
, fs_reg(10000)));
1082 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1083 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1089 /* Check the maximum loop iters counter. */
1090 inst
= emit(fs_inst(BRW_OPCODE_ADD
, max_iter
, max_iter
, fs_reg(-1)));
1091 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1093 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1094 inst
->predicated
= true;
1097 emit(fs_inst(BRW_OPCODE_WHILE
));
1101 fs_visitor::visit(ir_loop_jump
*ir
)
1104 case ir_loop_jump::jump_break
:
1105 emit(fs_inst(BRW_OPCODE_BREAK
));
1107 case ir_loop_jump::jump_continue
:
1108 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1114 fs_visitor::visit(ir_call
*ir
)
1116 assert(!"FINISHME");
1120 fs_visitor::visit(ir_return
*ir
)
1122 assert(!"FINISHME");
1126 fs_visitor::visit(ir_function
*ir
)
1128 /* Ignore function bodies other than main() -- we shouldn't see calls to
1129 * them since they should all be inlined before we get to ir_to_mesa.
1131 if (strcmp(ir
->name
, "main") == 0) {
1132 const ir_function_signature
*sig
;
1135 sig
= ir
->matching_signature(&empty
);
1139 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1140 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1149 fs_visitor::visit(ir_function_signature
*ir
)
1151 assert(!"not reached");
1156 fs_visitor::emit(fs_inst inst
)
1158 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1161 list_inst
->annotation
= this->current_annotation
;
1162 list_inst
->ir
= this->base_ir
;
1164 this->instructions
.push_tail(list_inst
);
1169 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1171 fs_visitor::emit_dummy_fs()
1173 /* Everyone's favorite color. */
1174 emit(fs_inst(BRW_OPCODE_MOV
,
1177 emit(fs_inst(BRW_OPCODE_MOV
,
1180 emit(fs_inst(BRW_OPCODE_MOV
,
1183 emit(fs_inst(BRW_OPCODE_MOV
,
1188 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1193 /* The register location here is relative to the start of the URB
1194 * data. It will get adjusted to be a real location before
1195 * generate_code() time.
1198 fs_visitor::interp_reg(int location
, int channel
)
1200 int regnr
= location
* 2 + channel
/ 2;
1201 int stride
= (channel
& 1) * 4;
1203 return brw_vec1_grf(regnr
, stride
);
1206 /** Emits the interpolation for the varying inputs. */
1208 fs_visitor::emit_interpolation()
1210 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1211 /* For now, the source regs for the setup URB data will be unset,
1212 * since we don't know until codegen how many push constants we'll
1213 * use, and therefore what the setup URB offset is.
1215 fs_reg src_reg
= reg_undef
;
1217 this->current_annotation
= "compute pixel centers";
1218 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1219 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1220 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1221 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1222 emit(fs_inst(BRW_OPCODE_ADD
,
1224 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1225 fs_reg(brw_imm_v(0x10101010))));
1226 emit(fs_inst(BRW_OPCODE_ADD
,
1228 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1229 fs_reg(brw_imm_v(0x11001100))));
1231 this->current_annotation
= "compute pixel deltas from v0";
1232 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1233 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1234 emit(fs_inst(BRW_OPCODE_ADD
,
1237 fs_reg(negate(brw_vec1_grf(1, 0)))));
1238 emit(fs_inst(BRW_OPCODE_ADD
,
1241 fs_reg(brw_vec1_grf(1, 1))));
1243 this->current_annotation
= "compute pos.w and 1/pos.w";
1244 /* Compute wpos. Unlike many other varying inputs, we usually need it
1245 * to produce 1/w, and the varying variable wouldn't show up.
1247 fs_reg wpos
= fs_reg(this, glsl_type::vec4_type
);
1248 this->interp_attrs
[FRAG_ATTRIB_WPOS
] = wpos
;
1249 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
)); /* FINISHME: ARB_fcc */
1251 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
)); /* FINISHME: ARB_fcc */
1253 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
1254 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
1256 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
1257 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1258 /* Compute the pixel W value from wpos.w. */
1259 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1260 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos
));
1262 /* FINISHME: gl_FrontFacing */
1264 foreach_iter(exec_list_iterator
, iter
, *this->shader
->ir
) {
1265 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1266 ir_variable
*var
= ir
->as_variable();
1271 if (var
->mode
!= ir_var_in
)
1274 /* If it's already set up (WPOS), skip. */
1275 if (var
->location
== 0)
1278 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1280 "(FRAG_ATTRIB[%d])",
1283 emit_pinterp(var
->location
);
1285 this->current_annotation
= NULL
;
1289 fs_visitor::emit_pinterp(int location
)
1291 fs_reg interp_attr
= fs_reg(this, glsl_type::vec4_type
);
1292 this->interp_attrs
[location
] = interp_attr
;
1294 for (unsigned int i
= 0; i
< 4; i
++) {
1295 struct brw_reg interp
= interp_reg(location
, i
);
1296 emit(fs_inst(FS_OPCODE_LINTERP
,
1301 interp_attr
.reg_offset
++;
1303 interp_attr
.reg_offset
-= 4;
1305 for (unsigned int i
= 0; i
< 4; i
++) {
1306 emit(fs_inst(BRW_OPCODE_MUL
,
1310 interp_attr
.reg_offset
++;
1315 fs_visitor::emit_fb_writes()
1317 this->current_annotation
= "FB write";
1319 assert(this->frag_color
|| !"FINISHME: MRT");
1320 fs_reg color
= *(variable_storage(this->frag_color
));
1322 for (int i
= 0; i
< 4; i
++) {
1323 emit(fs_inst(BRW_OPCODE_MOV
,
1329 emit(fs_inst(FS_OPCODE_FB_WRITE
,
1333 this->current_annotation
= NULL
;
1337 fs_visitor::generate_fb_write(fs_inst
*inst
)
1339 GLboolean eot
= 1; /* FINISHME: MRT */
1340 /* FINISHME: AADS */
1342 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1345 brw_push_insn_state(p
);
1346 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1347 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1350 brw_vec8_grf(1, 0));
1351 brw_pop_insn_state(p
);
1356 8, /* dispatch_width */
1357 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
1359 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
1360 0, /* FINISHME: MRT target */
1367 fs_visitor::generate_linterp(fs_inst
*inst
,
1368 struct brw_reg dst
, struct brw_reg
*src
)
1370 struct brw_reg delta_x
= src
[0];
1371 struct brw_reg delta_y
= src
[1];
1372 struct brw_reg interp
= src
[2];
1375 delta_y
.nr
== delta_x
.nr
+ 1 &&
1376 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
1377 brw_PLN(p
, dst
, interp
, delta_x
);
1379 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
1380 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
1385 fs_visitor::generate_math(fs_inst
*inst
,
1386 struct brw_reg dst
, struct brw_reg
*src
)
1390 switch (inst
->opcode
) {
1392 op
= BRW_MATH_FUNCTION_INV
;
1395 op
= BRW_MATH_FUNCTION_RSQ
;
1397 case FS_OPCODE_SQRT
:
1398 op
= BRW_MATH_FUNCTION_SQRT
;
1400 case FS_OPCODE_EXP2
:
1401 op
= BRW_MATH_FUNCTION_EXP
;
1403 case FS_OPCODE_LOG2
:
1404 op
= BRW_MATH_FUNCTION_LOG
;
1407 op
= BRW_MATH_FUNCTION_POW
;
1410 op
= BRW_MATH_FUNCTION_SIN
;
1413 op
= BRW_MATH_FUNCTION_COS
;
1416 assert(!"not reached: unknown math function");
1421 if (inst
->opcode
== FS_OPCODE_POW
) {
1422 brw_MOV(p
, brw_message_reg(3), src
[1]);
1427 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
1428 BRW_MATH_SATURATE_NONE
,
1430 BRW_MATH_DATA_VECTOR
,
1431 BRW_MATH_PRECISION_FULL
);
1435 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
1440 if (intel
->gen
== 5) {
1441 switch (inst
->opcode
) {
1443 if (inst
->shadow_compare
) {
1444 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
1446 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
1450 if (inst
->shadow_compare
) {
1451 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
1453 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
1458 switch (inst
->opcode
) {
1460 /* Note that G45 and older determines shadow compare and dispatch width
1461 * from message length for most messages.
1463 if (inst
->shadow_compare
) {
1464 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1466 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1469 if (inst
->shadow_compare
) {
1470 assert(!"FINISHME: shadow compare with bias.");
1471 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1473 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1479 assert(msg_type
!= -1);
1485 retype(dst
, BRW_REGISTER_TYPE_UW
),
1487 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
1488 SURF_INDEX_TEXTURE(inst
->sampler
),
1496 BRW_SAMPLER_SIMD_MODE_SIMD8
);
1500 fs_visitor::generate_discard(fs_inst
*inst
)
1502 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1503 brw_push_insn_state(p
);
1504 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1505 brw_NOT(p
, c
->emit_mask_reg
, brw_mask_reg(1)); /* IMASK */
1506 brw_AND(p
, g0
, c
->emit_mask_reg
, g0
);
1507 brw_pop_insn_state(p
);
1511 trivial_assign_reg(int header_size
, fs_reg
*reg
)
1513 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
1514 reg
->hw_reg
= header_size
+ reg
->reg
- 1 + reg
->reg_offset
;
1520 fs_visitor::assign_curb_setup()
1522 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
1523 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
1525 if (intel
->gen
== 5 && (c
->prog_data
.first_curbe_grf
+
1526 c
->prog_data
.curb_read_length
) & 1) {
1527 /* Align the start of the interpolation coefficients so that we can use
1528 * the PLN instruction.
1530 c
->prog_data
.first_curbe_grf
++;
1533 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1534 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1535 fs_inst
*inst
= (fs_inst
*)iter
.get();
1537 for (unsigned int i
= 0; i
< 3; i
++) {
1538 if (inst
->src
[i
].file
== UNIFORM
) {
1539 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
1540 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
1544 inst
->src
[i
].file
= FIXED_HW_REG
;
1545 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
1552 fs_visitor::assign_urb_setup()
1554 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
1555 int interp_reg_nr
[FRAG_ATTRIB_MAX
];
1557 c
->prog_data
.urb_read_length
= 0;
1559 /* Figure out where each of the incoming setup attributes lands. */
1560 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
1561 interp_reg_nr
[i
] = -1;
1563 if (i
!= FRAG_ATTRIB_WPOS
&&
1564 !(brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)))
1567 /* Each attribute is 4 setup channels, each of which is half a reg. */
1568 interp_reg_nr
[i
] = urb_start
+ c
->prog_data
.urb_read_length
;
1569 c
->prog_data
.urb_read_length
+= 2;
1572 /* Map the register numbers for FS_OPCODE_LINTERP so that it uses
1573 * the correct setup input.
1575 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1576 fs_inst
*inst
= (fs_inst
*)iter
.get();
1578 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
1581 assert(inst
->src
[2].file
== FIXED_HW_REG
);
1583 int location
= inst
->src
[2].fixed_hw_reg
.nr
/ 2;
1584 assert(interp_reg_nr
[location
] != -1);
1585 inst
->src
[2].fixed_hw_reg
.nr
= (interp_reg_nr
[location
] +
1586 (inst
->src
[2].fixed_hw_reg
.nr
& 1));
1589 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
1593 fs_visitor::assign_regs()
1595 int header_size
= this->first_non_payload_grf
;
1598 /* FINISHME: trivial assignment of register numbers */
1599 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1600 fs_inst
*inst
= (fs_inst
*)iter
.get();
1602 trivial_assign_reg(header_size
, &inst
->dst
);
1603 trivial_assign_reg(header_size
, &inst
->src
[0]);
1604 trivial_assign_reg(header_size
, &inst
->src
[1]);
1606 last_grf
= MAX2(last_grf
, inst
->dst
.hw_reg
);
1607 last_grf
= MAX2(last_grf
, inst
->src
[0].hw_reg
);
1608 last_grf
= MAX2(last_grf
, inst
->src
[1].hw_reg
);
1611 this->grf_used
= last_grf
+ 1;
1614 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
1616 struct brw_reg brw_reg
;
1618 switch (reg
->file
) {
1622 brw_reg
= brw_vec8_reg(reg
->file
,
1624 brw_reg
= retype(brw_reg
, reg
->type
);
1627 switch (reg
->type
) {
1628 case BRW_REGISTER_TYPE_F
:
1629 brw_reg
= brw_imm_f(reg
->imm
.f
);
1631 case BRW_REGISTER_TYPE_D
:
1632 brw_reg
= brw_imm_d(reg
->imm
.i
);
1634 case BRW_REGISTER_TYPE_UD
:
1635 brw_reg
= brw_imm_ud(reg
->imm
.u
);
1638 assert(!"not reached");
1643 brw_reg
= reg
->fixed_hw_reg
;
1646 /* Probably unused. */
1647 brw_reg
= brw_null_reg();
1650 assert(!"not reached");
1651 brw_reg
= brw_null_reg();
1655 brw_reg
= brw_abs(brw_reg
);
1657 brw_reg
= negate(brw_reg
);
1663 fs_visitor::generate_code()
1665 unsigned int annotation_len
= 0;
1666 int last_native_inst
= 0;
1667 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
1668 int if_stack_depth
= 0, loop_stack_depth
= 0;
1669 int if_depth_in_loop
[16];
1671 if_depth_in_loop
[loop_stack_depth
] = 0;
1673 memset(&if_stack
, 0, sizeof(if_stack
));
1674 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1675 fs_inst
*inst
= (fs_inst
*)iter
.get();
1676 struct brw_reg src
[3], dst
;
1678 for (unsigned int i
= 0; i
< 3; i
++) {
1679 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
1681 dst
= brw_reg_from_fs_reg(&inst
->dst
);
1683 brw_set_conditionalmod(p
, inst
->conditional_mod
);
1684 brw_set_predicate_control(p
, inst
->predicated
);
1686 switch (inst
->opcode
) {
1687 case BRW_OPCODE_MOV
:
1688 brw_MOV(p
, dst
, src
[0]);
1690 case BRW_OPCODE_ADD
:
1691 brw_ADD(p
, dst
, src
[0], src
[1]);
1693 case BRW_OPCODE_MUL
:
1694 brw_MUL(p
, dst
, src
[0], src
[1]);
1697 case BRW_OPCODE_FRC
:
1698 brw_FRC(p
, dst
, src
[0]);
1700 case BRW_OPCODE_RNDD
:
1701 brw_RNDD(p
, dst
, src
[0]);
1703 case BRW_OPCODE_RNDZ
:
1704 brw_RNDZ(p
, dst
, src
[0]);
1707 case BRW_OPCODE_AND
:
1708 brw_AND(p
, dst
, src
[0], src
[1]);
1711 brw_OR(p
, dst
, src
[0], src
[1]);
1713 case BRW_OPCODE_XOR
:
1714 brw_XOR(p
, dst
, src
[0], src
[1]);
1717 case BRW_OPCODE_CMP
:
1718 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1720 case BRW_OPCODE_SEL
:
1721 brw_SEL(p
, dst
, src
[0], src
[1]);
1725 assert(if_stack_depth
< 16);
1726 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
1729 case BRW_OPCODE_ELSE
:
1730 if_stack
[if_stack_depth
- 1] =
1731 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
1733 case BRW_OPCODE_ENDIF
:
1735 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
1739 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
1740 if_depth_in_loop
[loop_stack_depth
] = 0;
1743 case BRW_OPCODE_BREAK
:
1744 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
1745 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1747 case BRW_OPCODE_CONTINUE
:
1748 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
1749 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1752 case BRW_OPCODE_WHILE
: {
1753 struct brw_instruction
*inst0
, *inst1
;
1756 if (intel
->gen
== 5)
1759 assert(loop_stack_depth
> 0);
1761 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
1762 /* patch all the BREAK/CONT instructions from last BGNLOOP */
1763 while (inst0
> loop_stack
[loop_stack_depth
]) {
1765 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
1766 inst0
->bits3
.if_else
.jump_count
== 0) {
1767 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
1769 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
1770 inst0
->bits3
.if_else
.jump_count
== 0) {
1771 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
1779 case FS_OPCODE_SQRT
:
1780 case FS_OPCODE_EXP2
:
1781 case FS_OPCODE_LOG2
:
1785 generate_math(inst
, dst
, src
);
1787 case FS_OPCODE_LINTERP
:
1788 generate_linterp(inst
, dst
, src
);
1793 generate_tex(inst
, dst
, src
[0]);
1795 case FS_OPCODE_DISCARD
:
1796 generate_discard(inst
);
1798 case FS_OPCODE_FB_WRITE
:
1799 generate_fb_write(inst
);
1802 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
1803 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
1804 brw_opcodes
[inst
->opcode
].name
);
1806 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
1811 if (annotation_len
< p
->nr_insn
) {
1812 annotation_len
*= 2;
1813 if (annotation_len
< 16)
1814 annotation_len
= 16;
1816 this->annotation_string
= talloc_realloc(this->mem_ctx
,
1820 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
1826 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
1827 this->annotation_string
[i
] = inst
->annotation
;
1828 this->annotation_ir
[i
] = inst
->ir
;
1830 last_native_inst
= p
->nr_insn
;
1835 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
1837 struct brw_compile
*p
= &c
->func
;
1838 struct intel_context
*intel
= &brw
->intel
;
1839 GLcontext
*ctx
= &intel
->ctx
;
1840 struct brw_shader
*shader
= NULL
;
1841 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
1849 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
1850 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
1851 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
1858 /* We always use 8-wide mode, at least for now. For one, flow
1859 * control only works in 8-wide. Also, when we're fragment shader
1860 * bound, we're almost always under register pressure as well, so
1861 * 8-wide would save us from the performance cliff of spilling
1864 c
->dispatch_width
= 8;
1866 if (INTEL_DEBUG
& DEBUG_WM
) {
1867 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
1868 _mesa_print_ir(shader
->ir
, NULL
);
1872 /* Now the main event: Visit the shader IR and generate our FS IR for it.
1874 fs_visitor
v(c
, shader
);
1879 v
.emit_interpolation();
1881 /* Generate FS IR for main(). (the visitor only descends into
1882 * functions called "main").
1884 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
1885 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1891 v
.assign_curb_setup();
1892 v
.assign_urb_setup();
1898 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
1903 if (INTEL_DEBUG
& DEBUG_WM
) {
1904 const char *last_annotation_string
= NULL
;
1905 ir_instruction
*last_annotation_ir
= NULL
;
1907 printf("Native code for fragment shader %d:\n", prog
->Name
);
1908 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
1909 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
1910 last_annotation_ir
= v
.annotation_ir
[i
];
1911 if (last_annotation_ir
) {
1913 last_annotation_ir
->print();
1917 if (last_annotation_string
!= v
.annotation_string
[i
]) {
1918 last_annotation_string
= v
.annotation_string
[i
];
1919 if (last_annotation_string
)
1920 printf(" %s\n", last_annotation_string
);
1922 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
1927 c
->prog_data
.total_grf
= v
.grf_used
;
1928 c
->prog_data
.total_scratch
= 0;