2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "glsl/nir/glsl_types.h"
46 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
47 const fs_reg
*src
, unsigned sources
)
49 memset(this, 0, sizeof(*this));
51 this->src
= new fs_reg
[MAX2(sources
, 3)];
52 for (unsigned i
= 0; i
< sources
; i
++)
53 this->src
[i
] = src
[i
];
55 this->opcode
= opcode
;
57 this->sources
= sources
;
58 this->exec_size
= exec_size
;
60 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
62 assert(this->exec_size
!= 0);
64 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
66 /* This will be the case for almost all instructions. */
73 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
77 this->regs_written
= 0;
81 unreachable("Invalid destination register file");
84 this->writes_accumulator
= false;
89 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
92 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
94 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
99 init(opcode
, exec_size
, dst
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
105 const fs_reg src
[1] = { src0
};
106 init(opcode
, exec_size
, dst
, src
, 1);
109 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg
&src0
, const fs_reg
&src1
)
112 const fs_reg src
[2] = { src0
, src1
};
113 init(opcode
, exec_size
, dst
, src
, 2);
116 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
117 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
119 const fs_reg src
[3] = { src0
, src1
, src2
};
120 init(opcode
, exec_size
, dst
, src
, 3);
123 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
124 const fs_reg src
[], unsigned sources
)
126 init(opcode
, exec_width
, dst
, src
, sources
);
129 fs_inst::fs_inst(const fs_inst
&that
)
131 memcpy(this, &that
, sizeof(that
));
133 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
135 for (unsigned i
= 0; i
< that
.sources
; i
++)
136 this->src
[i
] = that
.src
[i
];
145 fs_inst::resize_sources(uint8_t num_sources
)
147 if (this->sources
!= num_sources
) {
148 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
150 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
151 src
[i
] = this->src
[i
];
155 this->sources
= num_sources
;
160 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
162 const fs_reg
&surf_index
,
163 const fs_reg
&varying_offset
,
164 uint32_t const_offset
)
166 /* We have our constant surface use a pitch of 4 bytes, so our index can
167 * be any component of a vector, and then we load 4 contiguous
168 * components starting from that.
170 * We break down the const_offset to a portion added to the variable
171 * offset and a portion done using reg_offset, which means that if you
172 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
173 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
174 * CSE can later notice that those loads are all the same and eliminate
175 * the redundant ones.
177 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
178 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
181 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
182 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
183 * u, v, r) as parameters, or we can just use the SIMD16 message
184 * consisting of (header, u). We choose the second, at the cost of a
185 * longer return length.
191 if (devinfo
->gen
>= 7)
192 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
194 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
196 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
197 fs_reg vec4_result
= fs_reg(VGRF
, alloc
.allocate(regs_written
), dst
.type
);
198 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
199 inst
->regs_written
= regs_written
;
201 if (devinfo
->gen
< 7) {
202 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
203 inst
->header_size
= 1;
204 if (devinfo
->gen
== 4)
207 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
210 bld
.MOV(dst
, offset(vec4_result
, bld
, ((const_offset
& 0xf) / 4) * scale
));
214 * A helper for MOV generation for fixing up broken hardware SEND dependency
218 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
220 /* The caller always wants uncompressed to emit the minimal extra
221 * dependencies, and to avoid having to deal with aligning its regs to 2.
223 const fs_builder ubld
= bld
.annotate("send dependency resolve")
226 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
230 fs_inst::equals(fs_inst
*inst
) const
232 return (opcode
== inst
->opcode
&&
233 dst
.equals(inst
->dst
) &&
234 src
[0].equals(inst
->src
[0]) &&
235 src
[1].equals(inst
->src
[1]) &&
236 src
[2].equals(inst
->src
[2]) &&
237 saturate
== inst
->saturate
&&
238 predicate
== inst
->predicate
&&
239 conditional_mod
== inst
->conditional_mod
&&
240 mlen
== inst
->mlen
&&
241 base_mrf
== inst
->base_mrf
&&
242 target
== inst
->target
&&
244 header_size
== inst
->header_size
&&
245 shadow_compare
== inst
->shadow_compare
&&
246 exec_size
== inst
->exec_size
&&
247 offset
== inst
->offset
);
251 fs_inst::overwrites_reg(const fs_reg
®
) const
253 return reg
.in_range(dst
, regs_written
);
257 fs_inst::is_send_from_grf() const
260 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
261 case SHADER_OPCODE_SHADER_TIME_ADD
:
262 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
263 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
264 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
265 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
266 case SHADER_OPCODE_UNTYPED_ATOMIC
:
267 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
268 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
269 case SHADER_OPCODE_TYPED_ATOMIC
:
270 case SHADER_OPCODE_TYPED_SURFACE_READ
:
271 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
272 case SHADER_OPCODE_URB_WRITE_SIMD8
:
273 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
274 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
275 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
276 case SHADER_OPCODE_URB_READ_SIMD8
:
277 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
279 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
280 return src
[1].file
== VGRF
;
281 case FS_OPCODE_FB_WRITE
:
282 return src
[0].file
== VGRF
;
285 return src
[0].file
== VGRF
;
292 * Returns true if this instruction's sources and destinations cannot
293 * safely be the same register.
295 * In most cases, a register can be written over safely by the same
296 * instruction that is its last use. For a single instruction, the
297 * sources are dereferenced before writing of the destination starts
300 * However, there are a few cases where this can be problematic:
302 * - Virtual opcodes that translate to multiple instructions in the
303 * code generator: if src == dst and one instruction writes the
304 * destination before a later instruction reads the source, then
305 * src will have been clobbered.
307 * - SIMD16 compressed instructions with certain regioning (see below).
309 * The register allocator uses this information to set up conflicts between
310 * GRF sources and the destination.
313 fs_inst::has_source_and_destination_hazard() const
316 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
317 /* Multiple partial writes to the destination */
320 /* The SIMD16 compressed instruction
322 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
324 * is actually decoded in hardware as:
326 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
327 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
329 * Which is safe. However, if we have uniform accesses
330 * happening, we get into trouble:
332 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
333 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
335 * Now our destination for the first instruction overwrote the
336 * second instruction's src0, and we get garbage for those 8
337 * pixels. There's a similar issue for the pre-gen6
338 * pixel_x/pixel_y, which are registers of 16-bit values and thus
339 * would get stomped by the first decode as well.
341 if (exec_size
== 16) {
342 for (int i
= 0; i
< sources
; i
++) {
343 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
344 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
345 src
[i
].type
== BRW_REGISTER_TYPE_W
||
346 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
347 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
357 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
359 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
362 fs_reg reg
= this->src
[0];
363 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
366 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
369 for (int i
= 0; i
< this->sources
; i
++) {
370 reg
.type
= this->src
[i
].type
;
371 if (!this->src
[i
].equals(reg
))
374 if (i
< this->header_size
) {
377 reg
.reg_offset
+= this->exec_size
/ 8;
385 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
387 if (devinfo
->gen
== 6 && is_math())
390 if (is_send_from_grf())
393 if (!backend_instruction::can_do_source_mods())
400 fs_inst::can_change_types() const
402 return dst
.type
== src
[0].type
&&
403 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
404 (opcode
== BRW_OPCODE_MOV
||
405 (opcode
== BRW_OPCODE_SEL
&&
406 dst
.type
== src
[1].type
&&
407 predicate
!= BRW_PREDICATE_NONE
&&
408 !src
[1].abs
&& !src
[1].negate
));
412 fs_inst::has_side_effects() const
414 return this->eot
|| backend_instruction::has_side_effects();
420 memset(this, 0, sizeof(*this));
424 /** Generic unset register constructor. */
428 this->file
= BAD_FILE
;
431 fs_reg::fs_reg(struct ::brw_reg reg
) :
434 this->reg_offset
= 0;
435 this->subreg_offset
= 0;
436 this->reladdr
= NULL
;
438 if (this->file
== IMM
&&
439 (this->type
!= BRW_REGISTER_TYPE_V
&&
440 this->type
!= BRW_REGISTER_TYPE_UV
&&
441 this->type
!= BRW_REGISTER_TYPE_VF
)) {
447 fs_reg::equals(const fs_reg
&r
) const
449 return (this->backend_reg::equals(r
) &&
450 subreg_offset
== r
.subreg_offset
&&
451 !reladdr
&& !r
.reladdr
&&
456 fs_reg::set_smear(unsigned subreg
)
458 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
459 subreg_offset
= subreg
* type_sz(type
);
465 fs_reg::is_contiguous() const
471 fs_reg::component_size(unsigned width
) const
473 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
476 return MAX2(width
* stride
, 1) * type_sz(type
);
480 type_size_scalar(const struct glsl_type
*type
)
482 unsigned int size
, i
;
484 switch (type
->base_type
) {
487 case GLSL_TYPE_FLOAT
:
489 return type
->components();
490 case GLSL_TYPE_ARRAY
:
491 return type_size_scalar(type
->fields
.array
) * type
->length
;
492 case GLSL_TYPE_STRUCT
:
494 for (i
= 0; i
< type
->length
; i
++) {
495 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
498 case GLSL_TYPE_SAMPLER
:
499 /* Samplers take up no register space, since they're baked in at
503 case GLSL_TYPE_ATOMIC_UINT
:
505 case GLSL_TYPE_SUBROUTINE
:
507 case GLSL_TYPE_IMAGE
:
508 return BRW_IMAGE_PARAM_SIZE
;
510 case GLSL_TYPE_ERROR
:
511 case GLSL_TYPE_INTERFACE
:
512 case GLSL_TYPE_DOUBLE
:
513 unreachable("not reached");
520 * Returns the number of scalar components needed to store type, assuming
521 * that vectors are padded out to vec4.
523 * This has the packing rules of type_size_vec4(), but counts components
524 * similar to type_size_scalar().
527 type_size_vec4_times_4(const struct glsl_type
*type
)
529 return 4 * type_size_vec4(type
);
533 * Create a MOV to read the timestamp register.
535 * The caller is responsible for emitting the MOV. The return value is
536 * the destination of the MOV, with extra parameters set.
539 fs_visitor::get_timestamp(const fs_builder
&bld
)
541 assert(devinfo
->gen
>= 7);
543 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
546 BRW_REGISTER_TYPE_UD
));
548 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
550 /* We want to read the 3 fields we care about even if it's not enabled in
553 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
559 fs_visitor::emit_shader_time_begin()
561 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
563 /* We want only the low 32 bits of the timestamp. Since it's running
564 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
565 * which is plenty of time for our purposes. It is identical across the
566 * EUs, but since it's tracking GPU core speed it will increment at a
567 * varying rate as render P-states change.
569 shader_start_time
.set_smear(0);
573 fs_visitor::emit_shader_time_end()
575 /* Insert our code just before the final SEND with EOT. */
576 exec_node
*end
= this->instructions
.get_tail();
577 assert(end
&& ((fs_inst
*) end
)->eot
);
578 const fs_builder ibld
= bld
.annotate("shader time end")
579 .exec_all().at(NULL
, end
);
581 fs_reg shader_end_time
= get_timestamp(ibld
);
583 /* We only use the low 32 bits of the timestamp - see
584 * emit_shader_time_begin()).
586 * We could also check if render P-states have changed (or anything
587 * else that might disrupt timing) by setting smear to 2 and checking if
588 * that field is != 0.
590 shader_end_time
.set_smear(0);
592 /* Check that there weren't any timestamp reset events (assuming these
593 * were the only two timestamp reads that happened).
595 fs_reg reset
= shader_end_time
;
597 set_condmod(BRW_CONDITIONAL_Z
,
598 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
599 ibld
.IF(BRW_PREDICATE_NORMAL
);
601 fs_reg start
= shader_start_time
;
603 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
606 const fs_builder cbld
= ibld
.group(1, 0);
607 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
609 /* If there were no instructions between the two timestamp gets, the diff
610 * is 2 cycles. Remove that overhead, so I can forget about that when
611 * trying to determine the time taken for single instructions.
613 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
614 SHADER_TIME_ADD(cbld
, 0, diff
);
615 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
616 ibld
.emit(BRW_OPCODE_ELSE
);
617 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
618 ibld
.emit(BRW_OPCODE_ENDIF
);
622 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
623 int shader_time_subindex
,
626 int index
= shader_time_index
* 3 + shader_time_subindex
;
627 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
630 if (dispatch_width
== 8)
631 payload
= vgrf(glsl_type::uvec2_type
);
633 payload
= vgrf(glsl_type::uint_type
);
635 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
639 fs_visitor::vfail(const char *format
, va_list va
)
648 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
649 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
651 this->fail_msg
= msg
;
654 fprintf(stderr
, "%s", msg
);
659 fs_visitor::fail(const char *format
, ...)
663 va_start(va
, format
);
669 * Mark this program as impossible to compile in SIMD16 mode.
671 * During the SIMD8 compile (which happens first), we can detect and flag
672 * things that are unsupported in SIMD16 mode, so the compiler can skip
673 * the SIMD16 compile altogether.
675 * During a SIMD16 compile (if one happens anyway), this just calls fail().
678 fs_visitor::no16(const char *msg
)
680 if (dispatch_width
== 16) {
683 simd16_unsupported
= true;
685 compiler
->shader_perf_log(log_data
,
686 "SIMD16 shader failed to compile: %s", msg
);
691 * Returns true if the instruction has a flag that means it won't
692 * update an entire destination register.
694 * For example, dead code elimination and live variable analysis want to know
695 * when a write to a variable screens off any preceding values that were in
699 fs_inst::is_partial_write() const
701 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
702 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
703 !this->dst
.is_contiguous());
707 fs_inst::components_read(unsigned i
) const
710 case FS_OPCODE_LINTERP
:
716 case FS_OPCODE_PIXEL_X
:
717 case FS_OPCODE_PIXEL_Y
:
721 case FS_OPCODE_FB_WRITE_LOGICAL
:
722 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
723 /* First/second FB write color. */
725 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
729 case SHADER_OPCODE_TEX_LOGICAL
:
730 case SHADER_OPCODE_TXD_LOGICAL
:
731 case SHADER_OPCODE_TXF_LOGICAL
:
732 case SHADER_OPCODE_TXL_LOGICAL
:
733 case SHADER_OPCODE_TXS_LOGICAL
:
734 case FS_OPCODE_TXB_LOGICAL
:
735 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
736 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
737 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
738 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
739 case SHADER_OPCODE_LOD_LOGICAL
:
740 case SHADER_OPCODE_TG4_LOGICAL
:
741 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
742 assert(src
[8].file
== IMM
&& src
[9].file
== IMM
);
743 /* Texture coordinates. */
746 /* Texture derivatives. */
747 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
749 /* Texture offset. */
753 else if (i
== 5 && opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
758 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
759 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
760 assert(src
[3].file
== IMM
);
761 /* Surface coordinates. */
764 /* Surface operation source (ignored for reads). */
770 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
771 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
772 assert(src
[3].file
== IMM
&&
774 /* Surface coordinates. */
777 /* Surface operation source. */
783 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
784 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
785 assert(src
[3].file
== IMM
&&
787 const unsigned op
= src
[4].ud
;
788 /* Surface coordinates. */
791 /* Surface operation source. */
792 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
794 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
795 op
== BRW_AOP_PREDEC
))
807 fs_inst::regs_read(int arg
) const
810 case FS_OPCODE_FB_WRITE
:
811 case SHADER_OPCODE_URB_WRITE_SIMD8
:
812 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
813 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
814 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
815 case SHADER_OPCODE_URB_READ_SIMD8
:
816 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
817 case SHADER_OPCODE_UNTYPED_ATOMIC
:
818 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
819 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
820 case SHADER_OPCODE_TYPED_ATOMIC
:
821 case SHADER_OPCODE_TYPED_SURFACE_READ
:
822 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
823 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
828 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
829 /* The payload is actually stored in src1 */
834 case FS_OPCODE_LINTERP
:
839 case SHADER_OPCODE_LOAD_PAYLOAD
:
840 if (arg
< this->header_size
)
844 case CS_OPCODE_CS_TERMINATE
:
845 case SHADER_OPCODE_BARRIER
:
848 case SHADER_OPCODE_MOV_INDIRECT
:
850 assert(src
[2].file
== IMM
);
851 unsigned region_length
= src
[2].ud
;
853 if (src
[0].file
== FIXED_GRF
) {
854 /* If the start of the region is not register aligned, then
855 * there's some portion of the register that's technically
856 * unread at the beginning.
858 * However, the register allocator works in terms of whole
859 * registers, and does not use subnr. It assumes that the
860 * read starts at the beginning of the register, and extends
861 * regs_read() whole registers beyond that.
863 * To compensate, we extend the region length to include this
864 * unread portion at the beginning.
867 region_length
+= src
[0].subnr
* type_sz(src
[0].type
);
869 return DIV_ROUND_UP(region_length
, REG_SIZE
);
871 assert(!"Invalid register file");
877 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
882 switch (src
[arg
].file
) {
892 return DIV_ROUND_UP(components_read(arg
) *
893 src
[arg
].component_size(exec_size
),
896 unreachable("MRF registers are not allowed as sources");
902 fs_inst::reads_flag() const
908 fs_inst::writes_flag() const
910 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
911 opcode
!= BRW_OPCODE_IF
&&
912 opcode
!= BRW_OPCODE_WHILE
)) ||
913 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
917 * Returns how many MRFs an FS opcode will write over.
919 * Note that this is not the 0 or 1 implied writes in an actual gen
920 * instruction -- the FS opcodes often generate MOVs in addition.
923 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
928 if (inst
->base_mrf
== -1)
931 switch (inst
->opcode
) {
932 case SHADER_OPCODE_RCP
:
933 case SHADER_OPCODE_RSQ
:
934 case SHADER_OPCODE_SQRT
:
935 case SHADER_OPCODE_EXP2
:
936 case SHADER_OPCODE_LOG2
:
937 case SHADER_OPCODE_SIN
:
938 case SHADER_OPCODE_COS
:
939 return 1 * dispatch_width
/ 8;
940 case SHADER_OPCODE_POW
:
941 case SHADER_OPCODE_INT_QUOTIENT
:
942 case SHADER_OPCODE_INT_REMAINDER
:
943 return 2 * dispatch_width
/ 8;
944 case SHADER_OPCODE_TEX
:
946 case SHADER_OPCODE_TXD
:
947 case SHADER_OPCODE_TXF
:
948 case SHADER_OPCODE_TXF_CMS
:
949 case SHADER_OPCODE_TXF_CMS_W
:
950 case SHADER_OPCODE_TXF_MCS
:
951 case SHADER_OPCODE_TG4
:
952 case SHADER_OPCODE_TG4_OFFSET
:
953 case SHADER_OPCODE_TXL
:
954 case SHADER_OPCODE_TXS
:
955 case SHADER_OPCODE_LOD
:
956 case SHADER_OPCODE_SAMPLEINFO
:
958 case FS_OPCODE_FB_WRITE
:
960 case FS_OPCODE_GET_BUFFER_SIZE
:
961 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
962 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
964 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
966 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
968 case SHADER_OPCODE_UNTYPED_ATOMIC
:
969 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
970 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
971 case SHADER_OPCODE_TYPED_ATOMIC
:
972 case SHADER_OPCODE_TYPED_SURFACE_READ
:
973 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
974 case SHADER_OPCODE_URB_WRITE_SIMD8
:
975 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
976 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
977 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
978 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
979 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
980 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
981 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
984 unreachable("not reached");
989 fs_visitor::vgrf(const glsl_type
*const type
)
991 int reg_width
= dispatch_width
/ 8;
992 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
993 brw_type_for_base_type(type
));
996 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1001 this->type
= BRW_REGISTER_TYPE_F
;
1002 this->stride
= (file
== UNIFORM
? 0 : 1);
1005 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1011 this->stride
= (file
== UNIFORM
? 0 : 1);
1014 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1015 * This brings in those uniform definitions
1018 fs_visitor::import_uniforms(fs_visitor
*v
)
1020 this->push_constant_loc
= v
->push_constant_loc
;
1021 this->pull_constant_loc
= v
->pull_constant_loc
;
1022 this->uniforms
= v
->uniforms
;
1023 this->param_size
= v
->param_size
;
1027 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
1028 bool origin_upper_left
)
1030 assert(stage
== MESA_SHADER_FRAGMENT
);
1031 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1032 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1034 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
1036 /* gl_FragCoord.x */
1037 if (pixel_center_integer
) {
1038 bld
.MOV(wpos
, this->pixel_x
);
1040 bld
.ADD(wpos
, this->pixel_x
, brw_imm_f(0.5f
));
1042 wpos
= offset(wpos
, bld
, 1);
1044 /* gl_FragCoord.y */
1045 if (!flip
&& pixel_center_integer
) {
1046 bld
.MOV(wpos
, this->pixel_y
);
1048 fs_reg pixel_y
= this->pixel_y
;
1049 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
1052 pixel_y
.negate
= true;
1053 offset
+= key
->drawable_height
- 1.0f
;
1056 bld
.ADD(wpos
, pixel_y
, brw_imm_f(offset
));
1058 wpos
= offset(wpos
, bld
, 1);
1060 /* gl_FragCoord.z */
1061 if (devinfo
->gen
>= 6) {
1062 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1064 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1065 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1066 interp_reg(VARYING_SLOT_POS
, 2));
1068 wpos
= offset(wpos
, bld
, 1);
1070 /* gl_FragCoord.w: Already set up in emit_interpolation */
1071 bld
.MOV(wpos
, this->wpos_w
);
1077 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1078 glsl_interp_qualifier interpolation_mode
,
1079 bool is_centroid
, bool is_sample
)
1081 brw_wm_barycentric_interp_mode barycoord_mode
;
1082 if (devinfo
->gen
>= 6) {
1084 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1085 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1087 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1088 } else if (is_sample
) {
1089 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1090 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1092 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1094 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1095 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1097 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1100 /* On Ironlake and below, there is only one interpolation mode.
1101 * Centroid interpolation doesn't mean anything on this hardware --
1102 * there is no multisampling.
1104 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1106 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1107 this->delta_xy
[barycoord_mode
], interp
);
1111 fs_visitor::emit_general_interpolation(fs_reg
*attr
, const char *name
,
1112 const glsl_type
*type
,
1113 glsl_interp_qualifier interpolation_mode
,
1114 int *location
, bool mod_centroid
,
1117 assert(stage
== MESA_SHADER_FRAGMENT
);
1118 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1119 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1121 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1123 *location
== VARYING_SLOT_COL0
|| *location
== VARYING_SLOT_COL1
;
1124 if (key
->flat_shade
&& is_gl_Color
) {
1125 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1127 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1131 if (type
->is_array() || type
->is_matrix()) {
1132 const glsl_type
*elem_type
= glsl_get_array_element(type
);
1133 const unsigned length
= glsl_get_length(type
);
1135 for (unsigned i
= 0; i
< length
; i
++) {
1136 emit_general_interpolation(attr
, name
, elem_type
, interpolation_mode
,
1137 location
, mod_centroid
, mod_sample
);
1139 } else if (type
->is_record()) {
1140 for (unsigned i
= 0; i
< type
->length
; i
++) {
1141 const glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
1142 emit_general_interpolation(attr
, name
, field_type
, interpolation_mode
,
1143 location
, mod_centroid
, mod_sample
);
1146 assert(type
->is_scalar() || type
->is_vector());
1148 if (prog_data
->urb_setup
[*location
] == -1) {
1149 /* If there's no incoming setup data for this slot, don't
1150 * emit interpolation for it.
1152 *attr
= offset(*attr
, bld
, type
->vector_elements
);
1157 attr
->type
= brw_type_for_base_type(type
->get_scalar_type());
1159 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1160 /* Constant interpolation (flat shading) case. The SF has
1161 * handed us defined values in only the constant offset
1162 * field of the setup reg.
1164 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1165 struct brw_reg interp
= interp_reg(*location
, i
);
1166 interp
= suboffset(interp
, 3);
1167 interp
.type
= attr
->type
;
1168 bld
.emit(FS_OPCODE_CINTERP
, *attr
, fs_reg(interp
));
1169 *attr
= offset(*attr
, bld
, 1);
1172 /* Smooth/noperspective interpolation case. */
1173 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1174 struct brw_reg interp
= interp_reg(*location
, i
);
1175 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1176 /* Get the pixel/sample mask into f0 so that we know
1177 * which pixels are lit. Then, for each channel that is
1178 * unlit, replace the centroid data with non-centroid
1181 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1184 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1186 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1187 inst
->predicate_inverse
= true;
1188 if (devinfo
->has_pln
)
1189 inst
->no_dd_clear
= true;
1191 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1192 mod_centroid
&& !key
->persample_shading
,
1193 mod_sample
|| key
->persample_shading
);
1194 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1195 inst
->predicate_inverse
= false;
1196 if (devinfo
->has_pln
)
1197 inst
->no_dd_check
= true;
1200 emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1201 mod_centroid
&& !key
->persample_shading
,
1202 mod_sample
|| key
->persample_shading
);
1204 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1205 bld
.MUL(*attr
, *attr
, this->pixel_w
);
1207 *attr
= offset(*attr
, bld
, 1);
1215 fs_visitor::emit_frontfacing_interpolation()
1217 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1219 if (devinfo
->gen
>= 6) {
1220 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1221 * a boolean result from this (~0/true or 0/false).
1223 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1224 * this task in only one instruction:
1225 * - a negation source modifier will flip the bit; and
1226 * - a W -> D type conversion will sign extend the bit into the high
1227 * word of the destination.
1229 * An ASR 15 fills the low word of the destination.
1231 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1234 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1236 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1237 * a boolean result from this (1/true or 0/false).
1239 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1240 * the negation source modifier to flip it. Unfortunately the SHR
1241 * instruction only operates on UD (or D with an abs source modifier)
1242 * sources without negation.
1244 * Instead, use ASR (which will give ~0/true or 0/false).
1246 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1249 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1256 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1258 assert(stage
== MESA_SHADER_FRAGMENT
);
1259 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1260 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1262 if (key
->compute_pos_offset
) {
1263 /* Convert int_sample_pos to floating point */
1264 bld
.MOV(dst
, int_sample_pos
);
1265 /* Scale to the range [0, 1] */
1266 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1269 /* From ARB_sample_shading specification:
1270 * "When rendering to a non-multisample buffer, or if multisample
1271 * rasterization is disabled, gl_SamplePosition will always be
1274 bld
.MOV(dst
, brw_imm_f(0.5f
));
1279 fs_visitor::emit_samplepos_setup()
1281 assert(devinfo
->gen
>= 6);
1283 const fs_builder abld
= bld
.annotate("compute sample position");
1284 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1286 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1287 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1289 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1290 * mode will be enabled.
1292 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1293 * R31.1:0 Position Offset X/Y for Slot[3:0]
1294 * R31.3:2 Position Offset X/Y for Slot[7:4]
1297 * The X, Y sample positions come in as bytes in thread payload. So, read
1298 * the positions using vstride=16, width=8, hstride=2.
1300 struct brw_reg sample_pos_reg
=
1301 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1302 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1304 if (dispatch_width
== 8) {
1305 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1307 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1308 abld
.half(1).MOV(half(int_sample_x
, 1),
1309 fs_reg(suboffset(sample_pos_reg
, 16)));
1311 /* Compute gl_SamplePosition.x */
1312 compute_sample_position(pos
, int_sample_x
);
1313 pos
= offset(pos
, abld
, 1);
1314 if (dispatch_width
== 8) {
1315 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1317 abld
.half(0).MOV(half(int_sample_y
, 0),
1318 fs_reg(suboffset(sample_pos_reg
, 1)));
1319 abld
.half(1).MOV(half(int_sample_y
, 1),
1320 fs_reg(suboffset(sample_pos_reg
, 17)));
1322 /* Compute gl_SamplePosition.y */
1323 compute_sample_position(pos
, int_sample_y
);
1328 fs_visitor::emit_sampleid_setup()
1330 assert(stage
== MESA_SHADER_FRAGMENT
);
1331 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1332 assert(devinfo
->gen
>= 6);
1334 const fs_builder abld
= bld
.annotate("compute sample id");
1335 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1337 if (key
->compute_sample_id
) {
1338 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1340 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1342 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1343 * 8x multisampling, subspan 0 will represent sample N (where N
1344 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1345 * 7. We can find the value of N by looking at R0.0 bits 7:6
1346 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1347 * (since samples are always delivered in pairs). That is, we
1348 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1349 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1350 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1351 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1352 * populating a temporary variable with the sequence (0, 1, 2, 3),
1353 * and then reading from it using vstride=1, width=4, hstride=0.
1354 * These computations hold good for 4x multisampling as well.
1356 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1357 * the first four slots are sample 0 of subspan 0; the next four
1358 * are sample 1 of subspan 0; the third group is sample 0 of
1359 * subspan 1, and finally sample 1 of subspan 1.
1362 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1363 * accomodate 16x MSAA.
1365 unsigned sspi_mask
= devinfo
->gen
>= 9 ? 0x1c0 : 0xc0;
1367 abld
.exec_all().group(1, 0)
1368 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1369 brw_imm_ud(sspi_mask
));
1370 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1372 /* This works for both SIMD8 and SIMD16 */
1373 abld
.exec_all().group(4, 0)
1374 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1376 /* This special instruction takes care of setting vstride=1,
1377 * width=4, hstride=0 of t2 during an ADD instruction.
1379 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1381 /* As per GL_ARB_sample_shading specification:
1382 * "When rendering to a non-multisample buffer, or if multisample
1383 * rasterization is disabled, gl_SampleID will always be zero."
1385 abld
.MOV(*reg
, brw_imm_d(0));
1392 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1394 if (!src
.abs
&& !src
.negate
)
1397 fs_reg temp
= bld
.vgrf(src
.type
);
1404 fs_visitor::emit_discard_jump()
1406 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1408 /* For performance, after a discard, jump to the end of the
1409 * shader if all relevant channels have been discarded.
1411 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1412 discard_jump
->flag_subreg
= 1;
1414 discard_jump
->predicate
= (dispatch_width
== 8)
1415 ? BRW_PREDICATE_ALIGN1_ANY8H
1416 : BRW_PREDICATE_ALIGN1_ANY16H
;
1417 discard_jump
->predicate_inverse
= true;
1421 fs_visitor::emit_gs_thread_end()
1423 assert(stage
== MESA_SHADER_GEOMETRY
);
1425 struct brw_gs_prog_data
*gs_prog_data
=
1426 (struct brw_gs_prog_data
*) prog_data
;
1428 if (gs_compile
->control_data_header_size_bits
> 0) {
1429 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1432 const fs_builder abld
= bld
.annotate("thread end");
1435 if (gs_prog_data
->static_vertex_count
!= -1) {
1436 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1437 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1438 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1439 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1440 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1443 /* Delete now dead instructions. */
1444 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1450 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1454 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1455 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1456 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1459 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1460 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1461 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1462 sources
[1] = this->final_gs_vertex_count
;
1463 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1464 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1472 fs_visitor::assign_curb_setup()
1474 if (dispatch_width
== 8) {
1475 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1477 if (stage
== MESA_SHADER_FRAGMENT
) {
1478 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1479 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1480 } else if (stage
== MESA_SHADER_COMPUTE
) {
1481 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1482 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1484 unreachable("Unsupported shader type!");
1488 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1490 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1491 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1492 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1493 if (inst
->src
[i
].file
== UNIFORM
) {
1494 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1496 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1497 constant_nr
= push_constant_loc
[uniform_nr
];
1499 /* Section 5.11 of the OpenGL 4.1 spec says:
1500 * "Out-of-bounds reads return undefined values, which include
1501 * values from other variables of the active program or zero."
1502 * Just return the first push constant.
1507 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1510 brw_reg
.abs
= inst
->src
[i
].abs
;
1511 brw_reg
.negate
= inst
->src
[i
].negate
;
1513 assert(inst
->src
[i
].stride
== 0);
1514 inst
->src
[i
] = byte_offset(
1515 retype(brw_reg
, inst
->src
[i
].type
),
1516 inst
->src
[i
].subreg_offset
);
1521 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1522 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1526 fs_visitor::calculate_urb_setup()
1528 assert(stage
== MESA_SHADER_FRAGMENT
);
1529 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1530 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1532 memset(prog_data
->urb_setup
, -1,
1533 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1536 /* Figure out where each of the incoming setup attributes lands. */
1537 if (devinfo
->gen
>= 6) {
1538 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1539 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1540 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1541 * first 16 varying inputs, so we can put them wherever we want.
1542 * Just put them in order.
1544 * This is useful because it means that (a) inputs not used by the
1545 * fragment shader won't take up valuable register space, and (b) we
1546 * won't have to recompile the fragment shader if it gets paired with
1547 * a different vertex (or geometry) shader.
1549 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1550 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1551 BITFIELD64_BIT(i
)) {
1552 prog_data
->urb_setup
[i
] = urb_next
++;
1556 bool include_vue_header
=
1557 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1559 /* We have enough input varyings that the SF/SBE pipeline stage can't
1560 * arbitrarily rearrange them to suit our whim; we have to put them
1561 * in an order that matches the output of the previous pipeline stage
1562 * (geometry or vertex shader).
1564 struct brw_vue_map prev_stage_vue_map
;
1565 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1566 key
->input_slots_valid
,
1567 nir
->info
.separate_shader
);
1569 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1571 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1572 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1574 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1575 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1576 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1577 BITFIELD64_BIT(varying
))) {
1578 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1581 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1584 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1585 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1586 /* Point size is packed into the header, not as a general attribute */
1587 if (i
== VARYING_SLOT_PSIZ
)
1590 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1591 /* The back color slot is skipped when the front color is
1592 * also written to. In addition, some slots can be
1593 * written in the vertex shader and not read in the
1594 * fragment shader. So the register number must always be
1595 * incremented, mapped or not.
1597 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1598 prog_data
->urb_setup
[i
] = urb_next
;
1604 * It's a FS only attribute, and we did interpolation for this attribute
1605 * in SF thread. So, count it here, too.
1607 * See compile_sf_prog() for more info.
1609 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1610 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1613 prog_data
->num_varying_inputs
= urb_next
;
1617 fs_visitor::assign_urb_setup()
1619 assert(stage
== MESA_SHADER_FRAGMENT
);
1620 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1622 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1624 /* Offset all the urb_setup[] index by the actual position of the
1625 * setup regs, now that the location of the constants has been chosen.
1627 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1628 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1629 assert(inst
->src
[1].file
== FIXED_GRF
);
1630 inst
->src
[1].nr
+= urb_start
;
1633 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1634 assert(inst
->src
[0].file
== FIXED_GRF
);
1635 inst
->src
[0].nr
+= urb_start
;
1639 /* Each attribute is 4 setup channels, each of which is half a reg. */
1640 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1644 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1646 for (int i
= 0; i
< inst
->sources
; i
++) {
1647 if (inst
->src
[i
].file
== ATTR
) {
1648 int grf
= payload
.num_regs
+
1649 prog_data
->curb_read_length
+
1651 inst
->src
[i
].reg_offset
;
1653 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : inst
->exec_size
;
1654 struct brw_reg reg
=
1655 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1656 inst
->src
[i
].subreg_offset
),
1657 inst
->exec_size
* inst
->src
[i
].stride
,
1658 width
, inst
->src
[i
].stride
);
1659 reg
.abs
= inst
->src
[i
].abs
;
1660 reg
.negate
= inst
->src
[i
].negate
;
1668 fs_visitor::assign_vs_urb_setup()
1670 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1672 assert(stage
== MESA_SHADER_VERTEX
);
1673 int count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1674 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
||
1675 vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1678 /* Each attribute is 4 regs. */
1679 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1681 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1683 /* Rewrite all ATTR file references to the hw grf that they land in. */
1684 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1685 convert_attr_sources_to_hw_regs(inst
);
1690 fs_visitor::assign_tes_urb_setup()
1692 assert(stage
== MESA_SHADER_TESS_EVAL
);
1694 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1696 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1698 /* Rewrite all ATTR file references to HW_REGs. */
1699 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1700 convert_attr_sources_to_hw_regs(inst
);
1705 fs_visitor::assign_gs_urb_setup()
1707 assert(stage
== MESA_SHADER_GEOMETRY
);
1709 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1711 first_non_payload_grf
+=
1712 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1714 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1715 /* Rewrite all ATTR file references to GRFs. */
1716 convert_attr_sources_to_hw_regs(inst
);
1722 * Split large virtual GRFs into separate components if we can.
1724 * This is mostly duplicated with what brw_fs_vector_splitting does,
1725 * but that's really conservative because it's afraid of doing
1726 * splitting that doesn't result in real progress after the rest of
1727 * the optimization phases, which would cause infinite looping in
1728 * optimization. We can do it once here, safely. This also has the
1729 * opportunity to split interpolated values, or maybe even uniforms,
1730 * which we don't have at the IR level.
1732 * We want to split, because virtual GRFs are what we register
1733 * allocate and spill (due to contiguousness requirements for some
1734 * instructions), and they're what we naturally generate in the
1735 * codegen process, but most virtual GRFs don't actually need to be
1736 * contiguous sets of GRFs. If we split, we'll end up with reduced
1737 * live intervals and better dead code elimination and coalescing.
1740 fs_visitor::split_virtual_grfs()
1742 int num_vars
= this->alloc
.count
;
1744 /* Count the total number of registers */
1746 int vgrf_to_reg
[num_vars
];
1747 for (int i
= 0; i
< num_vars
; i
++) {
1748 vgrf_to_reg
[i
] = reg_count
;
1749 reg_count
+= alloc
.sizes
[i
];
1752 /* An array of "split points". For each register slot, this indicates
1753 * if this slot can be separated from the previous slot. Every time an
1754 * instruction uses multiple elements of a register (as a source or
1755 * destination), we mark the used slots as inseparable. Then we go
1756 * through and split the registers into the smallest pieces we can.
1758 bool split_points
[reg_count
];
1759 memset(split_points
, 0, sizeof(split_points
));
1761 /* Mark all used registers as fully splittable */
1762 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1763 if (inst
->dst
.file
== VGRF
) {
1764 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1765 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1766 split_points
[reg
+ j
] = true;
1769 for (int i
= 0; i
< inst
->sources
; i
++) {
1770 if (inst
->src
[i
].file
== VGRF
) {
1771 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1772 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1773 split_points
[reg
+ j
] = true;
1778 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1779 if (inst
->dst
.file
== VGRF
) {
1780 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1781 for (int j
= 1; j
< inst
->regs_written
; j
++)
1782 split_points
[reg
+ j
] = false;
1784 for (int i
= 0; i
< inst
->sources
; i
++) {
1785 if (inst
->src
[i
].file
== VGRF
) {
1786 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1787 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1788 split_points
[reg
+ j
] = false;
1793 int new_virtual_grf
[reg_count
];
1794 int new_reg_offset
[reg_count
];
1797 for (int i
= 0; i
< num_vars
; i
++) {
1798 /* The first one should always be 0 as a quick sanity check. */
1799 assert(split_points
[reg
] == false);
1802 new_reg_offset
[reg
] = 0;
1807 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1808 /* If this is a split point, reset the offset to 0 and allocate a
1809 * new virtual GRF for the previous offset many registers
1811 if (split_points
[reg
]) {
1812 assert(offset
<= MAX_VGRF_SIZE
);
1813 int grf
= alloc
.allocate(offset
);
1814 for (int k
= reg
- offset
; k
< reg
; k
++)
1815 new_virtual_grf
[k
] = grf
;
1818 new_reg_offset
[reg
] = offset
;
1823 /* The last one gets the original register number */
1824 assert(offset
<= MAX_VGRF_SIZE
);
1825 alloc
.sizes
[i
] = offset
;
1826 for (int k
= reg
- offset
; k
< reg
; k
++)
1827 new_virtual_grf
[k
] = i
;
1829 assert(reg
== reg_count
);
1831 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1832 if (inst
->dst
.file
== VGRF
) {
1833 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1834 inst
->dst
.nr
= new_virtual_grf
[reg
];
1835 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1836 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1838 for (int i
= 0; i
< inst
->sources
; i
++) {
1839 if (inst
->src
[i
].file
== VGRF
) {
1840 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1841 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1842 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1843 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1847 invalidate_live_intervals();
1851 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1853 * During code generation, we create tons of temporary variables, many of
1854 * which get immediately killed and are never used again. Yet, in later
1855 * optimization and analysis passes, such as compute_live_intervals, we need
1856 * to loop over all the virtual GRFs. Compacting them can save a lot of
1860 fs_visitor::compact_virtual_grfs()
1862 bool progress
= false;
1863 int remap_table
[this->alloc
.count
];
1864 memset(remap_table
, -1, sizeof(remap_table
));
1866 /* Mark which virtual GRFs are used. */
1867 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1868 if (inst
->dst
.file
== VGRF
)
1869 remap_table
[inst
->dst
.nr
] = 0;
1871 for (int i
= 0; i
< inst
->sources
; i
++) {
1872 if (inst
->src
[i
].file
== VGRF
)
1873 remap_table
[inst
->src
[i
].nr
] = 0;
1877 /* Compact the GRF arrays. */
1879 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1880 if (remap_table
[i
] == -1) {
1881 /* We just found an unused register. This means that we are
1882 * actually going to compact something.
1886 remap_table
[i
] = new_index
;
1887 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1888 invalidate_live_intervals();
1893 this->alloc
.count
= new_index
;
1895 /* Patch all the instructions to use the newly renumbered registers */
1896 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1897 if (inst
->dst
.file
== VGRF
)
1898 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1900 for (int i
= 0; i
< inst
->sources
; i
++) {
1901 if (inst
->src
[i
].file
== VGRF
)
1902 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1906 /* Patch all the references to delta_xy, since they're used in register
1907 * allocation. If they're unused, switch them to BAD_FILE so we don't
1908 * think some random VGRF is delta_xy.
1910 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1911 if (delta_xy
[i
].file
== VGRF
) {
1912 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1913 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1915 delta_xy
[i
].file
= BAD_FILE
;
1924 * Assign UNIFORM file registers to either push constants or pull constants.
1926 * We allow a fragment shader to have more than the specified minimum
1927 * maximum number of fragment shader uniform components (64). If
1928 * there are too many of these, they'd fill up all of register space.
1929 * So, this will push some of them out to the pull constant buffer and
1930 * update the program to load them. We also use pull constants for all
1931 * indirect constant loads because we don't support indirect accesses in
1935 fs_visitor::assign_constant_locations()
1937 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1938 if (dispatch_width
!= 8)
1941 unsigned int num_pull_constants
= 0;
1943 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1944 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1946 bool is_live
[uniforms
];
1947 memset(is_live
, 0, sizeof(is_live
));
1949 /* First, we walk through the instructions and do two things:
1951 * 1) Figure out which uniforms are live.
1953 * 2) Find all indirect access of uniform arrays and flag them as needing
1954 * to go into the pull constant buffer.
1956 * Note that we don't move constant-indexed accesses to arrays. No
1957 * testing has been done of the performance impact of this choice.
1959 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1960 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1961 if (inst
->src
[i
].file
!= UNIFORM
)
1964 if (inst
->src
[i
].reladdr
) {
1965 int uniform
= inst
->src
[i
].nr
;
1967 /* If this array isn't already present in the pull constant buffer,
1970 if (pull_constant_loc
[uniform
] == -1) {
1971 assert(param_size
[uniform
]);
1972 for (int j
= 0; j
< param_size
[uniform
]; j
++)
1973 pull_constant_loc
[uniform
+ j
] = num_pull_constants
++;
1976 /* Mark the the one accessed uniform as live */
1977 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1978 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1979 is_live
[constant_nr
] = true;
1984 /* Only allow 16 registers (128 uniform components) as push constants.
1986 * Just demote the end of the list. We could probably do better
1987 * here, demoting things that are rarely used in the program first.
1989 * If changing this value, note the limitation about total_regs in
1992 unsigned int max_push_components
= 16 * 8;
1993 unsigned int num_push_constants
= 0;
1995 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1997 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1998 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1999 /* This UNIFORM register is either dead, or has already been demoted
2000 * to a pull const. Mark it as no longer living in the param[] array.
2002 push_constant_loc
[i
] = -1;
2006 if (num_push_constants
< max_push_components
) {
2007 /* Retain as a push constant. Record the location in the params[]
2010 push_constant_loc
[i
] = num_push_constants
++;
2012 /* Demote to a pull constant. */
2013 push_constant_loc
[i
] = -1;
2014 pull_constant_loc
[i
] = num_pull_constants
++;
2018 stage_prog_data
->nr_params
= num_push_constants
;
2019 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2021 /* Up until now, the param[] array has been indexed by reg + reg_offset
2022 * of UNIFORM registers. Move pull constants into pull_param[] and
2023 * condense param[] to only contain the uniforms we chose to push.
2025 * NOTE: Because we are condensing the params[] array, we know that
2026 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2027 * having to make a copy.
2029 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2030 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
2032 if (pull_constant_loc
[i
] != -1) {
2033 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2034 } else if (push_constant_loc
[i
] != -1) {
2035 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2041 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2042 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2045 fs_visitor::demote_pull_constants()
2047 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2048 for (int i
= 0; i
< inst
->sources
; i
++) {
2049 if (inst
->src
[i
].file
!= UNIFORM
)
2053 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2054 if (location
>= uniforms
) /* Out of bounds access */
2057 pull_index
= pull_constant_loc
[location
];
2059 if (pull_index
== -1)
2062 /* Set up the annotation tracking for new generated instructions. */
2063 const fs_builder
ibld(this, block
, inst
);
2064 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2065 fs_reg dst
= vgrf(glsl_type::float_type
);
2067 assert(inst
->src
[i
].stride
== 0);
2069 /* Generate a pull load into dst. */
2070 if (inst
->src
[i
].reladdr
) {
2071 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
2073 *inst
->src
[i
].reladdr
,
2075 inst
->src
[i
].reladdr
= NULL
;
2076 inst
->src
[i
].stride
= 1;
2078 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2079 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2080 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2081 dst
, brw_imm_ud(index
), offset
);
2082 inst
->src
[i
].set_smear(pull_index
& 3);
2084 brw_mark_surface_used(prog_data
, index
);
2086 /* Rewrite the instruction to use the temporary VGRF. */
2087 inst
->src
[i
].file
= VGRF
;
2088 inst
->src
[i
].nr
= dst
.nr
;
2089 inst
->src
[i
].reg_offset
= 0;
2092 invalidate_live_intervals();
2096 fs_visitor::opt_algebraic()
2098 bool progress
= false;
2100 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2101 switch (inst
->opcode
) {
2102 case BRW_OPCODE_MOV
:
2103 if (inst
->src
[0].file
!= IMM
)
2106 if (inst
->saturate
) {
2107 if (inst
->dst
.type
!= inst
->src
[0].type
)
2108 assert(!"unimplemented: saturate mixed types");
2110 if (brw_saturate_immediate(inst
->dst
.type
,
2111 &inst
->src
[0].as_brw_reg())) {
2112 inst
->saturate
= false;
2118 case BRW_OPCODE_MUL
:
2119 if (inst
->src
[1].file
!= IMM
)
2123 if (inst
->src
[1].is_one()) {
2124 inst
->opcode
= BRW_OPCODE_MOV
;
2125 inst
->src
[1] = reg_undef
;
2131 if (inst
->src
[1].is_negative_one()) {
2132 inst
->opcode
= BRW_OPCODE_MOV
;
2133 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2134 inst
->src
[1] = reg_undef
;
2140 if (inst
->src
[1].is_zero()) {
2141 inst
->opcode
= BRW_OPCODE_MOV
;
2142 inst
->src
[0] = inst
->src
[1];
2143 inst
->src
[1] = reg_undef
;
2148 if (inst
->src
[0].file
== IMM
) {
2149 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2150 inst
->opcode
= BRW_OPCODE_MOV
;
2151 inst
->src
[0].f
*= inst
->src
[1].f
;
2152 inst
->src
[1] = reg_undef
;
2157 case BRW_OPCODE_ADD
:
2158 if (inst
->src
[1].file
!= IMM
)
2162 if (inst
->src
[1].is_zero()) {
2163 inst
->opcode
= BRW_OPCODE_MOV
;
2164 inst
->src
[1] = reg_undef
;
2169 if (inst
->src
[0].file
== IMM
) {
2170 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2171 inst
->opcode
= BRW_OPCODE_MOV
;
2172 inst
->src
[0].f
+= inst
->src
[1].f
;
2173 inst
->src
[1] = reg_undef
;
2179 if (inst
->src
[0].equals(inst
->src
[1])) {
2180 inst
->opcode
= BRW_OPCODE_MOV
;
2181 inst
->src
[1] = reg_undef
;
2186 case BRW_OPCODE_LRP
:
2187 if (inst
->src
[1].equals(inst
->src
[2])) {
2188 inst
->opcode
= BRW_OPCODE_MOV
;
2189 inst
->src
[0] = inst
->src
[1];
2190 inst
->src
[1] = reg_undef
;
2191 inst
->src
[2] = reg_undef
;
2196 case BRW_OPCODE_CMP
:
2197 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2199 inst
->src
[0].negate
&&
2200 inst
->src
[1].is_zero()) {
2201 inst
->src
[0].abs
= false;
2202 inst
->src
[0].negate
= false;
2203 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2208 case BRW_OPCODE_SEL
:
2209 if (inst
->src
[0].equals(inst
->src
[1])) {
2210 inst
->opcode
= BRW_OPCODE_MOV
;
2211 inst
->src
[1] = reg_undef
;
2212 inst
->predicate
= BRW_PREDICATE_NONE
;
2213 inst
->predicate_inverse
= false;
2215 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2216 switch (inst
->conditional_mod
) {
2217 case BRW_CONDITIONAL_LE
:
2218 case BRW_CONDITIONAL_L
:
2219 switch (inst
->src
[1].type
) {
2220 case BRW_REGISTER_TYPE_F
:
2221 if (inst
->src
[1].f
>= 1.0f
) {
2222 inst
->opcode
= BRW_OPCODE_MOV
;
2223 inst
->src
[1] = reg_undef
;
2224 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2232 case BRW_CONDITIONAL_GE
:
2233 case BRW_CONDITIONAL_G
:
2234 switch (inst
->src
[1].type
) {
2235 case BRW_REGISTER_TYPE_F
:
2236 if (inst
->src
[1].f
<= 0.0f
) {
2237 inst
->opcode
= BRW_OPCODE_MOV
;
2238 inst
->src
[1] = reg_undef
;
2239 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2251 case BRW_OPCODE_MAD
:
2252 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2253 inst
->opcode
= BRW_OPCODE_MOV
;
2254 inst
->src
[1] = reg_undef
;
2255 inst
->src
[2] = reg_undef
;
2257 } else if (inst
->src
[0].is_zero()) {
2258 inst
->opcode
= BRW_OPCODE_MUL
;
2259 inst
->src
[0] = inst
->src
[2];
2260 inst
->src
[2] = reg_undef
;
2262 } else if (inst
->src
[1].is_one()) {
2263 inst
->opcode
= BRW_OPCODE_ADD
;
2264 inst
->src
[1] = inst
->src
[2];
2265 inst
->src
[2] = reg_undef
;
2267 } else if (inst
->src
[2].is_one()) {
2268 inst
->opcode
= BRW_OPCODE_ADD
;
2269 inst
->src
[2] = reg_undef
;
2271 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2272 inst
->opcode
= BRW_OPCODE_ADD
;
2273 inst
->src
[1].f
*= inst
->src
[2].f
;
2274 inst
->src
[2] = reg_undef
;
2278 case SHADER_OPCODE_RCP
: {
2279 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2280 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2281 if (inst
->src
[0].equals(prev
->dst
)) {
2282 inst
->opcode
= SHADER_OPCODE_RSQ
;
2283 inst
->src
[0] = prev
->src
[0];
2289 case SHADER_OPCODE_BROADCAST
:
2290 if (is_uniform(inst
->src
[0])) {
2291 inst
->opcode
= BRW_OPCODE_MOV
;
2293 inst
->force_writemask_all
= true;
2295 } else if (inst
->src
[1].file
== IMM
) {
2296 inst
->opcode
= BRW_OPCODE_MOV
;
2297 inst
->src
[0] = component(inst
->src
[0],
2300 inst
->force_writemask_all
= true;
2309 /* Swap if src[0] is immediate. */
2310 if (progress
&& inst
->is_commutative()) {
2311 if (inst
->src
[0].file
== IMM
) {
2312 fs_reg tmp
= inst
->src
[1];
2313 inst
->src
[1] = inst
->src
[0];
2322 * Optimize sample messages that have constant zero values for the trailing
2323 * texture coordinates. We can just reduce the message length for these
2324 * instructions instead of reserving a register for it. Trailing parameters
2325 * that aren't sent default to zero anyway. This will cause the dead code
2326 * eliminator to remove the MOV instruction that would otherwise be emitted to
2327 * set up the zero value.
2330 fs_visitor::opt_zero_samples()
2332 /* Gen4 infers the texturing opcode based on the message length so we can't
2335 if (devinfo
->gen
< 5)
2338 bool progress
= false;
2340 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2341 if (!inst
->is_tex())
2344 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2346 if (load_payload
->is_head_sentinel() ||
2347 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2350 /* We don't want to remove the message header or the first parameter.
2351 * Removing the first parameter is not allowed, see the Haswell PRM
2352 * volume 7, page 149:
2354 * "Parameter 0 is required except for the sampleinfo message, which
2355 * has no parameter 0"
2357 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2358 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2359 (inst
->exec_size
/ 8) +
2360 inst
->header_size
- 1].is_zero()) {
2361 inst
->mlen
-= inst
->exec_size
/ 8;
2367 invalidate_live_intervals();
2373 * Optimize sample messages which are followed by the final RT write.
2375 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2376 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2377 * final texturing results copied to the framebuffer write payload and modify
2378 * them to write to the framebuffer directly.
2381 fs_visitor::opt_sampler_eot()
2383 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2385 if (stage
!= MESA_SHADER_FRAGMENT
)
2388 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2391 /* FINISHME: It should be possible to implement this optimization when there
2392 * are multiple drawbuffers.
2394 if (key
->nr_color_regions
!= 1)
2397 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2398 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2399 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2400 assert(fb_write
->eot
);
2401 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2403 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2405 /* There wasn't one; nothing to do. */
2406 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2409 /* 3D Sampler » Messages » Message Format
2411 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2412 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2414 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2415 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2416 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2417 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2418 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2421 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2422 * It's very likely to be the previous instruction.
2424 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2425 if (load_payload
->is_head_sentinel() ||
2426 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2429 assert(!tex_inst
->eot
); /* We can't get here twice */
2430 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2432 const fs_builder
ibld(this, block
, tex_inst
);
2434 tex_inst
->offset
|= fb_write
->target
<< 24;
2435 tex_inst
->eot
= true;
2436 tex_inst
->dst
= ibld
.null_reg_ud();
2437 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2439 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2440 * to create a new LOAD_PAYLOAD command with the same sources and a space
2441 * saved for the header. Using a new destination register not only makes sure
2442 * we have enough space, but it will make sure the dead code eliminator kills
2443 * the instruction that this will replace.
2445 if (tex_inst
->header_size
!= 0)
2448 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2449 load_payload
->sources
+ 1);
2450 fs_reg
*new_sources
=
2451 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2453 new_sources
[0] = fs_reg();
2454 for (int i
= 0; i
< load_payload
->sources
; i
++)
2455 new_sources
[i
+1] = load_payload
->src
[i
];
2457 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2458 * requires a lot of information about the sources to appropriately figure
2459 * out the number of registers needed to be used. Given this stage in our
2460 * optimization, we may not have the appropriate GRFs required by
2461 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2462 * manually emit the instruction.
2464 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2465 load_payload
->exec_size
,
2468 load_payload
->sources
+ 1);
2470 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2471 new_load_payload
->header_size
= 1;
2473 tex_inst
->header_size
= 1;
2474 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2475 tex_inst
->src
[0] = send_header
;
2481 fs_visitor::opt_register_renaming()
2483 bool progress
= false;
2486 int remap
[alloc
.count
];
2487 memset(remap
, -1, sizeof(int) * alloc
.count
);
2489 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2490 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2492 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2493 inst
->opcode
== BRW_OPCODE_WHILE
) {
2497 /* Rewrite instruction sources. */
2498 for (int i
= 0; i
< inst
->sources
; i
++) {
2499 if (inst
->src
[i
].file
== VGRF
&&
2500 remap
[inst
->src
[i
].nr
] != -1 &&
2501 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2502 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2507 const int dst
= inst
->dst
.nr
;
2510 inst
->dst
.file
== VGRF
&&
2511 alloc
.sizes
[inst
->dst
.nr
] == inst
->exec_size
/ 8 &&
2512 !inst
->is_partial_write()) {
2513 if (remap
[dst
] == -1) {
2516 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2517 inst
->dst
.nr
= remap
[dst
];
2520 } else if (inst
->dst
.file
== VGRF
&&
2522 remap
[dst
] != dst
) {
2523 inst
->dst
.nr
= remap
[dst
];
2529 invalidate_live_intervals();
2531 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2532 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2533 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2542 * Remove redundant or useless discard jumps.
2544 * For example, we can eliminate jumps in the following sequence:
2546 * discard-jump (redundant with the next jump)
2547 * discard-jump (useless; jumps to the next instruction)
2551 fs_visitor::opt_redundant_discard_jumps()
2553 bool progress
= false;
2555 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2557 fs_inst
*placeholder_halt
= NULL
;
2558 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2559 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2560 placeholder_halt
= inst
;
2565 if (!placeholder_halt
)
2568 /* Delete any HALTs immediately before the placeholder halt. */
2569 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2570 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2571 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2572 prev
->remove(last_bblock
);
2577 invalidate_live_intervals();
2583 fs_visitor::compute_to_mrf()
2585 bool progress
= false;
2588 /* No MRFs on Gen >= 7. */
2589 if (devinfo
->gen
>= 7)
2592 calculate_live_intervals();
2594 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2598 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2599 inst
->is_partial_write() ||
2600 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2601 inst
->dst
.type
!= inst
->src
[0].type
||
2602 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2603 !inst
->src
[0].is_contiguous() ||
2604 inst
->src
[0].subreg_offset
)
2607 /* Work out which hardware MRF registers are written by this
2610 int mrf_low
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2612 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2613 mrf_high
= mrf_low
+ 4;
2614 } else if (inst
->exec_size
== 16) {
2615 mrf_high
= mrf_low
+ 1;
2620 /* Can't compute-to-MRF this GRF if someone else was going to
2623 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2626 /* Found a move of a GRF to a MRF. Let's see if we can go
2627 * rewrite the thing that made this GRF to write into the MRF.
2629 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2630 if (scan_inst
->dst
.file
== VGRF
&&
2631 scan_inst
->dst
.nr
== inst
->src
[0].nr
) {
2632 /* Found the last thing to write our reg we want to turn
2633 * into a compute-to-MRF.
2636 /* If this one instruction didn't populate all the
2637 * channels, bail. We might be able to rewrite everything
2638 * that writes that reg, but it would require smarter
2639 * tracking to delay the rewriting until complete success.
2641 if (scan_inst
->is_partial_write())
2644 /* Things returning more than one register would need us to
2645 * understand coalescing out more than one MOV at a time.
2647 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2650 /* SEND instructions can't have MRF as a destination. */
2651 if (scan_inst
->mlen
)
2654 if (devinfo
->gen
== 6) {
2655 /* gen6 math instructions must have the destination be
2656 * GRF, so no compute-to-MRF for them.
2658 if (scan_inst
->is_math()) {
2663 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2664 /* Found the creator of our MRF's source value. */
2665 scan_inst
->dst
.file
= MRF
;
2666 scan_inst
->dst
.nr
= inst
->dst
.nr
;
2667 scan_inst
->saturate
|= inst
->saturate
;
2668 inst
->remove(block
);
2674 /* We don't handle control flow here. Most computation of
2675 * values that end up in MRFs are shortly before the MRF
2678 if (block
->start() == scan_inst
)
2681 /* You can't read from an MRF, so if someone else reads our
2682 * MRF's source GRF that we wanted to rewrite, that stops us.
2684 bool interfered
= false;
2685 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2686 if (scan_inst
->src
[i
].file
== VGRF
&&
2687 scan_inst
->src
[i
].nr
== inst
->src
[0].nr
&&
2688 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2695 if (scan_inst
->dst
.file
== MRF
) {
2696 /* If somebody else writes our MRF here, we can't
2697 * compute-to-MRF before that.
2699 int scan_mrf_low
= scan_inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2702 if (scan_inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2703 scan_mrf_high
= scan_mrf_low
+ 4;
2704 } else if (scan_inst
->exec_size
== 16) {
2705 scan_mrf_high
= scan_mrf_low
+ 1;
2707 scan_mrf_high
= scan_mrf_low
;
2710 if (mrf_low
== scan_mrf_low
||
2711 mrf_low
== scan_mrf_high
||
2712 mrf_high
== scan_mrf_low
||
2713 mrf_high
== scan_mrf_high
) {
2718 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2719 /* Found a SEND instruction, which means that there are
2720 * live values in MRFs from base_mrf to base_mrf +
2721 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2724 if (mrf_low
>= scan_inst
->base_mrf
&&
2725 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2728 if (mrf_high
>= scan_inst
->base_mrf
&&
2729 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2737 invalidate_live_intervals();
2743 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2744 * flow. We could probably do better here with some form of divergence
2748 fs_visitor::eliminate_find_live_channel()
2750 bool progress
= false;
2753 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2754 switch (inst
->opcode
) {
2760 case BRW_OPCODE_ENDIF
:
2761 case BRW_OPCODE_WHILE
:
2765 case FS_OPCODE_DISCARD_JUMP
:
2766 /* This can potentially make control flow non-uniform until the end
2771 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2773 inst
->opcode
= BRW_OPCODE_MOV
;
2774 inst
->src
[0] = brw_imm_ud(0u);
2776 inst
->force_writemask_all
= true;
2790 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2791 * instructions to FS_OPCODE_REP_FB_WRITE.
2794 fs_visitor::emit_repclear_shader()
2796 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2798 int color_mrf
= base_mrf
+ 2;
2800 fs_inst
*mov
= bld
.exec_all().group(4, 0)
2801 .MOV(brw_message_reg(color_mrf
),
2802 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2805 if (key
->nr_color_regions
== 1) {
2806 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2807 write
->saturate
= key
->clamp_fragment_color
;
2808 write
->base_mrf
= color_mrf
;
2810 write
->header_size
= 0;
2813 assume(key
->nr_color_regions
> 0);
2814 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2815 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2816 write
->saturate
= key
->clamp_fragment_color
;
2817 write
->base_mrf
= base_mrf
;
2819 write
->header_size
= 2;
2827 assign_constant_locations();
2828 assign_curb_setup();
2830 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2831 assert(mov
->src
[0].file
== FIXED_GRF
);
2832 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2836 * Walks through basic blocks, looking for repeated MRF writes and
2837 * removing the later ones.
2840 fs_visitor::remove_duplicate_mrf_writes()
2842 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2843 bool progress
= false;
2845 /* Need to update the MRF tracking for compressed instructions. */
2846 if (dispatch_width
== 16)
2849 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2851 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2852 if (inst
->is_control_flow()) {
2853 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2856 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2857 inst
->dst
.file
== MRF
) {
2858 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2859 if (prev_inst
&& inst
->equals(prev_inst
)) {
2860 inst
->remove(block
);
2866 /* Clear out the last-write records for MRFs that were overwritten. */
2867 if (inst
->dst
.file
== MRF
) {
2868 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2871 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2872 /* Found a SEND instruction, which will include two or fewer
2873 * implied MRF writes. We could do better here.
2875 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2876 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2880 /* Clear out any MRF move records whose sources got overwritten. */
2881 if (inst
->dst
.file
== VGRF
) {
2882 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2883 if (last_mrf_move
[i
] &&
2884 last_mrf_move
[i
]->src
[0].nr
== inst
->dst
.nr
) {
2885 last_mrf_move
[i
] = NULL
;
2890 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2891 inst
->dst
.file
== MRF
&&
2892 inst
->src
[0].file
== VGRF
&&
2893 !inst
->is_partial_write()) {
2894 last_mrf_move
[inst
->dst
.nr
] = inst
;
2899 invalidate_live_intervals();
2905 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2907 /* Clear the flag for registers that actually got read (as expected). */
2908 for (int i
= 0; i
< inst
->sources
; i
++) {
2910 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
2911 grf
= inst
->src
[i
].nr
;
2916 if (grf
>= first_grf
&&
2917 grf
< first_grf
+ grf_len
) {
2918 deps
[grf
- first_grf
] = false;
2919 if (inst
->exec_size
== 16)
2920 deps
[grf
- first_grf
+ 1] = false;
2926 * Implements this workaround for the original 965:
2928 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2929 * check for post destination dependencies on this instruction, software
2930 * must ensure that there is no destination hazard for the case of ‘write
2931 * followed by a posted write’ shown in the following example.
2934 * 2. send r3.xy <rest of send instruction>
2937 * Due to no post-destination dependency check on the ‘send’, the above
2938 * code sequence could have two instructions (1 and 2) in flight at the
2939 * same time that both consider ‘r3’ as the target of their final writes.
2942 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2945 int write_len
= inst
->regs_written
;
2946 int first_write_grf
= inst
->dst
.nr
;
2947 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2948 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2950 memset(needs_dep
, false, sizeof(needs_dep
));
2951 memset(needs_dep
, true, write_len
);
2953 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2955 /* Walk backwards looking for writes to registers we're writing which
2956 * aren't read since being written. If we hit the start of the program,
2957 * we assume that there are no outstanding dependencies on entry to the
2960 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2961 /* If we hit control flow, assume that there *are* outstanding
2962 * dependencies, and force their cleanup before our instruction.
2964 if (block
->start() == scan_inst
) {
2965 for (int i
= 0; i
< write_len
; i
++) {
2967 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
2968 first_write_grf
+ i
);
2973 /* We insert our reads as late as possible on the assumption that any
2974 * instruction but a MOV that might have left us an outstanding
2975 * dependency has more latency than a MOV.
2977 if (scan_inst
->dst
.file
== VGRF
) {
2978 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2979 int reg
= scan_inst
->dst
.nr
+ i
;
2981 if (reg
>= first_write_grf
&&
2982 reg
< first_write_grf
+ write_len
&&
2983 needs_dep
[reg
- first_write_grf
]) {
2984 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
2985 needs_dep
[reg
- first_write_grf
] = false;
2986 if (scan_inst
->exec_size
== 16)
2987 needs_dep
[reg
- first_write_grf
+ 1] = false;
2992 /* Clear the flag for registers that actually got read (as expected). */
2993 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2995 /* Continue the loop only if we haven't resolved all the dependencies */
2997 for (i
= 0; i
< write_len
; i
++) {
3007 * Implements this workaround for the original 965:
3009 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3010 * used as a destination register until after it has been sourced by an
3011 * instruction with a different destination register.
3014 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3016 int write_len
= inst
->regs_written
;
3017 int first_write_grf
= inst
->dst
.nr
;
3018 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3019 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3021 memset(needs_dep
, false, sizeof(needs_dep
));
3022 memset(needs_dep
, true, write_len
);
3023 /* Walk forwards looking for writes to registers we're writing which aren't
3024 * read before being written.
3026 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3027 /* If we hit control flow, force resolve all remaining dependencies. */
3028 if (block
->end() == scan_inst
) {
3029 for (int i
= 0; i
< write_len
; i
++) {
3031 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3032 first_write_grf
+ i
);
3037 /* Clear the flag for registers that actually got read (as expected). */
3038 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3040 /* We insert our reads as late as possible since they're reading the
3041 * result of a SEND, which has massive latency.
3043 if (scan_inst
->dst
.file
== VGRF
&&
3044 scan_inst
->dst
.nr
>= first_write_grf
&&
3045 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3046 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3047 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3049 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3052 /* Continue the loop only if we haven't resolved all the dependencies */
3054 for (i
= 0; i
< write_len
; i
++) {
3064 fs_visitor::insert_gen4_send_dependency_workarounds()
3066 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3069 bool progress
= false;
3071 /* Note that we're done with register allocation, so GRF fs_regs always
3072 * have a .reg_offset of 0.
3075 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3076 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3077 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3078 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3084 invalidate_live_intervals();
3088 * Turns the generic expression-style uniform pull constant load instruction
3089 * into a hardware-specific series of instructions for loading a pull
3092 * The expression style allows the CSE pass before this to optimize out
3093 * repeated loads from the same offset, and gives the pre-register-allocation
3094 * scheduling full flexibility, while the conversion to native instructions
3095 * allows the post-register-allocation scheduler the best information
3098 * Note that execution masking for setting up pull constant loads is special:
3099 * the channels that need to be written are unrelated to the current execution
3100 * mask, since a later instruction will use one of the result channels as a
3101 * source operand for all 8 or 16 of its channels.
3104 fs_visitor::lower_uniform_pull_constant_loads()
3106 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3107 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3110 if (devinfo
->gen
>= 7) {
3111 /* The offset arg is a vec4-aligned immediate byte offset. */
3112 fs_reg const_offset_reg
= inst
->src
[1];
3113 assert(const_offset_reg
.file
== IMM
&&
3114 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3115 assert(const_offset_reg
.ud
% 16 == 0);
3117 fs_reg payload
, offset
;
3118 if (devinfo
->gen
>= 9) {
3119 /* We have to use a message header on Skylake to get SIMD4x2
3120 * mode. Reserve space for the register.
3122 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3123 offset
.reg_offset
++;
3126 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3130 /* This is actually going to be a MOV, but since only the first dword
3131 * is accessed, we have a special opcode to do just that one. Note
3132 * that this needs to be an operation that will be considered a def
3133 * by live variable analysis, or register allocation will explode.
3135 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3136 8, offset
, const_offset_reg
);
3137 setup
->force_writemask_all
= true;
3139 setup
->ir
= inst
->ir
;
3140 setup
->annotation
= inst
->annotation
;
3141 inst
->insert_before(block
, setup
);
3143 /* Similarly, this will only populate the first 4 channels of the
3144 * result register (since we only use smear values from 0-3), but we
3145 * don't tell the optimizer.
3147 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3148 inst
->src
[1] = payload
;
3149 inst
->base_mrf
= -1;
3151 invalidate_live_intervals();
3153 /* Before register allocation, we didn't tell the scheduler about the
3154 * MRF we use. We know it's safe to use this MRF because nothing
3155 * else does except for register spill/unspill, which generates and
3156 * uses its MRF within a single IR instruction.
3158 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3165 fs_visitor::lower_load_payload()
3167 bool progress
= false;
3169 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3170 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3173 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3174 assert(inst
->saturate
== false);
3175 fs_reg dst
= inst
->dst
;
3177 /* Get rid of COMPR4. We'll add it back in if we need it */
3178 if (dst
.file
== MRF
)
3179 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3181 const fs_builder
ibld(this, block
, inst
);
3182 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3184 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3185 if (inst
->src
[i
].file
!= BAD_FILE
) {
3186 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3187 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3188 hbld
.MOV(mov_dst
, mov_src
);
3190 dst
= offset(dst
, hbld
, 1);
3193 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3194 inst
->exec_size
> 8) {
3195 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3196 * a straightforward copy. Instead, the result of the
3197 * LOAD_PAYLOAD is treated as interleaved and the first four
3198 * non-header sources are unpacked as:
3209 * This is used for gen <= 5 fb writes.
3211 assert(inst
->exec_size
== 16);
3212 assert(inst
->header_size
+ 4 <= inst
->sources
);
3213 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3214 if (inst
->src
[i
].file
!= BAD_FILE
) {
3215 if (devinfo
->has_compr4
) {
3216 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3217 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3218 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3220 /* Platform doesn't have COMPR4. We have to fake it */
3221 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3222 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3224 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3231 /* The loop above only ever incremented us through the first set
3232 * of 4 registers. However, thanks to the magic of COMPR4, we
3233 * actually wrote to the first 8 registers, so we need to take
3234 * that into account now.
3238 /* The COMPR4 code took care of the first 4 sources. We'll let
3239 * the regular path handle any remaining sources. Yes, we are
3240 * modifying the instruction but we're about to delete it so
3241 * this really doesn't hurt anything.
3243 inst
->header_size
+= 4;
3246 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3247 if (inst
->src
[i
].file
!= BAD_FILE
)
3248 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3249 dst
= offset(dst
, ibld
, 1);
3252 inst
->remove(block
);
3257 invalidate_live_intervals();
3263 fs_visitor::lower_integer_multiplication()
3265 bool progress
= false;
3267 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3268 const fs_builder
ibld(this, block
, inst
);
3270 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3271 if (inst
->dst
.is_accumulator() ||
3272 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3273 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3276 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3277 * operation directly, but CHV/BXT cannot.
3279 if (devinfo
->gen
>= 8 &&
3280 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3283 if (inst
->src
[1].file
== IMM
&&
3284 inst
->src
[1].ud
< (1 << 16)) {
3285 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3286 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3289 * If multiplying by an immediate value that fits in 16-bits, do a
3290 * single MUL instruction with that value in the proper location.
3292 if (devinfo
->gen
< 7) {
3293 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3295 ibld
.MOV(imm
, inst
->src
[1]);
3296 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3298 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3301 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3302 * do 32-bit integer multiplication in one instruction, but instead
3303 * must do a sequence (which actually calculates a 64-bit result):
3305 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3306 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3307 * mov(8) g2<1>D acc0<8,8,1>D
3309 * But on Gen > 6, the ability to use second accumulator register
3310 * (acc1) for non-float data types was removed, preventing a simple
3311 * implementation in SIMD16. A 16-channel result can be calculated by
3312 * executing the three instructions twice in SIMD8, once with quarter
3313 * control of 1Q for the first eight channels and again with 2Q for
3314 * the second eight channels.
3316 * Which accumulator register is implicitly accessed (by AccWrEnable
3317 * for instance) is determined by the quarter control. Unfortunately
3318 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3319 * implicit accumulator access by an instruction with 2Q will access
3320 * acc1 regardless of whether the data type is usable in acc1.
3322 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3323 * integer data types.
3325 * Since we only want the low 32-bits of the result, we can do two
3326 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3327 * adjust the high result and add them (like the mach is doing):
3329 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3330 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3331 * shl(8) g9<1>D g8<8,8,1>D 16D
3332 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3334 * We avoid the shl instruction by realizing that we only want to add
3335 * the low 16-bits of the "high" result to the high 16-bits of the
3336 * "low" result and using proper regioning on the add:
3338 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3339 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3340 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3342 * Since it does not use the (single) accumulator register, we can
3343 * schedule multi-component multiplications much better.
3346 fs_reg orig_dst
= inst
->dst
;
3347 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3348 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3351 fs_reg low
= inst
->dst
;
3352 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3355 if (devinfo
->gen
>= 7) {
3356 fs_reg src1_0_w
= inst
->src
[1];
3357 fs_reg src1_1_w
= inst
->src
[1];
3359 if (inst
->src
[1].file
== IMM
) {
3360 src1_0_w
.ud
&= 0xffff;
3363 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3364 if (src1_0_w
.stride
!= 0) {
3365 assert(src1_0_w
.stride
== 1);
3366 src1_0_w
.stride
= 2;
3369 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3370 if (src1_1_w
.stride
!= 0) {
3371 assert(src1_1_w
.stride
== 1);
3372 src1_1_w
.stride
= 2;
3374 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3376 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3377 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3379 fs_reg src0_0_w
= inst
->src
[0];
3380 fs_reg src0_1_w
= inst
->src
[0];
3382 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3383 if (src0_0_w
.stride
!= 0) {
3384 assert(src0_0_w
.stride
== 1);
3385 src0_0_w
.stride
= 2;
3388 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3389 if (src0_1_w
.stride
!= 0) {
3390 assert(src0_1_w
.stride
== 1);
3391 src0_1_w
.stride
= 2;
3393 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3395 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3396 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3399 fs_reg dst
= inst
->dst
;
3400 dst
.type
= BRW_REGISTER_TYPE_UW
;
3401 dst
.subreg_offset
= 2;
3404 high
.type
= BRW_REGISTER_TYPE_UW
;
3407 low
.type
= BRW_REGISTER_TYPE_UW
;
3408 low
.subreg_offset
= 2;
3411 ibld
.ADD(dst
, low
, high
);
3413 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3414 set_condmod(inst
->conditional_mod
,
3415 ibld
.MOV(orig_dst
, inst
->dst
));
3419 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3420 /* Should have been lowered to 8-wide. */
3421 assert(inst
->exec_size
<= 8);
3422 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3424 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3425 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3427 if (devinfo
->gen
>= 8) {
3428 /* Until Gen8, integer multiplies read 32-bits from one source,
3429 * and 16-bits from the other, and relying on the MACH instruction
3430 * to generate the high bits of the result.
3432 * On Gen8, the multiply instruction does a full 32x32-bit
3433 * multiply, but in order to do a 64-bit multiply we can simulate
3434 * the previous behavior and then use a MACH instruction.
3436 * FINISHME: Don't use source modifiers on src1.
3438 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3439 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3440 mul
->src
[1].type
= (type_is_signed(mul
->src
[1].type
) ?
3441 BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
3442 mul
->src
[1].stride
*= 2;
3444 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3445 inst
->force_sechalf
) {
3446 /* Among other things the quarter control bits influence which
3447 * accumulator register is used by the hardware for instructions
3448 * that access the accumulator implicitly (e.g. MACH). A
3449 * second-half instruction would normally map to acc1, which
3450 * doesn't exist on Gen7 and up (the hardware does emulate it for
3451 * floating-point instructions *only* by taking advantage of the
3452 * extra precision of acc0 not normally used for floating point
3455 * HSW and up are careful enough not to try to access an
3456 * accumulator register that doesn't exist, but on earlier Gen7
3457 * hardware we need to make sure that the quarter control bits are
3458 * zero to avoid non-deterministic behaviour and emit an extra MOV
3459 * to get the result masked correctly according to the current
3462 mach
->force_sechalf
= false;
3463 mach
->force_writemask_all
= true;
3464 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3465 ibld
.MOV(inst
->dst
, mach
->dst
);
3471 inst
->remove(block
);
3476 invalidate_live_intervals();
3482 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3483 fs_reg
*dst
, fs_reg color
, unsigned components
)
3485 if (key
->clamp_fragment_color
) {
3486 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3487 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3489 for (unsigned i
= 0; i
< components
; i
++)
3491 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3496 for (unsigned i
= 0; i
< components
; i
++)
3497 dst
[i
] = offset(color
, bld
, i
);
3501 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3502 const brw_wm_prog_data
*prog_data
,
3503 const brw_wm_prog_key
*key
,
3504 const fs_visitor::thread_payload
&payload
)
3506 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3507 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3508 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3509 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3510 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3511 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3512 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3513 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3514 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3515 const unsigned components
=
3516 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3518 /* We can potentially have a message length of up to 15, so we have to set
3519 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3522 int header_size
= 2, payload_header_size
;
3523 unsigned length
= 0;
3525 /* From the Sandy Bridge PRM, volume 4, page 198:
3527 * "Dispatched Pixel Enables. One bit per pixel indicating
3528 * which pixels were originally enabled when the thread was
3529 * dispatched. This field is only required for the end-of-
3530 * thread message and on all dual-source messages."
3532 if (devinfo
->gen
>= 6 &&
3533 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3534 color1
.file
== BAD_FILE
&&
3535 key
->nr_color_regions
== 1) {
3539 if (header_size
!= 0) {
3540 assert(header_size
== 2);
3541 /* Allocate 2 registers for a header */
3545 if (payload
.aa_dest_stencil_reg
) {
3546 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3547 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3548 .MOV(sources
[length
],
3549 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3553 if (prog_data
->uses_omask
) {
3554 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3555 BRW_REGISTER_TYPE_UD
);
3557 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3558 * relevant. Since it's unsigned single words one vgrf is always
3559 * 16-wide, but only the lower or higher 8 channels will be used by the
3560 * hardware when doing a SIMD8 write depending on whether we have
3561 * selected the subspans for the first or second half respectively.
3563 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3564 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3565 sample_mask
.stride
*= 2;
3567 bld
.exec_all().annotate("FB write oMask")
3568 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3569 inst
->force_sechalf
),
3574 payload_header_size
= length
;
3576 if (src0_alpha
.file
!= BAD_FILE
) {
3577 /* FIXME: This is being passed at the wrong location in the payload and
3578 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3579 * It's supposed to be immediately before oMask but there seems to be no
3580 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3581 * requires header sources to form a contiguous segment at the beginning
3582 * of the message and src0_alpha has per-channel semantics.
3584 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3588 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3591 if (color1
.file
!= BAD_FILE
) {
3592 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3596 if (src_depth
.file
!= BAD_FILE
) {
3597 sources
[length
] = src_depth
;
3601 if (dst_depth
.file
!= BAD_FILE
) {
3602 sources
[length
] = dst_depth
;
3606 if (src_stencil
.file
!= BAD_FILE
) {
3607 assert(devinfo
->gen
>= 9);
3608 assert(bld
.dispatch_width() != 16);
3610 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3611 * available on gen9+. As such it's impossible to have both enabled at the
3612 * same time and therefore length cannot overrun the array.
3614 assert(length
< 15);
3616 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3617 bld
.exec_all().annotate("FB write OS")
3618 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3619 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3624 if (devinfo
->gen
>= 7) {
3625 /* Send from the GRF */
3626 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3627 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3628 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3629 load
->dst
= payload
;
3631 inst
->src
[0] = payload
;
3632 inst
->resize_sources(1);
3633 inst
->base_mrf
= -1;
3635 /* Send from the MRF */
3636 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3637 sources
, length
, payload_header_size
);
3639 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3640 * will do this for us if we just give it a COMPR4 destination.
3642 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3643 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3645 inst
->resize_sources(0);
3649 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3650 inst
->mlen
= load
->regs_written
;
3651 inst
->header_size
= header_size
;
3655 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3656 const fs_reg
&coordinate
,
3657 const fs_reg
&shadow_c
,
3658 const fs_reg
&lod
, const fs_reg
&lod2
,
3659 const fs_reg
&sampler
,
3660 unsigned coord_components
,
3661 unsigned grad_components
)
3663 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3664 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3665 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3666 fs_reg msg_end
= msg_begin
;
3669 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3671 for (unsigned i
= 0; i
< coord_components
; i
++)
3672 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3673 offset(coordinate
, bld
, i
));
3675 msg_end
= offset(msg_end
, bld
, coord_components
);
3677 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3678 * require all three components to be present and zero if they are unused.
3680 if (coord_components
> 0 &&
3681 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3682 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3683 for (unsigned i
= coord_components
; i
< 3; i
++)
3684 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3686 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3689 if (op
== SHADER_OPCODE_TXD
) {
3690 /* TXD unsupported in SIMD16 mode. */
3691 assert(bld
.dispatch_width() == 8);
3693 /* the slots for u and v are always present, but r is optional */
3694 if (coord_components
< 2)
3695 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3698 * dPdx = dudx, dvdx, drdx
3699 * dPdy = dudy, dvdy, drdy
3701 * 1-arg: Does not exist.
3703 * 2-arg: dudx dvdx dudy dvdy
3704 * dPdx.x dPdx.y dPdy.x dPdy.y
3707 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3708 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3709 * m5 m6 m7 m8 m9 m10
3711 for (unsigned i
= 0; i
< grad_components
; i
++)
3712 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3714 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3716 for (unsigned i
= 0; i
< grad_components
; i
++)
3717 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3719 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3723 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3724 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3726 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3727 bld
.dispatch_width() == 16);
3729 const brw_reg_type type
=
3730 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3731 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3732 bld
.MOV(retype(msg_end
, type
), lod
);
3733 msg_end
= offset(msg_end
, bld
, 1);
3736 if (shadow_c
.file
!= BAD_FILE
) {
3737 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3738 /* There's no plain shadow compare message, so we use shadow
3739 * compare with a bias of 0.0.
3741 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3742 msg_end
= offset(msg_end
, bld
, 1);
3745 bld
.MOV(msg_end
, shadow_c
);
3746 msg_end
= offset(msg_end
, bld
, 1);
3750 inst
->src
[0] = reg_undef
;
3751 inst
->src
[1] = sampler
;
3752 inst
->resize_sources(2);
3753 inst
->base_mrf
= msg_begin
.nr
;
3754 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3755 inst
->header_size
= 1;
3759 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3761 const fs_reg
&shadow_c
,
3762 fs_reg lod
, fs_reg lod2
,
3763 const fs_reg
&sample_index
,
3764 const fs_reg
&sampler
,
3765 const fs_reg
&offset_value
,
3766 unsigned coord_components
,
3767 unsigned grad_components
)
3769 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3770 fs_reg msg_coords
= message
;
3771 unsigned header_size
= 0;
3773 if (offset_value
.file
!= BAD_FILE
) {
3774 /* The offsets set up by the visitor are in the m1 header, so we can't
3781 for (unsigned i
= 0; i
< coord_components
; i
++) {
3782 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3783 coordinate
= offset(coordinate
, bld
, 1);
3785 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3786 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3788 if (shadow_c
.file
!= BAD_FILE
) {
3789 fs_reg msg_shadow
= msg_lod
;
3790 bld
.MOV(msg_shadow
, shadow_c
);
3791 msg_lod
= offset(msg_shadow
, bld
, 1);
3796 case SHADER_OPCODE_TXL
:
3798 bld
.MOV(msg_lod
, lod
);
3799 msg_end
= offset(msg_lod
, bld
, 1);
3801 case SHADER_OPCODE_TXD
:
3804 * dPdx = dudx, dvdx, drdx
3805 * dPdy = dudy, dvdy, drdy
3807 * Load up these values:
3808 * - dudx dudy dvdx dvdy drdx drdy
3809 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3812 for (unsigned i
= 0; i
< grad_components
; i
++) {
3813 bld
.MOV(msg_end
, lod
);
3814 lod
= offset(lod
, bld
, 1);
3815 msg_end
= offset(msg_end
, bld
, 1);
3817 bld
.MOV(msg_end
, lod2
);
3818 lod2
= offset(lod2
, bld
, 1);
3819 msg_end
= offset(msg_end
, bld
, 1);
3822 case SHADER_OPCODE_TXS
:
3823 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3824 bld
.MOV(msg_lod
, lod
);
3825 msg_end
= offset(msg_lod
, bld
, 1);
3827 case SHADER_OPCODE_TXF
:
3828 msg_lod
= offset(msg_coords
, bld
, 3);
3829 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3830 msg_end
= offset(msg_lod
, bld
, 1);
3832 case SHADER_OPCODE_TXF_CMS
:
3833 msg_lod
= offset(msg_coords
, bld
, 3);
3835 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3837 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3838 msg_end
= offset(msg_lod
, bld
, 2);
3845 inst
->src
[0] = reg_undef
;
3846 inst
->src
[1] = sampler
;
3847 inst
->resize_sources(2);
3848 inst
->base_mrf
= message
.nr
;
3849 inst
->mlen
= msg_end
.nr
- message
.nr
;
3850 inst
->header_size
= header_size
;
3852 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3853 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3857 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3859 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3862 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
3866 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3868 const fs_reg
&shadow_c
,
3869 fs_reg lod
, fs_reg lod2
,
3870 const fs_reg
&sample_index
,
3871 const fs_reg
&mcs
, const fs_reg
&sampler
,
3872 fs_reg offset_value
,
3873 unsigned coord_components
,
3874 unsigned grad_components
)
3876 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3877 int reg_width
= bld
.dispatch_width() / 8;
3878 unsigned header_size
= 0, length
= 0;
3879 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3880 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3881 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3883 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3884 offset_value
.file
!= BAD_FILE
||
3885 is_high_sampler(devinfo
, sampler
)) {
3886 /* For general texture offsets (no txf workaround), we need a header to
3887 * put them in. Note that we're only reserving space for it in the
3888 * message payload as it will be initialized implicitly by the
3891 * TG4 needs to place its channel select in the header, for interaction
3892 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3893 * larger sampler numbers we need to offset the Sampler State Pointer in
3897 sources
[0] = fs_reg();
3901 if (shadow_c
.file
!= BAD_FILE
) {
3902 bld
.MOV(sources
[length
], shadow_c
);
3906 bool coordinate_done
= false;
3908 /* The sampler can only meaningfully compute LOD for fragment shader
3909 * messages. For all other stages, we change the opcode to TXL and
3910 * hardcode the LOD to 0.
3912 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3913 op
== SHADER_OPCODE_TEX
) {
3914 op
= SHADER_OPCODE_TXL
;
3915 lod
= brw_imm_f(0.0f
);
3918 /* Set up the LOD info */
3921 case SHADER_OPCODE_TXL
:
3922 bld
.MOV(sources
[length
], lod
);
3925 case SHADER_OPCODE_TXD
:
3926 /* TXD should have been lowered in SIMD16 mode. */
3927 assert(bld
.dispatch_width() == 8);
3929 /* Load dPdx and the coordinate together:
3930 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3932 for (unsigned i
= 0; i
< coord_components
; i
++) {
3933 bld
.MOV(sources
[length
], coordinate
);
3934 coordinate
= offset(coordinate
, bld
, 1);
3937 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3938 * only derivatives for (u, v, r).
3940 if (i
< grad_components
) {
3941 bld
.MOV(sources
[length
], lod
);
3942 lod
= offset(lod
, bld
, 1);
3945 bld
.MOV(sources
[length
], lod2
);
3946 lod2
= offset(lod2
, bld
, 1);
3951 coordinate_done
= true;
3953 case SHADER_OPCODE_TXS
:
3954 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3957 case SHADER_OPCODE_TXF
:
3958 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3959 * On Gen9 they are u, v, lod, r
3961 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3962 coordinate
= offset(coordinate
, bld
, 1);
3965 if (devinfo
->gen
>= 9) {
3966 if (coord_components
>= 2) {
3967 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3968 coordinate
= offset(coordinate
, bld
, 1);
3973 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
3976 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
3977 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3978 coordinate
= offset(coordinate
, bld
, 1);
3982 coordinate_done
= true;
3984 case SHADER_OPCODE_TXF_CMS
:
3985 case SHADER_OPCODE_TXF_CMS_W
:
3986 case SHADER_OPCODE_TXF_UMS
:
3987 case SHADER_OPCODE_TXF_MCS
:
3988 if (op
== SHADER_OPCODE_TXF_UMS
||
3989 op
== SHADER_OPCODE_TXF_CMS
||
3990 op
== SHADER_OPCODE_TXF_CMS_W
) {
3991 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
3995 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
3996 /* Data from the multisample control surface. */
3997 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4000 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4003 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4004 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4007 offset(mcs
, bld
, 1));
4012 /* There is no offsetting for this message; just copy in the integer
4013 * texture coordinates.
4015 for (unsigned i
= 0; i
< coord_components
; i
++) {
4016 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4017 coordinate
= offset(coordinate
, bld
, 1);
4021 coordinate_done
= true;
4023 case SHADER_OPCODE_TG4_OFFSET
:
4024 /* gather4_po_c should have been lowered in SIMD16 mode. */
4025 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
4027 /* More crazy intermixing */
4028 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
4029 bld
.MOV(sources
[length
], coordinate
);
4030 coordinate
= offset(coordinate
, bld
, 1);
4034 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
4035 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
4036 offset_value
= offset(offset_value
, bld
, 1);
4040 if (coord_components
== 3) { /* r if present */
4041 bld
.MOV(sources
[length
], coordinate
);
4042 coordinate
= offset(coordinate
, bld
, 1);
4046 coordinate_done
= true;
4052 /* Set up the coordinate (except for cases where it was done above) */
4053 if (!coordinate_done
) {
4054 for (unsigned i
= 0; i
< coord_components
; i
++) {
4055 bld
.MOV(sources
[length
], coordinate
);
4056 coordinate
= offset(coordinate
, bld
, 1);
4063 mlen
= length
* reg_width
- header_size
;
4065 mlen
= length
* reg_width
;
4067 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4068 BRW_REGISTER_TYPE_F
);
4069 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4071 /* Generate the SEND. */
4073 inst
->src
[0] = src_payload
;
4074 inst
->src
[1] = sampler
;
4075 inst
->resize_sources(2);
4076 inst
->base_mrf
= -1;
4078 inst
->header_size
= header_size
;
4080 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4081 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4085 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4087 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4088 const fs_reg
&coordinate
= inst
->src
[0];
4089 const fs_reg
&shadow_c
= inst
->src
[1];
4090 const fs_reg
&lod
= inst
->src
[2];
4091 const fs_reg
&lod2
= inst
->src
[3];
4092 const fs_reg
&sample_index
= inst
->src
[4];
4093 const fs_reg
&mcs
= inst
->src
[5];
4094 const fs_reg
&sampler
= inst
->src
[6];
4095 const fs_reg
&offset_value
= inst
->src
[7];
4096 assert(inst
->src
[8].file
== IMM
&& inst
->src
[9].file
== IMM
);
4097 const unsigned coord_components
= inst
->src
[8].ud
;
4098 const unsigned grad_components
= inst
->src
[9].ud
;
4100 if (devinfo
->gen
>= 7) {
4101 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4102 shadow_c
, lod
, lod2
, sample_index
,
4103 mcs
, sampler
, offset_value
,
4104 coord_components
, grad_components
);
4105 } else if (devinfo
->gen
>= 5) {
4106 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4107 shadow_c
, lod
, lod2
, sample_index
,
4108 sampler
, offset_value
,
4109 coord_components
, grad_components
);
4111 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4112 shadow_c
, lod
, lod2
, sampler
,
4113 coord_components
, grad_components
);
4118 * Initialize the header present in some typed and untyped surface
4122 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4124 fs_builder ubld
= bld
.exec_all().group(8, 0);
4125 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4126 ubld
.MOV(dst
, brw_imm_d(0));
4127 ubld
.MOV(component(dst
, 7), sample_mask
);
4132 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4133 const fs_reg
&sample_mask
)
4135 /* Get the logical send arguments. */
4136 const fs_reg
&addr
= inst
->src
[0];
4137 const fs_reg
&src
= inst
->src
[1];
4138 const fs_reg
&surface
= inst
->src
[2];
4139 const UNUSED fs_reg
&dims
= inst
->src
[3];
4140 const fs_reg
&arg
= inst
->src
[4];
4142 /* Calculate the total number of components of the payload. */
4143 const unsigned addr_sz
= inst
->components_read(0);
4144 const unsigned src_sz
= inst
->components_read(1);
4145 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4146 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4148 /* Allocate space for the payload. */
4149 fs_reg
*const components
= new fs_reg
[sz
];
4150 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4153 /* Construct the payload. */
4155 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4157 for (unsigned i
= 0; i
< addr_sz
; i
++)
4158 components
[n
++] = offset(addr
, bld
, i
);
4160 for (unsigned i
= 0; i
< src_sz
; i
++)
4161 components
[n
++] = offset(src
, bld
, i
);
4163 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4165 /* Update the original instruction. */
4167 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4168 inst
->header_size
= header_sz
;
4170 inst
->src
[0] = payload
;
4171 inst
->src
[1] = surface
;
4173 inst
->resize_sources(3);
4175 delete[] components
;
4179 fs_visitor::lower_logical_sends()
4181 bool progress
= false;
4183 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4184 const fs_builder
ibld(this, block
, inst
);
4186 switch (inst
->opcode
) {
4187 case FS_OPCODE_FB_WRITE_LOGICAL
:
4188 assert(stage
== MESA_SHADER_FRAGMENT
);
4189 lower_fb_write_logical_send(ibld
, inst
,
4190 (const brw_wm_prog_data
*)prog_data
,
4191 (const brw_wm_prog_key
*)key
,
4195 case SHADER_OPCODE_TEX_LOGICAL
:
4196 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4199 case SHADER_OPCODE_TXD_LOGICAL
:
4200 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4203 case SHADER_OPCODE_TXF_LOGICAL
:
4204 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4207 case SHADER_OPCODE_TXL_LOGICAL
:
4208 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4211 case SHADER_OPCODE_TXS_LOGICAL
:
4212 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4215 case FS_OPCODE_TXB_LOGICAL
:
4216 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4219 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4220 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4223 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4224 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4227 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4228 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4231 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4232 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4235 case SHADER_OPCODE_LOD_LOGICAL
:
4236 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4239 case SHADER_OPCODE_TG4_LOGICAL
:
4240 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4243 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4244 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4247 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4248 lower_surface_logical_send(ibld
, inst
,
4249 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4253 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4254 lower_surface_logical_send(ibld
, inst
,
4255 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4256 ibld
.sample_mask_reg());
4259 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4260 lower_surface_logical_send(ibld
, inst
,
4261 SHADER_OPCODE_UNTYPED_ATOMIC
,
4262 ibld
.sample_mask_reg());
4265 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4266 lower_surface_logical_send(ibld
, inst
,
4267 SHADER_OPCODE_TYPED_SURFACE_READ
,
4271 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4272 lower_surface_logical_send(ibld
, inst
,
4273 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4274 ibld
.sample_mask_reg());
4277 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4278 lower_surface_logical_send(ibld
, inst
,
4279 SHADER_OPCODE_TYPED_ATOMIC
,
4280 ibld
.sample_mask_reg());
4291 invalidate_live_intervals();
4297 * Get the closest native SIMD width supported by the hardware for instruction
4298 * \p inst. The instruction will be left untouched by
4299 * fs_visitor::lower_simd_width() if the returned value is equal to the
4300 * original execution size.
4303 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4304 const fs_inst
*inst
)
4306 switch (inst
->opcode
) {
4307 case BRW_OPCODE_MOV
:
4308 case BRW_OPCODE_SEL
:
4309 case BRW_OPCODE_NOT
:
4310 case BRW_OPCODE_AND
:
4312 case BRW_OPCODE_XOR
:
4313 case BRW_OPCODE_SHR
:
4314 case BRW_OPCODE_SHL
:
4315 case BRW_OPCODE_ASR
:
4316 case BRW_OPCODE_CMP
:
4317 case BRW_OPCODE_CMPN
:
4318 case BRW_OPCODE_CSEL
:
4319 case BRW_OPCODE_F32TO16
:
4320 case BRW_OPCODE_F16TO32
:
4321 case BRW_OPCODE_BFREV
:
4322 case BRW_OPCODE_BFE
:
4323 case BRW_OPCODE_BFI1
:
4324 case BRW_OPCODE_BFI2
:
4325 case BRW_OPCODE_ADD
:
4326 case BRW_OPCODE_MUL
:
4327 case BRW_OPCODE_AVG
:
4328 case BRW_OPCODE_FRC
:
4329 case BRW_OPCODE_RNDU
:
4330 case BRW_OPCODE_RNDD
:
4331 case BRW_OPCODE_RNDE
:
4332 case BRW_OPCODE_RNDZ
:
4333 case BRW_OPCODE_LZD
:
4334 case BRW_OPCODE_FBH
:
4335 case BRW_OPCODE_FBL
:
4336 case BRW_OPCODE_CBIT
:
4337 case BRW_OPCODE_SAD2
:
4338 case BRW_OPCODE_MAD
:
4339 case BRW_OPCODE_LRP
:
4340 case SHADER_OPCODE_RCP
:
4341 case SHADER_OPCODE_RSQ
:
4342 case SHADER_OPCODE_SQRT
:
4343 case SHADER_OPCODE_EXP2
:
4344 case SHADER_OPCODE_LOG2
:
4345 case SHADER_OPCODE_POW
:
4346 case SHADER_OPCODE_INT_QUOTIENT
:
4347 case SHADER_OPCODE_INT_REMAINDER
:
4348 case SHADER_OPCODE_SIN
:
4349 case SHADER_OPCODE_COS
: {
4350 /* According to the PRMs:
4351 * "A. In Direct Addressing mode, a source cannot span more than 2
4352 * adjacent GRF registers.
4353 * B. A destination cannot span more than 2 adjacent GRF registers."
4355 * Look for the source or destination with the largest register region
4356 * which is the one that is going to limit the overal execution size of
4357 * the instruction due to this rule.
4359 unsigned reg_count
= inst
->regs_written
;
4361 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4362 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4364 /* Calculate the maximum execution size of the instruction based on the
4365 * factor by which it goes over the hardware limit of 2 GRFs.
4367 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4369 case SHADER_OPCODE_MULH
:
4370 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4371 * is 8-wide on Gen7+.
4373 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4375 case FS_OPCODE_FB_WRITE_LOGICAL
:
4376 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4379 assert(devinfo
->gen
!= 6 ||
4380 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4381 inst
->exec_size
== 8);
4382 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4383 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4384 8 : inst
->exec_size
);
4386 case SHADER_OPCODE_TXD_LOGICAL
:
4387 /* TXD is unsupported in SIMD16 mode. */
4390 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4391 /* gather4_po_c is unsupported in SIMD16 mode. */
4392 const fs_reg
&shadow_c
= inst
->src
[1];
4393 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4395 case SHADER_OPCODE_TXL_LOGICAL
:
4396 case FS_OPCODE_TXB_LOGICAL
: {
4397 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4398 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4399 * mode because the message exceeds the maximum length of 11.
4401 const fs_reg
&shadow_c
= inst
->src
[1];
4402 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4404 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4407 return inst
->exec_size
;
4409 case SHADER_OPCODE_TXF_LOGICAL
:
4410 case SHADER_OPCODE_TXS_LOGICAL
:
4411 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4412 * messages. Use SIMD16 instead.
4414 if (devinfo
->gen
== 4)
4417 return inst
->exec_size
;
4419 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4420 /* This opcode can take up to 6 arguments which means that in some
4421 * circumstances it can end up with a message that is too long in SIMD16
4424 const unsigned coord_components
= inst
->src
[8].ud
;
4425 /* First three arguments are the sample index and the two arguments for
4428 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4431 return inst
->exec_size
;
4434 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4435 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4436 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4440 return inst
->exec_size
;
4445 * The \p rows array of registers represents a \p num_rows by \p num_columns
4446 * matrix in row-major order, write it in column-major order into the register
4447 * passed as destination. \p stride gives the separation between matrix
4448 * elements in the input in fs_builder::dispatch_width() units.
4451 emit_transpose(const fs_builder
&bld
,
4452 const fs_reg
&dst
, const fs_reg
*rows
,
4453 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4455 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4457 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4458 for (unsigned j
= 0; j
< num_rows
; ++j
)
4459 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4462 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4464 delete[] components
;
4468 fs_visitor::lower_simd_width()
4470 bool progress
= false;
4472 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4473 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4475 if (lower_width
!= inst
->exec_size
) {
4476 /* Builder matching the original instruction. We may also need to
4477 * emit an instruction of width larger than the original, set the
4478 * execution size of the builder to the highest of both for now so
4479 * we're sure that both cases can be handled.
4481 const fs_builder ibld
= bld
.at(block
, inst
)
4482 .exec_all(inst
->force_writemask_all
)
4483 .group(MAX2(inst
->exec_size
, lower_width
),
4484 inst
->force_sechalf
);
4486 /* Split the copies in chunks of the execution width of either the
4487 * original or the lowered instruction, whichever is lower.
4489 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4490 const unsigned n
= inst
->exec_size
/ copy_width
;
4491 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4492 inst
->dst
.component_size(inst
->exec_size
);
4495 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4496 !inst
->writes_accumulator
&& !inst
->mlen
);
4498 for (unsigned i
= 0; i
< n
; i
++) {
4499 /* Emit a copy of the original instruction with the lowered width.
4500 * If the EOT flag was set throw it away except for the last
4501 * instruction to avoid killing the thread prematurely.
4503 fs_inst split_inst
= *inst
;
4504 split_inst
.exec_size
= lower_width
;
4505 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4507 /* Select the correct channel enables for the i-th group, then
4508 * transform the sources and destination and emit the lowered
4511 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4513 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4514 if (inst
->src
[j
].file
!= BAD_FILE
&&
4515 !is_uniform(inst
->src
[j
])) {
4516 /* Get the i-th copy_width-wide chunk of the source. */
4517 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4518 const unsigned src_size
= inst
->components_read(j
);
4520 /* Use a trivial transposition to copy one every n
4521 * copy_width-wide components of the register into a
4522 * temporary passed as source to the lowered instruction.
4524 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4525 emit_transpose(lbld
.group(copy_width
, 0),
4526 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4530 if (inst
->regs_written
) {
4531 /* Allocate enough space to hold the result of the lowered
4532 * instruction and fix up the number of registers written.
4534 split_inst
.dst
= dsts
[i
] =
4535 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4536 split_inst
.regs_written
=
4537 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4541 lbld
.emit(split_inst
);
4544 if (inst
->regs_written
) {
4545 /* Distance between useful channels in the temporaries, skipping
4546 * garbage if the lowered instruction is wider than the original.
4548 const unsigned m
= lower_width
/ copy_width
;
4550 /* Interleave the components of the result from the lowered
4551 * instructions. We need to set exec_all() when copying more than
4552 * one half per component, because LOAD_PAYLOAD (in terms of which
4553 * emit_transpose is implemented) can only use the same channel
4554 * enable signals for all of its non-header sources.
4556 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4557 .group(copy_width
, 0),
4558 inst
->dst
, dsts
, n
, dst_size
, m
);
4561 inst
->remove(block
);
4567 invalidate_live_intervals();
4573 fs_visitor::dump_instructions()
4575 dump_instructions(NULL
);
4579 fs_visitor::dump_instructions(const char *name
)
4581 FILE *file
= stderr
;
4582 if (name
&& geteuid() != 0) {
4583 file
= fopen(name
, "w");
4589 calculate_register_pressure();
4590 int ip
= 0, max_pressure
= 0;
4591 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4592 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4593 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4594 dump_instruction(inst
, file
);
4597 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4600 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4601 fprintf(file
, "%4d: ", ip
++);
4602 dump_instruction(inst
, file
);
4606 if (file
!= stderr
) {
4612 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4614 dump_instruction(be_inst
, stderr
);
4618 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4620 fs_inst
*inst
= (fs_inst
*)be_inst
;
4622 if (inst
->predicate
) {
4623 fprintf(file
, "(%cf0.%d) ",
4624 inst
->predicate_inverse
? '-' : '+',
4628 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4630 fprintf(file
, ".sat");
4631 if (inst
->conditional_mod
) {
4632 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4633 if (!inst
->predicate
&&
4634 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4635 inst
->opcode
!= BRW_OPCODE_IF
&&
4636 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4637 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4640 fprintf(file
, "(%d) ", inst
->exec_size
);
4643 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4646 switch (inst
->dst
.file
) {
4648 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
4649 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
4650 inst
->dst
.subreg_offset
)
4651 fprintf(file
, "+%d.%d",
4652 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4655 fprintf(file
, "g%d", inst
->dst
.nr
);
4658 fprintf(file
, "m%d", inst
->dst
.nr
);
4661 fprintf(file
, "(null)");
4664 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4667 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4670 switch (inst
->dst
.nr
) {
4672 fprintf(file
, "null");
4674 case BRW_ARF_ADDRESS
:
4675 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
4677 case BRW_ARF_ACCUMULATOR
:
4678 fprintf(file
, "acc%d", inst
->dst
.subnr
);
4681 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4684 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4687 if (inst
->dst
.subnr
)
4688 fprintf(file
, "+%d", inst
->dst
.subnr
);
4691 unreachable("not reached");
4693 if (inst
->dst
.stride
!= 1)
4694 fprintf(file
, "<%u>", inst
->dst
.stride
);
4695 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4697 for (int i
= 0; i
< inst
->sources
; i
++) {
4698 if (inst
->src
[i
].negate
)
4700 if (inst
->src
[i
].abs
)
4702 switch (inst
->src
[i
].file
) {
4704 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
4705 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
4706 inst
->src
[i
].subreg_offset
)
4707 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4708 inst
->src
[i
].subreg_offset
);
4711 fprintf(file
, "g%d", inst
->src
[i
].nr
);
4714 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
4717 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
4720 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
4721 if (inst
->src
[i
].reladdr
) {
4722 fprintf(file
, "+reladdr");
4723 } else if (inst
->src
[i
].subreg_offset
) {
4724 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4725 inst
->src
[i
].subreg_offset
);
4729 fprintf(file
, "(null)");
4732 switch (inst
->src
[i
].type
) {
4733 case BRW_REGISTER_TYPE_F
:
4734 fprintf(file
, "%ff", inst
->src
[i
].f
);
4736 case BRW_REGISTER_TYPE_W
:
4737 case BRW_REGISTER_TYPE_D
:
4738 fprintf(file
, "%dd", inst
->src
[i
].d
);
4740 case BRW_REGISTER_TYPE_UW
:
4741 case BRW_REGISTER_TYPE_UD
:
4742 fprintf(file
, "%uu", inst
->src
[i
].ud
);
4744 case BRW_REGISTER_TYPE_VF
:
4745 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4746 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
4747 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
4748 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
4749 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
4752 fprintf(file
, "???");
4757 switch (inst
->src
[i
].nr
) {
4759 fprintf(file
, "null");
4761 case BRW_ARF_ADDRESS
:
4762 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
4764 case BRW_ARF_ACCUMULATOR
:
4765 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
4768 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4771 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4774 if (inst
->src
[i
].subnr
)
4775 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
4778 if (inst
->src
[i
].abs
)
4781 if (inst
->src
[i
].file
!= IMM
) {
4783 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
4784 unsigned hstride
= inst
->src
[i
].hstride
;
4785 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
4787 stride
= inst
->src
[i
].stride
;
4790 fprintf(file
, "<%u>", stride
);
4792 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4795 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4796 fprintf(file
, ", ");
4801 if (inst
->force_writemask_all
)
4802 fprintf(file
, "NoMask ");
4804 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4805 if (inst
->force_sechalf
)
4806 fprintf(file
, "2ndhalf ");
4808 fprintf(file
, "1sthalf ");
4811 fprintf(file
, "\n");
4815 * Possibly returns an instruction that set up @param reg.
4817 * Sometimes we want to take the result of some expression/variable
4818 * dereference tree and rewrite the instruction generating the result
4819 * of the tree. When processing the tree, we know that the
4820 * instructions generated are all writing temporaries that are dead
4821 * outside of this tree. So, if we have some instructions that write
4822 * a temporary, we're free to point that temp write somewhere else.
4824 * Note that this doesn't guarantee that the instruction generated
4825 * only reg -- it might be the size=4 destination of a texture instruction.
4828 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4833 end
->is_partial_write() ||
4835 !reg
.equals(end
->dst
)) {
4843 fs_visitor::setup_payload_gen6()
4846 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4847 unsigned barycentric_interp_modes
=
4848 (stage
== MESA_SHADER_FRAGMENT
) ?
4849 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4851 assert(devinfo
->gen
>= 6);
4853 /* R0-1: masks, pixel X/Y coordinates. */
4854 payload
.num_regs
= 2;
4855 /* R2: only for 32-pixel dispatch.*/
4857 /* R3-26: barycentric interpolation coordinates. These appear in the
4858 * same order that they appear in the brw_wm_barycentric_interp_mode
4859 * enum. Each set of coordinates occupies 2 registers if dispatch width
4860 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4861 * appear if they were enabled using the "Barycentric Interpolation
4862 * Mode" bits in WM_STATE.
4864 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4865 if (barycentric_interp_modes
& (1 << i
)) {
4866 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4867 payload
.num_regs
+= 2;
4868 if (dispatch_width
== 16) {
4869 payload
.num_regs
+= 2;
4874 /* R27: interpolated depth if uses source depth */
4876 payload
.source_depth_reg
= payload
.num_regs
;
4878 if (dispatch_width
== 16) {
4879 /* R28: interpolated depth if not SIMD8. */
4883 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4885 payload
.source_w_reg
= payload
.num_regs
;
4887 if (dispatch_width
== 16) {
4888 /* R30: interpolated W if not SIMD8. */
4893 if (stage
== MESA_SHADER_FRAGMENT
) {
4894 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4895 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4896 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4897 /* R31: MSAA position offsets. */
4898 if (prog_data
->uses_pos_offset
) {
4899 payload
.sample_pos_reg
= payload
.num_regs
;
4904 /* R32: MSAA input coverage mask */
4905 if (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4906 assert(devinfo
->gen
>= 7);
4907 payload
.sample_mask_in_reg
= payload
.num_regs
;
4909 if (dispatch_width
== 16) {
4910 /* R33: input coverage mask if not SIMD8. */
4915 /* R34-: bary for 32-pixel. */
4916 /* R58-59: interp W for 32-pixel. */
4918 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4919 source_depth_to_render_target
= true;
4924 fs_visitor::setup_vs_payload()
4926 /* R0: thread header, R1: urb handles */
4927 payload
.num_regs
= 2;
4931 * We are building the local ID push constant data using the simplest possible
4932 * method. We simply push the local IDs directly as they should appear in the
4933 * registers for the uvec3 gl_LocalInvocationID variable.
4935 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4936 * registers worth of push constant space.
4938 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
4939 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
4942 * FINISHME: There are a few easy optimizations to consider.
4944 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
4945 * no need for using push constant space for that dimension.
4947 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
4948 * easily use 16-bit words rather than 32-bit dwords in the push constant
4951 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
4952 * conveying the data, and thereby reduce push constant usage.
4956 fs_visitor::setup_gs_payload()
4958 assert(stage
== MESA_SHADER_GEOMETRY
);
4960 struct brw_gs_prog_data
*gs_prog_data
=
4961 (struct brw_gs_prog_data
*) prog_data
;
4962 struct brw_vue_prog_data
*vue_prog_data
=
4963 (struct brw_vue_prog_data
*) prog_data
;
4965 /* R0: thread header, R1: output URB handles */
4966 payload
.num_regs
= 2;
4968 if (gs_prog_data
->include_primitive_id
) {
4969 /* R2: Primitive ID 0..7 */
4973 /* Use a maximum of 32 registers for push-model inputs. */
4974 const unsigned max_push_components
= 32;
4976 /* If pushing our inputs would take too many registers, reduce the URB read
4977 * length (which is in HWords, or 8 registers), and resort to pulling.
4979 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
4980 * have to multiply by VerticesIn to obtain the total storage requirement.
4982 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
4983 max_push_components
) {
4984 gs_prog_data
->base
.include_vue_handles
= true;
4986 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
4987 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
4989 vue_prog_data
->urb_read_length
=
4990 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
4995 fs_visitor::setup_cs_payload()
4997 assert(devinfo
->gen
>= 7);
4998 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
5000 payload
.num_regs
= 1;
5002 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
5003 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
5004 payload
.local_invocation_id_reg
= payload
.num_regs
;
5005 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
5010 fs_visitor::calculate_register_pressure()
5012 invalidate_live_intervals();
5013 calculate_live_intervals();
5015 unsigned num_instructions
= 0;
5016 foreach_block(block
, cfg
)
5017 num_instructions
+= block
->instructions
.length();
5019 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5021 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5022 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5023 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5028 fs_visitor::optimize()
5030 /* Start by validating the shader we currently have. */
5033 /* bld is the common builder object pointing at the end of the program we
5034 * used to translate it into i965 IR. For the optimization and lowering
5035 * passes coming next, any code added after the end of the program without
5036 * having explicitly called fs_builder::at() clearly points at a mistake.
5037 * Ideally optimization passes wouldn't be part of the visitor so they
5038 * wouldn't have access to bld at all, but they do, so just in case some
5039 * pass forgets to ask for a location explicitly set it to NULL here to
5040 * make it trip. The dispatch width is initialized to a bogus value to
5041 * make sure that optimizations set the execution controls explicitly to
5042 * match the code they are manipulating instead of relying on the defaults.
5044 bld
= fs_builder(this, 64);
5046 assign_constant_locations();
5047 demote_pull_constants();
5051 split_virtual_grfs();
5054 #define OPT(pass, args...) ({ \
5056 bool this_progress = pass(args); \
5058 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5059 char filename[64]; \
5060 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5061 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5063 backend_shader::dump_instructions(filename); \
5068 progress = progress || this_progress; \
5072 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5074 snprintf(filename
, 64, "%s%d-%s-00-start",
5075 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5077 backend_shader::dump_instructions(filename
);
5080 bool progress
= false;
5084 OPT(lower_simd_width
);
5085 OPT(lower_logical_sends
);
5092 OPT(remove_duplicate_mrf_writes
);
5096 OPT(opt_copy_propagate
);
5097 OPT(opt_predicated_break
, this);
5098 OPT(opt_cmod_propagation
);
5099 OPT(dead_code_eliminate
);
5100 OPT(opt_peephole_sel
);
5101 OPT(dead_control_flow_eliminate
, this);
5102 OPT(opt_register_renaming
);
5103 OPT(opt_redundant_discard_jumps
);
5104 OPT(opt_saturate_propagation
);
5105 OPT(opt_zero_samples
);
5106 OPT(register_coalesce
);
5107 OPT(compute_to_mrf
);
5108 OPT(eliminate_find_live_channel
);
5110 OPT(compact_virtual_grfs
);
5115 OPT(opt_sampler_eot
);
5117 if (OPT(lower_load_payload
)) {
5118 split_virtual_grfs();
5119 OPT(register_coalesce
);
5120 OPT(compute_to_mrf
);
5121 OPT(dead_code_eliminate
);
5124 OPT(opt_combine_constants
);
5125 OPT(lower_integer_multiplication
);
5127 lower_uniform_pull_constant_loads();
5133 * Three source instruction must have a GRF/MRF destination register.
5134 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5137 fs_visitor::fixup_3src_null_dest()
5139 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5140 if (inst
->is_3src() && inst
->dst
.is_null()) {
5141 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5148 fs_visitor::allocate_registers()
5150 bool allocated_without_spills
;
5152 static const enum instruction_scheduler_mode pre_modes
[] = {
5154 SCHEDULE_PRE_NON_LIFO
,
5158 /* Try each scheduling heuristic to see if it can successfully register
5159 * allocate without spilling. They should be ordered by decreasing
5160 * performance but increasing likelihood of allocating.
5162 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5163 schedule_instructions(pre_modes
[i
]);
5166 assign_regs_trivial();
5167 allocated_without_spills
= true;
5169 allocated_without_spills
= assign_regs(false);
5171 if (allocated_without_spills
)
5175 if (!allocated_without_spills
) {
5176 /* We assume that any spilling is worse than just dropping back to
5177 * SIMD8. There's probably actually some intermediate point where
5178 * SIMD16 with a couple of spills is still better.
5180 if (dispatch_width
== 16) {
5181 fail("Failure to register allocate. Reduce number of "
5182 "live scalar values to avoid this.");
5184 compiler
->shader_perf_log(log_data
,
5185 "%s shader triggered register spilling. "
5186 "Try reducing the number of live scalar "
5187 "values to improve performance.\n",
5191 /* Since we're out of heuristics, just go spill registers until we
5192 * get an allocation.
5194 while (!assign_regs(true)) {
5200 /* This must come after all optimization and register allocation, since
5201 * it inserts dead code that happens to have side effects, and it does
5202 * so based on the actual physical registers in use.
5204 insert_gen4_send_dependency_workarounds();
5209 schedule_instructions(SCHEDULE_POST
);
5211 if (last_scratch
> 0)
5212 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5216 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5218 assert(stage
== MESA_SHADER_VERTEX
);
5222 if (shader_time_index
>= 0)
5223 emit_shader_time_begin();
5230 compute_clip_distance(clip_planes
);
5234 if (shader_time_index
>= 0)
5235 emit_shader_time_end();
5241 assign_curb_setup();
5242 assign_vs_urb_setup();
5244 fixup_3src_null_dest();
5245 allocate_registers();
5251 fs_visitor::run_tes()
5253 assert(stage
== MESA_SHADER_TESS_EVAL
);
5255 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
5256 payload
.num_regs
= 5;
5258 if (shader_time_index
>= 0)
5259 emit_shader_time_begin();
5268 if (shader_time_index
>= 0)
5269 emit_shader_time_end();
5275 assign_curb_setup();
5276 assign_tes_urb_setup();
5278 fixup_3src_null_dest();
5279 allocate_registers();
5285 fs_visitor::run_gs()
5287 assert(stage
== MESA_SHADER_GEOMETRY
);
5291 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
5293 if (gs_compile
->control_data_header_size_bits
> 0) {
5294 /* Create a VGRF to store accumulated control data bits. */
5295 this->control_data_bits
= vgrf(glsl_type::uint_type
);
5297 /* If we're outputting more than 32 control data bits, then EmitVertex()
5298 * will set control_data_bits to 0 after emitting the first vertex.
5299 * Otherwise, we need to initialize it to 0 here.
5301 if (gs_compile
->control_data_header_size_bits
<= 32) {
5302 const fs_builder abld
= bld
.annotate("initialize control data bits");
5303 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
5307 if (shader_time_index
>= 0)
5308 emit_shader_time_begin();
5312 emit_gs_thread_end();
5314 if (shader_time_index
>= 0)
5315 emit_shader_time_end();
5324 assign_curb_setup();
5325 assign_gs_urb_setup();
5327 fixup_3src_null_dest();
5328 allocate_registers();
5334 fs_visitor::run_fs(bool do_rep_send
)
5336 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5337 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5339 assert(stage
== MESA_SHADER_FRAGMENT
);
5341 if (devinfo
->gen
>= 6)
5342 setup_payload_gen6();
5344 setup_payload_gen4();
5348 } else if (do_rep_send
) {
5349 assert(dispatch_width
== 16);
5350 emit_repclear_shader();
5352 if (shader_time_index
>= 0)
5353 emit_shader_time_begin();
5355 calculate_urb_setup();
5356 if (nir
->info
.inputs_read
> 0) {
5357 if (devinfo
->gen
< 6)
5358 emit_interpolation_setup_gen4();
5360 emit_interpolation_setup_gen6();
5363 /* We handle discards by keeping track of the still-live pixels in f0.1.
5364 * Initialize it with the dispatched pixels.
5366 if (wm_prog_data
->uses_kill
) {
5367 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5368 discard_init
->flag_subreg
= 1;
5371 /* Generate FS IR for main(). (the visitor only descends into
5372 * functions called "main").
5379 if (wm_prog_data
->uses_kill
)
5380 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5382 if (wm_key
->alpha_test_func
)
5387 if (shader_time_index
>= 0)
5388 emit_shader_time_end();
5394 assign_curb_setup();
5397 fixup_3src_null_dest();
5398 allocate_registers();
5404 if (dispatch_width
== 8)
5405 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5407 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5413 fs_visitor::run_cs()
5415 assert(stage
== MESA_SHADER_COMPUTE
);
5419 if (shader_time_index
>= 0)
5420 emit_shader_time_begin();
5427 emit_cs_terminate();
5429 if (shader_time_index
>= 0)
5430 emit_shader_time_end();
5436 assign_curb_setup();
5438 fixup_3src_null_dest();
5439 allocate_registers();
5448 * Return a bitfield where bit n is set if barycentric interpolation mode n
5449 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5452 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5453 bool shade_model_flat
,
5454 bool persample_shading
,
5455 const nir_shader
*shader
)
5457 unsigned barycentric_interp_modes
= 0;
5459 nir_foreach_variable(var
, &shader
->inputs
) {
5460 enum glsl_interp_qualifier interp_qualifier
=
5461 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5462 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5463 bool is_sample
= var
->data
.sample
|| persample_shading
;
5464 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5465 (var
->data
.location
== VARYING_SLOT_COL1
);
5467 /* Ignore WPOS and FACE, because they don't require interpolation. */
5468 if (var
->data
.location
== VARYING_SLOT_POS
||
5469 var
->data
.location
== VARYING_SLOT_FACE
)
5472 /* Determine the set (or sets) of barycentric coordinates needed to
5473 * interpolate this variable. Note that when
5474 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5475 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5476 * for lit pixels, so we need both sets of barycentric coordinates.
5478 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5480 barycentric_interp_modes
|=
5481 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5482 } else if (is_sample
) {
5483 barycentric_interp_modes
|=
5484 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5486 if ((!is_centroid
&& !is_sample
) ||
5487 devinfo
->needs_unlit_centroid_workaround
) {
5488 barycentric_interp_modes
|=
5489 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5491 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5492 (!(shade_model_flat
&& is_gl_Color
) &&
5493 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5495 barycentric_interp_modes
|=
5496 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5497 } else if (is_sample
) {
5498 barycentric_interp_modes
|=
5499 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5501 if ((!is_centroid
&& !is_sample
) ||
5502 devinfo
->needs_unlit_centroid_workaround
) {
5503 barycentric_interp_modes
|=
5504 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5509 return barycentric_interp_modes
;
5513 computed_depth_mode(const nir_shader
*shader
)
5515 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5516 switch (shader
->info
.fs
.depth_layout
) {
5517 case FRAG_DEPTH_LAYOUT_NONE
:
5518 case FRAG_DEPTH_LAYOUT_ANY
:
5519 return BRW_PSCDEPTH_ON
;
5520 case FRAG_DEPTH_LAYOUT_GREATER
:
5521 return BRW_PSCDEPTH_ON_GE
;
5522 case FRAG_DEPTH_LAYOUT_LESS
:
5523 return BRW_PSCDEPTH_ON_LE
;
5524 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5525 return BRW_PSCDEPTH_OFF
;
5528 return BRW_PSCDEPTH_OFF
;
5532 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5534 const struct brw_wm_prog_key
*key
,
5535 struct brw_wm_prog_data
*prog_data
,
5536 const nir_shader
*src_shader
,
5537 struct gl_program
*prog
,
5538 int shader_time_index8
, int shader_time_index16
,
5540 unsigned *final_assembly_size
,
5543 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5544 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5546 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5548 /* key->alpha_test_func means simulating alpha testing via discards,
5549 * so the shader definitely kills pixels.
5551 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5552 prog_data
->uses_omask
=
5553 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5554 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5555 prog_data
->computed_stencil
=
5556 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5558 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5560 prog_data
->barycentric_interp_modes
=
5561 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5563 key
->persample_shading
,
5566 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5567 &prog_data
->base
, prog
, shader
, 8,
5568 shader_time_index8
);
5569 if (!v
.run_fs(false /* do_rep_send */)) {
5571 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5576 cfg_t
*simd16_cfg
= NULL
;
5577 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5578 &prog_data
->base
, prog
, shader
, 16,
5579 shader_time_index16
);
5580 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5581 if (!v
.simd16_unsupported
) {
5582 /* Try a SIMD16 compile */
5583 v2
.import_uniforms(&v
);
5584 if (!v2
.run_fs(use_rep_send
)) {
5585 compiler
->shader_perf_log(log_data
,
5586 "SIMD16 shader failed to compile: %s",
5589 simd16_cfg
= v2
.cfg
;
5595 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5596 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5598 prog_data
->no_8
= true;
5601 prog_data
->no_8
= false;
5604 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5605 v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
5607 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5608 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5609 shader
->info
.label
? shader
->info
.label
:
5611 shader
->info
.name
));
5615 g
.generate_code(simd8_cfg
, 8);
5617 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5619 return g
.get_assembly(final_assembly_size
);
5623 fs_visitor::emit_cs_local_invocation_id_setup()
5625 assert(stage
== MESA_SHADER_COMPUTE
);
5627 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5629 struct brw_reg src
=
5630 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5631 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5633 src
.nr
+= dispatch_width
/ 8;
5634 bld
.MOV(offset(*reg
, bld
, 1), src
);
5635 src
.nr
+= dispatch_width
/ 8;
5636 bld
.MOV(offset(*reg
, bld
, 2), src
);
5642 fs_visitor::emit_cs_work_group_id_setup()
5644 assert(stage
== MESA_SHADER_COMPUTE
);
5646 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5648 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5649 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5650 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5652 bld
.MOV(*reg
, r0_1
);
5653 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5654 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5660 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5662 const struct brw_cs_prog_key
*key
,
5663 struct brw_cs_prog_data
*prog_data
,
5664 const nir_shader
*src_shader
,
5665 int shader_time_index
,
5666 unsigned *final_assembly_size
,
5669 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5670 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5672 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5674 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5675 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5676 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5677 unsigned local_workgroup_size
=
5678 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5679 shader
->info
.cs
.local_size
[2];
5681 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5684 const char *fail_msg
= NULL
;
5686 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5688 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5689 NULL
, /* Never used in core profile */
5690 shader
, 8, shader_time_index
);
5692 fail_msg
= v8
.fail_msg
;
5693 } else if (local_workgroup_size
<= 8 * max_cs_threads
) {
5695 prog_data
->simd_size
= 8;
5698 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5699 NULL
, /* Never used in core profile */
5700 shader
, 16, shader_time_index
);
5701 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5702 !fail_msg
&& !v8
.simd16_unsupported
&&
5703 local_workgroup_size
<= 16 * max_cs_threads
) {
5704 /* Try a SIMD16 compile */
5705 v16
.import_uniforms(&v8
);
5706 if (!v16
.run_cs()) {
5707 compiler
->shader_perf_log(log_data
,
5708 "SIMD16 shader failed to compile: %s",
5712 "Couldn't generate SIMD16 program and not "
5713 "enough threads for SIMD8";
5717 prog_data
->simd_size
= 16;
5721 if (unlikely(cfg
== NULL
)) {
5724 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5729 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5730 v8
.promoted_constants
, v8
.runtime_check_aads_emit
, "CS");
5731 if (INTEL_DEBUG
& DEBUG_CS
) {
5732 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5733 shader
->info
.label
? shader
->info
.label
:
5736 g
.enable_debug(name
);
5739 g
.generate_code(cfg
, prog_data
->simd_size
);
5741 return g
.get_assembly(final_assembly_size
);
5745 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
5746 void *buffer
, uint32_t threads
, uint32_t stride
)
5748 if (prog_data
->local_invocation_id_regs
== 0)
5751 /* 'stride' should be an integer number of registers, that is, a multiple
5754 assert(stride
% 32 == 0);
5756 unsigned x
= 0, y
= 0, z
= 0;
5757 for (unsigned t
= 0; t
< threads
; t
++) {
5758 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
5760 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
5761 param
[0 * prog_data
->simd_size
+ i
] = x
;
5762 param
[1 * prog_data
->simd_size
+ i
] = y
;
5763 param
[2 * prog_data
->simd_size
+ i
] = z
;
5766 if (x
== prog_data
->local_size
[0]) {
5769 if (y
== prog_data
->local_size
[1]) {
5772 if (z
== prog_data
->local_size
[2])