2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "compiler/glsl_types.h"
42 #include "compiler/nir/nir_builder.h"
43 #include "program/prog_parameter.h"
47 static unsigned get_lowered_simd_width(const struct brw_device_info
*devinfo
,
51 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
52 const fs_reg
*src
, unsigned sources
)
54 memset(this, 0, sizeof(*this));
56 this->src
= new fs_reg
[MAX2(sources
, 3)];
57 for (unsigned i
= 0; i
< sources
; i
++)
58 this->src
[i
] = src
[i
];
60 this->opcode
= opcode
;
62 this->sources
= sources
;
63 this->exec_size
= exec_size
;
66 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
68 assert(this->exec_size
!= 0);
70 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
72 /* This will be the case for almost all instructions. */
79 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
83 this->regs_written
= 0;
87 unreachable("Invalid destination register file");
90 this->writes_accumulator
= false;
95 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
98 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
100 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
103 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
105 init(opcode
, exec_size
, dst
, NULL
, 0);
108 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
111 const fs_reg src
[1] = { src0
};
112 init(opcode
, exec_size
, dst
, src
, 1);
115 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
116 const fs_reg
&src0
, const fs_reg
&src1
)
118 const fs_reg src
[2] = { src0
, src1
};
119 init(opcode
, exec_size
, dst
, src
, 2);
122 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
123 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
125 const fs_reg src
[3] = { src0
, src1
, src2
};
126 init(opcode
, exec_size
, dst
, src
, 3);
129 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
130 const fs_reg src
[], unsigned sources
)
132 init(opcode
, exec_width
, dst
, src
, sources
);
135 fs_inst::fs_inst(const fs_inst
&that
)
137 memcpy(this, &that
, sizeof(that
));
139 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
141 for (unsigned i
= 0; i
< that
.sources
; i
++)
142 this->src
[i
] = that
.src
[i
];
151 fs_inst::resize_sources(uint8_t num_sources
)
153 if (this->sources
!= num_sources
) {
154 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
156 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
157 src
[i
] = this->src
[i
];
161 this->sources
= num_sources
;
166 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
168 const fs_reg
&surf_index
,
169 const fs_reg
&varying_offset
,
170 uint32_t const_offset
)
172 /* We have our constant surface use a pitch of 4 bytes, so our index can
173 * be any component of a vector, and then we load 4 contiguous
174 * components starting from that.
176 * We break down the const_offset to a portion added to the variable
177 * offset and a portion done using reg_offset, which means that if you
178 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
179 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
180 * CSE can later notice that those loads are all the same and eliminate
181 * the redundant ones.
183 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
184 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
186 /* The pull load message will load a vec4 (16 bytes). If we are loading
187 * a double this means we are only loading 2 elements worth of data.
188 * We also want to use a 32-bit data type for the dst of the load operation
189 * so other parts of the driver don't get confused about the size of the
192 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
193 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
194 vec4_result
, surf_index
, vec4_offset
);
195 inst
->regs_written
= 4 * bld
.dispatch_width() / 8;
197 if (type_sz(dst
.type
) == 8) {
198 shuffle_32bit_load_result_to_64bit_data(
199 bld
, retype(vec4_result
, dst
.type
), vec4_result
, 2);
202 vec4_result
.type
= dst
.type
;
203 bld
.MOV(dst
, offset(vec4_result
, bld
,
204 (const_offset
& 0xf) / type_sz(vec4_result
.type
)));
208 * A helper for MOV generation for fixing up broken hardware SEND dependency
212 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
214 /* The caller always wants uncompressed to emit the minimal extra
215 * dependencies, and to avoid having to deal with aligning its regs to 2.
217 const fs_builder ubld
= bld
.annotate("send dependency resolve")
220 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
224 fs_inst::equals(fs_inst
*inst
) const
226 return (opcode
== inst
->opcode
&&
227 dst
.equals(inst
->dst
) &&
228 src
[0].equals(inst
->src
[0]) &&
229 src
[1].equals(inst
->src
[1]) &&
230 src
[2].equals(inst
->src
[2]) &&
231 saturate
== inst
->saturate
&&
232 predicate
== inst
->predicate
&&
233 conditional_mod
== inst
->conditional_mod
&&
234 mlen
== inst
->mlen
&&
235 base_mrf
== inst
->base_mrf
&&
236 target
== inst
->target
&&
238 header_size
== inst
->header_size
&&
239 shadow_compare
== inst
->shadow_compare
&&
240 exec_size
== inst
->exec_size
&&
241 offset
== inst
->offset
);
245 fs_inst::overwrites_reg(const fs_reg
®
) const
247 return reg
.in_range(dst
, regs_written
);
251 fs_inst::is_send_from_grf() const
254 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
255 case SHADER_OPCODE_SHADER_TIME_ADD
:
256 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
257 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
258 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
259 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
260 case SHADER_OPCODE_UNTYPED_ATOMIC
:
261 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
262 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
263 case SHADER_OPCODE_TYPED_ATOMIC
:
264 case SHADER_OPCODE_TYPED_SURFACE_READ
:
265 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
266 case SHADER_OPCODE_URB_WRITE_SIMD8
:
267 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
268 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
269 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
270 case SHADER_OPCODE_URB_READ_SIMD8
:
271 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
273 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
274 return src
[1].file
== VGRF
;
275 case FS_OPCODE_FB_WRITE
:
276 return src
[0].file
== VGRF
;
279 return src
[0].file
== VGRF
;
286 * Returns true if this instruction's sources and destinations cannot
287 * safely be the same register.
289 * In most cases, a register can be written over safely by the same
290 * instruction that is its last use. For a single instruction, the
291 * sources are dereferenced before writing of the destination starts
294 * However, there are a few cases where this can be problematic:
296 * - Virtual opcodes that translate to multiple instructions in the
297 * code generator: if src == dst and one instruction writes the
298 * destination before a later instruction reads the source, then
299 * src will have been clobbered.
301 * - SIMD16 compressed instructions with certain regioning (see below).
303 * The register allocator uses this information to set up conflicts between
304 * GRF sources and the destination.
307 fs_inst::has_source_and_destination_hazard() const
310 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
311 /* Multiple partial writes to the destination */
314 /* The SIMD16 compressed instruction
316 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
318 * is actually decoded in hardware as:
320 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
321 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
323 * Which is safe. However, if we have uniform accesses
324 * happening, we get into trouble:
326 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
327 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
329 * Now our destination for the first instruction overwrote the
330 * second instruction's src0, and we get garbage for those 8
331 * pixels. There's a similar issue for the pre-gen6
332 * pixel_x/pixel_y, which are registers of 16-bit values and thus
333 * would get stomped by the first decode as well.
335 if (exec_size
== 16) {
336 for (int i
= 0; i
< sources
; i
++) {
337 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
338 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
339 src
[i
].type
== BRW_REGISTER_TYPE_W
||
340 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
341 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
351 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
353 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
356 fs_reg reg
= this->src
[0];
357 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
360 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
363 for (int i
= 0; i
< this->sources
; i
++) {
364 reg
.type
= this->src
[i
].type
;
365 if (!this->src
[i
].equals(reg
))
368 if (i
< this->header_size
) {
371 reg
= horiz_offset(reg
, this->exec_size
);
379 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
381 if (devinfo
->gen
== 6 && is_math())
384 if (is_send_from_grf())
387 if (!backend_instruction::can_do_source_mods())
394 fs_inst::can_change_types() const
396 return dst
.type
== src
[0].type
&&
397 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
398 (opcode
== BRW_OPCODE_MOV
||
399 (opcode
== BRW_OPCODE_SEL
&&
400 dst
.type
== src
[1].type
&&
401 predicate
!= BRW_PREDICATE_NONE
&&
402 !src
[1].abs
&& !src
[1].negate
));
406 fs_inst::has_side_effects() const
408 return this->eot
|| backend_instruction::has_side_effects();
414 memset(this, 0, sizeof(*this));
418 /** Generic unset register constructor. */
422 this->file
= BAD_FILE
;
425 fs_reg::fs_reg(struct ::brw_reg reg
) :
428 this->reg_offset
= 0;
429 this->subreg_offset
= 0;
431 if (this->file
== IMM
&&
432 (this->type
!= BRW_REGISTER_TYPE_V
&&
433 this->type
!= BRW_REGISTER_TYPE_UV
&&
434 this->type
!= BRW_REGISTER_TYPE_VF
)) {
440 fs_reg::equals(const fs_reg
&r
) const
442 return (this->backend_reg::equals(r
) &&
443 subreg_offset
== r
.subreg_offset
&&
448 fs_reg::set_smear(unsigned subreg
)
450 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
451 subreg_offset
= subreg
* type_sz(type
);
457 fs_reg::is_contiguous() const
463 fs_reg::component_size(unsigned width
) const
465 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
468 return MAX2(width
* stride
, 1) * type_sz(type
);
472 type_size_scalar(const struct glsl_type
*type
)
474 unsigned int size
, i
;
476 switch (type
->base_type
) {
479 case GLSL_TYPE_FLOAT
:
481 return type
->components();
482 case GLSL_TYPE_DOUBLE
:
483 return type
->components() * 2;
484 case GLSL_TYPE_ARRAY
:
485 return type_size_scalar(type
->fields
.array
) * type
->length
;
486 case GLSL_TYPE_STRUCT
:
488 for (i
= 0; i
< type
->length
; i
++) {
489 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
492 case GLSL_TYPE_SAMPLER
:
493 /* Samplers take up no register space, since they're baked in at
497 case GLSL_TYPE_ATOMIC_UINT
:
499 case GLSL_TYPE_SUBROUTINE
:
501 case GLSL_TYPE_IMAGE
:
502 return BRW_IMAGE_PARAM_SIZE
;
504 case GLSL_TYPE_ERROR
:
505 case GLSL_TYPE_INTERFACE
:
506 case GLSL_TYPE_FUNCTION
:
507 unreachable("not reached");
513 /* Attribute arrays are loaded as one vec4 per element (or matrix column),
514 * except for double-precision types, which are loaded as one dvec4.
517 type_size_vs_input(const struct glsl_type
*type
)
519 if (type
->is_double()) {
520 return type_size_dvec4(type
);
522 return type_size_vec4(type
);
527 * Create a MOV to read the timestamp register.
529 * The caller is responsible for emitting the MOV. The return value is
530 * the destination of the MOV, with extra parameters set.
533 fs_visitor::get_timestamp(const fs_builder
&bld
)
535 assert(devinfo
->gen
>= 7);
537 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
540 BRW_REGISTER_TYPE_UD
));
542 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
544 /* We want to read the 3 fields we care about even if it's not enabled in
547 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
553 fs_visitor::emit_shader_time_begin()
555 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
557 /* We want only the low 32 bits of the timestamp. Since it's running
558 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
559 * which is plenty of time for our purposes. It is identical across the
560 * EUs, but since it's tracking GPU core speed it will increment at a
561 * varying rate as render P-states change.
563 shader_start_time
.set_smear(0);
567 fs_visitor::emit_shader_time_end()
569 /* Insert our code just before the final SEND with EOT. */
570 exec_node
*end
= this->instructions
.get_tail();
571 assert(end
&& ((fs_inst
*) end
)->eot
);
572 const fs_builder ibld
= bld
.annotate("shader time end")
573 .exec_all().at(NULL
, end
);
575 fs_reg shader_end_time
= get_timestamp(ibld
);
577 /* We only use the low 32 bits of the timestamp - see
578 * emit_shader_time_begin()).
580 * We could also check if render P-states have changed (or anything
581 * else that might disrupt timing) by setting smear to 2 and checking if
582 * that field is != 0.
584 shader_end_time
.set_smear(0);
586 /* Check that there weren't any timestamp reset events (assuming these
587 * were the only two timestamp reads that happened).
589 fs_reg reset
= shader_end_time
;
591 set_condmod(BRW_CONDITIONAL_Z
,
592 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
593 ibld
.IF(BRW_PREDICATE_NORMAL
);
595 fs_reg start
= shader_start_time
;
597 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
600 const fs_builder cbld
= ibld
.group(1, 0);
601 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
603 /* If there were no instructions between the two timestamp gets, the diff
604 * is 2 cycles. Remove that overhead, so I can forget about that when
605 * trying to determine the time taken for single instructions.
607 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
608 SHADER_TIME_ADD(cbld
, 0, diff
);
609 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
610 ibld
.emit(BRW_OPCODE_ELSE
);
611 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
612 ibld
.emit(BRW_OPCODE_ENDIF
);
616 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
617 int shader_time_subindex
,
620 int index
= shader_time_index
* 3 + shader_time_subindex
;
621 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
624 if (dispatch_width
== 8)
625 payload
= vgrf(glsl_type::uvec2_type
);
627 payload
= vgrf(glsl_type::uint_type
);
629 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
633 fs_visitor::vfail(const char *format
, va_list va
)
642 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
643 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
645 this->fail_msg
= msg
;
648 fprintf(stderr
, "%s", msg
);
653 fs_visitor::fail(const char *format
, ...)
657 va_start(va
, format
);
663 * Mark this program as impossible to compile with dispatch width greater
666 * During the SIMD8 compile (which happens first), we can detect and flag
667 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
668 * SIMD16+ compile altogether.
670 * During a compile of dispatch width greater than n (if one happens anyway),
671 * this just calls fail().
674 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
676 if (dispatch_width
> n
) {
679 max_dispatch_width
= n
;
680 compiler
->shader_perf_log(log_data
,
681 "Shader dispatch width limited to SIMD%d: %s",
687 * Returns true if the instruction has a flag that means it won't
688 * update an entire destination register.
690 * For example, dead code elimination and live variable analysis want to know
691 * when a write to a variable screens off any preceding values that were in
695 fs_inst::is_partial_write() const
697 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
698 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
699 !this->dst
.is_contiguous() ||
700 this->dst
.subreg_offset
> 0);
704 fs_inst::components_read(unsigned i
) const
707 case FS_OPCODE_LINTERP
:
713 case FS_OPCODE_PIXEL_X
:
714 case FS_OPCODE_PIXEL_Y
:
718 case FS_OPCODE_FB_WRITE_LOGICAL
:
719 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
720 /* First/second FB write color. */
722 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
726 case SHADER_OPCODE_TEX_LOGICAL
:
727 case SHADER_OPCODE_TXD_LOGICAL
:
728 case SHADER_OPCODE_TXF_LOGICAL
:
729 case SHADER_OPCODE_TXL_LOGICAL
:
730 case SHADER_OPCODE_TXS_LOGICAL
:
731 case FS_OPCODE_TXB_LOGICAL
:
732 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
733 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
734 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
735 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
736 case SHADER_OPCODE_LOD_LOGICAL
:
737 case SHADER_OPCODE_TG4_LOGICAL
:
738 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
739 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
740 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
741 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
742 /* Texture coordinates. */
743 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
744 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
745 /* Texture derivatives. */
746 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
747 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
748 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
749 /* Texture offset. */
750 else if (i
== TEX_LOGICAL_SRC_OFFSET_VALUE
)
753 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
758 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
759 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
760 assert(src
[3].file
== IMM
);
761 /* Surface coordinates. */
764 /* Surface operation source (ignored for reads). */
770 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
771 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
772 assert(src
[3].file
== IMM
&&
774 /* Surface coordinates. */
777 /* Surface operation source. */
783 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
784 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
785 assert(src
[3].file
== IMM
&&
787 const unsigned op
= src
[4].ud
;
788 /* Surface coordinates. */
791 /* Surface operation source. */
792 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
794 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
795 op
== BRW_AOP_PREDEC
))
807 fs_inst::regs_read(int arg
) const
810 case FS_OPCODE_FB_WRITE
:
811 case SHADER_OPCODE_URB_WRITE_SIMD8
:
812 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
813 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
814 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
815 case SHADER_OPCODE_URB_READ_SIMD8
:
816 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
817 case SHADER_OPCODE_UNTYPED_ATOMIC
:
818 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
819 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
820 case SHADER_OPCODE_TYPED_ATOMIC
:
821 case SHADER_OPCODE_TYPED_SURFACE_READ
:
822 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
823 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
828 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
829 /* The payload is actually stored in src1 */
834 case FS_OPCODE_LINTERP
:
839 case SHADER_OPCODE_LOAD_PAYLOAD
:
840 if (arg
< this->header_size
)
844 case CS_OPCODE_CS_TERMINATE
:
845 case SHADER_OPCODE_BARRIER
:
848 case SHADER_OPCODE_MOV_INDIRECT
:
850 assert(src
[2].file
== IMM
);
851 unsigned region_length
= src
[2].ud
;
853 if (src
[0].file
== UNIFORM
) {
854 assert(region_length
% 4 == 0);
855 return region_length
/ 4;
856 } else if (src
[0].file
== FIXED_GRF
) {
857 /* If the start of the region is not register aligned, then
858 * there's some portion of the register that's technically
859 * unread at the beginning.
861 * However, the register allocator works in terms of whole
862 * registers, and does not use subnr. It assumes that the
863 * read starts at the beginning of the register, and extends
864 * regs_read() whole registers beyond that.
866 * To compensate, we extend the region length to include this
867 * unread portion at the beginning.
870 region_length
+= src
[0].subnr
;
872 return DIV_ROUND_UP(region_length
, REG_SIZE
);
874 assert(!"Invalid register file");
880 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
885 switch (src
[arg
].file
) {
895 return DIV_ROUND_UP(components_read(arg
) *
896 src
[arg
].component_size(exec_size
),
899 unreachable("MRF registers are not allowed as sources");
905 /* Return the subset of flag registers that an instruction could
906 * potentially read or write based on the execution controls and flag
907 * subregister number of the instruction.
910 flag_mask(const fs_inst
*inst
)
912 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
913 const unsigned end
= start
+ inst
->exec_size
;
914 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
919 fs_inst::flags_read(const brw_device_info
*devinfo
) const
921 /* XXX - This doesn't consider explicit uses of the flag register as source
924 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
925 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
926 /* The vertical predication modes combine corresponding bits from
927 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
929 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
930 return flag_mask(this) << shift
| flag_mask(this);
931 } else if (predicate
) {
932 return flag_mask(this);
939 fs_inst::flags_written() const
941 /* XXX - This doesn't consider explicit uses of the flag register as
942 * destination region.
944 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
945 opcode
!= BRW_OPCODE_IF
&&
946 opcode
!= BRW_OPCODE_WHILE
)) ||
947 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
948 return flag_mask(this);
955 * Returns how many MRFs an FS opcode will write over.
957 * Note that this is not the 0 or 1 implied writes in an actual gen
958 * instruction -- the FS opcodes often generate MOVs in addition.
961 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
966 if (inst
->base_mrf
== -1)
969 switch (inst
->opcode
) {
970 case SHADER_OPCODE_RCP
:
971 case SHADER_OPCODE_RSQ
:
972 case SHADER_OPCODE_SQRT
:
973 case SHADER_OPCODE_EXP2
:
974 case SHADER_OPCODE_LOG2
:
975 case SHADER_OPCODE_SIN
:
976 case SHADER_OPCODE_COS
:
977 return 1 * dispatch_width
/ 8;
978 case SHADER_OPCODE_POW
:
979 case SHADER_OPCODE_INT_QUOTIENT
:
980 case SHADER_OPCODE_INT_REMAINDER
:
981 return 2 * dispatch_width
/ 8;
982 case SHADER_OPCODE_TEX
:
984 case SHADER_OPCODE_TXD
:
985 case SHADER_OPCODE_TXF
:
986 case SHADER_OPCODE_TXF_CMS
:
987 case SHADER_OPCODE_TXF_MCS
:
988 case SHADER_OPCODE_TG4
:
989 case SHADER_OPCODE_TG4_OFFSET
:
990 case SHADER_OPCODE_TXL
:
991 case SHADER_OPCODE_TXS
:
992 case SHADER_OPCODE_LOD
:
993 case SHADER_OPCODE_SAMPLEINFO
:
995 case FS_OPCODE_FB_WRITE
:
997 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
998 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1000 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1002 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1005 unreachable("not reached");
1010 fs_visitor::vgrf(const glsl_type
*const type
)
1012 int reg_width
= dispatch_width
/ 8;
1013 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
1014 brw_type_for_base_type(type
));
1017 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1022 this->type
= BRW_REGISTER_TYPE_F
;
1023 this->stride
= (file
== UNIFORM
? 0 : 1);
1026 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1032 this->stride
= (file
== UNIFORM
? 0 : 1);
1035 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1036 * This brings in those uniform definitions
1039 fs_visitor::import_uniforms(fs_visitor
*v
)
1041 this->push_constant_loc
= v
->push_constant_loc
;
1042 this->pull_constant_loc
= v
->pull_constant_loc
;
1043 this->uniforms
= v
->uniforms
;
1047 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1049 assert(stage
== MESA_SHADER_FRAGMENT
);
1051 /* gl_FragCoord.x */
1052 bld
.MOV(wpos
, this->pixel_x
);
1053 wpos
= offset(wpos
, bld
, 1);
1055 /* gl_FragCoord.y */
1056 bld
.MOV(wpos
, this->pixel_y
);
1057 wpos
= offset(wpos
, bld
, 1);
1059 /* gl_FragCoord.z */
1060 if (devinfo
->gen
>= 6) {
1061 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1063 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1064 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1065 interp_reg(VARYING_SLOT_POS
, 2));
1067 wpos
= offset(wpos
, bld
, 1);
1069 /* gl_FragCoord.w: Already set up in emit_interpolation */
1070 bld
.MOV(wpos
, this->wpos_w
);
1073 enum brw_barycentric_mode
1074 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1076 /* Barycentric modes don't make sense for flat inputs. */
1077 assert(mode
!= INTERP_MODE_FLAT
);
1081 case nir_intrinsic_load_barycentric_pixel
:
1082 case nir_intrinsic_load_barycentric_at_offset
:
1083 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1085 case nir_intrinsic_load_barycentric_centroid
:
1086 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1088 case nir_intrinsic_load_barycentric_sample
:
1089 case nir_intrinsic_load_barycentric_at_sample
:
1090 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1093 unreachable("invalid intrinsic");
1096 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1099 return (enum brw_barycentric_mode
) bary
;
1103 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1105 static enum brw_barycentric_mode
1106 centroid_to_pixel(enum brw_barycentric_mode bary
)
1108 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1109 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1110 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1114 fs_visitor::emit_frontfacing_interpolation()
1116 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1118 if (devinfo
->gen
>= 6) {
1119 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1120 * a boolean result from this (~0/true or 0/false).
1122 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1123 * this task in only one instruction:
1124 * - a negation source modifier will flip the bit; and
1125 * - a W -> D type conversion will sign extend the bit into the high
1126 * word of the destination.
1128 * An ASR 15 fills the low word of the destination.
1130 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1133 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1135 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1136 * a boolean result from this (1/true or 0/false).
1138 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1139 * the negation source modifier to flip it. Unfortunately the SHR
1140 * instruction only operates on UD (or D with an abs source modifier)
1141 * sources without negation.
1143 * Instead, use ASR (which will give ~0/true or 0/false).
1145 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1148 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1155 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1157 assert(stage
== MESA_SHADER_FRAGMENT
);
1158 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1159 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1161 if (wm_prog_data
->persample_dispatch
) {
1162 /* Convert int_sample_pos to floating point */
1163 bld
.MOV(dst
, int_sample_pos
);
1164 /* Scale to the range [0, 1] */
1165 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1168 /* From ARB_sample_shading specification:
1169 * "When rendering to a non-multisample buffer, or if multisample
1170 * rasterization is disabled, gl_SamplePosition will always be
1173 bld
.MOV(dst
, brw_imm_f(0.5f
));
1178 fs_visitor::emit_samplepos_setup()
1180 assert(devinfo
->gen
>= 6);
1182 const fs_builder abld
= bld
.annotate("compute sample position");
1183 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1185 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1186 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1188 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1189 * mode will be enabled.
1191 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1192 * R31.1:0 Position Offset X/Y for Slot[3:0]
1193 * R31.3:2 Position Offset X/Y for Slot[7:4]
1196 * The X, Y sample positions come in as bytes in thread payload. So, read
1197 * the positions using vstride=16, width=8, hstride=2.
1199 struct brw_reg sample_pos_reg
=
1200 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1201 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1203 if (dispatch_width
== 8) {
1204 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1206 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1207 abld
.half(1).MOV(half(int_sample_x
, 1),
1208 fs_reg(suboffset(sample_pos_reg
, 16)));
1210 /* Compute gl_SamplePosition.x */
1211 compute_sample_position(pos
, int_sample_x
);
1212 pos
= offset(pos
, abld
, 1);
1213 if (dispatch_width
== 8) {
1214 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1216 abld
.half(0).MOV(half(int_sample_y
, 0),
1217 fs_reg(suboffset(sample_pos_reg
, 1)));
1218 abld
.half(1).MOV(half(int_sample_y
, 1),
1219 fs_reg(suboffset(sample_pos_reg
, 17)));
1221 /* Compute gl_SamplePosition.y */
1222 compute_sample_position(pos
, int_sample_y
);
1227 fs_visitor::emit_sampleid_setup()
1229 assert(stage
== MESA_SHADER_FRAGMENT
);
1230 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1231 assert(devinfo
->gen
>= 6);
1233 const fs_builder abld
= bld
.annotate("compute sample id");
1234 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1236 if (!key
->multisample_fbo
) {
1237 /* As per GL_ARB_sample_shading specification:
1238 * "When rendering to a non-multisample buffer, or if multisample
1239 * rasterization is disabled, gl_SampleID will always be zero."
1241 abld
.MOV(*reg
, brw_imm_d(0));
1242 } else if (devinfo
->gen
>= 8) {
1243 /* Sample ID comes in as 4-bit numbers in g1.0:
1245 * 15:12 Slot 3 SampleID (only used in SIMD16)
1246 * 11:8 Slot 2 SampleID (only used in SIMD16)
1247 * 7:4 Slot 1 SampleID
1248 * 3:0 Slot 0 SampleID
1250 * Each slot corresponds to four channels, so we want to replicate each
1251 * half-byte value to 4 channels in a row:
1253 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1254 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1256 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1257 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1259 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1260 * channels to read the first byte (7:0), and the second group of 8
1261 * channels to read the second byte (15:8). Then, we shift right by
1262 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1263 * values into place. Finally, we AND with 0xf to keep the low nibble.
1265 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1266 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1268 * TODO: These payload bits exist on Gen7 too, but they appear to always
1269 * be zero, so this code fails to work. We should find out why.
1271 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1273 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1274 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1275 brw_imm_v(0x44440000));
1276 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1278 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1280 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1282 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1283 * 8x multisampling, subspan 0 will represent sample N (where N
1284 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1285 * 7. We can find the value of N by looking at R0.0 bits 7:6
1286 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1287 * (since samples are always delivered in pairs). That is, we
1288 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1289 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1290 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1291 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1292 * populating a temporary variable with the sequence (0, 1, 2, 3),
1293 * and then reading from it using vstride=1, width=4, hstride=0.
1294 * These computations hold good for 4x multisampling as well.
1296 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1297 * the first four slots are sample 0 of subspan 0; the next four
1298 * are sample 1 of subspan 0; the third group is sample 0 of
1299 * subspan 1, and finally sample 1 of subspan 1.
1302 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1303 * accomodate 16x MSAA.
1305 abld
.exec_all().group(1, 0)
1306 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1308 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1310 /* This works for both SIMD8 and SIMD16 */
1311 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1313 /* This special instruction takes care of setting vstride=1,
1314 * width=4, hstride=0 of t2 during an ADD instruction.
1316 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1323 fs_visitor::emit_samplemaskin_setup()
1325 assert(stage
== MESA_SHADER_FRAGMENT
);
1326 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1327 assert(devinfo
->gen
>= 6);
1329 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1331 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1332 BRW_REGISTER_TYPE_D
));
1334 if (wm_prog_data
->persample_dispatch
) {
1335 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1336 * and a mask representing which sample is being processed by the
1337 * current shader invocation.
1339 * From the OES_sample_variables specification:
1340 * "When per-sample shading is active due to the use of a fragment input
1341 * qualified by "sample" or due to the use of the gl_SampleID or
1342 * gl_SamplePosition variables, only the bit for the current sample is
1343 * set in gl_SampleMaskIn."
1345 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1347 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1348 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1350 fs_reg one
= vgrf(glsl_type::int_type
);
1351 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1352 abld
.MOV(one
, brw_imm_d(1));
1353 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1354 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1356 /* In per-pixel mode, the coverage mask is sufficient. */
1357 *reg
= coverage_mask
;
1363 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1365 if (!src
.abs
&& !src
.negate
)
1368 fs_reg temp
= bld
.vgrf(src
.type
);
1375 fs_visitor::emit_discard_jump()
1377 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1379 /* For performance, after a discard, jump to the end of the
1380 * shader if all relevant channels have been discarded.
1382 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1383 discard_jump
->flag_subreg
= 1;
1385 discard_jump
->predicate
= (dispatch_width
== 8)
1386 ? BRW_PREDICATE_ALIGN1_ANY8H
1387 : BRW_PREDICATE_ALIGN1_ANY16H
;
1388 discard_jump
->predicate_inverse
= true;
1392 fs_visitor::emit_gs_thread_end()
1394 assert(stage
== MESA_SHADER_GEOMETRY
);
1396 struct brw_gs_prog_data
*gs_prog_data
=
1397 (struct brw_gs_prog_data
*) prog_data
;
1399 if (gs_compile
->control_data_header_size_bits
> 0) {
1400 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1403 const fs_builder abld
= bld
.annotate("thread end");
1406 if (gs_prog_data
->static_vertex_count
!= -1) {
1407 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1408 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1409 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1410 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1411 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1414 /* Delete now dead instructions. */
1415 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1421 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1425 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1426 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1427 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1430 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1431 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1432 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1433 sources
[1] = this->final_gs_vertex_count
;
1434 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1435 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1443 fs_visitor::assign_curb_setup()
1445 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1447 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1448 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1449 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1450 if (inst
->src
[i
].file
== UNIFORM
) {
1451 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1453 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1454 constant_nr
= push_constant_loc
[uniform_nr
];
1456 /* Section 5.11 of the OpenGL 4.1 spec says:
1457 * "Out-of-bounds reads return undefined values, which include
1458 * values from other variables of the active program or zero."
1459 * Just return the first push constant.
1464 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1467 brw_reg
.abs
= inst
->src
[i
].abs
;
1468 brw_reg
.negate
= inst
->src
[i
].negate
;
1470 assert(inst
->src
[i
].stride
== 0);
1471 inst
->src
[i
] = byte_offset(
1472 retype(brw_reg
, inst
->src
[i
].type
),
1473 inst
->src
[i
].subreg_offset
);
1478 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1479 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1483 fs_visitor::calculate_urb_setup()
1485 assert(stage
== MESA_SHADER_FRAGMENT
);
1486 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1487 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1489 memset(prog_data
->urb_setup
, -1,
1490 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1493 /* Figure out where each of the incoming setup attributes lands. */
1494 if (devinfo
->gen
>= 6) {
1495 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1496 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1497 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1498 * first 16 varying inputs, so we can put them wherever we want.
1499 * Just put them in order.
1501 * This is useful because it means that (a) inputs not used by the
1502 * fragment shader won't take up valuable register space, and (b) we
1503 * won't have to recompile the fragment shader if it gets paired with
1504 * a different vertex (or geometry) shader.
1506 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1507 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1508 BITFIELD64_BIT(i
)) {
1509 prog_data
->urb_setup
[i
] = urb_next
++;
1513 bool include_vue_header
=
1514 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1516 /* We have enough input varyings that the SF/SBE pipeline stage can't
1517 * arbitrarily rearrange them to suit our whim; we have to put them
1518 * in an order that matches the output of the previous pipeline stage
1519 * (geometry or vertex shader).
1521 struct brw_vue_map prev_stage_vue_map
;
1522 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1523 key
->input_slots_valid
,
1524 nir
->info
.separate_shader
);
1526 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1528 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1529 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1531 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1532 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1533 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1534 BITFIELD64_BIT(varying
))) {
1535 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1538 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1541 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1542 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1543 /* Point size is packed into the header, not as a general attribute */
1544 if (i
== VARYING_SLOT_PSIZ
)
1547 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1548 /* The back color slot is skipped when the front color is
1549 * also written to. In addition, some slots can be
1550 * written in the vertex shader and not read in the
1551 * fragment shader. So the register number must always be
1552 * incremented, mapped or not.
1554 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1555 prog_data
->urb_setup
[i
] = urb_next
;
1561 * It's a FS only attribute, and we did interpolation for this attribute
1562 * in SF thread. So, count it here, too.
1564 * See compile_sf_prog() for more info.
1566 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1567 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1570 prog_data
->num_varying_inputs
= urb_next
;
1574 fs_visitor::assign_urb_setup()
1576 assert(stage
== MESA_SHADER_FRAGMENT
);
1577 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1579 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1581 /* Offset all the urb_setup[] index by the actual position of the
1582 * setup regs, now that the location of the constants has been chosen.
1584 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1585 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1586 assert(inst
->src
[1].file
== FIXED_GRF
);
1587 inst
->src
[1].nr
+= urb_start
;
1590 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1591 assert(inst
->src
[0].file
== FIXED_GRF
);
1592 inst
->src
[0].nr
+= urb_start
;
1596 /* Each attribute is 4 setup channels, each of which is half a reg. */
1597 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1601 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1603 for (int i
= 0; i
< inst
->sources
; i
++) {
1604 if (inst
->src
[i
].file
== ATTR
) {
1605 int grf
= payload
.num_regs
+
1606 prog_data
->curb_read_length
+
1608 inst
->src
[i
].reg_offset
;
1610 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1612 * VertStride must be used to cross GRF register boundaries. This
1613 * rule implies that elements within a 'Width' cannot cross GRF
1616 * So, for registers that are large enough, we have to split the exec
1617 * size in two and trust the compression state to sort it out.
1619 unsigned total_size
= inst
->exec_size
*
1620 inst
->src
[i
].stride
*
1621 type_sz(inst
->src
[i
].type
);
1623 assert(total_size
<= 2 * REG_SIZE
);
1624 const unsigned exec_size
=
1625 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1627 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1628 struct brw_reg reg
=
1629 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1630 inst
->src
[i
].subreg_offset
),
1631 exec_size
* inst
->src
[i
].stride
,
1632 width
, inst
->src
[i
].stride
);
1633 reg
.abs
= inst
->src
[i
].abs
;
1634 reg
.negate
= inst
->src
[i
].negate
;
1642 fs_visitor::assign_vs_urb_setup()
1644 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1646 assert(stage
== MESA_SHADER_VERTEX
);
1648 /* Each attribute is 4 regs. */
1649 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1651 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1653 /* Rewrite all ATTR file references to the hw grf that they land in. */
1654 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1655 convert_attr_sources_to_hw_regs(inst
);
1660 fs_visitor::assign_tcs_single_patch_urb_setup()
1662 assert(stage
== MESA_SHADER_TESS_CTRL
);
1664 /* Rewrite all ATTR file references to HW_REGs. */
1665 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1666 convert_attr_sources_to_hw_regs(inst
);
1671 fs_visitor::assign_tes_urb_setup()
1673 assert(stage
== MESA_SHADER_TESS_EVAL
);
1675 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1677 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1679 /* Rewrite all ATTR file references to HW_REGs. */
1680 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1681 convert_attr_sources_to_hw_regs(inst
);
1686 fs_visitor::assign_gs_urb_setup()
1688 assert(stage
== MESA_SHADER_GEOMETRY
);
1690 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1692 first_non_payload_grf
+=
1693 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1695 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1696 /* Rewrite all ATTR file references to GRFs. */
1697 convert_attr_sources_to_hw_regs(inst
);
1703 * Split large virtual GRFs into separate components if we can.
1705 * This is mostly duplicated with what brw_fs_vector_splitting does,
1706 * but that's really conservative because it's afraid of doing
1707 * splitting that doesn't result in real progress after the rest of
1708 * the optimization phases, which would cause infinite looping in
1709 * optimization. We can do it once here, safely. This also has the
1710 * opportunity to split interpolated values, or maybe even uniforms,
1711 * which we don't have at the IR level.
1713 * We want to split, because virtual GRFs are what we register
1714 * allocate and spill (due to contiguousness requirements for some
1715 * instructions), and they're what we naturally generate in the
1716 * codegen process, but most virtual GRFs don't actually need to be
1717 * contiguous sets of GRFs. If we split, we'll end up with reduced
1718 * live intervals and better dead code elimination and coalescing.
1721 fs_visitor::split_virtual_grfs()
1723 int num_vars
= this->alloc
.count
;
1725 /* Count the total number of registers */
1727 int vgrf_to_reg
[num_vars
];
1728 for (int i
= 0; i
< num_vars
; i
++) {
1729 vgrf_to_reg
[i
] = reg_count
;
1730 reg_count
+= alloc
.sizes
[i
];
1733 /* An array of "split points". For each register slot, this indicates
1734 * if this slot can be separated from the previous slot. Every time an
1735 * instruction uses multiple elements of a register (as a source or
1736 * destination), we mark the used slots as inseparable. Then we go
1737 * through and split the registers into the smallest pieces we can.
1739 bool split_points
[reg_count
];
1740 memset(split_points
, 0, sizeof(split_points
));
1742 /* Mark all used registers as fully splittable */
1743 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1744 if (inst
->dst
.file
== VGRF
) {
1745 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1746 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1747 split_points
[reg
+ j
] = true;
1750 for (int i
= 0; i
< inst
->sources
; i
++) {
1751 if (inst
->src
[i
].file
== VGRF
) {
1752 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1753 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1754 split_points
[reg
+ j
] = true;
1759 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1760 if (inst
->dst
.file
== VGRF
) {
1761 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1762 for (int j
= 1; j
< inst
->regs_written
; j
++)
1763 split_points
[reg
+ j
] = false;
1765 for (int i
= 0; i
< inst
->sources
; i
++) {
1766 if (inst
->src
[i
].file
== VGRF
) {
1767 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1768 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1769 split_points
[reg
+ j
] = false;
1774 int new_virtual_grf
[reg_count
];
1775 int new_reg_offset
[reg_count
];
1778 for (int i
= 0; i
< num_vars
; i
++) {
1779 /* The first one should always be 0 as a quick sanity check. */
1780 assert(split_points
[reg
] == false);
1783 new_reg_offset
[reg
] = 0;
1788 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1789 /* If this is a split point, reset the offset to 0 and allocate a
1790 * new virtual GRF for the previous offset many registers
1792 if (split_points
[reg
]) {
1793 assert(offset
<= MAX_VGRF_SIZE
);
1794 int grf
= alloc
.allocate(offset
);
1795 for (int k
= reg
- offset
; k
< reg
; k
++)
1796 new_virtual_grf
[k
] = grf
;
1799 new_reg_offset
[reg
] = offset
;
1804 /* The last one gets the original register number */
1805 assert(offset
<= MAX_VGRF_SIZE
);
1806 alloc
.sizes
[i
] = offset
;
1807 for (int k
= reg
- offset
; k
< reg
; k
++)
1808 new_virtual_grf
[k
] = i
;
1810 assert(reg
== reg_count
);
1812 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1813 if (inst
->dst
.file
== VGRF
) {
1814 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1815 inst
->dst
.nr
= new_virtual_grf
[reg
];
1816 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1817 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1819 for (int i
= 0; i
< inst
->sources
; i
++) {
1820 if (inst
->src
[i
].file
== VGRF
) {
1821 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1822 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1823 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1824 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1828 invalidate_live_intervals();
1832 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1834 * During code generation, we create tons of temporary variables, many of
1835 * which get immediately killed and are never used again. Yet, in later
1836 * optimization and analysis passes, such as compute_live_intervals, we need
1837 * to loop over all the virtual GRFs. Compacting them can save a lot of
1841 fs_visitor::compact_virtual_grfs()
1843 bool progress
= false;
1844 int remap_table
[this->alloc
.count
];
1845 memset(remap_table
, -1, sizeof(remap_table
));
1847 /* Mark which virtual GRFs are used. */
1848 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1849 if (inst
->dst
.file
== VGRF
)
1850 remap_table
[inst
->dst
.nr
] = 0;
1852 for (int i
= 0; i
< inst
->sources
; i
++) {
1853 if (inst
->src
[i
].file
== VGRF
)
1854 remap_table
[inst
->src
[i
].nr
] = 0;
1858 /* Compact the GRF arrays. */
1860 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1861 if (remap_table
[i
] == -1) {
1862 /* We just found an unused register. This means that we are
1863 * actually going to compact something.
1867 remap_table
[i
] = new_index
;
1868 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1869 invalidate_live_intervals();
1874 this->alloc
.count
= new_index
;
1876 /* Patch all the instructions to use the newly renumbered registers */
1877 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1878 if (inst
->dst
.file
== VGRF
)
1879 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1881 for (int i
= 0; i
< inst
->sources
; i
++) {
1882 if (inst
->src
[i
].file
== VGRF
)
1883 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1887 /* Patch all the references to delta_xy, since they're used in register
1888 * allocation. If they're unused, switch them to BAD_FILE so we don't
1889 * think some random VGRF is delta_xy.
1891 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1892 if (delta_xy
[i
].file
== VGRF
) {
1893 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1894 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1896 delta_xy
[i
].file
= BAD_FILE
;
1905 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
, bool contiguous
,
1906 int *push_constant_loc
, int *pull_constant_loc
,
1907 unsigned *num_push_constants
,
1908 unsigned *num_pull_constants
,
1909 const unsigned max_push_components
,
1910 const unsigned max_chunk_size
,
1911 struct brw_stage_prog_data
*stage_prog_data
)
1913 /* This is the first live uniform in the chunk */
1914 if (*chunk_start
< 0)
1915 *chunk_start
= uniform
;
1917 /* If this element does not need to be contiguous with the next, we
1918 * split at this point and everything between chunk_start and u forms a
1922 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
1924 /* Decide whether we should push or pull this parameter. In the
1925 * Vulkan driver, push constants are explicitly exposed via the API
1926 * so we push everything. In GL, we only push small arrays.
1928 if (stage_prog_data
->pull_param
== NULL
||
1929 (*num_push_constants
+ chunk_size
<= max_push_components
&&
1930 chunk_size
<= max_chunk_size
)) {
1931 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
1932 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1933 push_constant_loc
[j
] = (*num_push_constants
)++;
1935 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1936 pull_constant_loc
[j
] = (*num_pull_constants
)++;
1944 * Assign UNIFORM file registers to either push constants or pull constants.
1946 * We allow a fragment shader to have more than the specified minimum
1947 * maximum number of fragment shader uniform components (64). If
1948 * there are too many of these, they'd fill up all of register space.
1949 * So, this will push some of them out to the pull constant buffer and
1950 * update the program to load them.
1953 fs_visitor::assign_constant_locations()
1955 /* Only the first compile gets to decide on locations. */
1956 if (dispatch_width
!= min_dispatch_width
)
1959 bool is_live
[uniforms
];
1960 memset(is_live
, 0, sizeof(is_live
));
1961 bool is_live_64bit
[uniforms
];
1962 memset(is_live_64bit
, 0, sizeof(is_live_64bit
));
1964 /* For each uniform slot, a value of true indicates that the given slot and
1965 * the next slot must remain contiguous. This is used to keep us from
1966 * splitting arrays apart.
1968 bool contiguous
[uniforms
];
1969 memset(contiguous
, 0, sizeof(contiguous
));
1971 int thread_local_id_index
=
1972 (stage
== MESA_SHADER_COMPUTE
) ?
1973 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
: -1;
1975 /* First, we walk through the instructions and do two things:
1977 * 1) Figure out which uniforms are live.
1979 * 2) Mark any indirectly used ranges of registers as contiguous.
1981 * Note that we don't move constant-indexed accesses to arrays. No
1982 * testing has been done of the performance impact of this choice.
1984 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1985 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1986 if (inst
->src
[i
].file
!= UNIFORM
)
1989 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1991 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
1992 assert(inst
->src
[2].ud
% 4 == 0);
1993 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
1994 assert(last
< uniforms
);
1996 for (unsigned j
= constant_nr
; j
< last
; j
++) {
1998 contiguous
[j
] = true;
1999 if (type_sz(inst
->src
[i
].type
) == 8) {
2000 is_live_64bit
[j
] = true;
2003 is_live
[last
] = true;
2005 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
2006 int regs_read
= inst
->components_read(i
) *
2007 type_sz(inst
->src
[i
].type
) / 4;
2008 for (int j
= 0; j
< regs_read
; j
++) {
2009 is_live
[constant_nr
+ j
] = true;
2010 if (type_sz(inst
->src
[i
].type
) == 8) {
2011 is_live_64bit
[constant_nr
+ j
] = true;
2019 if (thread_local_id_index
>= 0 && !is_live
[thread_local_id_index
])
2020 thread_local_id_index
= -1;
2022 /* Only allow 16 registers (128 uniform components) as push constants.
2024 * Just demote the end of the list. We could probably do better
2025 * here, demoting things that are rarely used in the program first.
2027 * If changing this value, note the limitation about total_regs in
2030 unsigned int max_push_components
= 16 * 8;
2031 if (thread_local_id_index
>= 0)
2032 max_push_components
--; /* Save a slot for the thread ID */
2034 /* We push small arrays, but no bigger than 16 floats. This is big enough
2035 * for a vec4 but hopefully not large enough to push out other stuff. We
2036 * should probably use a better heuristic at some point.
2038 const unsigned int max_chunk_size
= 16;
2040 unsigned int num_push_constants
= 0;
2041 unsigned int num_pull_constants
= 0;
2043 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2044 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2046 /* Default to -1 meaning no location */
2047 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2048 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2050 int chunk_start
= -1;
2052 /* First push 64-bit uniforms to ensure they are properly aligned */
2053 for (unsigned u
= 0; u
< uniforms
; u
++) {
2054 if (!is_live
[u
] || !is_live_64bit
[u
])
2057 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2058 push_constant_loc
, pull_constant_loc
,
2059 &num_push_constants
, &num_pull_constants
,
2060 max_push_components
, max_chunk_size
,
2065 /* Then push the rest of uniforms */
2066 for (unsigned u
= 0; u
< uniforms
; u
++) {
2067 if (!is_live
[u
] || is_live_64bit
[u
])
2070 /* Skip thread_local_id_index to put it in the last push register. */
2071 if (thread_local_id_index
== (int)u
)
2074 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2075 push_constant_loc
, pull_constant_loc
,
2076 &num_push_constants
, &num_pull_constants
,
2077 max_push_components
, max_chunk_size
,
2081 /* Add the CS local thread ID uniform at the end of the push constants */
2082 if (thread_local_id_index
>= 0)
2083 push_constant_loc
[thread_local_id_index
] = num_push_constants
++;
2085 /* As the uniforms are going to be reordered, take the data from a temporary
2086 * copy of the original param[].
2088 gl_constant_value
**param
= ralloc_array(NULL
, gl_constant_value
*,
2089 stage_prog_data
->nr_params
);
2090 memcpy(param
, stage_prog_data
->param
,
2091 sizeof(gl_constant_value
*) * stage_prog_data
->nr_params
);
2092 stage_prog_data
->nr_params
= num_push_constants
;
2093 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2095 /* Up until now, the param[] array has been indexed by reg + reg_offset
2096 * of UNIFORM registers. Move pull constants into pull_param[] and
2097 * condense param[] to only contain the uniforms we chose to push.
2099 * NOTE: Because we are condensing the params[] array, we know that
2100 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2101 * having to make a copy.
2103 int new_thread_local_id_index
= -1;
2104 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2105 const gl_constant_value
*value
= param
[i
];
2107 if (pull_constant_loc
[i
] != -1) {
2108 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2109 } else if (push_constant_loc
[i
] != -1) {
2110 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2111 if (thread_local_id_index
== (int)i
)
2112 new_thread_local_id_index
= push_constant_loc
[i
];
2117 if (stage
== MESA_SHADER_COMPUTE
)
2118 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
=
2119 new_thread_local_id_index
;
2123 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2124 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2127 fs_visitor::lower_constant_loads()
2129 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2131 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2132 /* Set up the annotation tracking for new generated instructions. */
2133 const fs_builder
ibld(this, block
, inst
);
2135 for (int i
= 0; i
< inst
->sources
; i
++) {
2136 if (inst
->src
[i
].file
!= UNIFORM
)
2139 /* We'll handle this case later */
2140 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2143 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2144 if (location
>= uniforms
)
2145 continue; /* Out of bounds access */
2147 int pull_index
= pull_constant_loc
[location
];
2149 if (pull_index
== -1)
2152 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2155 if (type_sz(inst
->src
[i
].type
) <= 4)
2156 dst
= vgrf(glsl_type::float_type
);
2158 dst
= vgrf(glsl_type::double_type
);
2160 assert(inst
->src
[i
].stride
== 0);
2162 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2163 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2164 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2165 dst
, brw_imm_ud(index
), offset
);
2167 /* Rewrite the instruction to use the temporary VGRF. */
2168 inst
->src
[i
].file
= VGRF
;
2169 inst
->src
[i
].nr
= dst
.nr
;
2170 inst
->src
[i
].reg_offset
= 0;
2171 inst
->src
[i
].set_smear((pull_index
& 3) * 4 /
2172 type_sz(inst
->src
[i
].type
));
2174 brw_mark_surface_used(prog_data
, index
);
2177 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2178 inst
->src
[0].file
== UNIFORM
) {
2180 unsigned location
= inst
->src
[0].nr
+ inst
->src
[0].reg_offset
;
2181 if (location
>= uniforms
)
2182 continue; /* Out of bounds access */
2184 int pull_index
= pull_constant_loc
[location
];
2186 if (pull_index
== -1)
2189 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2193 inst
->remove(block
);
2195 brw_mark_surface_used(prog_data
, index
);
2198 invalidate_live_intervals();
2202 fs_visitor::opt_algebraic()
2204 bool progress
= false;
2206 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2207 switch (inst
->opcode
) {
2208 case BRW_OPCODE_MOV
:
2209 if (inst
->src
[0].file
!= IMM
)
2212 if (inst
->saturate
) {
2213 if (inst
->dst
.type
!= inst
->src
[0].type
)
2214 assert(!"unimplemented: saturate mixed types");
2216 if (brw_saturate_immediate(inst
->dst
.type
,
2217 &inst
->src
[0].as_brw_reg())) {
2218 inst
->saturate
= false;
2224 case BRW_OPCODE_MUL
:
2225 if (inst
->src
[1].file
!= IMM
)
2229 if (inst
->src
[1].is_one()) {
2230 inst
->opcode
= BRW_OPCODE_MOV
;
2231 inst
->src
[1] = reg_undef
;
2237 if (inst
->src
[1].is_negative_one()) {
2238 inst
->opcode
= BRW_OPCODE_MOV
;
2239 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2240 inst
->src
[1] = reg_undef
;
2246 if (inst
->src
[1].is_zero()) {
2247 inst
->opcode
= BRW_OPCODE_MOV
;
2248 inst
->src
[0] = inst
->src
[1];
2249 inst
->src
[1] = reg_undef
;
2254 if (inst
->src
[0].file
== IMM
) {
2255 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2256 inst
->opcode
= BRW_OPCODE_MOV
;
2257 inst
->src
[0].f
*= inst
->src
[1].f
;
2258 inst
->src
[1] = reg_undef
;
2263 case BRW_OPCODE_ADD
:
2264 if (inst
->src
[1].file
!= IMM
)
2268 if (inst
->src
[1].is_zero()) {
2269 inst
->opcode
= BRW_OPCODE_MOV
;
2270 inst
->src
[1] = reg_undef
;
2275 if (inst
->src
[0].file
== IMM
) {
2276 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2277 inst
->opcode
= BRW_OPCODE_MOV
;
2278 inst
->src
[0].f
+= inst
->src
[1].f
;
2279 inst
->src
[1] = reg_undef
;
2285 if (inst
->src
[0].equals(inst
->src
[1])) {
2286 inst
->opcode
= BRW_OPCODE_MOV
;
2287 inst
->src
[1] = reg_undef
;
2292 case BRW_OPCODE_LRP
:
2293 if (inst
->src
[1].equals(inst
->src
[2])) {
2294 inst
->opcode
= BRW_OPCODE_MOV
;
2295 inst
->src
[0] = inst
->src
[1];
2296 inst
->src
[1] = reg_undef
;
2297 inst
->src
[2] = reg_undef
;
2302 case BRW_OPCODE_CMP
:
2303 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2305 inst
->src
[0].negate
&&
2306 inst
->src
[1].is_zero()) {
2307 inst
->src
[0].abs
= false;
2308 inst
->src
[0].negate
= false;
2309 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2314 case BRW_OPCODE_SEL
:
2315 if (inst
->src
[0].equals(inst
->src
[1])) {
2316 inst
->opcode
= BRW_OPCODE_MOV
;
2317 inst
->src
[1] = reg_undef
;
2318 inst
->predicate
= BRW_PREDICATE_NONE
;
2319 inst
->predicate_inverse
= false;
2321 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2322 switch (inst
->conditional_mod
) {
2323 case BRW_CONDITIONAL_LE
:
2324 case BRW_CONDITIONAL_L
:
2325 switch (inst
->src
[1].type
) {
2326 case BRW_REGISTER_TYPE_F
:
2327 if (inst
->src
[1].f
>= 1.0f
) {
2328 inst
->opcode
= BRW_OPCODE_MOV
;
2329 inst
->src
[1] = reg_undef
;
2330 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2338 case BRW_CONDITIONAL_GE
:
2339 case BRW_CONDITIONAL_G
:
2340 switch (inst
->src
[1].type
) {
2341 case BRW_REGISTER_TYPE_F
:
2342 if (inst
->src
[1].f
<= 0.0f
) {
2343 inst
->opcode
= BRW_OPCODE_MOV
;
2344 inst
->src
[1] = reg_undef
;
2345 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2357 case BRW_OPCODE_MAD
:
2358 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2359 inst
->opcode
= BRW_OPCODE_MOV
;
2360 inst
->src
[1] = reg_undef
;
2361 inst
->src
[2] = reg_undef
;
2363 } else if (inst
->src
[0].is_zero()) {
2364 inst
->opcode
= BRW_OPCODE_MUL
;
2365 inst
->src
[0] = inst
->src
[2];
2366 inst
->src
[2] = reg_undef
;
2368 } else if (inst
->src
[1].is_one()) {
2369 inst
->opcode
= BRW_OPCODE_ADD
;
2370 inst
->src
[1] = inst
->src
[2];
2371 inst
->src
[2] = reg_undef
;
2373 } else if (inst
->src
[2].is_one()) {
2374 inst
->opcode
= BRW_OPCODE_ADD
;
2375 inst
->src
[2] = reg_undef
;
2377 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2378 inst
->opcode
= BRW_OPCODE_ADD
;
2379 inst
->src
[1].f
*= inst
->src
[2].f
;
2380 inst
->src
[2] = reg_undef
;
2384 case SHADER_OPCODE_BROADCAST
:
2385 if (is_uniform(inst
->src
[0])) {
2386 inst
->opcode
= BRW_OPCODE_MOV
;
2388 inst
->force_writemask_all
= true;
2390 } else if (inst
->src
[1].file
== IMM
) {
2391 inst
->opcode
= BRW_OPCODE_MOV
;
2392 inst
->src
[0] = component(inst
->src
[0],
2395 inst
->force_writemask_all
= true;
2404 /* Swap if src[0] is immediate. */
2405 if (progress
&& inst
->is_commutative()) {
2406 if (inst
->src
[0].file
== IMM
) {
2407 fs_reg tmp
= inst
->src
[1];
2408 inst
->src
[1] = inst
->src
[0];
2417 * Optimize sample messages that have constant zero values for the trailing
2418 * texture coordinates. We can just reduce the message length for these
2419 * instructions instead of reserving a register for it. Trailing parameters
2420 * that aren't sent default to zero anyway. This will cause the dead code
2421 * eliminator to remove the MOV instruction that would otherwise be emitted to
2422 * set up the zero value.
2425 fs_visitor::opt_zero_samples()
2427 /* Gen4 infers the texturing opcode based on the message length so we can't
2430 if (devinfo
->gen
< 5)
2433 bool progress
= false;
2435 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2436 if (!inst
->is_tex())
2439 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2441 if (load_payload
->is_head_sentinel() ||
2442 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2445 /* We don't want to remove the message header or the first parameter.
2446 * Removing the first parameter is not allowed, see the Haswell PRM
2447 * volume 7, page 149:
2449 * "Parameter 0 is required except for the sampleinfo message, which
2450 * has no parameter 0"
2452 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2453 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2454 (inst
->exec_size
/ 8) +
2455 inst
->header_size
- 1].is_zero()) {
2456 inst
->mlen
-= inst
->exec_size
/ 8;
2462 invalidate_live_intervals();
2468 * Optimize sample messages which are followed by the final RT write.
2470 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2471 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2472 * final texturing results copied to the framebuffer write payload and modify
2473 * them to write to the framebuffer directly.
2476 fs_visitor::opt_sampler_eot()
2478 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2480 if (stage
!= MESA_SHADER_FRAGMENT
)
2483 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2486 /* FINISHME: It should be possible to implement this optimization when there
2487 * are multiple drawbuffers.
2489 if (key
->nr_color_regions
!= 1)
2492 /* Requires emitting a bunch of saturating MOV instructions during logical
2493 * send lowering to clamp the color payload, which the sampler unit isn't
2494 * going to do for us.
2496 if (key
->clamp_fragment_color
)
2499 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2500 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2501 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2502 assert(fb_write
->eot
);
2503 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2505 /* There wasn't one; nothing to do. */
2506 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2509 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2511 /* 3D Sampler » Messages » Message Format
2513 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2514 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2516 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2517 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2518 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2519 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2520 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2521 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2522 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2523 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2526 /* XXX - This shouldn't be necessary. */
2527 if (tex_inst
->prev
->is_head_sentinel())
2530 /* Check that the FB write sources are fully initialized by the single
2531 * texturing instruction.
2533 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2534 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2535 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2536 fb_write
->regs_read(i
) != tex_inst
->regs_written
)
2538 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2539 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2544 assert(!tex_inst
->eot
); /* We can't get here twice */
2545 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2547 const fs_builder
ibld(this, block
, tex_inst
);
2549 tex_inst
->offset
|= fb_write
->target
<< 24;
2550 tex_inst
->eot
= true;
2551 tex_inst
->dst
= ibld
.null_reg_ud();
2552 tex_inst
->regs_written
= 0;
2553 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2555 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2556 * flag and submit a header together with the sampler message as required
2559 invalidate_live_intervals();
2564 fs_visitor::opt_register_renaming()
2566 bool progress
= false;
2569 int remap
[alloc
.count
];
2570 memset(remap
, -1, sizeof(int) * alloc
.count
);
2572 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2573 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2575 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2576 inst
->opcode
== BRW_OPCODE_WHILE
) {
2580 /* Rewrite instruction sources. */
2581 for (int i
= 0; i
< inst
->sources
; i
++) {
2582 if (inst
->src
[i
].file
== VGRF
&&
2583 remap
[inst
->src
[i
].nr
] != -1 &&
2584 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2585 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2590 const int dst
= inst
->dst
.nr
;
2593 inst
->dst
.file
== VGRF
&&
2594 alloc
.sizes
[inst
->dst
.nr
] == inst
->regs_written
&&
2595 !inst
->is_partial_write()) {
2596 if (remap
[dst
] == -1) {
2599 remap
[dst
] = alloc
.allocate(inst
->regs_written
);
2600 inst
->dst
.nr
= remap
[dst
];
2603 } else if (inst
->dst
.file
== VGRF
&&
2605 remap
[dst
] != dst
) {
2606 inst
->dst
.nr
= remap
[dst
];
2612 invalidate_live_intervals();
2614 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2615 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2616 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2625 * Remove redundant or useless discard jumps.
2627 * For example, we can eliminate jumps in the following sequence:
2629 * discard-jump (redundant with the next jump)
2630 * discard-jump (useless; jumps to the next instruction)
2634 fs_visitor::opt_redundant_discard_jumps()
2636 bool progress
= false;
2638 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2640 fs_inst
*placeholder_halt
= NULL
;
2641 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2642 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2643 placeholder_halt
= inst
;
2648 if (!placeholder_halt
)
2651 /* Delete any HALTs immediately before the placeholder halt. */
2652 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2653 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2654 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2655 prev
->remove(last_bblock
);
2660 invalidate_live_intervals();
2666 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2667 * from \p r which overlaps the region starting at \p r and spanning \p n GRF
2670 static inline unsigned
2671 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned n
)
2673 const int rel_offset
= (reg_offset(s
) - reg_offset(r
)) / REG_SIZE
;
2674 assert(reg_space(r
) == reg_space(s
) &&
2675 rel_offset
>= 0 && rel_offset
< int(8 * sizeof(unsigned)));
2676 return ((1 << n
) - 1) << rel_offset
;
2680 fs_visitor::compute_to_mrf()
2682 bool progress
= false;
2685 /* No MRFs on Gen >= 7. */
2686 if (devinfo
->gen
>= 7)
2689 calculate_live_intervals();
2691 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2695 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2696 inst
->is_partial_write() ||
2697 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2698 inst
->dst
.type
!= inst
->src
[0].type
||
2699 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2700 !inst
->src
[0].is_contiguous() ||
2701 inst
->src
[0].subreg_offset
)
2704 /* Can't compute-to-MRF this GRF if someone else was going to
2707 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2710 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2711 * things that computed the value of all GRFs of the source region. The
2712 * regs_left bitset keeps track of the registers we haven't yet found a
2713 * generating instruction for.
2715 unsigned regs_left
= (1 << inst
->regs_read(0)) - 1;
2717 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2718 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2719 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2720 /* Found the last thing to write our reg we want to turn
2721 * into a compute-to-MRF.
2724 /* If this one instruction didn't populate all the
2725 * channels, bail. We might be able to rewrite everything
2726 * that writes that reg, but it would require smarter
2729 if (scan_inst
->is_partial_write())
2732 /* Handling things not fully contained in the source of the copy
2733 * would need us to understand coalescing out more than one MOV at
2736 if (scan_inst
->dst
.reg_offset
< inst
->src
[0].reg_offset
||
2737 scan_inst
->dst
.reg_offset
+ scan_inst
->regs_written
>
2738 inst
->src
[0].reg_offset
+ inst
->regs_read(0))
2741 /* SEND instructions can't have MRF as a destination. */
2742 if (scan_inst
->mlen
)
2745 if (devinfo
->gen
== 6) {
2746 /* gen6 math instructions must have the destination be
2747 * GRF, so no compute-to-MRF for them.
2749 if (scan_inst
->is_math()) {
2754 /* Clear the bits for any registers this instruction overwrites. */
2755 regs_left
&= ~mask_relative_to(
2756 inst
->src
[0], scan_inst
->dst
, scan_inst
->regs_written
);
2761 /* We don't handle control flow here. Most computation of
2762 * values that end up in MRFs are shortly before the MRF
2765 if (block
->start() == scan_inst
)
2768 /* You can't read from an MRF, so if someone else reads our
2769 * MRF's source GRF that we wanted to rewrite, that stops us.
2771 bool interfered
= false;
2772 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2773 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->regs_read(i
) * REG_SIZE
,
2774 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2781 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2782 inst
->dst
, inst
->regs_written
* REG_SIZE
)) {
2783 /* If somebody else writes our MRF here, we can't
2784 * compute-to-MRF before that.
2789 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2790 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2791 inst
->dst
, inst
->regs_written
* REG_SIZE
)) {
2792 /* Found a SEND instruction, which means that there are
2793 * live values in MRFs from base_mrf to base_mrf +
2794 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2804 /* Found all generating instructions of our MRF's source value, so it
2805 * should be safe to rewrite them to point to the MRF directly.
2807 regs_left
= (1 << inst
->regs_read(0)) - 1;
2809 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2810 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2811 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2812 /* Clear the bits for any registers this instruction overwrites. */
2813 regs_left
&= ~mask_relative_to(
2814 inst
->src
[0], scan_inst
->dst
, scan_inst
->regs_written
);
2816 const unsigned rel_offset
= (reg_offset(scan_inst
->dst
) -
2817 reg_offset(inst
->src
[0])) / REG_SIZE
;
2819 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2820 /* Apply the same address transformation done by the hardware
2821 * for COMPR4 MRF writes.
2823 assert(rel_offset
< 2);
2824 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
* 4;
2826 /* Clear the COMPR4 bit if the generating instruction is not
2829 if (scan_inst
->regs_written
< 2)
2830 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2833 /* Calculate the MRF number the result of this instruction is
2834 * ultimately written to.
2836 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
;
2839 scan_inst
->dst
.file
= MRF
;
2840 scan_inst
->dst
.reg_offset
= 0;
2841 scan_inst
->saturate
|= inst
->saturate
;
2848 inst
->remove(block
);
2853 invalidate_live_intervals();
2859 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2860 * flow. We could probably do better here with some form of divergence
2864 fs_visitor::eliminate_find_live_channel()
2866 bool progress
= false;
2869 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2870 switch (inst
->opcode
) {
2876 case BRW_OPCODE_ENDIF
:
2877 case BRW_OPCODE_WHILE
:
2881 case FS_OPCODE_DISCARD_JUMP
:
2882 /* This can potentially make control flow non-uniform until the end
2887 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2889 inst
->opcode
= BRW_OPCODE_MOV
;
2890 inst
->src
[0] = brw_imm_ud(0u);
2892 inst
->force_writemask_all
= true;
2906 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2907 * instructions to FS_OPCODE_REP_FB_WRITE.
2910 fs_visitor::emit_repclear_shader()
2912 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2914 int color_mrf
= base_mrf
+ 2;
2918 mov
= bld
.exec_all().group(4, 0)
2919 .MOV(brw_message_reg(color_mrf
),
2920 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2922 struct brw_reg reg
=
2923 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2924 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
2925 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2927 mov
= bld
.exec_all().group(4, 0)
2928 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2932 if (key
->nr_color_regions
== 1) {
2933 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2934 write
->saturate
= key
->clamp_fragment_color
;
2935 write
->base_mrf
= color_mrf
;
2937 write
->header_size
= 0;
2940 assume(key
->nr_color_regions
> 0);
2941 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2942 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2943 write
->saturate
= key
->clamp_fragment_color
;
2944 write
->base_mrf
= base_mrf
;
2946 write
->header_size
= 2;
2954 assign_constant_locations();
2955 assign_curb_setup();
2957 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2959 assert(mov
->src
[0].file
== FIXED_GRF
);
2960 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2965 * Walks through basic blocks, looking for repeated MRF writes and
2966 * removing the later ones.
2969 fs_visitor::remove_duplicate_mrf_writes()
2971 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2972 bool progress
= false;
2974 /* Need to update the MRF tracking for compressed instructions. */
2975 if (dispatch_width
>= 16)
2978 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2980 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2981 if (inst
->is_control_flow()) {
2982 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2985 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2986 inst
->dst
.file
== MRF
) {
2987 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2988 if (prev_inst
&& inst
->equals(prev_inst
)) {
2989 inst
->remove(block
);
2995 /* Clear out the last-write records for MRFs that were overwritten. */
2996 if (inst
->dst
.file
== MRF
) {
2997 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3000 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3001 /* Found a SEND instruction, which will include two or fewer
3002 * implied MRF writes. We could do better here.
3004 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3005 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3009 /* Clear out any MRF move records whose sources got overwritten. */
3010 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3011 if (last_mrf_move
[i
] &&
3012 regions_overlap(inst
->dst
, inst
->regs_written
* REG_SIZE
,
3013 last_mrf_move
[i
]->src
[0],
3014 last_mrf_move
[i
]->regs_read(0) * REG_SIZE
)) {
3015 last_mrf_move
[i
] = NULL
;
3019 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3020 inst
->dst
.file
== MRF
&&
3021 inst
->src
[0].file
!= ARF
&&
3022 !inst
->is_partial_write()) {
3023 last_mrf_move
[inst
->dst
.nr
] = inst
;
3028 invalidate_live_intervals();
3034 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3036 /* Clear the flag for registers that actually got read (as expected). */
3037 for (int i
= 0; i
< inst
->sources
; i
++) {
3039 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3040 grf
= inst
->src
[i
].nr
;
3045 if (grf
>= first_grf
&&
3046 grf
< first_grf
+ grf_len
) {
3047 deps
[grf
- first_grf
] = false;
3048 if (inst
->exec_size
== 16)
3049 deps
[grf
- first_grf
+ 1] = false;
3055 * Implements this workaround for the original 965:
3057 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3058 * check for post destination dependencies on this instruction, software
3059 * must ensure that there is no destination hazard for the case of ‘write
3060 * followed by a posted write’ shown in the following example.
3063 * 2. send r3.xy <rest of send instruction>
3066 * Due to no post-destination dependency check on the ‘send’, the above
3067 * code sequence could have two instructions (1 and 2) in flight at the
3068 * same time that both consider ‘r3’ as the target of their final writes.
3071 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3074 int write_len
= inst
->regs_written
;
3075 int first_write_grf
= inst
->dst
.nr
;
3076 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3077 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3079 memset(needs_dep
, false, sizeof(needs_dep
));
3080 memset(needs_dep
, true, write_len
);
3082 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3084 /* Walk backwards looking for writes to registers we're writing which
3085 * aren't read since being written. If we hit the start of the program,
3086 * we assume that there are no outstanding dependencies on entry to the
3089 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3090 /* If we hit control flow, assume that there *are* outstanding
3091 * dependencies, and force their cleanup before our instruction.
3093 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3094 for (int i
= 0; i
< write_len
; i
++) {
3096 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3097 first_write_grf
+ i
);
3102 /* We insert our reads as late as possible on the assumption that any
3103 * instruction but a MOV that might have left us an outstanding
3104 * dependency has more latency than a MOV.
3106 if (scan_inst
->dst
.file
== VGRF
) {
3107 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
3108 int reg
= scan_inst
->dst
.nr
+ i
;
3110 if (reg
>= first_write_grf
&&
3111 reg
< first_write_grf
+ write_len
&&
3112 needs_dep
[reg
- first_write_grf
]) {
3113 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3114 needs_dep
[reg
- first_write_grf
] = false;
3115 if (scan_inst
->exec_size
== 16)
3116 needs_dep
[reg
- first_write_grf
+ 1] = false;
3121 /* Clear the flag for registers that actually got read (as expected). */
3122 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3124 /* Continue the loop only if we haven't resolved all the dependencies */
3126 for (i
= 0; i
< write_len
; i
++) {
3136 * Implements this workaround for the original 965:
3138 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3139 * used as a destination register until after it has been sourced by an
3140 * instruction with a different destination register.
3143 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3145 int write_len
= inst
->regs_written
;
3146 int first_write_grf
= inst
->dst
.nr
;
3147 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3148 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3150 memset(needs_dep
, false, sizeof(needs_dep
));
3151 memset(needs_dep
, true, write_len
);
3152 /* Walk forwards looking for writes to registers we're writing which aren't
3153 * read before being written.
3155 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3156 /* If we hit control flow, force resolve all remaining dependencies. */
3157 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3158 for (int i
= 0; i
< write_len
; i
++) {
3160 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3161 first_write_grf
+ i
);
3166 /* Clear the flag for registers that actually got read (as expected). */
3167 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3169 /* We insert our reads as late as possible since they're reading the
3170 * result of a SEND, which has massive latency.
3172 if (scan_inst
->dst
.file
== VGRF
&&
3173 scan_inst
->dst
.nr
>= first_write_grf
&&
3174 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3175 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3176 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3178 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3181 /* Continue the loop only if we haven't resolved all the dependencies */
3183 for (i
= 0; i
< write_len
; i
++) {
3193 fs_visitor::insert_gen4_send_dependency_workarounds()
3195 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3198 bool progress
= false;
3200 /* Note that we're done with register allocation, so GRF fs_regs always
3201 * have a .reg_offset of 0.
3204 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3205 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3206 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3207 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3213 invalidate_live_intervals();
3217 * Turns the generic expression-style uniform pull constant load instruction
3218 * into a hardware-specific series of instructions for loading a pull
3221 * The expression style allows the CSE pass before this to optimize out
3222 * repeated loads from the same offset, and gives the pre-register-allocation
3223 * scheduling full flexibility, while the conversion to native instructions
3224 * allows the post-register-allocation scheduler the best information
3227 * Note that execution masking for setting up pull constant loads is special:
3228 * the channels that need to be written are unrelated to the current execution
3229 * mask, since a later instruction will use one of the result channels as a
3230 * source operand for all 8 or 16 of its channels.
3233 fs_visitor::lower_uniform_pull_constant_loads()
3235 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3236 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3239 if (devinfo
->gen
>= 7) {
3240 /* The offset arg is a vec4-aligned immediate byte offset. */
3241 fs_reg const_offset_reg
= inst
->src
[1];
3242 assert(const_offset_reg
.file
== IMM
&&
3243 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3244 assert(const_offset_reg
.ud
% 16 == 0);
3246 fs_reg payload
, offset
;
3247 if (devinfo
->gen
>= 9) {
3248 /* We have to use a message header on Skylake to get SIMD4x2
3249 * mode. Reserve space for the register.
3251 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3252 offset
.reg_offset
++;
3255 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3259 /* This is actually going to be a MOV, but since only the first dword
3260 * is accessed, we have a special opcode to do just that one. Note
3261 * that this needs to be an operation that will be considered a def
3262 * by live variable analysis, or register allocation will explode.
3264 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3265 8, offset
, const_offset_reg
);
3266 setup
->force_writemask_all
= true;
3268 setup
->ir
= inst
->ir
;
3269 setup
->annotation
= inst
->annotation
;
3270 inst
->insert_before(block
, setup
);
3272 /* Similarly, this will only populate the first 4 channels of the
3273 * result register (since we only use smear values from 0-3), but we
3274 * don't tell the optimizer.
3276 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3277 inst
->src
[1] = payload
;
3279 invalidate_live_intervals();
3281 /* Before register allocation, we didn't tell the scheduler about the
3282 * MRF we use. We know it's safe to use this MRF because nothing
3283 * else does except for register spill/unspill, which generates and
3284 * uses its MRF within a single IR instruction.
3286 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3293 fs_visitor::lower_load_payload()
3295 bool progress
= false;
3297 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3298 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3301 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3302 assert(inst
->saturate
== false);
3303 fs_reg dst
= inst
->dst
;
3305 /* Get rid of COMPR4. We'll add it back in if we need it */
3306 if (dst
.file
== MRF
)
3307 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3309 const fs_builder
ibld(this, block
, inst
);
3310 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3312 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3313 if (inst
->src
[i
].file
!= BAD_FILE
) {
3314 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3315 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3316 hbld
.MOV(mov_dst
, mov_src
);
3318 dst
= offset(dst
, hbld
, 1);
3321 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3322 inst
->exec_size
> 8) {
3323 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3324 * a straightforward copy. Instead, the result of the
3325 * LOAD_PAYLOAD is treated as interleaved and the first four
3326 * non-header sources are unpacked as:
3337 * This is used for gen <= 5 fb writes.
3339 assert(inst
->exec_size
== 16);
3340 assert(inst
->header_size
+ 4 <= inst
->sources
);
3341 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3342 if (inst
->src
[i
].file
!= BAD_FILE
) {
3343 if (devinfo
->has_compr4
) {
3344 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3345 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3346 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3348 /* Platform doesn't have COMPR4. We have to fake it */
3349 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3350 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3352 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3359 /* The loop above only ever incremented us through the first set
3360 * of 4 registers. However, thanks to the magic of COMPR4, we
3361 * actually wrote to the first 8 registers, so we need to take
3362 * that into account now.
3366 /* The COMPR4 code took care of the first 4 sources. We'll let
3367 * the regular path handle any remaining sources. Yes, we are
3368 * modifying the instruction but we're about to delete it so
3369 * this really doesn't hurt anything.
3371 inst
->header_size
+= 4;
3374 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3375 if (inst
->src
[i
].file
!= BAD_FILE
)
3376 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3377 dst
= offset(dst
, ibld
, 1);
3380 inst
->remove(block
);
3385 invalidate_live_intervals();
3391 fs_visitor::lower_integer_multiplication()
3393 bool progress
= false;
3395 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3396 const fs_builder
ibld(this, block
, inst
);
3398 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3399 if (inst
->dst
.is_accumulator() ||
3400 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3401 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3404 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3405 * operation directly, but CHV/BXT cannot.
3407 if (devinfo
->gen
>= 8 &&
3408 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3411 if (inst
->src
[1].file
== IMM
&&
3412 inst
->src
[1].ud
< (1 << 16)) {
3413 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3414 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3417 * If multiplying by an immediate value that fits in 16-bits, do a
3418 * single MUL instruction with that value in the proper location.
3420 if (devinfo
->gen
< 7) {
3421 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3423 ibld
.MOV(imm
, inst
->src
[1]);
3424 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3426 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3427 ibld
.MUL(inst
->dst
, inst
->src
[0],
3428 ud
? brw_imm_uw(inst
->src
[1].ud
)
3429 : brw_imm_w(inst
->src
[1].d
));
3432 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3433 * do 32-bit integer multiplication in one instruction, but instead
3434 * must do a sequence (which actually calculates a 64-bit result):
3436 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3437 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3438 * mov(8) g2<1>D acc0<8,8,1>D
3440 * But on Gen > 6, the ability to use second accumulator register
3441 * (acc1) for non-float data types was removed, preventing a simple
3442 * implementation in SIMD16. A 16-channel result can be calculated by
3443 * executing the three instructions twice in SIMD8, once with quarter
3444 * control of 1Q for the first eight channels and again with 2Q for
3445 * the second eight channels.
3447 * Which accumulator register is implicitly accessed (by AccWrEnable
3448 * for instance) is determined by the quarter control. Unfortunately
3449 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3450 * implicit accumulator access by an instruction with 2Q will access
3451 * acc1 regardless of whether the data type is usable in acc1.
3453 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3454 * integer data types.
3456 * Since we only want the low 32-bits of the result, we can do two
3457 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3458 * adjust the high result and add them (like the mach is doing):
3460 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3461 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3462 * shl(8) g9<1>D g8<8,8,1>D 16D
3463 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3465 * We avoid the shl instruction by realizing that we only want to add
3466 * the low 16-bits of the "high" result to the high 16-bits of the
3467 * "low" result and using proper regioning on the add:
3469 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3470 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3471 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3473 * Since it does not use the (single) accumulator register, we can
3474 * schedule multi-component multiplications much better.
3477 fs_reg orig_dst
= inst
->dst
;
3478 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3479 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3482 fs_reg low
= inst
->dst
;
3483 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3486 if (devinfo
->gen
>= 7) {
3487 fs_reg src1_0_w
= inst
->src
[1];
3488 fs_reg src1_1_w
= inst
->src
[1];
3490 if (inst
->src
[1].file
== IMM
) {
3491 src1_0_w
.ud
&= 0xffff;
3494 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3495 if (src1_0_w
.stride
!= 0) {
3496 assert(src1_0_w
.stride
== 1);
3497 src1_0_w
.stride
= 2;
3500 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3501 if (src1_1_w
.stride
!= 0) {
3502 assert(src1_1_w
.stride
== 1);
3503 src1_1_w
.stride
= 2;
3505 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3507 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3508 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3510 fs_reg src0_0_w
= inst
->src
[0];
3511 fs_reg src0_1_w
= inst
->src
[0];
3513 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3514 if (src0_0_w
.stride
!= 0) {
3515 assert(src0_0_w
.stride
== 1);
3516 src0_0_w
.stride
= 2;
3519 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3520 if (src0_1_w
.stride
!= 0) {
3521 assert(src0_1_w
.stride
== 1);
3522 src0_1_w
.stride
= 2;
3524 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3526 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3527 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3530 fs_reg dst
= inst
->dst
;
3531 dst
.type
= BRW_REGISTER_TYPE_UW
;
3532 dst
.subreg_offset
= 2;
3535 high
.type
= BRW_REGISTER_TYPE_UW
;
3538 low
.type
= BRW_REGISTER_TYPE_UW
;
3539 low
.subreg_offset
= 2;
3542 ibld
.ADD(dst
, low
, high
);
3544 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3545 set_condmod(inst
->conditional_mod
,
3546 ibld
.MOV(orig_dst
, inst
->dst
));
3550 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3551 /* Should have been lowered to 8-wide. */
3552 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3553 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3555 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3556 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3558 if (devinfo
->gen
>= 8) {
3559 /* Until Gen8, integer multiplies read 32-bits from one source,
3560 * and 16-bits from the other, and relying on the MACH instruction
3561 * to generate the high bits of the result.
3563 * On Gen8, the multiply instruction does a full 32x32-bit
3564 * multiply, but in order to do a 64-bit multiply we can simulate
3565 * the previous behavior and then use a MACH instruction.
3567 * FINISHME: Don't use source modifiers on src1.
3569 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3570 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3571 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3572 mul
->src
[1].stride
*= 2;
3574 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3576 /* Among other things the quarter control bits influence which
3577 * accumulator register is used by the hardware for instructions
3578 * that access the accumulator implicitly (e.g. MACH). A
3579 * second-half instruction would normally map to acc1, which
3580 * doesn't exist on Gen7 and up (the hardware does emulate it for
3581 * floating-point instructions *only* by taking advantage of the
3582 * extra precision of acc0 not normally used for floating point
3585 * HSW and up are careful enough not to try to access an
3586 * accumulator register that doesn't exist, but on earlier Gen7
3587 * hardware we need to make sure that the quarter control bits are
3588 * zero to avoid non-deterministic behaviour and emit an extra MOV
3589 * to get the result masked correctly according to the current
3593 mach
->force_writemask_all
= true;
3594 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3595 ibld
.MOV(inst
->dst
, mach
->dst
);
3601 inst
->remove(block
);
3606 invalidate_live_intervals();
3612 fs_visitor::lower_minmax()
3614 assert(devinfo
->gen
< 6);
3616 bool progress
= false;
3618 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3619 const fs_builder
ibld(this, block
, inst
);
3621 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3622 inst
->predicate
== BRW_PREDICATE_NONE
) {
3623 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3624 * the original SEL.L/GE instruction
3626 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3627 inst
->conditional_mod
);
3628 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3629 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3636 invalidate_live_intervals();
3642 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3643 fs_reg
*dst
, fs_reg color
, unsigned components
)
3645 if (key
->clamp_fragment_color
) {
3646 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3647 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3649 for (unsigned i
= 0; i
< components
; i
++)
3651 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3656 for (unsigned i
= 0; i
< components
; i
++)
3657 dst
[i
] = offset(color
, bld
, i
);
3661 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3662 const brw_wm_prog_data
*prog_data
,
3663 const brw_wm_prog_key
*key
,
3664 const fs_visitor::thread_payload
&payload
)
3666 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3667 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3668 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3669 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3670 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3671 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3672 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3673 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3674 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3675 const unsigned components
=
3676 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3678 /* We can potentially have a message length of up to 15, so we have to set
3679 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3682 int header_size
= 2, payload_header_size
;
3683 unsigned length
= 0;
3685 /* From the Sandy Bridge PRM, volume 4, page 198:
3687 * "Dispatched Pixel Enables. One bit per pixel indicating
3688 * which pixels were originally enabled when the thread was
3689 * dispatched. This field is only required for the end-of-
3690 * thread message and on all dual-source messages."
3692 if (devinfo
->gen
>= 6 &&
3693 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3694 color1
.file
== BAD_FILE
&&
3695 key
->nr_color_regions
== 1) {
3699 if (header_size
!= 0) {
3700 assert(header_size
== 2);
3701 /* Allocate 2 registers for a header */
3705 if (payload
.aa_dest_stencil_reg
) {
3706 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3707 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3708 .MOV(sources
[length
],
3709 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3713 if (sample_mask
.file
!= BAD_FILE
) {
3714 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3715 BRW_REGISTER_TYPE_UD
);
3717 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3718 * relevant. Since it's unsigned single words one vgrf is always
3719 * 16-wide, but only the lower or higher 8 channels will be used by the
3720 * hardware when doing a SIMD8 write depending on whether we have
3721 * selected the subspans for the first or second half respectively.
3723 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3724 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3725 sample_mask
.stride
*= 2;
3727 bld
.exec_all().annotate("FB write oMask")
3728 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3734 payload_header_size
= length
;
3736 if (src0_alpha
.file
!= BAD_FILE
) {
3737 /* FIXME: This is being passed at the wrong location in the payload and
3738 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3739 * It's supposed to be immediately before oMask but there seems to be no
3740 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3741 * requires header sources to form a contiguous segment at the beginning
3742 * of the message and src0_alpha has per-channel semantics.
3744 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3748 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3751 if (color1
.file
!= BAD_FILE
) {
3752 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3756 if (src_depth
.file
!= BAD_FILE
) {
3757 sources
[length
] = src_depth
;
3761 if (dst_depth
.file
!= BAD_FILE
) {
3762 sources
[length
] = dst_depth
;
3766 if (src_stencil
.file
!= BAD_FILE
) {
3767 assert(devinfo
->gen
>= 9);
3768 assert(bld
.dispatch_width() != 16);
3770 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3771 * available on gen9+. As such it's impossible to have both enabled at the
3772 * same time and therefore length cannot overrun the array.
3774 assert(length
< 15);
3776 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3777 bld
.exec_all().annotate("FB write OS")
3778 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3779 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3784 if (devinfo
->gen
>= 7) {
3785 /* Send from the GRF */
3786 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3787 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3788 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3789 load
->dst
= payload
;
3791 inst
->src
[0] = payload
;
3792 inst
->resize_sources(1);
3794 /* Send from the MRF */
3795 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3796 sources
, length
, payload_header_size
);
3798 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3799 * will do this for us if we just give it a COMPR4 destination.
3801 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3802 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3804 inst
->resize_sources(0);
3808 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3809 inst
->mlen
= load
->regs_written
;
3810 inst
->header_size
= header_size
;
3814 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3815 const fs_reg
&coordinate
,
3816 const fs_reg
&shadow_c
,
3817 const fs_reg
&lod
, const fs_reg
&lod2
,
3818 const fs_reg
&surface
,
3819 const fs_reg
&sampler
,
3820 unsigned coord_components
,
3821 unsigned grad_components
)
3823 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3824 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3825 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3826 fs_reg msg_end
= msg_begin
;
3829 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3831 for (unsigned i
= 0; i
< coord_components
; i
++)
3832 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3833 offset(coordinate
, bld
, i
));
3835 msg_end
= offset(msg_end
, bld
, coord_components
);
3837 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3838 * require all three components to be present and zero if they are unused.
3840 if (coord_components
> 0 &&
3841 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3842 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3843 for (unsigned i
= coord_components
; i
< 3; i
++)
3844 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3846 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3849 if (op
== SHADER_OPCODE_TXD
) {
3850 /* TXD unsupported in SIMD16 mode. */
3851 assert(bld
.dispatch_width() == 8);
3853 /* the slots for u and v are always present, but r is optional */
3854 if (coord_components
< 2)
3855 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3858 * dPdx = dudx, dvdx, drdx
3859 * dPdy = dudy, dvdy, drdy
3861 * 1-arg: Does not exist.
3863 * 2-arg: dudx dvdx dudy dvdy
3864 * dPdx.x dPdx.y dPdy.x dPdy.y
3867 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3868 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3869 * m5 m6 m7 m8 m9 m10
3871 for (unsigned i
= 0; i
< grad_components
; i
++)
3872 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3874 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3876 for (unsigned i
= 0; i
< grad_components
; i
++)
3877 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3879 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3883 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3884 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3886 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3887 bld
.dispatch_width() == 16);
3889 const brw_reg_type type
=
3890 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3891 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3892 bld
.MOV(retype(msg_end
, type
), lod
);
3893 msg_end
= offset(msg_end
, bld
, 1);
3896 if (shadow_c
.file
!= BAD_FILE
) {
3897 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3898 /* There's no plain shadow compare message, so we use shadow
3899 * compare with a bias of 0.0.
3901 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3902 msg_end
= offset(msg_end
, bld
, 1);
3905 bld
.MOV(msg_end
, shadow_c
);
3906 msg_end
= offset(msg_end
, bld
, 1);
3910 inst
->src
[0] = reg_undef
;
3911 inst
->src
[1] = surface
;
3912 inst
->src
[2] = sampler
;
3913 inst
->resize_sources(3);
3914 inst
->base_mrf
= msg_begin
.nr
;
3915 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3916 inst
->header_size
= 1;
3920 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3921 const fs_reg
&coordinate
,
3922 const fs_reg
&shadow_c
,
3923 const fs_reg
&lod
, const fs_reg
&lod2
,
3924 const fs_reg
&sample_index
,
3925 const fs_reg
&surface
,
3926 const fs_reg
&sampler
,
3927 const fs_reg
&offset_value
,
3928 unsigned coord_components
,
3929 unsigned grad_components
)
3931 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3932 fs_reg msg_coords
= message
;
3933 unsigned header_size
= 0;
3935 if (offset_value
.file
!= BAD_FILE
) {
3936 /* The offsets set up by the visitor are in the m1 header, so we can't
3943 for (unsigned i
= 0; i
< coord_components
; i
++)
3944 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
3945 offset(coordinate
, bld
, i
));
3947 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3948 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3950 if (shadow_c
.file
!= BAD_FILE
) {
3951 fs_reg msg_shadow
= msg_lod
;
3952 bld
.MOV(msg_shadow
, shadow_c
);
3953 msg_lod
= offset(msg_shadow
, bld
, 1);
3958 case SHADER_OPCODE_TXL
:
3960 bld
.MOV(msg_lod
, lod
);
3961 msg_end
= offset(msg_lod
, bld
, 1);
3963 case SHADER_OPCODE_TXD
:
3966 * dPdx = dudx, dvdx, drdx
3967 * dPdy = dudy, dvdy, drdy
3969 * Load up these values:
3970 * - dudx dudy dvdx dvdy drdx drdy
3971 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3974 for (unsigned i
= 0; i
< grad_components
; i
++) {
3975 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
3976 msg_end
= offset(msg_end
, bld
, 1);
3978 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
3979 msg_end
= offset(msg_end
, bld
, 1);
3982 case SHADER_OPCODE_TXS
:
3983 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3984 bld
.MOV(msg_lod
, lod
);
3985 msg_end
= offset(msg_lod
, bld
, 1);
3987 case SHADER_OPCODE_TXF
:
3988 msg_lod
= offset(msg_coords
, bld
, 3);
3989 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3990 msg_end
= offset(msg_lod
, bld
, 1);
3992 case SHADER_OPCODE_TXF_CMS
:
3993 msg_lod
= offset(msg_coords
, bld
, 3);
3995 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3997 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3998 msg_end
= offset(msg_lod
, bld
, 2);
4005 inst
->src
[0] = reg_undef
;
4006 inst
->src
[1] = surface
;
4007 inst
->src
[2] = sampler
;
4008 inst
->resize_sources(3);
4009 inst
->base_mrf
= message
.nr
;
4010 inst
->mlen
= msg_end
.nr
- message
.nr
;
4011 inst
->header_size
= header_size
;
4013 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4014 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4018 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
4020 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4023 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4027 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4028 const fs_reg
&coordinate
,
4029 const fs_reg
&shadow_c
,
4030 fs_reg lod
, const fs_reg
&lod2
,
4031 const fs_reg
&sample_index
,
4033 const fs_reg
&surface
,
4034 const fs_reg
&sampler
,
4035 const fs_reg
&offset_value
,
4036 unsigned coord_components
,
4037 unsigned grad_components
)
4039 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4040 int reg_width
= bld
.dispatch_width() / 8;
4041 unsigned header_size
= 0, length
= 0;
4042 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4043 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4044 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4046 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4047 offset_value
.file
!= BAD_FILE
|| inst
->eot
||
4048 op
== SHADER_OPCODE_SAMPLEINFO
||
4049 is_high_sampler(devinfo
, sampler
)) {
4050 /* For general texture offsets (no txf workaround), we need a header to
4051 * put them in. Note that we're only reserving space for it in the
4052 * message payload as it will be initialized implicitly by the
4055 * TG4 needs to place its channel select in the header, for interaction
4056 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4057 * larger sampler numbers we need to offset the Sampler State Pointer in
4061 sources
[0] = fs_reg();
4064 /* If we're requesting fewer than four channels worth of response,
4065 * and we have an explicit header, we need to set up the sampler
4066 * writemask. It's reversed from normal: 1 means "don't write".
4068 if (!inst
->eot
&& inst
->regs_written
!= 4 * reg_width
) {
4069 assert((inst
->regs_written
% reg_width
) == 0);
4070 unsigned mask
= ~((1 << (inst
->regs_written
/ reg_width
)) - 1) & 0xf;
4071 inst
->offset
|= mask
<< 12;
4075 if (shadow_c
.file
!= BAD_FILE
) {
4076 bld
.MOV(sources
[length
], shadow_c
);
4080 bool coordinate_done
= false;
4082 /* The sampler can only meaningfully compute LOD for fragment shader
4083 * messages. For all other stages, we change the opcode to TXL and
4084 * hardcode the LOD to 0.
4086 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
4087 op
== SHADER_OPCODE_TEX
) {
4088 op
= SHADER_OPCODE_TXL
;
4089 lod
= brw_imm_f(0.0f
);
4092 /* Set up the LOD info */
4095 case SHADER_OPCODE_TXL
:
4096 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4097 op
= SHADER_OPCODE_TXL_LZ
;
4100 bld
.MOV(sources
[length
], lod
);
4103 case SHADER_OPCODE_TXD
:
4104 /* TXD should have been lowered in SIMD16 mode. */
4105 assert(bld
.dispatch_width() == 8);
4107 /* Load dPdx and the coordinate together:
4108 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4110 for (unsigned i
= 0; i
< coord_components
; i
++) {
4111 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4113 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4114 * only derivatives for (u, v, r).
4116 if (i
< grad_components
) {
4117 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4118 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4122 coordinate_done
= true;
4124 case SHADER_OPCODE_TXS
:
4125 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4128 case SHADER_OPCODE_TXF
:
4129 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4130 * On Gen9 they are u, v, lod, r
4132 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4134 if (devinfo
->gen
>= 9) {
4135 if (coord_components
>= 2) {
4136 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4137 offset(coordinate
, bld
, 1));
4139 sources
[length
] = brw_imm_d(0);
4144 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4145 op
= SHADER_OPCODE_TXF_LZ
;
4147 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4151 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4152 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4153 offset(coordinate
, bld
, i
));
4155 coordinate_done
= true;
4158 case SHADER_OPCODE_TXF_CMS
:
4159 case SHADER_OPCODE_TXF_CMS_W
:
4160 case SHADER_OPCODE_TXF_UMS
:
4161 case SHADER_OPCODE_TXF_MCS
:
4162 if (op
== SHADER_OPCODE_TXF_UMS
||
4163 op
== SHADER_OPCODE_TXF_CMS
||
4164 op
== SHADER_OPCODE_TXF_CMS_W
) {
4165 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4169 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4170 /* Data from the multisample control surface. */
4171 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4174 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4177 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4178 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4181 offset(mcs
, bld
, 1));
4186 /* There is no offsetting for this message; just copy in the integer
4187 * texture coordinates.
4189 for (unsigned i
= 0; i
< coord_components
; i
++)
4190 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4191 offset(coordinate
, bld
, i
));
4193 coordinate_done
= true;
4195 case SHADER_OPCODE_TG4_OFFSET
:
4196 /* gather4_po_c should have been lowered in SIMD16 mode. */
4197 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
4199 /* More crazy intermixing */
4200 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4201 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4203 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4204 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4205 offset(offset_value
, bld
, i
));
4207 if (coord_components
== 3) /* r if present */
4208 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4210 coordinate_done
= true;
4216 /* Set up the coordinate (except for cases where it was done above) */
4217 if (!coordinate_done
) {
4218 for (unsigned i
= 0; i
< coord_components
; i
++)
4219 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4224 mlen
= length
* reg_width
- header_size
;
4226 mlen
= length
* reg_width
;
4228 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4229 BRW_REGISTER_TYPE_F
);
4230 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4232 /* Generate the SEND. */
4234 inst
->src
[0] = src_payload
;
4235 inst
->src
[1] = surface
;
4236 inst
->src
[2] = sampler
;
4237 inst
->resize_sources(3);
4239 inst
->header_size
= header_size
;
4241 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4242 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4246 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4248 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4249 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4250 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4251 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4252 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4253 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4254 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4255 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4256 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4257 const fs_reg
&offset_value
= inst
->src
[TEX_LOGICAL_SRC_OFFSET_VALUE
];
4258 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4259 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4260 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4261 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4263 if (devinfo
->gen
>= 7) {
4264 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4265 shadow_c
, lod
, lod2
, sample_index
,
4266 mcs
, surface
, sampler
, offset_value
,
4267 coord_components
, grad_components
);
4268 } else if (devinfo
->gen
>= 5) {
4269 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4270 shadow_c
, lod
, lod2
, sample_index
,
4271 surface
, sampler
, offset_value
,
4272 coord_components
, grad_components
);
4274 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4275 shadow_c
, lod
, lod2
,
4277 coord_components
, grad_components
);
4282 * Initialize the header present in some typed and untyped surface
4286 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4288 fs_builder ubld
= bld
.exec_all().group(8, 0);
4289 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4290 ubld
.MOV(dst
, brw_imm_d(0));
4291 ubld
.MOV(component(dst
, 7), sample_mask
);
4296 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4297 const fs_reg
&sample_mask
)
4299 /* Get the logical send arguments. */
4300 const fs_reg
&addr
= inst
->src
[0];
4301 const fs_reg
&src
= inst
->src
[1];
4302 const fs_reg
&surface
= inst
->src
[2];
4303 const UNUSED fs_reg
&dims
= inst
->src
[3];
4304 const fs_reg
&arg
= inst
->src
[4];
4306 /* Calculate the total number of components of the payload. */
4307 const unsigned addr_sz
= inst
->components_read(0);
4308 const unsigned src_sz
= inst
->components_read(1);
4309 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4310 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4312 /* Allocate space for the payload. */
4313 fs_reg
*const components
= new fs_reg
[sz
];
4314 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4317 /* Construct the payload. */
4319 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4321 for (unsigned i
= 0; i
< addr_sz
; i
++)
4322 components
[n
++] = offset(addr
, bld
, i
);
4324 for (unsigned i
= 0; i
< src_sz
; i
++)
4325 components
[n
++] = offset(src
, bld
, i
);
4327 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4329 /* Update the original instruction. */
4331 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4332 inst
->header_size
= header_sz
;
4334 inst
->src
[0] = payload
;
4335 inst
->src
[1] = surface
;
4337 inst
->resize_sources(3);
4339 delete[] components
;
4343 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4345 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4347 if (devinfo
->gen
>= 7) {
4348 /* We are switching the instruction from an ALU-like instruction to a
4349 * send-from-grf instruction. Since sends can't handle strides or
4350 * source modifiers, we have to make a copy of the offset source.
4352 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4353 bld
.MOV(tmp
, inst
->src
[1]);
4356 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4359 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4360 BRW_REGISTER_TYPE_UD
);
4362 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4364 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4365 inst
->resize_sources(1);
4366 inst
->base_mrf
= payload
.nr
;
4367 inst
->header_size
= 1;
4368 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4373 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4375 assert(bld
.shader
->devinfo
->gen
< 6);
4378 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4380 if (inst
->sources
> 1) {
4381 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4382 * "Message Payload":
4384 * "Operand0[7]. For the INT DIV functions, this operand is the
4387 * "Operand1[7]. For the INT DIV functions, this operand is the
4390 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4391 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4392 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4394 inst
->resize_sources(1);
4395 inst
->src
[0] = src0
;
4397 assert(inst
->exec_size
== 8);
4398 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4403 fs_visitor::lower_logical_sends()
4405 bool progress
= false;
4407 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4408 const fs_builder
ibld(this, block
, inst
);
4410 switch (inst
->opcode
) {
4411 case FS_OPCODE_FB_WRITE_LOGICAL
:
4412 assert(stage
== MESA_SHADER_FRAGMENT
);
4413 lower_fb_write_logical_send(ibld
, inst
,
4414 (const brw_wm_prog_data
*)prog_data
,
4415 (const brw_wm_prog_key
*)key
,
4419 case SHADER_OPCODE_TEX_LOGICAL
:
4420 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4423 case SHADER_OPCODE_TXD_LOGICAL
:
4424 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4427 case SHADER_OPCODE_TXF_LOGICAL
:
4428 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4431 case SHADER_OPCODE_TXL_LOGICAL
:
4432 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4435 case SHADER_OPCODE_TXS_LOGICAL
:
4436 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4439 case FS_OPCODE_TXB_LOGICAL
:
4440 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4443 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4444 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4447 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4448 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4451 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4452 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4455 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4456 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4459 case SHADER_OPCODE_LOD_LOGICAL
:
4460 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4463 case SHADER_OPCODE_TG4_LOGICAL
:
4464 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4467 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4468 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4471 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4472 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4475 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4476 lower_surface_logical_send(ibld
, inst
,
4477 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4481 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4482 lower_surface_logical_send(ibld
, inst
,
4483 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4484 ibld
.sample_mask_reg());
4487 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4488 lower_surface_logical_send(ibld
, inst
,
4489 SHADER_OPCODE_UNTYPED_ATOMIC
,
4490 ibld
.sample_mask_reg());
4493 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4494 lower_surface_logical_send(ibld
, inst
,
4495 SHADER_OPCODE_TYPED_SURFACE_READ
,
4499 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4500 lower_surface_logical_send(ibld
, inst
,
4501 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4502 ibld
.sample_mask_reg());
4505 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4506 lower_surface_logical_send(ibld
, inst
,
4507 SHADER_OPCODE_TYPED_ATOMIC
,
4508 ibld
.sample_mask_reg());
4511 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4512 lower_varying_pull_constant_logical_send(ibld
, inst
);
4515 case SHADER_OPCODE_RCP
:
4516 case SHADER_OPCODE_RSQ
:
4517 case SHADER_OPCODE_SQRT
:
4518 case SHADER_OPCODE_EXP2
:
4519 case SHADER_OPCODE_LOG2
:
4520 case SHADER_OPCODE_SIN
:
4521 case SHADER_OPCODE_COS
:
4522 case SHADER_OPCODE_POW
:
4523 case SHADER_OPCODE_INT_QUOTIENT
:
4524 case SHADER_OPCODE_INT_REMAINDER
:
4525 /* The math opcodes are overloaded for the send-like and
4526 * expression-like instructions which seems kind of icky. Gen6+ has
4527 * a native (but rather quirky) MATH instruction so we don't need to
4528 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4529 * logical instructions (which we can easily recognize because they
4530 * have mlen = 0) into send-like virtual instructions.
4532 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4533 lower_math_logical_send(ibld
, inst
);
4548 invalidate_live_intervals();
4554 * Get the closest allowed SIMD width for instruction \p inst accounting for
4555 * some common regioning and execution control restrictions that apply to FPU
4556 * instructions. These restrictions don't necessarily have any relevance to
4557 * instructions not executed by the FPU pipeline like extended math, control
4558 * flow or send message instructions.
4560 * For virtual opcodes it's really up to the instruction -- In some cases
4561 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4562 * instructions) it may simplify virtual instruction lowering if we can
4563 * enforce FPU-like regioning restrictions already on the virtual instruction,
4564 * in other cases (e.g. virtual send-like instructions) this may be
4565 * excessively restrictive.
4568 get_fpu_lowered_simd_width(const struct brw_device_info
*devinfo
,
4569 const fs_inst
*inst
)
4571 /* Maximum execution size representable in the instruction controls. */
4572 unsigned max_width
= MIN2(32, inst
->exec_size
);
4574 /* According to the PRMs:
4575 * "A. In Direct Addressing mode, a source cannot span more than 2
4576 * adjacent GRF registers.
4577 * B. A destination cannot span more than 2 adjacent GRF registers."
4579 * Look for the source or destination with the largest register region
4580 * which is the one that is going to limit the overall execution size of
4581 * the instruction due to this rule.
4583 unsigned reg_count
= inst
->regs_written
;
4585 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4586 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4588 /* Calculate the maximum execution size of the instruction based on the
4589 * factor by which it goes over the hardware limit of 2 GRFs.
4592 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4594 /* According to the IVB PRMs:
4595 * "When destination spans two registers, the source MUST span two
4596 * registers. The exception to the above rule:
4598 * - When source is scalar, the source registers are not incremented.
4599 * - When source is packed integer Word and destination is packed
4600 * integer DWord, the source register is not incremented but the
4601 * source sub register is incremented."
4603 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4604 * restrictions. The code below intentionally doesn't check whether the
4605 * destination type is integer because empirically the hardware doesn't
4606 * seem to care what the actual type is as long as it's dword-aligned.
4608 if (devinfo
->gen
< 8) {
4609 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4610 if (inst
->regs_written
== 2 &&
4611 inst
->regs_read(i
) != 0 && inst
->regs_read(i
) != 2 &&
4612 !is_uniform(inst
->src
[i
]) &&
4613 !(type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4614 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1))
4615 max_width
= MIN2(max_width
, inst
->exec_size
/
4616 inst
->regs_written
);
4620 /* From the IVB PRMs:
4621 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4622 * are applied for both halves of the SIMD32 instruction. If different
4623 * execution mask channels are required, split the instruction into two
4624 * SIMD16 instructions."
4626 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4627 * 32-wide control flow support in hardware and will behave similarly.
4629 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4630 max_width
= MIN2(max_width
, 16);
4632 /* From the IVB PRMs (applies to HSW too):
4633 * "Instructions with condition modifiers must not use SIMD32."
4635 * From the BDW PRMs (applies to later hardware too):
4636 * "Ternary instruction with condition modifiers must not use SIMD32."
4638 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4639 max_width
= MIN2(max_width
, 16);
4641 /* From the IVB PRMs (applies to other devices that don't have the
4642 * brw_device_info::supports_simd16_3src flag set):
4643 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4644 * SIMD8 is not allowed for DF operations."
4646 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4647 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4649 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
4650 * the 8-bit quarter of the execution mask signals specified in the
4651 * instruction control fields) for the second compressed half of any
4652 * single-precision instruction (for double-precision instructions
4653 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
4654 * the EU will apply the wrong execution controls for the second
4655 * sequential GRF write if the number of channels per GRF is not exactly
4656 * eight in single-precision mode (or four in double-float mode).
4658 * In this situation we calculate the maximum size of the split
4659 * instructions so they only ever write to a single register.
4661 if (devinfo
->gen
< 8 && inst
->regs_written
> 1 &&
4662 !inst
->force_writemask_all
) {
4663 const unsigned channels_per_grf
= inst
->exec_size
/ inst
->regs_written
;
4664 unsigned exec_type_size
= 0;
4665 for (int i
= 0; i
< inst
->sources
; i
++) {
4666 if (inst
->src
[i
].file
!= BAD_FILE
)
4667 exec_type_size
= MAX2(exec_type_size
, type_sz(inst
->src
[i
].type
));
4669 assert(exec_type_size
);
4671 /* The hardware shifts exactly 8 channels per compressed half of the
4672 * instruction in single-precision mode and exactly 4 in double-precision.
4674 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
4675 max_width
= MIN2(max_width
, channels_per_grf
);
4678 /* Only power-of-two execution sizes are representable in the instruction
4681 return 1 << _mesa_logbase2(max_width
);
4685 * Get the closest native SIMD width supported by the hardware for instruction
4686 * \p inst. The instruction will be left untouched by
4687 * fs_visitor::lower_simd_width() if the returned value is equal to the
4688 * original execution size.
4691 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4692 const fs_inst
*inst
)
4694 switch (inst
->opcode
) {
4695 case BRW_OPCODE_MOV
:
4696 case BRW_OPCODE_SEL
:
4697 case BRW_OPCODE_NOT
:
4698 case BRW_OPCODE_AND
:
4700 case BRW_OPCODE_XOR
:
4701 case BRW_OPCODE_SHR
:
4702 case BRW_OPCODE_SHL
:
4703 case BRW_OPCODE_ASR
:
4704 case BRW_OPCODE_CMPN
:
4705 case BRW_OPCODE_CSEL
:
4706 case BRW_OPCODE_F32TO16
:
4707 case BRW_OPCODE_F16TO32
:
4708 case BRW_OPCODE_BFREV
:
4709 case BRW_OPCODE_BFE
:
4710 case BRW_OPCODE_ADD
:
4711 case BRW_OPCODE_MUL
:
4712 case BRW_OPCODE_AVG
:
4713 case BRW_OPCODE_FRC
:
4714 case BRW_OPCODE_RNDU
:
4715 case BRW_OPCODE_RNDD
:
4716 case BRW_OPCODE_RNDE
:
4717 case BRW_OPCODE_RNDZ
:
4718 case BRW_OPCODE_LZD
:
4719 case BRW_OPCODE_FBH
:
4720 case BRW_OPCODE_FBL
:
4721 case BRW_OPCODE_CBIT
:
4722 case BRW_OPCODE_SAD2
:
4723 case BRW_OPCODE_MAD
:
4724 case BRW_OPCODE_LRP
:
4725 case FS_OPCODE_PACK
:
4726 return get_fpu_lowered_simd_width(devinfo
, inst
);
4728 case BRW_OPCODE_CMP
: {
4729 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4730 * when the destination is a GRF the dependency-clear bit on the flag
4731 * register is cleared early.
4733 * Suggested workarounds are to disable coissuing CMP instructions
4734 * or to split CMP(16) instructions into two CMP(8) instructions.
4736 * We choose to split into CMP(8) instructions since disabling
4737 * coissuing would affect CMP instructions not otherwise affected by
4740 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4741 !inst
->dst
.is_null() ? 8 : ~0);
4742 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4744 case BRW_OPCODE_BFI1
:
4745 case BRW_OPCODE_BFI2
:
4746 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4748 * "Force BFI instructions to be executed always in SIMD8."
4750 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4751 get_fpu_lowered_simd_width(devinfo
, inst
));
4754 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4755 return inst
->exec_size
;
4757 case SHADER_OPCODE_RCP
:
4758 case SHADER_OPCODE_RSQ
:
4759 case SHADER_OPCODE_SQRT
:
4760 case SHADER_OPCODE_EXP2
:
4761 case SHADER_OPCODE_LOG2
:
4762 case SHADER_OPCODE_SIN
:
4763 case SHADER_OPCODE_COS
:
4764 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4767 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4768 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4769 MIN2(8, inst
->exec_size
));
4771 case SHADER_OPCODE_POW
:
4772 /* SIMD16 is only allowed on Gen7+. */
4773 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4774 MIN2(8, inst
->exec_size
));
4776 case SHADER_OPCODE_INT_QUOTIENT
:
4777 case SHADER_OPCODE_INT_REMAINDER
:
4778 /* Integer division is limited to SIMD8 on all generations. */
4779 return MIN2(8, inst
->exec_size
);
4781 case FS_OPCODE_LINTERP
:
4782 case FS_OPCODE_GET_BUFFER_SIZE
:
4783 case FS_OPCODE_DDX_COARSE
:
4784 case FS_OPCODE_DDX_FINE
:
4785 case FS_OPCODE_DDY_COARSE
:
4786 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4787 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4788 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4789 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4790 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4791 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
4792 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4793 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4794 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4795 return MIN2(16, inst
->exec_size
);
4797 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4798 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4799 * message used to implement varying pull constant loads, so expand it
4800 * to SIMD16. An alternative with longer message payload length but
4801 * shorter return payload would be to use the SIMD8 sampler message that
4802 * takes (header, u, v, r) as parameters instead of (header, u).
4804 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4806 case FS_OPCODE_DDY_FINE
:
4807 /* The implementation of this virtual opcode may require emitting
4808 * compressed Align16 instructions, which are severely limited on some
4811 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4812 * Region Restrictions):
4814 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4815 * and SIMD8 is not allowed for DF operations."
4817 * In this context, "DW operations" means "operations acting on 32-bit
4818 * values", so it includes operations on floats.
4820 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4821 * (Instruction Compression -> Rules and Restrictions):
4823 * "A compressed instruction must be in Align1 access mode. Align16
4824 * mode instructions cannot be compressed."
4826 * Similar text exists in the g45 PRM.
4828 * Empirically, compressed align16 instructions using odd register
4829 * numbers don't appear to work on Sandybridge either.
4831 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4832 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4833 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
4835 case SHADER_OPCODE_MULH
:
4836 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4837 * is 8-wide on Gen7+.
4839 return (devinfo
->gen
>= 7 ? 8 :
4840 get_fpu_lowered_simd_width(devinfo
, inst
));
4842 case FS_OPCODE_FB_WRITE_LOGICAL
:
4843 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4846 assert(devinfo
->gen
!= 6 ||
4847 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4848 inst
->exec_size
== 8);
4849 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4850 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4851 8 : MIN2(16, inst
->exec_size
));
4853 case SHADER_OPCODE_TEX_LOGICAL
:
4854 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4855 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4856 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4857 case SHADER_OPCODE_LOD_LOGICAL
:
4858 case SHADER_OPCODE_TG4_LOGICAL
:
4859 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4860 return MIN2(16, inst
->exec_size
);
4862 case SHADER_OPCODE_TXD_LOGICAL
:
4863 /* TXD is unsupported in SIMD16 mode. */
4866 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4867 /* gather4_po_c is unsupported in SIMD16 mode. */
4868 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4869 return (shadow_c
.file
!= BAD_FILE
? 8 : MIN2(16, inst
->exec_size
));
4871 case SHADER_OPCODE_TXL_LOGICAL
:
4872 case FS_OPCODE_TXB_LOGICAL
: {
4873 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4874 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4875 * mode because the message exceeds the maximum length of 11.
4877 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4878 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4880 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4883 return MIN2(16, inst
->exec_size
);
4885 case SHADER_OPCODE_TXF_LOGICAL
:
4886 case SHADER_OPCODE_TXS_LOGICAL
:
4887 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4888 * messages. Use SIMD16 instead.
4890 if (devinfo
->gen
== 4)
4893 return MIN2(16, inst
->exec_size
);
4895 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4896 /* This opcode can take up to 6 arguments which means that in some
4897 * circumstances it can end up with a message that is too long in SIMD16
4900 const unsigned coord_components
=
4901 inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4902 /* First three arguments are the sample index and the two arguments for
4905 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4908 return MIN2(16, inst
->exec_size
);
4911 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4912 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4913 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4916 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4917 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4918 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4919 return MIN2(16, inst
->exec_size
);
4921 case SHADER_OPCODE_URB_READ_SIMD8
:
4922 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
4923 case SHADER_OPCODE_URB_WRITE_SIMD8
:
4924 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
4925 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
4926 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
4927 return MIN2(8, inst
->exec_size
);
4929 case SHADER_OPCODE_MOV_INDIRECT
:
4930 /* Prior to Broadwell, we only have 8 address subregisters */
4931 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
4932 2 * REG_SIZE
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
4935 case SHADER_OPCODE_LOAD_PAYLOAD
: {
4936 const unsigned reg_count
=
4937 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
4939 if (reg_count
> 2) {
4940 /* Only LOAD_PAYLOAD instructions with per-channel destination region
4941 * can be easily lowered (which excludes headers and heterogeneous
4944 assert(!inst
->header_size
);
4945 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4946 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
4947 inst
->src
[i
].file
== BAD_FILE
);
4949 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4951 return inst
->exec_size
;
4955 return inst
->exec_size
;
4960 * Return true if splitting out the group of channels of instruction \p inst
4961 * given by lbld.group() requires allocating a temporary for the i-th source
4962 * of the lowered instruction.
4965 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
4967 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
4968 (inst
->components_read(i
) == 1 &&
4969 lbld
.dispatch_width() <= inst
->exec_size
));
4973 * Extract the data that would be consumed by the channel group given by
4974 * lbld.group() from the i-th source region of instruction \p inst and return
4975 * it as result in packed form. If any copy instructions are required they
4976 * will be emitted before the given \p inst in \p block.
4979 emit_unzip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
,
4982 /* Specified channel group from the source region. */
4983 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
4985 if (needs_src_copy(lbld
, inst
, i
)) {
4986 /* Builder of the right width to perform the copy avoiding uninitialized
4987 * data if the lowered execution size is greater than the original
4988 * execution size of the instruction.
4990 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
4991 inst
->exec_size
), 0);
4992 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
4994 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
4995 cbld
.at(block
, inst
)
4996 .MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
5000 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
5001 /* The source is invariant for all dispatch_width-wide groups of the
5004 return inst
->src
[i
];
5007 /* We can just point the lowered instruction at the right channel group
5008 * from the original region.
5015 * Return true if splitting out the group of channels of instruction \p inst
5016 * given by lbld.group() requires allocating a temporary for the destination
5017 * of the lowered instruction and copying the data back to the original
5018 * destination region.
5021 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5023 /* If the instruction writes more than one component we'll have to shuffle
5024 * the results of multiple lowered instructions in order to make sure that
5025 * they end up arranged correctly in the original destination region.
5027 if (inst
->regs_written
* REG_SIZE
>
5028 inst
->dst
.component_size(inst
->exec_size
))
5031 /* If the lowered execution size is larger than the original the result of
5032 * the instruction won't fit in the original destination, so we'll have to
5033 * allocate a temporary in any case.
5035 if (lbld
.dispatch_width() > inst
->exec_size
)
5038 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5039 /* If we already made a copy of the source for other reasons there won't
5040 * be any overlap with the destination.
5042 if (needs_src_copy(lbld
, inst
, i
))
5045 /* In order to keep the logic simple we emit a copy whenever the
5046 * destination region doesn't exactly match an overlapping source, which
5047 * may point at the source and destination not being aligned group by
5048 * group which could cause one of the lowered instructions to overwrite
5049 * the data read from the same source by other lowered instructions.
5051 if (regions_overlap(inst
->dst
, inst
->regs_written
* REG_SIZE
,
5052 inst
->src
[i
], inst
->regs_read(i
) * REG_SIZE
) &&
5053 !inst
->dst
.equals(inst
->src
[i
]))
5061 * Insert data from a packed temporary into the channel group given by
5062 * lbld.group() of the destination region of instruction \p inst and return
5063 * the temporary as result. If any copy instructions are required they will
5064 * be emitted around the given \p inst in \p block.
5067 emit_zip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
)
5069 /* Builder of the right width to perform the copy avoiding uninitialized
5070 * data if the lowered execution size is greater than the original
5071 * execution size of the instruction.
5073 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5074 inst
->exec_size
), 0);
5076 /* Specified channel group from the destination region. */
5077 const fs_reg dst
= horiz_offset(inst
->dst
, lbld
.group());
5078 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
5079 inst
->dst
.component_size(inst
->exec_size
);
5081 if (needs_dst_copy(lbld
, inst
)) {
5082 const fs_reg tmp
= lbld
.vgrf(inst
->dst
.type
, dst_size
);
5084 if (inst
->predicate
) {
5085 /* Handle predication by copying the original contents of
5086 * the destination into the temporary before emitting the
5087 * lowered instruction.
5089 for (unsigned k
= 0; k
< dst_size
; ++k
)
5090 cbld
.at(block
, inst
)
5091 .MOV(offset(tmp
, lbld
, k
), offset(dst
, inst
->exec_size
, k
));
5094 for (unsigned k
= 0; k
< dst_size
; ++k
)
5095 cbld
.at(block
, inst
->next
)
5096 .MOV(offset(dst
, inst
->exec_size
, k
), offset(tmp
, lbld
, k
));
5101 /* No need to allocate a temporary for the lowered instruction, just
5102 * take the right group of channels from the original region.
5109 fs_visitor::lower_simd_width()
5111 bool progress
= false;
5113 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5114 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5116 if (lower_width
!= inst
->exec_size
) {
5117 /* Builder matching the original instruction. We may also need to
5118 * emit an instruction of width larger than the original, set the
5119 * execution size of the builder to the highest of both for now so
5120 * we're sure that both cases can be handled.
5122 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5123 const fs_builder ibld
= bld
.at(block
, inst
)
5124 .exec_all(inst
->force_writemask_all
)
5125 .group(max_width
, inst
->group
/ max_width
);
5127 /* Split the copies in chunks of the execution width of either the
5128 * original or the lowered instruction, whichever is lower.
5130 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5131 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
5132 inst
->dst
.component_size(inst
->exec_size
);
5134 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5136 for (unsigned i
= 0; i
< n
; i
++) {
5137 /* Emit a copy of the original instruction with the lowered width.
5138 * If the EOT flag was set throw it away except for the last
5139 * instruction to avoid killing the thread prematurely.
5141 fs_inst split_inst
= *inst
;
5142 split_inst
.exec_size
= lower_width
;
5143 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
5145 /* Select the correct channel enables for the i-th group, then
5146 * transform the sources and destination and emit the lowered
5149 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5151 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5152 split_inst
.src
[j
] = emit_unzip(lbld
, block
, inst
, j
);
5154 split_inst
.dst
= emit_zip(lbld
, block
, inst
);
5155 split_inst
.regs_written
= DIV_ROUND_UP(
5156 split_inst
.dst
.component_size(lower_width
) * dst_size
,
5159 lbld
.emit(split_inst
);
5162 inst
->remove(block
);
5168 invalidate_live_intervals();
5174 fs_visitor::dump_instructions()
5176 dump_instructions(NULL
);
5180 fs_visitor::dump_instructions(const char *name
)
5182 FILE *file
= stderr
;
5183 if (name
&& geteuid() != 0) {
5184 file
= fopen(name
, "w");
5190 calculate_register_pressure();
5191 int ip
= 0, max_pressure
= 0;
5192 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5193 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5194 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5195 dump_instruction(inst
, file
);
5198 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5201 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5202 fprintf(file
, "%4d: ", ip
++);
5203 dump_instruction(inst
, file
);
5207 if (file
!= stderr
) {
5213 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5215 dump_instruction(be_inst
, stderr
);
5219 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5221 fs_inst
*inst
= (fs_inst
*)be_inst
;
5223 if (inst
->predicate
) {
5224 fprintf(file
, "(%cf0.%d) ",
5225 inst
->predicate_inverse
? '-' : '+',
5229 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5231 fprintf(file
, ".sat");
5232 if (inst
->conditional_mod
) {
5233 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5234 if (!inst
->predicate
&&
5235 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5236 inst
->opcode
!= BRW_OPCODE_IF
&&
5237 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5238 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5241 fprintf(file
, "(%d) ", inst
->exec_size
);
5244 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5248 fprintf(file
, "(EOT) ");
5251 switch (inst
->dst
.file
) {
5253 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5254 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
5255 inst
->dst
.subreg_offset
)
5256 fprintf(file
, "+%d.%d",
5257 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
5260 fprintf(file
, "g%d", inst
->dst
.nr
);
5263 fprintf(file
, "m%d", inst
->dst
.nr
);
5266 fprintf(file
, "(null)");
5269 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
5272 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
5275 switch (inst
->dst
.nr
) {
5277 fprintf(file
, "null");
5279 case BRW_ARF_ADDRESS
:
5280 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5282 case BRW_ARF_ACCUMULATOR
:
5283 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5286 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5289 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5292 if (inst
->dst
.subnr
)
5293 fprintf(file
, "+%d", inst
->dst
.subnr
);
5296 unreachable("not reached");
5298 if (inst
->dst
.stride
!= 1)
5299 fprintf(file
, "<%u>", inst
->dst
.stride
);
5300 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
5302 for (int i
= 0; i
< inst
->sources
; i
++) {
5303 if (inst
->src
[i
].negate
)
5305 if (inst
->src
[i
].abs
)
5307 switch (inst
->src
[i
].file
) {
5309 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5310 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
5311 inst
->src
[i
].subreg_offset
)
5312 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
5313 inst
->src
[i
].subreg_offset
);
5316 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5319 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5322 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
5325 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
5326 if (inst
->src
[i
].subreg_offset
) {
5327 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
5328 inst
->src
[i
].subreg_offset
);
5332 fprintf(file
, "(null)");
5335 switch (inst
->src
[i
].type
) {
5336 case BRW_REGISTER_TYPE_F
:
5337 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5339 case BRW_REGISTER_TYPE_DF
:
5340 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5342 case BRW_REGISTER_TYPE_W
:
5343 case BRW_REGISTER_TYPE_D
:
5344 fprintf(file
, "%dd", inst
->src
[i
].d
);
5346 case BRW_REGISTER_TYPE_UW
:
5347 case BRW_REGISTER_TYPE_UD
:
5348 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5350 case BRW_REGISTER_TYPE_VF
:
5351 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5352 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5353 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5354 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5355 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5358 fprintf(file
, "???");
5363 switch (inst
->src
[i
].nr
) {
5365 fprintf(file
, "null");
5367 case BRW_ARF_ADDRESS
:
5368 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5370 case BRW_ARF_ACCUMULATOR
:
5371 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5374 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5377 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5380 if (inst
->src
[i
].subnr
)
5381 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
5384 if (inst
->src
[i
].abs
)
5387 if (inst
->src
[i
].file
!= IMM
) {
5389 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5390 unsigned hstride
= inst
->src
[i
].hstride
;
5391 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5393 stride
= inst
->src
[i
].stride
;
5396 fprintf(file
, "<%u>", stride
);
5398 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
5401 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5402 fprintf(file
, ", ");
5407 if (inst
->force_writemask_all
)
5408 fprintf(file
, "NoMask ");
5410 if (inst
->exec_size
!= dispatch_width
)
5411 fprintf(file
, "group%d ", inst
->group
);
5413 fprintf(file
, "\n");
5417 * Possibly returns an instruction that set up @param reg.
5419 * Sometimes we want to take the result of some expression/variable
5420 * dereference tree and rewrite the instruction generating the result
5421 * of the tree. When processing the tree, we know that the
5422 * instructions generated are all writing temporaries that are dead
5423 * outside of this tree. So, if we have some instructions that write
5424 * a temporary, we're free to point that temp write somewhere else.
5426 * Note that this doesn't guarantee that the instruction generated
5427 * only reg -- it might be the size=4 destination of a texture instruction.
5430 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5435 end
->is_partial_write() ||
5436 !reg
.equals(end
->dst
)) {
5444 fs_visitor::setup_fs_payload_gen6()
5446 assert(stage
== MESA_SHADER_FRAGMENT
);
5447 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5449 unsigned barycentric_interp_modes
=
5450 (stage
== MESA_SHADER_FRAGMENT
) ?
5451 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
5453 assert(devinfo
->gen
>= 6);
5455 /* R0-1: masks, pixel X/Y coordinates. */
5456 payload
.num_regs
= 2;
5457 /* R2: only for 32-pixel dispatch.*/
5459 /* R3-26: barycentric interpolation coordinates. These appear in the
5460 * same order that they appear in the brw_barycentric_mode
5461 * enum. Each set of coordinates occupies 2 registers if dispatch width
5462 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5463 * appear if they were enabled using the "Barycentric Interpolation
5464 * Mode" bits in WM_STATE.
5466 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5467 if (barycentric_interp_modes
& (1 << i
)) {
5468 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5469 payload
.num_regs
+= 2;
5470 if (dispatch_width
== 16) {
5471 payload
.num_regs
+= 2;
5476 /* R27: interpolated depth if uses source depth */
5477 prog_data
->uses_src_depth
=
5478 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5479 if (prog_data
->uses_src_depth
) {
5480 payload
.source_depth_reg
= payload
.num_regs
;
5482 if (dispatch_width
== 16) {
5483 /* R28: interpolated depth if not SIMD8. */
5488 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5489 prog_data
->uses_src_w
=
5490 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5491 if (prog_data
->uses_src_w
) {
5492 payload
.source_w_reg
= payload
.num_regs
;
5494 if (dispatch_width
== 16) {
5495 /* R30: interpolated W if not SIMD8. */
5500 /* R31: MSAA position offsets. */
5501 if (prog_data
->persample_dispatch
&&
5502 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5503 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5505 * "MSDISPMODE_PERSAMPLE is required in order to select
5508 * So we can only really get sample positions if we are doing real
5509 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5510 * persample dispatch, we hard-code it to 0.5.
5512 prog_data
->uses_pos_offset
= true;
5513 payload
.sample_pos_reg
= payload
.num_regs
;
5517 /* R32: MSAA input coverage mask */
5518 prog_data
->uses_sample_mask
=
5519 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5520 if (prog_data
->uses_sample_mask
) {
5521 assert(devinfo
->gen
>= 7);
5522 payload
.sample_mask_in_reg
= payload
.num_regs
;
5524 if (dispatch_width
== 16) {
5525 /* R33: input coverage mask if not SIMD8. */
5530 /* R34-: bary for 32-pixel. */
5531 /* R58-59: interp W for 32-pixel. */
5533 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5534 source_depth_to_render_target
= true;
5539 fs_visitor::setup_vs_payload()
5541 /* R0: thread header, R1: urb handles */
5542 payload
.num_regs
= 2;
5546 fs_visitor::setup_gs_payload()
5548 assert(stage
== MESA_SHADER_GEOMETRY
);
5550 struct brw_gs_prog_data
*gs_prog_data
=
5551 (struct brw_gs_prog_data
*) prog_data
;
5552 struct brw_vue_prog_data
*vue_prog_data
=
5553 (struct brw_vue_prog_data
*) prog_data
;
5555 /* R0: thread header, R1: output URB handles */
5556 payload
.num_regs
= 2;
5558 if (gs_prog_data
->include_primitive_id
) {
5559 /* R2: Primitive ID 0..7 */
5563 /* Use a maximum of 24 registers for push-model inputs. */
5564 const unsigned max_push_components
= 24;
5566 /* If pushing our inputs would take too many registers, reduce the URB read
5567 * length (which is in HWords, or 8 registers), and resort to pulling.
5569 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5570 * have to multiply by VerticesIn to obtain the total storage requirement.
5572 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5573 max_push_components
) {
5574 gs_prog_data
->base
.include_vue_handles
= true;
5576 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5577 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5579 vue_prog_data
->urb_read_length
=
5580 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5585 fs_visitor::setup_cs_payload()
5587 assert(devinfo
->gen
>= 7);
5588 payload
.num_regs
= 1;
5592 fs_visitor::calculate_register_pressure()
5594 invalidate_live_intervals();
5595 calculate_live_intervals();
5597 unsigned num_instructions
= 0;
5598 foreach_block(block
, cfg
)
5599 num_instructions
+= block
->instructions
.length();
5601 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5603 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5604 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5605 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5610 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5612 * The needs_unlit_centroid_workaround ends up producing one of these per
5613 * channel of centroid input, so it's good to clean them up.
5615 * An assumption here is that nothing ever modifies the dispatched pixels
5616 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5617 * dictates that anyway.
5620 fs_visitor::opt_drop_redundant_mov_to_flags()
5622 bool flag_mov_found
[2] = {false};
5623 bool progress
= false;
5625 /* Instructions removed by this pass can only be added if this were true */
5626 if (!devinfo
->needs_unlit_centroid_workaround
)
5629 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5630 if (inst
->is_control_flow()) {
5631 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5632 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5633 if (!flag_mov_found
[inst
->flag_subreg
]) {
5634 flag_mov_found
[inst
->flag_subreg
] = true;
5636 inst
->remove(block
);
5639 } else if (inst
->flags_written()) {
5640 flag_mov_found
[inst
->flag_subreg
] = false;
5648 fs_visitor::optimize()
5650 /* Start by validating the shader we currently have. */
5653 /* bld is the common builder object pointing at the end of the program we
5654 * used to translate it into i965 IR. For the optimization and lowering
5655 * passes coming next, any code added after the end of the program without
5656 * having explicitly called fs_builder::at() clearly points at a mistake.
5657 * Ideally optimization passes wouldn't be part of the visitor so they
5658 * wouldn't have access to bld at all, but they do, so just in case some
5659 * pass forgets to ask for a location explicitly set it to NULL here to
5660 * make it trip. The dispatch width is initialized to a bogus value to
5661 * make sure that optimizations set the execution controls explicitly to
5662 * match the code they are manipulating instead of relying on the defaults.
5664 bld
= fs_builder(this, 64);
5666 assign_constant_locations();
5667 lower_constant_loads();
5671 split_virtual_grfs();
5674 #define OPT(pass, args...) ({ \
5676 bool this_progress = pass(args); \
5678 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5679 char filename[64]; \
5680 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5681 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5683 backend_shader::dump_instructions(filename); \
5688 progress = progress || this_progress; \
5692 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5694 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5695 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5697 backend_shader::dump_instructions(filename
);
5700 bool progress
= false;
5704 OPT(opt_drop_redundant_mov_to_flags
);
5711 OPT(remove_duplicate_mrf_writes
);
5715 OPT(opt_copy_propagate
);
5716 OPT(opt_predicated_break
, this);
5717 OPT(opt_cmod_propagation
);
5718 OPT(dead_code_eliminate
);
5719 OPT(opt_peephole_sel
);
5720 OPT(dead_control_flow_eliminate
, this);
5721 OPT(opt_register_renaming
);
5722 OPT(opt_saturate_propagation
);
5723 OPT(register_coalesce
);
5724 OPT(compute_to_mrf
);
5725 OPT(eliminate_find_live_channel
);
5727 OPT(compact_virtual_grfs
);
5733 if (OPT(lower_pack
)) {
5734 OPT(register_coalesce
);
5735 OPT(dead_code_eliminate
);
5738 if (OPT(lower_d2x
)) {
5739 OPT(opt_copy_propagate
);
5740 OPT(dead_code_eliminate
);
5743 OPT(lower_simd_width
);
5745 /* After SIMD lowering just in case we had to unroll the EOT send. */
5746 OPT(opt_sampler_eot
);
5748 OPT(lower_logical_sends
);
5751 OPT(opt_copy_propagate
);
5752 /* Only run after logical send lowering because it's easier to implement
5753 * in terms of physical sends.
5755 if (OPT(opt_zero_samples
))
5756 OPT(opt_copy_propagate
);
5757 /* Run after logical send lowering to give it a chance to CSE the
5758 * LOAD_PAYLOAD instructions created to construct the payloads of
5759 * e.g. texturing messages in cases where it wasn't possible to CSE the
5760 * whole logical instruction.
5763 OPT(register_coalesce
);
5764 OPT(compute_to_mrf
);
5765 OPT(dead_code_eliminate
);
5766 OPT(remove_duplicate_mrf_writes
);
5767 OPT(opt_peephole_sel
);
5770 OPT(opt_redundant_discard_jumps
);
5772 if (OPT(lower_load_payload
)) {
5773 split_virtual_grfs();
5774 OPT(register_coalesce
);
5775 OPT(compute_to_mrf
);
5776 OPT(dead_code_eliminate
);
5779 OPT(opt_combine_constants
);
5780 OPT(lower_integer_multiplication
);
5782 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5783 OPT(opt_cmod_propagation
);
5785 OPT(opt_copy_propagate
);
5786 OPT(dead_code_eliminate
);
5789 lower_uniform_pull_constant_loads();
5795 * Three source instruction must have a GRF/MRF destination register.
5796 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5799 fs_visitor::fixup_3src_null_dest()
5801 bool progress
= false;
5803 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5804 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5805 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5812 invalidate_live_intervals();
5816 fs_visitor::allocate_registers(bool allow_spilling
)
5818 bool allocated_without_spills
;
5820 static const enum instruction_scheduler_mode pre_modes
[] = {
5822 SCHEDULE_PRE_NON_LIFO
,
5826 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
5828 /* Try each scheduling heuristic to see if it can successfully register
5829 * allocate without spilling. They should be ordered by decreasing
5830 * performance but increasing likelihood of allocating.
5832 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5833 schedule_instructions(pre_modes
[i
]);
5836 assign_regs_trivial();
5837 allocated_without_spills
= true;
5839 allocated_without_spills
= assign_regs(false, spill_all
);
5841 if (allocated_without_spills
)
5845 if (!allocated_without_spills
) {
5846 /* We assume that any spilling is worse than just dropping back to
5847 * SIMD8. There's probably actually some intermediate point where
5848 * SIMD16 with a couple of spills is still better.
5850 if (dispatch_width
> min_dispatch_width
) {
5851 fail("Failure to register allocate. Reduce number of "
5852 "live scalar values to avoid this.");
5854 compiler
->shader_perf_log(log_data
,
5855 "%s shader triggered register spilling. "
5856 "Try reducing the number of live scalar "
5857 "values to improve performance.\n",
5861 /* Since we're out of heuristics, just go spill registers until we
5862 * get an allocation.
5864 while (!assign_regs(true, spill_all
)) {
5870 assert(last_scratch
== 0 || allow_spilling
);
5872 /* This must come after all optimization and register allocation, since
5873 * it inserts dead code that happens to have side effects, and it does
5874 * so based on the actual physical registers in use.
5876 insert_gen4_send_dependency_workarounds();
5881 schedule_instructions(SCHEDULE_POST
);
5883 if (last_scratch
> 0) {
5884 unsigned max_scratch_size
= 2 * 1024 * 1024;
5886 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5888 if (stage
== MESA_SHADER_COMPUTE
) {
5889 if (devinfo
->is_haswell
) {
5890 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5891 * field documentation, Haswell supports a minimum of 2kB of
5892 * scratch space for compute shaders, unlike every other stage
5895 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
5896 } else if (devinfo
->gen
<= 7) {
5897 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5898 * field documentation, platforms prior to Haswell measure scratch
5899 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
5901 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
5902 max_scratch_size
= 12 * 1024;
5906 /* We currently only support up to 2MB of scratch space. If we
5907 * need to support more eventually, the documentation suggests
5908 * that we could allocate a larger buffer, and partition it out
5909 * ourselves. We'd just have to undo the hardware's address
5910 * calculation by subtracting (FFTID * Per Thread Scratch Space)
5911 * and then add FFTID * (Larger Per Thread Scratch Space).
5913 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
5914 * Thread Group Tracking > Local Memory/Scratch Space.
5916 assert(prog_data
->total_scratch
< max_scratch_size
);
5921 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5923 assert(stage
== MESA_SHADER_VERTEX
);
5927 if (shader_time_index
>= 0)
5928 emit_shader_time_begin();
5935 compute_clip_distance(clip_planes
);
5939 if (shader_time_index
>= 0)
5940 emit_shader_time_end();
5946 assign_curb_setup();
5947 assign_vs_urb_setup();
5949 fixup_3src_null_dest();
5950 allocate_registers(true);
5956 fs_visitor::run_tcs_single_patch()
5958 assert(stage
== MESA_SHADER_TESS_CTRL
);
5960 struct brw_tcs_prog_data
*tcs_prog_data
=
5961 (struct brw_tcs_prog_data
*) prog_data
;
5963 /* r1-r4 contain the ICP handles. */
5964 payload
.num_regs
= 5;
5966 if (shader_time_index
>= 0)
5967 emit_shader_time_begin();
5969 /* Initialize gl_InvocationID */
5970 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
5971 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5972 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
5973 bld
.MOV(channels_ud
, channels_uw
);
5975 if (tcs_prog_data
->instances
== 1) {
5976 invocation_id
= channels_ud
;
5978 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5980 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
5981 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5982 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5983 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
5984 brw_imm_ud(INTEL_MASK(23, 17)));
5985 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
5987 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
5990 /* Fix the disptach mask */
5991 if (nir
->info
.tcs
.vertices_out
% 8) {
5992 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
5993 brw_imm_ud(nir
->info
.tcs
.vertices_out
), BRW_CONDITIONAL_L
);
5994 bld
.IF(BRW_PREDICATE_NORMAL
);
5999 if (nir
->info
.tcs
.vertices_out
% 8) {
6000 bld
.emit(BRW_OPCODE_ENDIF
);
6003 /* Emit EOT write; set TR DS Cache bit */
6005 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6006 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6007 fs_reg(brw_imm_ud(0)),
6009 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6010 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6012 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6013 bld
.null_reg_ud(), payload
);
6017 if (shader_time_index
>= 0)
6018 emit_shader_time_end();
6027 assign_curb_setup();
6028 assign_tcs_single_patch_urb_setup();
6030 fixup_3src_null_dest();
6031 allocate_registers(true);
6037 fs_visitor::run_tes()
6039 assert(stage
== MESA_SHADER_TESS_EVAL
);
6041 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6042 payload
.num_regs
= 5;
6044 if (shader_time_index
>= 0)
6045 emit_shader_time_begin();
6054 if (shader_time_index
>= 0)
6055 emit_shader_time_end();
6061 assign_curb_setup();
6062 assign_tes_urb_setup();
6064 fixup_3src_null_dest();
6065 allocate_registers(true);
6071 fs_visitor::run_gs()
6073 assert(stage
== MESA_SHADER_GEOMETRY
);
6077 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6079 if (gs_compile
->control_data_header_size_bits
> 0) {
6080 /* Create a VGRF to store accumulated control data bits. */
6081 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6083 /* If we're outputting more than 32 control data bits, then EmitVertex()
6084 * will set control_data_bits to 0 after emitting the first vertex.
6085 * Otherwise, we need to initialize it to 0 here.
6087 if (gs_compile
->control_data_header_size_bits
<= 32) {
6088 const fs_builder abld
= bld
.annotate("initialize control data bits");
6089 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6093 if (shader_time_index
>= 0)
6094 emit_shader_time_begin();
6098 emit_gs_thread_end();
6100 if (shader_time_index
>= 0)
6101 emit_shader_time_end();
6110 assign_curb_setup();
6111 assign_gs_urb_setup();
6113 fixup_3src_null_dest();
6114 allocate_registers(true);
6120 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6122 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
6123 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6125 assert(stage
== MESA_SHADER_FRAGMENT
);
6127 if (devinfo
->gen
>= 6)
6128 setup_fs_payload_gen6();
6130 setup_fs_payload_gen4();
6134 } else if (do_rep_send
) {
6135 assert(dispatch_width
== 16);
6136 emit_repclear_shader();
6138 if (shader_time_index
>= 0)
6139 emit_shader_time_begin();
6141 calculate_urb_setup();
6142 if (nir
->info
.inputs_read
> 0) {
6143 if (devinfo
->gen
< 6)
6144 emit_interpolation_setup_gen4();
6146 emit_interpolation_setup_gen6();
6149 /* We handle discards by keeping track of the still-live pixels in f0.1.
6150 * Initialize it with the dispatched pixels.
6152 if (wm_prog_data
->uses_kill
) {
6153 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6154 discard_init
->flag_subreg
= 1;
6157 /* Generate FS IR for main(). (the visitor only descends into
6158 * functions called "main").
6165 if (wm_prog_data
->uses_kill
)
6166 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6168 if (wm_key
->alpha_test_func
)
6173 if (shader_time_index
>= 0)
6174 emit_shader_time_end();
6180 assign_curb_setup();
6183 fixup_3src_null_dest();
6184 allocate_registers(allow_spilling
);
6194 fs_visitor::run_cs()
6196 assert(stage
== MESA_SHADER_COMPUTE
);
6200 if (shader_time_index
>= 0)
6201 emit_shader_time_begin();
6203 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6204 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6205 const fs_builder abld
= bld
.exec_all().group(1, 0);
6206 abld
.MOV(retype(suboffset(brw_sr0_reg(), 1), BRW_REGISTER_TYPE_UW
),
6207 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6215 emit_cs_terminate();
6217 if (shader_time_index
>= 0)
6218 emit_shader_time_end();
6224 assign_curb_setup();
6226 fixup_3src_null_dest();
6227 allocate_registers(true);
6236 * Return a bitfield where bit n is set if barycentric interpolation mode n
6237 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6239 * We examine the load_barycentric intrinsics rather than looking at input
6240 * variables so that we catch interpolateAtCentroid() messages too, which
6241 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6244 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
6245 const nir_shader
*shader
)
6247 unsigned barycentric_interp_modes
= 0;
6249 nir_foreach_function(f
, shader
) {
6253 nir_foreach_block(block
, f
->impl
) {
6254 nir_foreach_instr(instr
, block
) {
6255 if (instr
->type
!= nir_instr_type_intrinsic
)
6258 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6259 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6262 /* Ignore WPOS; it doesn't require interpolation. */
6263 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6266 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6267 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
6268 nir_intrinsic_interp_mode(intrin
);
6269 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
6270 enum brw_barycentric_mode bary
=
6271 brw_barycentric_mode(interp
, bary_op
);
6273 barycentric_interp_modes
|= 1 << bary
;
6275 if (devinfo
->needs_unlit_centroid_workaround
&&
6276 bary_op
== nir_intrinsic_load_barycentric_centroid
)
6277 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
6282 return barycentric_interp_modes
;
6286 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6287 const nir_shader
*shader
)
6289 prog_data
->flat_inputs
= 0;
6291 nir_foreach_variable(var
, &shader
->inputs
) {
6292 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6294 if (input_index
< 0)
6298 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6299 prog_data
->flat_inputs
|= (1 << input_index
);
6304 computed_depth_mode(const nir_shader
*shader
)
6306 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6307 switch (shader
->info
.fs
.depth_layout
) {
6308 case FRAG_DEPTH_LAYOUT_NONE
:
6309 case FRAG_DEPTH_LAYOUT_ANY
:
6310 return BRW_PSCDEPTH_ON
;
6311 case FRAG_DEPTH_LAYOUT_GREATER
:
6312 return BRW_PSCDEPTH_ON_GE
;
6313 case FRAG_DEPTH_LAYOUT_LESS
:
6314 return BRW_PSCDEPTH_ON_LE
;
6315 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6316 return BRW_PSCDEPTH_OFF
;
6319 return BRW_PSCDEPTH_OFF
;
6323 * Move load_interpolated_input with simple (payload-based) barycentric modes
6324 * to the top of the program so we don't emit multiple PLNs for the same input.
6326 * This works around CSE not being able to handle non-dominating cases
6332 * interpolate the same exact input
6335 * This should be replaced by global value numbering someday.
6338 move_interpolation_to_top(nir_shader
*nir
)
6340 nir_foreach_function(f
, nir
) {
6344 nir_block
*top
= nir_start_block(f
->impl
);
6346 nir_foreach_block(block
, f
->impl
) {
6350 nir_foreach_instr_reverse_safe(instr
, block
) {
6351 if (instr
->type
!= nir_instr_type_intrinsic
)
6354 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6355 switch (intrin
->intrinsic
) {
6356 case nir_intrinsic_load_barycentric_pixel
:
6357 case nir_intrinsic_load_barycentric_centroid
:
6358 case nir_intrinsic_load_barycentric_sample
:
6360 case nir_intrinsic_load_interpolated_input
: {
6361 nir_intrinsic_instr
*bary_intrinsic
=
6362 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6363 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
6365 /* Leave interpolateAtSample/Offset() where it is. */
6366 if (op
== nir_intrinsic_load_barycentric_at_sample
||
6367 op
== nir_intrinsic_load_barycentric_at_offset
)
6374 exec_node_remove(&instr
->node
);
6375 exec_list_push_head(&top
->instr_list
, &instr
->node
);
6379 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6380 ((unsigned) nir_metadata_block_index
|
6381 (unsigned) nir_metadata_dominance
));
6386 * Apply default interpolation settings to FS inputs which don't specify any.
6389 brw_nir_set_default_interpolation(const struct brw_device_info
*devinfo
,
6390 struct nir_shader
*nir
,
6391 bool api_flat_shade
,
6392 bool per_sample_interpolation
)
6394 assert(nir
->stage
== MESA_SHADER_FRAGMENT
);
6396 nir_foreach_variable(var
, &nir
->inputs
) {
6397 /* Apply default interpolation mode.
6399 * Everything defaults to smooth except for the legacy GL color
6400 * built-in variables, which might be flat depending on API state.
6402 if (var
->data
.interpolation
== INTERP_MODE_NONE
) {
6403 const bool flat
= api_flat_shade
&&
6404 (var
->data
.location
== VARYING_SLOT_COL0
||
6405 var
->data
.location
== VARYING_SLOT_COL1
);
6407 var
->data
.interpolation
= flat
? INTERP_MODE_FLAT
6408 : INTERP_MODE_SMOOTH
;
6411 /* Apply 'sample' if necessary for API state. */
6412 if (per_sample_interpolation
&&
6413 var
->data
.interpolation
!= INTERP_MODE_FLAT
) {
6414 var
->data
.centroid
= false;
6415 var
->data
.sample
= true;
6418 /* On Ironlake and below, there is only one interpolation mode.
6419 * Centroid interpolation doesn't mean anything on this hardware --
6420 * there is no multisampling.
6422 if (devinfo
->gen
< 6) {
6423 var
->data
.centroid
= false;
6424 var
->data
.sample
= false;
6430 * Demote per-sample barycentric intrinsics to centroid.
6432 * Useful when rendering to a non-multisampled buffer.
6435 demote_sample_qualifiers(nir_shader
*nir
)
6437 nir_foreach_function(f
, nir
) {
6442 nir_builder_init(&b
, f
->impl
);
6444 nir_foreach_block(block
, f
->impl
) {
6445 nir_foreach_instr_safe(instr
, block
) {
6446 if (instr
->type
!= nir_instr_type_intrinsic
)
6449 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6450 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
6451 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
6454 b
.cursor
= nir_before_instr(instr
);
6455 nir_ssa_def
*centroid
=
6456 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
6457 nir_intrinsic_interp_mode(intrin
));
6458 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
6459 nir_src_for_ssa(centroid
));
6460 nir_instr_remove(instr
);
6464 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6465 ((unsigned) nir_metadata_block_index
|
6466 (unsigned) nir_metadata_dominance
));
6471 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6473 const struct brw_wm_prog_key
*key
,
6474 struct brw_wm_prog_data
*prog_data
,
6475 const nir_shader
*src_shader
,
6476 struct gl_program
*prog
,
6477 int shader_time_index8
, int shader_time_index16
,
6478 bool allow_spilling
,
6480 unsigned *final_assembly_size
,
6483 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6484 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6486 brw_nir_set_default_interpolation(compiler
->devinfo
, shader
,
6487 key
->flat_shade
, key
->persample_interp
);
6488 brw_nir_lower_fs_inputs(shader
);
6489 brw_nir_lower_fs_outputs(shader
);
6490 if (!key
->multisample_fbo
)
6491 NIR_PASS_V(shader
, demote_sample_qualifiers
);
6492 NIR_PASS_V(shader
, move_interpolation_to_top
);
6493 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6495 /* key->alpha_test_func means simulating alpha testing via discards,
6496 * so the shader definitely kills pixels.
6498 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
6499 prog_data
->uses_omask
= key
->multisample_fbo
&&
6500 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6501 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6502 prog_data
->computed_stencil
=
6503 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6505 prog_data
->persample_dispatch
=
6506 key
->multisample_fbo
&&
6507 (key
->persample_interp
||
6508 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6509 SYSTEM_BIT_SAMPLE_POS
)) ||
6510 shader
->info
.fs
.uses_sample_qualifier
);
6512 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
6514 prog_data
->barycentric_interp_modes
=
6515 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
6517 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6518 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6519 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6521 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6522 &prog_data
->base
, prog
, shader
, 8,
6523 shader_time_index8
);
6524 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6526 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6529 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6531 simd8_grf_start
= v8
.payload
.num_regs
;
6532 simd8_grf_used
= v8
.grf_used
;
6535 if (v8
.max_dispatch_width
>= 16 &&
6536 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6537 /* Try a SIMD16 compile */
6538 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6539 &prog_data
->base
, prog
, shader
, 16,
6540 shader_time_index16
);
6541 v16
.import_uniforms(&v8
);
6542 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6543 compiler
->shader_perf_log(log_data
,
6544 "SIMD16 shader failed to compile: %s",
6547 simd16_cfg
= v16
.cfg
;
6548 simd16_grf_start
= v16
.payload
.num_regs
;
6549 simd16_grf_used
= v16
.grf_used
;
6553 /* When the caller requests a repclear shader, they want SIMD16-only */
6557 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6558 * at the top to select the shader. We've never implemented that.
6559 * Instead, we just give them exactly one shader and we pick the widest one
6562 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6565 if (prog_data
->persample_dispatch
) {
6566 /* Starting with SandyBridge (where we first get MSAA), the different
6567 * pixel dispatch combinations are grouped into classifications A
6568 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6569 * generations, the only configurations supporting persample dispatch
6570 * are are this in which only one dispatch width is enabled.
6572 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6573 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6575 if (compiler
->devinfo
->gen
== 6 &&
6576 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6578 } else if (simd16_cfg
) {
6583 /* We have to compute the flat inputs after the visitor is finished running
6584 * because it relies on prog_data->urb_setup which is computed in
6585 * fs_visitor::calculate_urb_setup().
6587 brw_compute_flat_inputs(prog_data
, shader
);
6589 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6590 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6591 MESA_SHADER_FRAGMENT
);
6593 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6594 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6595 shader
->info
.label
? shader
->info
.label
:
6597 shader
->info
.name
));
6601 prog_data
->dispatch_8
= true;
6602 g
.generate_code(simd8_cfg
, 8);
6603 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6604 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6607 prog_data
->dispatch_16
= true;
6608 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6609 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6610 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6612 } else if (simd16_cfg
) {
6613 prog_data
->dispatch_16
= true;
6614 g
.generate_code(simd16_cfg
, 16);
6615 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6616 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6619 return g
.get_assembly(final_assembly_size
);
6623 fs_visitor::emit_cs_work_group_id_setup()
6625 assert(stage
== MESA_SHADER_COMPUTE
);
6627 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6629 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6630 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6631 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6633 bld
.MOV(*reg
, r0_1
);
6634 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6635 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6641 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
6643 block
->dwords
= dwords
;
6644 block
->regs
= DIV_ROUND_UP(dwords
, 8);
6645 block
->size
= block
->regs
* 32;
6649 cs_fill_push_const_info(const struct brw_device_info
*devinfo
,
6650 struct brw_cs_prog_data
*cs_prog_data
)
6652 const struct brw_stage_prog_data
*prog_data
=
6653 (struct brw_stage_prog_data
*) cs_prog_data
;
6654 bool fill_thread_id
=
6655 cs_prog_data
->thread_local_id_index
>= 0 &&
6656 cs_prog_data
->thread_local_id_index
< (int)prog_data
->nr_params
;
6657 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
6659 /* The thread ID should be stored in the last param dword */
6660 assert(prog_data
->nr_params
> 0 || !fill_thread_id
);
6661 assert(!fill_thread_id
||
6662 cs_prog_data
->thread_local_id_index
==
6663 (int)prog_data
->nr_params
- 1);
6665 unsigned cross_thread_dwords
, per_thread_dwords
;
6666 if (!cross_thread_supported
) {
6667 cross_thread_dwords
= 0u;
6668 per_thread_dwords
= prog_data
->nr_params
;
6669 } else if (fill_thread_id
) {
6670 /* Fill all but the last register with cross-thread payload */
6671 cross_thread_dwords
= 8 * (cs_prog_data
->thread_local_id_index
/ 8);
6672 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
6673 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
6675 /* Fill all data using cross-thread payload */
6676 cross_thread_dwords
= prog_data
->nr_params
;
6677 per_thread_dwords
= 0u;
6680 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
6681 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
6683 unsigned total_dwords
=
6684 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
6685 cs_prog_data
->push
.cross_thread
.size
) / 4;
6686 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
6688 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
6689 cs_prog_data
->push
.per_thread
.size
== 0);
6690 assert(cs_prog_data
->push
.cross_thread
.dwords
+
6691 cs_prog_data
->push
.per_thread
.dwords
==
6692 prog_data
->nr_params
);
6696 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
6698 cs_prog_data
->simd_size
= size
;
6699 unsigned group_size
= cs_prog_data
->local_size
[0] *
6700 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
6701 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
6705 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6707 const struct brw_cs_prog_key
*key
,
6708 struct brw_cs_prog_data
*prog_data
,
6709 const nir_shader
*src_shader
,
6710 int shader_time_index
,
6711 unsigned *final_assembly_size
,
6714 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6715 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6717 brw_nir_lower_cs_shared(shader
);
6718 prog_data
->base
.total_shared
+= shader
->num_shared
;
6720 /* Now that we cloned the nir_shader, we can update num_uniforms based on
6721 * the thread_local_id_index.
6723 assert(prog_data
->thread_local_id_index
>= 0);
6724 shader
->num_uniforms
=
6725 MAX2(shader
->num_uniforms
,
6726 (unsigned)4 * (prog_data
->thread_local_id_index
+ 1));
6728 brw_nir_lower_intrinsics(shader
, &prog_data
->base
);
6729 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6731 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
6732 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
6733 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
6734 unsigned local_workgroup_size
=
6735 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
6736 shader
->info
.cs
.local_size
[2];
6738 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
6739 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
6742 const char *fail_msg
= NULL
;
6744 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6746 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6747 NULL
, /* Never used in core profile */
6748 shader
, 8, shader_time_index
);
6749 if (simd_required
<= 8) {
6751 fail_msg
= v8
.fail_msg
;
6754 cs_set_simd_size(prog_data
, 8);
6755 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6756 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
6760 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6761 NULL
, /* Never used in core profile */
6762 shader
, 16, shader_time_index
);
6763 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6764 !fail_msg
&& v8
.max_dispatch_width
>= 16 &&
6765 simd_required
<= 16) {
6766 /* Try a SIMD16 compile */
6767 if (simd_required
<= 8)
6768 v16
.import_uniforms(&v8
);
6769 if (!v16
.run_cs()) {
6770 compiler
->shader_perf_log(log_data
,
6771 "SIMD16 shader failed to compile: %s",
6775 "Couldn't generate SIMD16 program and not "
6776 "enough threads for SIMD8";
6780 cs_set_simd_size(prog_data
, 16);
6781 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6782 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
6786 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6787 NULL
, /* Never used in core profile */
6788 shader
, 32, shader_time_index
);
6789 if (!fail_msg
&& v8
.max_dispatch_width
>= 32 &&
6790 (simd_required
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
6791 /* Try a SIMD32 compile */
6792 if (simd_required
<= 8)
6793 v32
.import_uniforms(&v8
);
6794 else if (simd_required
<= 16)
6795 v32
.import_uniforms(&v16
);
6797 if (!v32
.run_cs()) {
6798 compiler
->shader_perf_log(log_data
,
6799 "SIMD32 shader failed to compile: %s",
6803 "Couldn't generate SIMD32 program and not "
6804 "enough threads for SIMD16";
6808 cs_set_simd_size(prog_data
, 32);
6809 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6813 if (unlikely(cfg
== NULL
)) {
6816 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6821 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6822 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6823 MESA_SHADER_COMPUTE
);
6824 if (INTEL_DEBUG
& DEBUG_CS
) {
6825 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6826 shader
->info
.label
? shader
->info
.label
:
6829 g
.enable_debug(name
);
6832 g
.generate_code(cfg
, prog_data
->simd_size
);
6834 return g
.get_assembly(final_assembly_size
);