2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
31 /* Evil hack for using libdrm in a c++ compiler. */
34 #include "intel_bufmgr.h"
37 #include "main/macros.h"
38 #include "main/shaderobj.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/prog_optimize.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
48 #include "../glsl/glsl_types.h"
49 #include "../glsl/ir_optimization.h"
50 #include "../glsl/ir_print_visitor.h"
53 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
54 GRF
= BRW_GENERAL_REGISTER_FILE
,
55 MRF
= BRW_MESSAGE_REGISTER_FILE
,
56 IMM
= BRW_IMMEDIATE_VALUE
,
57 FIXED_HW_REG
, /* a struct brw_reg */
58 UNIFORM
, /* prog_data->params[hw_reg] */
63 FS_OPCODE_FB_WRITE
= 256,
77 static int using_new_fs
= -1;
80 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
82 struct brw_shader
*shader
;
84 shader
= talloc_zero(NULL
, struct brw_shader
);
86 shader
->base
.Type
= type
;
87 shader
->base
.Name
= name
;
88 _mesa_init_shader(ctx
, &shader
->base
);
94 struct gl_shader_program
*
95 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
97 struct brw_shader_program
*prog
;
98 prog
= talloc_zero(NULL
, struct brw_shader_program
);
100 prog
->base
.Name
= name
;
101 _mesa_init_shader_program(ctx
, &prog
->base
);
107 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
109 if (!_mesa_ir_compile_shader(ctx
, shader
))
116 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
118 if (using_new_fs
== -1)
119 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
121 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
122 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
124 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
125 void *mem_ctx
= talloc_new(NULL
);
129 talloc_free(shader
->ir
);
130 shader
->ir
= new(shader
) exec_list
;
131 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
133 do_mat_op_to_vec(shader
->ir
);
134 do_div_to_mul_rcp(shader
->ir
);
135 do_sub_to_add_neg(shader
->ir
);
136 do_explog_to_explog2(shader
->ir
);
138 brw_do_channel_expressions(shader
->ir
);
139 brw_do_vector_splitting(shader
->ir
);
144 progress
= do_common_optimization(shader
->ir
, true) || progress
;
147 validate_ir_tree(shader
->ir
);
149 reparent_ir(shader
->ir
, shader
->ir
);
150 talloc_free(mem_ctx
);
154 if (!_mesa_ir_link_shader(ctx
, prog
))
161 type_size(const struct glsl_type
*type
)
163 unsigned int size
, i
;
165 switch (type
->base_type
) {
168 case GLSL_TYPE_FLOAT
:
170 return type
->components();
171 case GLSL_TYPE_ARRAY
:
172 /* FINISHME: uniform/varying arrays. */
173 return type_size(type
->fields
.array
) * type
->length
;
174 case GLSL_TYPE_STRUCT
:
176 for (i
= 0; i
< type
->length
; i
++) {
177 size
+= type_size(type
->fields
.structure
[i
].type
);
180 case GLSL_TYPE_SAMPLER
:
181 /* Samplers take up no register space, since they're baked in at
186 assert(!"not reached");
193 /* Callers of this talloc-based new need not call delete. It's
194 * easier to just talloc_free 'ctx' (or any of its ancestors). */
195 static void* operator new(size_t size
, void *ctx
)
199 node
= talloc_size(ctx
, size
);
200 assert(node
!= NULL
);
205 /** Generic unset register constructor. */
208 this->file
= BAD_FILE
;
210 this->reg_offset
= 0;
216 /** Immediate value constructor. */
222 this->type
= BRW_REGISTER_TYPE_F
;
228 /** Immediate value constructor. */
234 this->type
= BRW_REGISTER_TYPE_D
;
240 /** Immediate value constructor. */
246 this->type
= BRW_REGISTER_TYPE_UD
;
252 /** Fixed brw_reg Immediate value constructor. */
253 fs_reg(struct brw_reg fixed_hw_reg
)
255 this->file
= FIXED_HW_REG
;
256 this->fixed_hw_reg
= fixed_hw_reg
;
259 this->type
= fixed_hw_reg
.type
;
264 fs_reg(enum register_file file
, int hw_reg
);
265 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
267 /** Register file: ARF, GRF, MRF, IMM. */
268 enum register_file file
;
269 /** Abstract register number. 0 = fixed hw reg */
271 /** Offset within the abstract register. */
273 /** HW register number. Generally unset until register allocation. */
275 /** Register type. BRW_REGISTER_TYPE_* */
279 struct brw_reg fixed_hw_reg
;
281 /** Value for file == BRW_IMMMEDIATE_FILE */
289 static const fs_reg reg_undef
;
290 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
292 class fs_inst
: public exec_node
{
294 /* Callers of this talloc-based new need not call delete. It's
295 * easier to just talloc_free 'ctx' (or any of its ancestors). */
296 static void* operator new(size_t size
, void *ctx
)
300 node
= talloc_zero_size(ctx
, size
);
301 assert(node
!= NULL
);
308 this->opcode
= BRW_OPCODE_NOP
;
309 this->saturate
= false;
310 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
311 this->predicated
= false;
316 this->opcode
= opcode
;
317 this->saturate
= false;
318 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
319 this->predicated
= false;
322 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
)
324 this->opcode
= opcode
;
327 this->saturate
= false;
328 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
329 this->predicated
= false;
332 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
334 this->opcode
= opcode
;
338 this->saturate
= false;
339 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
340 this->predicated
= false;
343 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg src2
)
345 this->opcode
= opcode
;
350 this->saturate
= false;
351 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
352 this->predicated
= false;
355 int opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
360 int conditional_mod
; /**< BRW_CONDITIONAL_* */
363 * Annotation for the generated IR. One of the two can be set.
366 const char *annotation
;
370 class fs_visitor
: public ir_visitor
374 fs_visitor(struct brw_wm_compile
*c
, struct brw_shader
*shader
)
379 this->intel
= &brw
->intel
;
380 this->ctx
= &intel
->ctx
;
381 this->mem_ctx
= talloc_new(NULL
);
382 this->shader
= shader
;
384 this->next_abstract_grf
= 1;
385 this->variable_ht
= hash_table_ctor(0,
386 hash_table_pointer_hash
,
387 hash_table_pointer_compare
);
389 this->frag_color
= NULL
;
390 this->frag_data
= NULL
;
391 this->frag_depth
= NULL
;
392 this->first_non_payload_grf
= 0;
394 this->current_annotation
= NULL
;
395 this->annotation_string
= NULL
;
396 this->annotation_ir
= NULL
;
400 talloc_free(this->mem_ctx
);
401 hash_table_dtor(this->variable_ht
);
404 fs_reg
*variable_storage(ir_variable
*var
);
406 void visit(ir_variable
*ir
);
407 void visit(ir_assignment
*ir
);
408 void visit(ir_dereference_variable
*ir
);
409 void visit(ir_dereference_record
*ir
);
410 void visit(ir_dereference_array
*ir
);
411 void visit(ir_expression
*ir
);
412 void visit(ir_texture
*ir
);
413 void visit(ir_if
*ir
);
414 void visit(ir_constant
*ir
);
415 void visit(ir_swizzle
*ir
);
416 void visit(ir_return
*ir
);
417 void visit(ir_loop
*ir
);
418 void visit(ir_loop_jump
*ir
);
419 void visit(ir_discard
*ir
);
420 void visit(ir_call
*ir
);
421 void visit(ir_function
*ir
);
422 void visit(ir_function_signature
*ir
);
424 fs_inst
*emit(fs_inst inst
);
425 void assign_curb_setup();
426 void assign_urb_setup();
428 void generate_code();
429 void generate_fb_write(fs_inst
*inst
);
430 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
431 struct brw_reg
*src
);
432 void generate_math(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg
*src
);
434 void emit_dummy_fs();
435 void emit_interpolation();
436 void emit_pinterp(int location
);
437 void emit_fb_writes();
439 struct brw_reg
interp_reg(int location
, int channel
);
441 struct brw_context
*brw
;
442 struct intel_context
*intel
;
444 struct brw_wm_compile
*c
;
445 struct brw_compile
*p
;
446 struct brw_shader
*shader
;
448 exec_list instructions
;
449 int next_abstract_grf
;
450 struct hash_table
*variable_ht
;
451 ir_variable
*frag_color
, *frag_data
, *frag_depth
;
452 int first_non_payload_grf
;
454 /** @{ debug annotation info */
455 const char *current_annotation
;
456 ir_instruction
*base_ir
;
457 const char **annotation_string
;
458 ir_instruction
**annotation_ir
;
463 /* Result of last visit() method. */
471 fs_reg interp_attrs
[64];
477 /** Fixed HW reg constructor. */
478 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
482 this->reg_offset
= 0;
483 this->hw_reg
= hw_reg
;
484 this->type
= BRW_REGISTER_TYPE_F
;
489 /** Automatic reg constructor. */
490 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
493 this->reg
= v
->next_abstract_grf
;
494 this->reg_offset
= 0;
495 v
->next_abstract_grf
+= type_size(type
);
500 switch (type
->base_type
) {
501 case GLSL_TYPE_FLOAT
:
502 this->type
= BRW_REGISTER_TYPE_F
;
506 this->type
= BRW_REGISTER_TYPE_D
;
509 this->type
= BRW_REGISTER_TYPE_UD
;
512 assert(!"not reached");
513 this->type
= BRW_REGISTER_TYPE_F
;
519 fs_visitor::variable_storage(ir_variable
*var
)
521 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
525 fs_visitor::visit(ir_variable
*ir
)
529 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
530 this->frag_color
= ir
;
531 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
532 this->frag_data
= ir
;
533 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
534 this->frag_depth
= ir
;
535 assert(!"FINISHME: this hangs currently.");
538 if (ir
->mode
== ir_var_in
) {
539 reg
= &this->interp_attrs
[ir
->location
];
542 if (ir
->mode
== ir_var_uniform
) {
543 const float *vec_values
;
544 int param_index
= c
->prog_data
.nr_params
;
546 /* FINISHME: This is wildly incomplete. */
547 assert(ir
->type
->is_scalar() || ir
->type
->is_vector());
549 const struct gl_program
*fp
= &this->brw
->fragment_program
->Base
;
550 /* Our support for uniforms is piggy-backed on the struct
551 * gl_fragment_program, because that's where the values actually
552 * get stored, rather than in some global gl_shader_program uniform
555 vec_values
= fp
->Parameters
->ParameterValues
[ir
->location
];
556 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
557 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
560 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
564 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
566 hash_table_insert(this->variable_ht
, reg
, ir
);
570 fs_visitor::visit(ir_dereference_variable
*ir
)
572 fs_reg
*reg
= variable_storage(ir
->var
);
577 fs_visitor::visit(ir_dereference_record
*ir
)
583 fs_visitor::visit(ir_dereference_array
*ir
)
588 ir
->array
->accept(this);
589 index
= ir
->array_index
->as_constant();
591 if (ir
->type
->is_matrix()) {
592 element_size
= ir
->type
->vector_elements
;
594 element_size
= type_size(ir
->type
);
598 assert(this->result
.file
== UNIFORM
||
599 (this->result
.file
== GRF
&&
600 this->result
.reg
!= 0));
601 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
603 assert(!"FINISHME: non-constant matrix column");
608 fs_visitor::visit(ir_expression
*ir
)
610 unsigned int operand
;
615 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
616 ir
->operands
[operand
]->accept(this);
617 if (this->result
.file
== BAD_FILE
) {
619 printf("Failed to get tree for expression operand:\n");
620 ir
->operands
[operand
]->accept(&v
);
623 op
[operand
] = this->result
;
625 /* Matrix expression operands should have been broken down to vector
626 * operations already.
628 assert(!ir
->operands
[operand
]->type
->is_matrix());
629 /* And then those vector operands should have been broken down to scalar.
631 assert(!ir
->operands
[operand
]->type
->is_vector());
634 /* Storage for our result. If our result goes into an assignment, it will
635 * just get copy-propagated out, so no worries.
637 this->result
= fs_reg(this, ir
->type
);
639 switch (ir
->operation
) {
640 case ir_unop_logic_not
:
641 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
644 this->result
= op
[0];
645 op
[0].negate
= ~op
[0].negate
;
648 this->result
= op
[0];
652 temp
= fs_reg(this, ir
->type
);
654 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
655 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
657 inst
= emit(fs_inst(BRW_OPCODE_CMP
, temp
, op
[0], fs_reg(0.0f
)));
658 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
661 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, this->result
, temp
));
665 emit(fs_inst(FS_OPCODE_RCP
, this->result
, op
[0]));
669 emit(fs_inst(FS_OPCODE_EXP2
, this->result
, op
[0]));
672 emit(fs_inst(FS_OPCODE_LOG2
, this->result
, op
[0]));
676 assert(!"not reached: should be handled by ir_explog_to_explog2");
679 emit(fs_inst(FS_OPCODE_SIN
, this->result
, op
[0]));
682 emit(fs_inst(FS_OPCODE_COS
, this->result
, op
[0]));
686 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
689 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
693 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
696 assert(!"not reached: should be handled by ir_sub_to_add_neg");
700 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
703 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
706 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
710 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
711 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
713 case ir_binop_greater
:
714 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
715 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
717 case ir_binop_lequal
:
718 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
719 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
721 case ir_binop_gequal
:
722 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
723 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
726 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
727 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
729 case ir_binop_nequal
:
730 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
731 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
734 case ir_binop_logic_xor
:
735 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
738 case ir_binop_logic_or
:
739 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
742 case ir_binop_logic_and
:
743 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
749 assert(!"not reached: should be handled by brw_channel_expressions");
753 emit(fs_inst(FS_OPCODE_SQRT
, this->result
, op
[0]));
757 emit(fs_inst(FS_OPCODE_RSQ
, this->result
, op
[0]));
763 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
766 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
770 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
771 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
774 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
777 op
[0].negate
= ~op
[0].negate
;
778 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
779 this->result
.negate
= true;
782 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
785 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
789 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
790 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
792 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
793 inst
->predicated
= true;
796 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
797 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
799 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
800 inst
->predicated
= true;
804 inst
= emit(fs_inst(FS_OPCODE_POW
, this->result
, op
[0], op
[1]));
807 case ir_unop_bit_not
:
809 case ir_binop_lshift
:
810 case ir_binop_rshift
:
811 case ir_binop_bit_and
:
812 case ir_binop_bit_xor
:
813 case ir_binop_bit_or
:
814 assert(!"GLSL 1.30 features unsupported");
820 fs_visitor::visit(ir_assignment
*ir
)
827 /* FINISHME: arrays on the lhs */
828 ir
->lhs
->accept(this);
831 ir
->rhs
->accept(this);
834 /* FINISHME: This should really set to the correct maximal writemask for each
835 * FINISHME: component written (in the loops below). This case can only
836 * FINISHME: occur for matrices, arrays, and structures.
838 if (ir
->write_mask
== 0) {
839 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
840 write_mask
= WRITEMASK_XYZW
;
842 assert(ir
->lhs
->type
->is_vector() || ir
->lhs
->type
->is_scalar());
843 write_mask
= ir
->write_mask
;
846 assert(l
.file
!= BAD_FILE
);
847 assert(r
.file
!= BAD_FILE
);
850 /* Get the condition bool into the predicate. */
851 ir
->condition
->accept(this);
852 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, fs_reg(0)));
853 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
856 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
857 if (i
>= 4 || (write_mask
& (1 << i
))) {
858 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
860 inst
->predicated
= true;
868 fs_visitor::visit(ir_texture
*ir
)
874 fs_visitor::visit(ir_swizzle
*ir
)
876 ir
->val
->accept(this);
877 fs_reg val
= this->result
;
879 fs_reg result
= fs_reg(this, ir
->type
);
880 this->result
= result
;
882 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
883 fs_reg channel
= val
;
901 channel
.reg_offset
+= swiz
;
902 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
908 fs_visitor::visit(ir_discard
*ir
)
914 fs_visitor::visit(ir_constant
*ir
)
916 fs_reg
reg(this, ir
->type
);
919 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
920 switch (ir
->type
->base_type
) {
921 case GLSL_TYPE_FLOAT
:
922 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
925 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
928 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
931 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
934 assert(!"Non-float/uint/int/bool constant");
941 fs_visitor::visit(ir_if
*ir
)
945 /* Don't point the annotation at the if statement, because then it plus
946 * the then and else blocks get printed.
948 this->base_ir
= ir
->condition
;
950 /* Generate the condition into the condition code. */
951 ir
->condition
->accept(this);
952 inst
= emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(brw_null_reg()), this->result
));
953 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
955 inst
= emit(fs_inst(BRW_OPCODE_IF
));
956 inst
->predicated
= true;
958 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
959 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
965 if (!ir
->else_instructions
.is_empty()) {
966 emit(fs_inst(BRW_OPCODE_ELSE
));
968 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
969 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
976 emit(fs_inst(BRW_OPCODE_ENDIF
));
980 fs_visitor::visit(ir_loop
*ir
)
986 fs_visitor::visit(ir_loop_jump
*ir
)
992 fs_visitor::visit(ir_call
*ir
)
998 fs_visitor::visit(ir_return
*ir
)
1000 assert(!"FINISHME");
1004 fs_visitor::visit(ir_function
*ir
)
1006 /* Ignore function bodies other than main() -- we shouldn't see calls to
1007 * them since they should all be inlined before we get to ir_to_mesa.
1009 if (strcmp(ir
->name
, "main") == 0) {
1010 const ir_function_signature
*sig
;
1013 sig
= ir
->matching_signature(&empty
);
1017 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1018 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1027 fs_visitor::visit(ir_function_signature
*ir
)
1029 assert(!"not reached");
1034 fs_visitor::emit(fs_inst inst
)
1036 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1039 list_inst
->annotation
= this->current_annotation
;
1040 list_inst
->ir
= this->base_ir
;
1042 this->instructions
.push_tail(list_inst
);
1047 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1049 fs_visitor::emit_dummy_fs()
1051 /* Everyone's favorite color. */
1052 emit(fs_inst(BRW_OPCODE_MOV
,
1055 emit(fs_inst(BRW_OPCODE_MOV
,
1058 emit(fs_inst(BRW_OPCODE_MOV
,
1061 emit(fs_inst(BRW_OPCODE_MOV
,
1066 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1071 /* The register location here is relative to the start of the URB
1072 * data. It will get adjusted to be a real location before
1073 * generate_code() time.
1076 fs_visitor::interp_reg(int location
, int channel
)
1078 int regnr
= location
* 2 + channel
/ 2;
1079 int stride
= (channel
& 1) * 4;
1081 return brw_vec1_grf(regnr
, stride
);
1084 /** Emits the interpolation for the varying inputs. */
1086 fs_visitor::emit_interpolation()
1088 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1089 /* For now, the source regs for the setup URB data will be unset,
1090 * since we don't know until codegen how many push constants we'll
1091 * use, and therefore what the setup URB offset is.
1093 fs_reg src_reg
= reg_undef
;
1095 this->current_annotation
= "compute pixel centers";
1096 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1097 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1098 emit(fs_inst(BRW_OPCODE_ADD
,
1100 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1101 fs_reg(brw_imm_v(0x10101010))));
1102 emit(fs_inst(BRW_OPCODE_ADD
,
1104 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1105 fs_reg(brw_imm_v(0x11001100))));
1107 this->current_annotation
= "compute pixel deltas from v0";
1108 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1109 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1110 emit(fs_inst(BRW_OPCODE_ADD
,
1113 fs_reg(negate(brw_vec1_grf(1, 0)))));
1114 emit(fs_inst(BRW_OPCODE_ADD
,
1117 fs_reg(brw_vec1_grf(1, 1))));
1119 this->current_annotation
= "compute pos.w and 1/pos.w";
1120 /* Compute wpos. Unlike many other varying inputs, we usually need it
1121 * to produce 1/w, and the varying variable wouldn't show up.
1123 fs_reg wpos
= fs_reg(this, glsl_type::vec4_type
);
1124 this->interp_attrs
[FRAG_ATTRIB_WPOS
] = wpos
;
1125 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
)); /* FINISHME: ARB_fcc */
1127 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
)); /* FINISHME: ARB_fcc */
1129 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
1130 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
1132 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
1133 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1134 /* Compute the pixel W value from wpos.w. */
1135 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1136 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos
));
1138 /* FINISHME: gl_FrontFacing */
1140 foreach_iter(exec_list_iterator
, iter
, *this->shader
->ir
) {
1141 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1142 ir_variable
*var
= ir
->as_variable();
1147 if (var
->mode
!= ir_var_in
)
1150 /* If it's already set up (WPOS), skip. */
1151 if (var
->location
== 0)
1154 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1156 "(FRAG_ATTRIB[%d])",
1159 emit_pinterp(var
->location
);
1161 this->current_annotation
= NULL
;
1165 fs_visitor::emit_pinterp(int location
)
1167 fs_reg interp_attr
= fs_reg(this, glsl_type::vec4_type
);
1168 this->interp_attrs
[location
] = interp_attr
;
1170 for (unsigned int i
= 0; i
< 4; i
++) {
1171 struct brw_reg interp
= interp_reg(location
, i
);
1172 emit(fs_inst(FS_OPCODE_LINTERP
,
1177 interp_attr
.reg_offset
++;
1179 interp_attr
.reg_offset
-= 4;
1181 for (unsigned int i
= 0; i
< 4; i
++) {
1182 emit(fs_inst(BRW_OPCODE_MUL
,
1186 interp_attr
.reg_offset
++;
1191 fs_visitor::emit_fb_writes()
1193 this->current_annotation
= "FB write";
1195 assert(this->frag_color
|| !"FINISHME: MRT");
1196 fs_reg color
= *(variable_storage(this->frag_color
));
1198 for (int i
= 0; i
< 4; i
++) {
1199 emit(fs_inst(BRW_OPCODE_MOV
,
1205 emit(fs_inst(FS_OPCODE_FB_WRITE
,
1209 this->current_annotation
= NULL
;
1213 fs_visitor::generate_fb_write(fs_inst
*inst
)
1215 GLboolean eot
= 1; /* FINISHME: MRT */
1216 /* FINISHME: AADS */
1218 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1221 brw_push_insn_state(p
);
1222 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1223 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1226 brw_vec8_grf(1, 0));
1227 brw_pop_insn_state(p
);
1232 8, /* dispatch_width */
1233 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
1235 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
1236 0, /* FINISHME: MRT target */
1243 fs_visitor::generate_linterp(fs_inst
*inst
,
1244 struct brw_reg dst
, struct brw_reg
*src
)
1246 struct brw_reg delta_x
= src
[0];
1247 struct brw_reg delta_y
= src
[1];
1248 struct brw_reg interp
= src
[2];
1251 delta_y
.nr
== delta_x
.nr
+ 1 &&
1252 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
1253 brw_PLN(p
, dst
, interp
, delta_x
);
1255 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
1256 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
1261 fs_visitor::generate_math(fs_inst
*inst
,
1262 struct brw_reg dst
, struct brw_reg
*src
)
1266 switch (inst
->opcode
) {
1268 op
= BRW_MATH_FUNCTION_INV
;
1271 op
= BRW_MATH_FUNCTION_RSQ
;
1273 case FS_OPCODE_SQRT
:
1274 op
= BRW_MATH_FUNCTION_SQRT
;
1276 case FS_OPCODE_EXP2
:
1277 op
= BRW_MATH_FUNCTION_EXP
;
1279 case FS_OPCODE_LOG2
:
1280 op
= BRW_MATH_FUNCTION_LOG
;
1283 op
= BRW_MATH_FUNCTION_POW
;
1286 op
= BRW_MATH_FUNCTION_SIN
;
1289 op
= BRW_MATH_FUNCTION_COS
;
1292 assert(!"not reached: unknown math function");
1297 if (inst
->opcode
== FS_OPCODE_POW
) {
1298 brw_MOV(p
, brw_message_reg(3), src
[1]);
1303 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
1304 BRW_MATH_SATURATE_NONE
,
1306 BRW_MATH_DATA_VECTOR
,
1307 BRW_MATH_PRECISION_FULL
);
1311 trivial_assign_reg(int header_size
, fs_reg
*reg
)
1313 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
1314 reg
->hw_reg
= header_size
+ reg
->reg
- 1 + reg
->reg_offset
;
1320 fs_visitor::assign_curb_setup()
1322 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
1323 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
1325 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1326 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1327 fs_inst
*inst
= (fs_inst
*)iter
.get();
1329 for (unsigned int i
= 0; i
< 3; i
++) {
1330 if (inst
->src
[i
].file
== UNIFORM
) {
1331 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
1332 struct brw_reg brw_reg
;
1334 brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
1337 inst
->src
[i
] = fs_reg(brw_reg
);
1344 fs_visitor::assign_urb_setup()
1346 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
1347 int interp_reg_nr
[FRAG_ATTRIB_MAX
];
1349 c
->prog_data
.urb_read_length
= 0;
1351 /* Figure out where each of the incoming setup attributes lands. */
1352 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
1353 interp_reg_nr
[i
] = -1;
1355 if (i
!= FRAG_ATTRIB_WPOS
&&
1356 !(brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)))
1359 /* Each attribute is 4 setup channels, each of which is half a reg. */
1360 interp_reg_nr
[i
] = urb_start
+ c
->prog_data
.urb_read_length
;
1361 c
->prog_data
.urb_read_length
+= 2;
1364 /* Map the register numbers for FS_OPCODE_LINTERP so that it uses
1365 * the correct setup input.
1367 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1368 fs_inst
*inst
= (fs_inst
*)iter
.get();
1370 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
1373 assert(inst
->src
[2].file
== FIXED_HW_REG
);
1375 int location
= inst
->src
[2].fixed_hw_reg
.nr
/ 2;
1376 assert(interp_reg_nr
[location
] != -1);
1377 inst
->src
[2].fixed_hw_reg
.nr
= (interp_reg_nr
[location
] +
1378 (inst
->src
[2].fixed_hw_reg
.nr
& 1));
1381 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
1385 fs_visitor::assign_regs()
1387 int header_size
= this->first_non_payload_grf
;
1390 /* FINISHME: trivial assignment of register numbers */
1391 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1392 fs_inst
*inst
= (fs_inst
*)iter
.get();
1394 trivial_assign_reg(header_size
, &inst
->dst
);
1395 trivial_assign_reg(header_size
, &inst
->src
[0]);
1396 trivial_assign_reg(header_size
, &inst
->src
[1]);
1398 last_grf
= MAX2(last_grf
, inst
->dst
.hw_reg
);
1399 last_grf
= MAX2(last_grf
, inst
->src
[0].hw_reg
);
1400 last_grf
= MAX2(last_grf
, inst
->src
[1].hw_reg
);
1403 this->grf_used
= last_grf
+ 1;
1406 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
1408 struct brw_reg brw_reg
;
1410 switch (reg
->file
) {
1414 brw_reg
= brw_vec8_reg(reg
->file
,
1416 brw_reg
= retype(brw_reg
, reg
->type
);
1419 switch (reg
->type
) {
1420 case BRW_REGISTER_TYPE_F
:
1421 brw_reg
= brw_imm_f(reg
->imm
.f
);
1423 case BRW_REGISTER_TYPE_D
:
1424 brw_reg
= brw_imm_f(reg
->imm
.i
);
1426 case BRW_REGISTER_TYPE_UD
:
1427 brw_reg
= brw_imm_f(reg
->imm
.u
);
1430 assert(!"not reached");
1435 brw_reg
= reg
->fixed_hw_reg
;
1438 /* Probably unused. */
1439 brw_reg
= brw_null_reg();
1442 assert(!"not reached");
1443 brw_reg
= brw_null_reg();
1447 brw_reg
= brw_abs(brw_reg
);
1449 brw_reg
= negate(brw_reg
);
1455 fs_visitor::generate_code()
1457 unsigned int annotation_len
= 0;
1458 int last_native_inst
= 0;
1459 struct brw_instruction
*if_stack
[16];
1460 int if_stack_depth
= 0;
1462 memset(&if_stack
, 0, sizeof(if_stack
));
1463 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1464 fs_inst
*inst
= (fs_inst
*)iter
.get();
1465 struct brw_reg src
[3], dst
;
1467 for (unsigned int i
= 0; i
< 3; i
++) {
1468 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
1470 dst
= brw_reg_from_fs_reg(&inst
->dst
);
1472 brw_set_conditionalmod(p
, inst
->conditional_mod
);
1473 brw_set_predicate_control(p
, inst
->predicated
);
1475 switch (inst
->opcode
) {
1476 case BRW_OPCODE_MOV
:
1477 brw_MOV(p
, dst
, src
[0]);
1479 case BRW_OPCODE_ADD
:
1480 brw_ADD(p
, dst
, src
[0], src
[1]);
1482 case BRW_OPCODE_MUL
:
1483 brw_MUL(p
, dst
, src
[0], src
[1]);
1486 case BRW_OPCODE_AND
:
1487 brw_AND(p
, dst
, src
[0], src
[1]);
1490 brw_OR(p
, dst
, src
[0], src
[1]);
1492 case BRW_OPCODE_XOR
:
1493 brw_XOR(p
, dst
, src
[0], src
[1]);
1496 case BRW_OPCODE_CMP
:
1497 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1500 assert(if_stack_depth
< 16);
1501 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
1504 case BRW_OPCODE_ELSE
:
1505 if_stack
[if_stack_depth
- 1] =
1506 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
1508 case BRW_OPCODE_ENDIF
:
1510 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
1514 case FS_OPCODE_SQRT
:
1515 case FS_OPCODE_EXP2
:
1516 case FS_OPCODE_LOG2
:
1520 generate_math(inst
, dst
, src
);
1522 case FS_OPCODE_LINTERP
:
1523 generate_linterp(inst
, dst
, src
);
1525 case FS_OPCODE_FB_WRITE
:
1526 generate_fb_write(inst
);
1529 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
1530 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
1531 brw_opcodes
[inst
->opcode
].name
);
1533 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
1538 if (annotation_len
< p
->nr_insn
) {
1539 annotation_len
*= 2;
1540 if (annotation_len
< 16)
1541 annotation_len
= 16;
1543 this->annotation_string
= talloc_realloc(this->mem_ctx
,
1547 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
1553 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
1554 this->annotation_string
[i
] = inst
->annotation
;
1555 this->annotation_ir
[i
] = inst
->ir
;
1557 last_native_inst
= p
->nr_insn
;
1562 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
1564 struct brw_compile
*p
= &c
->func
;
1565 struct intel_context
*intel
= &brw
->intel
;
1566 GLcontext
*ctx
= &intel
->ctx
;
1567 struct brw_shader
*shader
= NULL
;
1568 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
1576 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
1577 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
1578 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
1585 /* We always use 8-wide mode, at least for now. For one, flow
1586 * control only works in 8-wide. Also, when we're fragment shader
1587 * bound, we're almost always under register pressure as well, so
1588 * 8-wide would save us from the performance cliff of spilling
1591 c
->dispatch_width
= 8;
1593 if (INTEL_DEBUG
& DEBUG_WM
) {
1594 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
1595 _mesa_print_ir(shader
->ir
, NULL
);
1599 /* Now the main event: Visit the shader IR and generate our FS IR for it.
1601 fs_visitor
v(c
, shader
);
1606 v
.emit_interpolation();
1608 /* Generate FS IR for main(). (the visitor only descends into
1609 * functions called "main").
1611 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
1612 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1621 v
.assign_curb_setup();
1622 v
.assign_urb_setup();
1628 if (INTEL_DEBUG
& DEBUG_WM
) {
1629 const char *last_annotation_string
= NULL
;
1630 ir_instruction
*last_annotation_ir
= NULL
;
1632 printf("Native code for fragment shader %d:\n", prog
->Name
);
1633 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
1634 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
1635 last_annotation_ir
= v
.annotation_ir
[i
];
1636 if (last_annotation_ir
) {
1638 last_annotation_ir
->print();
1642 if (last_annotation_string
!= v
.annotation_string
[i
]) {
1643 last_annotation_string
= v
.annotation_string
[i
];
1644 if (last_annotation_string
)
1645 printf(" %s\n", last_annotation_string
);
1647 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
1652 c
->prog_data
.total_grf
= v
.grf_used
;
1653 c
->prog_data
.total_scratch
= 0;