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i965: Fix type of gl_FragData[] dereference for FB write.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 extern "C" {
29
30 #include <sys/types.h>
31
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
42 #include "brw_eu.h"
43 #include "brw_wm.h"
44 #include "talloc.h"
45 }
46 #include "brw_fs.h"
47 #include "../glsl/glsl_types.h"
48 #include "../glsl/ir_optimization.h"
49 #include "../glsl/ir_print_visitor.h"
50
51 static struct brw_reg brw_reg_from_fs_reg(class fs_reg *reg);
52
53 struct gl_shader *
54 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
55 {
56 struct brw_shader *shader;
57
58 shader = talloc_zero(NULL, struct brw_shader);
59 if (shader) {
60 shader->base.Type = type;
61 shader->base.Name = name;
62 _mesa_init_shader(ctx, &shader->base);
63 }
64
65 return &shader->base;
66 }
67
68 struct gl_shader_program *
69 brw_new_shader_program(struct gl_context *ctx, GLuint name)
70 {
71 struct brw_shader_program *prog;
72 prog = talloc_zero(NULL, struct brw_shader_program);
73 if (prog) {
74 prog->base.Name = name;
75 _mesa_init_shader_program(ctx, &prog->base);
76 }
77 return &prog->base;
78 }
79
80 GLboolean
81 brw_compile_shader(struct gl_context *ctx, struct gl_shader *shader)
82 {
83 if (!_mesa_ir_compile_shader(ctx, shader))
84 return GL_FALSE;
85
86 return GL_TRUE;
87 }
88
89 GLboolean
90 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
91 {
92 struct brw_shader *shader =
93 (struct brw_shader *)prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
94 if (shader != NULL) {
95 void *mem_ctx = talloc_new(NULL);
96 bool progress;
97
98 if (shader->ir)
99 talloc_free(shader->ir);
100 shader->ir = new(shader) exec_list;
101 clone_ir_list(mem_ctx, shader->ir, shader->base.ir);
102
103 do_mat_op_to_vec(shader->ir);
104 lower_instructions(shader->ir,
105 MOD_TO_FRACT |
106 DIV_TO_MUL_RCP |
107 SUB_TO_ADD_NEG |
108 EXP_TO_EXP2 |
109 LOG_TO_LOG2);
110 do_lower_texture_projection(shader->ir);
111 brw_do_cubemap_normalize(shader->ir);
112
113 do {
114 progress = false;
115
116 brw_do_channel_expressions(shader->ir);
117 brw_do_vector_splitting(shader->ir);
118
119 progress = do_lower_jumps(shader->ir, true, true,
120 true, /* main return */
121 false, /* continue */
122 false /* loops */
123 ) || progress;
124
125 progress = do_common_optimization(shader->ir, true, 32) || progress;
126
127 progress = lower_noise(shader->ir) || progress;
128 progress =
129 lower_variable_index_to_cond_assign(shader->ir,
130 GL_TRUE, /* input */
131 GL_TRUE, /* output */
132 GL_TRUE, /* temp */
133 GL_TRUE /* uniform */
134 ) || progress;
135 progress = lower_quadop_vector(shader->ir, false) || progress;
136 } while (progress);
137
138 validate_ir_tree(shader->ir);
139
140 reparent_ir(shader->ir, shader->ir);
141 talloc_free(mem_ctx);
142 }
143
144 if (!_mesa_ir_link_shader(ctx, prog))
145 return GL_FALSE;
146
147 return GL_TRUE;
148 }
149
150 static int
151 type_size(const struct glsl_type *type)
152 {
153 unsigned int size, i;
154
155 switch (type->base_type) {
156 case GLSL_TYPE_UINT:
157 case GLSL_TYPE_INT:
158 case GLSL_TYPE_FLOAT:
159 case GLSL_TYPE_BOOL:
160 return type->components();
161 case GLSL_TYPE_ARRAY:
162 return type_size(type->fields.array) * type->length;
163 case GLSL_TYPE_STRUCT:
164 size = 0;
165 for (i = 0; i < type->length; i++) {
166 size += type_size(type->fields.structure[i].type);
167 }
168 return size;
169 case GLSL_TYPE_SAMPLER:
170 /* Samplers take up no register space, since they're baked in at
171 * link time.
172 */
173 return 0;
174 default:
175 assert(!"not reached");
176 return 0;
177 }
178 }
179
180 /**
181 * Returns how many MRFs an FS opcode will write over.
182 *
183 * Note that this is not the 0 or 1 implied writes in an actual gen
184 * instruction -- the FS opcodes often generate MOVs in addition.
185 */
186 int
187 fs_visitor::implied_mrf_writes(fs_inst *inst)
188 {
189 if (inst->mlen == 0)
190 return 0;
191
192 switch (inst->opcode) {
193 case FS_OPCODE_RCP:
194 case FS_OPCODE_RSQ:
195 case FS_OPCODE_SQRT:
196 case FS_OPCODE_EXP2:
197 case FS_OPCODE_LOG2:
198 case FS_OPCODE_SIN:
199 case FS_OPCODE_COS:
200 return 1;
201 case FS_OPCODE_POW:
202 return 2;
203 case FS_OPCODE_TEX:
204 case FS_OPCODE_TXB:
205 case FS_OPCODE_TXL:
206 return 1;
207 case FS_OPCODE_FB_WRITE:
208 return 2;
209 case FS_OPCODE_PULL_CONSTANT_LOAD:
210 case FS_OPCODE_UNSPILL:
211 return 1;
212 case FS_OPCODE_SPILL:
213 return 2;
214 default:
215 assert(!"not reached");
216 return inst->mlen;
217 }
218 }
219
220 int
221 fs_visitor::virtual_grf_alloc(int size)
222 {
223 if (virtual_grf_array_size <= virtual_grf_next) {
224 if (virtual_grf_array_size == 0)
225 virtual_grf_array_size = 16;
226 else
227 virtual_grf_array_size *= 2;
228 virtual_grf_sizes = talloc_realloc(mem_ctx, virtual_grf_sizes,
229 int, virtual_grf_array_size);
230
231 /* This slot is always unused. */
232 virtual_grf_sizes[0] = 0;
233 }
234 virtual_grf_sizes[virtual_grf_next] = size;
235 return virtual_grf_next++;
236 }
237
238 /** Fixed HW reg constructor. */
239 fs_reg::fs_reg(enum register_file file, int hw_reg)
240 {
241 init();
242 this->file = file;
243 this->hw_reg = hw_reg;
244 this->type = BRW_REGISTER_TYPE_F;
245 }
246
247 /** Fixed HW reg constructor. */
248 fs_reg::fs_reg(enum register_file file, int hw_reg, uint32_t type)
249 {
250 init();
251 this->file = file;
252 this->hw_reg = hw_reg;
253 this->type = type;
254 }
255
256 int
257 brw_type_for_base_type(const struct glsl_type *type)
258 {
259 switch (type->base_type) {
260 case GLSL_TYPE_FLOAT:
261 return BRW_REGISTER_TYPE_F;
262 case GLSL_TYPE_INT:
263 case GLSL_TYPE_BOOL:
264 return BRW_REGISTER_TYPE_D;
265 case GLSL_TYPE_UINT:
266 return BRW_REGISTER_TYPE_UD;
267 case GLSL_TYPE_ARRAY:
268 case GLSL_TYPE_STRUCT:
269 case GLSL_TYPE_SAMPLER:
270 /* These should be overridden with the type of the member when
271 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
272 * way to trip up if we don't.
273 */
274 return BRW_REGISTER_TYPE_UD;
275 default:
276 assert(!"not reached");
277 return BRW_REGISTER_TYPE_F;
278 }
279 }
280
281 /** Automatic reg constructor. */
282 fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type)
283 {
284 init();
285
286 this->file = GRF;
287 this->reg = v->virtual_grf_alloc(type_size(type));
288 this->reg_offset = 0;
289 this->type = brw_type_for_base_type(type);
290 }
291
292 fs_reg *
293 fs_visitor::variable_storage(ir_variable *var)
294 {
295 return (fs_reg *)hash_table_find(this->variable_ht, var);
296 }
297
298 /* Our support for uniforms is piggy-backed on the struct
299 * gl_fragment_program, because that's where the values actually
300 * get stored, rather than in some global gl_shader_program uniform
301 * store.
302 */
303 int
304 fs_visitor::setup_uniform_values(int loc, const glsl_type *type)
305 {
306 unsigned int offset = 0;
307 float *vec_values;
308
309 if (type->is_matrix()) {
310 const glsl_type *column = glsl_type::get_instance(GLSL_TYPE_FLOAT,
311 type->vector_elements,
312 1);
313
314 for (unsigned int i = 0; i < type->matrix_columns; i++) {
315 offset += setup_uniform_values(loc + offset, column);
316 }
317
318 return offset;
319 }
320
321 switch (type->base_type) {
322 case GLSL_TYPE_FLOAT:
323 case GLSL_TYPE_UINT:
324 case GLSL_TYPE_INT:
325 case GLSL_TYPE_BOOL:
326 vec_values = fp->Base.Parameters->ParameterValues[loc];
327 for (unsigned int i = 0; i < type->vector_elements; i++) {
328 unsigned int param = c->prog_data.nr_params++;
329
330 assert(param < ARRAY_SIZE(c->prog_data.param));
331
332 switch (type->base_type) {
333 case GLSL_TYPE_FLOAT:
334 c->prog_data.param_convert[param] = PARAM_NO_CONVERT;
335 break;
336 case GLSL_TYPE_UINT:
337 c->prog_data.param_convert[param] = PARAM_CONVERT_F2U;
338 break;
339 case GLSL_TYPE_INT:
340 c->prog_data.param_convert[param] = PARAM_CONVERT_F2I;
341 break;
342 case GLSL_TYPE_BOOL:
343 c->prog_data.param_convert[param] = PARAM_CONVERT_F2B;
344 break;
345 default:
346 assert(!"not reached");
347 c->prog_data.param_convert[param] = PARAM_NO_CONVERT;
348 break;
349 }
350
351 c->prog_data.param[param] = &vec_values[i];
352 }
353 return 1;
354
355 case GLSL_TYPE_STRUCT:
356 for (unsigned int i = 0; i < type->length; i++) {
357 offset += setup_uniform_values(loc + offset,
358 type->fields.structure[i].type);
359 }
360 return offset;
361
362 case GLSL_TYPE_ARRAY:
363 for (unsigned int i = 0; i < type->length; i++) {
364 offset += setup_uniform_values(loc + offset, type->fields.array);
365 }
366 return offset;
367
368 case GLSL_TYPE_SAMPLER:
369 /* The sampler takes up a slot, but we don't use any values from it. */
370 return 1;
371
372 default:
373 assert(!"not reached");
374 return 0;
375 }
376 }
377
378
379 /* Our support for builtin uniforms is even scarier than non-builtin.
380 * It sits on top of the PROG_STATE_VAR parameters that are
381 * automatically updated from GL context state.
382 */
383 void
384 fs_visitor::setup_builtin_uniform_values(ir_variable *ir)
385 {
386 const struct gl_builtin_uniform_desc *statevar = NULL;
387
388 for (unsigned int i = 0; _mesa_builtin_uniform_desc[i].name; i++) {
389 statevar = &_mesa_builtin_uniform_desc[i];
390 if (strcmp(ir->name, _mesa_builtin_uniform_desc[i].name) == 0)
391 break;
392 }
393
394 if (!statevar->name) {
395 this->fail = true;
396 printf("Failed to find builtin uniform `%s'\n", ir->name);
397 return;
398 }
399
400 int array_count;
401 if (ir->type->is_array()) {
402 array_count = ir->type->length;
403 } else {
404 array_count = 1;
405 }
406
407 for (int a = 0; a < array_count; a++) {
408 for (unsigned int i = 0; i < statevar->num_elements; i++) {
409 struct gl_builtin_uniform_element *element = &statevar->elements[i];
410 int tokens[STATE_LENGTH];
411
412 memcpy(tokens, element->tokens, sizeof(element->tokens));
413 if (ir->type->is_array()) {
414 tokens[1] = a;
415 }
416
417 /* This state reference has already been setup by ir_to_mesa,
418 * but we'll get the same index back here.
419 */
420 int index = _mesa_add_state_reference(this->fp->Base.Parameters,
421 (gl_state_index *)tokens);
422 float *vec_values = this->fp->Base.Parameters->ParameterValues[index];
423
424 /* Add each of the unique swizzles of the element as a
425 * parameter. This'll end up matching the expected layout of
426 * the array/matrix/structure we're trying to fill in.
427 */
428 int last_swiz = -1;
429 for (unsigned int i = 0; i < 4; i++) {
430 int swiz = GET_SWZ(element->swizzle, i);
431 if (swiz == last_swiz)
432 break;
433 last_swiz = swiz;
434
435 c->prog_data.param_convert[c->prog_data.nr_params] =
436 PARAM_NO_CONVERT;
437 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[swiz];
438 }
439 }
440 }
441 }
442
443 fs_reg *
444 fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
445 {
446 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
447 fs_reg wpos = *reg;
448 fs_reg neg_y = this->pixel_y;
449 neg_y.negate = true;
450 bool flip = !ir->origin_upper_left ^ c->key.render_to_fbo;
451
452 /* gl_FragCoord.x */
453 if (ir->pixel_center_integer) {
454 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_x));
455 } else {
456 emit(fs_inst(BRW_OPCODE_ADD, wpos, this->pixel_x, fs_reg(0.5f)));
457 }
458 wpos.reg_offset++;
459
460 /* gl_FragCoord.y */
461 if (!flip && ir->pixel_center_integer) {
462 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_y));
463 } else {
464 fs_reg pixel_y = this->pixel_y;
465 float offset = (ir->pixel_center_integer ? 0.0 : 0.5);
466
467 if (flip) {
468 pixel_y.negate = true;
469 offset += c->key.drawable_height - 1.0;
470 }
471
472 emit(fs_inst(BRW_OPCODE_ADD, wpos, pixel_y, fs_reg(offset)));
473 }
474 wpos.reg_offset++;
475
476 /* gl_FragCoord.z */
477 emit(fs_inst(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y,
478 interp_reg(FRAG_ATTRIB_WPOS, 2)));
479 wpos.reg_offset++;
480
481 /* gl_FragCoord.w: Already set up in emit_interpolation */
482 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->wpos_w));
483
484 return reg;
485 }
486
487 fs_reg *
488 fs_visitor::emit_general_interpolation(ir_variable *ir)
489 {
490 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
491 /* Interpolation is always in floating point regs. */
492 reg->type = BRW_REGISTER_TYPE_F;
493 fs_reg attr = *reg;
494
495 unsigned int array_elements;
496 const glsl_type *type;
497
498 if (ir->type->is_array()) {
499 array_elements = ir->type->length;
500 if (array_elements == 0) {
501 this->fail = true;
502 }
503 type = ir->type->fields.array;
504 } else {
505 array_elements = 1;
506 type = ir->type;
507 }
508
509 int location = ir->location;
510 for (unsigned int i = 0; i < array_elements; i++) {
511 for (unsigned int j = 0; j < type->matrix_columns; j++) {
512 if (urb_setup[location] == -1) {
513 /* If there's no incoming setup data for this slot, don't
514 * emit interpolation for it.
515 */
516 attr.reg_offset += type->vector_elements;
517 location++;
518 continue;
519 }
520
521 for (unsigned int c = 0; c < type->vector_elements; c++) {
522 struct brw_reg interp = interp_reg(location, c);
523 emit(fs_inst(FS_OPCODE_LINTERP,
524 attr,
525 this->delta_x,
526 this->delta_y,
527 fs_reg(interp)));
528 attr.reg_offset++;
529 }
530
531 if (intel->gen < 6) {
532 attr.reg_offset -= type->vector_elements;
533 for (unsigned int c = 0; c < type->vector_elements; c++) {
534 emit(fs_inst(BRW_OPCODE_MUL,
535 attr,
536 attr,
537 this->pixel_w));
538 attr.reg_offset++;
539 }
540 }
541 location++;
542 }
543 }
544
545 return reg;
546 }
547
548 fs_reg *
549 fs_visitor::emit_frontfacing_interpolation(ir_variable *ir)
550 {
551 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
552
553 /* The frontfacing comes in as a bit in the thread payload. */
554 if (intel->gen >= 6) {
555 emit(fs_inst(BRW_OPCODE_ASR,
556 *reg,
557 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)),
558 fs_reg(15)));
559 emit(fs_inst(BRW_OPCODE_NOT,
560 *reg,
561 *reg));
562 emit(fs_inst(BRW_OPCODE_AND,
563 *reg,
564 *reg,
565 fs_reg(1)));
566 } else {
567 struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD);
568 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
569 * us front face
570 */
571 fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP,
572 *reg,
573 fs_reg(r1_6ud),
574 fs_reg(1u << 31)));
575 inst->conditional_mod = BRW_CONDITIONAL_L;
576 emit(fs_inst(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u)));
577 }
578
579 return reg;
580 }
581
582 fs_inst *
583 fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src)
584 {
585 switch (opcode) {
586 case FS_OPCODE_RCP:
587 case FS_OPCODE_RSQ:
588 case FS_OPCODE_SQRT:
589 case FS_OPCODE_EXP2:
590 case FS_OPCODE_LOG2:
591 case FS_OPCODE_SIN:
592 case FS_OPCODE_COS:
593 break;
594 default:
595 assert(!"not reached: bad math opcode");
596 return NULL;
597 }
598
599 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
600 * might be able to do better by doing execsize = 1 math and then
601 * expanding that result out, but we would need to be careful with
602 * masking.
603 */
604 if (intel->gen >= 6 && src.file == UNIFORM) {
605 fs_reg expanded = fs_reg(this, glsl_type::float_type);
606 emit(fs_inst(BRW_OPCODE_MOV, expanded, src));
607 src = expanded;
608 }
609
610 fs_inst *inst = emit(fs_inst(opcode, dst, src));
611
612 if (intel->gen < 6) {
613 inst->base_mrf = 2;
614 inst->mlen = 1;
615 }
616
617 return inst;
618 }
619
620 fs_inst *
621 fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src0, fs_reg src1)
622 {
623 int base_mrf = 2;
624 fs_inst *inst;
625
626 assert(opcode == FS_OPCODE_POW);
627
628 if (intel->gen >= 6) {
629 /* Can't do hstride == 0 args to gen6 math, so expand it out. */
630 if (src0.file == UNIFORM) {
631 fs_reg expanded = fs_reg(this, glsl_type::float_type);
632 emit(fs_inst(BRW_OPCODE_MOV, expanded, src0));
633 src0 = expanded;
634 }
635
636 if (src1.file == UNIFORM) {
637 fs_reg expanded = fs_reg(this, glsl_type::float_type);
638 emit(fs_inst(BRW_OPCODE_MOV, expanded, src1));
639 src1 = expanded;
640 }
641
642 inst = emit(fs_inst(opcode, dst, src0, src1));
643 } else {
644 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + 1), src1));
645 inst = emit(fs_inst(opcode, dst, src0, reg_null_f));
646
647 inst->base_mrf = base_mrf;
648 inst->mlen = 2;
649 }
650 return inst;
651 }
652
653 void
654 fs_visitor::visit(ir_variable *ir)
655 {
656 fs_reg *reg = NULL;
657
658 if (variable_storage(ir))
659 return;
660
661 if (strcmp(ir->name, "gl_FragColor") == 0) {
662 this->frag_color = ir;
663 } else if (strcmp(ir->name, "gl_FragData") == 0) {
664 this->frag_data = ir;
665 } else if (strcmp(ir->name, "gl_FragDepth") == 0) {
666 this->frag_depth = ir;
667 }
668
669 if (ir->mode == ir_var_in) {
670 if (!strcmp(ir->name, "gl_FragCoord")) {
671 reg = emit_fragcoord_interpolation(ir);
672 } else if (!strcmp(ir->name, "gl_FrontFacing")) {
673 reg = emit_frontfacing_interpolation(ir);
674 } else {
675 reg = emit_general_interpolation(ir);
676 }
677 assert(reg);
678 hash_table_insert(this->variable_ht, reg, ir);
679 return;
680 }
681
682 if (ir->mode == ir_var_uniform) {
683 int param_index = c->prog_data.nr_params;
684
685 if (!strncmp(ir->name, "gl_", 3)) {
686 setup_builtin_uniform_values(ir);
687 } else {
688 setup_uniform_values(ir->location, ir->type);
689 }
690
691 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index);
692 reg->type = brw_type_for_base_type(ir->type);
693 }
694
695 if (!reg)
696 reg = new(this->mem_ctx) fs_reg(this, ir->type);
697
698 hash_table_insert(this->variable_ht, reg, ir);
699 }
700
701 void
702 fs_visitor::visit(ir_dereference_variable *ir)
703 {
704 fs_reg *reg = variable_storage(ir->var);
705 this->result = *reg;
706 }
707
708 void
709 fs_visitor::visit(ir_dereference_record *ir)
710 {
711 const glsl_type *struct_type = ir->record->type;
712
713 ir->record->accept(this);
714
715 unsigned int offset = 0;
716 for (unsigned int i = 0; i < struct_type->length; i++) {
717 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0)
718 break;
719 offset += type_size(struct_type->fields.structure[i].type);
720 }
721 this->result.reg_offset += offset;
722 this->result.type = brw_type_for_base_type(ir->type);
723 }
724
725 void
726 fs_visitor::visit(ir_dereference_array *ir)
727 {
728 ir_constant *index;
729 int element_size;
730
731 ir->array->accept(this);
732 index = ir->array_index->as_constant();
733
734 element_size = type_size(ir->type);
735 this->result.type = brw_type_for_base_type(ir->type);
736
737 if (index) {
738 assert(this->result.file == UNIFORM ||
739 (this->result.file == GRF &&
740 this->result.reg != 0));
741 this->result.reg_offset += index->value.i[0] * element_size;
742 } else {
743 assert(!"FINISHME: non-constant array element");
744 }
745 }
746
747 /* Instruction selection: Produce a MOV.sat instead of
748 * MIN(MAX(val, 0), 1) when possible.
749 */
750 bool
751 fs_visitor::try_emit_saturate(ir_expression *ir)
752 {
753 ir_rvalue *sat_val = ir->as_rvalue_to_saturate();
754
755 if (!sat_val)
756 return false;
757
758 sat_val->accept(this);
759 fs_reg src = this->result;
760
761 this->result = fs_reg(this, ir->type);
762 fs_inst *inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, src));
763 inst->saturate = true;
764
765 return true;
766 }
767
768 void
769 fs_visitor::visit(ir_expression *ir)
770 {
771 unsigned int operand;
772 fs_reg op[2], temp;
773 fs_inst *inst;
774
775 assert(ir->get_num_operands() <= 2);
776
777 if (try_emit_saturate(ir))
778 return;
779
780 for (operand = 0; operand < ir->get_num_operands(); operand++) {
781 ir->operands[operand]->accept(this);
782 if (this->result.file == BAD_FILE) {
783 ir_print_visitor v;
784 printf("Failed to get tree for expression operand:\n");
785 ir->operands[operand]->accept(&v);
786 this->fail = true;
787 }
788 op[operand] = this->result;
789
790 /* Matrix expression operands should have been broken down to vector
791 * operations already.
792 */
793 assert(!ir->operands[operand]->type->is_matrix());
794 /* And then those vector operands should have been broken down to scalar.
795 */
796 assert(!ir->operands[operand]->type->is_vector());
797 }
798
799 /* Storage for our result. If our result goes into an assignment, it will
800 * just get copy-propagated out, so no worries.
801 */
802 this->result = fs_reg(this, ir->type);
803
804 switch (ir->operation) {
805 case ir_unop_logic_not:
806 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
807 * ones complement of the whole register, not just bit 0.
808 */
809 emit(fs_inst(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)));
810 break;
811 case ir_unop_neg:
812 op[0].negate = !op[0].negate;
813 this->result = op[0];
814 break;
815 case ir_unop_abs:
816 op[0].abs = true;
817 this->result = op[0];
818 break;
819 case ir_unop_sign:
820 temp = fs_reg(this, ir->type);
821
822 emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)));
823
824 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)));
825 inst->conditional_mod = BRW_CONDITIONAL_G;
826 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)));
827 inst->predicated = true;
828
829 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)));
830 inst->conditional_mod = BRW_CONDITIONAL_L;
831 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)));
832 inst->predicated = true;
833
834 break;
835 case ir_unop_rcp:
836 emit_math(FS_OPCODE_RCP, this->result, op[0]);
837 break;
838
839 case ir_unop_exp2:
840 emit_math(FS_OPCODE_EXP2, this->result, op[0]);
841 break;
842 case ir_unop_log2:
843 emit_math(FS_OPCODE_LOG2, this->result, op[0]);
844 break;
845 case ir_unop_exp:
846 case ir_unop_log:
847 assert(!"not reached: should be handled by ir_explog_to_explog2");
848 break;
849 case ir_unop_sin:
850 case ir_unop_sin_reduced:
851 emit_math(FS_OPCODE_SIN, this->result, op[0]);
852 break;
853 case ir_unop_cos:
854 case ir_unop_cos_reduced:
855 emit_math(FS_OPCODE_COS, this->result, op[0]);
856 break;
857
858 case ir_unop_dFdx:
859 emit(fs_inst(FS_OPCODE_DDX, this->result, op[0]));
860 break;
861 case ir_unop_dFdy:
862 emit(fs_inst(FS_OPCODE_DDY, this->result, op[0]));
863 break;
864
865 case ir_binop_add:
866 emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], op[1]));
867 break;
868 case ir_binop_sub:
869 assert(!"not reached: should be handled by ir_sub_to_add_neg");
870 break;
871
872 case ir_binop_mul:
873 emit(fs_inst(BRW_OPCODE_MUL, this->result, op[0], op[1]));
874 break;
875 case ir_binop_div:
876 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
877 break;
878 case ir_binop_mod:
879 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
880 break;
881
882 case ir_binop_less:
883 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
884 inst->conditional_mod = BRW_CONDITIONAL_L;
885 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
886 break;
887 case ir_binop_greater:
888 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
889 inst->conditional_mod = BRW_CONDITIONAL_G;
890 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
891 break;
892 case ir_binop_lequal:
893 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
894 inst->conditional_mod = BRW_CONDITIONAL_LE;
895 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
896 break;
897 case ir_binop_gequal:
898 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
899 inst->conditional_mod = BRW_CONDITIONAL_GE;
900 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
901 break;
902 case ir_binop_equal:
903 case ir_binop_all_equal: /* same as nequal for scalars */
904 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
905 inst->conditional_mod = BRW_CONDITIONAL_Z;
906 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
907 break;
908 case ir_binop_nequal:
909 case ir_binop_any_nequal: /* same as nequal for scalars */
910 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
911 inst->conditional_mod = BRW_CONDITIONAL_NZ;
912 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
913 break;
914
915 case ir_binop_logic_xor:
916 emit(fs_inst(BRW_OPCODE_XOR, this->result, op[0], op[1]));
917 break;
918
919 case ir_binop_logic_or:
920 emit(fs_inst(BRW_OPCODE_OR, this->result, op[0], op[1]));
921 break;
922
923 case ir_binop_logic_and:
924 emit(fs_inst(BRW_OPCODE_AND, this->result, op[0], op[1]));
925 break;
926
927 case ir_binop_dot:
928 case ir_unop_any:
929 assert(!"not reached: should be handled by brw_fs_channel_expressions");
930 break;
931
932 case ir_unop_noise:
933 assert(!"not reached: should be handled by lower_noise");
934 break;
935
936 case ir_unop_sqrt:
937 emit_math(FS_OPCODE_SQRT, this->result, op[0]);
938 break;
939
940 case ir_unop_rsq:
941 emit_math(FS_OPCODE_RSQ, this->result, op[0]);
942 break;
943
944 case ir_unop_i2f:
945 case ir_unop_b2f:
946 case ir_unop_b2i:
947 case ir_unop_f2i:
948 emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0]));
949 break;
950 case ir_unop_f2b:
951 case ir_unop_i2b:
952 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], fs_reg(0.0f)));
953 inst->conditional_mod = BRW_CONDITIONAL_NZ;
954 inst = emit(fs_inst(BRW_OPCODE_AND, this->result,
955 this->result, fs_reg(1)));
956 break;
957
958 case ir_unop_trunc:
959 emit(fs_inst(BRW_OPCODE_RNDZ, this->result, op[0]));
960 break;
961 case ir_unop_ceil:
962 op[0].negate = !op[0].negate;
963 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
964 this->result.negate = true;
965 break;
966 case ir_unop_floor:
967 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
968 break;
969 case ir_unop_fract:
970 inst = emit(fs_inst(BRW_OPCODE_FRC, this->result, op[0]));
971 break;
972 case ir_unop_round_even:
973 emit(fs_inst(BRW_OPCODE_RNDE, this->result, op[0]));
974 break;
975
976 case ir_binop_min:
977 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
978 inst->conditional_mod = BRW_CONDITIONAL_L;
979
980 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1]));
981 inst->predicated = true;
982 break;
983 case ir_binop_max:
984 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
985 inst->conditional_mod = BRW_CONDITIONAL_G;
986
987 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1]));
988 inst->predicated = true;
989 break;
990
991 case ir_binop_pow:
992 emit_math(FS_OPCODE_POW, this->result, op[0], op[1]);
993 break;
994
995 case ir_unop_bit_not:
996 inst = emit(fs_inst(BRW_OPCODE_NOT, this->result, op[0]));
997 break;
998 case ir_binop_bit_and:
999 inst = emit(fs_inst(BRW_OPCODE_AND, this->result, op[0], op[1]));
1000 break;
1001 case ir_binop_bit_xor:
1002 inst = emit(fs_inst(BRW_OPCODE_XOR, this->result, op[0], op[1]));
1003 break;
1004 case ir_binop_bit_or:
1005 inst = emit(fs_inst(BRW_OPCODE_OR, this->result, op[0], op[1]));
1006 break;
1007
1008 case ir_unop_u2f:
1009 case ir_binop_lshift:
1010 case ir_binop_rshift:
1011 assert(!"GLSL 1.30 features unsupported");
1012 break;
1013 }
1014 }
1015
1016 void
1017 fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r,
1018 const glsl_type *type, bool predicated)
1019 {
1020 switch (type->base_type) {
1021 case GLSL_TYPE_FLOAT:
1022 case GLSL_TYPE_UINT:
1023 case GLSL_TYPE_INT:
1024 case GLSL_TYPE_BOOL:
1025 for (unsigned int i = 0; i < type->components(); i++) {
1026 l.type = brw_type_for_base_type(type);
1027 r.type = brw_type_for_base_type(type);
1028
1029 fs_inst *inst = emit(fs_inst(BRW_OPCODE_MOV, l, r));
1030 inst->predicated = predicated;
1031
1032 l.reg_offset++;
1033 r.reg_offset++;
1034 }
1035 break;
1036 case GLSL_TYPE_ARRAY:
1037 for (unsigned int i = 0; i < type->length; i++) {
1038 emit_assignment_writes(l, r, type->fields.array, predicated);
1039 }
1040 break;
1041
1042 case GLSL_TYPE_STRUCT:
1043 for (unsigned int i = 0; i < type->length; i++) {
1044 emit_assignment_writes(l, r, type->fields.structure[i].type,
1045 predicated);
1046 }
1047 break;
1048
1049 case GLSL_TYPE_SAMPLER:
1050 break;
1051
1052 default:
1053 assert(!"not reached");
1054 break;
1055 }
1056 }
1057
1058 void
1059 fs_visitor::visit(ir_assignment *ir)
1060 {
1061 struct fs_reg l, r;
1062 fs_inst *inst;
1063
1064 /* FINISHME: arrays on the lhs */
1065 ir->lhs->accept(this);
1066 l = this->result;
1067
1068 ir->rhs->accept(this);
1069 r = this->result;
1070
1071 assert(l.file != BAD_FILE);
1072 assert(r.file != BAD_FILE);
1073
1074 if (ir->condition) {
1075 emit_bool_to_cond_code(ir->condition);
1076 }
1077
1078 if (ir->lhs->type->is_scalar() ||
1079 ir->lhs->type->is_vector()) {
1080 for (int i = 0; i < ir->lhs->type->vector_elements; i++) {
1081 if (ir->write_mask & (1 << i)) {
1082 inst = emit(fs_inst(BRW_OPCODE_MOV, l, r));
1083 if (ir->condition)
1084 inst->predicated = true;
1085 r.reg_offset++;
1086 }
1087 l.reg_offset++;
1088 }
1089 } else {
1090 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL);
1091 }
1092 }
1093
1094 fs_inst *
1095 fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate)
1096 {
1097 int mlen;
1098 int base_mrf = 1;
1099 bool simd16 = false;
1100 fs_reg orig_dst;
1101
1102 /* g0 header. */
1103 mlen = 1;
1104
1105 if (ir->shadow_comparitor) {
1106 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1107 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i),
1108 coordinate));
1109 coordinate.reg_offset++;
1110 }
1111 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1112 mlen += 3;
1113
1114 if (ir->op == ir_tex) {
1115 /* There's no plain shadow compare message, so we use shadow
1116 * compare with a bias of 0.0.
1117 */
1118 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1119 fs_reg(0.0f)));
1120 mlen++;
1121 } else if (ir->op == ir_txb) {
1122 ir->lod_info.bias->accept(this);
1123 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1124 this->result));
1125 mlen++;
1126 } else {
1127 assert(ir->op == ir_txl);
1128 ir->lod_info.lod->accept(this);
1129 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1130 this->result));
1131 mlen++;
1132 }
1133
1134 ir->shadow_comparitor->accept(this);
1135 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1136 mlen++;
1137 } else if (ir->op == ir_tex) {
1138 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1139 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i),
1140 coordinate));
1141 coordinate.reg_offset++;
1142 }
1143 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1144 mlen += 3;
1145 } else {
1146 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1147 * instructions. We'll need to do SIMD16 here.
1148 */
1149 assert(ir->op == ir_txb || ir->op == ir_txl);
1150
1151 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1152 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2),
1153 coordinate));
1154 coordinate.reg_offset++;
1155 }
1156
1157 /* lod/bias appears after u/v/r. */
1158 mlen += 6;
1159
1160 if (ir->op == ir_txb) {
1161 ir->lod_info.bias->accept(this);
1162 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1163 this->result));
1164 mlen++;
1165 } else {
1166 ir->lod_info.lod->accept(this);
1167 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1168 this->result));
1169 mlen++;
1170 }
1171
1172 /* The unused upper half. */
1173 mlen++;
1174
1175 /* Now, since we're doing simd16, the return is 2 interleaved
1176 * vec4s where the odd-indexed ones are junk. We'll need to move
1177 * this weirdness around to the expected layout.
1178 */
1179 simd16 = true;
1180 orig_dst = dst;
1181 dst = fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type,
1182 2));
1183 dst.type = BRW_REGISTER_TYPE_F;
1184 }
1185
1186 fs_inst *inst = NULL;
1187 switch (ir->op) {
1188 case ir_tex:
1189 inst = emit(fs_inst(FS_OPCODE_TEX, dst));
1190 break;
1191 case ir_txb:
1192 inst = emit(fs_inst(FS_OPCODE_TXB, dst));
1193 break;
1194 case ir_txl:
1195 inst = emit(fs_inst(FS_OPCODE_TXL, dst));
1196 break;
1197 case ir_txd:
1198 case ir_txf:
1199 assert(!"GLSL 1.30 features unsupported");
1200 break;
1201 }
1202 inst->base_mrf = base_mrf;
1203 inst->mlen = mlen;
1204
1205 if (simd16) {
1206 for (int i = 0; i < 4; i++) {
1207 emit(fs_inst(BRW_OPCODE_MOV, orig_dst, dst));
1208 orig_dst.reg_offset++;
1209 dst.reg_offset += 2;
1210 }
1211 }
1212
1213 return inst;
1214 }
1215
1216 fs_inst *
1217 fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate)
1218 {
1219 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1220 * optional parameters like shadow comparitor or LOD bias. If
1221 * optional parameters aren't present, those base slots are
1222 * optional and don't need to be included in the message.
1223 *
1224 * We don't fill in the unnecessary slots regardless, which may
1225 * look surprising in the disassembly.
1226 */
1227 int mlen = 1; /* g0 header always present. */
1228 int base_mrf = 1;
1229
1230 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1231 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i),
1232 coordinate));
1233 coordinate.reg_offset++;
1234 }
1235 mlen += ir->coordinate->type->vector_elements;
1236
1237 if (ir->shadow_comparitor) {
1238 mlen = MAX2(mlen, 5);
1239
1240 ir->shadow_comparitor->accept(this);
1241 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1242 mlen++;
1243 }
1244
1245 fs_inst *inst = NULL;
1246 switch (ir->op) {
1247 case ir_tex:
1248 inst = emit(fs_inst(FS_OPCODE_TEX, dst));
1249 break;
1250 case ir_txb:
1251 ir->lod_info.bias->accept(this);
1252 mlen = MAX2(mlen, 5);
1253 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1254 mlen++;
1255
1256 inst = emit(fs_inst(FS_OPCODE_TXB, dst));
1257 break;
1258 case ir_txl:
1259 ir->lod_info.lod->accept(this);
1260 mlen = MAX2(mlen, 5);
1261 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1262 mlen++;
1263
1264 inst = emit(fs_inst(FS_OPCODE_TXL, dst));
1265 break;
1266 case ir_txd:
1267 case ir_txf:
1268 assert(!"GLSL 1.30 features unsupported");
1269 break;
1270 }
1271 inst->base_mrf = base_mrf;
1272 inst->mlen = mlen;
1273
1274 return inst;
1275 }
1276
1277 void
1278 fs_visitor::visit(ir_texture *ir)
1279 {
1280 int sampler;
1281 fs_inst *inst = NULL;
1282
1283 ir->coordinate->accept(this);
1284 fs_reg coordinate = this->result;
1285
1286 /* Should be lowered by do_lower_texture_projection */
1287 assert(!ir->projector);
1288
1289 sampler = _mesa_get_sampler_uniform_value(ir->sampler,
1290 ctx->Shader.CurrentFragmentProgram,
1291 &brw->fragment_program->Base);
1292 sampler = c->fp->program.Base.SamplerUnits[sampler];
1293
1294 /* The 965 requires the EU to do the normalization of GL rectangle
1295 * texture coordinates. We use the program parameter state
1296 * tracking to get the scaling factor.
1297 */
1298 if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) {
1299 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters;
1300 int tokens[STATE_LENGTH] = {
1301 STATE_INTERNAL,
1302 STATE_TEXRECT_SCALE,
1303 sampler,
1304 0,
1305 0
1306 };
1307
1308 c->prog_data.param_convert[c->prog_data.nr_params] =
1309 PARAM_NO_CONVERT;
1310 c->prog_data.param_convert[c->prog_data.nr_params + 1] =
1311 PARAM_NO_CONVERT;
1312
1313 fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params);
1314 fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1);
1315 GLuint index = _mesa_add_state_reference(params,
1316 (gl_state_index *)tokens);
1317 float *vec_values = this->fp->Base.Parameters->ParameterValues[index];
1318
1319 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[0];
1320 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[1];
1321
1322 fs_reg dst = fs_reg(this, ir->coordinate->type);
1323 fs_reg src = coordinate;
1324 coordinate = dst;
1325
1326 emit(fs_inst(BRW_OPCODE_MUL, dst, src, scale_x));
1327 dst.reg_offset++;
1328 src.reg_offset++;
1329 emit(fs_inst(BRW_OPCODE_MUL, dst, src, scale_y));
1330 }
1331
1332 /* Writemasking doesn't eliminate channels on SIMD8 texture
1333 * samples, so don't worry about them.
1334 */
1335 fs_reg dst = fs_reg(this, glsl_type::vec4_type);
1336
1337 if (intel->gen < 5) {
1338 inst = emit_texture_gen4(ir, dst, coordinate);
1339 } else {
1340 inst = emit_texture_gen5(ir, dst, coordinate);
1341 }
1342
1343 inst->sampler = sampler;
1344
1345 this->result = dst;
1346
1347 if (ir->shadow_comparitor)
1348 inst->shadow_compare = true;
1349
1350 if (c->key.tex_swizzles[inst->sampler] != SWIZZLE_NOOP) {
1351 fs_reg swizzle_dst = fs_reg(this, glsl_type::vec4_type);
1352
1353 for (int i = 0; i < 4; i++) {
1354 int swiz = GET_SWZ(c->key.tex_swizzles[inst->sampler], i);
1355 fs_reg l = swizzle_dst;
1356 l.reg_offset += i;
1357
1358 if (swiz == SWIZZLE_ZERO) {
1359 emit(fs_inst(BRW_OPCODE_MOV, l, fs_reg(0.0f)));
1360 } else if (swiz == SWIZZLE_ONE) {
1361 emit(fs_inst(BRW_OPCODE_MOV, l, fs_reg(1.0f)));
1362 } else {
1363 fs_reg r = dst;
1364 r.reg_offset += GET_SWZ(c->key.tex_swizzles[inst->sampler], i);
1365 emit(fs_inst(BRW_OPCODE_MOV, l, r));
1366 }
1367 }
1368 this->result = swizzle_dst;
1369 }
1370 }
1371
1372 void
1373 fs_visitor::visit(ir_swizzle *ir)
1374 {
1375 ir->val->accept(this);
1376 fs_reg val = this->result;
1377
1378 if (ir->type->vector_elements == 1) {
1379 this->result.reg_offset += ir->mask.x;
1380 return;
1381 }
1382
1383 fs_reg result = fs_reg(this, ir->type);
1384 this->result = result;
1385
1386 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1387 fs_reg channel = val;
1388 int swiz = 0;
1389
1390 switch (i) {
1391 case 0:
1392 swiz = ir->mask.x;
1393 break;
1394 case 1:
1395 swiz = ir->mask.y;
1396 break;
1397 case 2:
1398 swiz = ir->mask.z;
1399 break;
1400 case 3:
1401 swiz = ir->mask.w;
1402 break;
1403 }
1404
1405 channel.reg_offset += swiz;
1406 emit(fs_inst(BRW_OPCODE_MOV, result, channel));
1407 result.reg_offset++;
1408 }
1409 }
1410
1411 void
1412 fs_visitor::visit(ir_discard *ir)
1413 {
1414 fs_reg temp = fs_reg(this, glsl_type::uint_type);
1415
1416 assert(ir->condition == NULL); /* FINISHME */
1417
1418 emit(fs_inst(FS_OPCODE_DISCARD_NOT, temp, reg_null_d));
1419 emit(fs_inst(FS_OPCODE_DISCARD_AND, reg_null_d, temp));
1420 kill_emitted = true;
1421 }
1422
1423 void
1424 fs_visitor::visit(ir_constant *ir)
1425 {
1426 fs_reg reg(this, ir->type);
1427 this->result = reg;
1428
1429 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1430 switch (ir->type->base_type) {
1431 case GLSL_TYPE_FLOAT:
1432 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.f[i])));
1433 break;
1434 case GLSL_TYPE_UINT:
1435 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.u[i])));
1436 break;
1437 case GLSL_TYPE_INT:
1438 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.i[i])));
1439 break;
1440 case GLSL_TYPE_BOOL:
1441 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg((int)ir->value.b[i])));
1442 break;
1443 default:
1444 assert(!"Non-float/uint/int/bool constant");
1445 }
1446 reg.reg_offset++;
1447 }
1448 }
1449
1450 void
1451 fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir)
1452 {
1453 ir_expression *expr = ir->as_expression();
1454
1455 if (expr) {
1456 fs_reg op[2];
1457 fs_inst *inst;
1458
1459 assert(expr->get_num_operands() <= 2);
1460 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1461 assert(expr->operands[i]->type->is_scalar());
1462
1463 expr->operands[i]->accept(this);
1464 op[i] = this->result;
1465 }
1466
1467 switch (expr->operation) {
1468 case ir_unop_logic_not:
1469 inst = emit(fs_inst(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)));
1470 inst->conditional_mod = BRW_CONDITIONAL_Z;
1471 break;
1472
1473 case ir_binop_logic_xor:
1474 inst = emit(fs_inst(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]));
1475 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1476 break;
1477
1478 case ir_binop_logic_or:
1479 inst = emit(fs_inst(BRW_OPCODE_OR, reg_null_d, op[0], op[1]));
1480 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1481 break;
1482
1483 case ir_binop_logic_and:
1484 inst = emit(fs_inst(BRW_OPCODE_AND, reg_null_d, op[0], op[1]));
1485 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1486 break;
1487
1488 case ir_unop_f2b:
1489 if (intel->gen >= 6) {
1490 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d,
1491 op[0], fs_reg(0.0f)));
1492 } else {
1493 inst = emit(fs_inst(BRW_OPCODE_MOV, reg_null_d, op[0]));
1494 }
1495 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1496 break;
1497
1498 case ir_unop_i2b:
1499 if (intel->gen >= 6) {
1500 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)));
1501 } else {
1502 inst = emit(fs_inst(BRW_OPCODE_MOV, reg_null_d, op[0]));
1503 }
1504 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1505 break;
1506
1507 case ir_binop_greater:
1508 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
1509 inst->conditional_mod = BRW_CONDITIONAL_G;
1510 break;
1511 case ir_binop_gequal:
1512 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
1513 inst->conditional_mod = BRW_CONDITIONAL_GE;
1514 break;
1515 case ir_binop_less:
1516 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
1517 inst->conditional_mod = BRW_CONDITIONAL_L;
1518 break;
1519 case ir_binop_lequal:
1520 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
1521 inst->conditional_mod = BRW_CONDITIONAL_LE;
1522 break;
1523 case ir_binop_equal:
1524 case ir_binop_all_equal:
1525 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
1526 inst->conditional_mod = BRW_CONDITIONAL_Z;
1527 break;
1528 case ir_binop_nequal:
1529 case ir_binop_any_nequal:
1530 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
1531 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1532 break;
1533 default:
1534 assert(!"not reached");
1535 this->fail = true;
1536 break;
1537 }
1538 return;
1539 }
1540
1541 ir->accept(this);
1542
1543 if (intel->gen >= 6) {
1544 fs_inst *inst = emit(fs_inst(BRW_OPCODE_AND, reg_null_d,
1545 this->result, fs_reg(1)));
1546 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1547 } else {
1548 fs_inst *inst = emit(fs_inst(BRW_OPCODE_MOV, reg_null_d, this->result));
1549 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1550 }
1551 }
1552
1553 /**
1554 * Emit a gen6 IF statement with the comparison folded into the IF
1555 * instruction.
1556 */
1557 void
1558 fs_visitor::emit_if_gen6(ir_if *ir)
1559 {
1560 ir_expression *expr = ir->condition->as_expression();
1561
1562 if (expr) {
1563 fs_reg op[2];
1564 fs_inst *inst;
1565 fs_reg temp;
1566
1567 assert(expr->get_num_operands() <= 2);
1568 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1569 assert(expr->operands[i]->type->is_scalar());
1570
1571 expr->operands[i]->accept(this);
1572 op[i] = this->result;
1573 }
1574
1575 switch (expr->operation) {
1576 case ir_unop_logic_not:
1577 inst = emit(fs_inst(BRW_OPCODE_IF, temp, op[0], fs_reg(1)));
1578 inst->conditional_mod = BRW_CONDITIONAL_Z;
1579 return;
1580
1581 case ir_binop_logic_xor:
1582 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], op[1]));
1583 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1584 return;
1585
1586 case ir_binop_logic_or:
1587 temp = fs_reg(this, glsl_type::bool_type);
1588 emit(fs_inst(BRW_OPCODE_OR, temp, op[0], op[1]));
1589 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)));
1590 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1591 return;
1592
1593 case ir_binop_logic_and:
1594 temp = fs_reg(this, glsl_type::bool_type);
1595 emit(fs_inst(BRW_OPCODE_AND, temp, op[0], op[1]));
1596 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)));
1597 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1598 return;
1599
1600 case ir_unop_f2b:
1601 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)));
1602 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1603 return;
1604
1605 case ir_unop_i2b:
1606 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)));
1607 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1608 return;
1609
1610 case ir_binop_greater:
1611 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], op[1]));
1612 inst->conditional_mod = BRW_CONDITIONAL_G;
1613 return;
1614 case ir_binop_gequal:
1615 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], op[1]));
1616 inst->conditional_mod = BRW_CONDITIONAL_GE;
1617 return;
1618 case ir_binop_less:
1619 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], op[1]));
1620 inst->conditional_mod = BRW_CONDITIONAL_L;
1621 return;
1622 case ir_binop_lequal:
1623 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], op[1]));
1624 inst->conditional_mod = BRW_CONDITIONAL_LE;
1625 return;
1626 case ir_binop_equal:
1627 case ir_binop_all_equal:
1628 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], op[1]));
1629 inst->conditional_mod = BRW_CONDITIONAL_Z;
1630 return;
1631 case ir_binop_nequal:
1632 case ir_binop_any_nequal:
1633 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], op[1]));
1634 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1635 return;
1636 default:
1637 assert(!"not reached");
1638 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)));
1639 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1640 this->fail = true;
1641 return;
1642 }
1643 return;
1644 }
1645
1646 ir->condition->accept(this);
1647
1648 fs_inst *inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)));
1649 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1650 }
1651
1652 void
1653 fs_visitor::visit(ir_if *ir)
1654 {
1655 fs_inst *inst;
1656
1657 /* Don't point the annotation at the if statement, because then it plus
1658 * the then and else blocks get printed.
1659 */
1660 this->base_ir = ir->condition;
1661
1662 if (intel->gen >= 6) {
1663 emit_if_gen6(ir);
1664 } else {
1665 emit_bool_to_cond_code(ir->condition);
1666
1667 inst = emit(fs_inst(BRW_OPCODE_IF));
1668 inst->predicated = true;
1669 }
1670
1671 foreach_iter(exec_list_iterator, iter, ir->then_instructions) {
1672 ir_instruction *ir = (ir_instruction *)iter.get();
1673 this->base_ir = ir;
1674
1675 ir->accept(this);
1676 }
1677
1678 if (!ir->else_instructions.is_empty()) {
1679 emit(fs_inst(BRW_OPCODE_ELSE));
1680
1681 foreach_iter(exec_list_iterator, iter, ir->else_instructions) {
1682 ir_instruction *ir = (ir_instruction *)iter.get();
1683 this->base_ir = ir;
1684
1685 ir->accept(this);
1686 }
1687 }
1688
1689 emit(fs_inst(BRW_OPCODE_ENDIF));
1690 }
1691
1692 void
1693 fs_visitor::visit(ir_loop *ir)
1694 {
1695 fs_reg counter = reg_undef;
1696
1697 if (ir->counter) {
1698 this->base_ir = ir->counter;
1699 ir->counter->accept(this);
1700 counter = *(variable_storage(ir->counter));
1701
1702 if (ir->from) {
1703 this->base_ir = ir->from;
1704 ir->from->accept(this);
1705
1706 emit(fs_inst(BRW_OPCODE_MOV, counter, this->result));
1707 }
1708 }
1709
1710 emit(fs_inst(BRW_OPCODE_DO));
1711
1712 if (ir->to) {
1713 this->base_ir = ir->to;
1714 ir->to->accept(this);
1715
1716 fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d,
1717 counter, this->result));
1718 switch (ir->cmp) {
1719 case ir_binop_equal:
1720 inst->conditional_mod = BRW_CONDITIONAL_Z;
1721 break;
1722 case ir_binop_nequal:
1723 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1724 break;
1725 case ir_binop_gequal:
1726 inst->conditional_mod = BRW_CONDITIONAL_GE;
1727 break;
1728 case ir_binop_lequal:
1729 inst->conditional_mod = BRW_CONDITIONAL_LE;
1730 break;
1731 case ir_binop_greater:
1732 inst->conditional_mod = BRW_CONDITIONAL_G;
1733 break;
1734 case ir_binop_less:
1735 inst->conditional_mod = BRW_CONDITIONAL_L;
1736 break;
1737 default:
1738 assert(!"not reached: unknown loop condition");
1739 this->fail = true;
1740 break;
1741 }
1742
1743 inst = emit(fs_inst(BRW_OPCODE_BREAK));
1744 inst->predicated = true;
1745 }
1746
1747 foreach_iter(exec_list_iterator, iter, ir->body_instructions) {
1748 ir_instruction *ir = (ir_instruction *)iter.get();
1749
1750 this->base_ir = ir;
1751 ir->accept(this);
1752 }
1753
1754 if (ir->increment) {
1755 this->base_ir = ir->increment;
1756 ir->increment->accept(this);
1757 emit(fs_inst(BRW_OPCODE_ADD, counter, counter, this->result));
1758 }
1759
1760 emit(fs_inst(BRW_OPCODE_WHILE));
1761 }
1762
1763 void
1764 fs_visitor::visit(ir_loop_jump *ir)
1765 {
1766 switch (ir->mode) {
1767 case ir_loop_jump::jump_break:
1768 emit(fs_inst(BRW_OPCODE_BREAK));
1769 break;
1770 case ir_loop_jump::jump_continue:
1771 emit(fs_inst(BRW_OPCODE_CONTINUE));
1772 break;
1773 }
1774 }
1775
1776 void
1777 fs_visitor::visit(ir_call *ir)
1778 {
1779 assert(!"FINISHME");
1780 }
1781
1782 void
1783 fs_visitor::visit(ir_return *ir)
1784 {
1785 assert(!"FINISHME");
1786 }
1787
1788 void
1789 fs_visitor::visit(ir_function *ir)
1790 {
1791 /* Ignore function bodies other than main() -- we shouldn't see calls to
1792 * them since they should all be inlined before we get to ir_to_mesa.
1793 */
1794 if (strcmp(ir->name, "main") == 0) {
1795 const ir_function_signature *sig;
1796 exec_list empty;
1797
1798 sig = ir->matching_signature(&empty);
1799
1800 assert(sig);
1801
1802 foreach_iter(exec_list_iterator, iter, sig->body) {
1803 ir_instruction *ir = (ir_instruction *)iter.get();
1804 this->base_ir = ir;
1805
1806 ir->accept(this);
1807 }
1808 }
1809 }
1810
1811 void
1812 fs_visitor::visit(ir_function_signature *ir)
1813 {
1814 assert(!"not reached");
1815 (void)ir;
1816 }
1817
1818 fs_inst *
1819 fs_visitor::emit(fs_inst inst)
1820 {
1821 fs_inst *list_inst = new(mem_ctx) fs_inst;
1822 *list_inst = inst;
1823
1824 list_inst->annotation = this->current_annotation;
1825 list_inst->ir = this->base_ir;
1826
1827 this->instructions.push_tail(list_inst);
1828
1829 return list_inst;
1830 }
1831
1832 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1833 void
1834 fs_visitor::emit_dummy_fs()
1835 {
1836 /* Everyone's favorite color. */
1837 emit(fs_inst(BRW_OPCODE_MOV,
1838 fs_reg(MRF, 2),
1839 fs_reg(1.0f)));
1840 emit(fs_inst(BRW_OPCODE_MOV,
1841 fs_reg(MRF, 3),
1842 fs_reg(0.0f)));
1843 emit(fs_inst(BRW_OPCODE_MOV,
1844 fs_reg(MRF, 4),
1845 fs_reg(1.0f)));
1846 emit(fs_inst(BRW_OPCODE_MOV,
1847 fs_reg(MRF, 5),
1848 fs_reg(0.0f)));
1849
1850 fs_inst *write;
1851 write = emit(fs_inst(FS_OPCODE_FB_WRITE,
1852 fs_reg(0),
1853 fs_reg(0)));
1854 write->base_mrf = 0;
1855 }
1856
1857 /* The register location here is relative to the start of the URB
1858 * data. It will get adjusted to be a real location before
1859 * generate_code() time.
1860 */
1861 struct brw_reg
1862 fs_visitor::interp_reg(int location, int channel)
1863 {
1864 int regnr = urb_setup[location] * 2 + channel / 2;
1865 int stride = (channel & 1) * 4;
1866
1867 assert(urb_setup[location] != -1);
1868
1869 return brw_vec1_grf(regnr, stride);
1870 }
1871
1872 /** Emits the interpolation for the varying inputs. */
1873 void
1874 fs_visitor::emit_interpolation_setup_gen4()
1875 {
1876 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
1877
1878 this->current_annotation = "compute pixel centers";
1879 this->pixel_x = fs_reg(this, glsl_type::uint_type);
1880 this->pixel_y = fs_reg(this, glsl_type::uint_type);
1881 this->pixel_x.type = BRW_REGISTER_TYPE_UW;
1882 this->pixel_y.type = BRW_REGISTER_TYPE_UW;
1883 emit(fs_inst(BRW_OPCODE_ADD,
1884 this->pixel_x,
1885 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
1886 fs_reg(brw_imm_v(0x10101010))));
1887 emit(fs_inst(BRW_OPCODE_ADD,
1888 this->pixel_y,
1889 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
1890 fs_reg(brw_imm_v(0x11001100))));
1891
1892 this->current_annotation = "compute pixel deltas from v0";
1893 if (brw->has_pln) {
1894 this->delta_x = fs_reg(this, glsl_type::vec2_type);
1895 this->delta_y = this->delta_x;
1896 this->delta_y.reg_offset++;
1897 } else {
1898 this->delta_x = fs_reg(this, glsl_type::float_type);
1899 this->delta_y = fs_reg(this, glsl_type::float_type);
1900 }
1901 emit(fs_inst(BRW_OPCODE_ADD,
1902 this->delta_x,
1903 this->pixel_x,
1904 fs_reg(negate(brw_vec1_grf(1, 0)))));
1905 emit(fs_inst(BRW_OPCODE_ADD,
1906 this->delta_y,
1907 this->pixel_y,
1908 fs_reg(negate(brw_vec1_grf(1, 1)))));
1909
1910 this->current_annotation = "compute pos.w and 1/pos.w";
1911 /* Compute wpos.w. It's always in our setup, since it's needed to
1912 * interpolate the other attributes.
1913 */
1914 this->wpos_w = fs_reg(this, glsl_type::float_type);
1915 emit(fs_inst(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y,
1916 interp_reg(FRAG_ATTRIB_WPOS, 3)));
1917 /* Compute the pixel 1/W value from wpos.w. */
1918 this->pixel_w = fs_reg(this, glsl_type::float_type);
1919 emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w);
1920 this->current_annotation = NULL;
1921 }
1922
1923 /** Emits the interpolation for the varying inputs. */
1924 void
1925 fs_visitor::emit_interpolation_setup_gen6()
1926 {
1927 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
1928
1929 /* If the pixel centers end up used, the setup is the same as for gen4. */
1930 this->current_annotation = "compute pixel centers";
1931 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type);
1932 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type);
1933 int_pixel_x.type = BRW_REGISTER_TYPE_UW;
1934 int_pixel_y.type = BRW_REGISTER_TYPE_UW;
1935 emit(fs_inst(BRW_OPCODE_ADD,
1936 int_pixel_x,
1937 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
1938 fs_reg(brw_imm_v(0x10101010))));
1939 emit(fs_inst(BRW_OPCODE_ADD,
1940 int_pixel_y,
1941 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
1942 fs_reg(brw_imm_v(0x11001100))));
1943
1944 /* As of gen6, we can no longer mix float and int sources. We have
1945 * to turn the integer pixel centers into floats for their actual
1946 * use.
1947 */
1948 this->pixel_x = fs_reg(this, glsl_type::float_type);
1949 this->pixel_y = fs_reg(this, glsl_type::float_type);
1950 emit(fs_inst(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x));
1951 emit(fs_inst(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y));
1952
1953 this->current_annotation = "compute 1/pos.w";
1954 this->wpos_w = fs_reg(brw_vec8_grf(c->key.source_w_reg, 0));
1955 this->pixel_w = fs_reg(this, glsl_type::float_type);
1956 emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w);
1957
1958 this->delta_x = fs_reg(brw_vec8_grf(2, 0));
1959 this->delta_y = fs_reg(brw_vec8_grf(3, 0));
1960
1961 this->current_annotation = NULL;
1962 }
1963
1964 void
1965 fs_visitor::emit_fb_writes()
1966 {
1967 this->current_annotation = "FB write header";
1968 GLboolean header_present = GL_TRUE;
1969 int nr = 0;
1970
1971 if (intel->gen >= 6 &&
1972 !this->kill_emitted &&
1973 c->key.nr_color_regions == 1) {
1974 header_present = false;
1975 }
1976
1977 if (header_present) {
1978 /* m0, m1 header */
1979 nr += 2;
1980 }
1981
1982 if (c->key.aa_dest_stencil_reg) {
1983 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
1984 fs_reg(brw_vec8_grf(c->key.aa_dest_stencil_reg, 0))));
1985 }
1986
1987 /* Reserve space for color. It'll be filled in per MRT below. */
1988 int color_mrf = nr;
1989 nr += 4;
1990
1991 if (c->key.source_depth_to_render_target) {
1992 if (c->key.computes_depth) {
1993 /* Hand over gl_FragDepth. */
1994 assert(this->frag_depth);
1995 fs_reg depth = *(variable_storage(this->frag_depth));
1996
1997 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++), depth));
1998 } else {
1999 /* Pass through the payload depth. */
2000 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
2001 fs_reg(brw_vec8_grf(c->key.source_depth_reg, 0))));
2002 }
2003 }
2004
2005 if (c->key.dest_depth_reg) {
2006 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
2007 fs_reg(brw_vec8_grf(c->key.dest_depth_reg, 0))));
2008 }
2009
2010 fs_reg color = reg_undef;
2011 if (this->frag_color)
2012 color = *(variable_storage(this->frag_color));
2013 else if (this->frag_data) {
2014 color = *(variable_storage(this->frag_data));
2015 color.type = BRW_REGISTER_TYPE_F;
2016 }
2017
2018 for (int target = 0; target < c->key.nr_color_regions; target++) {
2019 this->current_annotation = talloc_asprintf(this->mem_ctx,
2020 "FB write target %d",
2021 target);
2022 if (this->frag_color || this->frag_data) {
2023 for (int i = 0; i < 4; i++) {
2024 emit(fs_inst(BRW_OPCODE_MOV,
2025 fs_reg(MRF, color_mrf + i),
2026 color));
2027 color.reg_offset++;
2028 }
2029 }
2030
2031 if (this->frag_color)
2032 color.reg_offset -= 4;
2033
2034 fs_inst *inst = emit(fs_inst(FS_OPCODE_FB_WRITE,
2035 reg_undef, reg_undef));
2036 inst->target = target;
2037 inst->base_mrf = 0;
2038 inst->mlen = nr;
2039 if (target == c->key.nr_color_regions - 1)
2040 inst->eot = true;
2041 inst->header_present = header_present;
2042 }
2043
2044 if (c->key.nr_color_regions == 0) {
2045 fs_inst *inst = emit(fs_inst(FS_OPCODE_FB_WRITE,
2046 reg_undef, reg_undef));
2047 inst->base_mrf = 0;
2048 inst->mlen = nr;
2049 inst->eot = true;
2050 inst->header_present = header_present;
2051 }
2052
2053 this->current_annotation = NULL;
2054 }
2055
2056 void
2057 fs_visitor::generate_fb_write(fs_inst *inst)
2058 {
2059 GLboolean eot = inst->eot;
2060 struct brw_reg implied_header;
2061
2062 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
2063 * move, here's g1.
2064 */
2065 brw_push_insn_state(p);
2066 brw_set_mask_control(p, BRW_MASK_DISABLE);
2067 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
2068
2069 if (inst->header_present) {
2070 if (intel->gen >= 6) {
2071 brw_MOV(p,
2072 brw_message_reg(inst->base_mrf),
2073 brw_vec8_grf(0, 0));
2074
2075 if (inst->target > 0) {
2076 /* Set the render target index for choosing BLEND_STATE. */
2077 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 0, 2),
2078 BRW_REGISTER_TYPE_UD),
2079 brw_imm_ud(inst->target));
2080 }
2081
2082 /* Clear viewport index, render target array index. */
2083 brw_AND(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 0, 0),
2084 BRW_REGISTER_TYPE_UD),
2085 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD),
2086 brw_imm_ud(0xf7ff));
2087
2088 implied_header = brw_null_reg();
2089 } else {
2090 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
2091 }
2092
2093 brw_MOV(p,
2094 brw_message_reg(inst->base_mrf + 1),
2095 brw_vec8_grf(1, 0));
2096 } else {
2097 implied_header = brw_null_reg();
2098 }
2099
2100 brw_pop_insn_state(p);
2101
2102 brw_fb_WRITE(p,
2103 8, /* dispatch_width */
2104 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW),
2105 inst->base_mrf,
2106 implied_header,
2107 inst->target,
2108 inst->mlen,
2109 0,
2110 eot);
2111 }
2112
2113 void
2114 fs_visitor::generate_linterp(fs_inst *inst,
2115 struct brw_reg dst, struct brw_reg *src)
2116 {
2117 struct brw_reg delta_x = src[0];
2118 struct brw_reg delta_y = src[1];
2119 struct brw_reg interp = src[2];
2120
2121 if (brw->has_pln &&
2122 delta_y.nr == delta_x.nr + 1 &&
2123 (intel->gen >= 6 || (delta_x.nr & 1) == 0)) {
2124 brw_PLN(p, dst, interp, delta_x);
2125 } else {
2126 brw_LINE(p, brw_null_reg(), interp, delta_x);
2127 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
2128 }
2129 }
2130
2131 void
2132 fs_visitor::generate_math(fs_inst *inst,
2133 struct brw_reg dst, struct brw_reg *src)
2134 {
2135 int op;
2136
2137 switch (inst->opcode) {
2138 case FS_OPCODE_RCP:
2139 op = BRW_MATH_FUNCTION_INV;
2140 break;
2141 case FS_OPCODE_RSQ:
2142 op = BRW_MATH_FUNCTION_RSQ;
2143 break;
2144 case FS_OPCODE_SQRT:
2145 op = BRW_MATH_FUNCTION_SQRT;
2146 break;
2147 case FS_OPCODE_EXP2:
2148 op = BRW_MATH_FUNCTION_EXP;
2149 break;
2150 case FS_OPCODE_LOG2:
2151 op = BRW_MATH_FUNCTION_LOG;
2152 break;
2153 case FS_OPCODE_POW:
2154 op = BRW_MATH_FUNCTION_POW;
2155 break;
2156 case FS_OPCODE_SIN:
2157 op = BRW_MATH_FUNCTION_SIN;
2158 break;
2159 case FS_OPCODE_COS:
2160 op = BRW_MATH_FUNCTION_COS;
2161 break;
2162 default:
2163 assert(!"not reached: unknown math function");
2164 op = 0;
2165 break;
2166 }
2167
2168 if (intel->gen >= 6) {
2169 assert(inst->mlen == 0);
2170
2171 if (inst->opcode == FS_OPCODE_POW) {
2172 brw_math2(p, dst, op, src[0], src[1]);
2173 } else {
2174 brw_math(p, dst,
2175 op,
2176 inst->saturate ? BRW_MATH_SATURATE_SATURATE :
2177 BRW_MATH_SATURATE_NONE,
2178 0, src[0],
2179 BRW_MATH_DATA_VECTOR,
2180 BRW_MATH_PRECISION_FULL);
2181 }
2182 } else {
2183 assert(inst->mlen >= 1);
2184
2185 brw_math(p, dst,
2186 op,
2187 inst->saturate ? BRW_MATH_SATURATE_SATURATE :
2188 BRW_MATH_SATURATE_NONE,
2189 inst->base_mrf, src[0],
2190 BRW_MATH_DATA_VECTOR,
2191 BRW_MATH_PRECISION_FULL);
2192 }
2193 }
2194
2195 void
2196 fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst)
2197 {
2198 int msg_type = -1;
2199 int rlen = 4;
2200 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
2201
2202 if (intel->gen >= 5) {
2203 switch (inst->opcode) {
2204 case FS_OPCODE_TEX:
2205 if (inst->shadow_compare) {
2206 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5;
2207 } else {
2208 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_GEN5;
2209 }
2210 break;
2211 case FS_OPCODE_TXB:
2212 if (inst->shadow_compare) {
2213 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5;
2214 } else {
2215 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5;
2216 }
2217 break;
2218 }
2219 } else {
2220 switch (inst->opcode) {
2221 case FS_OPCODE_TEX:
2222 /* Note that G45 and older determines shadow compare and dispatch width
2223 * from message length for most messages.
2224 */
2225 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
2226 if (inst->shadow_compare) {
2227 assert(inst->mlen == 6);
2228 } else {
2229 assert(inst->mlen <= 4);
2230 }
2231 break;
2232 case FS_OPCODE_TXB:
2233 if (inst->shadow_compare) {
2234 assert(inst->mlen == 6);
2235 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
2236 } else {
2237 assert(inst->mlen == 9);
2238 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
2239 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
2240 }
2241 break;
2242 }
2243 }
2244 assert(msg_type != -1);
2245
2246 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
2247 rlen = 8;
2248 dst = vec16(dst);
2249 }
2250
2251 brw_SAMPLE(p,
2252 retype(dst, BRW_REGISTER_TYPE_UW),
2253 inst->base_mrf,
2254 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
2255 SURF_INDEX_TEXTURE(inst->sampler),
2256 inst->sampler,
2257 WRITEMASK_XYZW,
2258 msg_type,
2259 rlen,
2260 inst->mlen,
2261 0,
2262 1,
2263 simd_mode);
2264 }
2265
2266
2267 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2268 * looking like:
2269 *
2270 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2271 *
2272 * and we're trying to produce:
2273 *
2274 * DDX DDY
2275 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2276 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2277 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2278 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2279 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2280 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2281 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2282 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2283 *
2284 * and add another set of two more subspans if in 16-pixel dispatch mode.
2285 *
2286 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2287 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2288 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2289 * between each other. We could probably do it like ddx and swizzle the right
2290 * order later, but bail for now and just produce
2291 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2292 */
2293 void
2294 fs_visitor::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
2295 {
2296 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
2297 BRW_REGISTER_TYPE_F,
2298 BRW_VERTICAL_STRIDE_2,
2299 BRW_WIDTH_2,
2300 BRW_HORIZONTAL_STRIDE_0,
2301 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
2302 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
2303 BRW_REGISTER_TYPE_F,
2304 BRW_VERTICAL_STRIDE_2,
2305 BRW_WIDTH_2,
2306 BRW_HORIZONTAL_STRIDE_0,
2307 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
2308 brw_ADD(p, dst, src0, negate(src1));
2309 }
2310
2311 void
2312 fs_visitor::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
2313 {
2314 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
2315 BRW_REGISTER_TYPE_F,
2316 BRW_VERTICAL_STRIDE_4,
2317 BRW_WIDTH_4,
2318 BRW_HORIZONTAL_STRIDE_0,
2319 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
2320 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
2321 BRW_REGISTER_TYPE_F,
2322 BRW_VERTICAL_STRIDE_4,
2323 BRW_WIDTH_4,
2324 BRW_HORIZONTAL_STRIDE_0,
2325 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
2326 brw_ADD(p, dst, src0, negate(src1));
2327 }
2328
2329 void
2330 fs_visitor::generate_discard_not(fs_inst *inst, struct brw_reg mask)
2331 {
2332 if (intel->gen >= 6) {
2333 /* Gen6 no longer has the mask reg for us to just read the
2334 * active channels from. However, cmp updates just the channels
2335 * of the flag reg that are enabled, so we can get at the
2336 * channel enables that way. In this step, make a reg of ones
2337 * we'll compare to.
2338 */
2339 brw_MOV(p, mask, brw_imm_ud(1));
2340 } else {
2341 brw_push_insn_state(p);
2342 brw_set_mask_control(p, BRW_MASK_DISABLE);
2343 brw_NOT(p, mask, brw_mask_reg(1)); /* IMASK */
2344 brw_pop_insn_state(p);
2345 }
2346 }
2347
2348 void
2349 fs_visitor::generate_discard_and(fs_inst *inst, struct brw_reg mask)
2350 {
2351 if (intel->gen >= 6) {
2352 struct brw_reg f0 = brw_flag_reg();
2353 struct brw_reg g1 = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
2354
2355 brw_push_insn_state(p);
2356 brw_set_mask_control(p, BRW_MASK_DISABLE);
2357 brw_MOV(p, f0, brw_imm_uw(0xffff)); /* inactive channels undiscarded */
2358 brw_pop_insn_state(p);
2359
2360 brw_CMP(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
2361 BRW_CONDITIONAL_Z, mask, brw_imm_ud(0)); /* active channels fail test */
2362 /* Undo CMP's whacking of predication*/
2363 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
2364
2365 brw_push_insn_state(p);
2366 brw_set_mask_control(p, BRW_MASK_DISABLE);
2367 brw_AND(p, g1, f0, g1);
2368 brw_pop_insn_state(p);
2369 } else {
2370 struct brw_reg g0 = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
2371
2372 mask = brw_uw1_reg(mask.file, mask.nr, 0);
2373
2374 brw_push_insn_state(p);
2375 brw_set_mask_control(p, BRW_MASK_DISABLE);
2376 brw_AND(p, g0, mask, g0);
2377 brw_pop_insn_state(p);
2378 }
2379 }
2380
2381 void
2382 fs_visitor::generate_spill(fs_inst *inst, struct brw_reg src)
2383 {
2384 assert(inst->mlen != 0);
2385
2386 brw_MOV(p,
2387 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
2388 retype(src, BRW_REGISTER_TYPE_UD));
2389 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf), 1,
2390 inst->offset);
2391 }
2392
2393 void
2394 fs_visitor::generate_unspill(fs_inst *inst, struct brw_reg dst)
2395 {
2396 assert(inst->mlen != 0);
2397
2398 /* Clear any post destination dependencies that would be ignored by
2399 * the block read. See the B-Spec for pre-gen5 send instruction.
2400 *
2401 * This could use a better solution, since texture sampling and
2402 * math reads could potentially run into it as well -- anywhere
2403 * that we have a SEND with a destination that is a register that
2404 * was written but not read within the last N instructions (what's
2405 * N? unsure). This is rare because of dead code elimination, but
2406 * not impossible.
2407 */
2408 if (intel->gen == 4 && !intel->is_g4x)
2409 brw_MOV(p, brw_null_reg(), dst);
2410
2411 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf), 1,
2412 inst->offset);
2413
2414 if (intel->gen == 4 && !intel->is_g4x) {
2415 /* gen4 errata: destination from a send can't be used as a
2416 * destination until it's been read. Just read it so we don't
2417 * have to worry.
2418 */
2419 brw_MOV(p, brw_null_reg(), dst);
2420 }
2421 }
2422
2423
2424 void
2425 fs_visitor::generate_pull_constant_load(fs_inst *inst, struct brw_reg dst)
2426 {
2427 assert(inst->mlen != 0);
2428
2429 /* Clear any post destination dependencies that would be ignored by
2430 * the block read. See the B-Spec for pre-gen5 send instruction.
2431 *
2432 * This could use a better solution, since texture sampling and
2433 * math reads could potentially run into it as well -- anywhere
2434 * that we have a SEND with a destination that is a register that
2435 * was written but not read within the last N instructions (what's
2436 * N? unsure). This is rare because of dead code elimination, but
2437 * not impossible.
2438 */
2439 if (intel->gen == 4 && !intel->is_g4x)
2440 brw_MOV(p, brw_null_reg(), dst);
2441
2442 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
2443 inst->offset, SURF_INDEX_FRAG_CONST_BUFFER);
2444
2445 if (intel->gen == 4 && !intel->is_g4x) {
2446 /* gen4 errata: destination from a send can't be used as a
2447 * destination until it's been read. Just read it so we don't
2448 * have to worry.
2449 */
2450 brw_MOV(p, brw_null_reg(), dst);
2451 }
2452 }
2453
2454 void
2455 fs_visitor::assign_curb_setup()
2456 {
2457 c->prog_data.first_curbe_grf = c->key.nr_payload_regs;
2458 c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8;
2459
2460 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2461 foreach_iter(exec_list_iterator, iter, this->instructions) {
2462 fs_inst *inst = (fs_inst *)iter.get();
2463
2464 for (unsigned int i = 0; i < 3; i++) {
2465 if (inst->src[i].file == UNIFORM) {
2466 int constant_nr = inst->src[i].hw_reg + inst->src[i].reg_offset;
2467 struct brw_reg brw_reg = brw_vec1_grf(c->prog_data.first_curbe_grf +
2468 constant_nr / 8,
2469 constant_nr % 8);
2470
2471 inst->src[i].file = FIXED_HW_REG;
2472 inst->src[i].fixed_hw_reg = retype(brw_reg, inst->src[i].type);
2473 }
2474 }
2475 }
2476 }
2477
2478 void
2479 fs_visitor::calculate_urb_setup()
2480 {
2481 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
2482 urb_setup[i] = -1;
2483 }
2484
2485 int urb_next = 0;
2486 /* Figure out where each of the incoming setup attributes lands. */
2487 if (intel->gen >= 6) {
2488 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
2489 if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(i)) {
2490 urb_setup[i] = urb_next++;
2491 }
2492 }
2493 } else {
2494 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2495 for (unsigned int i = 0; i < VERT_RESULT_MAX; i++) {
2496 if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) {
2497 int fp_index;
2498
2499 if (i >= VERT_RESULT_VAR0)
2500 fp_index = i - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
2501 else if (i <= VERT_RESULT_TEX7)
2502 fp_index = i;
2503 else
2504 fp_index = -1;
2505
2506 if (fp_index >= 0)
2507 urb_setup[fp_index] = urb_next++;
2508 }
2509 }
2510 }
2511
2512 /* Each attribute is 4 setup channels, each of which is half a reg. */
2513 c->prog_data.urb_read_length = urb_next * 2;
2514 }
2515
2516 void
2517 fs_visitor::assign_urb_setup()
2518 {
2519 int urb_start = c->prog_data.first_curbe_grf + c->prog_data.curb_read_length;
2520
2521 /* Offset all the urb_setup[] index by the actual position of the
2522 * setup regs, now that the location of the constants has been chosen.
2523 */
2524 foreach_iter(exec_list_iterator, iter, this->instructions) {
2525 fs_inst *inst = (fs_inst *)iter.get();
2526
2527 if (inst->opcode != FS_OPCODE_LINTERP)
2528 continue;
2529
2530 assert(inst->src[2].file == FIXED_HW_REG);
2531
2532 inst->src[2].fixed_hw_reg.nr += urb_start;
2533 }
2534
2535 this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length;
2536 }
2537
2538 /**
2539 * Split large virtual GRFs into separate components if we can.
2540 *
2541 * This is mostly duplicated with what brw_fs_vector_splitting does,
2542 * but that's really conservative because it's afraid of doing
2543 * splitting that doesn't result in real progress after the rest of
2544 * the optimization phases, which would cause infinite looping in
2545 * optimization. We can do it once here, safely. This also has the
2546 * opportunity to split interpolated values, or maybe even uniforms,
2547 * which we don't have at the IR level.
2548 *
2549 * We want to split, because virtual GRFs are what we register
2550 * allocate and spill (due to contiguousness requirements for some
2551 * instructions), and they're what we naturally generate in the
2552 * codegen process, but most virtual GRFs don't actually need to be
2553 * contiguous sets of GRFs. If we split, we'll end up with reduced
2554 * live intervals and better dead code elimination and coalescing.
2555 */
2556 void
2557 fs_visitor::split_virtual_grfs()
2558 {
2559 int num_vars = this->virtual_grf_next;
2560 bool split_grf[num_vars];
2561 int new_virtual_grf[num_vars];
2562
2563 /* Try to split anything > 0 sized. */
2564 for (int i = 0; i < num_vars; i++) {
2565 if (this->virtual_grf_sizes[i] != 1)
2566 split_grf[i] = true;
2567 else
2568 split_grf[i] = false;
2569 }
2570
2571 if (brw->has_pln) {
2572 /* PLN opcodes rely on the delta_xy being contiguous. */
2573 split_grf[this->delta_x.reg] = false;
2574 }
2575
2576 foreach_iter(exec_list_iterator, iter, this->instructions) {
2577 fs_inst *inst = (fs_inst *)iter.get();
2578
2579 /* Texturing produces 4 contiguous registers, so no splitting. */
2580 if ((inst->opcode == FS_OPCODE_TEX ||
2581 inst->opcode == FS_OPCODE_TXB ||
2582 inst->opcode == FS_OPCODE_TXL) &&
2583 inst->dst.file == GRF) {
2584 split_grf[inst->dst.reg] = false;
2585 }
2586 }
2587
2588 /* Allocate new space for split regs. Note that the virtual
2589 * numbers will be contiguous.
2590 */
2591 for (int i = 0; i < num_vars; i++) {
2592 if (split_grf[i]) {
2593 new_virtual_grf[i] = virtual_grf_alloc(1);
2594 for (int j = 2; j < this->virtual_grf_sizes[i]; j++) {
2595 int reg = virtual_grf_alloc(1);
2596 assert(reg == new_virtual_grf[i] + j - 1);
2597 (void) reg;
2598 }
2599 this->virtual_grf_sizes[i] = 1;
2600 }
2601 }
2602
2603 foreach_iter(exec_list_iterator, iter, this->instructions) {
2604 fs_inst *inst = (fs_inst *)iter.get();
2605
2606 if (inst->dst.file == GRF &&
2607 split_grf[inst->dst.reg] &&
2608 inst->dst.reg_offset != 0) {
2609 inst->dst.reg = (new_virtual_grf[inst->dst.reg] +
2610 inst->dst.reg_offset - 1);
2611 inst->dst.reg_offset = 0;
2612 }
2613 for (int i = 0; i < 3; i++) {
2614 if (inst->src[i].file == GRF &&
2615 split_grf[inst->src[i].reg] &&
2616 inst->src[i].reg_offset != 0) {
2617 inst->src[i].reg = (new_virtual_grf[inst->src[i].reg] +
2618 inst->src[i].reg_offset - 1);
2619 inst->src[i].reg_offset = 0;
2620 }
2621 }
2622 }
2623 }
2624
2625 /**
2626 * Choose accesses from the UNIFORM file to demote to using the pull
2627 * constant buffer.
2628 *
2629 * We allow a fragment shader to have more than the specified minimum
2630 * maximum number of fragment shader uniform components (64). If
2631 * there are too many of these, they'd fill up all of register space.
2632 * So, this will push some of them out to the pull constant buffer and
2633 * update the program to load them.
2634 */
2635 void
2636 fs_visitor::setup_pull_constants()
2637 {
2638 /* Only allow 16 registers (128 uniform components) as push constants. */
2639 unsigned int max_uniform_components = 16 * 8;
2640 if (c->prog_data.nr_params <= max_uniform_components)
2641 return;
2642
2643 /* Just demote the end of the list. We could probably do better
2644 * here, demoting things that are rarely used in the program first.
2645 */
2646 int pull_uniform_base = max_uniform_components;
2647 int pull_uniform_count = c->prog_data.nr_params - pull_uniform_base;
2648
2649 foreach_iter(exec_list_iterator, iter, this->instructions) {
2650 fs_inst *inst = (fs_inst *)iter.get();
2651
2652 for (int i = 0; i < 3; i++) {
2653 if (inst->src[i].file != UNIFORM)
2654 continue;
2655
2656 int uniform_nr = inst->src[i].hw_reg + inst->src[i].reg_offset;
2657 if (uniform_nr < pull_uniform_base)
2658 continue;
2659
2660 fs_reg dst = fs_reg(this, glsl_type::float_type);
2661 fs_inst *pull = new(mem_ctx) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD,
2662 dst);
2663 pull->offset = ((uniform_nr - pull_uniform_base) * 4) & ~15;
2664 pull->ir = inst->ir;
2665 pull->annotation = inst->annotation;
2666 pull->base_mrf = 14;
2667 pull->mlen = 1;
2668
2669 inst->insert_before(pull);
2670
2671 inst->src[i].file = GRF;
2672 inst->src[i].reg = dst.reg;
2673 inst->src[i].reg_offset = 0;
2674 inst->src[i].smear = (uniform_nr - pull_uniform_base) & 3;
2675 }
2676 }
2677
2678 for (int i = 0; i < pull_uniform_count; i++) {
2679 c->prog_data.pull_param[i] = c->prog_data.param[pull_uniform_base + i];
2680 c->prog_data.pull_param_convert[i] =
2681 c->prog_data.param_convert[pull_uniform_base + i];
2682 }
2683 c->prog_data.nr_params -= pull_uniform_count;
2684 c->prog_data.nr_pull_params = pull_uniform_count;
2685 }
2686
2687 void
2688 fs_visitor::calculate_live_intervals()
2689 {
2690 int num_vars = this->virtual_grf_next;
2691 int *def = talloc_array(mem_ctx, int, num_vars);
2692 int *use = talloc_array(mem_ctx, int, num_vars);
2693 int loop_depth = 0;
2694 int loop_start = 0;
2695 int bb_header_ip = 0;
2696
2697 for (int i = 0; i < num_vars; i++) {
2698 def[i] = 1 << 30;
2699 use[i] = -1;
2700 }
2701
2702 int ip = 0;
2703 foreach_iter(exec_list_iterator, iter, this->instructions) {
2704 fs_inst *inst = (fs_inst *)iter.get();
2705
2706 if (inst->opcode == BRW_OPCODE_DO) {
2707 if (loop_depth++ == 0)
2708 loop_start = ip;
2709 } else if (inst->opcode == BRW_OPCODE_WHILE) {
2710 loop_depth--;
2711
2712 if (loop_depth == 0) {
2713 /* Patches up the use of vars marked for being live across
2714 * the whole loop.
2715 */
2716 for (int i = 0; i < num_vars; i++) {
2717 if (use[i] == loop_start) {
2718 use[i] = ip;
2719 }
2720 }
2721 }
2722 } else {
2723 for (unsigned int i = 0; i < 3; i++) {
2724 if (inst->src[i].file == GRF && inst->src[i].reg != 0) {
2725 int reg = inst->src[i].reg;
2726
2727 if (!loop_depth || (this->virtual_grf_sizes[reg] == 1 &&
2728 def[reg] >= bb_header_ip)) {
2729 use[reg] = ip;
2730 } else {
2731 def[reg] = MIN2(loop_start, def[reg]);
2732 use[reg] = loop_start;
2733
2734 /* Nobody else is going to go smash our start to
2735 * later in the loop now, because def[reg] now
2736 * points before the bb header.
2737 */
2738 }
2739 }
2740 }
2741 if (inst->dst.file == GRF && inst->dst.reg != 0) {
2742 int reg = inst->dst.reg;
2743
2744 if (!loop_depth || (this->virtual_grf_sizes[reg] == 1 &&
2745 !inst->predicated)) {
2746 def[reg] = MIN2(def[reg], ip);
2747 } else {
2748 def[reg] = MIN2(def[reg], loop_start);
2749 }
2750 }
2751 }
2752
2753 ip++;
2754
2755 /* Set the basic block header IP. This is used for determining
2756 * if a complete def of single-register virtual GRF in a loop
2757 * dominates a use in the same basic block. It's a quick way to
2758 * reduce the live interval range of most register used in a
2759 * loop.
2760 */
2761 if (inst->opcode == BRW_OPCODE_IF ||
2762 inst->opcode == BRW_OPCODE_ELSE ||
2763 inst->opcode == BRW_OPCODE_ENDIF ||
2764 inst->opcode == BRW_OPCODE_DO ||
2765 inst->opcode == BRW_OPCODE_WHILE ||
2766 inst->opcode == BRW_OPCODE_BREAK ||
2767 inst->opcode == BRW_OPCODE_CONTINUE) {
2768 bb_header_ip = ip;
2769 }
2770 }
2771
2772 talloc_free(this->virtual_grf_def);
2773 talloc_free(this->virtual_grf_use);
2774 this->virtual_grf_def = def;
2775 this->virtual_grf_use = use;
2776 }
2777
2778 /**
2779 * Attempts to move immediate constants into the immediate
2780 * constant slot of following instructions.
2781 *
2782 * Immediate constants are a bit tricky -- they have to be in the last
2783 * operand slot, you can't do abs/negate on them,
2784 */
2785
2786 bool
2787 fs_visitor::propagate_constants()
2788 {
2789 bool progress = false;
2790
2791 foreach_iter(exec_list_iterator, iter, this->instructions) {
2792 fs_inst *inst = (fs_inst *)iter.get();
2793
2794 if (inst->opcode != BRW_OPCODE_MOV ||
2795 inst->predicated ||
2796 inst->dst.file != GRF || inst->src[0].file != IMM ||
2797 inst->dst.type != inst->src[0].type)
2798 continue;
2799
2800 /* Don't bother with cases where we should have had the
2801 * operation on the constant folded in GLSL already.
2802 */
2803 if (inst->saturate)
2804 continue;
2805
2806 /* Found a move of a constant to a GRF. Find anything else using the GRF
2807 * before it's written, and replace it with the constant if we can.
2808 */
2809 exec_list_iterator scan_iter = iter;
2810 scan_iter.next();
2811 for (; scan_iter.has_next(); scan_iter.next()) {
2812 fs_inst *scan_inst = (fs_inst *)scan_iter.get();
2813
2814 if (scan_inst->opcode == BRW_OPCODE_DO ||
2815 scan_inst->opcode == BRW_OPCODE_WHILE ||
2816 scan_inst->opcode == BRW_OPCODE_ELSE ||
2817 scan_inst->opcode == BRW_OPCODE_ENDIF) {
2818 break;
2819 }
2820
2821 for (int i = 2; i >= 0; i--) {
2822 if (scan_inst->src[i].file != GRF ||
2823 scan_inst->src[i].reg != inst->dst.reg ||
2824 scan_inst->src[i].reg_offset != inst->dst.reg_offset)
2825 continue;
2826
2827 /* Don't bother with cases where we should have had the
2828 * operation on the constant folded in GLSL already.
2829 */
2830 if (scan_inst->src[i].negate || scan_inst->src[i].abs)
2831 continue;
2832
2833 switch (scan_inst->opcode) {
2834 case BRW_OPCODE_MOV:
2835 scan_inst->src[i] = inst->src[0];
2836 progress = true;
2837 break;
2838
2839 case BRW_OPCODE_MUL:
2840 case BRW_OPCODE_ADD:
2841 if (i == 1) {
2842 scan_inst->src[i] = inst->src[0];
2843 progress = true;
2844 } else if (i == 0 && scan_inst->src[1].file != IMM) {
2845 /* Fit this constant in by commuting the operands */
2846 scan_inst->src[0] = scan_inst->src[1];
2847 scan_inst->src[1] = inst->src[0];
2848 }
2849 break;
2850 case BRW_OPCODE_CMP:
2851 case BRW_OPCODE_SEL:
2852 if (i == 1) {
2853 scan_inst->src[i] = inst->src[0];
2854 progress = true;
2855 }
2856 }
2857 }
2858
2859 if (scan_inst->dst.file == GRF &&
2860 scan_inst->dst.reg == inst->dst.reg &&
2861 (scan_inst->dst.reg_offset == inst->dst.reg_offset ||
2862 scan_inst->opcode == FS_OPCODE_TEX)) {
2863 break;
2864 }
2865 }
2866 }
2867
2868 return progress;
2869 }
2870 /**
2871 * Must be called after calculate_live_intervales() to remove unused
2872 * writes to registers -- register allocation will fail otherwise
2873 * because something deffed but not used won't be considered to
2874 * interfere with other regs.
2875 */
2876 bool
2877 fs_visitor::dead_code_eliminate()
2878 {
2879 bool progress = false;
2880 int pc = 0;
2881
2882 foreach_iter(exec_list_iterator, iter, this->instructions) {
2883 fs_inst *inst = (fs_inst *)iter.get();
2884
2885 if (inst->dst.file == GRF && this->virtual_grf_use[inst->dst.reg] <= pc) {
2886 inst->remove();
2887 progress = true;
2888 }
2889
2890 pc++;
2891 }
2892
2893 return progress;
2894 }
2895
2896 bool
2897 fs_visitor::register_coalesce()
2898 {
2899 bool progress = false;
2900
2901 foreach_iter(exec_list_iterator, iter, this->instructions) {
2902 fs_inst *inst = (fs_inst *)iter.get();
2903
2904 if (inst->opcode != BRW_OPCODE_MOV ||
2905 inst->predicated ||
2906 inst->saturate ||
2907 inst->dst.file != GRF || inst->src[0].file != GRF ||
2908 inst->dst.type != inst->src[0].type)
2909 continue;
2910
2911 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
2912 * them: check for no writes to either one until the exit of the
2913 * program.
2914 */
2915 bool interfered = false;
2916 exec_list_iterator scan_iter = iter;
2917 scan_iter.next();
2918 for (; scan_iter.has_next(); scan_iter.next()) {
2919 fs_inst *scan_inst = (fs_inst *)scan_iter.get();
2920
2921 if (scan_inst->opcode == BRW_OPCODE_DO ||
2922 scan_inst->opcode == BRW_OPCODE_WHILE ||
2923 scan_inst->opcode == BRW_OPCODE_ENDIF) {
2924 interfered = true;
2925 iter = scan_iter;
2926 break;
2927 }
2928
2929 if (scan_inst->dst.file == GRF) {
2930 if (scan_inst->dst.reg == inst->dst.reg &&
2931 (scan_inst->dst.reg_offset == inst->dst.reg_offset ||
2932 scan_inst->opcode == FS_OPCODE_TEX)) {
2933 interfered = true;
2934 break;
2935 }
2936 if (scan_inst->dst.reg == inst->src[0].reg &&
2937 (scan_inst->dst.reg_offset == inst->src[0].reg_offset ||
2938 scan_inst->opcode == FS_OPCODE_TEX)) {
2939 interfered = true;
2940 break;
2941 }
2942 }
2943 }
2944 if (interfered) {
2945 continue;
2946 }
2947
2948 /* Update live interval so we don't have to recalculate. */
2949 this->virtual_grf_use[inst->src[0].reg] = MAX2(virtual_grf_use[inst->src[0].reg],
2950 virtual_grf_use[inst->dst.reg]);
2951
2952 /* Rewrite the later usage to point at the source of the move to
2953 * be removed.
2954 */
2955 for (exec_list_iterator scan_iter = iter; scan_iter.has_next();
2956 scan_iter.next()) {
2957 fs_inst *scan_inst = (fs_inst *)scan_iter.get();
2958
2959 for (int i = 0; i < 3; i++) {
2960 if (scan_inst->src[i].file == GRF &&
2961 scan_inst->src[i].reg == inst->dst.reg &&
2962 scan_inst->src[i].reg_offset == inst->dst.reg_offset) {
2963 scan_inst->src[i].reg = inst->src[0].reg;
2964 scan_inst->src[i].reg_offset = inst->src[0].reg_offset;
2965 scan_inst->src[i].abs |= inst->src[0].abs;
2966 scan_inst->src[i].negate ^= inst->src[0].negate;
2967 scan_inst->src[i].smear = inst->src[0].smear;
2968 }
2969 }
2970 }
2971
2972 inst->remove();
2973 progress = true;
2974 }
2975
2976 return progress;
2977 }
2978
2979
2980 bool
2981 fs_visitor::compute_to_mrf()
2982 {
2983 bool progress = false;
2984 int next_ip = 0;
2985
2986 foreach_iter(exec_list_iterator, iter, this->instructions) {
2987 fs_inst *inst = (fs_inst *)iter.get();
2988
2989 int ip = next_ip;
2990 next_ip++;
2991
2992 if (inst->opcode != BRW_OPCODE_MOV ||
2993 inst->predicated ||
2994 inst->dst.file != MRF || inst->src[0].file != GRF ||
2995 inst->dst.type != inst->src[0].type ||
2996 inst->src[0].abs || inst->src[0].negate || inst->src[0].smear != -1)
2997 continue;
2998
2999 /* Can't compute-to-MRF this GRF if someone else was going to
3000 * read it later.
3001 */
3002 if (this->virtual_grf_use[inst->src[0].reg] > ip)
3003 continue;
3004
3005 /* Found a move of a GRF to a MRF. Let's see if we can go
3006 * rewrite the thing that made this GRF to write into the MRF.
3007 */
3008 fs_inst *scan_inst;
3009 for (scan_inst = (fs_inst *)inst->prev;
3010 scan_inst->prev != NULL;
3011 scan_inst = (fs_inst *)scan_inst->prev) {
3012 if (scan_inst->dst.file == GRF &&
3013 scan_inst->dst.reg == inst->src[0].reg) {
3014 /* Found the last thing to write our reg we want to turn
3015 * into a compute-to-MRF.
3016 */
3017
3018 if (scan_inst->opcode == FS_OPCODE_TEX) {
3019 /* texturing writes several continuous regs, so we can't
3020 * compute-to-mrf that.
3021 */
3022 break;
3023 }
3024
3025 /* If it's predicated, it (probably) didn't populate all
3026 * the channels.
3027 */
3028 if (scan_inst->predicated)
3029 break;
3030
3031 /* SEND instructions can't have MRF as a destination. */
3032 if (scan_inst->mlen)
3033 break;
3034
3035 if (intel->gen >= 6) {
3036 /* gen6 math instructions must have the destination be
3037 * GRF, so no compute-to-MRF for them.
3038 */
3039 if (scan_inst->opcode == FS_OPCODE_RCP ||
3040 scan_inst->opcode == FS_OPCODE_RSQ ||
3041 scan_inst->opcode == FS_OPCODE_SQRT ||
3042 scan_inst->opcode == FS_OPCODE_EXP2 ||
3043 scan_inst->opcode == FS_OPCODE_LOG2 ||
3044 scan_inst->opcode == FS_OPCODE_SIN ||
3045 scan_inst->opcode == FS_OPCODE_COS ||
3046 scan_inst->opcode == FS_OPCODE_POW) {
3047 break;
3048 }
3049 }
3050
3051 if (scan_inst->dst.reg_offset == inst->src[0].reg_offset) {
3052 /* Found the creator of our MRF's source value. */
3053 scan_inst->dst.file = MRF;
3054 scan_inst->dst.hw_reg = inst->dst.hw_reg;
3055 scan_inst->saturate |= inst->saturate;
3056 inst->remove();
3057 progress = true;
3058 }
3059 break;
3060 }
3061
3062 /* We don't handle flow control here. Most computation of
3063 * values that end up in MRFs are shortly before the MRF
3064 * write anyway.
3065 */
3066 if (scan_inst->opcode == BRW_OPCODE_DO ||
3067 scan_inst->opcode == BRW_OPCODE_WHILE ||
3068 scan_inst->opcode == BRW_OPCODE_ENDIF) {
3069 break;
3070 }
3071
3072 /* You can't read from an MRF, so if someone else reads our
3073 * MRF's source GRF that we wanted to rewrite, that stops us.
3074 */
3075 bool interfered = false;
3076 for (int i = 0; i < 3; i++) {
3077 if (scan_inst->src[i].file == GRF &&
3078 scan_inst->src[i].reg == inst->src[0].reg &&
3079 scan_inst->src[i].reg_offset == inst->src[0].reg_offset) {
3080 interfered = true;
3081 }
3082 }
3083 if (interfered)
3084 break;
3085
3086 if (scan_inst->dst.file == MRF &&
3087 scan_inst->dst.hw_reg == inst->dst.hw_reg) {
3088 /* Somebody else wrote our MRF here, so we can't can't
3089 * compute-to-MRF before that.
3090 */
3091 break;
3092 }
3093
3094 if (scan_inst->mlen > 0) {
3095 /* Found a SEND instruction, which means that there are
3096 * live values in MRFs from base_mrf to base_mrf +
3097 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3098 * above it.
3099 */
3100 if (inst->dst.hw_reg >= scan_inst->base_mrf &&
3101 inst->dst.hw_reg < scan_inst->base_mrf + scan_inst->mlen) {
3102 break;
3103 }
3104 }
3105 }
3106 }
3107
3108 return progress;
3109 }
3110
3111 /**
3112 * Walks through basic blocks, locking for repeated MRF writes and
3113 * removing the later ones.
3114 */
3115 bool
3116 fs_visitor::remove_duplicate_mrf_writes()
3117 {
3118 fs_inst *last_mrf_move[16];
3119 bool progress = false;
3120
3121 memset(last_mrf_move, 0, sizeof(last_mrf_move));
3122
3123 foreach_iter(exec_list_iterator, iter, this->instructions) {
3124 fs_inst *inst = (fs_inst *)iter.get();
3125
3126 switch (inst->opcode) {
3127 case BRW_OPCODE_DO:
3128 case BRW_OPCODE_WHILE:
3129 case BRW_OPCODE_IF:
3130 case BRW_OPCODE_ELSE:
3131 case BRW_OPCODE_ENDIF:
3132 memset(last_mrf_move, 0, sizeof(last_mrf_move));
3133 continue;
3134 default:
3135 break;
3136 }
3137
3138 if (inst->opcode == BRW_OPCODE_MOV &&
3139 inst->dst.file == MRF) {
3140 fs_inst *prev_inst = last_mrf_move[inst->dst.hw_reg];
3141 if (prev_inst && inst->equals(prev_inst)) {
3142 inst->remove();
3143 progress = true;
3144 continue;
3145 }
3146 }
3147
3148 /* Clear out the last-write records for MRFs that were overwritten. */
3149 if (inst->dst.file == MRF) {
3150 last_mrf_move[inst->dst.hw_reg] = NULL;
3151 }
3152
3153 if (inst->mlen > 0) {
3154 /* Found a SEND instruction, which will include two of fewer
3155 * implied MRF writes. We could do better here.
3156 */
3157 for (int i = 0; i < implied_mrf_writes(inst); i++) {
3158 last_mrf_move[inst->base_mrf + i] = NULL;
3159 }
3160 }
3161
3162 /* Clear out any MRF move records whose sources got overwritten. */
3163 if (inst->dst.file == GRF) {
3164 for (unsigned int i = 0; i < Elements(last_mrf_move); i++) {
3165 if (last_mrf_move[i] &&
3166 last_mrf_move[i]->src[0].reg == inst->dst.reg) {
3167 last_mrf_move[i] = NULL;
3168 }
3169 }
3170 }
3171
3172 if (inst->opcode == BRW_OPCODE_MOV &&
3173 inst->dst.file == MRF &&
3174 inst->src[0].file == GRF &&
3175 !inst->predicated) {
3176 last_mrf_move[inst->dst.hw_reg] = inst;
3177 }
3178 }
3179
3180 return progress;
3181 }
3182
3183 bool
3184 fs_visitor::virtual_grf_interferes(int a, int b)
3185 {
3186 int start = MAX2(this->virtual_grf_def[a], this->virtual_grf_def[b]);
3187 int end = MIN2(this->virtual_grf_use[a], this->virtual_grf_use[b]);
3188
3189 /* For dead code, just check if the def interferes with the other range. */
3190 if (this->virtual_grf_use[a] == -1) {
3191 return (this->virtual_grf_def[a] >= this->virtual_grf_def[b] &&
3192 this->virtual_grf_def[a] < this->virtual_grf_use[b]);
3193 }
3194 if (this->virtual_grf_use[b] == -1) {
3195 return (this->virtual_grf_def[b] >= this->virtual_grf_def[a] &&
3196 this->virtual_grf_def[b] < this->virtual_grf_use[a]);
3197 }
3198
3199 return start < end;
3200 }
3201
3202 static struct brw_reg brw_reg_from_fs_reg(fs_reg *reg)
3203 {
3204 struct brw_reg brw_reg;
3205
3206 switch (reg->file) {
3207 case GRF:
3208 case ARF:
3209 case MRF:
3210 if (reg->smear == -1) {
3211 brw_reg = brw_vec8_reg(reg->file,
3212 reg->hw_reg, 0);
3213 } else {
3214 brw_reg = brw_vec1_reg(reg->file,
3215 reg->hw_reg, reg->smear);
3216 }
3217 brw_reg = retype(brw_reg, reg->type);
3218 break;
3219 case IMM:
3220 switch (reg->type) {
3221 case BRW_REGISTER_TYPE_F:
3222 brw_reg = brw_imm_f(reg->imm.f);
3223 break;
3224 case BRW_REGISTER_TYPE_D:
3225 brw_reg = brw_imm_d(reg->imm.i);
3226 break;
3227 case BRW_REGISTER_TYPE_UD:
3228 brw_reg = brw_imm_ud(reg->imm.u);
3229 break;
3230 default:
3231 assert(!"not reached");
3232 break;
3233 }
3234 break;
3235 case FIXED_HW_REG:
3236 brw_reg = reg->fixed_hw_reg;
3237 break;
3238 case BAD_FILE:
3239 /* Probably unused. */
3240 brw_reg = brw_null_reg();
3241 break;
3242 case UNIFORM:
3243 assert(!"not reached");
3244 brw_reg = brw_null_reg();
3245 break;
3246 }
3247 if (reg->abs)
3248 brw_reg = brw_abs(brw_reg);
3249 if (reg->negate)
3250 brw_reg = negate(brw_reg);
3251
3252 return brw_reg;
3253 }
3254
3255 void
3256 fs_visitor::generate_code()
3257 {
3258 int last_native_inst = 0;
3259 struct brw_instruction *if_stack[16], *loop_stack[16];
3260 int if_stack_depth = 0, loop_stack_depth = 0;
3261 int if_depth_in_loop[16];
3262 const char *last_annotation_string = NULL;
3263 ir_instruction *last_annotation_ir = NULL;
3264
3265 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
3266 printf("Native code for fragment shader %d:\n",
3267 ctx->Shader.CurrentFragmentProgram->Name);
3268 }
3269
3270 if_depth_in_loop[loop_stack_depth] = 0;
3271
3272 memset(&if_stack, 0, sizeof(if_stack));
3273 foreach_iter(exec_list_iterator, iter, this->instructions) {
3274 fs_inst *inst = (fs_inst *)iter.get();
3275 struct brw_reg src[3], dst;
3276
3277 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
3278 if (last_annotation_ir != inst->ir) {
3279 last_annotation_ir = inst->ir;
3280 if (last_annotation_ir) {
3281 printf(" ");
3282 last_annotation_ir->print();
3283 printf("\n");
3284 }
3285 }
3286 if (last_annotation_string != inst->annotation) {
3287 last_annotation_string = inst->annotation;
3288 if (last_annotation_string)
3289 printf(" %s\n", last_annotation_string);
3290 }
3291 }
3292
3293 for (unsigned int i = 0; i < 3; i++) {
3294 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
3295 }
3296 dst = brw_reg_from_fs_reg(&inst->dst);
3297
3298 brw_set_conditionalmod(p, inst->conditional_mod);
3299 brw_set_predicate_control(p, inst->predicated);
3300 brw_set_saturate(p, inst->saturate);
3301
3302 switch (inst->opcode) {
3303 case BRW_OPCODE_MOV:
3304 brw_MOV(p, dst, src[0]);
3305 break;
3306 case BRW_OPCODE_ADD:
3307 brw_ADD(p, dst, src[0], src[1]);
3308 break;
3309 case BRW_OPCODE_MUL:
3310 brw_MUL(p, dst, src[0], src[1]);
3311 break;
3312
3313 case BRW_OPCODE_FRC:
3314 brw_FRC(p, dst, src[0]);
3315 break;
3316 case BRW_OPCODE_RNDD:
3317 brw_RNDD(p, dst, src[0]);
3318 break;
3319 case BRW_OPCODE_RNDE:
3320 brw_RNDE(p, dst, src[0]);
3321 break;
3322 case BRW_OPCODE_RNDZ:
3323 brw_RNDZ(p, dst, src[0]);
3324 break;
3325
3326 case BRW_OPCODE_AND:
3327 brw_AND(p, dst, src[0], src[1]);
3328 break;
3329 case BRW_OPCODE_OR:
3330 brw_OR(p, dst, src[0], src[1]);
3331 break;
3332 case BRW_OPCODE_XOR:
3333 brw_XOR(p, dst, src[0], src[1]);
3334 break;
3335 case BRW_OPCODE_NOT:
3336 brw_NOT(p, dst, src[0]);
3337 break;
3338 case BRW_OPCODE_ASR:
3339 brw_ASR(p, dst, src[0], src[1]);
3340 break;
3341 case BRW_OPCODE_SHR:
3342 brw_SHR(p, dst, src[0], src[1]);
3343 break;
3344 case BRW_OPCODE_SHL:
3345 brw_SHL(p, dst, src[0], src[1]);
3346 break;
3347
3348 case BRW_OPCODE_CMP:
3349 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
3350 break;
3351 case BRW_OPCODE_SEL:
3352 brw_SEL(p, dst, src[0], src[1]);
3353 break;
3354
3355 case BRW_OPCODE_IF:
3356 assert(if_stack_depth < 16);
3357 if (inst->src[0].file != BAD_FILE) {
3358 assert(intel->gen >= 6);
3359 if_stack[if_stack_depth] = brw_IF_gen6(p, inst->conditional_mod, src[0], src[1]);
3360 } else {
3361 if_stack[if_stack_depth] = brw_IF(p, BRW_EXECUTE_8);
3362 }
3363 if_depth_in_loop[loop_stack_depth]++;
3364 if_stack_depth++;
3365 break;
3366
3367 case BRW_OPCODE_ELSE:
3368 if_stack[if_stack_depth - 1] =
3369 brw_ELSE(p, if_stack[if_stack_depth - 1]);
3370 break;
3371 case BRW_OPCODE_ENDIF:
3372 if_stack_depth--;
3373 brw_ENDIF(p , if_stack[if_stack_depth]);
3374 if_depth_in_loop[loop_stack_depth]--;
3375 break;
3376
3377 case BRW_OPCODE_DO:
3378 /* FINISHME: We need to write the loop instruction support still. */
3379 if (intel->gen >= 6)
3380 this->fail = true;
3381
3382 loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
3383 if_depth_in_loop[loop_stack_depth] = 0;
3384 break;
3385
3386 case BRW_OPCODE_BREAK:
3387 brw_BREAK(p, if_depth_in_loop[loop_stack_depth]);
3388 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
3389 break;
3390 case BRW_OPCODE_CONTINUE:
3391 brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
3392 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
3393 break;
3394
3395 case BRW_OPCODE_WHILE: {
3396 struct brw_instruction *inst0, *inst1;
3397 GLuint br = 1;
3398
3399 if (intel->gen >= 5)
3400 br = 2;
3401
3402 assert(loop_stack_depth > 0);
3403 loop_stack_depth--;
3404 inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
3405 /* patch all the BREAK/CONT instructions from last BGNLOOP */
3406 while (inst0 > loop_stack[loop_stack_depth]) {
3407 inst0--;
3408 if (inst0->header.opcode == BRW_OPCODE_BREAK &&
3409 inst0->bits3.if_else.jump_count == 0) {
3410 inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
3411 }
3412 else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
3413 inst0->bits3.if_else.jump_count == 0) {
3414 inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
3415 }
3416 }
3417 }
3418 break;
3419
3420 case FS_OPCODE_RCP:
3421 case FS_OPCODE_RSQ:
3422 case FS_OPCODE_SQRT:
3423 case FS_OPCODE_EXP2:
3424 case FS_OPCODE_LOG2:
3425 case FS_OPCODE_POW:
3426 case FS_OPCODE_SIN:
3427 case FS_OPCODE_COS:
3428 generate_math(inst, dst, src);
3429 break;
3430 case FS_OPCODE_LINTERP:
3431 generate_linterp(inst, dst, src);
3432 break;
3433 case FS_OPCODE_TEX:
3434 case FS_OPCODE_TXB:
3435 case FS_OPCODE_TXL:
3436 generate_tex(inst, dst);
3437 break;
3438 case FS_OPCODE_DISCARD_NOT:
3439 generate_discard_not(inst, dst);
3440 break;
3441 case FS_OPCODE_DISCARD_AND:
3442 generate_discard_and(inst, src[0]);
3443 break;
3444 case FS_OPCODE_DDX:
3445 generate_ddx(inst, dst, src[0]);
3446 break;
3447 case FS_OPCODE_DDY:
3448 generate_ddy(inst, dst, src[0]);
3449 break;
3450
3451 case FS_OPCODE_SPILL:
3452 generate_spill(inst, src[0]);
3453 break;
3454
3455 case FS_OPCODE_UNSPILL:
3456 generate_unspill(inst, dst);
3457 break;
3458
3459 case FS_OPCODE_PULL_CONSTANT_LOAD:
3460 generate_pull_constant_load(inst, dst);
3461 break;
3462
3463 case FS_OPCODE_FB_WRITE:
3464 generate_fb_write(inst);
3465 break;
3466 default:
3467 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
3468 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
3469 brw_opcodes[inst->opcode].name);
3470 } else {
3471 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
3472 }
3473 this->fail = true;
3474 }
3475
3476 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
3477 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
3478 if (0) {
3479 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3480 ((uint32_t *)&p->store[i])[3],
3481 ((uint32_t *)&p->store[i])[2],
3482 ((uint32_t *)&p->store[i])[1],
3483 ((uint32_t *)&p->store[i])[0]);
3484 }
3485 brw_disasm(stdout, &p->store[i], intel->gen);
3486 }
3487 }
3488
3489 last_native_inst = p->nr_insn;
3490 }
3491 }
3492
3493 GLboolean
3494 brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c)
3495 {
3496 struct intel_context *intel = &brw->intel;
3497 struct gl_context *ctx = &intel->ctx;
3498 struct gl_shader_program *prog = ctx->Shader.CurrentFragmentProgram;
3499
3500 if (!prog)
3501 return GL_FALSE;
3502
3503 struct brw_shader *shader =
3504 (brw_shader *) prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
3505 if (!shader)
3506 return GL_FALSE;
3507
3508 /* We always use 8-wide mode, at least for now. For one, flow
3509 * control only works in 8-wide. Also, when we're fragment shader
3510 * bound, we're almost always under register pressure as well, so
3511 * 8-wide would save us from the performance cliff of spilling
3512 * regs.
3513 */
3514 c->dispatch_width = 8;
3515
3516 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
3517 printf("GLSL IR for native fragment shader %d:\n", prog->Name);
3518 _mesa_print_ir(shader->ir, NULL);
3519 printf("\n");
3520 }
3521
3522 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3523 */
3524 fs_visitor v(c, shader);
3525
3526 if (0) {
3527 v.emit_dummy_fs();
3528 } else {
3529 v.calculate_urb_setup();
3530 if (intel->gen < 6)
3531 v.emit_interpolation_setup_gen4();
3532 else
3533 v.emit_interpolation_setup_gen6();
3534
3535 /* Generate FS IR for main(). (the visitor only descends into
3536 * functions called "main").
3537 */
3538 foreach_iter(exec_list_iterator, iter, *shader->ir) {
3539 ir_instruction *ir = (ir_instruction *)iter.get();
3540 v.base_ir = ir;
3541 ir->accept(&v);
3542 }
3543
3544 v.emit_fb_writes();
3545
3546 v.split_virtual_grfs();
3547 v.setup_pull_constants();
3548
3549 v.assign_curb_setup();
3550 v.assign_urb_setup();
3551
3552 bool progress;
3553 do {
3554 progress = false;
3555
3556 progress = v.remove_duplicate_mrf_writes() || progress;
3557
3558 v.calculate_live_intervals();
3559 progress = v.propagate_constants() || progress;
3560 progress = v.register_coalesce() || progress;
3561 progress = v.compute_to_mrf() || progress;
3562 progress = v.dead_code_eliminate() || progress;
3563 } while (progress);
3564
3565 if (0) {
3566 /* Debug of register spilling: Go spill everything. */
3567 int virtual_grf_count = v.virtual_grf_next;
3568 for (int i = 1; i < virtual_grf_count; i++) {
3569 v.spill_reg(i);
3570 }
3571 v.calculate_live_intervals();
3572 }
3573
3574 if (0)
3575 v.assign_regs_trivial();
3576 else {
3577 while (!v.assign_regs()) {
3578 if (v.fail)
3579 break;
3580
3581 v.calculate_live_intervals();
3582 }
3583 }
3584 }
3585
3586 if (!v.fail)
3587 v.generate_code();
3588
3589 assert(!v.fail); /* FINISHME: Cleanly fail, tested at link time, etc. */
3590
3591 if (v.fail)
3592 return GL_FALSE;
3593
3594 c->prog_data.total_grf = v.grf_used;
3595
3596 return GL_TRUE;
3597 }