2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
31 /* Evil hack for using libdrm in a c++ compiler. */
34 #include "intel_bufmgr.h"
37 #include "main/macros.h"
38 #include "main/shaderobj.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/prog_optimize.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
48 #include "../glsl/glsl_types.h"
49 #include "../glsl/ir_optimization.h"
50 #include "../glsl/ir_print_visitor.h"
53 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
54 GRF
= BRW_GENERAL_REGISTER_FILE
,
55 MRF
= BRW_MESSAGE_REGISTER_FILE
,
56 IMM
= BRW_IMMEDIATE_VALUE
,
57 FIXED_HW_REG
, /* a struct brw_reg */
58 UNIFORM
, /* prog_data->params[hw_reg] */
63 FS_OPCODE_FB_WRITE
= 256,
77 static int using_new_fs
= -1;
80 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
82 struct brw_shader
*shader
;
84 shader
= talloc_zero(NULL
, struct brw_shader
);
86 shader
->base
.Type
= type
;
87 shader
->base
.Name
= name
;
88 _mesa_init_shader(ctx
, &shader
->base
);
94 struct gl_shader_program
*
95 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
97 struct brw_shader_program
*prog
;
98 prog
= talloc_zero(NULL
, struct brw_shader_program
);
100 prog
->base
.Name
= name
;
101 _mesa_init_shader_program(ctx
, &prog
->base
);
107 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
109 if (!_mesa_ir_compile_shader(ctx
, shader
))
116 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
118 if (using_new_fs
== -1)
119 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
121 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
122 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
124 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
125 void *mem_ctx
= talloc_new(NULL
);
129 talloc_free(shader
->ir
);
130 shader
->ir
= new(shader
) exec_list
;
131 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
133 do_mat_op_to_vec(shader
->ir
);
134 do_mod_to_fract(shader
->ir
);
135 do_div_to_mul_rcp(shader
->ir
);
136 do_sub_to_add_neg(shader
->ir
);
137 do_explog_to_explog2(shader
->ir
);
139 brw_do_channel_expressions(shader
->ir
);
140 brw_do_vector_splitting(shader
->ir
);
145 progress
= do_common_optimization(shader
->ir
, true) || progress
;
148 validate_ir_tree(shader
->ir
);
150 reparent_ir(shader
->ir
, shader
->ir
);
151 talloc_free(mem_ctx
);
155 if (!_mesa_ir_link_shader(ctx
, prog
))
162 type_size(const struct glsl_type
*type
)
164 unsigned int size
, i
;
166 switch (type
->base_type
) {
169 case GLSL_TYPE_FLOAT
:
171 return type
->components();
172 case GLSL_TYPE_ARRAY
:
173 /* FINISHME: uniform/varying arrays. */
174 return type_size(type
->fields
.array
) * type
->length
;
175 case GLSL_TYPE_STRUCT
:
177 for (i
= 0; i
< type
->length
; i
++) {
178 size
+= type_size(type
->fields
.structure
[i
].type
);
181 case GLSL_TYPE_SAMPLER
:
182 /* Samplers take up no register space, since they're baked in at
187 assert(!"not reached");
194 /* Callers of this talloc-based new need not call delete. It's
195 * easier to just talloc_free 'ctx' (or any of its ancestors). */
196 static void* operator new(size_t size
, void *ctx
)
200 node
= talloc_size(ctx
, size
);
201 assert(node
!= NULL
);
206 /** Generic unset register constructor. */
209 this->file
= BAD_FILE
;
211 this->reg_offset
= 0;
217 /** Immediate value constructor. */
223 this->type
= BRW_REGISTER_TYPE_F
;
229 /** Immediate value constructor. */
235 this->type
= BRW_REGISTER_TYPE_D
;
241 /** Immediate value constructor. */
247 this->type
= BRW_REGISTER_TYPE_UD
;
253 /** Fixed brw_reg Immediate value constructor. */
254 fs_reg(struct brw_reg fixed_hw_reg
)
256 this->file
= FIXED_HW_REG
;
257 this->fixed_hw_reg
= fixed_hw_reg
;
260 this->type
= fixed_hw_reg
.type
;
265 fs_reg(enum register_file file
, int hw_reg
);
266 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
268 /** Register file: ARF, GRF, MRF, IMM. */
269 enum register_file file
;
270 /** Abstract register number. 0 = fixed hw reg */
272 /** Offset within the abstract register. */
274 /** HW register number. Generally unset until register allocation. */
276 /** Register type. BRW_REGISTER_TYPE_* */
280 struct brw_reg fixed_hw_reg
;
282 /** Value for file == BRW_IMMMEDIATE_FILE */
290 static const fs_reg reg_undef
;
291 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
293 class fs_inst
: public exec_node
{
295 /* Callers of this talloc-based new need not call delete. It's
296 * easier to just talloc_free 'ctx' (or any of its ancestors). */
297 static void* operator new(size_t size
, void *ctx
)
301 node
= talloc_zero_size(ctx
, size
);
302 assert(node
!= NULL
);
309 this->opcode
= BRW_OPCODE_NOP
;
310 this->saturate
= false;
311 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
312 this->predicated
= false;
317 this->opcode
= opcode
;
318 this->saturate
= false;
319 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
320 this->predicated
= false;
323 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
)
325 this->opcode
= opcode
;
328 this->saturate
= false;
329 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
330 this->predicated
= false;
333 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
335 this->opcode
= opcode
;
339 this->saturate
= false;
340 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
341 this->predicated
= false;
344 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg src2
)
346 this->opcode
= opcode
;
351 this->saturate
= false;
352 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
353 this->predicated
= false;
356 int opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
361 int conditional_mod
; /**< BRW_CONDITIONAL_* */
364 * Annotation for the generated IR. One of the two can be set.
367 const char *annotation
;
371 class fs_visitor
: public ir_visitor
375 fs_visitor(struct brw_wm_compile
*c
, struct brw_shader
*shader
)
380 this->intel
= &brw
->intel
;
381 this->ctx
= &intel
->ctx
;
382 this->mem_ctx
= talloc_new(NULL
);
383 this->shader
= shader
;
385 this->next_abstract_grf
= 1;
386 this->variable_ht
= hash_table_ctor(0,
387 hash_table_pointer_hash
,
388 hash_table_pointer_compare
);
390 this->frag_color
= NULL
;
391 this->frag_data
= NULL
;
392 this->frag_depth
= NULL
;
393 this->first_non_payload_grf
= 0;
395 this->current_annotation
= NULL
;
396 this->annotation_string
= NULL
;
397 this->annotation_ir
= NULL
;
401 talloc_free(this->mem_ctx
);
402 hash_table_dtor(this->variable_ht
);
405 fs_reg
*variable_storage(ir_variable
*var
);
407 void visit(ir_variable
*ir
);
408 void visit(ir_assignment
*ir
);
409 void visit(ir_dereference_variable
*ir
);
410 void visit(ir_dereference_record
*ir
);
411 void visit(ir_dereference_array
*ir
);
412 void visit(ir_expression
*ir
);
413 void visit(ir_texture
*ir
);
414 void visit(ir_if
*ir
);
415 void visit(ir_constant
*ir
);
416 void visit(ir_swizzle
*ir
);
417 void visit(ir_return
*ir
);
418 void visit(ir_loop
*ir
);
419 void visit(ir_loop_jump
*ir
);
420 void visit(ir_discard
*ir
);
421 void visit(ir_call
*ir
);
422 void visit(ir_function
*ir
);
423 void visit(ir_function_signature
*ir
);
425 fs_inst
*emit(fs_inst inst
);
426 void assign_curb_setup();
427 void assign_urb_setup();
429 void generate_code();
430 void generate_fb_write(fs_inst
*inst
);
431 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
432 struct brw_reg
*src
);
433 void generate_math(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg
*src
);
435 void emit_dummy_fs();
436 void emit_interpolation();
437 void emit_pinterp(int location
);
438 void emit_fb_writes();
440 struct brw_reg
interp_reg(int location
, int channel
);
442 struct brw_context
*brw
;
443 struct intel_context
*intel
;
445 struct brw_wm_compile
*c
;
446 struct brw_compile
*p
;
447 struct brw_shader
*shader
;
449 exec_list instructions
;
450 int next_abstract_grf
;
451 struct hash_table
*variable_ht
;
452 ir_variable
*frag_color
, *frag_data
, *frag_depth
;
453 int first_non_payload_grf
;
455 /** @{ debug annotation info */
456 const char *current_annotation
;
457 ir_instruction
*base_ir
;
458 const char **annotation_string
;
459 ir_instruction
**annotation_ir
;
464 /* Result of last visit() method. */
472 fs_reg interp_attrs
[64];
478 /** Fixed HW reg constructor. */
479 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
483 this->reg_offset
= 0;
484 this->hw_reg
= hw_reg
;
485 this->type
= BRW_REGISTER_TYPE_F
;
490 /** Automatic reg constructor. */
491 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
494 this->reg
= v
->next_abstract_grf
;
495 this->reg_offset
= 0;
496 v
->next_abstract_grf
+= type_size(type
);
501 switch (type
->base_type
) {
502 case GLSL_TYPE_FLOAT
:
503 this->type
= BRW_REGISTER_TYPE_F
;
507 this->type
= BRW_REGISTER_TYPE_D
;
510 this->type
= BRW_REGISTER_TYPE_UD
;
513 assert(!"not reached");
514 this->type
= BRW_REGISTER_TYPE_F
;
520 fs_visitor::variable_storage(ir_variable
*var
)
522 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
526 fs_visitor::visit(ir_variable
*ir
)
530 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
531 this->frag_color
= ir
;
532 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
533 this->frag_data
= ir
;
534 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
535 this->frag_depth
= ir
;
536 assert(!"FINISHME: this hangs currently.");
539 if (ir
->mode
== ir_var_in
) {
540 reg
= &this->interp_attrs
[ir
->location
];
543 if (ir
->mode
== ir_var_uniform
) {
544 const float *vec_values
;
545 int param_index
= c
->prog_data
.nr_params
;
547 /* FINISHME: This is wildly incomplete. */
548 assert(ir
->type
->is_scalar() || ir
->type
->is_vector());
550 const struct gl_program
*fp
= &this->brw
->fragment_program
->Base
;
551 /* Our support for uniforms is piggy-backed on the struct
552 * gl_fragment_program, because that's where the values actually
553 * get stored, rather than in some global gl_shader_program uniform
556 vec_values
= fp
->Parameters
->ParameterValues
[ir
->location
];
557 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
558 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
561 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
565 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
567 hash_table_insert(this->variable_ht
, reg
, ir
);
571 fs_visitor::visit(ir_dereference_variable
*ir
)
573 fs_reg
*reg
= variable_storage(ir
->var
);
578 fs_visitor::visit(ir_dereference_record
*ir
)
584 fs_visitor::visit(ir_dereference_array
*ir
)
589 ir
->array
->accept(this);
590 index
= ir
->array_index
->as_constant();
592 if (ir
->type
->is_matrix()) {
593 element_size
= ir
->type
->vector_elements
;
595 element_size
= type_size(ir
->type
);
599 assert(this->result
.file
== UNIFORM
||
600 (this->result
.file
== GRF
&&
601 this->result
.reg
!= 0));
602 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
604 assert(!"FINISHME: non-constant matrix column");
609 fs_visitor::visit(ir_expression
*ir
)
611 unsigned int operand
;
616 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
617 ir
->operands
[operand
]->accept(this);
618 if (this->result
.file
== BAD_FILE
) {
620 printf("Failed to get tree for expression operand:\n");
621 ir
->operands
[operand
]->accept(&v
);
624 op
[operand
] = this->result
;
626 /* Matrix expression operands should have been broken down to vector
627 * operations already.
629 assert(!ir
->operands
[operand
]->type
->is_matrix());
630 /* And then those vector operands should have been broken down to scalar.
632 assert(!ir
->operands
[operand
]->type
->is_vector());
635 /* Storage for our result. If our result goes into an assignment, it will
636 * just get copy-propagated out, so no worries.
638 this->result
= fs_reg(this, ir
->type
);
640 switch (ir
->operation
) {
641 case ir_unop_logic_not
:
642 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
645 op
[0].negate
= ~op
[0].negate
;
646 this->result
= op
[0];
650 this->result
= op
[0];
653 temp
= fs_reg(this, ir
->type
);
655 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
656 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
658 inst
= emit(fs_inst(BRW_OPCODE_CMP
, temp
, op
[0], fs_reg(0.0f
)));
659 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
662 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, this->result
, temp
));
666 emit(fs_inst(FS_OPCODE_RCP
, this->result
, op
[0]));
670 emit(fs_inst(FS_OPCODE_EXP2
, this->result
, op
[0]));
673 emit(fs_inst(FS_OPCODE_LOG2
, this->result
, op
[0]));
677 assert(!"not reached: should be handled by ir_explog_to_explog2");
680 emit(fs_inst(FS_OPCODE_SIN
, this->result
, op
[0]));
683 emit(fs_inst(FS_OPCODE_COS
, this->result
, op
[0]));
687 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
690 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
694 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
697 assert(!"not reached: should be handled by ir_sub_to_add_neg");
701 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
704 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
707 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
711 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
712 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
714 case ir_binop_greater
:
715 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
716 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
718 case ir_binop_lequal
:
719 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
720 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
722 case ir_binop_gequal
:
723 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
724 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
727 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
728 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
730 case ir_binop_nequal
:
731 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
732 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
735 case ir_binop_logic_xor
:
736 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
739 case ir_binop_logic_or
:
740 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
743 case ir_binop_logic_and
:
744 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
750 assert(!"not reached: should be handled by brw_channel_expressions");
754 emit(fs_inst(FS_OPCODE_SQRT
, this->result
, op
[0]));
758 emit(fs_inst(FS_OPCODE_RSQ
, this->result
, op
[0]));
764 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
767 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
771 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
772 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
775 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
778 op
[0].negate
= ~op
[0].negate
;
779 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
780 this->result
.negate
= true;
783 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
786 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
790 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
791 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
793 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
794 inst
->predicated
= true;
797 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
798 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
800 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
801 inst
->predicated
= true;
805 inst
= emit(fs_inst(FS_OPCODE_POW
, this->result
, op
[0], op
[1]));
808 case ir_unop_bit_not
:
810 case ir_binop_lshift
:
811 case ir_binop_rshift
:
812 case ir_binop_bit_and
:
813 case ir_binop_bit_xor
:
814 case ir_binop_bit_or
:
815 assert(!"GLSL 1.30 features unsupported");
821 fs_visitor::visit(ir_assignment
*ir
)
828 /* FINISHME: arrays on the lhs */
829 ir
->lhs
->accept(this);
832 ir
->rhs
->accept(this);
835 /* FINISHME: This should really set to the correct maximal writemask for each
836 * FINISHME: component written (in the loops below). This case can only
837 * FINISHME: occur for matrices, arrays, and structures.
839 if (ir
->write_mask
== 0) {
840 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
841 write_mask
= WRITEMASK_XYZW
;
843 assert(ir
->lhs
->type
->is_vector() || ir
->lhs
->type
->is_scalar());
844 write_mask
= ir
->write_mask
;
847 assert(l
.file
!= BAD_FILE
);
848 assert(r
.file
!= BAD_FILE
);
851 /* Get the condition bool into the predicate. */
852 ir
->condition
->accept(this);
853 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, fs_reg(0)));
854 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
857 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
858 if (i
>= 4 || (write_mask
& (1 << i
))) {
859 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
861 inst
->predicated
= true;
869 fs_visitor::visit(ir_texture
*ir
)
875 fs_visitor::visit(ir_swizzle
*ir
)
877 ir
->val
->accept(this);
878 fs_reg val
= this->result
;
880 fs_reg result
= fs_reg(this, ir
->type
);
881 this->result
= result
;
883 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
884 fs_reg channel
= val
;
902 channel
.reg_offset
+= swiz
;
903 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
909 fs_visitor::visit(ir_discard
*ir
)
915 fs_visitor::visit(ir_constant
*ir
)
917 fs_reg
reg(this, ir
->type
);
920 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
921 switch (ir
->type
->base_type
) {
922 case GLSL_TYPE_FLOAT
:
923 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
926 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
929 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
932 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
935 assert(!"Non-float/uint/int/bool constant");
942 fs_visitor::visit(ir_if
*ir
)
946 /* Don't point the annotation at the if statement, because then it plus
947 * the then and else blocks get printed.
949 this->base_ir
= ir
->condition
;
951 /* Generate the condition into the condition code. */
952 ir
->condition
->accept(this);
953 inst
= emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(brw_null_reg()), this->result
));
954 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
956 inst
= emit(fs_inst(BRW_OPCODE_IF
));
957 inst
->predicated
= true;
959 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
960 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
966 if (!ir
->else_instructions
.is_empty()) {
967 emit(fs_inst(BRW_OPCODE_ELSE
));
969 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
970 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
977 emit(fs_inst(BRW_OPCODE_ENDIF
));
981 fs_visitor::visit(ir_loop
*ir
)
987 fs_visitor::visit(ir_loop_jump
*ir
)
993 fs_visitor::visit(ir_call
*ir
)
999 fs_visitor::visit(ir_return
*ir
)
1001 assert(!"FINISHME");
1005 fs_visitor::visit(ir_function
*ir
)
1007 /* Ignore function bodies other than main() -- we shouldn't see calls to
1008 * them since they should all be inlined before we get to ir_to_mesa.
1010 if (strcmp(ir
->name
, "main") == 0) {
1011 const ir_function_signature
*sig
;
1014 sig
= ir
->matching_signature(&empty
);
1018 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1019 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1028 fs_visitor::visit(ir_function_signature
*ir
)
1030 assert(!"not reached");
1035 fs_visitor::emit(fs_inst inst
)
1037 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1040 list_inst
->annotation
= this->current_annotation
;
1041 list_inst
->ir
= this->base_ir
;
1043 this->instructions
.push_tail(list_inst
);
1048 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1050 fs_visitor::emit_dummy_fs()
1052 /* Everyone's favorite color. */
1053 emit(fs_inst(BRW_OPCODE_MOV
,
1056 emit(fs_inst(BRW_OPCODE_MOV
,
1059 emit(fs_inst(BRW_OPCODE_MOV
,
1062 emit(fs_inst(BRW_OPCODE_MOV
,
1067 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1072 /* The register location here is relative to the start of the URB
1073 * data. It will get adjusted to be a real location before
1074 * generate_code() time.
1077 fs_visitor::interp_reg(int location
, int channel
)
1079 int regnr
= location
* 2 + channel
/ 2;
1080 int stride
= (channel
& 1) * 4;
1082 return brw_vec1_grf(regnr
, stride
);
1085 /** Emits the interpolation for the varying inputs. */
1087 fs_visitor::emit_interpolation()
1089 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1090 /* For now, the source regs for the setup URB data will be unset,
1091 * since we don't know until codegen how many push constants we'll
1092 * use, and therefore what the setup URB offset is.
1094 fs_reg src_reg
= reg_undef
;
1096 this->current_annotation
= "compute pixel centers";
1097 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1098 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1099 emit(fs_inst(BRW_OPCODE_ADD
,
1101 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1102 fs_reg(brw_imm_v(0x10101010))));
1103 emit(fs_inst(BRW_OPCODE_ADD
,
1105 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1106 fs_reg(brw_imm_v(0x11001100))));
1108 this->current_annotation
= "compute pixel deltas from v0";
1109 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1110 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1111 emit(fs_inst(BRW_OPCODE_ADD
,
1114 fs_reg(negate(brw_vec1_grf(1, 0)))));
1115 emit(fs_inst(BRW_OPCODE_ADD
,
1118 fs_reg(brw_vec1_grf(1, 1))));
1120 this->current_annotation
= "compute pos.w and 1/pos.w";
1121 /* Compute wpos. Unlike many other varying inputs, we usually need it
1122 * to produce 1/w, and the varying variable wouldn't show up.
1124 fs_reg wpos
= fs_reg(this, glsl_type::vec4_type
);
1125 this->interp_attrs
[FRAG_ATTRIB_WPOS
] = wpos
;
1126 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
)); /* FINISHME: ARB_fcc */
1128 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
)); /* FINISHME: ARB_fcc */
1130 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
1131 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
1133 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
1134 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1135 /* Compute the pixel W value from wpos.w. */
1136 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1137 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos
));
1139 /* FINISHME: gl_FrontFacing */
1141 foreach_iter(exec_list_iterator
, iter
, *this->shader
->ir
) {
1142 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1143 ir_variable
*var
= ir
->as_variable();
1148 if (var
->mode
!= ir_var_in
)
1151 /* If it's already set up (WPOS), skip. */
1152 if (var
->location
== 0)
1155 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1157 "(FRAG_ATTRIB[%d])",
1160 emit_pinterp(var
->location
);
1162 this->current_annotation
= NULL
;
1166 fs_visitor::emit_pinterp(int location
)
1168 fs_reg interp_attr
= fs_reg(this, glsl_type::vec4_type
);
1169 this->interp_attrs
[location
] = interp_attr
;
1171 for (unsigned int i
= 0; i
< 4; i
++) {
1172 struct brw_reg interp
= interp_reg(location
, i
);
1173 emit(fs_inst(FS_OPCODE_LINTERP
,
1178 interp_attr
.reg_offset
++;
1180 interp_attr
.reg_offset
-= 4;
1182 for (unsigned int i
= 0; i
< 4; i
++) {
1183 emit(fs_inst(BRW_OPCODE_MUL
,
1187 interp_attr
.reg_offset
++;
1192 fs_visitor::emit_fb_writes()
1194 this->current_annotation
= "FB write";
1196 assert(this->frag_color
|| !"FINISHME: MRT");
1197 fs_reg color
= *(variable_storage(this->frag_color
));
1199 for (int i
= 0; i
< 4; i
++) {
1200 emit(fs_inst(BRW_OPCODE_MOV
,
1206 emit(fs_inst(FS_OPCODE_FB_WRITE
,
1210 this->current_annotation
= NULL
;
1214 fs_visitor::generate_fb_write(fs_inst
*inst
)
1216 GLboolean eot
= 1; /* FINISHME: MRT */
1217 /* FINISHME: AADS */
1219 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1222 brw_push_insn_state(p
);
1223 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1224 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1227 brw_vec8_grf(1, 0));
1228 brw_pop_insn_state(p
);
1233 8, /* dispatch_width */
1234 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
1236 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
1237 0, /* FINISHME: MRT target */
1244 fs_visitor::generate_linterp(fs_inst
*inst
,
1245 struct brw_reg dst
, struct brw_reg
*src
)
1247 struct brw_reg delta_x
= src
[0];
1248 struct brw_reg delta_y
= src
[1];
1249 struct brw_reg interp
= src
[2];
1252 delta_y
.nr
== delta_x
.nr
+ 1 &&
1253 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
1254 brw_PLN(p
, dst
, interp
, delta_x
);
1256 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
1257 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
1262 fs_visitor::generate_math(fs_inst
*inst
,
1263 struct brw_reg dst
, struct brw_reg
*src
)
1267 switch (inst
->opcode
) {
1269 op
= BRW_MATH_FUNCTION_INV
;
1272 op
= BRW_MATH_FUNCTION_RSQ
;
1274 case FS_OPCODE_SQRT
:
1275 op
= BRW_MATH_FUNCTION_SQRT
;
1277 case FS_OPCODE_EXP2
:
1278 op
= BRW_MATH_FUNCTION_EXP
;
1280 case FS_OPCODE_LOG2
:
1281 op
= BRW_MATH_FUNCTION_LOG
;
1284 op
= BRW_MATH_FUNCTION_POW
;
1287 op
= BRW_MATH_FUNCTION_SIN
;
1290 op
= BRW_MATH_FUNCTION_COS
;
1293 assert(!"not reached: unknown math function");
1298 if (inst
->opcode
== FS_OPCODE_POW
) {
1299 brw_MOV(p
, brw_message_reg(3), src
[1]);
1304 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
1305 BRW_MATH_SATURATE_NONE
,
1307 BRW_MATH_DATA_VECTOR
,
1308 BRW_MATH_PRECISION_FULL
);
1312 trivial_assign_reg(int header_size
, fs_reg
*reg
)
1314 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
1315 reg
->hw_reg
= header_size
+ reg
->reg
- 1 + reg
->reg_offset
;
1321 fs_visitor::assign_curb_setup()
1323 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
1324 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
1326 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1327 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1328 fs_inst
*inst
= (fs_inst
*)iter
.get();
1330 for (unsigned int i
= 0; i
< 3; i
++) {
1331 if (inst
->src
[i
].file
== UNIFORM
) {
1332 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
1333 struct brw_reg brw_reg
;
1335 brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
1338 inst
->src
[i
] = fs_reg(brw_reg
);
1345 fs_visitor::assign_urb_setup()
1347 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
1348 int interp_reg_nr
[FRAG_ATTRIB_MAX
];
1350 c
->prog_data
.urb_read_length
= 0;
1352 /* Figure out where each of the incoming setup attributes lands. */
1353 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
1354 interp_reg_nr
[i
] = -1;
1356 if (i
!= FRAG_ATTRIB_WPOS
&&
1357 !(brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)))
1360 /* Each attribute is 4 setup channels, each of which is half a reg. */
1361 interp_reg_nr
[i
] = urb_start
+ c
->prog_data
.urb_read_length
;
1362 c
->prog_data
.urb_read_length
+= 2;
1365 /* Map the register numbers for FS_OPCODE_LINTERP so that it uses
1366 * the correct setup input.
1368 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1369 fs_inst
*inst
= (fs_inst
*)iter
.get();
1371 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
1374 assert(inst
->src
[2].file
== FIXED_HW_REG
);
1376 int location
= inst
->src
[2].fixed_hw_reg
.nr
/ 2;
1377 assert(interp_reg_nr
[location
] != -1);
1378 inst
->src
[2].fixed_hw_reg
.nr
= (interp_reg_nr
[location
] +
1379 (inst
->src
[2].fixed_hw_reg
.nr
& 1));
1382 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
1386 fs_visitor::assign_regs()
1388 int header_size
= this->first_non_payload_grf
;
1391 /* FINISHME: trivial assignment of register numbers */
1392 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1393 fs_inst
*inst
= (fs_inst
*)iter
.get();
1395 trivial_assign_reg(header_size
, &inst
->dst
);
1396 trivial_assign_reg(header_size
, &inst
->src
[0]);
1397 trivial_assign_reg(header_size
, &inst
->src
[1]);
1399 last_grf
= MAX2(last_grf
, inst
->dst
.hw_reg
);
1400 last_grf
= MAX2(last_grf
, inst
->src
[0].hw_reg
);
1401 last_grf
= MAX2(last_grf
, inst
->src
[1].hw_reg
);
1404 this->grf_used
= last_grf
+ 1;
1407 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
1409 struct brw_reg brw_reg
;
1411 switch (reg
->file
) {
1415 brw_reg
= brw_vec8_reg(reg
->file
,
1417 brw_reg
= retype(brw_reg
, reg
->type
);
1420 switch (reg
->type
) {
1421 case BRW_REGISTER_TYPE_F
:
1422 brw_reg
= brw_imm_f(reg
->imm
.f
);
1424 case BRW_REGISTER_TYPE_D
:
1425 brw_reg
= brw_imm_f(reg
->imm
.i
);
1427 case BRW_REGISTER_TYPE_UD
:
1428 brw_reg
= brw_imm_f(reg
->imm
.u
);
1431 assert(!"not reached");
1436 brw_reg
= reg
->fixed_hw_reg
;
1439 /* Probably unused. */
1440 brw_reg
= brw_null_reg();
1443 assert(!"not reached");
1444 brw_reg
= brw_null_reg();
1448 brw_reg
= brw_abs(brw_reg
);
1450 brw_reg
= negate(brw_reg
);
1456 fs_visitor::generate_code()
1458 unsigned int annotation_len
= 0;
1459 int last_native_inst
= 0;
1460 struct brw_instruction
*if_stack
[16];
1461 int if_stack_depth
= 0;
1463 memset(&if_stack
, 0, sizeof(if_stack
));
1464 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1465 fs_inst
*inst
= (fs_inst
*)iter
.get();
1466 struct brw_reg src
[3], dst
;
1468 for (unsigned int i
= 0; i
< 3; i
++) {
1469 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
1471 dst
= brw_reg_from_fs_reg(&inst
->dst
);
1473 brw_set_conditionalmod(p
, inst
->conditional_mod
);
1474 brw_set_predicate_control(p
, inst
->predicated
);
1476 switch (inst
->opcode
) {
1477 case BRW_OPCODE_MOV
:
1478 brw_MOV(p
, dst
, src
[0]);
1480 case BRW_OPCODE_ADD
:
1481 brw_ADD(p
, dst
, src
[0], src
[1]);
1483 case BRW_OPCODE_MUL
:
1484 brw_MUL(p
, dst
, src
[0], src
[1]);
1486 case BRW_OPCODE_FRC
:
1487 brw_FRC(p
, dst
, src
[0]);
1490 case BRW_OPCODE_AND
:
1491 brw_AND(p
, dst
, src
[0], src
[1]);
1494 brw_OR(p
, dst
, src
[0], src
[1]);
1496 case BRW_OPCODE_XOR
:
1497 brw_XOR(p
, dst
, src
[0], src
[1]);
1500 case BRW_OPCODE_CMP
:
1501 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1504 assert(if_stack_depth
< 16);
1505 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
1508 case BRW_OPCODE_ELSE
:
1509 if_stack
[if_stack_depth
- 1] =
1510 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
1512 case BRW_OPCODE_ENDIF
:
1514 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
1518 case FS_OPCODE_SQRT
:
1519 case FS_OPCODE_EXP2
:
1520 case FS_OPCODE_LOG2
:
1524 generate_math(inst
, dst
, src
);
1526 case FS_OPCODE_LINTERP
:
1527 generate_linterp(inst
, dst
, src
);
1529 case FS_OPCODE_FB_WRITE
:
1530 generate_fb_write(inst
);
1533 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
1534 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
1535 brw_opcodes
[inst
->opcode
].name
);
1537 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
1542 if (annotation_len
< p
->nr_insn
) {
1543 annotation_len
*= 2;
1544 if (annotation_len
< 16)
1545 annotation_len
= 16;
1547 this->annotation_string
= talloc_realloc(this->mem_ctx
,
1551 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
1557 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
1558 this->annotation_string
[i
] = inst
->annotation
;
1559 this->annotation_ir
[i
] = inst
->ir
;
1561 last_native_inst
= p
->nr_insn
;
1566 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
1568 struct brw_compile
*p
= &c
->func
;
1569 struct intel_context
*intel
= &brw
->intel
;
1570 GLcontext
*ctx
= &intel
->ctx
;
1571 struct brw_shader
*shader
= NULL
;
1572 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
1580 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
1581 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
1582 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
1589 /* We always use 8-wide mode, at least for now. For one, flow
1590 * control only works in 8-wide. Also, when we're fragment shader
1591 * bound, we're almost always under register pressure as well, so
1592 * 8-wide would save us from the performance cliff of spilling
1595 c
->dispatch_width
= 8;
1597 if (INTEL_DEBUG
& DEBUG_WM
) {
1598 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
1599 _mesa_print_ir(shader
->ir
, NULL
);
1603 /* Now the main event: Visit the shader IR and generate our FS IR for it.
1605 fs_visitor
v(c
, shader
);
1610 v
.emit_interpolation();
1612 /* Generate FS IR for main(). (the visitor only descends into
1613 * functions called "main").
1615 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
1616 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1625 v
.assign_curb_setup();
1626 v
.assign_urb_setup();
1632 if (INTEL_DEBUG
& DEBUG_WM
) {
1633 const char *last_annotation_string
= NULL
;
1634 ir_instruction
*last_annotation_ir
= NULL
;
1636 printf("Native code for fragment shader %d:\n", prog
->Name
);
1637 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
1638 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
1639 last_annotation_ir
= v
.annotation_ir
[i
];
1640 if (last_annotation_ir
) {
1642 last_annotation_ir
->print();
1646 if (last_annotation_string
!= v
.annotation_string
[i
]) {
1647 last_annotation_string
= v
.annotation_string
[i
];
1648 if (last_annotation_string
)
1649 printf(" %s\n", last_annotation_string
);
1651 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
1656 c
->prog_data
.total_grf
= v
.grf_used
;
1657 c
->prog_data
.total_scratch
= 0;