2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "glsl/nir/glsl_types.h"
46 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
47 const fs_reg
*src
, unsigned sources
)
49 memset(this, 0, sizeof(*this));
51 this->src
= new fs_reg
[MAX2(sources
, 3)];
52 for (unsigned i
= 0; i
< sources
; i
++)
53 this->src
[i
] = src
[i
];
55 this->opcode
= opcode
;
57 this->sources
= sources
;
58 this->exec_size
= exec_size
;
60 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
62 assert(this->exec_size
!= 0);
64 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
66 /* This will be the case for almost all instructions. */
73 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
77 this->regs_written
= 0;
81 unreachable("Invalid destination register file");
84 this->writes_accumulator
= false;
89 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
92 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
94 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
99 init(opcode
, exec_size
, dst
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
105 const fs_reg src
[1] = { src0
};
106 init(opcode
, exec_size
, dst
, src
, 1);
109 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg
&src0
, const fs_reg
&src1
)
112 const fs_reg src
[2] = { src0
, src1
};
113 init(opcode
, exec_size
, dst
, src
, 2);
116 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
117 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
119 const fs_reg src
[3] = { src0
, src1
, src2
};
120 init(opcode
, exec_size
, dst
, src
, 3);
123 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
124 const fs_reg src
[], unsigned sources
)
126 init(opcode
, exec_width
, dst
, src
, sources
);
129 fs_inst::fs_inst(const fs_inst
&that
)
131 memcpy(this, &that
, sizeof(that
));
133 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
135 for (unsigned i
= 0; i
< that
.sources
; i
++)
136 this->src
[i
] = that
.src
[i
];
145 fs_inst::resize_sources(uint8_t num_sources
)
147 if (this->sources
!= num_sources
) {
148 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
150 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
151 src
[i
] = this->src
[i
];
155 this->sources
= num_sources
;
160 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
162 const fs_reg
&surf_index
,
163 const fs_reg
&varying_offset
,
164 uint32_t const_offset
)
166 /* We have our constant surface use a pitch of 4 bytes, so our index can
167 * be any component of a vector, and then we load 4 contiguous
168 * components starting from that.
170 * We break down the const_offset to a portion added to the variable
171 * offset and a portion done using reg_offset, which means that if you
172 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
173 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
174 * CSE can later notice that those loads are all the same and eliminate
175 * the redundant ones.
177 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
178 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~3));
181 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
182 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
183 * u, v, r) as parameters, or we can just use the SIMD16 message
184 * consisting of (header, u). We choose the second, at the cost of a
185 * longer return length.
191 if (devinfo
->gen
>= 7)
192 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
194 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
196 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
197 fs_reg vec4_result
= fs_reg(VGRF
, alloc
.allocate(regs_written
), dst
.type
);
198 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
199 inst
->regs_written
= regs_written
;
201 if (devinfo
->gen
< 7) {
202 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
203 inst
->header_size
= 1;
204 if (devinfo
->gen
== 4)
207 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
210 bld
.MOV(dst
, offset(vec4_result
, bld
, (const_offset
& 3) * scale
));
214 * A helper for MOV generation for fixing up broken hardware SEND dependency
218 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
220 /* The caller always wants uncompressed to emit the minimal extra
221 * dependencies, and to avoid having to deal with aligning its regs to 2.
223 const fs_builder ubld
= bld
.annotate("send dependency resolve")
226 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
230 fs_inst::equals(fs_inst
*inst
) const
232 return (opcode
== inst
->opcode
&&
233 dst
.equals(inst
->dst
) &&
234 src
[0].equals(inst
->src
[0]) &&
235 src
[1].equals(inst
->src
[1]) &&
236 src
[2].equals(inst
->src
[2]) &&
237 saturate
== inst
->saturate
&&
238 predicate
== inst
->predicate
&&
239 conditional_mod
== inst
->conditional_mod
&&
240 mlen
== inst
->mlen
&&
241 base_mrf
== inst
->base_mrf
&&
242 target
== inst
->target
&&
244 header_size
== inst
->header_size
&&
245 shadow_compare
== inst
->shadow_compare
&&
246 exec_size
== inst
->exec_size
&&
247 offset
== inst
->offset
);
251 fs_inst::overwrites_reg(const fs_reg
®
) const
253 return reg
.in_range(dst
, regs_written
);
257 fs_inst::is_send_from_grf() const
260 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
261 case SHADER_OPCODE_SHADER_TIME_ADD
:
262 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
263 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
264 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
265 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
266 case SHADER_OPCODE_UNTYPED_ATOMIC
:
267 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
268 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
269 case SHADER_OPCODE_TYPED_ATOMIC
:
270 case SHADER_OPCODE_TYPED_SURFACE_READ
:
271 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
272 case SHADER_OPCODE_URB_WRITE_SIMD8
:
273 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
274 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
275 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
276 case SHADER_OPCODE_URB_READ_SIMD8
:
277 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
279 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
280 return src
[1].file
== VGRF
;
281 case FS_OPCODE_FB_WRITE
:
282 return src
[0].file
== VGRF
;
285 return src
[0].file
== VGRF
;
292 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
294 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
297 fs_reg reg
= this->src
[0];
298 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
301 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
304 for (int i
= 0; i
< this->sources
; i
++) {
305 reg
.type
= this->src
[i
].type
;
306 if (!this->src
[i
].equals(reg
))
309 if (i
< this->header_size
) {
312 reg
.reg_offset
+= this->exec_size
/ 8;
320 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
322 if (devinfo
->gen
== 6 && is_math())
325 if (is_send_from_grf())
328 if (!backend_instruction::can_do_source_mods())
335 fs_inst::can_change_types() const
337 return dst
.type
== src
[0].type
&&
338 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
339 (opcode
== BRW_OPCODE_MOV
||
340 (opcode
== BRW_OPCODE_SEL
&&
341 dst
.type
== src
[1].type
&&
342 predicate
!= BRW_PREDICATE_NONE
&&
343 !src
[1].abs
&& !src
[1].negate
));
347 fs_inst::has_side_effects() const
349 return this->eot
|| backend_instruction::has_side_effects();
355 memset(this, 0, sizeof(*this));
359 /** Generic unset register constructor. */
363 this->file
= BAD_FILE
;
366 fs_reg::fs_reg(struct ::brw_reg reg
) :
369 this->reg_offset
= 0;
370 this->subreg_offset
= 0;
371 this->reladdr
= NULL
;
373 if (this->file
== IMM
&&
374 (this->type
!= BRW_REGISTER_TYPE_V
&&
375 this->type
!= BRW_REGISTER_TYPE_UV
&&
376 this->type
!= BRW_REGISTER_TYPE_VF
)) {
382 fs_reg::equals(const fs_reg
&r
) const
384 return (this->backend_reg::equals(r
) &&
385 subreg_offset
== r
.subreg_offset
&&
386 !reladdr
&& !r
.reladdr
&&
391 fs_reg::set_smear(unsigned subreg
)
393 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
394 subreg_offset
= subreg
* type_sz(type
);
400 fs_reg::is_contiguous() const
406 fs_reg::component_size(unsigned width
) const
408 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
411 return MAX2(width
* stride
, 1) * type_sz(type
);
415 type_size_scalar(const struct glsl_type
*type
)
417 unsigned int size
, i
;
419 switch (type
->base_type
) {
422 case GLSL_TYPE_FLOAT
:
424 return type
->components();
425 case GLSL_TYPE_ARRAY
:
426 return type_size_scalar(type
->fields
.array
) * type
->length
;
427 case GLSL_TYPE_STRUCT
:
429 for (i
= 0; i
< type
->length
; i
++) {
430 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
433 case GLSL_TYPE_SAMPLER
:
434 /* Samplers take up no register space, since they're baked in at
438 case GLSL_TYPE_ATOMIC_UINT
:
440 case GLSL_TYPE_SUBROUTINE
:
442 case GLSL_TYPE_IMAGE
:
443 return BRW_IMAGE_PARAM_SIZE
;
445 case GLSL_TYPE_ERROR
:
446 case GLSL_TYPE_INTERFACE
:
447 case GLSL_TYPE_DOUBLE
:
448 unreachable("not reached");
455 * Returns the number of scalar components needed to store type, assuming
456 * that vectors are padded out to vec4.
458 * This has the packing rules of type_size_vec4(), but counts components
459 * similar to type_size_scalar().
462 type_size_vec4_times_4(const struct glsl_type
*type
)
464 return 4 * type_size_vec4(type
);
468 * Create a MOV to read the timestamp register.
470 * The caller is responsible for emitting the MOV. The return value is
471 * the destination of the MOV, with extra parameters set.
474 fs_visitor::get_timestamp(const fs_builder
&bld
)
476 assert(devinfo
->gen
>= 7);
478 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
481 BRW_REGISTER_TYPE_UD
));
483 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
485 /* We want to read the 3 fields we care about even if it's not enabled in
488 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
494 fs_visitor::emit_shader_time_begin()
496 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
498 /* We want only the low 32 bits of the timestamp. Since it's running
499 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
500 * which is plenty of time for our purposes. It is identical across the
501 * EUs, but since it's tracking GPU core speed it will increment at a
502 * varying rate as render P-states change.
504 shader_start_time
.set_smear(0);
508 fs_visitor::emit_shader_time_end()
510 /* Insert our code just before the final SEND with EOT. */
511 exec_node
*end
= this->instructions
.get_tail();
512 assert(end
&& ((fs_inst
*) end
)->eot
);
513 const fs_builder ibld
= bld
.annotate("shader time end")
514 .exec_all().at(NULL
, end
);
516 fs_reg shader_end_time
= get_timestamp(ibld
);
518 /* We only use the low 32 bits of the timestamp - see
519 * emit_shader_time_begin()).
521 * We could also check if render P-states have changed (or anything
522 * else that might disrupt timing) by setting smear to 2 and checking if
523 * that field is != 0.
525 shader_end_time
.set_smear(0);
527 /* Check that there weren't any timestamp reset events (assuming these
528 * were the only two timestamp reads that happened).
530 fs_reg reset
= shader_end_time
;
532 set_condmod(BRW_CONDITIONAL_Z
,
533 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
534 ibld
.IF(BRW_PREDICATE_NORMAL
);
536 fs_reg start
= shader_start_time
;
538 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
541 const fs_builder cbld
= ibld
.group(1, 0);
542 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
544 /* If there were no instructions between the two timestamp gets, the diff
545 * is 2 cycles. Remove that overhead, so I can forget about that when
546 * trying to determine the time taken for single instructions.
548 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
549 SHADER_TIME_ADD(cbld
, 0, diff
);
550 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
551 ibld
.emit(BRW_OPCODE_ELSE
);
552 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
553 ibld
.emit(BRW_OPCODE_ENDIF
);
557 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
558 int shader_time_subindex
,
561 int index
= shader_time_index
* 3 + shader_time_subindex
;
562 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
565 if (dispatch_width
== 8)
566 payload
= vgrf(glsl_type::uvec2_type
);
568 payload
= vgrf(glsl_type::uint_type
);
570 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
574 fs_visitor::vfail(const char *format
, va_list va
)
583 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
584 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
586 this->fail_msg
= msg
;
589 fprintf(stderr
, "%s", msg
);
594 fs_visitor::fail(const char *format
, ...)
598 va_start(va
, format
);
604 * Mark this program as impossible to compile in SIMD16 mode.
606 * During the SIMD8 compile (which happens first), we can detect and flag
607 * things that are unsupported in SIMD16 mode, so the compiler can skip
608 * the SIMD16 compile altogether.
610 * During a SIMD16 compile (if one happens anyway), this just calls fail().
613 fs_visitor::no16(const char *msg
)
615 if (dispatch_width
== 16) {
618 simd16_unsupported
= true;
620 compiler
->shader_perf_log(log_data
,
621 "SIMD16 shader failed to compile: %s", msg
);
626 * Returns true if the instruction has a flag that means it won't
627 * update an entire destination register.
629 * For example, dead code elimination and live variable analysis want to know
630 * when a write to a variable screens off any preceding values that were in
634 fs_inst::is_partial_write() const
636 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
637 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
638 !this->dst
.is_contiguous());
642 fs_inst::components_read(unsigned i
) const
645 case FS_OPCODE_LINTERP
:
651 case FS_OPCODE_PIXEL_X
:
652 case FS_OPCODE_PIXEL_Y
:
656 case FS_OPCODE_FB_WRITE_LOGICAL
:
657 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
658 /* First/second FB write color. */
660 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
664 case SHADER_OPCODE_TEX_LOGICAL
:
665 case SHADER_OPCODE_TXD_LOGICAL
:
666 case SHADER_OPCODE_TXF_LOGICAL
:
667 case SHADER_OPCODE_TXL_LOGICAL
:
668 case SHADER_OPCODE_TXS_LOGICAL
:
669 case FS_OPCODE_TXB_LOGICAL
:
670 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
671 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
672 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
673 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
674 case SHADER_OPCODE_LOD_LOGICAL
:
675 case SHADER_OPCODE_TG4_LOGICAL
:
676 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
677 assert(src
[8].file
== IMM
&& src
[9].file
== IMM
);
678 /* Texture coordinates. */
681 /* Texture derivatives. */
682 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
684 /* Texture offset. */
688 else if (i
== 5 && opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
693 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
694 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
695 assert(src
[3].file
== IMM
);
696 /* Surface coordinates. */
699 /* Surface operation source (ignored for reads). */
705 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
706 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
707 assert(src
[3].file
== IMM
&&
709 /* Surface coordinates. */
712 /* Surface operation source. */
718 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
719 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
720 assert(src
[3].file
== IMM
&&
722 const unsigned op
= src
[4].ud
;
723 /* Surface coordinates. */
726 /* Surface operation source. */
727 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
729 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
730 op
== BRW_AOP_PREDEC
))
742 fs_inst::regs_read(int arg
) const
745 case FS_OPCODE_FB_WRITE
:
746 case SHADER_OPCODE_URB_WRITE_SIMD8
:
747 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
748 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
749 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
750 case SHADER_OPCODE_URB_READ_SIMD8
:
751 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
752 case SHADER_OPCODE_UNTYPED_ATOMIC
:
753 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
754 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
755 case SHADER_OPCODE_TYPED_ATOMIC
:
756 case SHADER_OPCODE_TYPED_SURFACE_READ
:
757 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
758 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
763 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
764 /* The payload is actually stored in src1 */
769 case FS_OPCODE_LINTERP
:
774 case SHADER_OPCODE_LOAD_PAYLOAD
:
775 if (arg
< this->header_size
)
779 case CS_OPCODE_CS_TERMINATE
:
780 case SHADER_OPCODE_BARRIER
:
783 case SHADER_OPCODE_MOV_INDIRECT
:
785 assert(src
[2].file
== IMM
);
786 unsigned region_length
= src
[2].ud
;
788 if (src
[0].file
== FIXED_GRF
) {
789 /* If the start of the region is not register aligned, then
790 * there's some portion of the register that's technically
791 * unread at the beginning.
793 * However, the register allocator works in terms of whole
794 * registers, and does not use subnr. It assumes that the
795 * read starts at the beginning of the register, and extends
796 * regs_read() whole registers beyond that.
798 * To compensate, we extend the region length to include this
799 * unread portion at the beginning.
802 region_length
+= src
[0].subnr
* type_sz(src
[0].type
);
804 return DIV_ROUND_UP(region_length
, REG_SIZE
);
806 assert(!"Invalid register file");
812 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
817 switch (src
[arg
].file
) {
827 return DIV_ROUND_UP(components_read(arg
) *
828 src
[arg
].component_size(exec_size
),
831 unreachable("MRF registers are not allowed as sources");
837 fs_inst::reads_flag() const
843 fs_inst::writes_flag() const
845 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
846 opcode
!= BRW_OPCODE_IF
&&
847 opcode
!= BRW_OPCODE_WHILE
)) ||
848 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
852 * Returns how many MRFs an FS opcode will write over.
854 * Note that this is not the 0 or 1 implied writes in an actual gen
855 * instruction -- the FS opcodes often generate MOVs in addition.
858 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
863 if (inst
->base_mrf
== -1)
866 switch (inst
->opcode
) {
867 case SHADER_OPCODE_RCP
:
868 case SHADER_OPCODE_RSQ
:
869 case SHADER_OPCODE_SQRT
:
870 case SHADER_OPCODE_EXP2
:
871 case SHADER_OPCODE_LOG2
:
872 case SHADER_OPCODE_SIN
:
873 case SHADER_OPCODE_COS
:
874 return 1 * dispatch_width
/ 8;
875 case SHADER_OPCODE_POW
:
876 case SHADER_OPCODE_INT_QUOTIENT
:
877 case SHADER_OPCODE_INT_REMAINDER
:
878 return 2 * dispatch_width
/ 8;
879 case SHADER_OPCODE_TEX
:
881 case SHADER_OPCODE_TXD
:
882 case SHADER_OPCODE_TXF
:
883 case SHADER_OPCODE_TXF_CMS
:
884 case SHADER_OPCODE_TXF_CMS_W
:
885 case SHADER_OPCODE_TXF_MCS
:
886 case SHADER_OPCODE_TG4
:
887 case SHADER_OPCODE_TG4_OFFSET
:
888 case SHADER_OPCODE_TXL
:
889 case SHADER_OPCODE_TXS
:
890 case SHADER_OPCODE_LOD
:
891 case SHADER_OPCODE_SAMPLEINFO
:
893 case FS_OPCODE_FB_WRITE
:
895 case FS_OPCODE_GET_BUFFER_SIZE
:
896 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
897 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
899 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
901 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
903 case SHADER_OPCODE_UNTYPED_ATOMIC
:
904 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
905 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
906 case SHADER_OPCODE_TYPED_ATOMIC
:
907 case SHADER_OPCODE_TYPED_SURFACE_READ
:
908 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
909 case SHADER_OPCODE_URB_WRITE_SIMD8
:
910 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
911 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
912 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
913 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
914 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
915 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
916 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
919 unreachable("not reached");
924 fs_visitor::vgrf(const glsl_type
*const type
)
926 int reg_width
= dispatch_width
/ 8;
927 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
928 brw_type_for_base_type(type
));
931 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
936 this->type
= BRW_REGISTER_TYPE_F
;
937 this->stride
= (file
== UNIFORM
? 0 : 1);
940 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
946 this->stride
= (file
== UNIFORM
? 0 : 1);
949 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
950 * This brings in those uniform definitions
953 fs_visitor::import_uniforms(fs_visitor
*v
)
955 this->push_constant_loc
= v
->push_constant_loc
;
956 this->pull_constant_loc
= v
->pull_constant_loc
;
957 this->uniforms
= v
->uniforms
;
958 this->param_size
= v
->param_size
;
962 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
963 bool origin_upper_left
)
965 assert(stage
== MESA_SHADER_FRAGMENT
);
966 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
967 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
969 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
972 if (pixel_center_integer
) {
973 bld
.MOV(wpos
, this->pixel_x
);
975 bld
.ADD(wpos
, this->pixel_x
, brw_imm_f(0.5f
));
977 wpos
= offset(wpos
, bld
, 1);
980 if (!flip
&& pixel_center_integer
) {
981 bld
.MOV(wpos
, this->pixel_y
);
983 fs_reg pixel_y
= this->pixel_y
;
984 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
987 pixel_y
.negate
= true;
988 offset
+= key
->drawable_height
- 1.0f
;
991 bld
.ADD(wpos
, pixel_y
, brw_imm_f(offset
));
993 wpos
= offset(wpos
, bld
, 1);
996 if (devinfo
->gen
>= 6) {
997 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
999 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1000 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1001 interp_reg(VARYING_SLOT_POS
, 2));
1003 wpos
= offset(wpos
, bld
, 1);
1005 /* gl_FragCoord.w: Already set up in emit_interpolation */
1006 bld
.MOV(wpos
, this->wpos_w
);
1012 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1013 glsl_interp_qualifier interpolation_mode
,
1014 bool is_centroid
, bool is_sample
)
1016 brw_wm_barycentric_interp_mode barycoord_mode
;
1017 if (devinfo
->gen
>= 6) {
1019 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1020 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1022 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1023 } else if (is_sample
) {
1024 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1025 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1027 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1029 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1030 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1032 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1035 /* On Ironlake and below, there is only one interpolation mode.
1036 * Centroid interpolation doesn't mean anything on this hardware --
1037 * there is no multisampling.
1039 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1041 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1042 this->delta_xy
[barycoord_mode
], interp
);
1046 fs_visitor::emit_general_interpolation(fs_reg
*attr
, const char *name
,
1047 const glsl_type
*type
,
1048 glsl_interp_qualifier interpolation_mode
,
1049 int *location
, bool mod_centroid
,
1052 assert(stage
== MESA_SHADER_FRAGMENT
);
1053 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1054 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1056 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1058 *location
== VARYING_SLOT_COL0
|| *location
== VARYING_SLOT_COL1
;
1059 if (key
->flat_shade
&& is_gl_Color
) {
1060 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1062 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1066 if (type
->is_array() || type
->is_matrix()) {
1067 const glsl_type
*elem_type
= glsl_get_array_element(type
);
1068 const unsigned length
= glsl_get_length(type
);
1070 for (unsigned i
= 0; i
< length
; i
++) {
1071 emit_general_interpolation(attr
, name
, elem_type
, interpolation_mode
,
1072 location
, mod_centroid
, mod_sample
);
1074 } else if (type
->is_record()) {
1075 for (unsigned i
= 0; i
< type
->length
; i
++) {
1076 const glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
1077 emit_general_interpolation(attr
, name
, field_type
, interpolation_mode
,
1078 location
, mod_centroid
, mod_sample
);
1081 assert(type
->is_scalar() || type
->is_vector());
1083 if (prog_data
->urb_setup
[*location
] == -1) {
1084 /* If there's no incoming setup data for this slot, don't
1085 * emit interpolation for it.
1087 *attr
= offset(*attr
, bld
, type
->vector_elements
);
1092 attr
->type
= brw_type_for_base_type(type
->get_scalar_type());
1094 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1095 /* Constant interpolation (flat shading) case. The SF has
1096 * handed us defined values in only the constant offset
1097 * field of the setup reg.
1099 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1100 struct brw_reg interp
= interp_reg(*location
, i
);
1101 interp
= suboffset(interp
, 3);
1102 interp
.type
= attr
->type
;
1103 bld
.emit(FS_OPCODE_CINTERP
, *attr
, fs_reg(interp
));
1104 *attr
= offset(*attr
, bld
, 1);
1107 /* Smooth/noperspective interpolation case. */
1108 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1109 struct brw_reg interp
= interp_reg(*location
, i
);
1110 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1111 /* Get the pixel/sample mask into f0 so that we know
1112 * which pixels are lit. Then, for each channel that is
1113 * unlit, replace the centroid data with non-centroid
1116 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1119 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1121 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1122 inst
->predicate_inverse
= true;
1123 if (devinfo
->has_pln
)
1124 inst
->no_dd_clear
= true;
1126 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1127 mod_centroid
&& !key
->persample_shading
,
1128 mod_sample
|| key
->persample_shading
);
1129 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1130 inst
->predicate_inverse
= false;
1131 if (devinfo
->has_pln
)
1132 inst
->no_dd_check
= true;
1135 emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1136 mod_centroid
&& !key
->persample_shading
,
1137 mod_sample
|| key
->persample_shading
);
1139 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1140 bld
.MUL(*attr
, *attr
, this->pixel_w
);
1142 *attr
= offset(*attr
, bld
, 1);
1150 fs_visitor::emit_frontfacing_interpolation()
1152 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1154 if (devinfo
->gen
>= 6) {
1155 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1156 * a boolean result from this (~0/true or 0/false).
1158 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1159 * this task in only one instruction:
1160 * - a negation source modifier will flip the bit; and
1161 * - a W -> D type conversion will sign extend the bit into the high
1162 * word of the destination.
1164 * An ASR 15 fills the low word of the destination.
1166 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1169 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1171 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1172 * a boolean result from this (1/true or 0/false).
1174 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1175 * the negation source modifier to flip it. Unfortunately the SHR
1176 * instruction only operates on UD (or D with an abs source modifier)
1177 * sources without negation.
1179 * Instead, use ASR (which will give ~0/true or 0/false).
1181 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1184 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1191 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1193 assert(stage
== MESA_SHADER_FRAGMENT
);
1194 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1195 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1197 if (key
->compute_pos_offset
) {
1198 /* Convert int_sample_pos to floating point */
1199 bld
.MOV(dst
, int_sample_pos
);
1200 /* Scale to the range [0, 1] */
1201 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1204 /* From ARB_sample_shading specification:
1205 * "When rendering to a non-multisample buffer, or if multisample
1206 * rasterization is disabled, gl_SamplePosition will always be
1209 bld
.MOV(dst
, brw_imm_f(0.5f
));
1214 fs_visitor::emit_samplepos_setup()
1216 assert(devinfo
->gen
>= 6);
1218 const fs_builder abld
= bld
.annotate("compute sample position");
1219 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1221 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1222 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1224 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1225 * mode will be enabled.
1227 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1228 * R31.1:0 Position Offset X/Y for Slot[3:0]
1229 * R31.3:2 Position Offset X/Y for Slot[7:4]
1232 * The X, Y sample positions come in as bytes in thread payload. So, read
1233 * the positions using vstride=16, width=8, hstride=2.
1235 struct brw_reg sample_pos_reg
=
1236 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1237 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1239 if (dispatch_width
== 8) {
1240 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1242 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1243 abld
.half(1).MOV(half(int_sample_x
, 1),
1244 fs_reg(suboffset(sample_pos_reg
, 16)));
1246 /* Compute gl_SamplePosition.x */
1247 compute_sample_position(pos
, int_sample_x
);
1248 pos
= offset(pos
, abld
, 1);
1249 if (dispatch_width
== 8) {
1250 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1252 abld
.half(0).MOV(half(int_sample_y
, 0),
1253 fs_reg(suboffset(sample_pos_reg
, 1)));
1254 abld
.half(1).MOV(half(int_sample_y
, 1),
1255 fs_reg(suboffset(sample_pos_reg
, 17)));
1257 /* Compute gl_SamplePosition.y */
1258 compute_sample_position(pos
, int_sample_y
);
1263 fs_visitor::emit_sampleid_setup()
1265 assert(stage
== MESA_SHADER_FRAGMENT
);
1266 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1267 assert(devinfo
->gen
>= 6);
1269 const fs_builder abld
= bld
.annotate("compute sample id");
1270 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1272 if (key
->compute_sample_id
) {
1273 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1275 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1277 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1278 * 8x multisampling, subspan 0 will represent sample N (where N
1279 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1280 * 7. We can find the value of N by looking at R0.0 bits 7:6
1281 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1282 * (since samples are always delivered in pairs). That is, we
1283 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1284 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1285 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1286 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1287 * populating a temporary variable with the sequence (0, 1, 2, 3),
1288 * and then reading from it using vstride=1, width=4, hstride=0.
1289 * These computations hold good for 4x multisampling as well.
1291 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1292 * the first four slots are sample 0 of subspan 0; the next four
1293 * are sample 1 of subspan 0; the third group is sample 0 of
1294 * subspan 1, and finally sample 1 of subspan 1.
1297 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1298 * accomodate 16x MSAA.
1300 unsigned sspi_mask
= devinfo
->gen
>= 9 ? 0x1c0 : 0xc0;
1302 abld
.exec_all().group(1, 0)
1303 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1304 brw_imm_ud(sspi_mask
));
1305 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1307 /* This works for both SIMD8 and SIMD16 */
1308 abld
.exec_all().group(4, 0)
1309 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1311 /* This special instruction takes care of setting vstride=1,
1312 * width=4, hstride=0 of t2 during an ADD instruction.
1314 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1316 /* As per GL_ARB_sample_shading specification:
1317 * "When rendering to a non-multisample buffer, or if multisample
1318 * rasterization is disabled, gl_SampleID will always be zero."
1320 abld
.MOV(*reg
, brw_imm_d(0));
1327 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1329 if (!src
.abs
&& !src
.negate
)
1332 fs_reg temp
= bld
.vgrf(src
.type
);
1339 fs_visitor::emit_discard_jump()
1341 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1343 /* For performance, after a discard, jump to the end of the
1344 * shader if all relevant channels have been discarded.
1346 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1347 discard_jump
->flag_subreg
= 1;
1349 discard_jump
->predicate
= (dispatch_width
== 8)
1350 ? BRW_PREDICATE_ALIGN1_ANY8H
1351 : BRW_PREDICATE_ALIGN1_ANY16H
;
1352 discard_jump
->predicate_inverse
= true;
1356 fs_visitor::emit_gs_thread_end()
1358 assert(stage
== MESA_SHADER_GEOMETRY
);
1360 struct brw_gs_prog_data
*gs_prog_data
=
1361 (struct brw_gs_prog_data
*) prog_data
;
1363 if (gs_compile
->control_data_header_size_bits
> 0) {
1364 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1367 const fs_builder abld
= bld
.annotate("thread end");
1370 if (gs_prog_data
->static_vertex_count
!= -1) {
1371 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1372 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1373 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1374 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1375 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1378 /* Delete now dead instructions. */
1379 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1385 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1389 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1390 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1391 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1394 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1395 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1396 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1397 sources
[1] = this->final_gs_vertex_count
;
1398 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1399 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1407 fs_visitor::assign_curb_setup()
1409 if (dispatch_width
== 8) {
1410 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1412 if (stage
== MESA_SHADER_FRAGMENT
) {
1413 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1414 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1415 } else if (stage
== MESA_SHADER_COMPUTE
) {
1416 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1417 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1419 unreachable("Unsupported shader type!");
1423 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1425 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1426 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1427 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1428 if (inst
->src
[i
].file
== UNIFORM
) {
1429 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1431 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1432 constant_nr
= push_constant_loc
[uniform_nr
];
1434 /* Section 5.11 of the OpenGL 4.1 spec says:
1435 * "Out-of-bounds reads return undefined values, which include
1436 * values from other variables of the active program or zero."
1437 * Just return the first push constant.
1442 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1445 brw_reg
.abs
= inst
->src
[i
].abs
;
1446 brw_reg
.negate
= inst
->src
[i
].negate
;
1448 assert(inst
->src
[i
].stride
== 0);
1449 inst
->src
[i
] = byte_offset(
1450 retype(brw_reg
, inst
->src
[i
].type
),
1451 inst
->src
[i
].subreg_offset
);
1456 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1457 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1461 fs_visitor::calculate_urb_setup()
1463 assert(stage
== MESA_SHADER_FRAGMENT
);
1464 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1465 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1467 memset(prog_data
->urb_setup
, -1,
1468 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1471 /* Figure out where each of the incoming setup attributes lands. */
1472 if (devinfo
->gen
>= 6) {
1473 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1474 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1475 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1476 * first 16 varying inputs, so we can put them wherever we want.
1477 * Just put them in order.
1479 * This is useful because it means that (a) inputs not used by the
1480 * fragment shader won't take up valuable register space, and (b) we
1481 * won't have to recompile the fragment shader if it gets paired with
1482 * a different vertex (or geometry) shader.
1484 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1485 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1486 BITFIELD64_BIT(i
)) {
1487 prog_data
->urb_setup
[i
] = urb_next
++;
1491 bool include_vue_header
=
1492 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1494 /* We have enough input varyings that the SF/SBE pipeline stage can't
1495 * arbitrarily rearrange them to suit our whim; we have to put them
1496 * in an order that matches the output of the previous pipeline stage
1497 * (geometry or vertex shader).
1499 struct brw_vue_map prev_stage_vue_map
;
1500 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1501 key
->input_slots_valid
,
1502 nir
->info
.separate_shader
);
1504 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1506 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1507 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1509 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1510 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1511 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1512 BITFIELD64_BIT(varying
))) {
1513 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1516 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1519 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1520 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1521 /* Point size is packed into the header, not as a general attribute */
1522 if (i
== VARYING_SLOT_PSIZ
)
1525 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1526 /* The back color slot is skipped when the front color is
1527 * also written to. In addition, some slots can be
1528 * written in the vertex shader and not read in the
1529 * fragment shader. So the register number must always be
1530 * incremented, mapped or not.
1532 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1533 prog_data
->urb_setup
[i
] = urb_next
;
1539 * It's a FS only attribute, and we did interpolation for this attribute
1540 * in SF thread. So, count it here, too.
1542 * See compile_sf_prog() for more info.
1544 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1545 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1548 prog_data
->num_varying_inputs
= urb_next
;
1552 fs_visitor::assign_urb_setup()
1554 assert(stage
== MESA_SHADER_FRAGMENT
);
1555 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1557 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1559 /* Offset all the urb_setup[] index by the actual position of the
1560 * setup regs, now that the location of the constants has been chosen.
1562 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1563 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1564 assert(inst
->src
[1].file
== FIXED_GRF
);
1565 inst
->src
[1].nr
+= urb_start
;
1568 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1569 assert(inst
->src
[0].file
== FIXED_GRF
);
1570 inst
->src
[0].nr
+= urb_start
;
1574 /* Each attribute is 4 setup channels, each of which is half a reg. */
1575 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1579 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1581 for (int i
= 0; i
< inst
->sources
; i
++) {
1582 if (inst
->src
[i
].file
== ATTR
) {
1583 int grf
= payload
.num_regs
+
1584 prog_data
->curb_read_length
+
1586 inst
->src
[i
].reg_offset
;
1588 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : inst
->exec_size
;
1589 struct brw_reg reg
=
1590 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1591 inst
->src
[i
].subreg_offset
),
1592 inst
->exec_size
* inst
->src
[i
].stride
,
1593 width
, inst
->src
[i
].stride
);
1594 reg
.abs
= inst
->src
[i
].abs
;
1595 reg
.negate
= inst
->src
[i
].negate
;
1603 fs_visitor::assign_vs_urb_setup()
1605 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1607 assert(stage
== MESA_SHADER_VERTEX
);
1608 int count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1609 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1612 /* Each attribute is 4 regs. */
1613 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1615 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1617 /* Rewrite all ATTR file references to the hw grf that they land in. */
1618 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1619 convert_attr_sources_to_hw_regs(inst
);
1624 fs_visitor::assign_gs_urb_setup()
1626 assert(stage
== MESA_SHADER_GEOMETRY
);
1628 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1630 first_non_payload_grf
+=
1631 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1633 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1634 /* Rewrite all ATTR file references to GRFs. */
1635 convert_attr_sources_to_hw_regs(inst
);
1641 * Split large virtual GRFs into separate components if we can.
1643 * This is mostly duplicated with what brw_fs_vector_splitting does,
1644 * but that's really conservative because it's afraid of doing
1645 * splitting that doesn't result in real progress after the rest of
1646 * the optimization phases, which would cause infinite looping in
1647 * optimization. We can do it once here, safely. This also has the
1648 * opportunity to split interpolated values, or maybe even uniforms,
1649 * which we don't have at the IR level.
1651 * We want to split, because virtual GRFs are what we register
1652 * allocate and spill (due to contiguousness requirements for some
1653 * instructions), and they're what we naturally generate in the
1654 * codegen process, but most virtual GRFs don't actually need to be
1655 * contiguous sets of GRFs. If we split, we'll end up with reduced
1656 * live intervals and better dead code elimination and coalescing.
1659 fs_visitor::split_virtual_grfs()
1661 int num_vars
= this->alloc
.count
;
1663 /* Count the total number of registers */
1665 int vgrf_to_reg
[num_vars
];
1666 for (int i
= 0; i
< num_vars
; i
++) {
1667 vgrf_to_reg
[i
] = reg_count
;
1668 reg_count
+= alloc
.sizes
[i
];
1671 /* An array of "split points". For each register slot, this indicates
1672 * if this slot can be separated from the previous slot. Every time an
1673 * instruction uses multiple elements of a register (as a source or
1674 * destination), we mark the used slots as inseparable. Then we go
1675 * through and split the registers into the smallest pieces we can.
1677 bool split_points
[reg_count
];
1678 memset(split_points
, 0, sizeof(split_points
));
1680 /* Mark all used registers as fully splittable */
1681 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1682 if (inst
->dst
.file
== VGRF
) {
1683 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1684 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1685 split_points
[reg
+ j
] = true;
1688 for (int i
= 0; i
< inst
->sources
; i
++) {
1689 if (inst
->src
[i
].file
== VGRF
) {
1690 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1691 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1692 split_points
[reg
+ j
] = true;
1697 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1698 if (inst
->dst
.file
== VGRF
) {
1699 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1700 for (int j
= 1; j
< inst
->regs_written
; j
++)
1701 split_points
[reg
+ j
] = false;
1703 for (int i
= 0; i
< inst
->sources
; i
++) {
1704 if (inst
->src
[i
].file
== VGRF
) {
1705 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1706 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1707 split_points
[reg
+ j
] = false;
1712 int new_virtual_grf
[reg_count
];
1713 int new_reg_offset
[reg_count
];
1716 for (int i
= 0; i
< num_vars
; i
++) {
1717 /* The first one should always be 0 as a quick sanity check. */
1718 assert(split_points
[reg
] == false);
1721 new_reg_offset
[reg
] = 0;
1726 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1727 /* If this is a split point, reset the offset to 0 and allocate a
1728 * new virtual GRF for the previous offset many registers
1730 if (split_points
[reg
]) {
1731 assert(offset
<= MAX_VGRF_SIZE
);
1732 int grf
= alloc
.allocate(offset
);
1733 for (int k
= reg
- offset
; k
< reg
; k
++)
1734 new_virtual_grf
[k
] = grf
;
1737 new_reg_offset
[reg
] = offset
;
1742 /* The last one gets the original register number */
1743 assert(offset
<= MAX_VGRF_SIZE
);
1744 alloc
.sizes
[i
] = offset
;
1745 for (int k
= reg
- offset
; k
< reg
; k
++)
1746 new_virtual_grf
[k
] = i
;
1748 assert(reg
== reg_count
);
1750 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1751 if (inst
->dst
.file
== VGRF
) {
1752 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1753 inst
->dst
.nr
= new_virtual_grf
[reg
];
1754 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1755 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1757 for (int i
= 0; i
< inst
->sources
; i
++) {
1758 if (inst
->src
[i
].file
== VGRF
) {
1759 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1760 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1761 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1762 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1766 invalidate_live_intervals();
1770 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1772 * During code generation, we create tons of temporary variables, many of
1773 * which get immediately killed and are never used again. Yet, in later
1774 * optimization and analysis passes, such as compute_live_intervals, we need
1775 * to loop over all the virtual GRFs. Compacting them can save a lot of
1779 fs_visitor::compact_virtual_grfs()
1781 bool progress
= false;
1782 int remap_table
[this->alloc
.count
];
1783 memset(remap_table
, -1, sizeof(remap_table
));
1785 /* Mark which virtual GRFs are used. */
1786 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1787 if (inst
->dst
.file
== VGRF
)
1788 remap_table
[inst
->dst
.nr
] = 0;
1790 for (int i
= 0; i
< inst
->sources
; i
++) {
1791 if (inst
->src
[i
].file
== VGRF
)
1792 remap_table
[inst
->src
[i
].nr
] = 0;
1796 /* Compact the GRF arrays. */
1798 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1799 if (remap_table
[i
] == -1) {
1800 /* We just found an unused register. This means that we are
1801 * actually going to compact something.
1805 remap_table
[i
] = new_index
;
1806 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1807 invalidate_live_intervals();
1812 this->alloc
.count
= new_index
;
1814 /* Patch all the instructions to use the newly renumbered registers */
1815 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1816 if (inst
->dst
.file
== VGRF
)
1817 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1819 for (int i
= 0; i
< inst
->sources
; i
++) {
1820 if (inst
->src
[i
].file
== VGRF
)
1821 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1825 /* Patch all the references to delta_xy, since they're used in register
1826 * allocation. If they're unused, switch them to BAD_FILE so we don't
1827 * think some random VGRF is delta_xy.
1829 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1830 if (delta_xy
[i
].file
== VGRF
) {
1831 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1832 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1834 delta_xy
[i
].file
= BAD_FILE
;
1843 * Assign UNIFORM file registers to either push constants or pull constants.
1845 * We allow a fragment shader to have more than the specified minimum
1846 * maximum number of fragment shader uniform components (64). If
1847 * there are too many of these, they'd fill up all of register space.
1848 * So, this will push some of them out to the pull constant buffer and
1849 * update the program to load them. We also use pull constants for all
1850 * indirect constant loads because we don't support indirect accesses in
1854 fs_visitor::assign_constant_locations()
1856 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1857 if (dispatch_width
!= 8)
1860 unsigned int num_pull_constants
= 0;
1862 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1863 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1865 bool is_live
[uniforms
];
1866 memset(is_live
, 0, sizeof(is_live
));
1868 /* First, we walk through the instructions and do two things:
1870 * 1) Figure out which uniforms are live.
1872 * 2) Find all indirect access of uniform arrays and flag them as needing
1873 * to go into the pull constant buffer.
1875 * Note that we don't move constant-indexed accesses to arrays. No
1876 * testing has been done of the performance impact of this choice.
1878 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1879 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1880 if (inst
->src
[i
].file
!= UNIFORM
)
1883 if (inst
->src
[i
].reladdr
) {
1884 int uniform
= inst
->src
[i
].nr
;
1886 /* If this array isn't already present in the pull constant buffer,
1889 if (pull_constant_loc
[uniform
] == -1) {
1890 assert(param_size
[uniform
]);
1891 for (int j
= 0; j
< param_size
[uniform
]; j
++)
1892 pull_constant_loc
[uniform
+ j
] = num_pull_constants
++;
1895 /* Mark the the one accessed uniform as live */
1896 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1897 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1898 is_live
[constant_nr
] = true;
1903 /* Only allow 16 registers (128 uniform components) as push constants.
1905 * Just demote the end of the list. We could probably do better
1906 * here, demoting things that are rarely used in the program first.
1908 * If changing this value, note the limitation about total_regs in
1911 unsigned int max_push_components
= 16 * 8;
1912 unsigned int num_push_constants
= 0;
1914 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1916 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1917 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1918 /* This UNIFORM register is either dead, or has already been demoted
1919 * to a pull const. Mark it as no longer living in the param[] array.
1921 push_constant_loc
[i
] = -1;
1925 if (num_push_constants
< max_push_components
) {
1926 /* Retain as a push constant. Record the location in the params[]
1929 push_constant_loc
[i
] = num_push_constants
++;
1931 /* Demote to a pull constant. */
1932 push_constant_loc
[i
] = -1;
1933 pull_constant_loc
[i
] = num_pull_constants
++;
1937 stage_prog_data
->nr_params
= num_push_constants
;
1938 stage_prog_data
->nr_pull_params
= num_pull_constants
;
1940 /* Up until now, the param[] array has been indexed by reg + reg_offset
1941 * of UNIFORM registers. Move pull constants into pull_param[] and
1942 * condense param[] to only contain the uniforms we chose to push.
1944 * NOTE: Because we are condensing the params[] array, we know that
1945 * push_constant_loc[i] <= i and we can do it in one smooth loop without
1946 * having to make a copy.
1948 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1949 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
1951 if (pull_constant_loc
[i
] != -1) {
1952 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
1953 } else if (push_constant_loc
[i
] != -1) {
1954 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
1960 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
1961 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
1964 fs_visitor::demote_pull_constants()
1966 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1967 for (int i
= 0; i
< inst
->sources
; i
++) {
1968 if (inst
->src
[i
].file
!= UNIFORM
)
1972 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1973 if (location
>= uniforms
) /* Out of bounds access */
1976 pull_index
= pull_constant_loc
[location
];
1978 if (pull_index
== -1)
1981 /* Set up the annotation tracking for new generated instructions. */
1982 const fs_builder
ibld(this, block
, inst
);
1983 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
1984 fs_reg dst
= vgrf(glsl_type::float_type
);
1986 assert(inst
->src
[i
].stride
== 0);
1988 /* Generate a pull load into dst. */
1989 if (inst
->src
[i
].reladdr
) {
1990 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
1992 *inst
->src
[i
].reladdr
,
1994 inst
->src
[i
].reladdr
= NULL
;
1995 inst
->src
[i
].stride
= 1;
1997 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
1998 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
1999 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2000 dst
, brw_imm_ud(index
), offset
);
2001 inst
->src
[i
].set_smear(pull_index
& 3);
2003 brw_mark_surface_used(prog_data
, index
);
2005 /* Rewrite the instruction to use the temporary VGRF. */
2006 inst
->src
[i
].file
= VGRF
;
2007 inst
->src
[i
].nr
= dst
.nr
;
2008 inst
->src
[i
].reg_offset
= 0;
2011 invalidate_live_intervals();
2015 fs_visitor::opt_algebraic()
2017 bool progress
= false;
2019 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2020 switch (inst
->opcode
) {
2021 case BRW_OPCODE_MOV
:
2022 if (inst
->src
[0].file
!= IMM
)
2025 if (inst
->saturate
) {
2026 if (inst
->dst
.type
!= inst
->src
[0].type
)
2027 assert(!"unimplemented: saturate mixed types");
2029 if (brw_saturate_immediate(inst
->dst
.type
,
2030 &inst
->src
[0].as_brw_reg())) {
2031 inst
->saturate
= false;
2037 case BRW_OPCODE_MUL
:
2038 if (inst
->src
[1].file
!= IMM
)
2042 if (inst
->src
[1].is_one()) {
2043 inst
->opcode
= BRW_OPCODE_MOV
;
2044 inst
->src
[1] = reg_undef
;
2050 if (inst
->src
[1].is_negative_one()) {
2051 inst
->opcode
= BRW_OPCODE_MOV
;
2052 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2053 inst
->src
[1] = reg_undef
;
2059 if (inst
->src
[1].is_zero()) {
2060 inst
->opcode
= BRW_OPCODE_MOV
;
2061 inst
->src
[0] = inst
->src
[1];
2062 inst
->src
[1] = reg_undef
;
2067 if (inst
->src
[0].file
== IMM
) {
2068 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2069 inst
->opcode
= BRW_OPCODE_MOV
;
2070 inst
->src
[0].f
*= inst
->src
[1].f
;
2071 inst
->src
[1] = reg_undef
;
2076 case BRW_OPCODE_ADD
:
2077 if (inst
->src
[1].file
!= IMM
)
2081 if (inst
->src
[1].is_zero()) {
2082 inst
->opcode
= BRW_OPCODE_MOV
;
2083 inst
->src
[1] = reg_undef
;
2088 if (inst
->src
[0].file
== IMM
) {
2089 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2090 inst
->opcode
= BRW_OPCODE_MOV
;
2091 inst
->src
[0].f
+= inst
->src
[1].f
;
2092 inst
->src
[1] = reg_undef
;
2098 if (inst
->src
[0].equals(inst
->src
[1])) {
2099 inst
->opcode
= BRW_OPCODE_MOV
;
2100 inst
->src
[1] = reg_undef
;
2105 case BRW_OPCODE_LRP
:
2106 if (inst
->src
[1].equals(inst
->src
[2])) {
2107 inst
->opcode
= BRW_OPCODE_MOV
;
2108 inst
->src
[0] = inst
->src
[1];
2109 inst
->src
[1] = reg_undef
;
2110 inst
->src
[2] = reg_undef
;
2115 case BRW_OPCODE_CMP
:
2116 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2118 inst
->src
[0].negate
&&
2119 inst
->src
[1].is_zero()) {
2120 inst
->src
[0].abs
= false;
2121 inst
->src
[0].negate
= false;
2122 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2127 case BRW_OPCODE_SEL
:
2128 if (inst
->src
[0].equals(inst
->src
[1])) {
2129 inst
->opcode
= BRW_OPCODE_MOV
;
2130 inst
->src
[1] = reg_undef
;
2131 inst
->predicate
= BRW_PREDICATE_NONE
;
2132 inst
->predicate_inverse
= false;
2134 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2135 switch (inst
->conditional_mod
) {
2136 case BRW_CONDITIONAL_LE
:
2137 case BRW_CONDITIONAL_L
:
2138 switch (inst
->src
[1].type
) {
2139 case BRW_REGISTER_TYPE_F
:
2140 if (inst
->src
[1].f
>= 1.0f
) {
2141 inst
->opcode
= BRW_OPCODE_MOV
;
2142 inst
->src
[1] = reg_undef
;
2143 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2151 case BRW_CONDITIONAL_GE
:
2152 case BRW_CONDITIONAL_G
:
2153 switch (inst
->src
[1].type
) {
2154 case BRW_REGISTER_TYPE_F
:
2155 if (inst
->src
[1].f
<= 0.0f
) {
2156 inst
->opcode
= BRW_OPCODE_MOV
;
2157 inst
->src
[1] = reg_undef
;
2158 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2170 case BRW_OPCODE_MAD
:
2171 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2172 inst
->opcode
= BRW_OPCODE_MOV
;
2173 inst
->src
[1] = reg_undef
;
2174 inst
->src
[2] = reg_undef
;
2176 } else if (inst
->src
[0].is_zero()) {
2177 inst
->opcode
= BRW_OPCODE_MUL
;
2178 inst
->src
[0] = inst
->src
[2];
2179 inst
->src
[2] = reg_undef
;
2181 } else if (inst
->src
[1].is_one()) {
2182 inst
->opcode
= BRW_OPCODE_ADD
;
2183 inst
->src
[1] = inst
->src
[2];
2184 inst
->src
[2] = reg_undef
;
2186 } else if (inst
->src
[2].is_one()) {
2187 inst
->opcode
= BRW_OPCODE_ADD
;
2188 inst
->src
[2] = reg_undef
;
2190 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2191 inst
->opcode
= BRW_OPCODE_ADD
;
2192 inst
->src
[1].f
*= inst
->src
[2].f
;
2193 inst
->src
[2] = reg_undef
;
2197 case SHADER_OPCODE_RCP
: {
2198 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2199 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2200 if (inst
->src
[0].equals(prev
->dst
)) {
2201 inst
->opcode
= SHADER_OPCODE_RSQ
;
2202 inst
->src
[0] = prev
->src
[0];
2208 case SHADER_OPCODE_BROADCAST
:
2209 if (is_uniform(inst
->src
[0])) {
2210 inst
->opcode
= BRW_OPCODE_MOV
;
2212 inst
->force_writemask_all
= true;
2214 } else if (inst
->src
[1].file
== IMM
) {
2215 inst
->opcode
= BRW_OPCODE_MOV
;
2216 inst
->src
[0] = component(inst
->src
[0],
2219 inst
->force_writemask_all
= true;
2228 /* Swap if src[0] is immediate. */
2229 if (progress
&& inst
->is_commutative()) {
2230 if (inst
->src
[0].file
== IMM
) {
2231 fs_reg tmp
= inst
->src
[1];
2232 inst
->src
[1] = inst
->src
[0];
2241 * Optimize sample messages that have constant zero values for the trailing
2242 * texture coordinates. We can just reduce the message length for these
2243 * instructions instead of reserving a register for it. Trailing parameters
2244 * that aren't sent default to zero anyway. This will cause the dead code
2245 * eliminator to remove the MOV instruction that would otherwise be emitted to
2246 * set up the zero value.
2249 fs_visitor::opt_zero_samples()
2251 /* Gen4 infers the texturing opcode based on the message length so we can't
2254 if (devinfo
->gen
< 5)
2257 bool progress
= false;
2259 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2260 if (!inst
->is_tex())
2263 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2265 if (load_payload
->is_head_sentinel() ||
2266 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2269 /* We don't want to remove the message header or the first parameter.
2270 * Removing the first parameter is not allowed, see the Haswell PRM
2271 * volume 7, page 149:
2273 * "Parameter 0 is required except for the sampleinfo message, which
2274 * has no parameter 0"
2276 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2277 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2278 (inst
->exec_size
/ 8) +
2279 inst
->header_size
- 1].is_zero()) {
2280 inst
->mlen
-= inst
->exec_size
/ 8;
2286 invalidate_live_intervals();
2292 * Optimize sample messages which are followed by the final RT write.
2294 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2295 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2296 * final texturing results copied to the framebuffer write payload and modify
2297 * them to write to the framebuffer directly.
2300 fs_visitor::opt_sampler_eot()
2302 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2304 if (stage
!= MESA_SHADER_FRAGMENT
)
2307 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2310 /* FINISHME: It should be possible to implement this optimization when there
2311 * are multiple drawbuffers.
2313 if (key
->nr_color_regions
!= 1)
2316 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2317 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2318 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2319 assert(fb_write
->eot
);
2320 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2322 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2324 /* There wasn't one; nothing to do. */
2325 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2328 /* 3D Sampler » Messages » Message Format
2330 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2331 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2333 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2334 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2335 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2336 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2337 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2340 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2341 * It's very likely to be the previous instruction.
2343 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2344 if (load_payload
->is_head_sentinel() ||
2345 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2348 assert(!tex_inst
->eot
); /* We can't get here twice */
2349 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2351 const fs_builder
ibld(this, block
, tex_inst
);
2353 tex_inst
->offset
|= fb_write
->target
<< 24;
2354 tex_inst
->eot
= true;
2355 tex_inst
->dst
= ibld
.null_reg_ud();
2356 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2358 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2359 * to create a new LOAD_PAYLOAD command with the same sources and a space
2360 * saved for the header. Using a new destination register not only makes sure
2361 * we have enough space, but it will make sure the dead code eliminator kills
2362 * the instruction that this will replace.
2364 if (tex_inst
->header_size
!= 0)
2367 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2368 load_payload
->sources
+ 1);
2369 fs_reg
*new_sources
=
2370 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2372 new_sources
[0] = fs_reg();
2373 for (int i
= 0; i
< load_payload
->sources
; i
++)
2374 new_sources
[i
+1] = load_payload
->src
[i
];
2376 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2377 * requires a lot of information about the sources to appropriately figure
2378 * out the number of registers needed to be used. Given this stage in our
2379 * optimization, we may not have the appropriate GRFs required by
2380 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2381 * manually emit the instruction.
2383 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2384 load_payload
->exec_size
,
2387 load_payload
->sources
+ 1);
2389 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2390 new_load_payload
->header_size
= 1;
2392 tex_inst
->header_size
= 1;
2393 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2394 tex_inst
->src
[0] = send_header
;
2400 fs_visitor::opt_register_renaming()
2402 bool progress
= false;
2405 int remap
[alloc
.count
];
2406 memset(remap
, -1, sizeof(int) * alloc
.count
);
2408 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2409 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2411 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2412 inst
->opcode
== BRW_OPCODE_WHILE
) {
2416 /* Rewrite instruction sources. */
2417 for (int i
= 0; i
< inst
->sources
; i
++) {
2418 if (inst
->src
[i
].file
== VGRF
&&
2419 remap
[inst
->src
[i
].nr
] != -1 &&
2420 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2421 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2426 const int dst
= inst
->dst
.nr
;
2429 inst
->dst
.file
== VGRF
&&
2430 alloc
.sizes
[inst
->dst
.nr
] == inst
->exec_size
/ 8 &&
2431 !inst
->is_partial_write()) {
2432 if (remap
[dst
] == -1) {
2435 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2436 inst
->dst
.nr
= remap
[dst
];
2439 } else if (inst
->dst
.file
== VGRF
&&
2441 remap
[dst
] != dst
) {
2442 inst
->dst
.nr
= remap
[dst
];
2448 invalidate_live_intervals();
2450 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2451 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2452 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2461 * Remove redundant or useless discard jumps.
2463 * For example, we can eliminate jumps in the following sequence:
2465 * discard-jump (redundant with the next jump)
2466 * discard-jump (useless; jumps to the next instruction)
2470 fs_visitor::opt_redundant_discard_jumps()
2472 bool progress
= false;
2474 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2476 fs_inst
*placeholder_halt
= NULL
;
2477 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2478 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2479 placeholder_halt
= inst
;
2484 if (!placeholder_halt
)
2487 /* Delete any HALTs immediately before the placeholder halt. */
2488 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2489 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2490 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2491 prev
->remove(last_bblock
);
2496 invalidate_live_intervals();
2502 fs_visitor::compute_to_mrf()
2504 bool progress
= false;
2507 /* No MRFs on Gen >= 7. */
2508 if (devinfo
->gen
>= 7)
2511 calculate_live_intervals();
2513 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2517 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2518 inst
->is_partial_write() ||
2519 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2520 inst
->dst
.type
!= inst
->src
[0].type
||
2521 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2522 !inst
->src
[0].is_contiguous() ||
2523 inst
->src
[0].subreg_offset
)
2526 /* Work out which hardware MRF registers are written by this
2529 int mrf_low
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2531 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2532 mrf_high
= mrf_low
+ 4;
2533 } else if (inst
->exec_size
== 16) {
2534 mrf_high
= mrf_low
+ 1;
2539 /* Can't compute-to-MRF this GRF if someone else was going to
2542 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2545 /* Found a move of a GRF to a MRF. Let's see if we can go
2546 * rewrite the thing that made this GRF to write into the MRF.
2548 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2549 if (scan_inst
->dst
.file
== VGRF
&&
2550 scan_inst
->dst
.nr
== inst
->src
[0].nr
) {
2551 /* Found the last thing to write our reg we want to turn
2552 * into a compute-to-MRF.
2555 /* If this one instruction didn't populate all the
2556 * channels, bail. We might be able to rewrite everything
2557 * that writes that reg, but it would require smarter
2558 * tracking to delay the rewriting until complete success.
2560 if (scan_inst
->is_partial_write())
2563 /* Things returning more than one register would need us to
2564 * understand coalescing out more than one MOV at a time.
2566 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2569 /* SEND instructions can't have MRF as a destination. */
2570 if (scan_inst
->mlen
)
2573 if (devinfo
->gen
== 6) {
2574 /* gen6 math instructions must have the destination be
2575 * GRF, so no compute-to-MRF for them.
2577 if (scan_inst
->is_math()) {
2582 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2583 /* Found the creator of our MRF's source value. */
2584 scan_inst
->dst
.file
= MRF
;
2585 scan_inst
->dst
.nr
= inst
->dst
.nr
;
2586 scan_inst
->saturate
|= inst
->saturate
;
2587 inst
->remove(block
);
2593 /* We don't handle control flow here. Most computation of
2594 * values that end up in MRFs are shortly before the MRF
2597 if (block
->start() == scan_inst
)
2600 /* You can't read from an MRF, so if someone else reads our
2601 * MRF's source GRF that we wanted to rewrite, that stops us.
2603 bool interfered
= false;
2604 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2605 if (scan_inst
->src
[i
].file
== VGRF
&&
2606 scan_inst
->src
[i
].nr
== inst
->src
[0].nr
&&
2607 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2614 if (scan_inst
->dst
.file
== MRF
) {
2615 /* If somebody else writes our MRF here, we can't
2616 * compute-to-MRF before that.
2618 int scan_mrf_low
= scan_inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2621 if (scan_inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2622 scan_mrf_high
= scan_mrf_low
+ 4;
2623 } else if (scan_inst
->exec_size
== 16) {
2624 scan_mrf_high
= scan_mrf_low
+ 1;
2626 scan_mrf_high
= scan_mrf_low
;
2629 if (mrf_low
== scan_mrf_low
||
2630 mrf_low
== scan_mrf_high
||
2631 mrf_high
== scan_mrf_low
||
2632 mrf_high
== scan_mrf_high
) {
2637 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2638 /* Found a SEND instruction, which means that there are
2639 * live values in MRFs from base_mrf to base_mrf +
2640 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2643 if (mrf_low
>= scan_inst
->base_mrf
&&
2644 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2647 if (mrf_high
>= scan_inst
->base_mrf
&&
2648 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2656 invalidate_live_intervals();
2662 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2663 * flow. We could probably do better here with some form of divergence
2667 fs_visitor::eliminate_find_live_channel()
2669 bool progress
= false;
2672 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2673 switch (inst
->opcode
) {
2679 case BRW_OPCODE_ENDIF
:
2680 case BRW_OPCODE_WHILE
:
2684 case FS_OPCODE_DISCARD_JUMP
:
2685 /* This can potentially make control flow non-uniform until the end
2690 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2692 inst
->opcode
= BRW_OPCODE_MOV
;
2693 inst
->src
[0] = brw_imm_ud(0u);
2695 inst
->force_writemask_all
= true;
2709 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2710 * instructions to FS_OPCODE_REP_FB_WRITE.
2713 fs_visitor::emit_repclear_shader()
2715 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2717 int color_mrf
= base_mrf
+ 2;
2719 fs_inst
*mov
= bld
.exec_all().group(4, 0)
2720 .MOV(brw_message_reg(color_mrf
),
2721 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2724 if (key
->nr_color_regions
== 1) {
2725 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2726 write
->saturate
= key
->clamp_fragment_color
;
2727 write
->base_mrf
= color_mrf
;
2729 write
->header_size
= 0;
2732 assume(key
->nr_color_regions
> 0);
2733 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2734 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2735 write
->saturate
= key
->clamp_fragment_color
;
2736 write
->base_mrf
= base_mrf
;
2738 write
->header_size
= 2;
2746 assign_constant_locations();
2747 assign_curb_setup();
2749 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2750 assert(mov
->src
[0].file
== FIXED_GRF
);
2751 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2755 * Walks through basic blocks, looking for repeated MRF writes and
2756 * removing the later ones.
2759 fs_visitor::remove_duplicate_mrf_writes()
2761 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2762 bool progress
= false;
2764 /* Need to update the MRF tracking for compressed instructions. */
2765 if (dispatch_width
== 16)
2768 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2770 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2771 if (inst
->is_control_flow()) {
2772 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2775 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2776 inst
->dst
.file
== MRF
) {
2777 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2778 if (prev_inst
&& inst
->equals(prev_inst
)) {
2779 inst
->remove(block
);
2785 /* Clear out the last-write records for MRFs that were overwritten. */
2786 if (inst
->dst
.file
== MRF
) {
2787 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2790 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2791 /* Found a SEND instruction, which will include two or fewer
2792 * implied MRF writes. We could do better here.
2794 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2795 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2799 /* Clear out any MRF move records whose sources got overwritten. */
2800 if (inst
->dst
.file
== VGRF
) {
2801 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2802 if (last_mrf_move
[i
] &&
2803 last_mrf_move
[i
]->src
[0].nr
== inst
->dst
.nr
) {
2804 last_mrf_move
[i
] = NULL
;
2809 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2810 inst
->dst
.file
== MRF
&&
2811 inst
->src
[0].file
== VGRF
&&
2812 !inst
->is_partial_write()) {
2813 last_mrf_move
[inst
->dst
.nr
] = inst
;
2818 invalidate_live_intervals();
2824 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2826 /* Clear the flag for registers that actually got read (as expected). */
2827 for (int i
= 0; i
< inst
->sources
; i
++) {
2829 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
2830 grf
= inst
->src
[i
].nr
;
2835 if (grf
>= first_grf
&&
2836 grf
< first_grf
+ grf_len
) {
2837 deps
[grf
- first_grf
] = false;
2838 if (inst
->exec_size
== 16)
2839 deps
[grf
- first_grf
+ 1] = false;
2845 * Implements this workaround for the original 965:
2847 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2848 * check for post destination dependencies on this instruction, software
2849 * must ensure that there is no destination hazard for the case of ‘write
2850 * followed by a posted write’ shown in the following example.
2853 * 2. send r3.xy <rest of send instruction>
2856 * Due to no post-destination dependency check on the ‘send’, the above
2857 * code sequence could have two instructions (1 and 2) in flight at the
2858 * same time that both consider ‘r3’ as the target of their final writes.
2861 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2864 int write_len
= inst
->regs_written
;
2865 int first_write_grf
= inst
->dst
.nr
;
2866 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2867 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2869 memset(needs_dep
, false, sizeof(needs_dep
));
2870 memset(needs_dep
, true, write_len
);
2872 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2874 /* Walk backwards looking for writes to registers we're writing which
2875 * aren't read since being written. If we hit the start of the program,
2876 * we assume that there are no outstanding dependencies on entry to the
2879 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2880 /* If we hit control flow, assume that there *are* outstanding
2881 * dependencies, and force their cleanup before our instruction.
2883 if (block
->start() == scan_inst
) {
2884 for (int i
= 0; i
< write_len
; i
++) {
2886 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
2887 first_write_grf
+ i
);
2892 /* We insert our reads as late as possible on the assumption that any
2893 * instruction but a MOV that might have left us an outstanding
2894 * dependency has more latency than a MOV.
2896 if (scan_inst
->dst
.file
== VGRF
) {
2897 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2898 int reg
= scan_inst
->dst
.nr
+ i
;
2900 if (reg
>= first_write_grf
&&
2901 reg
< first_write_grf
+ write_len
&&
2902 needs_dep
[reg
- first_write_grf
]) {
2903 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
2904 needs_dep
[reg
- first_write_grf
] = false;
2905 if (scan_inst
->exec_size
== 16)
2906 needs_dep
[reg
- first_write_grf
+ 1] = false;
2911 /* Clear the flag for registers that actually got read (as expected). */
2912 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2914 /* Continue the loop only if we haven't resolved all the dependencies */
2916 for (i
= 0; i
< write_len
; i
++) {
2926 * Implements this workaround for the original 965:
2928 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2929 * used as a destination register until after it has been sourced by an
2930 * instruction with a different destination register.
2933 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2935 int write_len
= inst
->regs_written
;
2936 int first_write_grf
= inst
->dst
.nr
;
2937 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2938 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2940 memset(needs_dep
, false, sizeof(needs_dep
));
2941 memset(needs_dep
, true, write_len
);
2942 /* Walk forwards looking for writes to registers we're writing which aren't
2943 * read before being written.
2945 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
2946 /* If we hit control flow, force resolve all remaining dependencies. */
2947 if (block
->end() == scan_inst
) {
2948 for (int i
= 0; i
< write_len
; i
++) {
2950 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2951 first_write_grf
+ i
);
2956 /* Clear the flag for registers that actually got read (as expected). */
2957 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2959 /* We insert our reads as late as possible since they're reading the
2960 * result of a SEND, which has massive latency.
2962 if (scan_inst
->dst
.file
== VGRF
&&
2963 scan_inst
->dst
.nr
>= first_write_grf
&&
2964 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
2965 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
2966 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2968 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
2971 /* Continue the loop only if we haven't resolved all the dependencies */
2973 for (i
= 0; i
< write_len
; i
++) {
2983 fs_visitor::insert_gen4_send_dependency_workarounds()
2985 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
2988 bool progress
= false;
2990 /* Note that we're done with register allocation, so GRF fs_regs always
2991 * have a .reg_offset of 0.
2994 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2995 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
2996 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
2997 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3003 invalidate_live_intervals();
3007 * Turns the generic expression-style uniform pull constant load instruction
3008 * into a hardware-specific series of instructions for loading a pull
3011 * The expression style allows the CSE pass before this to optimize out
3012 * repeated loads from the same offset, and gives the pre-register-allocation
3013 * scheduling full flexibility, while the conversion to native instructions
3014 * allows the post-register-allocation scheduler the best information
3017 * Note that execution masking for setting up pull constant loads is special:
3018 * the channels that need to be written are unrelated to the current execution
3019 * mask, since a later instruction will use one of the result channels as a
3020 * source operand for all 8 or 16 of its channels.
3023 fs_visitor::lower_uniform_pull_constant_loads()
3025 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3026 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3029 if (devinfo
->gen
>= 7) {
3030 /* The offset arg before was a vec4-aligned byte offset. We need to
3031 * turn it into a dword offset.
3033 fs_reg const_offset_reg
= inst
->src
[1];
3034 assert(const_offset_reg
.file
== IMM
&&
3035 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3036 const_offset_reg
.ud
/= 4;
3038 fs_reg payload
, offset
;
3039 if (devinfo
->gen
>= 9) {
3040 /* We have to use a message header on Skylake to get SIMD4x2
3041 * mode. Reserve space for the register.
3043 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3044 offset
.reg_offset
++;
3047 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3051 /* This is actually going to be a MOV, but since only the first dword
3052 * is accessed, we have a special opcode to do just that one. Note
3053 * that this needs to be an operation that will be considered a def
3054 * by live variable analysis, or register allocation will explode.
3056 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3057 8, offset
, const_offset_reg
);
3058 setup
->force_writemask_all
= true;
3060 setup
->ir
= inst
->ir
;
3061 setup
->annotation
= inst
->annotation
;
3062 inst
->insert_before(block
, setup
);
3064 /* Similarly, this will only populate the first 4 channels of the
3065 * result register (since we only use smear values from 0-3), but we
3066 * don't tell the optimizer.
3068 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3069 inst
->src
[1] = payload
;
3070 inst
->base_mrf
= -1;
3072 invalidate_live_intervals();
3074 /* Before register allocation, we didn't tell the scheduler about the
3075 * MRF we use. We know it's safe to use this MRF because nothing
3076 * else does except for register spill/unspill, which generates and
3077 * uses its MRF within a single IR instruction.
3079 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3086 fs_visitor::lower_load_payload()
3088 bool progress
= false;
3090 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3091 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3094 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3095 assert(inst
->saturate
== false);
3096 fs_reg dst
= inst
->dst
;
3098 /* Get rid of COMPR4. We'll add it back in if we need it */
3099 if (dst
.file
== MRF
)
3100 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3102 const fs_builder
ibld(this, block
, inst
);
3103 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3105 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3106 if (inst
->src
[i
].file
!= BAD_FILE
) {
3107 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3108 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3109 hbld
.MOV(mov_dst
, mov_src
);
3111 dst
= offset(dst
, hbld
, 1);
3114 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3115 inst
->exec_size
> 8) {
3116 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3117 * a straightforward copy. Instead, the result of the
3118 * LOAD_PAYLOAD is treated as interleaved and the first four
3119 * non-header sources are unpacked as:
3130 * This is used for gen <= 5 fb writes.
3132 assert(inst
->exec_size
== 16);
3133 assert(inst
->header_size
+ 4 <= inst
->sources
);
3134 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3135 if (inst
->src
[i
].file
!= BAD_FILE
) {
3136 if (devinfo
->has_compr4
) {
3137 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3138 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3139 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3141 /* Platform doesn't have COMPR4. We have to fake it */
3142 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3143 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3145 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3152 /* The loop above only ever incremented us through the first set
3153 * of 4 registers. However, thanks to the magic of COMPR4, we
3154 * actually wrote to the first 8 registers, so we need to take
3155 * that into account now.
3159 /* The COMPR4 code took care of the first 4 sources. We'll let
3160 * the regular path handle any remaining sources. Yes, we are
3161 * modifying the instruction but we're about to delete it so
3162 * this really doesn't hurt anything.
3164 inst
->header_size
+= 4;
3167 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3168 if (inst
->src
[i
].file
!= BAD_FILE
)
3169 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3170 dst
= offset(dst
, ibld
, 1);
3173 inst
->remove(block
);
3178 invalidate_live_intervals();
3184 fs_visitor::lower_integer_multiplication()
3186 bool progress
= false;
3188 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3189 const fs_builder
ibld(this, block
, inst
);
3191 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3192 if (inst
->dst
.is_accumulator() ||
3193 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3194 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3197 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3198 * operation directly, but CHV/BXT cannot.
3200 if (devinfo
->gen
>= 8 &&
3201 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3204 if (inst
->src
[1].file
== IMM
&&
3205 inst
->src
[1].ud
< (1 << 16)) {
3206 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3207 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3210 * If multiplying by an immediate value that fits in 16-bits, do a
3211 * single MUL instruction with that value in the proper location.
3213 if (devinfo
->gen
< 7) {
3214 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3216 ibld
.MOV(imm
, inst
->src
[1]);
3217 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3219 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3222 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3223 * do 32-bit integer multiplication in one instruction, but instead
3224 * must do a sequence (which actually calculates a 64-bit result):
3226 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3227 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3228 * mov(8) g2<1>D acc0<8,8,1>D
3230 * But on Gen > 6, the ability to use second accumulator register
3231 * (acc1) for non-float data types was removed, preventing a simple
3232 * implementation in SIMD16. A 16-channel result can be calculated by
3233 * executing the three instructions twice in SIMD8, once with quarter
3234 * control of 1Q for the first eight channels and again with 2Q for
3235 * the second eight channels.
3237 * Which accumulator register is implicitly accessed (by AccWrEnable
3238 * for instance) is determined by the quarter control. Unfortunately
3239 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3240 * implicit accumulator access by an instruction with 2Q will access
3241 * acc1 regardless of whether the data type is usable in acc1.
3243 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3244 * integer data types.
3246 * Since we only want the low 32-bits of the result, we can do two
3247 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3248 * adjust the high result and add them (like the mach is doing):
3250 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3251 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3252 * shl(8) g9<1>D g8<8,8,1>D 16D
3253 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3255 * We avoid the shl instruction by realizing that we only want to add
3256 * the low 16-bits of the "high" result to the high 16-bits of the
3257 * "low" result and using proper regioning on the add:
3259 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3260 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3261 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3263 * Since it does not use the (single) accumulator register, we can
3264 * schedule multi-component multiplications much better.
3267 fs_reg orig_dst
= inst
->dst
;
3268 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3269 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3272 fs_reg low
= inst
->dst
;
3273 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3276 if (devinfo
->gen
>= 7) {
3277 fs_reg src1_0_w
= inst
->src
[1];
3278 fs_reg src1_1_w
= inst
->src
[1];
3280 if (inst
->src
[1].file
== IMM
) {
3281 src1_0_w
.ud
&= 0xffff;
3284 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3285 if (src1_0_w
.stride
!= 0) {
3286 assert(src1_0_w
.stride
== 1);
3287 src1_0_w
.stride
= 2;
3290 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3291 if (src1_1_w
.stride
!= 0) {
3292 assert(src1_1_w
.stride
== 1);
3293 src1_1_w
.stride
= 2;
3295 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3297 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3298 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3300 fs_reg src0_0_w
= inst
->src
[0];
3301 fs_reg src0_1_w
= inst
->src
[0];
3303 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3304 if (src0_0_w
.stride
!= 0) {
3305 assert(src0_0_w
.stride
== 1);
3306 src0_0_w
.stride
= 2;
3309 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3310 if (src0_1_w
.stride
!= 0) {
3311 assert(src0_1_w
.stride
== 1);
3312 src0_1_w
.stride
= 2;
3314 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3316 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3317 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3320 fs_reg dst
= inst
->dst
;
3321 dst
.type
= BRW_REGISTER_TYPE_UW
;
3322 dst
.subreg_offset
= 2;
3325 high
.type
= BRW_REGISTER_TYPE_UW
;
3328 low
.type
= BRW_REGISTER_TYPE_UW
;
3329 low
.subreg_offset
= 2;
3332 ibld
.ADD(dst
, low
, high
);
3334 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3335 set_condmod(inst
->conditional_mod
,
3336 ibld
.MOV(orig_dst
, inst
->dst
));
3340 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3341 /* Should have been lowered to 8-wide. */
3342 assert(inst
->exec_size
<= 8);
3343 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3345 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3346 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3348 if (devinfo
->gen
>= 8) {
3349 /* Until Gen8, integer multiplies read 32-bits from one source,
3350 * and 16-bits from the other, and relying on the MACH instruction
3351 * to generate the high bits of the result.
3353 * On Gen8, the multiply instruction does a full 32x32-bit
3354 * multiply, but in order to do a 64-bit multiply we can simulate
3355 * the previous behavior and then use a MACH instruction.
3357 * FINISHME: Don't use source modifiers on src1.
3359 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3360 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3361 mul
->src
[1].type
= (type_is_signed(mul
->src
[1].type
) ?
3362 BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
3363 mul
->src
[1].stride
*= 2;
3365 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3366 inst
->force_sechalf
) {
3367 /* Among other things the quarter control bits influence which
3368 * accumulator register is used by the hardware for instructions
3369 * that access the accumulator implicitly (e.g. MACH). A
3370 * second-half instruction would normally map to acc1, which
3371 * doesn't exist on Gen7 and up (the hardware does emulate it for
3372 * floating-point instructions *only* by taking advantage of the
3373 * extra precision of acc0 not normally used for floating point
3376 * HSW and up are careful enough not to try to access an
3377 * accumulator register that doesn't exist, but on earlier Gen7
3378 * hardware we need to make sure that the quarter control bits are
3379 * zero to avoid non-deterministic behaviour and emit an extra MOV
3380 * to get the result masked correctly according to the current
3383 mach
->force_sechalf
= false;
3384 mach
->force_writemask_all
= true;
3385 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3386 ibld
.MOV(inst
->dst
, mach
->dst
);
3392 inst
->remove(block
);
3397 invalidate_live_intervals();
3403 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3404 fs_reg
*dst
, fs_reg color
, unsigned components
)
3406 if (key
->clamp_fragment_color
) {
3407 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3408 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3410 for (unsigned i
= 0; i
< components
; i
++)
3412 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3417 for (unsigned i
= 0; i
< components
; i
++)
3418 dst
[i
] = offset(color
, bld
, i
);
3422 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3423 const brw_wm_prog_data
*prog_data
,
3424 const brw_wm_prog_key
*key
,
3425 const fs_visitor::thread_payload
&payload
)
3427 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3428 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3429 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3430 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3431 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3432 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3433 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3434 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3435 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3436 const unsigned components
=
3437 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3439 /* We can potentially have a message length of up to 15, so we have to set
3440 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3443 int header_size
= 2, payload_header_size
;
3444 unsigned length
= 0;
3446 /* From the Sandy Bridge PRM, volume 4, page 198:
3448 * "Dispatched Pixel Enables. One bit per pixel indicating
3449 * which pixels were originally enabled when the thread was
3450 * dispatched. This field is only required for the end-of-
3451 * thread message and on all dual-source messages."
3453 if (devinfo
->gen
>= 6 &&
3454 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3455 color1
.file
== BAD_FILE
&&
3456 key
->nr_color_regions
== 1) {
3460 if (header_size
!= 0) {
3461 assert(header_size
== 2);
3462 /* Allocate 2 registers for a header */
3466 if (payload
.aa_dest_stencil_reg
) {
3467 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3468 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3469 .MOV(sources
[length
],
3470 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3474 if (prog_data
->uses_omask
) {
3475 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3476 BRW_REGISTER_TYPE_UD
);
3478 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3479 * relevant. Since it's unsigned single words one vgrf is always
3480 * 16-wide, but only the lower or higher 8 channels will be used by the
3481 * hardware when doing a SIMD8 write depending on whether we have
3482 * selected the subspans for the first or second half respectively.
3484 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3485 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3486 sample_mask
.stride
*= 2;
3488 bld
.exec_all().annotate("FB write oMask")
3489 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3490 inst
->force_sechalf
),
3495 payload_header_size
= length
;
3497 if (src0_alpha
.file
!= BAD_FILE
) {
3498 /* FIXME: This is being passed at the wrong location in the payload and
3499 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3500 * It's supposed to be immediately before oMask but there seems to be no
3501 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3502 * requires header sources to form a contiguous segment at the beginning
3503 * of the message and src0_alpha has per-channel semantics.
3505 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3509 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3512 if (color1
.file
!= BAD_FILE
) {
3513 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3517 if (src_depth
.file
!= BAD_FILE
) {
3518 sources
[length
] = src_depth
;
3522 if (dst_depth
.file
!= BAD_FILE
) {
3523 sources
[length
] = dst_depth
;
3527 if (src_stencil
.file
!= BAD_FILE
) {
3528 assert(devinfo
->gen
>= 9);
3529 assert(bld
.dispatch_width() != 16);
3531 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3532 * available on gen9+. As such it's impossible to have both enabled at the
3533 * same time and therefore length cannot overrun the array.
3535 assert(length
< 15);
3537 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3538 bld
.exec_all().annotate("FB write OS")
3539 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3540 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3545 if (devinfo
->gen
>= 7) {
3546 /* Send from the GRF */
3547 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3548 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3549 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3550 load
->dst
= payload
;
3552 inst
->src
[0] = payload
;
3553 inst
->resize_sources(1);
3554 inst
->base_mrf
= -1;
3556 /* Send from the MRF */
3557 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3558 sources
, length
, payload_header_size
);
3560 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3561 * will do this for us if we just give it a COMPR4 destination.
3563 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3564 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3566 inst
->resize_sources(0);
3570 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3571 inst
->mlen
= load
->regs_written
;
3572 inst
->header_size
= header_size
;
3576 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3577 const fs_reg
&coordinate
,
3578 const fs_reg
&shadow_c
,
3579 const fs_reg
&lod
, const fs_reg
&lod2
,
3580 const fs_reg
&sampler
,
3581 unsigned coord_components
,
3582 unsigned grad_components
)
3584 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3585 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3586 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3587 fs_reg msg_end
= msg_begin
;
3590 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3592 for (unsigned i
= 0; i
< coord_components
; i
++)
3593 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3594 offset(coordinate
, bld
, i
));
3596 msg_end
= offset(msg_end
, bld
, coord_components
);
3598 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3599 * require all three components to be present and zero if they are unused.
3601 if (coord_components
> 0 &&
3602 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3603 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3604 for (unsigned i
= coord_components
; i
< 3; i
++)
3605 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3607 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3610 if (op
== SHADER_OPCODE_TXD
) {
3611 /* TXD unsupported in SIMD16 mode. */
3612 assert(bld
.dispatch_width() == 8);
3614 /* the slots for u and v are always present, but r is optional */
3615 if (coord_components
< 2)
3616 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3619 * dPdx = dudx, dvdx, drdx
3620 * dPdy = dudy, dvdy, drdy
3622 * 1-arg: Does not exist.
3624 * 2-arg: dudx dvdx dudy dvdy
3625 * dPdx.x dPdx.y dPdy.x dPdy.y
3628 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3629 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3630 * m5 m6 m7 m8 m9 m10
3632 for (unsigned i
= 0; i
< grad_components
; i
++)
3633 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3635 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3637 for (unsigned i
= 0; i
< grad_components
; i
++)
3638 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3640 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3644 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3645 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3647 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3648 bld
.dispatch_width() == 16);
3650 const brw_reg_type type
=
3651 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3652 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3653 bld
.MOV(retype(msg_end
, type
), lod
);
3654 msg_end
= offset(msg_end
, bld
, 1);
3657 if (shadow_c
.file
!= BAD_FILE
) {
3658 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3659 /* There's no plain shadow compare message, so we use shadow
3660 * compare with a bias of 0.0.
3662 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3663 msg_end
= offset(msg_end
, bld
, 1);
3666 bld
.MOV(msg_end
, shadow_c
);
3667 msg_end
= offset(msg_end
, bld
, 1);
3671 inst
->src
[0] = reg_undef
;
3672 inst
->src
[1] = sampler
;
3673 inst
->resize_sources(2);
3674 inst
->base_mrf
= msg_begin
.nr
;
3675 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3676 inst
->header_size
= 1;
3680 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3682 const fs_reg
&shadow_c
,
3683 fs_reg lod
, fs_reg lod2
,
3684 const fs_reg
&sample_index
,
3685 const fs_reg
&sampler
,
3686 const fs_reg
&offset_value
,
3687 unsigned coord_components
,
3688 unsigned grad_components
)
3690 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3691 fs_reg msg_coords
= message
;
3692 unsigned header_size
= 0;
3694 if (offset_value
.file
!= BAD_FILE
) {
3695 /* The offsets set up by the visitor are in the m1 header, so we can't
3702 for (unsigned i
= 0; i
< coord_components
; i
++) {
3703 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3704 coordinate
= offset(coordinate
, bld
, 1);
3706 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3707 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3709 if (shadow_c
.file
!= BAD_FILE
) {
3710 fs_reg msg_shadow
= msg_lod
;
3711 bld
.MOV(msg_shadow
, shadow_c
);
3712 msg_lod
= offset(msg_shadow
, bld
, 1);
3717 case SHADER_OPCODE_TXL
:
3719 bld
.MOV(msg_lod
, lod
);
3720 msg_end
= offset(msg_lod
, bld
, 1);
3722 case SHADER_OPCODE_TXD
:
3725 * dPdx = dudx, dvdx, drdx
3726 * dPdy = dudy, dvdy, drdy
3728 * Load up these values:
3729 * - dudx dudy dvdx dvdy drdx drdy
3730 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3733 for (unsigned i
= 0; i
< grad_components
; i
++) {
3734 bld
.MOV(msg_end
, lod
);
3735 lod
= offset(lod
, bld
, 1);
3736 msg_end
= offset(msg_end
, bld
, 1);
3738 bld
.MOV(msg_end
, lod2
);
3739 lod2
= offset(lod2
, bld
, 1);
3740 msg_end
= offset(msg_end
, bld
, 1);
3743 case SHADER_OPCODE_TXS
:
3744 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3745 bld
.MOV(msg_lod
, lod
);
3746 msg_end
= offset(msg_lod
, bld
, 1);
3748 case SHADER_OPCODE_TXF
:
3749 msg_lod
= offset(msg_coords
, bld
, 3);
3750 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3751 msg_end
= offset(msg_lod
, bld
, 1);
3753 case SHADER_OPCODE_TXF_CMS
:
3754 msg_lod
= offset(msg_coords
, bld
, 3);
3756 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3758 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3759 msg_end
= offset(msg_lod
, bld
, 2);
3766 inst
->src
[0] = reg_undef
;
3767 inst
->src
[1] = sampler
;
3768 inst
->resize_sources(2);
3769 inst
->base_mrf
= message
.nr
;
3770 inst
->mlen
= msg_end
.nr
- message
.nr
;
3771 inst
->header_size
= header_size
;
3773 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3774 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3778 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3780 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3783 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
3787 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3789 const fs_reg
&shadow_c
,
3790 fs_reg lod
, fs_reg lod2
,
3791 const fs_reg
&sample_index
,
3792 const fs_reg
&mcs
, const fs_reg
&sampler
,
3793 fs_reg offset_value
,
3794 unsigned coord_components
,
3795 unsigned grad_components
)
3797 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3798 int reg_width
= bld
.dispatch_width() / 8;
3799 unsigned header_size
= 0, length
= 0;
3800 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3801 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3802 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3804 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3805 offset_value
.file
!= BAD_FILE
||
3806 is_high_sampler(devinfo
, sampler
)) {
3807 /* For general texture offsets (no txf workaround), we need a header to
3808 * put them in. Note that we're only reserving space for it in the
3809 * message payload as it will be initialized implicitly by the
3812 * TG4 needs to place its channel select in the header, for interaction
3813 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3814 * larger sampler numbers we need to offset the Sampler State Pointer in
3818 sources
[0] = fs_reg();
3822 if (shadow_c
.file
!= BAD_FILE
) {
3823 bld
.MOV(sources
[length
], shadow_c
);
3827 bool coordinate_done
= false;
3829 /* The sampler can only meaningfully compute LOD for fragment shader
3830 * messages. For all other stages, we change the opcode to TXL and
3831 * hardcode the LOD to 0.
3833 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3834 op
== SHADER_OPCODE_TEX
) {
3835 op
= SHADER_OPCODE_TXL
;
3836 lod
= brw_imm_f(0.0f
);
3839 /* Set up the LOD info */
3842 case SHADER_OPCODE_TXL
:
3843 bld
.MOV(sources
[length
], lod
);
3846 case SHADER_OPCODE_TXD
:
3847 /* TXD should have been lowered in SIMD16 mode. */
3848 assert(bld
.dispatch_width() == 8);
3850 /* Load dPdx and the coordinate together:
3851 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3853 for (unsigned i
= 0; i
< coord_components
; i
++) {
3854 bld
.MOV(sources
[length
], coordinate
);
3855 coordinate
= offset(coordinate
, bld
, 1);
3858 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3859 * only derivatives for (u, v, r).
3861 if (i
< grad_components
) {
3862 bld
.MOV(sources
[length
], lod
);
3863 lod
= offset(lod
, bld
, 1);
3866 bld
.MOV(sources
[length
], lod2
);
3867 lod2
= offset(lod2
, bld
, 1);
3872 coordinate_done
= true;
3874 case SHADER_OPCODE_TXS
:
3875 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3878 case SHADER_OPCODE_TXF
:
3879 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3880 * On Gen9 they are u, v, lod, r
3882 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3883 coordinate
= offset(coordinate
, bld
, 1);
3886 if (devinfo
->gen
>= 9) {
3887 if (coord_components
>= 2) {
3888 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3889 coordinate
= offset(coordinate
, bld
, 1);
3894 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
3897 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
3898 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3899 coordinate
= offset(coordinate
, bld
, 1);
3903 coordinate_done
= true;
3905 case SHADER_OPCODE_TXF_CMS
:
3906 case SHADER_OPCODE_TXF_CMS_W
:
3907 case SHADER_OPCODE_TXF_UMS
:
3908 case SHADER_OPCODE_TXF_MCS
:
3909 if (op
== SHADER_OPCODE_TXF_UMS
||
3910 op
== SHADER_OPCODE_TXF_CMS
||
3911 op
== SHADER_OPCODE_TXF_CMS_W
) {
3912 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
3916 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
3917 /* Data from the multisample control surface. */
3918 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
3921 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
3924 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
3925 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
3928 offset(mcs
, bld
, 1));
3933 /* There is no offsetting for this message; just copy in the integer
3934 * texture coordinates.
3936 for (unsigned i
= 0; i
< coord_components
; i
++) {
3937 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3938 coordinate
= offset(coordinate
, bld
, 1);
3942 coordinate_done
= true;
3944 case SHADER_OPCODE_TG4_OFFSET
:
3945 /* gather4_po_c should have been lowered in SIMD16 mode. */
3946 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
3948 /* More crazy intermixing */
3949 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
3950 bld
.MOV(sources
[length
], coordinate
);
3951 coordinate
= offset(coordinate
, bld
, 1);
3955 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
3956 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
3957 offset_value
= offset(offset_value
, bld
, 1);
3961 if (coord_components
== 3) { /* r if present */
3962 bld
.MOV(sources
[length
], coordinate
);
3963 coordinate
= offset(coordinate
, bld
, 1);
3967 coordinate_done
= true;
3973 /* Set up the coordinate (except for cases where it was done above) */
3974 if (!coordinate_done
) {
3975 for (unsigned i
= 0; i
< coord_components
; i
++) {
3976 bld
.MOV(sources
[length
], coordinate
);
3977 coordinate
= offset(coordinate
, bld
, 1);
3984 mlen
= length
* reg_width
- header_size
;
3986 mlen
= length
* reg_width
;
3988 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
3989 BRW_REGISTER_TYPE_F
);
3990 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
3992 /* Generate the SEND. */
3994 inst
->src
[0] = src_payload
;
3995 inst
->src
[1] = sampler
;
3996 inst
->resize_sources(2);
3997 inst
->base_mrf
= -1;
3999 inst
->header_size
= header_size
;
4001 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4002 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4006 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4008 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4009 const fs_reg
&coordinate
= inst
->src
[0];
4010 const fs_reg
&shadow_c
= inst
->src
[1];
4011 const fs_reg
&lod
= inst
->src
[2];
4012 const fs_reg
&lod2
= inst
->src
[3];
4013 const fs_reg
&sample_index
= inst
->src
[4];
4014 const fs_reg
&mcs
= inst
->src
[5];
4015 const fs_reg
&sampler
= inst
->src
[6];
4016 const fs_reg
&offset_value
= inst
->src
[7];
4017 assert(inst
->src
[8].file
== IMM
&& inst
->src
[9].file
== IMM
);
4018 const unsigned coord_components
= inst
->src
[8].ud
;
4019 const unsigned grad_components
= inst
->src
[9].ud
;
4021 if (devinfo
->gen
>= 7) {
4022 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4023 shadow_c
, lod
, lod2
, sample_index
,
4024 mcs
, sampler
, offset_value
,
4025 coord_components
, grad_components
);
4026 } else if (devinfo
->gen
>= 5) {
4027 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4028 shadow_c
, lod
, lod2
, sample_index
,
4029 sampler
, offset_value
,
4030 coord_components
, grad_components
);
4032 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4033 shadow_c
, lod
, lod2
, sampler
,
4034 coord_components
, grad_components
);
4039 * Initialize the header present in some typed and untyped surface
4043 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4045 fs_builder ubld
= bld
.exec_all().group(8, 0);
4046 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4047 ubld
.MOV(dst
, brw_imm_d(0));
4048 ubld
.MOV(component(dst
, 7), sample_mask
);
4053 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4054 const fs_reg
&sample_mask
)
4056 /* Get the logical send arguments. */
4057 const fs_reg
&addr
= inst
->src
[0];
4058 const fs_reg
&src
= inst
->src
[1];
4059 const fs_reg
&surface
= inst
->src
[2];
4060 const UNUSED fs_reg
&dims
= inst
->src
[3];
4061 const fs_reg
&arg
= inst
->src
[4];
4063 /* Calculate the total number of components of the payload. */
4064 const unsigned addr_sz
= inst
->components_read(0);
4065 const unsigned src_sz
= inst
->components_read(1);
4066 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4067 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4069 /* Allocate space for the payload. */
4070 fs_reg
*const components
= new fs_reg
[sz
];
4071 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4074 /* Construct the payload. */
4076 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4078 for (unsigned i
= 0; i
< addr_sz
; i
++)
4079 components
[n
++] = offset(addr
, bld
, i
);
4081 for (unsigned i
= 0; i
< src_sz
; i
++)
4082 components
[n
++] = offset(src
, bld
, i
);
4084 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4086 /* Update the original instruction. */
4088 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4089 inst
->header_size
= header_sz
;
4091 inst
->src
[0] = payload
;
4092 inst
->src
[1] = surface
;
4094 inst
->resize_sources(3);
4096 delete[] components
;
4100 fs_visitor::lower_logical_sends()
4102 bool progress
= false;
4104 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4105 const fs_builder
ibld(this, block
, inst
);
4107 switch (inst
->opcode
) {
4108 case FS_OPCODE_FB_WRITE_LOGICAL
:
4109 assert(stage
== MESA_SHADER_FRAGMENT
);
4110 lower_fb_write_logical_send(ibld
, inst
,
4111 (const brw_wm_prog_data
*)prog_data
,
4112 (const brw_wm_prog_key
*)key
,
4116 case SHADER_OPCODE_TEX_LOGICAL
:
4117 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4120 case SHADER_OPCODE_TXD_LOGICAL
:
4121 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4124 case SHADER_OPCODE_TXF_LOGICAL
:
4125 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4128 case SHADER_OPCODE_TXL_LOGICAL
:
4129 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4132 case SHADER_OPCODE_TXS_LOGICAL
:
4133 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4136 case FS_OPCODE_TXB_LOGICAL
:
4137 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4140 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4141 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4144 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4145 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4148 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4149 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4152 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4153 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4156 case SHADER_OPCODE_LOD_LOGICAL
:
4157 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4160 case SHADER_OPCODE_TG4_LOGICAL
:
4161 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4164 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4165 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4168 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4169 lower_surface_logical_send(ibld
, inst
,
4170 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4174 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4175 lower_surface_logical_send(ibld
, inst
,
4176 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4177 ibld
.sample_mask_reg());
4180 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4181 lower_surface_logical_send(ibld
, inst
,
4182 SHADER_OPCODE_UNTYPED_ATOMIC
,
4183 ibld
.sample_mask_reg());
4186 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4187 lower_surface_logical_send(ibld
, inst
,
4188 SHADER_OPCODE_TYPED_SURFACE_READ
,
4192 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4193 lower_surface_logical_send(ibld
, inst
,
4194 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4195 ibld
.sample_mask_reg());
4198 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4199 lower_surface_logical_send(ibld
, inst
,
4200 SHADER_OPCODE_TYPED_ATOMIC
,
4201 ibld
.sample_mask_reg());
4212 invalidate_live_intervals();
4218 * Get the closest native SIMD width supported by the hardware for instruction
4219 * \p inst. The instruction will be left untouched by
4220 * fs_visitor::lower_simd_width() if the returned value is equal to the
4221 * original execution size.
4224 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4225 const fs_inst
*inst
)
4227 switch (inst
->opcode
) {
4228 case BRW_OPCODE_MOV
:
4229 case BRW_OPCODE_SEL
:
4230 case BRW_OPCODE_NOT
:
4231 case BRW_OPCODE_AND
:
4233 case BRW_OPCODE_XOR
:
4234 case BRW_OPCODE_SHR
:
4235 case BRW_OPCODE_SHL
:
4236 case BRW_OPCODE_ASR
:
4237 case BRW_OPCODE_CMP
:
4238 case BRW_OPCODE_CMPN
:
4239 case BRW_OPCODE_CSEL
:
4240 case BRW_OPCODE_F32TO16
:
4241 case BRW_OPCODE_F16TO32
:
4242 case BRW_OPCODE_BFREV
:
4243 case BRW_OPCODE_BFE
:
4244 case BRW_OPCODE_BFI1
:
4245 case BRW_OPCODE_BFI2
:
4246 case BRW_OPCODE_ADD
:
4247 case BRW_OPCODE_MUL
:
4248 case BRW_OPCODE_AVG
:
4249 case BRW_OPCODE_FRC
:
4250 case BRW_OPCODE_RNDU
:
4251 case BRW_OPCODE_RNDD
:
4252 case BRW_OPCODE_RNDE
:
4253 case BRW_OPCODE_RNDZ
:
4254 case BRW_OPCODE_LZD
:
4255 case BRW_OPCODE_FBH
:
4256 case BRW_OPCODE_FBL
:
4257 case BRW_OPCODE_CBIT
:
4258 case BRW_OPCODE_SAD2
:
4259 case BRW_OPCODE_MAD
:
4260 case BRW_OPCODE_LRP
:
4261 case SHADER_OPCODE_RCP
:
4262 case SHADER_OPCODE_RSQ
:
4263 case SHADER_OPCODE_SQRT
:
4264 case SHADER_OPCODE_EXP2
:
4265 case SHADER_OPCODE_LOG2
:
4266 case SHADER_OPCODE_POW
:
4267 case SHADER_OPCODE_INT_QUOTIENT
:
4268 case SHADER_OPCODE_INT_REMAINDER
:
4269 case SHADER_OPCODE_SIN
:
4270 case SHADER_OPCODE_COS
: {
4271 /* According to the PRMs:
4272 * "A. In Direct Addressing mode, a source cannot span more than 2
4273 * adjacent GRF registers.
4274 * B. A destination cannot span more than 2 adjacent GRF registers."
4276 * Look for the source or destination with the largest register region
4277 * which is the one that is going to limit the overal execution size of
4278 * the instruction due to this rule.
4280 unsigned reg_count
= inst
->regs_written
;
4282 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4283 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4285 /* Calculate the maximum execution size of the instruction based on the
4286 * factor by which it goes over the hardware limit of 2 GRFs.
4288 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4290 case SHADER_OPCODE_MULH
:
4291 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4292 * is 8-wide on Gen7+.
4294 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4296 case FS_OPCODE_FB_WRITE_LOGICAL
:
4297 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4300 assert(devinfo
->gen
!= 6 ||
4301 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4302 inst
->exec_size
== 8);
4303 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4304 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4305 8 : inst
->exec_size
);
4307 case SHADER_OPCODE_TXD_LOGICAL
:
4308 /* TXD is unsupported in SIMD16 mode. */
4311 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4312 /* gather4_po_c is unsupported in SIMD16 mode. */
4313 const fs_reg
&shadow_c
= inst
->src
[1];
4314 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4316 case SHADER_OPCODE_TXL_LOGICAL
:
4317 case FS_OPCODE_TXB_LOGICAL
: {
4318 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4319 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4320 * mode because the message exceeds the maximum length of 11.
4322 const fs_reg
&shadow_c
= inst
->src
[1];
4323 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4325 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4328 return inst
->exec_size
;
4330 case SHADER_OPCODE_TXF_LOGICAL
:
4331 case SHADER_OPCODE_TXS_LOGICAL
:
4332 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4333 * messages. Use SIMD16 instead.
4335 if (devinfo
->gen
== 4)
4338 return inst
->exec_size
;
4340 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4341 /* This opcode can take up to 6 arguments which means that in some
4342 * circumstances it can end up with a message that is too long in SIMD16
4345 const unsigned coord_components
= inst
->src
[8].ud
;
4346 /* First three arguments are the sample index and the two arguments for
4349 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4352 return inst
->exec_size
;
4355 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4356 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4357 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4361 return inst
->exec_size
;
4366 * The \p rows array of registers represents a \p num_rows by \p num_columns
4367 * matrix in row-major order, write it in column-major order into the register
4368 * passed as destination. \p stride gives the separation between matrix
4369 * elements in the input in fs_builder::dispatch_width() units.
4372 emit_transpose(const fs_builder
&bld
,
4373 const fs_reg
&dst
, const fs_reg
*rows
,
4374 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4376 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4378 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4379 for (unsigned j
= 0; j
< num_rows
; ++j
)
4380 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4383 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4385 delete[] components
;
4389 fs_visitor::lower_simd_width()
4391 bool progress
= false;
4393 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4394 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4396 if (lower_width
!= inst
->exec_size
) {
4397 /* Builder matching the original instruction. We may also need to
4398 * emit an instruction of width larger than the original, set the
4399 * execution size of the builder to the highest of both for now so
4400 * we're sure that both cases can be handled.
4402 const fs_builder ibld
= bld
.at(block
, inst
)
4403 .exec_all(inst
->force_writemask_all
)
4404 .group(MAX2(inst
->exec_size
, lower_width
),
4405 inst
->force_sechalf
);
4407 /* Split the copies in chunks of the execution width of either the
4408 * original or the lowered instruction, whichever is lower.
4410 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4411 const unsigned n
= inst
->exec_size
/ copy_width
;
4412 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4413 inst
->dst
.component_size(inst
->exec_size
);
4416 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4417 !inst
->writes_accumulator
&& !inst
->mlen
);
4419 for (unsigned i
= 0; i
< n
; i
++) {
4420 /* Emit a copy of the original instruction with the lowered width.
4421 * If the EOT flag was set throw it away except for the last
4422 * instruction to avoid killing the thread prematurely.
4424 fs_inst split_inst
= *inst
;
4425 split_inst
.exec_size
= lower_width
;
4426 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4428 /* Select the correct channel enables for the i-th group, then
4429 * transform the sources and destination and emit the lowered
4432 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4434 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4435 if (inst
->src
[j
].file
!= BAD_FILE
&&
4436 !is_uniform(inst
->src
[j
])) {
4437 /* Get the i-th copy_width-wide chunk of the source. */
4438 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4439 const unsigned src_size
= inst
->components_read(j
);
4441 /* Use a trivial transposition to copy one every n
4442 * copy_width-wide components of the register into a
4443 * temporary passed as source to the lowered instruction.
4445 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4446 emit_transpose(lbld
.group(copy_width
, 0),
4447 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4451 if (inst
->regs_written
) {
4452 /* Allocate enough space to hold the result of the lowered
4453 * instruction and fix up the number of registers written.
4455 split_inst
.dst
= dsts
[i
] =
4456 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4457 split_inst
.regs_written
=
4458 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4462 lbld
.emit(split_inst
);
4465 if (inst
->regs_written
) {
4466 /* Distance between useful channels in the temporaries, skipping
4467 * garbage if the lowered instruction is wider than the original.
4469 const unsigned m
= lower_width
/ copy_width
;
4471 /* Interleave the components of the result from the lowered
4472 * instructions. We need to set exec_all() when copying more than
4473 * one half per component, because LOAD_PAYLOAD (in terms of which
4474 * emit_transpose is implemented) can only use the same channel
4475 * enable signals for all of its non-header sources.
4477 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4478 .group(copy_width
, 0),
4479 inst
->dst
, dsts
, n
, dst_size
, m
);
4482 inst
->remove(block
);
4488 invalidate_live_intervals();
4494 fs_visitor::dump_instructions()
4496 dump_instructions(NULL
);
4500 fs_visitor::dump_instructions(const char *name
)
4502 FILE *file
= stderr
;
4503 if (name
&& geteuid() != 0) {
4504 file
= fopen(name
, "w");
4510 calculate_register_pressure();
4511 int ip
= 0, max_pressure
= 0;
4512 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4513 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4514 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4515 dump_instruction(inst
, file
);
4518 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4521 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4522 fprintf(file
, "%4d: ", ip
++);
4523 dump_instruction(inst
, file
);
4527 if (file
!= stderr
) {
4533 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4535 dump_instruction(be_inst
, stderr
);
4539 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4541 fs_inst
*inst
= (fs_inst
*)be_inst
;
4543 if (inst
->predicate
) {
4544 fprintf(file
, "(%cf0.%d) ",
4545 inst
->predicate_inverse
? '-' : '+',
4549 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4551 fprintf(file
, ".sat");
4552 if (inst
->conditional_mod
) {
4553 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4554 if (!inst
->predicate
&&
4555 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4556 inst
->opcode
!= BRW_OPCODE_IF
&&
4557 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4558 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4561 fprintf(file
, "(%d) ", inst
->exec_size
);
4564 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4567 switch (inst
->dst
.file
) {
4569 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
4570 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
4571 inst
->dst
.subreg_offset
)
4572 fprintf(file
, "+%d.%d",
4573 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4576 fprintf(file
, "g%d", inst
->dst
.nr
);
4579 fprintf(file
, "m%d", inst
->dst
.nr
);
4582 fprintf(file
, "(null)");
4585 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4588 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4591 switch (inst
->dst
.nr
) {
4593 fprintf(file
, "null");
4595 case BRW_ARF_ADDRESS
:
4596 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
4598 case BRW_ARF_ACCUMULATOR
:
4599 fprintf(file
, "acc%d", inst
->dst
.subnr
);
4602 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4605 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4608 if (inst
->dst
.subnr
)
4609 fprintf(file
, "+%d", inst
->dst
.subnr
);
4612 unreachable("not reached");
4614 if (inst
->dst
.stride
!= 1)
4615 fprintf(file
, "<%u>", inst
->dst
.stride
);
4616 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4618 for (int i
= 0; i
< inst
->sources
; i
++) {
4619 if (inst
->src
[i
].negate
)
4621 if (inst
->src
[i
].abs
)
4623 switch (inst
->src
[i
].file
) {
4625 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
4626 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
4627 inst
->src
[i
].subreg_offset
)
4628 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4629 inst
->src
[i
].subreg_offset
);
4632 fprintf(file
, "g%d", inst
->src
[i
].nr
);
4635 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
4638 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
4641 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
4642 if (inst
->src
[i
].reladdr
) {
4643 fprintf(file
, "+reladdr");
4644 } else if (inst
->src
[i
].subreg_offset
) {
4645 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4646 inst
->src
[i
].subreg_offset
);
4650 fprintf(file
, "(null)");
4653 switch (inst
->src
[i
].type
) {
4654 case BRW_REGISTER_TYPE_F
:
4655 fprintf(file
, "%ff", inst
->src
[i
].f
);
4657 case BRW_REGISTER_TYPE_W
:
4658 case BRW_REGISTER_TYPE_D
:
4659 fprintf(file
, "%dd", inst
->src
[i
].d
);
4661 case BRW_REGISTER_TYPE_UW
:
4662 case BRW_REGISTER_TYPE_UD
:
4663 fprintf(file
, "%uu", inst
->src
[i
].ud
);
4665 case BRW_REGISTER_TYPE_VF
:
4666 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4667 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
4668 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
4669 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
4670 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
4673 fprintf(file
, "???");
4678 switch (inst
->src
[i
].nr
) {
4680 fprintf(file
, "null");
4682 case BRW_ARF_ADDRESS
:
4683 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
4685 case BRW_ARF_ACCUMULATOR
:
4686 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
4689 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4692 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4695 if (inst
->src
[i
].subnr
)
4696 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
4699 if (inst
->src
[i
].abs
)
4702 if (inst
->src
[i
].file
!= IMM
) {
4704 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
4705 unsigned hstride
= inst
->src
[i
].hstride
;
4706 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
4708 stride
= inst
->src
[i
].stride
;
4711 fprintf(file
, "<%u>", stride
);
4713 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4716 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4717 fprintf(file
, ", ");
4722 if (inst
->force_writemask_all
)
4723 fprintf(file
, "NoMask ");
4725 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4726 if (inst
->force_sechalf
)
4727 fprintf(file
, "2ndhalf ");
4729 fprintf(file
, "1sthalf ");
4732 fprintf(file
, "\n");
4736 * Possibly returns an instruction that set up @param reg.
4738 * Sometimes we want to take the result of some expression/variable
4739 * dereference tree and rewrite the instruction generating the result
4740 * of the tree. When processing the tree, we know that the
4741 * instructions generated are all writing temporaries that are dead
4742 * outside of this tree. So, if we have some instructions that write
4743 * a temporary, we're free to point that temp write somewhere else.
4745 * Note that this doesn't guarantee that the instruction generated
4746 * only reg -- it might be the size=4 destination of a texture instruction.
4749 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4754 end
->is_partial_write() ||
4756 !reg
.equals(end
->dst
)) {
4764 fs_visitor::setup_payload_gen6()
4767 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4768 unsigned barycentric_interp_modes
=
4769 (stage
== MESA_SHADER_FRAGMENT
) ?
4770 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4772 assert(devinfo
->gen
>= 6);
4774 /* R0-1: masks, pixel X/Y coordinates. */
4775 payload
.num_regs
= 2;
4776 /* R2: only for 32-pixel dispatch.*/
4778 /* R3-26: barycentric interpolation coordinates. These appear in the
4779 * same order that they appear in the brw_wm_barycentric_interp_mode
4780 * enum. Each set of coordinates occupies 2 registers if dispatch width
4781 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4782 * appear if they were enabled using the "Barycentric Interpolation
4783 * Mode" bits in WM_STATE.
4785 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4786 if (barycentric_interp_modes
& (1 << i
)) {
4787 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4788 payload
.num_regs
+= 2;
4789 if (dispatch_width
== 16) {
4790 payload
.num_regs
+= 2;
4795 /* R27: interpolated depth if uses source depth */
4797 payload
.source_depth_reg
= payload
.num_regs
;
4799 if (dispatch_width
== 16) {
4800 /* R28: interpolated depth if not SIMD8. */
4804 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4806 payload
.source_w_reg
= payload
.num_regs
;
4808 if (dispatch_width
== 16) {
4809 /* R30: interpolated W if not SIMD8. */
4814 if (stage
== MESA_SHADER_FRAGMENT
) {
4815 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4816 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4817 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4818 /* R31: MSAA position offsets. */
4819 if (prog_data
->uses_pos_offset
) {
4820 payload
.sample_pos_reg
= payload
.num_regs
;
4825 /* R32: MSAA input coverage mask */
4826 if (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4827 assert(devinfo
->gen
>= 7);
4828 payload
.sample_mask_in_reg
= payload
.num_regs
;
4830 if (dispatch_width
== 16) {
4831 /* R33: input coverage mask if not SIMD8. */
4836 /* R34-: bary for 32-pixel. */
4837 /* R58-59: interp W for 32-pixel. */
4839 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4840 source_depth_to_render_target
= true;
4845 fs_visitor::setup_vs_payload()
4847 /* R0: thread header, R1: urb handles */
4848 payload
.num_regs
= 2;
4852 * We are building the local ID push constant data using the simplest possible
4853 * method. We simply push the local IDs directly as they should appear in the
4854 * registers for the uvec3 gl_LocalInvocationID variable.
4856 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4857 * registers worth of push constant space.
4859 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
4860 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
4863 * FINISHME: There are a few easy optimizations to consider.
4865 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
4866 * no need for using push constant space for that dimension.
4868 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
4869 * easily use 16-bit words rather than 32-bit dwords in the push constant
4872 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
4873 * conveying the data, and thereby reduce push constant usage.
4877 fs_visitor::setup_gs_payload()
4879 assert(stage
== MESA_SHADER_GEOMETRY
);
4881 struct brw_gs_prog_data
*gs_prog_data
=
4882 (struct brw_gs_prog_data
*) prog_data
;
4883 struct brw_vue_prog_data
*vue_prog_data
=
4884 (struct brw_vue_prog_data
*) prog_data
;
4886 /* R0: thread header, R1: output URB handles */
4887 payload
.num_regs
= 2;
4889 if (gs_prog_data
->include_primitive_id
) {
4890 /* R2: Primitive ID 0..7 */
4894 /* Use a maximum of 32 registers for push-model inputs. */
4895 const unsigned max_push_components
= 32;
4897 /* If pushing our inputs would take too many registers, reduce the URB read
4898 * length (which is in HWords, or 8 registers), and resort to pulling.
4900 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
4901 * have to multiply by VerticesIn to obtain the total storage requirement.
4903 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
4904 max_push_components
) {
4905 gs_prog_data
->base
.include_vue_handles
= true;
4907 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
4908 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
4910 vue_prog_data
->urb_read_length
=
4911 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
4916 fs_visitor::setup_cs_payload()
4918 assert(devinfo
->gen
>= 7);
4919 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
4921 payload
.num_regs
= 1;
4923 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
4924 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
4925 payload
.local_invocation_id_reg
= payload
.num_regs
;
4926 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
4931 fs_visitor::calculate_register_pressure()
4933 invalidate_live_intervals();
4934 calculate_live_intervals();
4936 unsigned num_instructions
= 0;
4937 foreach_block(block
, cfg
)
4938 num_instructions
+= block
->instructions
.length();
4940 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
4942 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
4943 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
4944 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
4949 fs_visitor::optimize()
4951 /* Start by validating the shader we currently have. */
4954 /* bld is the common builder object pointing at the end of the program we
4955 * used to translate it into i965 IR. For the optimization and lowering
4956 * passes coming next, any code added after the end of the program without
4957 * having explicitly called fs_builder::at() clearly points at a mistake.
4958 * Ideally optimization passes wouldn't be part of the visitor so they
4959 * wouldn't have access to bld at all, but they do, so just in case some
4960 * pass forgets to ask for a location explicitly set it to NULL here to
4961 * make it trip. The dispatch width is initialized to a bogus value to
4962 * make sure that optimizations set the execution controls explicitly to
4963 * match the code they are manipulating instead of relying on the defaults.
4965 bld
= fs_builder(this, 64);
4967 assign_constant_locations();
4968 demote_pull_constants();
4972 split_virtual_grfs();
4975 #define OPT(pass, args...) ({ \
4977 bool this_progress = pass(args); \
4979 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
4980 char filename[64]; \
4981 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
4982 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
4984 backend_shader::dump_instructions(filename); \
4989 progress = progress || this_progress; \
4993 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
4995 snprintf(filename
, 64, "%s%d-%s-00-start",
4996 stage_abbrev
, dispatch_width
, nir
->info
.name
);
4998 backend_shader::dump_instructions(filename
);
5001 bool progress
= false;
5005 OPT(lower_simd_width
);
5006 OPT(lower_logical_sends
);
5013 OPT(remove_duplicate_mrf_writes
);
5017 OPT(opt_copy_propagate
);
5018 OPT(opt_predicated_break
, this);
5019 OPT(opt_cmod_propagation
);
5020 OPT(dead_code_eliminate
);
5021 OPT(opt_peephole_sel
);
5022 OPT(dead_control_flow_eliminate
, this);
5023 OPT(opt_register_renaming
);
5024 OPT(opt_redundant_discard_jumps
);
5025 OPT(opt_saturate_propagation
);
5026 OPT(opt_zero_samples
);
5027 OPT(register_coalesce
);
5028 OPT(compute_to_mrf
);
5029 OPT(eliminate_find_live_channel
);
5031 OPT(compact_virtual_grfs
);
5036 OPT(opt_sampler_eot
);
5038 if (OPT(lower_load_payload
)) {
5039 split_virtual_grfs();
5040 OPT(register_coalesce
);
5041 OPT(compute_to_mrf
);
5042 OPT(dead_code_eliminate
);
5045 OPT(opt_combine_constants
);
5046 OPT(lower_integer_multiplication
);
5048 lower_uniform_pull_constant_loads();
5054 * Three source instruction must have a GRF/MRF destination register.
5055 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5058 fs_visitor::fixup_3src_null_dest()
5060 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5061 if (inst
->is_3src() && inst
->dst
.is_null()) {
5062 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5069 fs_visitor::allocate_registers()
5071 bool allocated_without_spills
;
5073 static const enum instruction_scheduler_mode pre_modes
[] = {
5075 SCHEDULE_PRE_NON_LIFO
,
5079 /* Try each scheduling heuristic to see if it can successfully register
5080 * allocate without spilling. They should be ordered by decreasing
5081 * performance but increasing likelihood of allocating.
5083 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5084 schedule_instructions(pre_modes
[i
]);
5087 assign_regs_trivial();
5088 allocated_without_spills
= true;
5090 allocated_without_spills
= assign_regs(false);
5092 if (allocated_without_spills
)
5096 if (!allocated_without_spills
) {
5097 /* We assume that any spilling is worse than just dropping back to
5098 * SIMD8. There's probably actually some intermediate point where
5099 * SIMD16 with a couple of spills is still better.
5101 if (dispatch_width
== 16) {
5102 fail("Failure to register allocate. Reduce number of "
5103 "live scalar values to avoid this.");
5105 compiler
->shader_perf_log(log_data
,
5106 "%s shader triggered register spilling. "
5107 "Try reducing the number of live scalar "
5108 "values to improve performance.\n",
5112 /* Since we're out of heuristics, just go spill registers until we
5113 * get an allocation.
5115 while (!assign_regs(true)) {
5121 /* This must come after all optimization and register allocation, since
5122 * it inserts dead code that happens to have side effects, and it does
5123 * so based on the actual physical registers in use.
5125 insert_gen4_send_dependency_workarounds();
5130 schedule_instructions(SCHEDULE_POST
);
5132 if (last_scratch
> 0)
5133 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5137 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5139 assert(stage
== MESA_SHADER_VERTEX
);
5143 if (shader_time_index
>= 0)
5144 emit_shader_time_begin();
5151 compute_clip_distance(clip_planes
);
5155 if (shader_time_index
>= 0)
5156 emit_shader_time_end();
5162 assign_curb_setup();
5163 assign_vs_urb_setup();
5165 fixup_3src_null_dest();
5166 allocate_registers();
5172 fs_visitor::run_gs()
5174 assert(stage
== MESA_SHADER_GEOMETRY
);
5178 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
5180 if (gs_compile
->control_data_header_size_bits
> 0) {
5181 /* Create a VGRF to store accumulated control data bits. */
5182 this->control_data_bits
= vgrf(glsl_type::uint_type
);
5184 /* If we're outputting more than 32 control data bits, then EmitVertex()
5185 * will set control_data_bits to 0 after emitting the first vertex.
5186 * Otherwise, we need to initialize it to 0 here.
5188 if (gs_compile
->control_data_header_size_bits
<= 32) {
5189 const fs_builder abld
= bld
.annotate("initialize control data bits");
5190 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
5194 if (shader_time_index
>= 0)
5195 emit_shader_time_begin();
5199 emit_gs_thread_end();
5201 if (shader_time_index
>= 0)
5202 emit_shader_time_end();
5211 assign_curb_setup();
5212 assign_gs_urb_setup();
5214 fixup_3src_null_dest();
5215 allocate_registers();
5221 fs_visitor::run_fs(bool do_rep_send
)
5223 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5224 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5226 assert(stage
== MESA_SHADER_FRAGMENT
);
5228 if (devinfo
->gen
>= 6)
5229 setup_payload_gen6();
5231 setup_payload_gen4();
5235 } else if (do_rep_send
) {
5236 assert(dispatch_width
== 16);
5237 emit_repclear_shader();
5239 if (shader_time_index
>= 0)
5240 emit_shader_time_begin();
5242 calculate_urb_setup();
5243 if (nir
->info
.inputs_read
> 0) {
5244 if (devinfo
->gen
< 6)
5245 emit_interpolation_setup_gen4();
5247 emit_interpolation_setup_gen6();
5250 /* We handle discards by keeping track of the still-live pixels in f0.1.
5251 * Initialize it with the dispatched pixels.
5253 if (wm_prog_data
->uses_kill
) {
5254 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5255 discard_init
->flag_subreg
= 1;
5258 /* Generate FS IR for main(). (the visitor only descends into
5259 * functions called "main").
5266 if (wm_prog_data
->uses_kill
)
5267 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5269 if (wm_key
->alpha_test_func
)
5274 if (shader_time_index
>= 0)
5275 emit_shader_time_end();
5281 assign_curb_setup();
5284 fixup_3src_null_dest();
5285 allocate_registers();
5291 if (dispatch_width
== 8)
5292 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5294 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5300 fs_visitor::run_cs()
5302 assert(stage
== MESA_SHADER_COMPUTE
);
5306 if (shader_time_index
>= 0)
5307 emit_shader_time_begin();
5314 emit_cs_terminate();
5316 if (shader_time_index
>= 0)
5317 emit_shader_time_end();
5323 assign_curb_setup();
5325 fixup_3src_null_dest();
5326 allocate_registers();
5335 * Return a bitfield where bit n is set if barycentric interpolation mode n
5336 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5339 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5340 bool shade_model_flat
,
5341 bool persample_shading
,
5342 const nir_shader
*shader
)
5344 unsigned barycentric_interp_modes
= 0;
5346 nir_foreach_variable(var
, &shader
->inputs
) {
5347 enum glsl_interp_qualifier interp_qualifier
=
5348 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5349 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5350 bool is_sample
= var
->data
.sample
|| persample_shading
;
5351 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5352 (var
->data
.location
== VARYING_SLOT_COL1
);
5354 /* Ignore WPOS and FACE, because they don't require interpolation. */
5355 if (var
->data
.location
== VARYING_SLOT_POS
||
5356 var
->data
.location
== VARYING_SLOT_FACE
)
5359 /* Determine the set (or sets) of barycentric coordinates needed to
5360 * interpolate this variable. Note that when
5361 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5362 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5363 * for lit pixels, so we need both sets of barycentric coordinates.
5365 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5367 barycentric_interp_modes
|=
5368 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5369 } else if (is_sample
) {
5370 barycentric_interp_modes
|=
5371 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5373 if ((!is_centroid
&& !is_sample
) ||
5374 devinfo
->needs_unlit_centroid_workaround
) {
5375 barycentric_interp_modes
|=
5376 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5378 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5379 (!(shade_model_flat
&& is_gl_Color
) &&
5380 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5382 barycentric_interp_modes
|=
5383 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5384 } else if (is_sample
) {
5385 barycentric_interp_modes
|=
5386 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5388 if ((!is_centroid
&& !is_sample
) ||
5389 devinfo
->needs_unlit_centroid_workaround
) {
5390 barycentric_interp_modes
|=
5391 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5396 return barycentric_interp_modes
;
5400 computed_depth_mode(const nir_shader
*shader
)
5402 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5403 switch (shader
->info
.fs
.depth_layout
) {
5404 case FRAG_DEPTH_LAYOUT_NONE
:
5405 case FRAG_DEPTH_LAYOUT_ANY
:
5406 return BRW_PSCDEPTH_ON
;
5407 case FRAG_DEPTH_LAYOUT_GREATER
:
5408 return BRW_PSCDEPTH_ON_GE
;
5409 case FRAG_DEPTH_LAYOUT_LESS
:
5410 return BRW_PSCDEPTH_ON_LE
;
5411 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5412 return BRW_PSCDEPTH_OFF
;
5415 return BRW_PSCDEPTH_OFF
;
5419 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5421 const struct brw_wm_prog_key
*key
,
5422 struct brw_wm_prog_data
*prog_data
,
5423 const nir_shader
*src_shader
,
5424 struct gl_program
*prog
,
5425 int shader_time_index8
, int shader_time_index16
,
5427 unsigned *final_assembly_size
,
5430 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5431 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5433 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5435 /* key->alpha_test_func means simulating alpha testing via discards,
5436 * so the shader definitely kills pixels.
5438 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5439 prog_data
->uses_omask
=
5440 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5441 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5442 prog_data
->computed_stencil
=
5443 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5445 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5447 prog_data
->barycentric_interp_modes
=
5448 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5450 key
->persample_shading
,
5453 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5454 &prog_data
->base
, prog
, shader
, 8,
5455 shader_time_index8
);
5456 if (!v
.run_fs(false /* do_rep_send */)) {
5458 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5463 cfg_t
*simd16_cfg
= NULL
;
5464 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5465 &prog_data
->base
, prog
, shader
, 16,
5466 shader_time_index16
);
5467 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5468 if (!v
.simd16_unsupported
) {
5469 /* Try a SIMD16 compile */
5470 v2
.import_uniforms(&v
);
5471 if (!v2
.run_fs(use_rep_send
)) {
5472 compiler
->shader_perf_log(log_data
,
5473 "SIMD16 shader failed to compile: %s",
5476 simd16_cfg
= v2
.cfg
;
5482 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5483 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5485 prog_data
->no_8
= true;
5488 prog_data
->no_8
= false;
5491 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5492 v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
5494 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5495 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5496 shader
->info
.label
? shader
->info
.label
:
5498 shader
->info
.name
));
5502 g
.generate_code(simd8_cfg
, 8);
5504 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5506 return g
.get_assembly(final_assembly_size
);
5510 fs_visitor::emit_cs_local_invocation_id_setup()
5512 assert(stage
== MESA_SHADER_COMPUTE
);
5514 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5516 struct brw_reg src
=
5517 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5518 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5520 src
.nr
+= dispatch_width
/ 8;
5521 bld
.MOV(offset(*reg
, bld
, 1), src
);
5522 src
.nr
+= dispatch_width
/ 8;
5523 bld
.MOV(offset(*reg
, bld
, 2), src
);
5529 fs_visitor::emit_cs_work_group_id_setup()
5531 assert(stage
== MESA_SHADER_COMPUTE
);
5533 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5535 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5536 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5537 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5539 bld
.MOV(*reg
, r0_1
);
5540 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5541 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5547 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5549 const struct brw_cs_prog_key
*key
,
5550 struct brw_cs_prog_data
*prog_data
,
5551 const nir_shader
*src_shader
,
5552 int shader_time_index
,
5553 unsigned *final_assembly_size
,
5556 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5557 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5559 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5561 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5562 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5563 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5564 unsigned local_workgroup_size
=
5565 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5566 shader
->info
.cs
.local_size
[2];
5568 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5571 const char *fail_msg
= NULL
;
5573 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5575 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5576 NULL
, /* Never used in core profile */
5577 shader
, 8, shader_time_index
);
5579 fail_msg
= v8
.fail_msg
;
5580 } else if (local_workgroup_size
<= 8 * max_cs_threads
) {
5582 prog_data
->simd_size
= 8;
5585 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5586 NULL
, /* Never used in core profile */
5587 shader
, 16, shader_time_index
);
5588 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5589 !fail_msg
&& !v8
.simd16_unsupported
&&
5590 local_workgroup_size
<= 16 * max_cs_threads
) {
5591 /* Try a SIMD16 compile */
5592 v16
.import_uniforms(&v8
);
5593 if (!v16
.run_cs()) {
5594 compiler
->shader_perf_log(log_data
,
5595 "SIMD16 shader failed to compile: %s",
5599 "Couldn't generate SIMD16 program and not "
5600 "enough threads for SIMD8";
5604 prog_data
->simd_size
= 16;
5608 if (unlikely(cfg
== NULL
)) {
5611 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5616 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5617 v8
.promoted_constants
, v8
.runtime_check_aads_emit
, "CS");
5618 if (INTEL_DEBUG
& DEBUG_CS
) {
5619 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5620 shader
->info
.label
? shader
->info
.label
:
5623 g
.enable_debug(name
);
5626 g
.generate_code(cfg
, prog_data
->simd_size
);
5628 return g
.get_assembly(final_assembly_size
);